bq2461x Stand-Alone Synchronous Switched-Mode Li-Ion or Li-Polymer Battery Charger

bq2461x Stand-Alone Synchronous Switched-Mode Li-Ion or Li-Polymer Battery Charger
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bq24610, bq24617
SLUS892C – DECEMBER 2009 – REVISED APRIL 2015
bq2461x Stand-Alone Synchronous Switched-Mode Li-Ion or Li-Polymer Battery Charger
With System Power Selector and Low Iq
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
600-kHz NMOS-NMOS Synchronous Buck
Converter
Stand-Alone Charger Support for Li-Ion or LiPolymer
5-V to 28-V VCC Input Operating Range and
Supports 1- to 6-Battery Cells (bq24610)
5-V to 24-V VCC Input Operating Range and
Supports 1- to 5-Battery Cells (bq24617)
Up to 10-A Charge Current and Adapter Current
High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
Integration
– Automatic System Power Selection From
Adapter or Battery
– Internal Loop Compensation and Soft Start
– Dynamic Power Management
Safety Protection
– Input Overvoltage Protection
– Battery Thermistor Sense Hot and Cold
Charge Suspend
– Battery Detection
– Reverse Protection Input FET
– Programmable Safety Timer
– Charge Overcurrent Protection
– Battery Short Protection
– Battery Overvoltage Protection
– Thermal Shutdown
Status Outputs
– Adapter Present
•
– Charger Operation Status
Charge Enable Pin
6-V Gate Drive for Synchronous Buck Converter
30-ns Driver Dead-Time and 99.5% Maximum
Effective Duty Cycle
Energy Star Low Quiescent Current Iq
– < 15-µA Off-State Battery Discharge Current
– < 1.5-mA Off-State Input Quiescent Current
2 Applications
•
•
•
•
•
Netbooks, Mobile Internet Devices, and UltraMobile PCs
Personal Digital Assistants (PDAs)
Handheld Terminals
Industrial and Medical Equipment
Portable Equipment
3 Description
The bq2461x is a highly integrated Li-ion or Lipolymer switched-mode battery charge controller.
The device offers a constant-frequency synchronous
switching PWM controller with high-accuracy charge
current
and
voltage
regulation,
charge
preconditioning,
termination,
adapter
current
regulation, and charge status monitoring.
The bq2461x charges the battery in three phases:
preconditioning, constant current, and constant
voltage.
Device Information(1)
PART NUMBER
bq24610
bq24617
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
ADAPTER
SYSTEM
ACP
ACDRV
ACN
BATDRV
HIDRV
CE
VREF
VREF
ADAPTER
STAT1
STAT2
PG
TS
PH
bq2461x
ISET1
ISET2
ACSET
LODRV
Battery
pack
SRP
SRN
VFB
TTC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24610, bq24617
SLUS892C – DECEMBER 2009 – REVISED APRIL 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
9
1
1
1
2
3
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 25
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ............................................... 26
11 Power Supply Recommendations ..................... 32
12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 Layout Example .................................................... 33
13 Device and Documentation Support ................. 34
13.1
13.2
13.3
13.4
13.5
Device Support......................................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
14 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2013) to Revision C
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision A (October 2011) to Revision B
•
Page
Page
Changed Figure 14, pin VLTFH to: VLTF_HYS .......................................................................................................................... 20
Changes from Original (December 2009) to Revision A
Page
•
Corrected equation for calculating RT2 ................................................................................................................................ 21
•
Corrected equation for calculating ICOUT .............................................................................................................................. 28
2
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SLUS892C – DECEMBER 2009 – REVISED APRIL 2015
5 Description (continued)
Charge is terminated when the current reaches a minimum user-selectable level. A programmable charge timer
provides a safety backup. The bq2461x automatically restarts the charge cycle if the battery voltage falls below
an internal threshold, and enters a low quiescent current sleep mode when the input voltage falls below the
battery voltage.
6 Device Comparison Table
bq24600
bq24610
bq24616
bq24617
bq24618
bq24650
Li-Ion/Li-Polymer
Li-Ion/Li-Polymer
Li-Ion/Li-Polymer
Li-Ion/Li-Polymer
Li-Ion/Li-Polymer
Li-Ion/Li-Polymer
1 to 6
1 to 6
1 to 6
1 to 5
1 to 6
1 to 6
2.1 to 26
2.1 to 26
2.1 to 26
2.1 to 22
2.1 to 26
2.1 to 26
5 to 28
5 to 28
5 to 28
5 to 24
4.7 to 28
5 to 28
Input overvoltage
(V)
32
32
32
26
32
32
Maximum battery
charging current
(A)
10
10
10
10
10
10
1200
600
600
600
600
600
JEITA charging
temperature profile
No
No
Yes
No
No
No
DPM
No
IIN DPM
IIN DPM
IIN DPM
IIN DPM
VIN DPM
Cell chemistry
Number of cells in
series (minimum to
maximum, 4.2
V/cell)
Charge voltage
(minimum to
maximum) (V)
Input voltage range
(minimum to
maximum) (V)
Switching
frequency (kHz)
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7 Pin Configuration and Functions
PH
LODRV
23
BTST
BATDRV
24
HIDRV
VCC
RGE Package
24-Pin VQFN
Top View
22
21
20
19
ACN
1
18 REGN
ACP
2
17 GND
16 ACSET
ACDRV 3
CE
4
15 ISET2
STAT1
5
14 SRP
TS
6
10
PG
STAT2
VREF
11
12
VFB
9
ISET1
8
TTC
13 SRN
7
Pin Functions
PIN
NAME
DESCRIPTION
NO.
ACDRV
3
AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel
power MOSFET and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is
asymmetrical, allowing a quick turnoff and slow turnon, in addition to the internal break-before-make logic with
respect to BATDRV. If needed, an optional capacitor from gate to source of the ACFET is used to slow down the ON
and OFF times.
ACN
1
Adapter current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to GND for commonmode filtering.
ACP
2
Adapter current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to GND for common-mode filtering.
ACSET
16
Adapter current-set input. The voltage of the ACSET pin programs the input current regulation set point during
Dynamic Power Management (DPM).
BATDRV
23
Battery-to-system MOSFET driver output. Gate drive for the battery-to-system load BAT PMOS power FET to isolate
the system from the battery to prevent current flow from the system to the battery, while allowing a low-impedance
path from battery to system. Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel
MOSFET. Connect the source of the FET to the system-load voltage node. Connect the drain of the FET to the
battery pack positive terminal. The internal gate drive is asymmetrical to allow a quick turnoff and slow turnon, in
addition to the internal break-before-make logic with respect to ACDRV. If needed, an optional capacitor from gate to
source of the BATFET is used to slow down the ON and OFF times.
BTST
22
PWM high-side driver positive supply. Connect a 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap
Schottky diode from REGN to BTST.
CE
4
Charge enable active HIGH logic input. HI enables charge. LO disables charge. It has an internal 1-MΩ pulldown
resistor.
GND
17
Low-current sensitive analog and digital ground. On PCB layout, connect with the thermal pad underneath the IC.
HIDRV
21
PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
ISET1
11
Fast-charge current-set input. The voltage of the ISET1 pin programs the fast-charge current regulation set point.
ISET2
15
Precharge and termination current set input. The voltage of the ISET2 pin programs the precharge current regulation
set point and termination current trigger point.
LODRV
19
PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PG
8
Open-drain power-good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP
mode). Active HIGH when IC has an invalid VCC. PG can be used to drive an LED or communicate with a host
processor.
PH
20
PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power
MOSFET drain, high-side power MOSFET source, and output inductor).
REGN
18
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the GND pin, close
to the IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode
from REGN to BTST.
4
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Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
SRN
13
Charge current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for commonmode filtering.
SRP
14
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to GND for common-mode filtering.
STAT1
5
Open-drain charge status pin to indicate various charger operation (see Table 2).
STAT2
9
Open-drain charge status pin to indicate various charger operations (see Table 2).
Thermal
pad
—
Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal pad plane
star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to
dissipate the heat.
TS
6
Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot
and cold temperature window with a resistor divider from VREF to TS to GND (see Figure 15).
TTC
7
SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is
LOW, the timer and termination are disabled. When this input is HIGH, the timer is disabled but termination is
allowed.
VCC
24
IC power positive supply. Connect through a 10-Ω resistor to the common-source (diode-OR) point: source of highside P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor
from VCC to the GND pin close to the IC.
VFB
12
Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery
terminals to this node to adjust the output battery regulation voltage.
VREF
10
3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage
could be used for programming of voltage and current regulation and for programming the TS threshold.
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
–0.3
33
PH
–2
36
VFB
–0.3
16
REGN, LODRV, ACSET, TS, TTC
–0.3
7
BTST, HIDRV with respect to GND
–0.3
39
VREF, ISET1, ISET2
–0.3
3.6
–0.5
0.5
V
Junction temperature
–40
155
°C
Tstg Storage temperature
–55
155
°C
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2,
PG
Voltage
Maximum difference
voltage
TJ
(1)
(2)
(3)
ACP–ACN, SRP–SRN
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
Must have a series resistor between battery pack to VFB if battery-pack voltage is expected to be greater than 16 V. Usually the
resistor-divider top resistor takes care of this.
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8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
–0.3
28
V
bq24617: VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1,
STAT2, PG
–0.3
24
V
–2
30
V
PH
Voltage
VFB
–0.3
14
V
REGN, LODRV, ACSET, TS, TTC
–0.3
6.5
V
BTST, HIDRV with respect to GND
–0.3
34
V
ISET1, ISET2
–0.3
3.3
V
3.3
V
–0.2
0.2
V
0
125
°C
VREF
Maximum difference
voltage
TJ
MAX UNIT
bq24610: VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1,
STAT2, PG
ACP–ACN, SRP–SRN
Junction temperature
8.4 Thermal Information
bq2461x
THERMAL METRIC (1)
RGE [VQFN]
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
43
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
54.3
°C/W
20
ψJT
°C/W
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
19
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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8.5 Electrical Characteristics
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating
range(610)
5
28
VCC input voltage operating
range(617)
5
24
V
QUIESCENT CURRENTS
IBAT
Total battery discharge current
(sum of currents into VCC, BTST,
PH, ACP, ACN, SRP, SRN, VFB),
VFB ≤ 2.1 V
Battery discharge current (sum of
currents into BTST, PH, SRP,
SRN, VFB), VFB ≤ 2.1 V
VVCC < VSRN, VVCC > VUVLO (SLEEP)
15
μA
VVCC > VSRN, VVCC > VUVLO CE = LOW
5
VVCC > VSRN, VVCC > VVCCLOW CE = HIGH,
charge done
5
VVCC > VSRN, VVCC > VUVLO CE = LOW (IC
quiescent current)
IAC
1
1.5
Adapter supply current (current into VVCC > VSRN, VVCC >VVCCLOW , CE = HIGH,
VCC, ACP, ACN pin)
charge done
2
5
VVCC > VSRN, VVCC >VVCCLOW , CE = HIGH,
charging, Qg_total = 20 nC
25
mA
CHARGE VOLTAGE REGULATION
VFB
Feedback regulation voltage
2.1
Charge voltage regulation accuracy
IVFB
Leakage current into VFB pin
V
TJ = 0°C to 85°C
–0.5%
0.5%
TJ = –40°C to 125°C
–0.7%
0.7%
VFB = 2.1 V
100
nA
2
V
CURRENT REGULATION – FAST CHARGE
VISET1
ISET1 voltage range
VIREG_CHG
SRP-SRN current-sense voltage
range
VIREG_CHG = VSRP – VSRN
KISET1
Charge current set factor (amps of
charge current per volt on ISET1
pin)
RSENSE = 10 mΩ
VIREG_CHG = 40 mV
Charge current regulation accuracy
IISET1
Leakage current into ISET1 pin
100
5
–3%
mV
A/V
3%
VIREG_CHG = 20 mV
–4%
4%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV (VSRN > 3.1 V)
–40%
40%
VISET1 = 2 V
100
nA
2
V
CURRENT REGULATION – PRECHARGE
VISET2
ISET2 voltage range
KISET2
Precharge current set factor (amps
of precharge current per volt on
ISET2 pin)
Precharge current regulation
accuracy
IISET2
Leakage current into ISET2 pin
RSENSE = 10 mΩ
1
A/V
VIREG_PRECH = 20 mV
–4%
4%
VIREG_PRECH = 5 mV
–25%
25%
VIREG_PRECH = 1.5 mV (VSRN < 3.1 V)
–55%
55%
VISET2 = 2 V
100
nA
CHARGE TERMINATION
KTERM
Termination current set factor
(amps of termination current per
volt on ISET2 pin)
RSENSE = 10 mΩ
1
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Termination current accuracy
MIN
TYP
MAX
VITERM = 20 mV
–4%
4%
VITERM = 5 mV
–25%
25%
VITERM = 1.5 mV
–45%
45%
Deglitch time for termination (both
edge)
100
tQUAL
Termination qualification time
VBAT > VRECH and ICHG<ITERM
IQUAL
Termination qualification current
Discharge current once termination is detected
UNIT
ms
250
ms
2
mA
INPUT CURRENT REGULATION
VACSET
ACSET voltage range
VIREG_DPM
ACP-ACN current-sense voltage
range
VIREG_DPM = VACP – VACN
KACSET
Input current set factor (amps of
input current per volt on ACSET
pin)
RSENSE = 10 mΩ
IACSET
Input current regulation accuracy
leakage current in to ACSET pin
IISET1
2
Leakage current in to ACSET pin
100
5
V
mV
A/V
VIREG_DPM = 40 mV
–3%
VIREG_DPM = 20 mV
–4%
3%
4%
VIREG_DPM = 5 mV
–25%
25%
VACSET = 2 V
100
nA
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO
AC undervoltage rising threshold
VUVLO_HYS
AC undervoltage hysteresis, falling
Measure on VCC
3.65
3.85
4
350
V
mV
VCC LOWV COMPARATOR
Falling threshold, disable charge
Measure on VCC
4.1
Rising threshold, resume charge
V
4.35
4.5
V
100
150
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
VSLEEP_HYS
SLEEP falling threshold
VVCC – VSRN to enter SLEEP
40
SLEEP hysteresis
500
mV
SLEEP rising delay
VCC falling below SRN, delay to turn off ACFET
1
μs
SLEEP falling delay
VCC rising above SRN, delay to turn on ACFET
30
μs
SLEEP rising shutdown deglitch
VCC falling below SRN, delay to enter SLEEP
mode
100
ms
SLEEP falling power-up deglitch
VCC rising above SRN, delay to exit SLEEP
mode
30
ms
ACN / SRN COMPARATOR
VACN-SRN_FALL
ACN to SRN falling threshold
VACN-SRN_HYS
ACN to SRN rising hysteresis
VACN – VSRN to turn on BATFET
100
200
310
mV
100
mV
ACN to SRN rising deglitch
VACN – VSRN > VACN-SRN_RISE
2
ms
ACN to SRN falling deglitch
VACN – VSRN < VACN-SRN_FALL
50
μs
BAT LOWV COMPARATOR
VLOWV
Precharge to fast-charge transition
(LOWV threshold)
VLOWV_HYS
LOWV hysteresis
Measured on VFB pin, rising
1.534
1.55
1.566
V
100
mV
LOWV rising deglitch
VFB falling below VLOWV
25
ms
LOWV falling deglitch
VFB rising above VLOWV + VLOWV_HYS
25
ms
RECHARGE COMPARATOR
VRECHG
8
Recharge threshold (with-respectto VREG)
Measured on VFB pin, falling
Recharge rising deglitch
VFB decreasing below VRECHG
10
ms
Recharge falling deglitch
VFB decreasing above VRECHG
10
ms
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50
65
mV
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32.96
V
BAT OVERVOLTAGE COMPARATOR
VOV_RISE
Overvoltage rising threshold
As percentage of VFB
104%
VOV_FALL
Overvoltage falling threshold
As percentage of VFB
102%
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC overvoltage rising threshold on
VCC (bq24610)
VACOV_HYS
AC overvoltage falling hysteresis
(bq24610)
VACOV
AC overvoltage rising threshold on
VCC (bq24617)
VACOV_HYS
AC overvoltage falling
hysteresis(bq24617)
31.04
32
1
25.22
26
V
26.78
V
820
mV
1
ms
AC overvoltage deglitch (both
edge)
Delay to changing the STAT pins
AC overvoltage rising deglitch
Delay to disable charge
1
ms
AC overvoltage falling deglitch
Delay to resume charge
20
ms
Temperature increasing
145
°C
15
°C
Thermal shutdown rising deglitch
Temperature increasing
100
μs
Thermal shutdown falling deglitch
Temperature decreasing
10
ms
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising
temperature
TSHUT_HYS
Thermal shutdown hysteresis
THERMISTOR COMPARATOR
VLTF
Cold temperature rising threshold
As Percentage to VVREF
72.5% 73.5% 74.5%
VLTF_HYS
Rising hysteresis
As Percentage to VVREF
0.2%
VHTF
Hot temperature rising threshold
As Percentage to VVREF
36.2%
VTCO
Cut-off temperature rising threshold As Percentage to VVREF
0.4%
0.6%
37% 37.8%
33.7% 34.4% 35.1%
Deglitch time for temperature outof-range detection
VTS > VLTF, or VTS < VTCO, or VTS < VHTF
Deglitch time for temperature invalid-range detection
VTS < VLTF – VLTF_HYS or VTS >VTCO, or VTS >
VHTF
400
ms
20
ms
45.5
mV
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
Current rising, in nonsynchronous mode,
mesure on V(SRP-SRN), VSRP < 2 V
Charge overcurrent falling
threshold
Current rising, as percentage of V(IREG_CHG), in
synchronous mode, VSRP > 2.2 V
160%
Charge overcurrent threshold floor
Minimum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
50
mV
Charge overcurrent threshold
ceiling
Maximum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
180
mV
VOC
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
Charge undercurrent falling
threshold
Switch from SYNCH to NON-SYNCH, VSRP >
2.2 V
1
5
9
mV
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT
BAT short falling threshold, forced
nonsynchronous mode
VBATSHT_HYS
BAT short rising hysteresis
VBATSHT_DEG
Deglitch on both edge
VSRP falling
2
200
mV
1
μs
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW CHARGE CURRENT COMPARATOR
VLC
Low charge current (average)
falling threshold to force into
nonsynchronous mode
VLC_HYS
Low charge current rising
hysteresis
VLC_DEG
Deglitch on both edge
Measure on V(SRP-SRN)
1.25
mV
1.25
mV
1
μs
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO, (0- to 35-mA load)
IVREF_LIM
VREF current limit
VVREF = 0 V, VVCC > VUVLO
3.267
35
3.3
3.333
V
mA
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VVCC > 10 V, CE = HIGH, (0- to 40-mA load)
5.7
IREGN_LIM
REGN current limit
VREGN = 0 V, VVCC > VUVLO, CE = HIGH
40
6
6.3
V
mA
TTC INPUT AND SAFETY TIMER
TPRECHG
Precharge safety timer range (1)
Precharge time before fault occurs
TCHARGE
Fast charge safety timer range,
with +/– 10% accuracy (1)
Tchg = CTTC × KTTC
Fast charge timer accuracy (1)
0.01 μF ≤ CTTC ≤ 0.11 μF
KTTC
1440
1800
1
–10%
Timer multiplier
2160
s
10
h
10%
5.6
VTTC below this threshold disables the safety
timer and termination
TTC low threshold
min/nF
0.4
TTC oscillator high threshold
1.5
TTC oscillator low threshold
V
1
TTC source/sink current
45
50
V
V
55
μA
BATTERY SWITCH (BATFET) DRIVER
RDS_BAT_OFF
BATFET turnoff resistance
VACN > 5 V
150
Ω
RDS_BAT_ON
BATFET turnon resistance
VACN > 5 V
20
kΩ
VBATDRV_REG
BATFET drive voltage
VBATDRV_REG = VACN – VBATDRV when VACN > 5
V and BATFET is on
7
V
4.2
AC SWITCH (ACFET) DRIVER
RDS_AC_OFF
ACFET turnoff resistance
VVCC > 5 V
30
Ω
RDS_AC_ON
ACFET turnon resistance
VVCC > 5 V
20
kΩ
ACFET drive voltage
VACDRV_REG = VVCC – VACDRV when VVCC > 5 V
and ACFET is on
7
V
VACDRV_REG
4.2
AC / BAT MOSFET DRIVERS TIMING
Dead time when switching between AC and
BAT
Driver dead time
μs
10
BATTERY DETECTION
tWAKE
Wake time
Max time charge is enabled
IWAKE
Wake current
RSENSE = 10 mΩ
tDISCHARGE
Discharge time
Maximum time discharge current is applied
IDISCHARGE
IFAULT
VWAKE
Wake threshold (with-respect-to
VREG)
VDISCH
Discharge threshold
(1)
10
500
50
125
ms
200
mA
1
s
Discharge current
8
mA
Fault current after a timeout fault
2
mA
Voltage on VFB to detect battery absent during
wake
50
mV
Voltage on VFB to detect battery absent during
discharge
1.55
V
Verified by design.
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM HIGH-SIDE DRIVER (HIDRV)
RDS_HI_ON
High-side driver (HSD) turnon
resistance
VBTST – VPH = 5.5 V
3.3
6
Ω
RDS_HI_OFF
High-side driver turnoff resistance
VBTST – VPH = 5.5 V
1
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator
threshold voltage
VBTST – VPH when low side refresh pulse is
requested
4
4.2
V
PWM LOW-SIDE DRIVER (LODRV)
RDS_LO_ON
Low-side driver (LSD) turnon
resistance
RDS_LO_OFF
Low-side driver turnoff resistance
4.1
7
Ω
1
1.4
Ω
PWM DRIVERS TIMING
Dead time when switching between LSD and
HSD, no load at LSD and HSD
Driver dead time
30
ns
PWM OSCILLATOR
VRAMP_HEIGHT
PWM ramp height
As percentage of VCC
7%
PWM switching frequency (1)
510
600
690
kHz
INTERNAL SOFT START (8 steps to regulation current ICHG)
Soft-start steps
Soft-start step time
8
step
1.6
ms
1.5
s
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power
up
Delay from CE = 1 to charger is allowed to turn
on
LOGIC IO PIN CHARACTERISTICS (CE, STAT1, STAT2, PG)
VIN_LO
CE input low threshold voltage
VIN_HI
CE input high threshold voltage
0.8
V
6
μA
2.1
VBIAS_CE
CE input bias current
V = 3.3 V (CE has internal 1-MΩ pulldown
resistor)
VOUT_LO
STAT1, STAT2, PG output-low
saturation voltage
Sink Current = 5 mA
0.5
V
IOUT_HI
Leakage current
V = 32 V
1.2
µA
8.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE
REF REGN and PG Power Up (CE = 1)
Figure 1
Charge Enable
Figure 2
Current Soft Start (CE = 1)
Figure 3
Charge Disable
Figure 4
Continuous Conduction Mode Switching Waveforms
Figure 5
Cycle-by-Cycle Synchronous to Nonsynchronous
Figure 6
100% Duty and Refresh Pulse
Figure 7
Transient System Load (DPM)
Figure 8
Battery Insertion
Figure 9
Battery-to-Ground Short Protection
Figure 10
Battery-to-Ground Short Transition
Figure 11
Efficiency vs Output Current
Figure 12
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10 V/div
10 V/div
SLUS892C – DECEMBER 2009 – REVISED APRIL 2015
PH
2 A/div
IBAT
REGN
5 V/div
CE
5 V/div
2 V/div
VREF
5 V/div
/PG
2 V/div
VCC
LODRV
t − Time = 200 ms/div
t − Time = 4 ms/div
Figure 2. Charge Enable
10 V/div
10 V/div
Figure 1. REF REGN and PG Power Up (CE = 1)
CE
5 V/div
2 A/div
IBAT
PH
5 V/div 2 A/div
5 V/div
LODRV
5 V/div
PH
LODRV
IL
CE
t − Time = 2 μs/div
t − Time = 4 ms/div
Figure 4. Charge Disable
5 V/div
PH
HIDRV
LODRV
1 A/div 5 V/div
PH
2 A/div
5 V/div 20 V/div 20 V/div
Figure 3. Current Soft Start (CE = 1)
IL
LODRV
IL
t − Time = 100 ns/div
t − Time = 100 ns/div
Figure 5. Continuous Conduction Mode Switching
Waveforms
12
Figure 6. Cycle-by-Cycle Synchronous to Nonsynchronous
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10 V/div
2 A/div
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2 A/div
IIN
ISYS
LODRV
2 A/div
0.5 A/div 5 V/div
PH
IL
IBAT
t − Time = 200 μs/div
t − Time = 400 ns/div
Figure 7. 100% Duty and Refresh Pulse
10 V/div
10 V/div
Figure 8. Transient System Load (DPM)
PH
2 A/div
LODRV
IL
IL
20 V/div
2 A/div
5 V/div
5 V/div
PH
VBAT
VBAT
t − Time = 200 ms/div
t − Time = 4 ms/div
Figure 9. Battery Insertion
Figure 10. Battery-to-GND Short Protection
10 V/div
98
96
94
Efficiency - %
92
LODRV
20 V/div
2 A/div
5 V/div
PH
90
20 Vin, 4 cell
88
12 Vin, 2 cell
86
IL
20 Vin, 3 cell
VBAT
84
12 Vin, 1 cell
82
t − Time = 10 μs/div
80
0
Figure 11. Battery-to-GND Short Transition
1
2
5
4
3
IBAT - Output Current - A
6
7
8
Figure 12. Efficiency vs Output Current
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9 Detailed Description
9.1 Overview
The bq2461x device is a stand-alone, integrated Li-ion or Li-polymer battery charger. The device employs a
switched-mode synchronous buck PWM controller with constant switching frequency. The device controls
external switches to prevent battery discharge back to the input, connect the adapter to the system, and connect
the battery to the system using 6-V gate drives for better system efficiency. The bq2461x features Dynamic
Power Management (DPM) which reduces battery charge current when the input power limit is reached to avoid
overloading the AC adapter when supplying current to the system and the battery charger simultaneously. A
highly accurate current-sense amplifier enables precise measurement of input current from the AC adapter to
monitor the overall system power. The input current limit can be configured through the ACSET pin of the device.
The bq2461x has a battery detect scheme that allows it to automatically detect the presence and absence of a
battery. When the battery is detected, charging begins in one of three phases (depending upon battery voltage):
precharge, constant current (fast-charge current regulation), and constant voltage (fast-charge voltage
regulation). The device will terminate charging when the termination current threshold has been reached and will
begin a recharge cycle when the battery voltage has dropped below the recharge threshold (VRECHG). Precharge,
constant current, and termination current can be configured through the ISET1 and ISET2 pins, allowing for
flexibility in battery charging profile. During charging, the integrated fault monitors of the device, such as battery
overvoltage protection, battery short detection (VBATSHT), thermal shutdown (internal TSHUT and TS pin), safety
timer expiration (TTC pin), and input voltage protection (VACOV), ensure battery safety.
The bq2461x has three status pins (STAT1, STAT2, and PG) to indicate the charging status and input voltage
(AC adapter) status. These pins can be used to drive LEDs or communicate with a host processor.
Regulation Voltage
VRECH
Regulation Current
Precharge
Current
Regulation
Phase
Fastcharge Current
Regulation Phase
Fastcharge Voltage
Regulation Phase
Termination
Charge
Current
Charge
Voltage
VLOWV
IPRECH
and
ITERM
Precharge
Time
Fastcharge Safety Time
Figure 13. Typical Charging Profile
14
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9.2 Functional Block Diagram
bq24610/17
VREF
VCC-6 V
ACN ACN-6 V ACN-6 V
LDO
INTERNAL
REFERENCE
VREF
3.3 V
LDO
VCC
-
SRN+100 mV
+
VCC
-
VUVLO
+
ACN
+
VCC
VCC
SLEEP
UVLO
VCC
VCC-6 V
LDO
SLEEP
SRN+200 mV
UVLO
ACN-SRN
-
ACDRV
SYSTEM
POWER
SELECTOR
LOGIC
VCC-6V
ACN
ACOV
CE
BATDRV
1M
ACN-6V
+
20X
-
V(ACP-ACN)
+
COMP
ERROR
AMPLIFIER
ACN
ACSET
+
1V
+
-
2.1 V
+
REGN
2 mA
LODRV
V(SRP-SRN)
160% X IBAT_REG
-
CHG_OCP
GND
TTC
Safety
Timer
IC Tj
+
145 degC
-
CHARGE
FAULT
STAT 1
STAT1
ISET1
IBAT_ REG
ISET2
+
LOWV
104% X VBAT_REG
-
-
BAT
+
ISET2
6 V LDO
REFRESH
4.2V
FAULT
+
ISET1
CE
+
+
-
PH
-
PH
VCC
PWM
CONTROL
LOGIC
BTST
20µA
8 mA
SYNCH
+
5 mV -
-
IBAT_ REG
SRN
CHARGE
OR
DISCHARGE
+
SRP-SRN
-
V(SRP-SRN)
HIDRV
BAT_OVP
20 µA
+
20X
-
LEVEL
SHIFTER
PWM
-
VFB
SRP
BTST
CE
+
ACP
TSHUT
STATE
MACHINE
LOGIC
BAT_OVP
STAT 2
STAT2
PG
PG
VFB
+
- 1.55V
TTC
-
0.4 V
+
VCC
+
DISABLE
TMR/TERM
BATTERY
DETECTION
LOGIC
ACOV
TTC
TTC
VREF
DISCHARGE
VACOV +-
LTF
+
VFB
-
TS
SUSPEND
RCHRG
HTF
+
+
-
2.05 V +-
RCHRG
V(SRP - SRN)
+
ISET2
-
TERM
TERM
TCO
+
-
TERMINATE CHARGE
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9.3 Feature Description
9.3.1 Battery Voltage Regulation
The bq2461x uses a high-accuracy voltage bandgap and regulator for the high charging voltage accuracy. The
charge voltage is programmed through a resistor divider from the battery to ground, with the midpoint tied to the
VFB pin. The voltage at the VFB pin is regulated to 2.1 V, giving the following equation for the regulation voltage:
é R2 ù
V
= 2.1 V ´ ê1+
ú,
BAT
ë R1 û
where
•
R2 is connected from VFB to the battery and R1 is connected from VFB to GND.
(1)
9.3.2 Battery Current Regulation
The ISET1 input sets the maximum fast-charging current. Battery charge current is sensed by resistor RSR
connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus,
for a 10-mΩ sense resistor, the maximum charging current is 10 A. The equation for charge current is:
VISET1
ICHARGE =
20 ´ RSR
(2)
VISET1, the input voltage range of ISET1, is from 0 V to 2 V. The SRP and SRN pins are used to sense voltage
across RSR with default value of 10 mΩ. However, resistors of other values can also be used. A larger sense
resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction
loss.
9.3.3 Input Adapter Current Regulation
The total input from an AC adapter or other DC source is a function of the system supply current and the battery
charging current. System current normally fluctuates as portions of the systems are powered up or down. Without
DPM, the source must be able to supply the maximum system current and the maximum charger input current
simultaneously. By using DPM, the battery charger reduces the charging current when the input current exceeds
the input current limit set by ACSET. The current capability of the AC adapter can be lowered, reducing system
cost.
Similar to setting battery regulation current, adapter current is sensed by resistor RAC connected between ACP
and ACN. Its maximum value is set by ACSET using Equation 3:
VACSET
IDPM =
20 ´ RAC
(3)
VACSET, the input voltage range of ACSET, is from 0 V to 2 V. The ACP and ACN pins are used to sense voltage
across RAC with default value of 10 mΩ. However, resistors of other values can also be used. A larger the sense
resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction
loss.
9.3.4 Precharge
On power up, if the battery voltage is below the VLOWV threshold, the bq2461x applies the precharge current to
the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within
30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
The precharge current is determined by the voltage, VISET2, on the ISET2 pin.
VISET2
IPRECHARGE =
100 ´ R SR
(4)
9.3.5 Charge Termination, Recharge, and Safety Timer
The bq2461x monitors the charging current during the voltage regulation phase. When VTTC is valid, termination
is detected while the voltage on the VFB pin is higher than the VRECH threshold AND the charge current is less
than the ITERM threshold, as calculated in Equation 5:
16
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Feature Description (continued)
ITERM =
VISET2
100 ´ RSR
(5)
The input voltage of ISET2 is from 0 V to 2 V. The minimum precharge/termination current is clamped to be
around 125 mA with default 10-mΩ sensing resistor. As a safety backup, the bq2461x also provides a
programmable charge timer. The charge time is programmed by the capacitor connected between the TTC pin
and GND, and is given by Equation 6
tCHARGE = CTTC ´ K TTC
where
•
•
A
•
•
•
CTTC (range from 0.01 µF to 0.11 µF to give 1- to 10-h safety time) is the capacitor connected from TTC pin to
GND.
KTTC is the constant multiplier (5.6 min/nF).
(6)
new charge cycle is initiated and safety timer is reset when one of the following conditions occurs:
The battery voltage falls below the recharge threshold.
A power-on-reset (POR) event occurs.
CE is toggled.
The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF,
the bq2461x continues to allow termination, but disables the safety timer. TTC taken low resets the safety timer.
When ACOV, VCCLOWV, and SLEEP mode resume normal, the safety timer is reset.
9.3.6 Power Up
The bq2461x uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be
supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq2461x
enables the ACFET and disables BATFET. If all other conditions are met for charging, the bq2461x then
attempts to charge the battery (see Enable and Disable Charging). If the SRN voltage is greater than VCC,
indicating that the battery is the power source, the bq2461x enables the BATFET and enters a low quiescent
current (<15 μA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, ACFET turns off and BATFET turns on.
9.3.7 Enable and Disable Charging
The following conditions must be valid before charge is enabled:
• CE is HIGH.
• The device is not in undervoltage lockout (UVLO) and not in VCCLOWV mode.
• The device is not in SLEEP mode.
• The VCC voltage is lower than the AC overvoltage threshold (VCC < VACOV).
• 30-ms delay is complete after initial power up.
• The REGN LDO and VREF LDO voltages are at the correct levels.
• Thermal shut (TSHUT) is not valid.
• TS fault is not detected.
One of the following conditions will stop ongoing charging:
• CE is LOW.
• Adapter is removed, causing the device to enter UVLO, VCCLOWV, or SLEEP mode.
• Adapter is over voltage.
• The REGN or VREF LDO is overloaded.
• TSHUT IC temperature threshold is reached (145°C on rising edge with 15°C hysteresis).
• TS voltage goes out of range, indicating the battery temperature is too hot or too cold.
• TTC safety timer out.
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Feature Description (continued)
9.3.8 System Power Selector
The bq2461x automatically switches adapter or battery power to the system load. The battery is connected to the
system by default during power up or during SLEEP mode. The battery is disconnected from the system and
then the adapter is connected to the system 30 ms after exiting SLEEP. An automatic break-before-make logic
prevents shoot-through currents when the selectors switch.
The ACDRV is used to drive a pair of back-to-back P-channel power MOSFETs between the adapter and ACP
with sources connected together and to VCC. The FET connected to the adapter prevents reverse discharge
from the battery to the adapter when turned off. The P-channel FET with the drain connected to the adapter input
provides reverse battery discharge protection when off; and also minimizes system power dissipation with its low
rDS(on), compared to a Schottky diode. The other P-channel FET connected to ACP separates the battery from
the adapter, and provides a limited dI/dt when connecting the adapter to the system by controlling the FET
turnon time. The BATDRV controls a P-channel power MOSFET placed between BAT and the system.
When the adapter is not detected, ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter from
system. BATDRV stays at ACN-6V to connect the battery to the system.
Approximately 30 ms after the device comes out of SLEEP mode, the system begins to switch from the battery to
the adapter. The break-before-make logic keeps both ACFET and BATFET off for 10 µs before ACFET turns on.
This prevents shoot-through current or any large discharging current from going into the battery. BATDRV is
pulled up to ACN and the ACDRV pin is set to VCC-6V by an internal regulator to turn on P-channel ACFET,
connecting the adapter to the system.
When the adapter is removed, the system waits until VCC drops back to within 200 mV above SRN to switch
from the adapter back to the battery. The break-before-make logic still keeps 10 μs dead time. The ACDRV is
pulled up to VCC and the BATDRV pin is set to ACN-6V by an internal regulator to turn on P-channel BATFET,
connecting the battery to the system.
Asymmetrical gate drive (fast turnoff and slow turnon) for the ACDRV and BATDRV drivers provides fast turnoff
and slow turnon of the ACFET and BATFET to help the break-before-make logic and to allow a soft start at
turnon of either FET. The soft-start time can be further increased by putting a capacitor from gate to source of
the P-channel power MOSFETs.
9.3.9 Automatic Internal Soft-Start Charger Current
The charger automatically soft starts the charger regulation current every time the charger goes into fast charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft start consists
of stepping-up the charge regulation current into eight evenly divided steps up to the programmed charge
current. Each step lasts around 1.6 ms, for a typical rise time of 12.8 ms. No external components are needed
for this function.
9.3.10 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with feed-forward control scheme. A
type-III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter is selected to give a resonant frequency of 12 kHz to 17 kHz for bq2461x, where the
resonant frequency, fo, is given by:
1
fo =
2 p L o Co
(7)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty cycle of the
converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to get a 100% dutycycle PWM request. Internal gate-drive logic allows achieving 99.5% duty cycle while ensuring the N-channel
18
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Feature Description (continued)
upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for
more than 3 cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel
power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side
driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to
leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region. Also see Application and Implementation for how to select the inductor, capacitor, and MOSFET.
9.3.11 Synchronous and Nonsynchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10 mΩ sense resistor). During synchronous mode, the internal gate-drive logic ensures there is breakbefore-make complimentary switching to prevent shoot-through currents. During the 30 ns dead time where both
FETs are off, the body diode of the low-side power MOSFET conducts the inductor current. Having the low-side
FET turn on keeps the power dissipation low, and allows safely charging at high currents. During synchronous
mode, the inductor current is always flowing and the converter operates in Continuous Conduction Mode (CCM),
creating a fixed two-pole system.
The charger operates in nonsynchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current for a 10-mΩ sense resistor). The charger is forced into nonsynchronous mode when battery voltage is
lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During nonsynchronous operation, the body diode of lower-side MOSFET can conduct the positive inductor
current after the high-side N-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode is turned off and the inductor current becomes discontinuous. This
mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side N-channel power MOSFET
turns on for around 80 ns when the bootstrap capacitor voltage drops below 4.2 V; then the low-side power
MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power MOSFET is
turned on again. The 80-ns low-side MOSFET on-time is required to ensure the bootstrap capacitor is always
recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for battery
chargers, where unlike regular DC-DC converters, there is a battery load that maintains a voltage and can both
source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high- and low-side
MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80 ns, the
low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during nonsynchronous operation, there may be a small amount of negative inductor current
during the 80-ns recharge pulse. The charge should be low enough to be absorbed by the input capacitance.
Whenever the converter goes into zero-percent duty cycle, the high-side MOSFET does not turn on, and the lowside MOSFET does not turn on (only 80 ns recharge pulse) either, and there is almost no discharge from the
battery.
During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current because the converter does not sink current and only the load provides a
current sink. This means at very low currents, the loop response is slower, as there is less sinking current
available to discharge the output voltage.
9.3.12 Cycle-by-Cycle Charge Undercurrent Protection
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on for around 80
ns when the bootstrap capacitor voltage drops below 4.2 V to provide refresh charge for the bootstrap capacitor.
This is important to prevent negative inductor current from causing a boost effect in which the input voltage
increases, as power is transferred from the battery to the input capacitors and leads to an overvoltage stress on
the VCC node and potentially causes damage to the system.
9.3.13 Input Overvoltage Protection (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled and the system is switched to the battery instead of the adapter.
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Feature Description (continued)
9.3.14 Input Undervoltage Lockout (UVLO)
The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either input adapter or battery, because a conduction path exists from the battery to VCC through the high-side
NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC are disabled, and the gatedrive bias to ACFET and BATFET is disabled.
9.3.15 Battery Overvoltage Protection
The converter does not allow the high-side FET to turn on until the BAT voltage goes below 102% of the
regulation voltage. This allows one-cycle response to an overvoltage condition, such as occurs when the load is
removed or the battery is disconnected. An 8-mA current sink from SRP to GND is on only during charge and
allows discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP also
suspends the safety timer.
9.3.16 Cycle-by-Cycle Charge Overcurrent Protection
The charger has a secondary cycle-to-cycle overcurrent protection. It monitors the charge current, and prevents
the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the
overcurrent is detected, and automatically resumes when the current falls below the overcurrent threshold.
9.3.17 Thermal Shutdown Protection
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C; then the charger will soft start again if all other enable charge
conditions are valid. Thermal shutdown also suspends the safety timer.
9.3.18 Temperature Qualification
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. If battery
temperature is outside of this range, the controller suspends charge and the safety timer, and waits until the
battery temperature is within the VLTF to VHTF range. During the charge cycle, the battery temperature must be
within the VLTF to VTCO thresholds. If battery temperature is outside of this range, the controller suspends charge
and waits until the battery temperature is within the VLTF to VHTF range. The controller suspends charge by
turning off the PWM charge FETs. Figure 14 summarizes the operation.
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTF
VLTF_HYS
VLTF_HYS
TEMPERATURE RANGE
TO INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE
CYCLE
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
GND
GND
Figure 14. TS Pin, Thermistor Sense Thresholds
20
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Feature Description (continued)
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 19, the value RT1 and RT2 can be
determined by using the following equations:
æ 1
1 ö
VVREF ´ RTHCOLD ´ RTHHOT ´ ç
÷
V
V
TCO ø
è LTF
RT2 =
æV
ö
æV
ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
è VLTF
ø
è VTCO
ø
VVREF
RT1 =
VLTF
(8)
-1
1
1
+
RT2 RTHCOLD
(9)
For example, 103AT NTC thermistors are used to monitor the battery pack temperature. Select TCOLD = 0ºC and
TCUT_OFF = 45ºC; then we get RT2 = 430 kΩ, RT1 = 9.31 kΩ. A small RC filter is suggested to use for system-level
ESD protection.
VREF
bq24610/7
RT1
TS
RT2
RTH
103AT
Figure 15. TS Resistor Network
9.3.19 Timer Fault Recovery
The bq2461x provides a recovery method to deal with timer fault conditions. The following summarizes this
method:
Condition 1: The battery voltage is above the recharge threshold and a timeout fault occurs.
Recovery Method: The timer fault clears when the battery voltage falls below the recharge threshold, and
battery detection will begin. Taking CE low or a POR condition also clears the fault.
Condition 2: The battery voltage is below the recharge threshold and a timeout fault occurs.
Recovery Method: Under this scenario, the bq2461x applies the IFAULT current to the battery. This small current
is used to detect a battery removal condition and remains on as long as the battery voltage stays below the
recharge threshold. If the battery voltage goes above the recharge threshold, the bq2461x disables the fault
current and executes the recovery method described in Condition 1. Taking CE low or a POR condition also
clears the fault.
9.3.20
PG Output
The open-drain PG (power-good) output indicates whether the VCC voltage is valid or not. The open-drain FET
turns on whenever bq2461x has a valid VCC input (not in UVLO or ACOV or SLEEP mode). The PGpin can be
used to drive an LED or communicate to the host processor.
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Feature Description (continued)
9.3.21 CE (Charge Enable)
The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables
charge, provided all the other conditions for charge are met (see Enable and Disable Charging). A high-to-low
transition on this pin also resets all timers and fault conditions. There is an internal 1-MΩ pulldown resistor on the
CE pin, so if CE is floated the charge does not turn on.
9.3.22 Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the Table 2. These
status pins can be used to drive LEDs or communicate with the host processor. OFF indicates that the opendrain transistor is turned off.
Table 2. STAT Pin Definition for bq2461x
STAT1
STAT2
Charge in progress
CHARGE STATE
ON
OFF
Charge complete
OFF
ON
Charge suspend, timer fault, overvoltage, sleep mode, battery absent
OFF
OFF
22
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9.3.23 Battery Detection
For applications with removable battery packs, bq2461x provides a battery-absent detection scheme to reliably
detect insertion or removal of battery packs.
POR or RECHARGE
The battery detection routine runs on
power up, or if VFB falls below VRECH
due to removing a battery or
discharging a battery
Apply 8-mA discharge
current, start 1-s timer
VFB < VLOWV
No
Yes
1-s timer
expired
No
Yes
Battery Present,
Begin Charge
Disable 8-mA
discharge current
Enable 125-mA Charge,
Start 0.5-s timer
VFB > VRECH
Yes
Disable 125-mA
Charge
No
0.5-s timer
expired
No
Yes
Battery Present,
Begin Charge
Battery Absent
Figure 16. Battery Detection Flow Chart
Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery
voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is
turned on at low charge current (125 mA). If the battery voltage rises above the recharge threshold within 500
ms, there is no battery present and the cycle restarts. If either the 500-ms or 1-second timer times out before its
respective threshold is hit, a battery is detected and a charge cycle is initiated.
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Battery not detected
VREG
VRECH
(VWAKE)
Battery
inserted
VLOWV
Battery detected
(VDISH)
tLOWV_DEG
tWAKE
tRECH_DEG
Figure 17. Battery Detect Timing Diagram
Ensure that the total output capacitance at the battery node is not so large that the discharge current source
cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum output
capacitance can be calculated as follows:
CMAX =
IDISCH ´ tDISCH
é R ù
0.5 ´ ê1+ 2 ú
ë R1 û
where
•
•
•
•
CMAX is the maximum output capacitance.
IDISCH is the discharge current.
tDISCH is the discharge time.
R2 and R1 are the voltage feedback resistors from the battery to the VFB pin.
(10)
The 0.5 factor is the difference between the RECHARGE and the LOWV thresholds at the VFB pin.
Example
For a 3-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 kΩ (giving 12.6 V for voltage regulation), IDISCH = 8 mA,
tDISCH = 1 second,
8mA ´ 1sec
CMAX =
= 2.7 mF
é 500k ù
0.5 ´ ê1+
ú
ë 100k û
(11)
Based on these calculations, no more than 2.7 mF should be allowed on the battery node for proper operation of
the battery detection circuit.
24
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9.4 Device Functional Modes
Figure 18. Device Operation Flow Chart
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The bq2461x battery charger is ideal for high current charging (up to 10 A) and can charge battery packs
consisting of single cells or multiple cells in series. The bq24610EVM evaluation module is a complete charge
module for evaluating the bq2461x. The application curves were taken using the bq24610EVM. Refer to the EVM
user's guide (SLUU396) for EVM information.
10.2 Typical Application
Q1 (ACFET)
SI7617DN
R17
10Ω
SYSTEM
P
ADAPTER-
P
R14
100 kW
C16
2.2μF
RAC
0.010 W
Q2 (ACFET)
SI7616DN
C14
0.1 mF
C15
0.1 µF
C3
0.1 µF
C2
0.1 µF
ACN
VCC
BATDRV
ACDRV
R5
100 kW
R18
1 kΩ
R7
100 kW
R6
10 kW
R15
100 kW
PH
ISET2
BTST
R8
22.1 kW
VREF
REGN
bq24610
bq24617
C6
0.1 µF
C5
1 µF
LODRV
C4
1 µF
Q4
SIS412DN
L1
D1
BAT54
D2
R12 10 kW
D3
C12
C13
10 µF* 10 µF*
Q5
SIS412DN
SRP
C11
0.1 µF
R2
500 kΩ
Cff
22 pF
D4
R1
100 kW
SRN
STAT2
PG
VREF
103AT
PACK+
PACK-
STAT1
ADAPTER +
Pack
Thermistor
Sense
VBAT
6.8 µH*
C10
0.1 µF
GND
R9
9.31 kW
RSR
0.010 W
CE
R11 10 kW
R13 10 kW
P
Q3 (BATFET)
SI7617DN
R19
1 kΩ
HIDRV
ISET1
ACSET
R4
32.4 kW
C7
1µF
ACP
VREF
R3
100 kW
C9
10 μF
C8
10 µF
N
R20
2Ω
N
ADAPTER+
VFB
R16
100 W
R10
430 kW
C1
0.1 μF
TS
TTC
PwrPad
CTTC
0.056 μF
VIN = 19 V, 3-cell, Iadapter_limit = 4 A, Icharge = 3 A, Ipre-charge = Iterm = 0.3 A, 5-hour saftey timer
Figure 19. System Schematic
26
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Typical Application (continued)
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
AC adapter voltage (VIN)
19 V
AC adapter current limit
4A
Battery charge voltage (number of cells in series)
Battery charge current (during constant current phase)
Precharge and termination current
Safety timer
12.6 V (3 cells)
3A
0.3 A
5 hours
10.2.2 Detailed Design Procedure
10.2.2.1 Inductor Selection
The bq2461x has 600-kHz switching frequency to allow the use of small inductor and capacitor values. Inductor
saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(12)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L
(13)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9 V to 12.6 V for a 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is a 4-cell battery, the battery voltage range is from 12 V
to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20%–40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
The bq2461x has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charging-current
sensing resistor to prevent negative inductor current. The typical UCP threshold is 5-mV falling edge
corresponding to 0.5-A falling edge for a 10-mΩ charging-current sensing resistor.
10.2.2.2 Input Capacitor
The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worstcase RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst-case capacitor RMS current ICIN occurs where the duty cycle is closest
to 50% and can be estimated by the following equation:
ICIN = ICHG ´
D ´ (1 - D)
(14)
A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V or higher-rating
capacitor is preferred for 20-V input voltage. 10-µF to 20-µF capacitance is suggested for typical of 3-A to 4-A
charging current.
10.2.2.3 Output Capacitor
Output capacitor also should have enough ripple-current rating to absorb the output switching ripple current. The
output capacitor RMS current ICOUT is given:
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ICOUT =
IRIPPLE
2 ´
3
www.ti.com
» 0.29 ´ IRIPPLE
(15)
The output capacitor voltage ripple can be calculated as follows:
DVo =
1
8LCfs
2
æ
V 2
ç VBAT - BAT
ç
VIN
è
ö
÷
÷
ø
(16)
At a certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The bq2461x has an internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor should be designed between 12 kHz and 17 kHz. The preferred ceramic capacitor
has a 25-V or higher rating, X7R or X5R for 4-cell application.
10.2.2.4 Power MOSFETs Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate drive voltage. 30-V or higher-voltage rating MOSFETs are
preferred for 20-V input voltage and 40-V or higher-rating MOSFETs are preferred for 20-V to 28-V input voltage.
Figure-of-merit (FOM) is usually used for selecting the proper MOSFET based on a tradeoff between the
conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of the MOSFET ONresistance, rDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product
of the MOSFET ON-resistance, rDS(on), and the total gate charge, QG.
FOM top = RDS(on) ´ QG D
FOMbottom = RDS(on) ´ QG
(17)
The lower the FOM value, the lower the total power loss. Usually lower rDS(on) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D =
VOUT/VIN), charging current (ICHG), the MOSFET ON-resistance tDS(on)), input voltage (VIN), switching frequency
(fS), turnon time (ton) and turnoff time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ fS
2
(18)
The first item represents the conduction loss. Usually MOSFET rDS(on) increases by 50% with 100ºC junction
temperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are
given by:
Q
Q
ton = SW , t off = SW
Ion
Ioff
where
•
•
•
Qsw is the switching charge.
Ion is the turnon gate-driving current.
Ioff is the turnoff gate driving current.
(19)
If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain charge (QGD)
and gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(20)
Total gate-driving current can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total
turnon gate resistance (Ron), and turnoff gate resistance (Roff) of the gate driver:
VREG N - Vplt
Vplt
Ion =
, Ioff =
Ron
Roff
(21)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous CCM:
28
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Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on)
(22)
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum
charging current in nonsynchronous mode can be up to 0.9 A (0.5 A typical) for a 10-mΩ charging-current
sensing resistor, considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or
body diode capable of carrying the maximum nonsynchronous-mode charging current.
MOSFET gate-driver power loss contributes to the dominant losses on the controller IC when the buck converter
is switching. Choosing the MOSFET with a small Qg_total reduces the IC power loss to avoid thermal shutdown.
PICLoss_driver = VIN × Qg_total × fs
where
•
Qg_total is the total gate charge for both upper and lower MOSFETs at 6-V VREGN.
(23)
10.2.2.5 Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a secondorder system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the
IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin. The
ACP/ACN pins must be placed after the input ACFET in order to avoid overvoltage stress on these pins during
hot plug-in.
There are several methods for damping or limiting the overvoltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC
maximum pin voltage rating. A high-current capability TVS Zener diode can also limit the overvoltage level to an
IC safe level. However these two solutions may not have low cost or small size.
A cost-effective and small size-solution is shown in Figure 20. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used
for reverse voltage protection for the VCC pin (it can be the body diode of input ACFET). C2 is VCC pin
decoupling capacitor and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping
RC network to further protect the IC from high dv/dt and high-voltage spike. The C2 value should be less than
the C1 value so R1 can be dominant over the ESR of C1 to get enough damping effect for hot plug-in. The R1
and R2 packages must be sized to handle in-rush current power loss according to resistor manufacturer’s
datasheet. The filter component values always must be verified with the real application and minor adjustments
may be needed to fit in the real application circuit.
D1
Adapter
connector
R1
2W
C1
2.2 mF
(2010)
R2 (1206)
4.7 -30W
VCC pin
C2
0.1-1 mF
Figure 20. Input Filter
10.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
The bq2461x provides internal loop compensation. With this scheme, best stability occurs when the LC resonant
frequency, fo, is approximately 12 kHz to 17 kHz for bq2461x.
Table 4 provides a summary of typical LC components for various charge currents:
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Table 4. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current for
bq2461x (600-kHz Switching Frequency)
CHARGE CURRENT
2A
4A
6A
8A
10 A
Output inductor LO
6.8 μH
6.8 μH
4.7 μH
3.3 μH
3.3 μH
Output capacitor CO
20 μF
20 μF
30 μF
40 μF
40 μF
Sense resistor
10 mΩ
10 mΩ
10 mΩ
10 mΩ
10 mΩ
Table 5. Component List for Typical System Circuit of Figure 19
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2, Q3
3
P-channel MOSFET, –30 V, –35 A, PowerPAK 1212-8, Vishay-Siliconix, Si7617DN
Q4, Q5
2
N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN
D1
1
Diode, dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D2, D3, D4
3
LED diode, green, 2.1 V, 20 mA, LTST-C190GKT
RAC, RSR
2
Sense resistor, 10 mΩ, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 6.8 µH, 5.5A, Vishay-Dale IHLP2525CZ
C8, C9, C12, C13
4
Capacitor, ceramic, 10 µF, 35 V, 20%, X7R
C4, C5
2
Capacitor, ceramic, 1 µF, 16 V, 10%, X7R
C1, C3, C6, C11
4
Capacitor, ceramic, 0.1 µF, 16 V, 10%, X7R
C2, C10
2
Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R
C7
1
Capacitor, ceramic, 1 µF, 50 V, 10%, X7R
C14, C15 (Optional)
2
Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R
C16
1
Capacitor, ceramic, 2.2 µF, 35 V, 10%, X7R
Cff
1
Capacitor, ceramic, 22 pF, 25 V, 10%, X7R
CTTC
1
Capacitor, ceramic, 0.056 µF, 16 V, 5%, X7R
R1, R3, R5, R7
4
Resistor, chip, 100 kΩ, 1/16 W, 0.5%
R2
1
Resistor, chip, 500 kΩ, 1/16 W, 0.5%
R4
1
Resistor, chip, 32.4 kΩ, 1/16 W, 0.5%
R6
1
Resistor, chip, 10 kΩ, 1/16 W, 0.5%
R8
1
Resistor, chip, 22.1 kΩ, 1/16 W, 0.5%
R9
1
Resistor, chip, 9.31 kΩ, 1/16 W, 1%
R10
1
Resistor, chip, 430 kΩ, 1/16 W, 1%
R11, R12, R13, R18, R19
5
Resistor, chip, 10 kΩ, 1/16 W, 5%
R14, R15 (optional)
2
Resistor, chip, 100 kΩ, 1/16 W, 5%
R16
1
Resistor, chip, 100 Ω, 1/16 W, 5%
R17
1
Resistor, chip, 10 Ω, 1/4 W, 5%
R20
1
Resistor, chip, 2 Ω, 1 W, 5%
30
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10.2.3 Application Curves
VIN: 19 V
VBAT: 12 V
ICHG = 4 A
Figure 21. Continuous Conduction Mode Switching
Waveform
VIN: 19 V
VBAT: 12 V
Figure 22. Battery Charging Soft Start
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11 Power Supply Recommendations
For proper operation of bq2461x, VCC must be from 5 V to 28 V (bq24610) or 24 V (bq24617). To begin
charging, VCC must be higher than SRN by at least 500 mV (otherwise, the device will be in sleep mode). TI
recommends an input voltage of at least 1.5 V to 2 V higher than the battery voltage, taking into consideration
the DC losses in the high-side FET (Rdson), inductor (DCR), and input sense resistor (between ACP and ACN),
the body diode drop of RBFET between VCC and input power supply, and battery sense resistor (between SRP
and SRN). Power limit for the input supply must be greater than the maximum power required by either the
system load or for battery charging (the greater of the two).
12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current-path loop (see Figure 23) is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to switching MOSFET supply and ground connections and use
the shortest possible copper trace connection. These parts should be placed on the same layer of the PCB
instead of on different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals to keep the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 24 for Kelvin connection for
best current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper-pour for analog
ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to
GND. Connect analog ground and power ground together using the thermal pad as the single ground
connection point. Or use a 0-Ω resistor to tie analog ground to power ground (thermal pad should tie to
analog ground in this case). A star connection under the thermal pad is highly recommended.
8. It is critical to solder the exposed thermal pad on the back side of the IC package to the PCB ground. Ensure
that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
9. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
10. Size and number of all vias must be enough for a given current path.
See the EVM design (SLUU396) for the recommended component placement with trace and via locations.
For the QFN information, see SCBA017 and SLUA271.
32
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12.2 Layout Example
SW
L1
V BAT
R1
High
Frequency
VIN
BAT
Current
C1
Path
PGND
C2
C3
Figure 23. High-Frequency Current Path
Current Direction
R SNS
Current Sensing Direction
To SRP - SRN pin or ACP - ACN pin
Figure 24. Sensing Resistor PCB Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq24610
Click here
Click here
Click here
Click here
Click here
bq24617
Click here
Click here
Click here
Click here
Click here
13.3 Trademarks
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24610RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAS
BQ24610RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAS
BQ24617RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OFB
BQ24617RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OFB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Aug-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24610RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24610RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24610RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24610RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24617RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24617RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24617RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24617RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24610RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24610RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24610RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24610RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24617RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24617RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24617RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24617RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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