datasheet for M30xxLFXI by Cypress Semiconductor

datasheet for M30xxLFXI by Cypress Semiconductor
MoBL® Clock
M3000/M6000
Three-PLL Programmable Clock Generator
for Portable Applications
Features
Benefits
■
Device operating voltage options:
®
❐ MoBL Clock M3000 family: 1.8 V
❐ MoBL Clock M6000 family: 2.5 V, 3.0 V, or 3.3 V
■
Selectable clock output voltages for both MoBL clock M3000
and M6000:
❐ 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V
■
Fully integrated ultra-low power phase-locked loops (PLLs)
■
Input reference clock frequency range:
❐ External crystal: 8 to 48 MHz
❐ External reference: 1- to 48-MHz clock
■
Suitable for cell phone, portable, and consumer electronics
applications
■
Replaces multiple crystals or crystal oscillators saving board
space
■
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
■
Capable of zero parts per million (PPM) frequency synthesis
error
■
Application compatibility in multiple output voltage levels
■
Optional Spread Spectrum capable-PLLs with Lexmark or
Linear profile for maximum electromagnetic interference (EMI)
reduction
■
Output clock frequency range: 3 to 50 MHz
■
Up to eight I2C programmable output clocks
■
Programmable output drive strengths
■
Programmable PLLs for system frequency margin tests
■
150 ps typical cycle-to-cycle jitter
■
Meets critical timing requirements in complex system designs
■
Optional Spread Spectrum for EMI reduction
■
Individually enable or disable each output using I2C
■
24-pin (4 × 4 × 1 mm) quad flat no leads (QFN) package
■
■
Industrial temperature range
Ease of output clock selection using programmable crossbar
switches
Logic Block Diagram
CLK1
XIN/
EXCLKIN
XOUT
Bank
1
OSC
Crossbar
Switch
PLL1
Output
Dividers
CLK3
and
Drive
Strength
PLL2
(SS)
MUX
and
Control
Logic
CLK2
Bank
2
CLK4
CLK5
Control
CLK6
Bank
3
PLL3
(SS)
SCL
CLK7
CLK8
2
SDA
I C
SSON
PD #/ OE
Cypress Semiconductor Corporation
Document #: 001-29159 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 17, 2010
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MoBL® Clock
M3000/M6000
Contents
Pinouts ..............................................................................
MoBL Clock M3000 .....................................................
MoBL Clock M6000 .....................................................
General Description .........................................................
Three Configurable PLLs ............................................
I2C Programming ........................................................
Input Reference Clocks ...............................................
Output Supply Bank Settings ......................................
Output Source Selection .............................................
Spread Spectrum Control............................................
PD#/OE Mode .............................................................
Keep Alive Mode .........................................................
Output Drive Strength..................................................
Custom Configuration Programming ...........................
I2C Serial Interface ...........................................................
Device Address ...........................................................
Data Valid....................................................................
Data Frame .................................................................
Acknowledge Pulse .....................................................
Write Operations...............................................................
Writing Individual Bytes ...............................................
Writing Multiple Bytes..................................................
Read Operations...............................................................
Current Address Read.................................................
Random Read .............................................................
Sequential Read..........................................................
Document #: 001-29159 Rev. *C
3
3
4
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
Serial Programming Interface Timing............................. 8
Serial I2C Programming Interface
Timing Specifications ...................................................... 8
Absolute Maximum Conditions....................................... 9
Recommended Operating Conditions ............................ 9
DC Electrical Specifications .......................................... 10
AC Electrical Specifications .......................................... 11
Recommended Crystal Specification
for SMD Package ............................................................ 11
Recommended Crystal Specification
for Thru-Hole Package ................................................... 11
Test and Measurement Setup........................................ 12
Voltage and Timing Definitions..................................... 12
Ordering Information...................................................... 13
Possible Configurations............................................. 13
Ordering Code Definition........................................... 13
Package Drawing and Dimensions ............................... 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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MoBL® Clock
M3000/M6000
Pinouts
MoBL Clock M3000
XIN/
EXCLKIN
XOUT
VDD
DNU
CLK8
GND
Figure 1. Pin Diagram - 24-Pin QFN
24
23
22
21
20
19
GND
1
18
GND
CLK1
2
17
CLK7
VDD_CLK_B1
3
16
VDD_CLK_B3
PD#/OE
4
15
CLK6/ SSON
VDD
5
14
CLK2
6
13
10
11
12
CLK4
GND
SCL
9
CLK3
8
SDA
7
GND
MoBL Clock M3000
VDD_CLK_B2
CLK5
Table 1. Pin Definitions - MoBL Clock M3000 Family (VDD = 1.8-V Supply)
Pin Number
Name
IO
Description
1
GND
Power
Power supply ground
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK1
VDD_CLK_B1
PD#/OE
VDD
CLK2
GND
SCL
SDA
CLK3
CLK4
GND
CLK5
VDD_CLK_B2
Output
Power
Input
Power
Output
Power
Input
Input/Output
Output
Output
Power
Output
Power
15
CLK6/SSON
Output/Input
16
VDD_CLK_B3
Power
17
18
19
20
21
22
23
24
CLK7
GND
GND
CLK8
DNU
VDD
XOUT
XIN/EXCLKIN
Output
Power
Power
Output
Input
Power
Output
Input
Programmable clock output. Output voltage depends on Bank1 voltage
Power supply for Bank1 (CLK1, CLK2) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
Multifunction programmable pin: Output enable or power-down modes
Power supply: 1.8 V
Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
Power supply ground
Serial data clock
Serial data input/output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
Power supply ground
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
Power supply for Bank2 (CLK3, CLK4, CLK5) outputs:
1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
Multifunction programmable pin: Programmable clock output or Spread Spectrum
control input pin. Output voltage depends on VDD_CLK_B3 voltage
Power supply for Bank3 (CLK6, CLK7, CLK8) outputs:
1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
Power supply ground
Power supply ground
Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
Do not use
Power supply: 1.8 V
Crystal output
Crystal input or 1.8 V external reference clock input
Document #: 001-29159 Rev. *C
Page 3 of 16
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MoBL® Clock
M3000/M6000
MoBL Clock M6000
XIN
/
EXCLKIN
XOUT
VDD
DNU
CLK8
GND
Figure 2. Pin Diagram - 24-Pin QFN
2
4
2
3
2
2
2
1
2
0
1
9
GND
1
1
8
GND
CLK1
2
1
7
CLK7
V DD_CLK_B1
3
1
6
VDD_CLK_B3
4
1
5
CLK6/SSON
5
1
4
VDD_CLK_B2
6
1
3
CLK5
7
8
9
1
0
1
1
1
2
SDA
CLK3
CLK4
GND
CLK2
SCL
DNU
GND
PD#/
OE
MoBL Clock M6000
Table 2. Pin Definitions - MoBL Clock M6000 Family (VDD = 2.5-V, 3.0-V, or 3.3-V Supply)
Pin Number
Name
IO
Description
1
GND
Power
Power supply ground
2
CLK1
Output
Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
3
VDD_CLK_B1
Power
Power supply for Bank1 (CLK1, CLK2) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
4
PD#/OE
Input
Multifunction programmable pin: Output enable or power-down modes
5
DNU
DNU
Do not use
6
CLK2
Output
Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
7
GND
Power
Power supply ground
8
SCL
Input
Serial data clock
9
SDA
Input/Output
Serial data input/output
10
CLK3
Output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
11
CLK4
Output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
12
GND
Power
Power supply ground
13
CLK5
Output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
14
VDD_CLK_B2
Power
Power supply for Bank2 (CLK4, CLK4, CLK5) outputs:
1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
15
CLK6/SSON
Output/Input
Multifunction programmable pin: Programmable clock output or Spread Spectrum
ON/OFF control input pin. Output voltage depends on VDD_CLK_B3 voltage
16
VDD_CLK_B3
Power
Power supply for Bank3 (CLK6, CLK7, CLK8) outputs:
1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
17
CLK7
Output
Programmable Clock Output. Output voltage depends on VDD_CLK_B3 voltage
18
GND
Power
Power supply ground
19
GND
Power
Power supply ground
20
CLK8
Output
Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
21
DNU
Input
Do not use
22
VDD
Power
Power supply: 2.5 V/3.0 V/3.3 V
23
XOUT
Output
Crystal output
24
XIN/EXCLKIN
Input
Crystal input or 1.8 V external reference clock input
Document #: 001-29159 Rev. *C
Page 4 of 16
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MoBL® Clock
M3000/M6000
General Description
Three Configurable PLLs
The MoBL® Clock M3000/M6000 family of products are
three-PLL clock generator ICs designed for cell phone, portable,
or consumer electronics applications. It can be used to generate
three independent output frequencies ranging from 3 MHz to
50 MHz from a single input reference clock.
I2C Programming
The MoBL® Clock M3000 and M6000 have a serial I2C interface
that programs the configuration memory array to synthesize
output frequencies by programmable output divider, spread
characteristics, and drive strength. I2C can also be used for
in-system control of these programmable features.
Input Reference Clocks
The input to the M3000 and M6000 can be either a crystal or a
clock signal. The input frequency range for crystals is 8 MHz to
48 MHz, while that for EXCLKIN is 1 MHz to 48 MHz. The voltage
level for the input reference clock used must meet the voltage
requirement for the device as shown in the DC and AC
specifications.
Output Supply Bank Settings
These devices have eight clock outputs grouped in three banks.
The Bank 1, Bank 2, and Bank 3 correspond to (CLK1, CLK2),
(CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8) respectively. A
separate power supply is used for each of these three output
drivers and they can be 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V giving
the user multiple choices of output clock voltage levels.
Output Source Selection
These devices have eight clock outputs (CLK1 to CLK8). There
are four available clock sources for these outputs. These clock
sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3. Output
clock source selection is done using a four out of four crossbar
switch. Therefore, any one of these four available clock sources
can be arbitrarily selected for the clock outputs. This gives the
user a flexibility to have up to three independent clocks and
reference clock outputs.
Spread Spectrum Control
PD#/OE Mode
PD#/OE input (Pin 4) can be programmed to operate as either
power down (PD#) or output enable (OE) mode. Note that PD#
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal High brings the
device in the operational mode with default register settings. The
PD# turn-on time is limited by the turn-on time of the PLLs.
Disabled outputs are first driven to a low state before turning off.
When off, they are held low by internal weak resistors (~160 kΩ).
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Keep Alive Mode
By activating the device in the Keep Alive mode, the power-down
mode is changed to power-saving mode, which disables all PLLs
and outputs, but preserves the contents of the volatile registers.
Therefore, any configuration changes made through the I2C
interface are preserved. By deactivating the Keep Alive mode,
I2C memory is not preserved during power-down, but power
consumption is reduced relative to the Keep Alive mode.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 3 shows the typical rise
and fall times for different drive strength settings.
Table 3. Output Drive Strength
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Low
6.8
Mid Low
3.4
Mid High
2.0
High
1.0
Custom Configuration Programming
The MoBL® Clock can be custom-programmed to any desired
frequency and listed features. For customer-specific
programming and I2C programmable memory bitmap definitions,
contact the local Cypress field application engineer (FAE) or
sales representative.
Two of the four PLLs (PLL2 and PLL3) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress-proprietary PLL and Spread Spectrum Clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off by I2C
device programming. It can be factory-programmed to either
center spread range from ±0.125% to ±2.50%, or down spread
range from –0.25% to –5.0%, with Lexmark or Linear modulation
profile.
Document #: 001-29159 Rev. *C
Page 5 of 16
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MoBL® Clock
M3000/M6000
I2C Serial Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I2C serial interface is provided. This interface is used
to write (and optionally read) control registers that control various
device functions such as enabling individual clock output buffers.
The registers initialize to their default setting upon power-up and
therefore, use of this interface is optional. Clock device registers
are normally changed upon system initialization. Any data written
through I2C is volatile and is not retained when the device is
powered down.
Writing Multiple Bytes
To write multiple bytes at a time, the master must not end the
write sequence with a stop condition, but instead send multiple
contiguous bytes of data to be stored. After each byte, the slave
responds with an acknowledge bit, the same as after the first
byte, and accepts data until the acknowledge bit is responded to
by the stop condition. When receiving multiple bytes, the MoBL
Clock M3000/M6000 internally increments the register address.
Read Operations
The I2C interface uses two signals, SDA and SCL, that operates
up to 400 kbits/s in Read or Write mode. The SDA and SCL
timing and data transfer sequence is shown in Figure 3 on page
7. The basic Write serial format is as follows:
Read operations are initiated the same way as write operations
except that the R/W bit of the slave address is set to ‘1’ (High).
There are three basic read operations: current address read,
random read, and sequential read.
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4 on page 7.
Current Address Read
Data Valid
The MoBL Clock M3000/M6000 have an onboard address
counter that retains ‘1’ more than the address of the last word
accessed. If the last word written or read was word ‘n’, then a
current address read operation returns the value stored in
location ‘n+1’. When the MoBL Clock M3000/M6000 receives the
slave address with the R/W bit set to a ‘1’, it issues an
acknowledge and transmits the 8-bit word. The master device
does not acknowledge the transfer, but generates a stop
condition, which causes the MoBL Clock M3000/M6000 to stop
transmission.
Data is valid when the clock is High, and can only be transitioned
when the clock is low, as illustrated in Figure 5 on page 7.
Random Read
Device Address
The device serial interface address is 69H. The device address
is combined with a read/write bit as the least significant bit (LSB)
and is sent after each start bit.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 6 on page 8.
Start Sequence: SDA going low when SCL is High indicates a
start frame. Every time a start signal is supplied, the next 8-bit
data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Stop Sequence: SDA going High when SCL is High indicates a
stop frame. A stop frame frees the bus to write to another part on
the same bus or to write to another random register address.
Acknowledge Pulse
During Write mode, the MoBL Clock M3000 responds with an
Acknowledge pulse after every eight bits. This is done by pulling
the SDA line low during the N*9th clock cycle, as illustrated in
Figure 7 on page 8 (N = the number of bytes transmitted). During
Read mode, the master generates the acknowledge pulse after
reading the data packet.
Write Operations
Writing Individual Bytes
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. To do this, send the address to the MoBL
Clock M3000/M6000 as part of a write operation. After the word
address is sent, the master generates a start condition following
the acknowledge. This terminates the write operation before any
data is stored in the address, but not before the internal address
pointer is set. Next, the master reissues the control byte with the
R/W byte set to ‘1’. The MoBL Clock M3000/M6000 then issues
an acknowledge and transmits the 8-bit word. The master device
does not acknowledge the transfer, but generates a stop
condition, which causes the MoBL Clock M3000/M6000 to stop
transmission.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a stop condition after transmission of the first 8-bit data word.
This action increments the internal address pointer, and
subsequently outputs the next 8-bit data word. By continuing to
issue acknowledges instead of stop conditions, the master
serially reads the entire contents of the slave device memory.
When the internal address pointer points to the FFH register,
after the next increment, the pointer points to the 00H register.
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the receiving the data word, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a stop condition.
Document #: 001-29159 Rev. *C
Page 6 of 16
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MoBL® Clock
M3000/M6000
Figure 3. Data Transfer Sequence on the Serial Bus
SCL
SDA
Address or
Acknowledge
Valid
START
Condition
STOP
Condition
Data may
be changed
Figure 4. Data Frame Architecture
SDA Write
Multiple
Contiguous
Registers
1 Bit
1 Bit Slave
R/W = 0 ACK
7-bit
Device
Address
1 Bit
Slave
ACK
8-bit
Register
Address
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+1)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+2)
1 Bit
Slave
ACK
8-bit
Register
Data
(FFH)
1 Bit
Slave
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
SDA Read
Current
Address
Read Start Signal
SDA Read
Multiple
Contiguous
Registers
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
R/W = 1 ACK
7-bit
Device
Address
1 Bit
Slave
ACK
1 Bit
Master
ACK
8-bit
Register
Data
Stop Signal
1 Bit
1 Bit Slave
R/W = 0 ACK
7-bit
Device
Address
1 Bit
Slave
ACK
8-bit
Register
Address
(XXH)
1 Bit
Master
ACK
7-bit
Device
Address
+R/W=1
1 Bit
Master
ACK
8-bit
Register
Data
(XXH)
1 Bit
Master
ACK
8-bit
Register
Data
(XXH+1)
8-bit
Register
Data
(FFH)
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
Repeated
Start bit
Figure 5. Data Valid and Data Transition Periods
Data Valid
Transition
to next Bit
SDA
tDH
tSU
CLKHIGH
VIH
SCL
Document #: 001-29159 Rev. *C
VIL
CLKLOW
Page 7 of 16
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MoBL® Clock
M3000/M6000
Serial Programming Interface Timing
Figure 6. Start and Stop Frame
SDA
SCL
Transition
to next Bit
START
STOP
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDA
+
START
SCL
DA6
DA5 DA0
+
R/W
ACK
RA7
RA6 RA1
+
RA0
ACK
+
+
D7
D6
D1
D0
ACK
STOP
+
Serial I2C Programming Interface Timing Specifications
Parameter
fSCL
Description
Frequency of SCL
Start mode time from SDA LOW to SCL LOW
Min
Max
Unit
–
400
kHz
0.6
–
μs
CLKLOW
SCL Low period
1.3
–
μs
CLKHIGH
SCL High period
0.6
–
μs
tSU
Data transition to SCL High
250
–
ns
tDH
Data hold (SCL Low to data transition)
0
–
ns
Rise time of SCL and SDA
–
300
ns
Fall time of SCL and SDA
–
300
ns
Stop mode time from SCL High to SDA High
0.6
–
μs
Stop mode to Start mode
1.3
–
μs
Document #: 001-29159 Rev. *C
Page 8 of 16
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MoBL® Clock
M3000/M6000
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply voltage for MoBL Clock M60xx
–0.5
4.4
V
VDD
Supply voltage for MoBL Clock M30xx
–0.5
2.8
V
VDD_CLKX
Supply voltage for MoBL Clock
M30xx/M60xx
–0.5
4.4
V
VIN
Input voltage for MoBL Clock M60xx
Relative to VSS
–0.5
VDD+0.5
V
VIN
Input voltage for MoBL Clock M30xx
Relative to VSS
–0.5
2.2
V
TS
Temperature, Storage
Non functional
–65
+150
°C
ESDHBM
Electrostatic discharge (ESD) protection
(Human body model)
JEDEC EIA/JESD22-A114-E
2000
UL-94
Flammability rating
V – 0 at 1/8 in.
MSL
Moisture sensitivity level
V
10
ppm
3
Recommended Operating Conditions
The Recommended Operating Conditions table for MoBL Clock M30xx/M60xx family.
Parameter
VDD
Description
VDD operating voltage for MoBL Clock M60xx
Min
Typ
Max
Unit
2.25
–
3.60
V
VDD
VDD operating voltage for MoBL Clock M30xx
1.65
1.80
1.95
V
VDD_CLK_BX
Output driver voltage for MoBL Clock M30xx/M60xx
1.43
–
3.60
V
TAI
Industrial ambient temperature
–40
–
85
°C
CLOAD
Maximum load capacitance
–
–
15
pF
tPU
Power-up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
ms
Document #: 001-29159 Rev. *C
Page 9 of 16
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MoBL® Clock
M3000/M6000
DC Electrical Specifications
DC Electrical Specification table for MoBL Clock M30xx/M60xx family (VDD_CLK_BX = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V)
Parameter
Description
Output low voltage, CLK pins
VOL
Conditions
IOL = 2 mA, drive strength = [00]
Min
Typ
Max
Unit
–
–
0.4
V
VDD_CLK_BX
– 0.4
–
–
V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
Output high voltage, CLK pins
VOH
IOH = –2 mA, drive strength = [00]
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VOLSD
Output low voltage, SDA
–
–
0.4
V
VIL1
Input low voltage of SSON,
PD#/OE, SDA and SCL pins
–
–
0.2*VDD
V
VIL2
Input low voltage of EXCLKIN pin
–
–
0.15
V
VIH1
Input high voltage of SSON,
PD#/OE, SDA and SCL pins
0.8 × VDD
–
–
V
VIH2
Input high voltage of EXCLKIN
pin
1.6
–
2.2
V
IIL1
Input low current, PD#/OE pin
VIL = 0 V
–
–
10
µA
IIH1
Input high current, PD#/OE pin
VIH = VDD
–
–
10
µA
IIL2
Input low current, SSON pin
VIL = 0V (Internal pull down resistor
= 160k typ.)
–
–
10
µA
IIH2
Input high current, SSON pin
VIH = VDD (Internal pull down resistor
= 160k typ.)
14
–
36
µA
RDN
Pull-down resistor of SSON and Clock outputs in off-state by setting
clocks (CLK1-CLK8) in off state PD# = Low
100
160
250
kΩ
IDD[1,2]
IDDS
[1]
CIN[2]
IOL = 4 mA
Supply current
All outputs running, CLOAD = 0
–
15
–
mA
Standby current
PD# = Low, and I2C circuit not in Keep
–
3
–
µA
–
–
7
pF
Alive mode
Input capacitance
SCL, SDA, SSON and PD#/OE
inputs
Notes
1. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1].
2. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
Document #: 001-29159 Rev. *C
Page 10 of 16
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MoBL® Clock
M3000/M6000
AC Electrical Specifications
AC Electrical Specification table for M30xx/M60xx family (VDD_CLK_BX = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V)
Parameter
FCLK
Description
Clock output frequency
Conditions
Min
Typ
Max
Unit
3
–
50
MHz
FREF (crystal) Crystal frequency, XIN
All clock outputs
8
–
48
MHz
FREF (clock)
Input clock frequency,
EXCLKIN
1
–
48
MHz
DC
Output clock duty cycle
Duty cycle is defined in Figure 9 on page
12; t1/t2 measured at 50% of VDD_CLK_BX
45
50
55
%
TRF1[2]
Output clock rise/fall time
Measured from 20% to 80% of
VDD_CLK_BX, as shown in Figure 10 on
page 12, CLOAD = 15 pF, drive strength [00]
–
6.8
10.0
ns
TRF2[2]
Output clock rise/fall time
Measured from 20% to 80% of
VDD_CLK_BX, as shown in Figure 10 on
page 12, CLOAD = 15 pF, drive strength [01]
–
3.4
5.0
ns
TRF3[2]
Output clock rise/fall time
Measured from 20% to 80% of
VDD_CLKX_BX, as shown in Figure 10 on
page 12, CLOAD = 15 pF, drive strength [10]
–
2.0
3.0
ns
TRF4[2]
Output clock rise/fall time
Measured from 20% to 80% of
VDD_CLKX_BX, as shown in Figure 10 on
page 12, CLOAD = 15 pF, drive strength [11]
–
1.0
1.5
ns
TCCJ[1,2]
Cycle-to-cycle jitter
EXCLKIN = CLKx = 48 MHz,
CLOAD = 15 pF, 3 PLLs and 1 output for
each PLL enabled, drive strength = [11]
–
150
–
ps
TLOCK[2]
PLL lock time
–
1
3
ms
Recommended Crystal Specification for SMD Package
Parameter
Description
Range 1 Range 2 Range 3
Unit
Fmin
Minimum frequency
8
14
28
MHz
Fmax
Maximum frequency
14
28
48
MHz
R1
Motional resistance (ESR)
135
50
30
Ω
C0
Shunt capacitance
4
4
2
pF
CL
Parallel load capacitance
18
14
12
pF
DL(max)
Maximum crystal drive level
300
300
300
µW
Recommended Crystal Specification for Thru-Hole Package
Parameter
Description
Range 1 Range 2 Range 3
Unit
Fmin
Minimum frequency
8
14
24
MHz
Fmax
Maximum frequency
14
24
32
MHz
R1
Motional resistance (ESR)
90
50
30
Ω
C0
Shunt capacitance
7
7
7
pF
CL
Parallel load capacitance
18
12
12
pF
DL(max)
Maximum crystal drive level
1000
1000
1000
µW
Document #: 001-29159 Rev. *C
Page 11 of 16
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MoBL® Clock
M3000/M6000
Test and Measurement Setup
Figure 8. Test and Measurement Setup
VDD
Outputs
0.1 μF
CLOAD
DUT
GND
Voltage and Timing Definitions
Figure 9. Duty Cycle Definition
t1
t
2
VDD_CLK_BX
50% of VDD_CLK_BX
Clock
Output
0V
Figure 10. Rise Time = TRF, Fall Time = TRF
T RF
T RF
V DD_CL KX_B X
80% of VD D_CLK _B X
Clock
Output
Document #: 001-29159 Rev. *C
20% of VD D_CLK X_BX
0V
Page 12 of 16
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MoBL® Clock
M3000/M6000
Ordering Information
All product offerings are factory-programmed customer specific devices with customized part numbers. The Possible Configurations
table shows the available device types but not complete part numbers. Contact your local Cypress FAE or sales representative for
more information.
Possible Configurations
Part Number[3]
Frequency Configuration
VDD (V)
Package
Production Flow
Pb-Free
M30xxLFXI
VDD = 1.8 V
Customer-specific configuration
VDD_CLK_Bx =
EXCLKIN = xxxxMHz
CLK1 = xxxxMHz, CLK2 = xxxxMHz 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
CLK3 = xxxxMHz, CLK4 = xxxxMHz
CLK5 = xxxxMHz, CLK6 = xxxxMHz
CLK7 = xxxxMHz, CLK8 = xxxxMHz
24-pin QFN
M30xxLFXIT
Customer-specific configuration
VDD = 1.8 V
VDD_CLK_Bx =
EXCLKIN = xxxxMHz
CLK1 = xxxxMHz, CLK2 = xxxxMHz 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
CLK3 = xxxxMHz, CLK4 = xxxxMHz
CLK5 = xxxxMHz, CLK5 = xxxxMHz
CLK7 = xxxxMHz, CLK8 = xxxxMHz
24-pin QFN
Industrial, –40 °C to 85 °C
(Tape and reel)
M60xxLFXI
VDD = 2.5 V/3.0 V/3.3 V
Customer-specific configuration
VDD_CLK_Bx =
EXCLKIN = xxxxMHz
CLK1 = xxxxMHz, CLK2 = xxxxMHz 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
CLK3 = xxxxMHz, CLK4 = xxxxMHz
CLK5 = xxxxMHz, CLK5 = xxxxMHz
CLK7 = xxxxMHz, CLK8 = xxxxMHz
24-pin QFN
M60xxLFXIT
VDD = 2.5 V/3.0 V/3.3 V
Customer-specific configuration
VDD_CLK_Bx =
EXCLKIN = xxxxMHz
CLK1 = xxxxMHz, CLK2 = xxxxMHz 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
CLK3 = xxxxMHz, CLK4 = xxxxMHz
CLK5 = xxxxMHz, CLK5 = xxxxMHz
CLK7 = xxxxMHz, CLK8 = xxxxMHz
24-pin QFN
Industrial, –40 °C to 85 °C
(Tape and reel)
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Ordering Code Definition
M30/M60 XX LFX I
T
Tape and reel
Temperature range
I = Industrial
Pb-free QFN package
Custom configuration code
Base part number
Note
3. xx indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or sales representative
Document #: 001-29159 Rev. *C
Page 13 of 16
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MoBL® Clock
M3000/M6000
Package Drawing and Dimensions
Figure 11. 24-Pin QFN 4 × 4 mm (Subcon Punch Type Pkg with 2.49 × 2.49 EPAD) LF24A/LY24A
51-85203-*A
51-85203 *B
Document #: 001-29159 Rev. *C
Page 14 of 16
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MoBL® Clock
M3000/M6000
Acronyms
Document Conventions
Table 4. Acronyms Used in this Document
Table 5. Units of Measure
Acronym
Description
Symbol
Unit of Measure
EMI
electromagnetic interference
°C
degree Celsius
ESD
electrostatic discharge
kΩ
kilo ohm
FAE
field applications engineer
µA
microamperes
HBM
human body model
µF
micro Farad
JEDEC
Joint Electron Devices Engineering Council
µs
microsecond
MoBL
More Battery Life™
mA
milliamperes
OE
output enable
ms
millisecond
PLL
phase-locked loop
mV
millivolt
QFN
quad flat no-leads
MHz
megahertz
SSC
Spread Spectrum clock
ns
nanosecond
ppm
parts per million
Ω
ohm
pF
pico Farad
ps
pico second
V
volts
W
watts
Document #: 001-29159 Rev. *C
Page 15 of 16
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MoBL® Clock
M3000/M6000
Document History Page
Document Title: MoBL® Clock M3000/M6000 Three-PLL Programmable Clock Generator for Portable Applications
Document Number: 001-29159
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
1535768
See ECN
RGL
New Data Sheet
*A
2750166
08/10/2009
TSAI
Post to external web
*B
2897317
03/22/10
KVM
Moved ‘xx’ parts to Possible Configurations table
Updated package diagram
*C
3011498
CXQ
08/19/2010 Changed subsection at end of “General Description” to “Custom
Configuration Programming” and removed reference to Factory Specific
Configuration that was previously removed from the Ordering Information.
Added Contents, Ordering Code section, and Acronyms table.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC Solutions
Products
Automotive
Clocks & Buffers
Interface
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psoc.cypress.com/solutions
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
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Memory
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Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
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cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-29159 Rev. *C
Revised August 17, 2010
Page 16 of 16
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned
in this document may be the trademarks of their respective holders.
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