Volume 2: Arria GX Device Handbook

Volume 2: Arria GX Device Handbook
Arria GX Device Handbook, Volume 2
101 Innovation Drive
San Jose, CA 95134
www.altera.com
AGX5V2-2.0
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised
to obtain the latest version of device specifications before relying on any published information and before
placing orders for products or services.
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Altera Corporation
Chapter Revision Dates
The chapters in this book, Arria GX Device Handbook, Volume 2, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Arria GX Transceiver Architecture
Revised:
May 2008
Part number: AGX52001-2.0
Chapter 2. Arria GX Transceiver Protocol Support and Additional Features
Revised:
May 2008
Part number: AGX52002-2.0
Chapter 3. Arria GX ALT2GXB Megafunction User Guide
Revised:
May 2008
Part number: AGX52003-2.0
Chapter 4. Specifications and Additional Information
Revised:
May 2007
Part number: AGX52004-1.0
Chapter 5. PLLs in Arria GX Devices
Revised:
May 2008
Part number: AGX52005-1.2
Chapter 6. TriMatrix Embedded Memory Blocks in Arria GX Devices
Revised:
May 2008
Part number: AGX52006-1.2
Chapter 7. External Memory Interfaces in Arria GX Devices
Revised:
May 2008
Part number: AGX52007-1.2
Chapter 8. Selectable I/O Standards in Arria GX Devices
Revised:
May 2008
Part number: AGX52008-1.2
Chapter 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Revised:
May 2008
Part number: AGX52009-1.2
Altera Corporation
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Chapter Revision Dates
Arria GX Device Handbook, Volume 2
Chapter 10. DSP Blocks in Arria GX Devices
Revised:
May 2008
Part number: AGX52010-1.2
Chapter 11. Configuring Arria GX Devices
Revised:
May 2008
Part number: AGX52011-1.3
Chapter 12. Remote System Upgrades with Arria GX Devices
Revised:
May 2008
Part number: AGX52012-1.2
Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
Revised:
May 2008
Part number: AGX52013-1.2
Chapter 14. Package Information for Arria GX Devices
Revised:
May 2008
Part number: AGX52014-1.1
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Altera Corporation
Contents
Chapter Revision Dates .......................................................................... iii
About this Handbook ............................................................................. xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. Arria GX Transceiver User Guide
Chapter 1. Arria GX Transceiver Architecture
Introduction ............................................................................................................................................ 1–1
Building Blocks ...................................................................................................................................... 1–1
Port List ................................................................................................................................................... 1–3
Transmitter Channel Architecture ...................................................................................................... 1–8
Clock Multiplier Unit ....................................................................................................................... 1–9
Transmitter Phase Compensation FIFO ...................................................................................... 1–23
Byte Serializer ................................................................................................................................. 1–24
8B/10B Encoder .............................................................................................................................. 1–26
Serializer .......................................................................................................................................... 1–31
Transmitter Buffer .......................................................................................................................... 1–33
Receiver Channel Architecture .......................................................................................................... 1–36
Receiver Buffer ................................................................................................................................ 1–37
Receiver PLL ................................................................................................................................... 1–39
Clock Recovery Unit (CRU) ............................................................................................................. 1–41
Deserializer ....................................................................................................................................... 1–44
Word Aligner .................................................................................................................................... 1–47
Channel Aligner (Deskew) ................................................................................................................ 1–59
Rate Matcher ..................................................................................................................................... 1–59
8B/10B Decoder .............................................................................................................................. 1–62
Byte Deserializer ............................................................................................................................. 1–65
Receiver Phase Compensation FIFO Buffer ............................................................................... 1–66
PLD-Transceiver Interface Clocking ................................................................................................. 1–68
Automatic Phase Compensation FIFO Clock Selection ............................................................ 1–68
User Controlled Phase Compensation FIFO Clock Selection .................................................. 1–71
Loopback Modes .................................................................................................................................. 1–75
Serial Loopback .............................................................................................................................. 1–75
PCI Express PIPE Reverse Parallel Loopback ............................................................................ 1–76
Reverse Serial Loopback ............................................................................................................... 1–77
Reverse Serial Pre-CDR Loopback ............................................................................................... 1–78
Altera Corporation
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Contents
Arria GX Device Handbook, Volume 2
Built-In Self Test Modes ................................................................................................................
BIST in Basic Mode .........................................................................................................................
Calibration Blocks ................................................................................................................................
Referenced Documents .......................................................................................................................
Document Revision History ...............................................................................................................
1–79
1–80
1–82
1–84
1–85
Chapter 2. Arria GX Transceiver Protocol Support and Additional Features
Introduction ............................................................................................................................................ 2–1
PCI Express (PIPE) Mode ..................................................................................................................... 2–2
PCI Express (PIPE) Mode Transmitter Architecture ................................................................... 2–2
PCI Express (PIPE) Mode Receiver Architecture ...................................................................... 2–11
Receiver Status ................................................................................................................................ 2–21
Power State Management ............................................................................................................. 2–22
NFTS Fast Recovery IP (NFRI) ..................................................................................................... 2–23
Low-Latency (Synchronous) PCI Express (PIPE) Mode ........................................................... 2–24
Gigabit Ethernet (GIGE) mode .......................................................................................................... 2–26
GIGE Mode Transmitter Architecture ......................................................................................... 2–27
GIGE Mode Receiver Architecture .............................................................................................. 2–34
UNH-IOL Gigabit Ethernet Compliance .................................................................................... 2–42
Serial RapidIO Mode ........................................................................................................................... 2–43
Serial RapidIO Mode Transmitter Architecture ........................................................................ 2–43
Serial RapidIO Mode Receiver Architecture .............................................................................. 2–50
Basic Single-Width Mode ................................................................................................................... 2–57
XAUI Mode ........................................................................................................................................... 2–60
XAUI Mode Transmitter Architecture ........................................................................................ 2–64
XAUI Mode Receiver Architecture .............................................................................................. 2–71
Serial Digital Interface (SDI) Mode ................................................................................................... 2–81
Reset Control and Power-Down ........................................................................................................ 2–83
User Reset and Power-Down Signals .......................................................................................... 2–84
Recommended Reset Sequence for GIGE and Serial RapidIO in CRU Automatic Lock Mode ..
2–85
Recommended Reset Sequence for GIGE, Serial RapidIO, XAUI, SDI, and Basic Modes in CRU
Manual Lock Mode ........................................................................................................................ 2–86
Recommended Reset Sequence for PCI Express (PIPE) Mode ................................................ 2–88
Power-Down ................................................................................................................................... 2–90
TimeQuest Timing Analyzer ........................................................................................................ 2–90
Unconstrained Asynchronous ALT2GXB Ports ........................................................................ 2–98
Referenced Document ......................................................................................................................... 2–99
Document Revision History ............................................................................................................. 2–100
Chapter 3. Arria GX ALT2GXB Megafunction User Guide
Introduction ............................................................................................................................................ 3–1
Basic Mode .............................................................................................................................................. 3–3
PCI Express (PIPE) Mode ................................................................................................................... 3–25
XAUI Mode ........................................................................................................................................... 3–46
GIGE Mode ........................................................................................................................................... 3–64
SDI Mode .............................................................................................................................................. 3–86
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Contents
Contents
Serial RapidIO Mode ......................................................................................................................... 3–117
Referenced Documents ..................................................................................................................... 3–141
Document Revision History ............................................................................................................. 3–142
Chapter 4. Specifications and Additional Information
8B/10B Code .......................................................................................................................................... 4–1
Code Notation ................................................................................................................................... 4–1
Disparity Calculation ....................................................................................................................... 4–1
Supported Codes .............................................................................................................................. 4–3
Document Revision History ............................................................................................................... 4–11
Section II. Clock Management
Chapter 5. PLLs in Arria GX Devices
Introduction ............................................................................................................................................ 5–1
Enhanced PLLs ....................................................................................................................................... 5–5
Enhanced PLL Hardware Overview ............................................................................................. 5–5
Enhanced PLL Software Overview ................................................................................................ 5–8
Enhanced PLL Pins ........................................................................................................................ 5–11
Fast PLLs ............................................................................................................................................... 5–14
Fast PLL Hardware Overview ..................................................................................................... 5–14
Fast PLL Software Overview ........................................................................................................ 5–15
Fast PLL Pins ................................................................................................................................... 5–16
Clock Feedback Modes ....................................................................................................................... 5–18
Source-Synchronous Mode ........................................................................................................... 5–18
No Compensation Mode ............................................................................................................... 5–19
Normal Mode .................................................................................................................................. 5–20
Zero Delay Buffer Mode ................................................................................................................ 5–21
External Feedback Mode ............................................................................................................... 5–22
Hardware Features .............................................................................................................................. 5–23
Clock Multiplication and Division .............................................................................................. 5–24
Phase-Shift Implementation ......................................................................................................... 5–25
Programmable Duty Cycle ........................................................................................................... 5–26
Advanced Clear and Enable Control ........................................................................................... 5–27
Advanced Features .............................................................................................................................. 5–30
Counter Cascading ......................................................................................................................... 5–30
Clock Switchover ............................................................................................................................ 5–31
Reconfigurable Bandwidth ................................................................................................................ 5–42
PLL Reconfiguration ........................................................................................................................... 5–49
Spread-Spectrum Clocking ................................................................................................................ 5–49
Board Layout ........................................................................................................................................ 5–54
VCCA and GNDA ............................................................................................................................ 5–54
VCCD ................................................................................................................................................................................................................... 5–56
External Clock Output Power ...................................................................................................... 5–57
Guidelines ........................................................................................................................................ 5–58
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Contents
Arria GX Device Handbook, Volume 2
PLL Specifications ................................................................................................................................
Clocking ................................................................................................................................................
Global and Hierarchical Clocking ................................................................................................
Clock Sources Per Region ..............................................................................................................
Clock Input Connections ...............................................................................................................
Clock Source Control For Enhanced PLLs ..................................................................................
Clock Source Control for Fast PLLs .............................................................................................
Delay Compensation for Fast PLLs .............................................................................................
Clock Output Connections ............................................................................................................
Clock Control Block .............................................................................................................................
clkena Signals ..................................................................................................................................
Conclusion ............................................................................................................................................
Referenced Documents .......................................................................................................................
Document Revision History ...............................................................................................................
5–59
5–59
5–59
5–62
5–67
5–69
5–69
5–70
5–71
5–77
5–80
5–81
5–81
5–82
Section III. Memory
Chapter 6. TriMatrix Embedded Memory Blocks in Arria GX Devices
Introduction ............................................................................................................................................ 6–1
TriMatrix Memory Overview .............................................................................................................. 6–1
Parity Bit Support ............................................................................................................................. 6–3
Byte Enable Support ........................................................................................................................ 6–3
Pack Mode Support .......................................................................................................................... 6–7
Address Clock Enable Support ...................................................................................................... 6–7
Memory Modes ...................................................................................................................................... 6–9
Single-Port Mode ............................................................................................................................ 6–10
Simple Dual-Port Mode ................................................................................................................. 6–11
True Dual-Port Mode ..................................................................................................................... 6–14
Shift-Register Mode ....................................................................................................................... 6–17
ROM Mode ...................................................................................................................................... 6–19
FIFO Buffers Mode ......................................................................................................................... 6–19
Clock Modes ......................................................................................................................................... 6–19
Independent Clock Mode .............................................................................................................. 6–20
Input and Output Clock Mode ..................................................................................................... 6–22
Read and Write Clock Mode ......................................................................................................... 6–25
Single-Clock Mode ......................................................................................................................... 6–27
Designing With TriMatrix Memory .................................................................................................. 6–30
Selecting TriMatrix Memory Blocks ............................................................................................ 6–30
Synchronous and Pseudo-Asynchronous Modes ...................................................................... 6–31
Power-Up Conditions & Memory Initialization ........................................................................ 6–31
Read-During-Write Operation at the Same Address ..................................................................... 6–32
Same-Port Read-During-Write Mode .......................................................................................... 6–32
Mixed-Port Read-During-Write Mode ........................................................................................ 6–33
Conclusion ............................................................................................................................................ 6–34
Referenced Documents ....................................................................................................................... 6–35
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Contents
Contents
Document Revision History ............................................................................................................... 6–35
Chapter 7. External Memory Interfaces in Arria GX Devices
Introduction ............................................................................................................................................ 7–1
External Memory Standards ................................................................................................................ 7–3
DDR and DDR2 SDRAM ................................................................................................................. 7–3
Arria GX DDR Memory Support Overview ...................................................................................... 7–7
DDR Memory Interface Pins ........................................................................................................... 7–8
DQS Phase-Shift Circuitry ............................................................................................................ 7–11
DQS Logic Block ............................................................................................................................. 7–16
DDR Registers ................................................................................................................................. 7–19
PLL ................................................................................................................................................... 7–26
Conclusion ............................................................................................................................................ 7–26
Referenced Documents ....................................................................................................................... 7–26
Document Revision History ............................................................................................................... 7–26
Section IV. I/O Standards
Chapter 8. Selectable I/O Standards in Arria GX Devices
Introduction ............................................................................................................................................ 8–1
Arria GX I/O Features .......................................................................................................................... 8–1
Arria GX I/O Standards Support ........................................................................................................ 8–2
Single-Ended I/O Standards .......................................................................................................... 8–3
Differential I/O Standards ............................................................................................................ 8–10
Arria GX External Memory Interfaces .............................................................................................. 8–19
Arria GX I/O Banks ............................................................................................................................ 8–20
Programmable I/O Standards ...................................................................................................... 8–21
On-Chip Termination .......................................................................................................................... 8–25
On-Chip Series Termination without Calibration ..................................................................... 8–26
Design Considerations ........................................................................................................................ 8–28
I/O Termination ............................................................................................................................. 8–28
I/O Banks Restrictions .................................................................................................................. 8–29
I/O Placement Guidelines ............................................................................................................ 8–30
DC Guidelines ................................................................................................................................. 8–34
Conclusion ............................................................................................................................................ 8–37
References ............................................................................................................................................. 8–37
Referenced Documents ....................................................................................................................... 8–38
Document Revision History ............................................................................................................... 8–38
Chapter 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Introduction ............................................................................................................................................
I/O Banks ................................................................................................................................................
Differential Transmitter ........................................................................................................................
Differential Receiver ..............................................................................................................................
Receiver Data Realignment Circuit ...............................................................................................
Altera Corporation
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9–2
9–3
9–6
9–7
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Contents
Arria GX Device Handbook, Volume 2
Dynamic Phase Aligner ................................................................................................................... 9–8
Synchronizer ..................................................................................................................................... 9–9
Differential I/O Termination ............................................................................................................. 9–10
Fast PLL ................................................................................................................................................ 9–10
Clocking ................................................................................................................................................ 9–11
Source Synchronous Timing Budget ........................................................................................... 9–13
Differential Data Orientation ........................................................................................................ 9–14
Differential I/O Bit Position ......................................................................................................... 9–14
Receiver Skew Margin for Non-DPA .......................................................................................... 9–16
Differential Pin Placement Guidelines ............................................................................................. 9–18
High-Speed Differential I/Os and Single-Ended I/Os ............................................................. 9–18
DPA Usage Guidelines .................................................................................................................. 9–19
Non-DPA Differential I/O Usage Guidelines ............................................................................ 9–22
Board Design Considerations ............................................................................................................ 9–23
Conclusion ............................................................................................................................................ 9–24
Referenced Documents ....................................................................................................................... 9–25
Document Revision History ............................................................................................................... 9–25
Section V. Digital Signal Processing (DSP)
Chapter 10. DSP Blocks in Arria GX Devices
Introduction .......................................................................................................................................... 10–1
DSP Block Overview ........................................................................................................................... 10–2
Architecture .......................................................................................................................................... 10–7
Multiplier Block .............................................................................................................................. 10–7
Adder/Output Block ................................................................................................................... 10–14
Accumulator ....................................................................................................................................... 10–16
Operational Modes ............................................................................................................................ 10–18
Simple Multiplier Mode .............................................................................................................. 10–20
Multiply Accumulate Mode ....................................................................................................... 10–23
Multiply Add Mode ..................................................................................................................... 10–24
Complex Multiply ............................................................................................................................. 10–26
FIR Filter .............................................................................................................................................. 10–29
Software Support ............................................................................................................................... 10–31
Conclusion .......................................................................................................................................... 10–31
Referenced Documents ..................................................................................................................... 10–32
Document Revision History ............................................................................................................. 10–32
Section VI. Configuration& Remote System Upgrades
Chapter 11. Configuring Arria GX Devices
Introduction .......................................................................................................................................... 11–1
Configuration Devices ................................................................................................................... 11–1
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Contents
Contents
Configuration Features ....................................................................................................................... 11–4
Configuration Data Decompression ............................................................................................ 11–5
Remote System Upgrade ............................................................................................................... 11–8
Power-On Reset Circuit ................................................................................................................. 11–8
VCCPD Pins ....................................................................................................................................... 11–9
VCCSEL Pin .................................................................................................................................... 11–9
Fast Passive Parallel Configuration ................................................................................................ 11–13
FPP Configuration Using a MAX II Device as an External Host .......................................... 11–13
FPP Configuration Using a Microprocessor ............................................................................. 11–24
FPP Configuration Using an Enhanced Configuration Device ............................................. 11–24
Active Serial Configuration (Serial Configuration Devices) ....................................................... 11–32
Estimating Active Serial Configuration Time .......................................................................... 11–41
Programming Serial Configuration Devices ............................................................................ 11–41
Passive Serial Configuration ............................................................................................................ 11–44
PS Configuration Using a MAX II Device as an External Host ............................................. 11–45
PS Configuration Using a Microprocessor ............................................................................... 11–52
PS Configuration Using a Configuration Device ..................................................................... 11–53
PS Configuration Using a Download Cable ............................................................................. 11–65
Passive Parallel Asynchronous Configuration .............................................................................. 11–71
JTAG Configuration .......................................................................................................................... 11–82
Jam STAPL .................................................................................................................................... 11–89
Device Configuration Pins ............................................................................................................... 11–90
Conclusion ........................................................................................................................................ 11–104
Referenced Documents ................................................................................................................... 11–104
Document Revision History ........................................................................................................... 11–105
Chapter 12. Remote System Upgrades with Arria GX Devices
Introduction .......................................................................................................................................... 12–1
Functional Description ........................................................................................................................ 12–2
Configuration Image Types & Pages ........................................................................................... 12–5
Remote System Upgrade Modes ....................................................................................................... 12–7
Overview ......................................................................................................................................... 12–7
Remote Update Mode .................................................................................................................... 12–9
Local Update Mode ...................................................................................................................... 12–11
Dedicated Remote System Upgrade Circuitry .............................................................................. 12–13
Remote System Upgrade Registers ............................................................................................ 12–15
Remote System Upgrade State Machine ................................................................................... 12–18
User Watchdog Timer .................................................................................................................. 12–19
Interface Signals between Remote System Upgrade Circuitry & FPGA Logic Array ....... 12–20
Remote System Upgrade Pin Descriptions ............................................................................... 12–23
Quartus II Software Support ............................................................................................................ 12–23
altremote_update Megafunction ................................................................................................ 12–24
Remote System Upgrade Atom .................................................................................................. 12–27
System Design Guidelines ................................................................................................................ 12–27
Remote System Upgrade With Serial Configuration Devices ............................................... 12–28
Remote System Upgrade With a MAX II Device or Microprocessor & Flash Device ........ 12–28
Remote System Upgrade with Enhanced Configuration Devices ........................................ 12–29
Altera Corporation
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Contents
Arria GX Device Handbook, Volume 2
Conclusion .......................................................................................................................................... 12–30
Referenced Documents ..................................................................................................................... 12–31
Document Revision History ............................................................................................................. 12–31
Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
Introduction .......................................................................................................................................... 13–1
IEEE Std. 1149.1 BST Architecture .................................................................................................... 13–3
IEEE Std. 1149.1 Boundary-Scan Register ........................................................................................ 13–4
Boundary-Scan Cells of a Arria GX Device I/O Pin ................................................................. 13–5
IEEE Std. 1149.1 BST Operation Control .......................................................................................... 13–7
SAMPLE/PRELOAD Instruction Mode ................................................................................... 13–11
Capture Phase ............................................................................................................................... 13–12
Shift & Update Phases ................................................................................................................. 13–12
EXTEST Instruction Mode .......................................................................................................... 13–13
Capture Phase ............................................................................................................................... 13–14
Shift & Update Phases ................................................................................................................. 13–14
BYPASS Instruction Mode .......................................................................................................... 13–15
IDCODE Instruction Mode ......................................................................................................... 13–16
USERCODE Instruction Mode ................................................................................................... 13–16
CLAMP Instruction Mode .......................................................................................................... 13–17
HIGHZ Instruction Mode ........................................................................................................... 13–17
I/O Voltage Support in JTAG Chain .............................................................................................. 13–17
Using IEEE Std. 1149.1 BST Circuitry ............................................................................................. 13–19
BST for Configured Devices ............................................................................................................. 13–19
Disabling IEEE Std. 1149.1 BST Circuitry ....................................................................................... 13–20
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing ............................................................. 13–20
Boundary-Scan Description Language (BSDL) Support .............................................................. 13–21
Conclusion .......................................................................................................................................... 13–22
References ........................................................................................................................................... 13–22
Referenced Documents ..................................................................................................................... 13–22
Document Revision History ............................................................................................................. 13–22
Section VII. PCB Layout Guidelines
Chapter 14. Package Information for Arria GX Devices
Introduction ..........................................................................................................................................
Thermal Resistance ........................................................................................................................
Package Outlines .................................................................................................................................
484-Pin FBGA - Flip Chip ..............................................................................................................
780-Pin FBGA - Flip Chip ..............................................................................................................
1,152-Pin FBGA - Flip Chip ...........................................................................................................
Document Revision History ...............................................................................................................
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14–1
14–2
14–3
14–3
14–5
14–7
14–8
Altera Corporation
About this Handbook
This handbook provides comprehensive information about the Altera®
Arria™ GX family of devices.
How to Contact
Altera
For the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Technical support
Technical training
Contact
Method
Address
Website
www.altera.com/support
Website
www.altera.com/training
Email
[email protected]
Product literature
Website
www.altera.com/literature
Non-technical support
(General)
Email
[email protected]
(Software Licensing) Email
[email protected]
Note to table:
(1)
Typographic
Conventions
Visual Cue
You can also contact your local Altera sales office or sales representative.
This document uses the typographic conventions shown below.
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Altera Corporation
xiii
Preliminary
Typographic Conventions
Visual Cue
Arria GX Device Handbook, Volume 2
Meaning
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
●
•
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
c
A caution calls attention to a condition or possible situation that can damage or
destory the product or the user’s work.
w
The warning calls attention to a condition or possible situation that could cause
injury to the user.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
xiv
Preliminary
Altera Corporation
Section I. Arria GX
Transceiver User Guide
This section provides information on the configuration modes for
Arria™ GX devices. It also includes information on testing, Arria GX port
and parameter information, and pin constraint information.
This section includes the following chapters:
Revision History
Altera Corporation
■
Chapter 1, Arria GX Transceiver Architecture
■
Chapter 2, Arria GX Transceiver Protocol Support and Additional
Features
■
Chapter 3, Arria GX ALT2GXB Megafunction User Guide
■
Chapter 4, Specifications and Additional Information
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section I–1
Preliminary
Arria GX Transceiver User Guide
Section I–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
1. Arria GX Transceiver
Architecture
AGX52001-2.0
Introduction
Arria™ GX is a protocol-optimized FPGA family that leverages Altera’s
advanced multi-gigabit transceivers. The Arria GX transceiver blocks
build on the success of the Stratix® II GX family and are optimally
designed to support the following serial connectivity protocols
(functional modes):
■
■
■
■
■
■
Building Blocks
XAUI
PCI Express (PIPE)
Gigabit Ethernet (GIGE)
SDI
Serial RapidIO®
Basic Mode
Arria GX transceivers are structured into full duplex (transmitter and
receiver) four-channel groups called transceiver blocks. The Arria GX
device family offers up to 12 transceiver channels (three transceiver
blocks) per device. You can configure each transceiver block to one of the
supported functional modes; for example, four GIGE ports or one
four-lane (×4) PCI Express (PIPE) port. In Arria GX devices that offer
more than one transceiver block, you can configure each transceiver block
to a different functional mode; for example, one transceiver block
configured as a four-lane (×4) PCI Express (PIPE) port and the other
transceiver block can be configured as four GIGE ports.
Figure 1–1 shows the Arria GX transceiver block diagram divided into
transmitter and receiver circuits.
Altera Corporation
May 2008
1–1
Arria GX Transceiver Architecture
Figure 1–1. Arria GX Gigabit Transceiver Block Diagram
alt2gxb
Input
Output
rx_datain
rx_dataout
rx_seriallpbken
rx_signaldetect
rx_bitslip
rx_syncstatus
rx_enapatternalign
rx_patterndetect
rx_analogreset
rx_digitalreset
SIPO
Word
Aligner
Rate
Matcher
Channel
Aligner
8B/10B
Decoder
debug_rx_phase_comp_fifo_error
rx_cruclk
pipephydonestatus
rx_locktorefclk
pipeelecidle
Clock
Recovery
Unit
rx_locktodata
pipestatus
PIPE
Interface
rx_invpolarity
rx_revbitorderwa
rx_revbyteorderwa
refclk
rxvalid
rx_errdetect
Phase
Compensation
FIFO
Byte
Deserializer
Receiver
PLL
rx_ctrldetect
pipe8b10binvpolarity
rx_disperr
rx_bisterr
rx_bistdone
Receiver
tx_forceelecidle
tx_forcedispcompliance
powerdn
tx_detectrxloopback
tx_dataout
tx_datain
tx_clkout
tx_ctrlenable
coreclkout
tx_digitalreset
debug_tx_phase_comp_fifo_error
Phase
Compensation
FIFO
tx_forcedisp
tx_invpolarity
PIPE
Interface
Byte
Serializer
8B/10B
Encoder
PISO
pll_locked
rx_channelaligned
tx_dispval
fixedclk
cal_blk_clk
High-Speed
Clock
cal_blk_powerdown
pll_inclk
Transmitter
Clock
Divider
gxb_powerdown
gxb_enable
Transmitter
Central
Block
Central
Control
Unit
1–2
Arria GX Device Handbook, Volume 1
Reset
Logic
XAUI, PCIe,
and GIGE
State Machines
Altera Corporation
May 2008
Port List
Port List
You instantiate the Arria GX transceivers using the ALT2GXB MegaCore®
instance provided in the Quartus® II MegaWizard® Plug-In Manager. The
ALT2GXB instance allows you to configure the transceivers for your
intended protocol and select optional control and status ports to and from
the instantiated transceiver channels.
Table 1–1. Arria GX ALT2GXB Ports (Part 1 of 6)
Port Name
Input/
Output
Description
Scope
—
Receiver Physical Coding Sublayer (PCS) Ports
rx_dataout
Output
Receiver parallel data output. The bus width
depends on the channel width multiplied by the
number of channels per instance.
rx_clkout
Output
Recovered clock from the receiver channel.
Channel
rx_coreclk
Input
Optional read clock port for the receiver phase
compensation first-in first-out (FIFO). If not
selected, the Quartus II software automatically
selects rx_clkout/tx_clkout as the
read clock for receiver phase compensation
FIFO. If selected, you must drive this port with
a clock that is frequency locked to
rx_clkout/tx_clkout.
Channel
rx_enapatternalign
Input
Enables word aligner to align to the comma.
This port can be either edge or level sensitive
based on the word aligner mode.
Channel
rx_bitslip
Input
Word aligner bit slip control. The word aligner
slips a bit of the current word boundary every
rising edge of this signal.
Channel
rx_rlv
Output
Run-length violation indicator. A high signal is
driven when the run length (consecutive '1's or
'0's) of the received data exceeds the
configured limit.
Channel
pipe8b10binvpolarity
Input
Physical Interface for PCI Express (PIPE)
polarity inversion at the 8B/10B decoder input.
This port inverts the data at the input to the
8B/10B decoder.
Channel
Altera Corporation
May 2008
1–3
Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 2 of 6)
Port Name
Input/
Output
Description
Scope
pipestatus
Output
PIPE receiver status port. In case of multiple
status signals, the lower number signal takes
precedence.
000 - Received data OK
001 - 1 skip added (not supported)
010 - 1 skip removed (not supported)
011 - Receiver detected
100 - 8B/10B decoder error
101 - Elastic buffer overflow
110 - Elastic buffer underflow
111 - Received disparity error
Channel
pipephydonestatus
Output
PIPE indicates a mode transition
completion-power transition and rx_detect.
A pulse is given.
Channel
rx_pipedatavalid
Output
PIPE valid data indicator on the rx_dataout
port.
Channel
pipeelecidle
Output
PIPE signal detect for PCI Express.
Channel
rx_digitalreset
Input
Reset port for the receiver PCS block. This port
resets all the digital logic in the receiver
channel. The minimum pulse width is two
parallel clock cycles.
Channel
rx_bisterr
Output
Built-in self test (BIST) block error flag. This
port latches high if an error is detected.
Assertion of rx_digitalreset resets the
BIST verifier, which clears the error flag.
Channel
rx_bistdone
Output
Built-in self test verifier done flag. This port
goes high if the receiver finishes reception of
the test sequence.
Channel
rx_ctrldetect
Output
Receiver control code indicator port. Indicates
whether the data at the output of
rx_dataout is a control or data word. Used
with the 8B/10B decoder.
Channel
rx_errdetect
Output
8B/10B code group violation signal. Indicates
that the data at the output of rx_dataout
has a code violation or a disparity error. Used
with disparity error signal to differentiate
between a code group error and/or a disparity
error. In addition, in XAUI mode,
rx_errdetect is asserted in the
corresponding byte position when ALT2GXB
substitutes the received data with 9'b1FE
because of XAUI protocol violations.
Channel
1–4
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Port List
Table 1–1. Arria GX ALT2GXB Ports (Part 3 of 6)
Port Name
Input/
Output
Description
Scope
rx_syncstatus
Output
Indicates when the word aligner either aligns to
a new word boundary (in single width mode the
rx_patterndetect port is level sensitive),
indicates that a resynchronization is needed
(the rx_patterndetect is edge sensitive),
or indicates if synchronization is achieved or
not (the dedicated synchronization state
machine is used).
Channel
rx_disperr
Output
8B/10B disparity error indicator port. Indicates
that the data at the output of rx_dataout
has a disparity error.
Channel
rx_patterndetect
Output
Indicates when the word aligner detects the
alignment pattern in the current word
boundary.
Channel
rx_invpolarity
Input
Inverts the polarity of the received data at the
input of the word aligner
Channel
rx_revbitorderwa
Input
Available in Basic mode with bit-slip word
alignment enabled. Reverses the bit-order of
the received data at a byte level at the output
of the word aligner.
Channel
debug_rx_phase_comp_
fifo_error
Output
Indicates receiver phase compensation FIFO
overrun or underrun situation
Channel
Receiver Physical Media Attachment (PMA)
rx_pll_locked
Output
Receiver PLL locked signal. Indicates if the
receiver PLL is phase locked to the CRU
reference clock.
Channel
rx_analogreset
Input
Receiver analog reset. Resets all analog
circuits in the receiver PMA.
Channel
rx_freqlocked
Output
CRU mode indicator port. Indicates if the CRU
is locked to data mode or locked to the
reference clock mode.
0 – Receiver CRU is in lock-to-reference clock
mode
1 – Receiver CRU is in lock-to-data mode
Channel
rx_signaldetect
Output
Signal detect port. In PIPE mode, indicates if a
signal that meets the specified range is present
at the input of the receiver buffer. In all other
modes, rx_signaldetect is forced high
and must not be used as an indication of a valid
signal at receiver input.
Channel
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 4 of 6)
Port Name
Input/
Output
rx_seriallpbken
Input
rx_locktodata
Input
Description
Scope
Serial loopback control port.
0 – normal data path, no serial loopback
1 – serial loopback
Channel
Lock-to-data control for the CRU. Use with
Channel
rx_locktorefclk.
rx_locktorefclk
Input
Lock-to-reference lock mode for the CRU. Use
with rx_locktodata.
rx_locktodata/rx_locktorefclk
0/0 – CRU is in automatic mode
0/1 – CRU is in lock-to-reference clock
1/0 – CRU is in lock-to-data mode
1/1 – CRU is in lock-to-data mode
Channel
rx_cruclk
Input
Receiver PLL/CRU reference clock.
Channel
tx_datain
Input
Transmitter parallel data input. The bus width
depends on the channel width for the selected
functional mode multiplied by the number of
channels in the instance.
Channel
tx_clkout
Output
PLD logic array clock from the transceiver to
the PLD. In an individual-channel mode, there
is one tx_clkout per channel.
Channel
tx_coreclk
Input
Optional write clock port for the transmitter
phase compensation FIFO. If not selected, the
Quartus II software automatically selects
tx_clkout as the write clock for transmitter
phase compensation FIFO. If selected, you
must drive this port with a clock that is
frequency locked to tx_clkout.
Channel
tx_detectrxloopback
Input
PIPE receiver detect / loopback pin.
Depending on the power-down state (P0 or
P1), the signal either activates receiver detect
or loopback.
Channel
tx_forceelecidle
Input
PIPE Electrical Idle mode.
Channel
tx_forcedispcompliance
Input
PIPE forced negative disparity port for
transmission of the compliance pattern. The
pattern requires starting at a negative disparity.
Assertion of this port at the first byte ensures
that the first byte has a negative disparity. This
port must be deasserted after the first byte.
Channel
Transmitter PCS
1–6
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Port List
Table 1–1. Arria GX ALT2GXB Ports (Part 5 of 6)
Port Name
Input/
Output
Description
Scope
powerdn
Input
PIPE power mode port. This port sets the
power mode of the associated PCI Express
channel. The power modes are as follows:
2'b00: P0 – Normal operation
2'b01: P0s – Low recovery time latency, power
saving state
2'b10: P1 – Longer recovery time (64 μs max)
latency, lower power state
2'b11: P2 – Lowest power state
Channel
tx_digitalreset
Input
Reset port for the transmitter PCS block. This
port resets all the digital logic in the transmit
channel. The minimum pulse width is two
parallel clock cycles.
Channel
tx_ctrlenable
Input
Transmitter control code indicator port.
Indicates whether the data at the tx_datain
port is a control or data word. This port is used
with the 8B/10B encoder.
Channel
tx_invpolarity
Input
Available in all modes. Inverts the polarity of
the data to be transmitted at the transmitter
PCS-PMA interface (input to the serializer).
Channel
debug_tx_phase_comp_
fifo_error
Output
Indicates transmitter phase compensation
FIFO overrun or underrun situation.
Channel
Input
125-MHz clock for receiver detect circuitry in
PCI Express (PIPE) mode.
Channel
gxb_powerdown
Input
Transceiver block reset and power down. This
resets and powers down all circuits in the
transceiver block. This does not affect the
REFCLK buffers and reference clock lines.
Transceiver
block
pll_locked
Output
PLL locked indicator for the transmitter PLLs.
Transceiver
block
pll_inclk
Input
Reference clocks for the transmitter PLLs.
Transceiver
block
Input
Calibration clock for the transceiver
termination blocks. This clock supports
frequencies from 10 MHz to 125 MHz.
Transmitter PMA
fixedclk
CMU PMA
Calibration Block
cal_blk_clk
Altera Corporation
May 2008
Device
1–7
Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 6 of 6)
Input/
Output
Port Name
Description
Scope
Input
Power-down signal for the calibration block.
Assertion of this signal may interrupt data
transmission and reception. Use this signal to
re-calibrate the termination resistors if
temperature and/or voltage changes warrant it.
Device
tx_dataout
Output
Transmitter serial output port.
Channel
rx_datain
Input
Receiver serial input port.
Channel
rrefb (1)
Output
Reference resistor port. This port is always
used and must be tied to a 2K-Ω resistor to
ground. This port is highly sensitive to noise.
There must be no noise coupled to this port.
Device
refclk (1)
Input
Dedicated reference clock inputs (two per
transceiver block) for the transceiver. The
buffer structure is similar to the receiver buffer,
but the termination is not calibrated.
Transceiver
block
gxb_enable
Input
Dedicated transceiver block enable pin. If
instantiated, this port must be tied to the
pll_ena input pin. A high level on this signal
enables the transceiver block; a low level
disables it.
Transceiver
block
cal_blk_powerdown
(active low)
External Signals
Note to Table 1–1:
(1)
These are dedicated pins for the transceiver and do not appear in the MegaWizard Plug-In Manager.
Transmitter
Channel
Architecture
This section provides a brief description about sub-blocks within the
transmitter channel (shown in Figure 1–2). The sub-blocks are described
in order from the PLD-transmitter parallel interface to the serial
transmitter buffer.
Figure 1–2. Arria GX Transmitter Channel Block Diagram
Transmitter PCS
PLD
Logic
Array
PIPE
Interface
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
1–8
Arria GX Device Handbook, Volume 1
Reference
Clock
Altera Corporation
May 2008
Transmitter Channel Architecture
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a
reference clock and synthesizes two clocks: a high-speed serial clock to
serialize the data and a low-speed parallel clock used to clock the
transmitter digital logic (PCS) and the PLD-transceiver interface.
The CMU is further divided into three sub-blocks
■
■
■
Transmitter PLL
Central clock divider block
Local clock divider block
Each transceiver block has one transmitter PLL, one central clock divider
and four local clock dividers. One local clock divider is located in each
transmitter channel of the transceiver block.
Figure 1–3 shows a block diagram of the CMU block within each
transceiver block.
Figure 1–3. Clock Multiplier Unit Block Diagram
CMU Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Transmitter Channels [3:2]
Local Clock
TX Clock
Gen Block
Divider Block
Reference clock
from REFCLKs,
Global Clock (1)
Inter-Transceiver
Lines
Transmitter
PLL
Central Clock
Divider
Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Local Clock
TX Clock
Divider Block
Transmitter Channels[1:0]
Gen Block
Note to Figure 1–3:
(1)
The global clock line must be driven from an input pin only.
Altera Corporation
May 2008
1–9
Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Transmitter PLL
The transmitter PLL multiplies the input reference clock to generate the
high-speed serial clock required to support the intended protocol. It
synthesizes a half-rate high-speed serial clock that runs at half the
frequency of the serial data rate for which it is configured; for example,
the transmitter PLL runs at 625 MHz when configured in 1.25-Gbps GIGE
functional mode.
The transmitter PLL output feeds the central clock divider block and the
local clock divider blocks. These clock divider blocks divide the
high-speed serial clock to generate the low-speed parallel clock for the
transceiver PCS logic and the PLD-transceiver interface clock. Depending
on the functional mode for which the transceiver block is configured,
either the central clock divider block or the local clock divider block is
used to generate the low-speed parallel clock.
Figure 1–4 shows a block diagram of the transmitter PLL.
Figure 1–4. Transmitter PLL
Transmitter PLL
/M (1)
To
Inter-Transceiver Block Lines
Dedicated
REFCLK0
up
/2
INCLK
Dedicated
/2
REFCLK1
Inter-Transceiver Block Lines [2:0]
Phase
Frequency
Detector
down
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
/L (1)
High Speed
Serial Clock
Global Clock (2)
Notes to Figure 1–4:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers (clock multiplication factors).
The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
1–10
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May 2008
Transmitter Channel Architecture
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide the reference clock for
the transmitter PLL.
Transmitter PLL Bandwidth Setting
The Arria GX transmitter PLLs in the transceiver offer a programmable
bandwidth setting. The bandwidth of a PLL is the measure of its ability to
track the input clock and jitter. It is determined by the -3dB frequency of
the closed-loop gain of the PLL.
There are three bandwidth settings: high, medium, and low. The high
bandwidth setting filters out internal noise from the VCO because it tracks
the input clock above the frequency of the internal VCO noise. With the
low bandwidth setting, if the noise on the input reference clock is greater
than the internal noise of the VCO, the PLL filters out the noise above the
-3dB frequency of the closed-loop gain of the PLL. The medium
bandwidth setting is a compromise between the high and low settings.
The -3dB frequencies for these settings can vary because of the non-linear
nature and frequency dependencies of the circuit.
Dedicated Reference Clock Input Pins
Each transceiver block has two dedicated reference clock input pins
(REFCLK0 and REFCLK1). The clock route from REFCLK0 and REFCLK1
pins in each transceiver block has an optional pre-divider that divides the
reference clock by two before feeding it to the transmitter PLL (shown in
Figure 1–4). The refclk pre-divider is required if one of the following
conditions is satisfied:
■
■
If the input clock frequency is greater than 325 MHz.
For functional modes with a data rate less than 3.125 Gbps (the data
rate is specified in the what is the data rate? option in the General
tab of the ALT2GXB MegaWizard):
●
If the input clock frequency is greater than or equal to 100 MHz
AND
●
If the ratio of data rate to input clock frequency is 4, 5, or 25
Reference Clock From PLD Global Clock Network
You can drive the reference clock to the transmitter PLL from a PLD
global clock network. If you choose this option, you must drive the global
PLD reference clock line from a non-REFCLK FPGA input pin. You cannot
use a clock generated by PLD logic or an enhanced PLL to drive the
reference clock input to the transmitter PLL.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
1
The Quartus II software requires the following setting for the
non-REFCLK FPGA input pin used to drive the reference clock
input:
Assignment name: Stratix II GX/Arria GX REFCLK coupling and
termination setting
Value: Use as regular IO.
Inter-Transceiver Block Line Routing
The inter-transceiver block lines allow the dedicated reference clock input
pins of one transceiver block to drive the transmitter and receiver PLL of
other transceiver blocks. There are a maximum of three inter-transceiver
block routing lines available in the Arria GX device family. Each
transceiver block can drive one inter-transceiver block line from either
one of its associated reference clock pins. The inter-transceiver block lines
can drive any or all of the transmitter and receiver PLLs in the device. The
inter-transceiver block lines offer flexibility when multiple channels in
separate transceiver blocks share a common reference clock frequency.
The inter-transceiver block lines also drive the reference clock from the
REFCLK pins into the PLD fabric, which reduces the need to drive
multiple clocks of the same frequency into the device. If a divide-by-two
reference clock pre-divider is used, the inter-transceiver block line driven
by the corresponding REFCLK pin cannot be used to clock PLD logic.
The Quartus II software automatically uses the appropriate
inter-transceiver line if the transceiver block is being clocked by the
dedicated reference clock (REFCLK) pin of another transceiver block.
1–12
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May 2008
Transmitter Channel Architecture
Figure 1–5 shows the inter-transceiver block line interface to the
transceivers in the gigabit transceiver blocks and to the PLD.
Figure 1–5. Inter-Transceiver Block Line Routing
Inter-Transceiver Block Line[2]
Transceiver Block 2
Inter-Transceiver Block Line[1]
Transceiver Block 1
Transceiver Block 0
Inter-Transceiver Block Line[0]
Inter-Transceiver Block Lines[2:0]
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Transmitter
PLL
Global Clock (1)
Note to Figure 1–5:
(1)
The global clock line must be driven from an input pin only.
1
Depending on the functional mode, the Quartus II software
automatically selects the appropriate transmitter PLL
bandwidth.
Central Clock Divider Block
The central clock divider block is located in the central block of the
transceiver block (refer to Figure 1–6). This block provides the high-speed
clock for the serializer and the low-speed clock for the transceiver’s PCS
logic within the transceiver block in a four-lane mode.
Figure 1–6 shows the central clock divider block. The /4 and /5 block
generates the slow-speed clock based on the serialization factor. The
high-speed clock goes directly into each channel’s serializer.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Figure 1–6. Central Clock Divider Block
High-Speed Serial Clock (1)
High-Speed
Serial Clock from
Transmitter PLL
Low-Speed Parallel Clock
/4 or /5
Notes to Figure 1–6:
(1)
This feeds the PCS logic.
The central clock divider block feeds all the channels in the transceiver
block when in PIPE ×4 mode. This ensures that the serializer in each
channel outputs the same bit number at the same time and minimizes the
channel-to-channel skew.
Transmitter Local Clock Divider Block
The Tx local clock divider blocks are located in each transmitter channel
of the transceiver block. The purpose of this block is to provide the
high-speed clock for the serializer and the low-speed clock for the
transmitter data path and the PLD for all the transmitters within the
transceiver block. This allows for each of the transmitter channels to run
at different rates. The /n divider offers /1, /2, and /4 factors to provide
capability to reduce base frequency of the driving PLL to half or a quarter
rate. This allows each transmitter channel to run at /1, /2, or /4 of the
original data rate.
Figure 1–7 shows the transmitter local clock divider block.
Figure 1–7. Transmitter Local Clock Divider Block
High-Speed Clock
From Transmitter PLL0
High-Speed
Clock to Transmitter
÷n
High-Speed Clock
From Transmitter PLL1
÷ 4, 5
Slow-Speed
Clock to Transmitter
÷1, 2, or 4
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May 2008
Transmitter Channel Architecture
Each transmitter local clock divider block is operated independently so
there is no guarantee that each channel sends out the same bit at the same
time.
Clock Synthesis
Each PLL in a transceiver block receives a reference clock and generates a
high-speed clock that is forwarded to the clock generator blocks. There
are two types of clock generators:
■
■
Transmitter local clock divider block
Central clock divider block
The transmitter local clock divider block resides in the transmit channel
and synthesizes the high-speed serial clock (used by the serializer) and
slow-speed clock (used by the transmitter’s PCS logic). The central clock
divider block resides in the transceiver block outside the transmit or
receive channels. This block synthesizes the high-speed serial clock (used
by the serializer) and slow-speed clock (used by the transceiver block PCS
logic—transmitter and receiver (if the rate matcher is used)). The PLD
clock is also supplied by the central clock divider block and goes through
the divide-by-two block (located in the central block of the transceiver
block) if the byte serializer/deserializer is used.
The PLLs in the transceiver have half rate voltage-controlled oscillators
(VCOs) that run at half the rate of the data stream. When in the individual
channel mode, the slow-speed clocks for the transmitter logic and the
serializer need only be a /4, or a /5 divider to support a ×8 and ×10
serialization factor. Table 1–2 shows the divider settings for achieving the
available serialization factor.
Table 1–2. Serialization Factor and Divider Settings
Serialization Factor
Divider Setting
×8
/4
×10
/5
In the four-lane mode, the central clock divider block supplies all the
necessary clocks for the entire transceiver block.
The reference clock ranges from 50 MHz to 622.08 MHz. The phase
frequency detector (PFD) has a minimum frequency limit of 50 MHz and
a maximum frequency limit of 325 MHz.
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May 2008
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Arria GX Transceiver Architecture
The refclk pre-divider (/2 ) is available if you use the dedicated
refclk pins for the input reference clock. The refclk pre-divider is
required if one of the following conditions is satisfied:
■
■
If the input clock frequency is greater than 325 MHz.
For functional modes with a data rate less than 3.125 Gbps (the data
rate is specified in the what is the data rate? option in the General
tab of the ALT2GXB MegaWizard):
●
If the input clock frequency is greater than or equal to 100 MHz
AND
●
If the ratio of data rate to input clock frequency is 4, 5, or 25
Transceiver Clock Distribution
This section describes single lane and four-lane configurations for the
high speed and low speed transceiver clocks. All protocol support falls in
the single lane configuration except for the four-lane PIPE mode and
XAUI. The four-lane PIPE mode uses the four-lane configuration.
Single Lane
In a single lane configuration, the PLLs in the central block supply the
high speed clock. Then the clock generation blocks in each transmitter
channel divides down the high speed clock to the frequency needed to
support its particular data rate. In this configuration, two separate clocks
can be supplied through the central block to provide support for two
separate base frequencies. The transmitter clock generation blocks can
divide those down to create additional frequencies for specific data rate
requirements. Each of the four transmitter channels can operate at a
different data rate with the use of the individual transmitter local clock
dividers and both Transmitter PLL0 and Transmitter PLL1.
1
If you instantiate four channels and are not in PIPE ×4, XAUI, or
Basic single-width mode with ×4 clocking, the Quartus II
software automatically chooses the single lane configuration.
Figure 1–8 shows clock distribution for individual channel configuration.
1–16
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May 2008
Transmitter Channel Architecture
Figure 1–8. Clock Distribution for Individual Channel Configuration
TX Channel 3
TX Channel 2
TX Local Clk
Div Block
refclk 0
TXPLL 0
High Speed TXPLL 0 Clock
TXPLL 1
High Speed TXPLL 1 Clock
refclk 1
TXPLL Block
Central Block
TX Channel 1
TX Channel 0
TX Local Clk
Div Block
Four-Lane Mode
In a four-lane configuration (shown in Figure 1–9), the central block
generates the parallel and serial clocks that feed the transmitter channels
within the transceiver. All channels in a transceiver must operate at the
same data rate. This configuration is only supported in PIPE ×4, XAUI
and Basic mode with ×4 clocking.
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Figure 1–9. Clock Distribution for a Four-Lane Configuration Note (1)
Transmitter Channel 3
Transmitter Channel 2
Transmitter PLL0
Reference
clocks (refclks,
Global Clock (1),
IQ Lines)
Transmitter PLL1
Central
Clock Divider
Block
coreclk_out
÷2
Transmitter PLL Block
To PLD
Central Block
Transmitter Channel 1
Transmitter Channel 0
Note to Figure 1–9:
(1)
The global clock line must be driven by an input pin.
Figure 1–10 shows how single transceiver block devices EP1AGX20CF,
EP1AGX35CF, EP1AGX50CF and EP1AGX60CF devices are configured
for PCI-E ×4 mode. When ArriaGX devices are used in ×4 bonded mode
for PCI-E, physical Lane 0 of the transmitter should be connected to
physical Lane 0 of the receiver and vice versa.
Figure 1–10. Two Transceiver Block Device with One ×4 PCI-E Link
Bank 14 (Slave)
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
GXB_TX/RX1
PCIe Lane 1
GXB_TX/RX0
PCIe Lane 0
GXB_TX/RX2
PCIe Lane 2
GXB_TX/RX3
PCIe Lane 3
The two transceiver block devices EP1AGX35DF, EP1AGX50DF, and
EP1AGX60DF support only two PCI-E ×4 links. Fig Figure 1–11shows the
PCI-E ×4 configuration.
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May 2008
Transmitter Channel Architecture
Figure 1–11. Two Transceiver Block Device with Two ×4 PCI-E Links
Bank 13
EP1AGX35DF
EP1AGX50DF
EP1AGX60DF
GXB_TX/RX1
PCIe Lane 5
GXB_TX/RX0
PCIe Lane 4
GXB_TX/RX2
PCIe Lane 6
GXB_TX/RX3
PCIe Lane 7
Bank 14
GXB_TX/RX5
PCIe Lane 1
GXB_TX/RX4
PCIe Lane 0
GXB_TX/RX6
PCIe Lane 2
GXB_TX/RX7
PCIe Lane 3
The three transceiver block devices EP1AGX60EF and EP1AGX90EF
support up to three PCI-E ×4 links. Figure 1–12 shows the PCI-E ×4
configuration.
Figure 1–12. Three Transceiver Block Device with Three ×4 PCI-E Links
Bank 13
EP1AGX60EF
EP1AGX90EF
GXB_TX/RX1
PCIe Lane 1
GXB_TX/RX0
PCIe Lane 0
GXB_TX/RX2
PCIe Lane 2
GXB_TX/RX3
PCIe Lane 3
Bank 14
GXB_TX/RX5
PCIe Lane 1
GXB_TX/RX4
PCIe Lane 0
GXB_TX/RX6
PCIe Lane 2
GXB_TX/RX7
PCIe Lane 3
Bank 15
Altera Corporation
May 2008
GXB_TX/RX9
PCIe Lane 1
GXB_TX/RX8
PCIe Lane 0
GXB_TX/RX10
PCIe Lane 2
GXB_TX/RX11
PCIe Lane 3
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Channel Clock Distribution
This section describes clocking within each channel for:
■
■
Individual channels in Basic (without ×4 clocking enabled), PIPE ×1,
GIGE, Serial RapidIO, and SDI modes
Bonded channels in XAUI, PIPE ×4, and Basic (with ×4 clocking
enabled) modes
Individual Channels Clocking
In individual channel modes, the transmitter logic is clocked by the slow
speed clock from the clock divider block. The transmitter phase
compensation FIFO buffer and the PIPE interface (in PIPE mode) are
clocked by the tx_clkout clock of the channel that is fed back to the
transmitter channel from the PLD logic. Figure 1–13 shows the clock
routing for the transmitter channel.
Figure 1–13. Individual Channel Transmitter Logic Clocking
PLD
Logic
Array
XCVR
PIPE
Interface
Transmitter
Digital
TX
Logic
Phase
Compensation
FIFO
Transmitter Analog Circuits
Byte
Serializer
8B/10B
Encoder
Serializer
÷1, 2
tx_clkout
Central Block
Reference
Clocks
The receiver logic clocking has two clocking methods: one when rate
matching is used and the other when rate matching is not used.
If rate matching is used (PIPE, GIGE, and Basic modes), the receiver logic
from the serializer to the rate matcher is clocked by the recovered clock
from its associated channel. The rest of the logic is clocked by the slow
clock from the clock divider block of its associated channel. The read side
of the phase compensation FIFO buffer and the PIPE interface (for PIPE
mode) is clocked by the tx_clkout fed back through the PLD logic.
Figure 1–14 shows the clocking of the receiver logic with the rate matcher.
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May 2008
Transmitter Channel Architecture
Figure 1–14. Individual Channel Receiver Logic Clocking with Rate Matching
PLD
XCVR
Receiver Analog Circuits
Receiver Digital Logic
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
Deserializer
Rate
Match
FIFO
8B/10B
Decoder
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2
Central
Block
tx_clkout
Reference
Clocks
If rate matching is not used (Basic, SDI, and Serial RapidIO modes), then
the receiver logic is clocked by the recovered clock of its associated
channel (Figure 1–15). The receiver phase compensation FIFO buffer's
read port is clocked by the recovered clock that is fed back from the PLD
logic array as rx_clkout.
Figure 1–15. Individual Channel Receiver Logic Clocking Without Rate Matching
PLD
XCVR
PIPE
rx_clkout
Receiver Analog Circuits
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2
Transmitter Clocking (Bonded Channels)
The clocking in bonded channel modes (Figure 1–16) is different from
that of the individual channel. All the transmitters are synchronized to
the same transmitter PLL and clock divider from the central block. In ×4
bonded channel modes, the central clock divider of the transceiver block
clocks all four channels.
The transmitter logic up to the read port of the transmitter phase
compensation FIFO buffer is clocked by the slow speed clock from the
central block. The PIPE interface and the write port of the transmitter
phase compensation FIFO buffer is clocked by the coreclkout signal
routed from the PLD.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–16. Transmitter Channel Clocking in Transceiver Mode
PLD
Logic
Array
Transmitter
Digital
Logic
XCVR
PIPE
Interface
Transmitter Analog Circuits
TX
Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Serializer
÷1, 2
coreclkout
Central Block
Reference
Clocks
For the receiver logic, in XAUI mode (Figure 1–17), the local recovered
clock feeds the logic up to the write clock of the deskew FIFO buffer. The
recovered clock from Channel 0 feeds the read clock of the deskew FIFO
buffer and the write port of the rate matcher. The slow clock from the
central block feeds the rest of the logic up to the write port of the phase
compensation FIFO buffer. The coreclkout signal routed through the
PLD from the central block feeds the read side of the phase compensation
FIFO buffer.
Figure 1–17. Receiver Channel Clocking in XAUI Mode
XCVR
PLD
Receiver Analog Circuits
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Clock
Recovery
Unit
Deserializer
÷1, 2
Central Block
coreclkout
Reference
Clocks
In the PIPE ×4 mode (Figure 1–18), the local recovered clock feeds the
logic up to the write port of the rate matcher FIFO buffer. The slow clock
from the central block feeds the rest of the logic up to the write port of the
phase compensation FIFO buffer. The coreclkout signal routed
through the PLD from the central block feeds the read side of the phase
compensation FIFO buffer.
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May 2008
Transmitter Channel Architecture
Figure 1–18. Receiver Channel PIPE 4 Mode
XCVR
PLD
Receiver Analog Circuits
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2
Central Block
coreclkout
Reference
Clocks
Transmitter Phase Compensation FIFO
A transmitter phase compensation FIFO (Figure 1–19) is located at each
transmitter channel's logic array interface. It compensates for the phase
difference between the transmitter PCS clock and the local PLD clock.
In individual channel mode (for example, GIGE and Serial RapidIO), the
low-speed parallel clock (or its divide-by-two version if the byte serializer
is used) from the local clock divider block of each channel clocks the read
port of its transmitter phase compensation FIFO buffer. This clock is also
forwarded to the logic array on tx_clkout port of its associated
channel. If the tx_coreclk port is not instantiated, the clock signal on
the tx_clkout port of Channel 0 is automatically fed back to clock the
write port of the transmitter phase compensation FIFOs in all channels
within the transceiver block. If the tx_coreclk port is instantiated, the
clock signal driven on the tx_coreclk port clocks the write port of the
transmitter phase compensation FIFO of its associated channel. You must
ensure that the clock on the tx_coreclk port is frequency locked to the
read clock of the transmitter phase compensation FIFO. For more
information about using the PLD core clock (tx_coreclk), refer to
“PLD-Transceiver Interface Clocking” on page 1–68.
In bonded channel mode (for example, ×4 PCI Express (PIPE)), the low
speed parallel clock from the central clock divider block is divided by
two. This divide-by-two clock clocks the read port of the transmitter
phase compensation FIFO. This clock is also forwarded to the logic array
on the coreclkout port. If the tx_coreclk port is not instantiated, the
clock signal on the coreclkout port is automatically fed back to clock
the write port of transmitter phase compensation FIFO buffers in all
channels within the transceiver block. If the tx_coreclk port is
instantiated, the clock signal driven on the tx_coreclk port clocks the
write port of the transmitter phase compensation FIFO of its associated
channel. You must ensure that the clock on the tx_coreclk port is
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
frequency locked to the read clock of the transmitter phase compensation
FIFO. For more information about using the PLD core clock
(tx_coreclk), refer to “PLD-Transceiver Interface Clocking” on
page 1–68.
Figure 1–19. Transmitter Phase Compensation FIFO
Transmitter Channel
datain[]
From PLD
or PIPE
Interface
Transmitter
Phase
Compensation
FIFO
wrclk
rdclk
dataout[]
To Byte Serializer
or 8B/10B
Encoder
tx_coreclk
/2
CMU
Local/Central Clock
Divider Block
tx_clkout
or
coreclkout
Transmitter Phase Compensation FIFO Error Flag
The write port of the transmitter phase compensation FIFO can be
clocked by either the CMU output clock or its divide-by-two version
(tx_clkout or coreclkout) or a PLD clock. The read port is always
clocked by the CMU output clock or its divide-by-two version. In all
configurations, the write clock and the read clock must have 0 parts per
million (PPM) difference to avoid overrun/underflow of the phase
compensation FIFO.
An optional debug_tx_phase_comp_fifo_error port is available in
all modes to indicate transmitter phase compensation FIFO
overrun/underflow condition. This feature should be used for debug
purposes only if link errors are observed.
Byte Serializer
The byte serializer (Figure 1–20) takes in 16- or 20-bit wide data from the
transmitter phase compensation FIFO buffer and serializes it into 8- or
10-bit wide data at twice the speed. This allows clocking the
PLD-transceiver interface at half the speed as compared to the transmitter
PCS logic. The byte serializer is bypassed in GIGE mode.
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May 2008
Transmitter Channel Architecture
Figure 1–20. Byte Serializer Note (1)
datain[15:0]
dataout[7:0]
Byte Serializer
From Transmitter
Phase Compensation
FIFO
To 8B/10B
Encoder
wrclk
rdclk
CMU
Local/Central Clock
Divider Block
/2
Low-Speed Parallel
Clock
Divide-By-Two Version
of Low-Speed
Parallel Clock
Note to Figure 1–20:
(1)
datain and dataout may also be 20 bits and 10 bits wide, respectively.
After serialization, the byte serializer transmits the least significant byte
(LSByte) first and the most significant byte (MSByte) last.
Figure 1–21 shows byte serializer input and output. datain[15:0] is
the input to the byte serializer from the transmitter phase compensation
FIFO and dataout[7:0] is the output of the byte serializer. datain
may also be 20 bits wide and dataout may be 10 bits wide depending on
implementation.
Figure 1–21. Byte Serializer Operation
D1
datain[15:0]
{8'h02, 8'h03}
D1 LSByte
dataout[7:0]
xxxxxxxxxx
D3
D2
{8'h00, 8'h01}
xxxxxxxxxx
8'h01
xxxx
D1 MSByte
8'h00
D2LSByte
8'h03
D2MSByte
8'h02
In Figure 1–21, the LSByte is transmitted before the MSByte from the
transmitter byte serializer. For input data D1, the output data is D1LSByte
and then D1MSByte.
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May 2008
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Arria GX Transceiver Architecture
8B/10B Encoder
The 8B/10B encoder block takes in 8-bit data from the byte serializer or
transmitter phase compensation FIFO buffer (if the byte serializer is not
used). It generates a 10-bit code group with proper running disparity
from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).
The 10-bit code group is fed to the serializer. The 8B/10B encoder
conforms to the IEEE 802.3 1998 edition standard.
Figure 1–22 shows the 8B/10B conversion format.
f
For additional information about 8B/10B encoding rules, refer to the
Specifications and Additional Information chapter in volume 2 of the
Arria GX Device Handbook.
Figure 1–22. 8B/10B Encoder
7 6 5 4 3 2 1 0
Ctrl
H G F E D C B A
8B-10B Conversion
j
h g f
i
e d c b a
9 8 7 6 5 4 3 2 1 0
MSB
LSB
The 10-bit encoded data output from the 8B/10B encoder is fed to the
serializer that transmits the data from LSB to MSB.
Reset Behavior
The transmitter digital reset (tx_digitalreset) signal resets the
8B/10B encoder. During reset, the running disparity and data registers
are cleared and the 8B/10B encoder outputs a K28.5 pattern from the
RD- column continuously. Once out of reset, the 8B/10B encoder starts
with a negative disparity (RD-) and transmits three K28.5 code groups for
synchronizing before it starts encoding the input data or control
character.
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Transmitter Channel Architecture
Figure 1–23 shows the 8B/10B encoder's reset behavior. When in reset
(tx_digitalreset is high), a K28.5- (K28.5 10-bit code group from the
RD- column) is sent continuously until tx_digitalreset is low. The
transmitter channel pipelining causes some "don't cares (10'hxxx)" until
the first of three K28.5 is sent. User data follows the third K28.5.
Figure 1–23. 8B/10B Encoder Output During Reset
clock
tx_digitalreset
dataout[9:0]
K28.5-
K28.5-
K28.5-
xxx
...
xxx
K28.5-
K28.5+
K28.5-
Dx.y+
Control Code Group Encoding
A control identifier (tx_ctrlenable) input signal specifies whether the
8-bit input character is to be encoded as a control word (Kx.y) or data
word (Dx.y). When tx_ctrlenable is low, the input character is
encoded as data (Dx.y). When tx_ctrlenable is high, the input
character is encoded as a control word (Kx.y). The waveform in
Figure 1–24 shows that the second 0xBC character is encoded as a control
word (K28.5). The rest of the characters are encoded as data (Dx.y).
Figure 1–24. Control Code Group Identification
clock
datain[7..0]
83
78
BC
BC
0F
00
BF
3C
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D28.1
tx_ctrlenable
Code Group
1
Altera Corporation
May 2008
The 8B/10B encoder does not check whether the code group
word entered is one of the 12 valid codes. If you enter an invalid
control code, the resultant 10-bit code group may be encoded as
an invalid code (does not map to a valid Dx.y or Kx.y code
group), or unintended valid Dx.y code group, depending on the
value entered.
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Arria GX Transceiver Architecture
Transmitter Force Disparity
Upon power on or reset, the 8B/10B encoder has a negative disparity and
chooses the 10-bit code from the RD- column. The Transmitter Force
Disparity feature allows altering the running disparity via the
tx_forcedisp and tx_dispval ports.
Two optional ports, tx_forcedisp and tx_dispval, are available in
8B/10B enabled Basic mode. A high value on the tx_forcedisp bit will
change the disparity value of the data to the value indicated by the
associated tx_dispval bit. If the tx_forcedisp bit is low, then
tx_dispval is ignored and the current running disparity is not altered.
Forcing disparity can either maintain the current running disparity
calculations if the forced disparity value (on the tx_dispval bit)
happens to match the current running disparity, or flip the current
running disparity calculations if it does not. If the forced disparity flips
the current running disparity, the downstream 8B/10B decoder may
detect a disparity error that should be tolerated by the downstream
device.
Figure 1–25 shows the current running disparity being altered in Basic
mode by forcing a positive disparity on a negative disparity K28.5. In this
example, a series of K28.5 code groups are continuously being sent. The
stream alternates between a positive ending running disparity (RD+)
K28.5 and a negative ending running disparity (RD-) K28.5 as governed
by the 8B/10B encoder to maintain a neutral overall disparity. The current
running disparity at time n+3 indicates that the K28.5 in time n+4 should
be encoded with a negative disparity. Since the tx_forcedisp is high at
time n+4, and tx_dispval is also high, the K28.5 at time n+4 is encoded
as a positive disparity code group. As the tx_forcedisp is low at n+5,
the K28.5 will take the current running disparity of n+4 and encode the
K28.5 in time n+5 with a negative disparity. If the tx_forcedisp were
driven high at time n+5, that K28.5 would also be encoded with positive
disparity.
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May 2008
Transmitter Channel Architecture
Figure 1–25. Transmitter Force Disparity Feature in Basic Mode
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
BC
BC
BC
BC
BC
BC
BC
BC
RD-
RD+
RD-
RD+
RD+
RD-
RD+
RD-
17C
283
283
17C
283
17C
clock
tx_in[7:0]
tx_ctrlenable
tx_forcedisp
tx_dispval
Current Disparity
tx_out
17C
283
Transmitter Polarity Inversion
The positive and negative signals of a serial differential link might
accidentally be swapped during board layout. Solutions such as a board
re-spin or major updates to the PLD logic can prove expensive. The
transmitter polarity inversion feature is provided to correct this situation.
An optional tx_invpolarity port is available in all modes to
dynamically enable the transmitter polarity inversion feature. A high on
the tx_invpolarity port inverts the polarity of every bit of the 8- or
10-bit input data word to the serializer in the transmitter data path. Since
inverting the polarity of each bit has the same effect as swapping the
positive and negative signals of the differential link, correct data is seen
by the receiver. The tx_invpolarity is a dynamic signal and may
cause initial disparity errors at the receiver of an 8B/10B encoded link.
The downstream system must be able to tolerate these disparity errors.
Figure 1–26 illustrates the transmitter polarity inversion feature in a
10-bit wide data path configuration.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–26. Transmitter Polarity Inversion
0
1
1
0
0
1
1
0
1
tx_invpolarity = HIGH
0
1
0
1
0
1
0
0
1
0
1
Output from transmitter PCS
To Serializer
Input to transmitter PMA
Transmitter Bit Reversal
By default, the Arria GX transmitted bit order is LSBit to MSBit. In Basic
mode, the least significant bit of the 8/10-bit data word is transmitted first
and the most significant bit is transmitted last. The Transmitter Bit
Reversal feature allows reversing the transmitted bit order as MSBit to
LSBit.
If the Transmitter Bit Reversal feature is enabled in Basic mode, the 8-bit
D[7:0] or 10-bit D[9:0] data at the input of the serializer gets rewired
to D[0:7] or D[0:9], respectively. Flipping the parallel data using this
feature and transmitting LSBit to MSBit effectively provides MSBit to
LSBit transmission.
Figure 1–27 illustrates the transmitter bit reversal feature in a Basic mode
10-bit wide data path configuration.
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May 2008
Transmitter Channel Architecture
Figure 1–27. Transmitter Bit Reversal in Basic Mode
D[9]
D[0]
D[8]
D[1]
D[7]
D[2]
D[6]
D[3]
D[5] TX Bit Reversal = Enabled
D[4]
D[4]
D[5]
D[3]
D[6]
D[2]
D[7]
D[1]
D[8]
D[0]
D[9]
Output from transmitter PCS
To Serializer
Input to transmitter PMA
Serializer
The serializer block clocks in 8- or 10-bit data using the low-speed parallel
clock and clocks out serial data using the high-speed serial clock from the
central or local clock divider blocks. The serializer natively feeds the data
LSB to MSB to the transmitter output buffer.
Figure 1–28 shows the serializer block diagram.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–28. Serializer
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
From 8B/10B
Encoder
CMU
Central/
Local Clock
Divider
To Transmitter
Output Buffer
Low-Speed Parallel Clock
High-Speed Serial Clock
Figure 1–29 shows the serial bit order at the serializer output. In this
example, 10'b17C data is serialized and transmitted from LSB to MSB.
Figure 1–29. Serializer Bit Order
Low Speed Parallel Clock
High Speed Serial Clock
datain[9:0]
0101111100
dataout[0]
0 0 1
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1
1010000011
1
1
1 0
1
0
1
1
0
0
0
0 0
1
0
1
Altera Corporation
May 2008
Transmitter Channel Architecture
Transmitter Buffer
The Arria GX transmitter buffers support 1.2-V and 1.5-V pseudo current
mode logic (PCML) up to 3.125 Gbps and can drive 40 inches of FR4 trace
across two connectors. The transmitter buffer (refer to Figure 1–30) has
additional circuitry to improve signal integrity-programmable output
voltage, programmable pre-emphasis circuit, and internal termination
circuitry-and the capability to detect the presence of a downstream
receiver. The Arria GX transmitter buffer supports a common mode of
600 or 700 mV.
Figure 1–30. Transmitter Buffer
50Ω
+VTT-
Programmable
Pre-emphasis
and VOD
Transmitter
Output Pins
50Ω
RX Detect
Programmable Voltage Output Differential
Arria GX devices allow you to customize the differential output voltage
(VOD) to handle different trace lengths, various backplanes, and receiver
requirements (refer to Figure 1–31). You select the VOD from a range
between 400 and 1200 mV, as shown in Table 1–3.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–31. VOD (Differential) Signal Level
Single-Ended Waveform
VA
+VOD
VB
Differential Waveform
+600
+VOD
0-V Differential
VOD
VOD (Differential)
-VOD
-600
= VA – VB
Table 1–3 shows the VOD setting per supply voltage for an on-chip
termination value of 100 Ω .
Table 1–3. VOD Differential Peak to Peak
1.2-V VCC
1.5-V VCC
100-Ω (mV)
100-Ω (mV)
—
400
480
600
640
800
800
1000
960
1200
You set the VOD values in the MegaWizard Plug-In Manager.
The transmitter buffer is powered by either a 1.2-V or a 1.5-V power
supply. You choose the transmitter buffer power (VCCH) of 1.2 V or 1.5 V
through the ALT2GXB MegaWizard Plug-In Manager (the What is the
transmit buffer power (VCCH)? option). The transmitter buffer power
supply in Arria GX devices is transceiver-based. The 1.2 V power supply
supports the 1.2-V PCML standard.
You specify the static VOD settings through the ALT2GXB MegaWizard
Plug-In Manager.
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May 2008
Transmitter Channel Architecture
Programmable Pre-Emphasis
The programmable pre-emphasis module in each transmit buffer boosts
the high frequencies in the transmit data signal, which may be attenuated
in the transmission media. Using pre-emphasis can maximize the data
eye opening at the far-end receiver.
The transmission line’s transfer function can be represented in the
frequency domain as a low pass filter. Any frequency components below
the -3dB frequency pass through with minimal losses. Frequency
components greater than the -3dB frequency are attenuated. This
variation in frequency response yields data dependent jitter and other ISI
effects. By applying pre-emphasis, the high frequency components are
boosted, that is, pre-emphasized. Pre-emphasis equalizes the frequency
response at the receiver so the difference between the low frequency and
high frequency components are reduced, which minimizes the ISI effects
from the transmission medium.
The pre-emphasis requirements increase as data rates through legacy
backplanes increase. The Arria GX transmitter buffer employs a
pre-emphasis circuit with up to 184% of pre-emphasis to correct for losses
in the transmission medium.
You set pre-emphasis settings through a slider menu in the ALT2GXB
MegaWizard Plug-In Manager. Arria GX devices support the first five
settings for first post-tap pre-emphasis. Specify the first post-tap
pre-emphasis settings through the MegaWizard Plug-In Manager.
Transmitter Termination
The Arria GX transmitter buffer includes on-chip differential termination
of 100 Ω . The resistance is adjusted by the on-chip calibration circuit in
the calibration block (refer to “Calibration Blocks” on page 1–82 for more
information), which compensates for temperature, voltage, and process
changes. You can disable the on-chip termination to use external
termination. If you select external termination, the transmitter common
mode is also tri-stated.
You set the transmitter termination setting through a pull-down menu in
the ALT2GXB MegaWizard Plug-In Manager.
PCI Express Receiver Detect
The Arria GX transmitter buffer has a built-in receiver detection circuit
for use in the PIPE mode. This circuit detects if there is a receiver
downstream by sending out a pulse on the common mode of the
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transmitter and monitoring the reflection. This mode requires the
transmitter buffer to be tri-stated (in Electrical Idle mode) and the use of
on-chip termination and a 125 MHz fixedclk signal.
This feature is only available in the PIPE mode. You enable it by setting
the tx_forceelecidle and tx_detectrxloopback ports to 1'b1.
You must set the powerdn port to 2'b10 to place the transmitter in the
PCI-Express P1 power down state. The results of the receiver detect are
encoded on the pipestatus port.
PCI Express Electrical Idle
The Arria GX transmitter buffer supports PCI Express Electrical Idle (or
individual transmitter tri-state). This feature is only active in the PIPE
mode. The tx_forceelecidle port puts the transmitter buffer in
Electrical Idle mode. This port is available in all PCI Express power-down
modes and has a specific use in each mode. Table 1–4 shows the usage in
each power mode.
Table 1–4. Power Mode Usage
Power Mode
P0
Usage
tx_forceelecidle must be asserted. If this signal is deasserted, it indicates that there is
valid data.
P1
tx_forceelecidle must be asserted.
P2
When deasserted, the beacon signal must be transmitted.
Receiver
Channel
Architecture
This section provides a brief description about sub-blocks within the
receiver channel (Figure 1–32). The sub-blocks are described in order
from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 1–32. Receiver Channel Block Diagram
Receiver Digital Logic
RX Phase
Compensation
FIFO
Receiver Analog Circuits
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Reference
Receiver Clock
PLL
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Receiver Channel Architecture
Receiver Buffer
The Arria GX receiver buffers support 1.2-V, 1.5-V, 3.3-V PCML
(pseudo-current mode logic), differential LVPECL and LVDS I/O
standards. The receiver buffers support data rates from 600 Mbps to
3.125 Gbps and are capable of compensating up to 40 inches of FR4 trace
across two connectors. The receiver buffer (Figure 1–33) has additional
circuitry to improve signal integrity, including a programmable
equalization circuit and internal termination circuitry. Through a signal
detect circuit, the receiver buffers can also detect if a signal of predefined
amplitude exists at the receiver.
Figure 1–33. Receiver Buffer
50Ω
Receiver
Input Pins
Programmable
Equalizer
+VTT-
To CRU
50Ω
Signal
Detect
Receiver Termination
The Arria GX receiver buffer has an optional on-chip differential
termination of 100 Ω . You can set the receiver termination resistance
setting using one of these options:
■
Set receiver termination resistance by:
a. Set the receiver termination resistance option in the
MegaWizard Plug-In Manager if on-chip termination is used.
Arria GX supports 100 Ω termination. If the design requires
external receive termination, turn on the Use External Receiver
Termination option.
b.
■
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May 2008
You make the differential termination assignment per pin in the
Quartus II software. (On the Assignments menu, point to
Assignment Organizer, and click Options for Individual
Nodes Only. Then click Stratix II GX GXB Termination Value.)
Verify and set the receiver termination settings before compilation.
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Signal Threshold Detection Circuit
The signal detect feature is supported only in PIPE mode. The signal
detect/loss threshold detector senses if the specified voltage level exists
at the receiver buffer. This detector has a hysteresis response, that filters
out any high frequency ringing caused by inter symbol interference or
high frequency losses in the transmission medium. The
rx_signaldetect signal indicates if a signal conforms to the signal
detection settings. A high level indicates that the signal conforms to the
settings, a low level indicates that the signal does not conform to the
settings.
The signal detect levels are to be determined by characterization. The
signal detect levels may vary because of changing data patterns.
The signal/detect loss threshold detector also switches the receiver
PLL/CRU from lock-to-reference mode to lock-to-data mode. The
lock-to-reference and lock-to-data modes dictate whether the VCO of the
clock recovery unit (CRU) is trained by the reference clock or by the data
stream.
You can bypass the signal/detect loss threshold detection circuit by
choosing the Forced Signal Detect option in the MegaWizard Plug-In
Manager. This is useful in lossy environments where the voltage
thresholds might not meet the lowest voltage threshold setting. Forcing
this signal high enables the receiver PLL to switch from VCO training
based on the reference clock to the incoming data without detecting a
valid voltage threshold.
Receiver Common Mode
Arria GX transceivers support the receiver buffer common mode voltages
of 0.85 V and 1.2 V. Altera recommends selecting 0.85 V as the receiver
buffer common mode voltage.
Programmable Equalization
The Arria GX device offers an equalization circuit in each gigabit
transceiver block receiver channel to increase noise margins and help
reduce the effects of high frequency losses. The programmable equalizer
compensates for the high frequency losses that distort the signal and
reduces the noise margin of the transmission medium by equalizing the
frequency response. There are five equalizer control settings allowed for
an Arria GX device (including a setting with no equalization). In addition
to equalization, Arria GX devices offer an equalizer DC gain option.
There are three legal settings for DC gain. You specify the equalizer
settings (Equalization Settings and DC Gain) through the MegaWizard
Plug-In Manager.
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Receiver Channel Architecture
The transmission line's transfer function can be represented in the
frequency domain as a low pass filter. Any frequency components below
the -3dB frequency pass through with minimal losses. Frequency
components that are greater than the -3dB frequency are attenuated. This
variation in frequency response yields data-dependent jitter and other ISI
effects. By applying equalization, the low frequency components are
attenuated. This equalizes the frequency response such that the delta
between the low frequency and high frequency components is reduced,
which in return minimizes the ISI effects from the transmission medium.
Receiver PLL
Each transceiver channel has its own receiver PLL that is fed by an input
reference clock. The reference clock frequency depends on the functional
mode for which the transceiver channel is configured for. The clock
recovery unit (CRU) controls whether the receiver PLL locks to the input
reference clock (lock-to-reference mode) or the incoming serial data (lockto-data mode). Refer to “Clock Recovery Unit (CRU)” on page 1–41 for
more details on lock-to-reference and lock-to-data modes. The receiver
PLL, in conjunction with the clock recovery unit, generates two clocks: a
high speed serial clock that clocks the deserializer and a low-speed
parallel clock that clocks the receiver’s digital logic.
1
This section only discusses the receiver PLL operation in
lock-to-reference mode. For lock-to-data mode, refer to “Clock
Recovery Unit (CRU)” on page 1–41.
Figure 1–34 shows the block diagram of the receiver PLL in
lock-to-reference mode.
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Figure 1–34. Receiver PLL Block Diagram
/M (1)
rx_pll_locked
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
PFD
rx_cruclk
up
dn
up
dn
Inter-Transceiver Lines[2:0]
Charge
Pump +
Loop
Filter
VCO
/L (1)
Global Clock (2)
rx_freqlocked
rx_locktorefclk
Clock Recovery Unit (CRU) Control
rx_locktodata
High-speed serial recovered clock
rx_datain
Low-speed parallel recovered clock
inactive circuits
active circuits
Notes to Figure 1–34:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers.
The global clock line must be driven from an input pin only.
The reference clock input to the receiver PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD clock network (must be driven directly from an input clock pin
and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Depending on the functional mode, the Quartus II software automatically
selects the appropriate receiver PLL bandwidth.
Clock Synthesis
The maximum input frequency of the receiver PLL's phase frequency
detector (PFD) is 325 MHz. To achieve a reference clock frequency above
this limitation, the divide by 2 pre-divider on the dedicated local REFCLK
path is automatically enabled by the Quartus II software. This divides the
reference clock frequency by a factor of 2, and the /M PLL multiplier
multiplies this pre-divided clock to yield the configured data rate. For
example, in a situation with a data rate of 2500 Mbps and a reference clock
of 500 MHz, the reference clock must be assigned to the REFCLK port
where the 500 MHz reference clock can be divided by 2, yielding a
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Receiver Channel Architecture
250 MHz clock at the PFD. The VCO runs at half the data rate, so the
selected multiplication factor should yield a 1250 MHz high speed clock.
The Quartus II software automatically selects a multiplication factor of ×5
in this case to generate a 1250 MHz clock from the pre-divided 250 MHz
clock.
If the /2 pre-divider is used, the reference clock must be fed by a
dedicated reference clock input (REFCLK) pin. Otherwise, the Quartus II
compiler gives a Fitter error.
The pre-divider and the multiplication factors are automatically set by the
Quartus II software. The MegaWizard Plug-In Manager takes the data
rate input and provides a list of the available reference clock frequencies
that fall within the supported multiplication factors that you can select.
PPM Frequency Threshold Detector
The PPM frequency threshold detector senses whether the incoming
reference clock to the clock recovery unit (CRU) and the PLL VCO of the
CRU are within a prescribed PPM tolerance range. Valid parameters are
62.5, 100, 125, 200, 250, 300, 500, or 1000 PPM. The default parameter, if no
assignments are made, is 1000 PPM. The output of the PPM frequency
threshold detector is one of the variables that assert the rx_freqlocked
signal. Refer to “Automatic Lock Mode” on page 1–42 for more details
regarding the rx_freqlocked signal.
Receiver Bandwidth Type
The Arria GX receiver PLL in the CRU offers a programmable bandwidth
setting. The PLL bandwidth is the measure of the PLL’s ability to track the
input data and jitter. The bandwidth is determined by the -3dB frequency
of the closed-loop gain of the PLL.
A higher bandwidth setting helps reject noise from the VCO and power
supplies. A low bandwidth setting filters out more high frequency data
input jitter.
Valid receiver bandwidth settings are low, medium, or high. The -3dB
frequencies for these settings vary because of the non-linear nature and
data dependencies of the circuit. You can vary the bandwidth to adjust
and customize the performance on specific systems.
Clock Recovery Unit (CRU)
The CRU (Figure 1–35) in each transceiver channel recovers the clock
from the received serial data stream. You can set the CRU to lock to the
received serial data phase and frequency (lock-to-data mode) to eliminate
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any clock-to-data skew or to keep the receiver PLL locked to the reference
clock (lock-to-reference mode). The switch between lock-to-data and
lock-to-reference modes can be done automatically or manually. The
CRU, in conjunction with the receiver PLL, generates two clocks: a
high-speed serial recovered clock that feeds the deserializer and a
low-speed parallel recovered clock that feeds the receiver’s digital logic.
Figure 1–35. Clock Recovery Unit
/M
rx_pll_locked
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
PFD
rx_cruclk
up
dn
up
dn
Inter-Transceiver Lines[2:0]
CP+LF
VCO
/L
Global Clock (2)
rx_freqlocked
rx_locktorefclk
Clock Recovery Unit (CRU) Control
rx_locktodata
High-Speed Serial Recovered Clock
rx_datain
Low-Speed Parallel Recovered Clock
inactive circuits
active circuits
Notes to Figure 1–35:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers.
The global clock line must be driven from an input pin only.
Automatic Lock Mode
After coming out of reset in automatic lock mode, the CRU initially sets
the receiver PLL to lock to the input reference clock (lock-to-reference
mode). After the receiver PLL locks to the input reference clock, the CRU
automatically sets it to lock to the incoming serial data (lock-to-data
mode) when the following two conditions are met:
■
■
The receiver PLL output clock is within the configured PPM
frequency threshold setting with respect to its reference clock
(frequency locked)
The reference clock and receiver PLL output clock are phase matched
within approximately 0.08 UI (phase locked)
When the receiver PLL and CRU are in lock-to-reference mode, the PPM
detector and the phase detector circuits monitor the relationship of the
reference clock to the receiver PLL VCO output. If the frequency
difference is within the configured PPM setting (as set in the MegaWizard
Plug-In Manager) and the phase difference is within 0.08 UI, the CRU
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Receiver Channel Architecture
switches to lock-to-data mode. The switch from lock-to-reference to
lock-to-data mode is indicated by the assertion of the rx_freqlocked
signal.
In lock-to-data mode, the receiver PLL uses a phase detector to keep the
recovered clock phase-matched to the data. If the PLL does not stay
locked to data due to frequency drift or severe amplitude attenuation, the
CRU switches back to lock-to-reference mode to lock the PLL to the
reference clock. In automatic lock mode, the following condition forces
the CRU to fall out of lock-to-data mode:
The CRU PLL is not within the configured PPM frequency threshold
setting with respect to its reference clock.
The switch from lock-to-data to lock-to-reference mode is indicated by the
de-assertion of rx_freqlocked signal.
When the CRU is in lock-to-data mode (rx_freqlocked is asserted), it
tries to phase-match the PLL with the incoming data. As a result, the
phase of the PLL output clock may differ from the reference clock due to
which rx_pll_locked signal might get de-asserted. You should ignore
the rx_pll_locked signal when the rx_freqlocked signal is asserted
high.
Manual Lock Mode
Two optional input pins (rx_locktorefclk and rx_locktodata)
allow you to control whether the CRU PLL automatically or manually
switches between lock-to-reference mode and lock-to-data mode. This
enables you to bypass the default automatic switchover circuitry if either
rx_locktorefclk or rx_locktodata is instantiated.
When the rx_locktorefclk signal is asserted, the CRU forces the
receiver PLL to lock to the reference clock. When the rx_locktodata
signal is asserted, the CRU forces the receiver PLL to lock-to-data. When
both signals are asserted, the rx_locktodata signal takes precedence
over the rx_locktorefclk signal, forcing the receiver PLL to
lock-to-data.
The PPM threshold frequency detector and phase relationship detector
reaction times may be too long for some applications. You can manually
control the CRU to reduce PLL lock times using the rx_locktorefclk
and rx_locktodata ports. Using the manual mode may reduce the
time it takes for the CRU to switch from lock-to-reference mode to
lock-to-data mode. You can assert the rx_locktorefclk to initially
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train the PLL to the reference clock. Once the receiver PLL locks to the
reference clock, you can assert the rx_locktodata signal to force the
PLL to lock to the incoming data.
When the rx_locktorefclk signal is asserted high, the
rx_freqlocked signal does not have any significance and is always
driven low, indicating that the CRU is in lock-to-reference mode. When
the rx_locktodata signal is asserted high, the rx_freqlocked signal
is always driven high, indicating that the CRU is in lock-to-data mode. If
both signals are de-asserted, the CRU is in automatic lock mode.
Table 1–5 shows a summary of the control signals.
Table 1–5. CRU User Control Lock Signals
rx_locktorefclk
rx_locktodata
CRU Mode
1
0
Lock-to-reference clock
x
1
Lock to data
0
0
Automatic
Deserializer
The deserializer block clocks in serial input data from the receiver buffer
using the high-speed serial recovered clock and deserializes it into 8- or
10-bit parallel data using the low-speed parallel recovered clock. It feeds
the deserialized data to the word aligner as shown in Figure 1–36.
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Figure 1–36. Deserializer
Received Data
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
Clock
Recovery
Unit
To Word
Aligner
High-Speed Serial Recovered Clock
Low-Speed Parallel Recovered Clock
Figure 1–37 shows the serial bit order of the deserializer block input and
the parallel data output of the deserializer block. A serial stream
(0101111100) is deserialized to a value 10'h17C. The serial data is assumed
to be received LSB to MSB.
Figure 1–37. Deserializer Bit Order
Low-Speed Parallel Clock
High-Speed Serial Clock
datain
dataout
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May 2008
0 0 1
1
1
1
1 0
1
0
1
1
0
0
0
0 0
0101111100
1
0
1
1010000011
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Receiver Polarity Inversion
The positive and negative signals of a serial differential link might be
accidentally swapped during board layout. Solutions such as a board
re-spin or major updates to the PLD logic can prove expensive. The
receiver polarity inversion feature is provided to correct this situation.
An optional rx_invpolarity port is available in all modes to
dynamically enable the receiver polarity inversion feature. A high on the
rx_invpolarity port inverts the polarity of every bit of the 8- or 10-bit
input data word to the word aligner in the receiver data path. Since
inverting the polarity of each bit has the same effect as swapping the
positive and negative signals of the differential link, correct data is seen
by the receiver. The rx_invpolarity is a dynamic signal and may
cause initial disparity errors in an 8B/10B encoded link. The downstream
system must be able to tolerate these disparity errors.
The receiver polarity inversion feature is different from the PCI Express
(PIPE) 8B/10B polarity inversion feature. The receiver polarity inversion
feature inverts the polarity of the data bits at the input of the word aligner.
The PCI Express (PIPE) 8B/10B polarity inversion feature inverts the
polarity of the data bits at the input of the 8B/10B decoder and is
available only in PCI Express (PIPE) mode. Enabling the generic receiver
polarity inversion and the PCI Express (PIPE) 8B/10B polarity inversion
simultaneously is not allowed in PCI Express (PIPE) mode.
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Figure 1–38 illustrates the receiver polarity inversion feature.
Figure 1–38. Receiver Polarity Inversion
0
1
1
0
0
1
1
0
1
rx_invpolarity = High
To Word Aligner
0
1
0
1
0
1
0
0
1
0
1
Input to Word Aligner
Output from Deserializer
Word Aligner
The word aligner (refer to Figure 1–39) clocks in received data from the
deserializer using the low-speed recovered clock. It restores the word
boundary of the upstream transmitter based on the pre-defined word
alignment character for the selected protocol. In addition to restoring the
word boundary, the word aligner also implements a synchronization
state machine in all functional modes to achieve lane synchronization.
Figure 1–39 shows the block diagram for the word aligner block.
Figure 1–39. Word Aligner
datain
bitslip
Word
Aligner
enapatternalign
dataout
syncstatus
patterndetect
clock
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The word aligner consists of four sub-modules:
■
■
■
■
Aligner block
Pattern detect block
Manual bit-slip block
Run-length checker
There are two modes in which the word aligner works: basic mode and
automatic synchronization state machine mode. The following sections
explain each of the blocks in each mode of operation. The word aligner
cannot be bypassed and must be used. However, you can use the
rx_enapatternalign port to set the word alignment to not align to the
pattern.
Basic Mode
In basic mode, there are three blocks active in the word aligner:
■
■
■
Pattern detector
Manual word aligner
Automatic synchronization state machine
The pattern detector detects if the pattern exists in the current word
boundary. The manual alignment identifies the alignment pattern across
the byte boundaries and aligns to the correct byte boundary. The
synchronization state machine detects the number of alignment patterns
and good code groups for synchronization and goes out of
synchronization if code group errors (bad code groups) are detected.
Figure 1–40 and Table 1–6 show the supported alignment modes when
basic mode is selected.
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Figure 1–40. Word Aligner Components in Basic Mode
Basic Mode
Manual
Alignment Mode
Pattern Detector
10-Bit
Mode
Bit-Slip
Mode
7-Bit
Mode
Synchronization
State Machines
7-Bit
Mode
10-Bit
Mode
Basic Mode
10-Bit
GIGE
Mode
PIPE Mode
16-Bit
XAUI
Mode
Table 1–6. Word Alignment Modes
Word Alignment
Mode
Effective Mode
Synchronization
state machine
PCI Express, XAUI, GIGE, Serial
RapidIO, or Basic
Automatically controlled to
adhere to the specified
standard or by user entered
parameter
rx_syncstatus
rx_patterndetect
Manual 7- and
10-bit alignment
mode
Alignment to detected pattern
when allowed by the
rx_enapatternalign signal
rx_enapatternalign
rx_syncstatus
rx_patterndetect
Manual
bit-slipping
alignment mode
Manual bit slip controlled by the
PLD logic array
rx_bitslip
rx_patterndetect
Control Signals
Status Signals
Pattern Detector Module
The pattern detector matches a pre-defined alignment pattern to the
current byte boundary. When the pattern detector locates the alignment
pattern, the optional rx_patterndetect signal is asserted for the
duration of one clock cycle to signify that the alignment pattern exists in
the current word boundary. The pattern detector module only indicates
that the signal exists and does not modify the word boundary.
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Modification of the word boundary is discussed in the sections “Manual
Alignment Modes” on page 1–51 and “Synchronization State Machine
Mode” on page 1–55.
In the MegaWizard, you can program a 7-bit or a 10-bit pattern for the
pattern detector to recognize. The pattern used for pattern matching is
automatically derived from the word alignment pattern in the
MegaWizard. For the 7-bit and 10-bit patterns, the actual alignment
pattern specified in the MegaWizard and its complement are checked.
Table 1–7 shows the supported alignment patterns.
Table 1–7. Supported Alignment Patterns
Pattern Detect Mode
Supported Protocols
Pattern Checked
7 bit
Basic, GIGE (enhanced
only)
Actual and complement
10 bit
Basic, XAUI, GIGE, Serial Actual and complement
RapidIO, and PIPE
In 8B/10B encoded data, actual and complement pattern indicates
positive and negative disparities.
7-Bit Pattern Mode
In the 7-bit pattern detection mode (use this mode with 8B/10B code), the
pattern detector matches the seven LSBs of the 10-bit alignment pattern,
which you specified in your ALT2GXB custom megafunction variation, in
the current word boundary. Both positive and negative disparities are
also checked in this mode.
The 7-bit pattern mode can mask out the three MSBs of the data, which
allows the pattern detector to recognize multiple alignment patterns. For
example, in the 8B/10B encoded data, a /K28.5/ (b'0011111010), /K28.1/
(b'0011111001), and /K28.7/ (b'0011111000) share seven common LSBs.
Masking the three MSBs allows the pattern detector to resolve all three
alignment patterns and indicate them on the rx_patterndetect port.
In 7-bit pattern mode, the word aligner still aligns to a 10 bit word
boundary. The specified 7-bit pattern forms the least significant seven bits
of the 10-bit word.
10-Bit Pattern Mode
In the 10-bit pattern detection mode (use this mode with 8B/10B code),
the module matches the 10-bit alignment pattern you specified in your
ALT2GXB custom megafunction variation with the data and its
complement in the current word boundary. Both positive and negative
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disparities are checked by the pattern checker in this mode. For example,
if you specify a /K28.5/ (b'0011111010) pattern as the comma,
rx_patterndetect is asserted if b'0011111010 or b'1100000101 is
detected in the incoming data.
Manual Alignment Modes
The word aligner has two manual alignment modes (7- and 10-bits) when
the transceiver data path is in Basic mode.
7-bit Alignment Mode
In the 7-bit alignment mode (use the 8B/10B encoded data with this
mode), the module looks for the 7-bit alignment pattern you specified in
the MegaWizard Plug-In Manager in the incoming data stream. The 7-bit
alignment mode is useful because it can mask out the three most
significant bits of the data, which allows the word aligner to align to
multiple alignment patterns. For example, in the 8B/10B encoded data, a
/K28.5/ (b'0011111010), /K28.1/ (b'0011111001), and /K28.7/
(b'0011111000) share seven common LSBs. Masking the three MSBs allows
the word aligner to resolve all three alignment patterns synchronized to
it. The word aligner places the boundary of the 7-bit pattern in the LSByte
position with bit positions [0..7]. The true and complement of the patterns
is checked.
Use the rx_enapatternalign port to enable the 7-bit manual word
alignment mode. When the rx_enapatternalign signal is high, the
word aligner detects the specified alignment patterns and realigns the
byte boundary if needed. The rx_syncstatus port is asserted for one
parallel clock cycle to signify that the word boundary was detected across
the current word boundary and has synchronized to the new boundary,
if a rising edge was detected previously on the rx_enapatternalign
port. You must differentiate if the acquired byte boundary is correct,
because the 7-bit pattern can appear between word boundaries. For
example, in the standard 7-bit alignment pattern 7'b1111100, if a K28.7 is
followed by a K28.5, the 7-bit alignment pattern appears on K28.7,
between K28.7 and K28.5, and also again in K28.5 (refer to Figure 1–41).
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Figure 1–41. Cross Boundary 7-Bit Comma When /K28.7 is Followed by /K28.5
K28.7
0
0
1
1
1
1
K28.5
1
0
0
0
7-bit comma-
0
0
1
1
1
1
1
0
1
0
7-bit comma7-bit comma+
Manual 10-Bit Alignment Mode
You can configure the word aligner to align to a 10-bit word boundary.
The internal word alignment circuitry shifts to the correct word boundary
if the alignment pattern specified in the pattern detector is detected in the
data stream.
The rx_enapatternalign port enables the word alignment in the
manual 10-bit alignment mode. When the rx_enapatternalign signal
is high, the word aligner detects the specified alignment pattern and
realigns the byte boundary if necessary. The rx_syncstatus port is
asserted for one parallel clock cycle to signify that the word boundary has
been detected across the word boundary and has synchronized to the
new boundary.
The rx_enapatternalign signal is held high if the alignment pattern
is known to be unique and does not appear across the byte boundaries of
other data. For example, if an 8B/10B encoding scheme guarantees that
the /K28.5/ code group is a unique pattern in the data stream, the
rx_enapatternalign port is held at a constant high.
If the alignment pattern can exist between word boundaries, the
rx_enapatternalign port must be controlled by the user logic in the
PLD to avoid false word alignment. For example, assume that 8B/10B is
used and a /+D19.1/ (b'110010 1001) character is specified as the
alignment pattern. In this case, a false word boundary is detected if a
/-D15.1/ (b'010111 1001) is followed by a /+D18.1/ (b'010011 1001). Refer
to Figure 1–42.
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Figure 1–42. False Word Boundary Alignment if Alignment Pattern Exists Across Word Boundaries, Basic
Mode
+D18.1
- D15.1
…..
0
1
0
1
1
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
…..
+D19.1
In this example, the rx_enapatternalign signal is deasserted after the
word aligner locates the initial word alignment to prevent false word
boundary alignment. When the rx_enapatternalign signal is
deasserted, the current word boundary is locked even if the alignment
pattern is detected across different boundaries. In this case, the
rx_syncstatus acts as a re-synchronization signal to signify that the
alignment pattern was detected, but the boundary is different than the
current boundary. You must monitor this signal and reassert the
rx_enapatternalign signal if realignment is desired.
Figure 1–43 shows an example of how the word aligner signals interact in
10-bit alignment mode. In this example, a /K28.5/ (10'b0011111010) is
specified as the alignment pattern. The rx_enapatternalign signal is
held high at time n, so alignment occurs whenever an alignment pattern
exists in the pattern. The rx_patterndetect signal is asserted for one
clock cycle to signify that the pattern exists on the re-aligned boundary.
The rx_syncstatus signal is also asserted for one clock cycle to signify
that the boundary has been synchronized. At time n + 1, the
rx_enapatternalign signal is deasserted to instruct the word aligner
to lock the current word boundary.
The alignment pattern is detected at time n + 2, but it exists on a different
boundary than the current locked boundary. The bit orientation of the
Arria GX device is LSB to MSB, so the alignment pattern exists across time
n + 2 and n + 3 (refer to Figure 1–43). In this condition the
rx_patterndetect remains low because the alignment pattern does
not exist on the current word boundary, but the rx_syncstatus signal
is asserted for one clock cycle to signify a resynchronization condition.
This means that the alignment pattern has been detected across another
word boundary.
The user logic design in the PLD must decide whether or not to assert the
rx_enapatternalign to reinitiate the word alignment process. At time
n + 5 the rx_patterndetect signal is asserted for one clock cycle to
signify that the alignment pattern has been detected on the current word
boundary.
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Figure 1–43. Word Aligner Symbol Interaction in 10-Bit Manual Alignment Mode
n
n+1
n+2
n+3
n+4
n+5
1111001010
1000000101
111110000
0101111100
rx_clkout
rx_dataout[10..0]
111110000
0101111100
111110000
rx_enapatternalign
rx_patterndetect
rx_syncstatus
Manual Bit-Slip Alignment Mode
You can also achieve word alignment by enabling the manual bit-slip
option in the MegaWizard Plug-In Manager. With this option enabled, the
transceiver shifts the word boundary MSB to LSB one bit every parallel
clock cycle. The transceiver shifts the word boundary every time the bitslipping circuitry detects a rising edge of the rx_bitslip signal. At each
rising edge of the rx_bitslip signal, the word boundary slips one bit.
The bit that arrives at the receiver first is skipped. When the word
boundary matches the alignment pattern you specified in the
MegaWizard Plug-In Manager, the rx_patterndetect signal is
asserted for one clock cycle. You must implement the logic in the PLD
logic array to control the bit-slip circuitry.
The bit slipper is useful if the alignment pattern changes dynamically
when the Arria GX device is in user mode. You can implement the
controller in the logic array, so you can build a custom controller to
dynamically change the alignment pattern without needing to reprogram
the Arria GX device.
Figure 1–44 shows an example of how the word aligner signals interact in
the manual bit slip alignment mode. For this example, 8'b00111100 is
specified as the alignment pattern and an 8'b11110000 value is held at the
rx_datain port.
Every rising edge on the rx_bitslip port causes the rx_dataout data
to shift one bit from the MSB to the LSB by default. This is shown at time
n + 2 where the 8'b11110000 data is shifted to a value of 8'b01111000. At
this state the rx_patterndetect signal is held low because the
specified alignment pattern does not exist in the current word boundary.
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The rx_bitslip is disabled at time n + 3 and re-enabled at time n + 4.
The output of the rx_dataout now matches the specified alignment
pattern, thus the rx_patterndetect signal is asserted for one clock
cycle. At time n + 5, the rx_patterndetect signal is still asserted
because the alignment pattern still exists in the current word boundary.
Finally, at time n + 6 the rx_dataout boundary is shifted again and the
rx_patterndetect signal is deasserted to signify that the word
boundary does not contain the alignment pattern.
Figure 1–44. Word Aligner Symbol Interaction in Manual Bit-Slip Mode
n
n+1
n+2
n+3
n+4
n+5
n+6
rx_clkout
00001111
rx_datain
rx_dataout[7..0]
11110000
01111000
00111100
00011110
rx_bitslip
rx_patterndetect
Synchronization State Machine Mode
You can choose to have the link synchronization handled by a state
machine. Unlike the manual alignment mode where there is no built-in
hysteresis to go into or fall out of synchronization, the synchronization
state machine offers automatic detection of a valid number of alignment
patterns and synchronization and detection of code group errors for
automatically falling out of synchronization. The synchronization state
machine is available in the Basic, XAUI, GIGE, and PIPE modes. For the
XAUI, GIGE, and PIPE modes, the number of alignment patterns,
consecutive code groups, and bad code groups are fixed. You must use
the 8B/10B code for the synchronization state machine. In XAUI, GIGE,
and PIPE modes, the 8B/10B encoder/decoder is embedded in the
transceiver data path. In Basic mode, you can configure the MegaWizard
Plug-In Manager to either use or bypass the 8B/10B encoder/decoder in
the transceiver. If the synchronization state machine is enabled and the
8B/10B encoder/decoder is bypassed, the 8B/10B encoder/decoder logic
must be implemented outside the transceiver as a requirement for using
the synchronization state machine.
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In Basic mode, you can configure the state machine to suit a variety of
standard and custom protocols. In the MegaWizard Plug-In Manager, you
can program the number of alignment patterns to acquire link
synchronization. You can program the number of bad code groups to fall
out of synchronization. You can program the number of good code
groups to negate a bad code group. You enter these values in the
MegaWizard Plug-In Manager. The rx_syncstatus port indicates the
link status. A high level indicates link synchronization is achieved, a low
level indicates that synchronization has not yet been achieved or that
there were enough code group errors to fall out of synchronization.
Figure 1–45 shows a flowchart of the synchronization state machine.
Figure 1–45. Word Aligner Synchronization State Machine Flow Chart
Loss of Sync
Data= Comma
Data= !Valid
Comma Detect
if Data == comma
kcntr++
else
kcntr=kcntr
Data=valid;
kcntr<3
kcntr = 3
Synchronized
Data=valid
Data= !Valid
ecntr = 17
Synchronized Error
Detect
if Data == !valid
ecntr++
gcntr=0
else if gcntr==16
ecntr- gcntr=0
else
gcntr++
ecntr = 0
The maximum value for the number of valid alignment patterns and
good code groups is 256. The maximum value of invalid or bad code
groups to fall out of synchronization is 8. For example, if 3 is set for the
number of good code groups, then when 3 consecutive good code groups
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are detected after a bad code group, the effect of the bad code group on
synchronization is negated. This does not negate the bad code group that
actually triggers the loss of synchronization. To negate a loss of
synchronization, the protocol defined number of alignment patterns
must be received.
When either XAUI or GIGE mode is used, the synchronization and word
alignment is handled automatically by a built-in state machine that
adheres to either the IEEE 802.3ae or IEEE 802.3 synchronization
specifications, respectively. If you specify either standard, the alignment
pattern is automatically defaulted to /K28.5/ (b'0011111010).
When you specify the XAUI protocol, code-group synchronization is
achieved upon the reception of four /K28.5/ commas. Each comma can
be followed by any number of valid code groups. Invalid code groups are
not allowed during the synchronization stage. When code-group
synchronization is achieved the optional rx_syncstatus signal is
asserted.
f
For more information about the operation of the synchronization phase,
refer to clause 47-48 of the IEEE P802.3ae standard or XAUI mode in the
Arria GX Transceiver Protocol Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook.
If you specify the GIGE protocol, code-group synchronization is achieved
upon the reception of three consecutive ordered sets. An ordered set
starts with the /K28.5/ comma and can be followed by an odd number of
valid data code groups. Invalid code groups are not allowed during the
reception of three ordered-sets. When code-group synchronization is
achieved, the optional rx_syncstatus signal is asserted.
In PIPE mode, lane synchronization is achieved when the word aligner
sees four good /K28.5/ commas and 16 good code groups. This is
accomplished through the reception of four good PCI Express training
sequences (TS1 or TS2). The PCI-Express fast training sequence (FTS) can
also be used to achieve lane or link synchronization, but requires at least
five of these training sequences. The rx_syncstatus signal is asserted
when synchronization is achieved and is deasserted when the word
aligner receives 23 code group errors.
Run Length Checker
The programmable run-length violation circuit resides in the word
aligner block and detects consecutive 1s or 0s in the data. If the data
stream exceeds the preset maximum number of consecutive 1s or 0s, the
violation is signified by the assertion of the rx_rlv signal.
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This signal is not synchronized to the parallel data and appears in the
logic array earlier than the run-length violation data. To ensure that the
PLD can latch this signal in systems where there are frequency variations
between the recovered clock and the PLD logic array clock, the rx_rlv
signal is asserted for a minimum of two clock cycles. The rx_rlv signal
may be asserted longer, depending on the run-length of the received data.
The run-length violation circuit detects up to a run length of 128 (for an
8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). The
settings are in increments of 4 or 5 for the 8-bit or 10-bit deserialization
factors, respectively.
Receiver Bit Reversal
By default, the Arria GX receiver assumes an LSB to MSB transmission. If
the transmission order is MSB to LSB, then the receiver will put out the
bit-flipped version of the data on the PLD interface. The Receiver Bit
Reversal feature is available to correct this situation.
The Receiver Bit Reversal feature is available only in Basic mode. If the
Receiver Bit Reversal feature is enabled, the 10-bit data D[9:0] at the
output of the word aligner gets rewired to D[0:9]. Flipping the parallel
data using this feature allows the receiver to put out the correctly
bit-ordered data on the PLD interface in case of MSBit to LSBit
transmission.
Because the receiver bit reversal is done at the output of the word aligner,
a dynamic bit reversal would also require a reversal of word alignment
pattern. As a result, the Receiver Bit Reversal feature is dynamic only if
the receiver uses manual bit-slip alignment mode (no word alignment
pattern). The Receiver Bit Reversal feature is static in all other Basic mode
configurations and can be enabled through the MegaWizard Plug-In
Manager. In configurations where this feature is dynamic, an
rx_revbitordwa port is available to control the bit reversal
dynamically. A high on the rx_revbitordwa port reverses the bit order
at the input of the word aligner.
Figure 1–46 illustrates the receiver bit reversal feature in Basic 10-bit wide
data path configuration.
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Figure 1–46. Receiver Bit Reversal in Basic Mode
D[9]
D[0]
D[8]
D[1]
D[7]
D[2]
D[6]
D[3]
D[5]
RX Bit Reversal = Enabled
D[4]
D[4]
D[5]
D[3]
D[6]
D[2]
D[7]
D[1]
D[8]
D[0]
D[9]
Output of Word Aligner before
RX bit reversal
Output of Word Aligner after RX
bit reversal
Channel Aligner (Deskew)
The channel aligner is automatically used when implementing the XAUI
protocol to ensure that the channels are aligned with respect to each other.
The channel aligner uses a 16-word deep FIFO buffer and is available
only in the XAUI mode.
f
For additional information about the Channel Aligner block, refer to the
Arria GX Transceiver Protocol Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook.
Rate Matcher
In asynchronous systems, the upstream transmitter and the local receiver
may be clocked with independent reference clock sources. Frequency
differences in the order of a few hundred PPM can potentially corrupt the
data at the receiver. The rate matcher compensates for small clock
frequency differences between the upstream transmitter and the local
receiver clocks by inserting or removing skip characters or ordered-sets
from the inter-packet gap (IPG) or idle streams. It inserts a skip character
or ordered-set if the local receiver is running a faster clock than the
upstream transmitter. It deletes a skip character or ordered-set if the local
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receiver is running a slower clock than the upstream transmitter. The rate
matcher is available in PCI Express (PIPE), GIGE, XAUI, and Basic
functional modes.
The rate matcher consists of a 20-word-deep FIFO buffer and necessary
logic to detect and perform the insertion and deletion functions. The write
port of the rate matcher FIFO is clocked by the low-speed parallel
recovered clock. The read port is clocked by the low-speed parallel clock
from the CMU central or local clock divider block (Figure 1–47).
Figure 1–47. Rate Matcher
dataout[9:0]
datain[9:0]
Rate Matcher
To 8B/10B
Decoder
From Word Aligner
wrclk
Low-Speed Parallel
Recovered Clock
from CRU
f
rdclk
Low-Speed Parallel
CMU Clock
CMU
Local/Central Clock
Divider Block
For information about the rate matcher in PIPE, GIGE, and XAUI modes,
refer to the Arria GX Transceiver Protocol Support and Additional Features
chapter in volume 2 of the Arria GX Device Handbook.
Basic Mode General Rate Matching
In Basic mode, the rate matcher supports up to 300 PPM differences
between the upstream transmitter and the receiver. The rate matcher
looks for the skip ordered set (SOS), which is a /K28.5/ comma followed
by three programmable neutral disparity skip characters (for example,
/K28.0/). For general rate matching, you can customize the SOS to
support a variety of protocols, including custom protocols. The SOS must
contain a valid control code group (Kx.y), followed by any neutral
disparity skip code group (any Kx.y or Dx.y of neutral disparity, for
example, K28.0). The rate matcher deletes or inserts skip characters when
necessary to prevent the rate matching FIFO buffer from overflowing or
underflowing.
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The rate matcher in Basic mode can delete any number of skip characters
as necessary in a cluster as long as there are skip characters to delete.
There are no restrictions regarding deleting more than one skip character
in a cluster of skip characters. Figure 1–48 shows an example of a Basic
mode rate matcher deletion of two skip characters. Although the skip
characters are programmable, the /K28.0/ control group is used for
illustration purposes.
Figure 1–48. Basic Mode Deletion of Two Skip Characters
clock
datain
K28.5
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
dataout
K28.5
K28.0
Dx.y
K28.5
K28.0
K28.0
Dx.y
Dx.y
Two Skips Deleted
The rate matcher inserts skip characters as required for rate matching. For
a given skip ordered set, the rate matcher inserts skip characters so that
the total number of consecutive skip characters does not exceed five at the
output of the rate matching FIFO buffer. Figure 1–49 shows an example
where a skip character insertion is made on the second set of skip ordered
sets because the first set has the maximum number of skip characters.
Figure 1–49. Basic Mode Insertion of a Skip Character
One Skip Inserted
One Skip Inserted
clock
datain
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
Dx.y
dataout
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
The Arria GX rate matcher in Basic mode has FIFO buffer overflow and
underflow protection. In the event of a FIFO buffer overflow the rate
matcher deletes any data after the overflow condition to prevent FIFO
buffer pointer corruption until the rate matcher is not full. In an
underflow condition, the rate matcher inserts 9'h1FE (/K30.7) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer
gracefully exits the overflow and underflow condition without requiring
a FIFO buffer reset.
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8B/10B Decoder
The 8B/10B decoder takes in 10-bit data from the rate matcher and
decodes it into 8-bit data + 1-bit control identifier, thereby restoring the
original transmitted data at the receiver. The decoded data is fed to either
the byte deserializer or the receiver phase compensation FIFO buffer
(depending on protocol). The 8B/10B decoder conforms to IEEE 802.3
1998 edition standards.
Figure 1–50 shows a 10-bit code group decoded to an 8-bit data and a 1-bit
control indicator.
Figure 1–50. 10-Bit to 8-Bit Conversion
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
MSB Received Last
LSB Received First
8B/10B Conversion
ctrl
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
Parallel Data
Control Code Group Detection
The 8B/10B decoder differentiates between data and control codes
through the rx_ctrldetect port. If the received 10-bit code group is a
control code group (Kx.y), the rx_ctrldetect signal is driven high. If
it is a data code group (Dx.y), the rx_ctrldetect signal is driven low.
Figure 1–51 shows an example waveform demonstrating the receipt of a
K28.5 code group (BC + ctrl). The rx_ctrldetect=1'b1 is aligned with
8'hbc, indicating that it is a control code group. The rest of the codes
received are Dx.y code groups.
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Figure 1–51. Control Code Group Detection
clock
dataout[7..0 ]
83
78
BC
BC
0F
00
BF
3C
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D28.1
ctrldetect
Code Group
Code Group Error Detection
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
In GIGE, XAUI, and PIPE modes, the invalid code is replaced by a
/K30.7/ code (8'hFE on rx_dataout + 1'b1 on rx_ctrldetect). In all
other modes, the value of the invalid code value can vary and should be
ignored
Disparity Error Detection
If the received 10-bit code group is detected with incorrect running
disparity, the 8B/10B decoder block asserts an error flag on the
rx_disperr and rx_errdetect ports.
f
Refer to the Specifications and Additional Information chapter in volume 2
of the Arria GX Device Handbook for information about the disparity
calculation.
If negative disparity is calculated for the last 10-bit code group, a neutral
or positive disparity 10-bit code group is expected. If the 8B/10B decoder
does not receive a neutral or positive disparity 10-bit code group, the
rx_disperr signal goes high, indicating that the code group received
has a disparity error. Similarly, if a neutral or negative disparity is
expected and a 10-bit code group with positive disparity is received, the
rx_disperr signal goes high.
The detection of the disparity error might be delayed, depending on the
data that follows the actual disparity error. The 8B/10B control codes
terminate propagation of the disparity error. Any disparity errors
propagated stop at the control code group, terminating that disparity
error.
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In GIGE and XAUI modes, the code that contains a disparity error is
replaced by a /K30.7/ code (8'hFE on rx_dataout + rx_ctrldetect).
In all other modes, the code with incorrect disparity should be treated as
an invalid code and ignored.
Figure 1–52 shows a case where the disparity is violated. A K28.5 code
group has an 8-bit value of 8'hbc and a 10-bit value that depends on the
disparity calculation at the point of the generation of the K28.5 code
group. The 10-bit value is 10'b0011111010 (10'h17c) for RD– or
10'b1100000101 (10'h283) for RD+. If the running disparity at time n - 1 is
negative, the expected code group at time must be from the RD– column.
A K28.5 does not have a balanced 10-bit code group (equal number of 1s
and 0s), so the expected RD code group must toggle back and forth
between RD– and RD+. At time n + 3, the 8B/10B decoder received a RD+
K28.5 code group (10'h283), which makes the current running disparity
negative. At time n + 4, because the current disparity is negative, a K28.5
from the RD– column is expected, but a K28.5 code group from the RD+
is received instead. This prompts rx_disperr to go high during time
n + 4 to indicate that this particular K28.5 code group had a disparity
error. The current running disparity at the end of time n + 4 is negative
because a K28.5 from the RD+ column was received. Based on the current
running disparity at the end of time n + 5, a positive disparity K28.5 code
group (from the RD–) column is expected at time n + 5.
Figure 1–52. Disparity Error Detection
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
BC
BC
BC
BC
xx
BC
BC
BC
Expected RD Code
RD-
RD+
RD-
RD+
RD-
RD-
RD+
RD-
RD Code Received
RD-
RD+
RD-
RD+
RD+
RD-
RD+
RD-
rx_datain
17C
283
17C
283
283
17C
283
17C
clock
rx_dataout[7..0 ]
rx_disperr
rx_errdetect
rx_ctrldetect
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Reset Condition
The reset for the 8B/10B decoder block is derived from the receiver digital
reset (rx_digitalreset). When rx_digitalreset is asserted, the
8B/10B decoder block resets. In reset, the disparity registers are cleared
and the outputs of the 8B/10B decoder block are driven low. After reset,
the 8B/10B decoder starts with unknown disparity, depending on the
disparity of the data it receives. The decoder calculates the initial running
disparity based on the first valid code group received.
1
The receiver block must be word aligned after reset before the
8B/10B decoder can decode valid data or control codes. If word
alignment has not been achieved, the data from the 8B/10B
decoder should be considered invalid and discarded.
Polarity Inversion
The 8B/10B decoder has a PCI Express compatible polarity inversion on
the data bus prior to 8B/10B decoding. This polarity inversion inverts the
bits of the incoming data stream prior to the 8B/10B decoding block to fix
potential P-N polarity inversion on the differential input buffer. You use
the optional pipe8b10binvpolarity port to invert the inputs to the
8B/10B decoder dynamically from the PLD.
Byte Deserializer
The byte deserializer (Figure 1–53) takes in 8- or 10-bit wide data from the
8B/10B decoder and deserializes it into 16- or 20-bit wide data at half the
speed. This allows clocking the PLD-transceiver interface at half the
speed as compared to the receiver PCS logic. The byte deserializer is
bypassed in GIGE mode.
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Figure 1–53. Byte Deserializer
dataout[15:0]
datain[7:0]
Byte
Deserializer
From 8B/10B
Decoder
To receiver phase
compensation
wrclk
rdclk
FIFO
/2
Low -speed parallel recovered
clock from CRU (1) or Low -speed
parallel CMU clock (2)
Notes to Figure 1–53:
(1)
(2)
Write port is clocked by low-speed parallel recovered clock if rate matcher is not used.
Write port is clocked by low-speed parallel CMU clock if rate matcher is used.
If the byte deserializer is used, the byte ordering at the receiver output
might be different than what was transmitted. Figure 1–54 shows the
16-bit transmitted data pattern with A at the lower byte, followed by B at
the upper byte. C and D follow in the next lower and upper bytes,
respectively. At the byte deserializer, byte A arrives when it is stuffing the
upper byte instead of stuffing the lower byte. This is a non-deterministic
swap because it depends on PLL lock times and link delay. Implement
byte-ordering logic in the PLD to correct this situation.
Figure 1–54. Intended Transmitted Pattern and Incorrect Byte Position at
Receiver After Byte Serializer
X
B
D
A
C
X
X
A
C
X
B
D
Intended Transmitted
Pattern
Incorrect Byte Position
at Receiver
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer (Figure 1–55) is located at
the FPGA logic array interface in the receiver block and is used to
compensate for phase difference between the receiver clock and the clock
from the PLD. The receiver phase compensation FIFO buffer operates in
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Receiver Channel Architecture
two modes: low latency and high latency. In low latency mode, the FIFO
buffer is four words deep. The Quartus II software chooses the low
latency mode automatically for every mode except the PCI-Express PIPE
mode (which automatically uses high latency mode). In high latency
mode, the FIFO buffer is eight words deep.
Figure 1–55. Receiver Phase Compensation FIFO Buffer
Receiver Channel
rx_dataout[]
datain[ ]
From Byte
Deserializer or
8B/10B Decoder
Low-Speed Parallel
Recovered Clock (1) or
Low-Speed Parallel
CMU Clock (2)
Receiver Phase
Compensation
FIFO
wrclk
To PLD or PIPE
interface
rdclk
rx_coreclk
/2
rx_clkout or
tx_clkout or
coreclkout
Notes to Figure 1–55:
(1)
(2)
Write port is clocked by low-speed parallel recovered clock when rate matcher is not used.
Write port is clocked by low-speed parallel CMU clock when rate matcher is used.
In Basic mode, the write port is clocked by the recovered clock from the
CRU. This clock is half the rate if the byte deserializer is used. The read
clock is clocked by the associated channel’s recovered clock.
1
The receiver phase compensation FIFO is always used and
cannot be bypassed.
In four-channel (×4) bonding mode, all the read pointers are derived from
a common source so that there is no need to synchronize the data of each
channel in the PLD logic.
Receiver Phase Compensation FIFO Error Flag
Depending on the transceiver configuration, the write port of the receiver
phase compensation FIFO can be clocked by either the recovered clock
(rx_clkout) or transmitter PLL output clock (tx_clkout or
coreclkout). The read port can be clocked by the recovered clock
(rx_clkout), transmitter PLL output clock (tx_clkout or
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Arria GX Transceiver Architecture
coreclkout) or a PLD clock. In all configurations, the write clock and
the read clock must have 0 PPM difference to avoid overrun/underflow
of the phase compensation FIFO.
An optional debug_rx_phase_comp_fifo_error port is available in
all modes to indicate receiver phase compensation FIFO
overrun/underflow condition. debug_rx_phase_comp_fifo_error
is asserted high when the phase compensation FIFO gets either full or
empty. This feature is useful to verify the phase compensation FIFO
overrun/underflow condition as a probable cause of link errors.
PLD-Transceiver
Interface
Clocking
The transmitter phase compensation FIFO present at each channel’s
PLD-transmitter interface compensates for the phase difference between
the PLD clock that produces the data to be transmitted and the
transmitter PCS clock. The receiver phase compensation FIFO present at
each channel’s PLD-receiver interface compensates for the phase
difference between the PLD clock that processes the received data and the
receiver PCS clock.
Depending on the functional mode, the Quartus II software automatically
selects appropriate clocks to clock the read port of the transmitter phase
compensation FIFO and the write port of the receiver phase
compensation FIFO.
The write clock of the transmitter phase compensation FIFO and the read
clock of the receiver phase compensation FIFO are part of the
PLD-transceiver interface clocks. Arria GX transceivers provide the
following two options for selecting these PLD-transceiver interface
clocks:
■
■
Automatic Phase Compensation FIFO clock selection
User Controlled Phase Compensation FIFO clock selection
The automatic phase compensation FIFO clock selection is a simpler
option, but could lead to higher clock resource utilization as compared to
user controlled phase compensation FIFO clock selection. This could be
critical in designs with high clock resource requirements.
Automatic Phase Compensation FIFO Clock Selection
If you do not instantiate the tx_coreclk and rx_coreclk ports for the
Arria GX transceiver instance in the MegaWizard Plug-In Manager, the
Quartus II software automatically selects appropriate clocks to clock the
write port of the transmitter phase compensation FIFO and the read clock
of the receiver phase compensation FIFO.
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PLD-Transceiver Interface Clocking
Table 1–8 lists the clock sources that the Quartus II software automatically
selects for the transmitter and receiver phase compensation FIFOs,
depending on the functional mode.
Table 1–8. Clock Sources for the Transmitter and Receiver Phase Compensation FIFOs
Write port clock selection for
Transmitter Phase Compensation
FIFO
Functional Mode
Read port clock selection for
Receiver Phase Compensation
FIFO
Individual-channel mode with rate
matcher
tx_clkout[0] from channel 0
clocks the FIFO write port in all
channels in the same transceiver
block.
tx_clkout[0] from channel 0
clocks the FIFO read port in all
channels in the same transceiver
block.
Individual-channel mode without
rate matcher
tx_clkout[0] from channel 0
clocks the FIFO write port in all
channels in the same transceiver
block.
rx_clkout from each channel
clocks the FIFO read port of its
associated channel.
Bonded-channel mode with/without
rate matcher
coreclkout clocks the FIFO
coreclkout clocks the FIFO read
write port in all channels in the same port in all channels in the same
transceiver block.
transceiver block.
In an individual-channel mode without rate matcher (Serial RapidIO), a
total of five global/regional clock resources per transceiver block are used
by the PLD-transceiver interface clocks. Four clock resources are used by
the rx_clkout signal of each channel being routed back to clock the read
port of its receiver phase compensation FIFO. One clock resource is used
by the tx_clkout[0] signal of Channel 0 being routed back to clock the
write port of all transmitter phase compensation FIFOs in the transceiver
block.
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Arria GX Transceiver Architecture
Figure 1–56 shows the minimum PLD-Interface clock utilization per
transceiver block when configured in individual-channel mode without
the rate matcher.
Figure 1–56. Minimum PLD-Interface Clock Utilization Per Transceiver Block Without the Rate Matcher
PLD
XCVR
Channel 3
RX Phase
Comp FIFO
rx_clkout[3]
TX Phase
Comp FIFO
tx_clkout[0]
RX
CRU
TX
TX CLK
Div Block
Channel 2
RX Phase
Comp FIFO
rx_clkout[2]
TX Phase
Comp FIFO
tx_clkout[0]
RX
CRU
TX
TX CLK
Div Block
Channel 1
RX Phase
Comp FIFO
rx_clkout[1]
TX Phase
Comp FIFO
tx_clkout[0]
RX
CRU
TX
TX CLK
Div Block
Channel 0
RX Phase
Comp FIFO
rx_clkout[0]
TX Phase
Comp FIFO
RX
CRU
TX
TX CLK
Div Block
tx_clkout[0]
The PLD-transceiver clock utilization can be reduced by driving the
transmitter and receiver phase compensation FIFOs with a single clock.
This is possible only if the driving clock is frequency-locked to the
transceiver output clocks (tx_clkout, coreclkout, or rx_clkout).
To control the write and read clock selection for the transmitter and
receiver phase compensation FIFO, you must instantiate the
tx_coreclk and rx_coreclk ports for the transceiver channels.
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May 2008
PLD-Transceiver Interface Clocking
User Controlled Phase Compensation FIFO Clock Selection
Instead of the Quartus II software automatically selecting the write and
read clocks of the transmitter and receiver phase compensation FIFOs,
respectively, you can manually connect appropriate clocks by
instantiating the tx_coreclk and rx_coreclk ports in the
MegaWizard Plug-In Manager. For all like channels configured in the
same functional mode and running off the same clock source, you can
connect the tx_coreclk and rx_coreclk ports of all channels together
and drive them using the same clock source. You can use a PLD clock
input pin or a transceiver clock
(tx_clkout[0]/coreclkout/rx_clkout) to clock the
tx_coreclk/rx_coreclk ports (Figure 1–57).
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Arria GX Transceiver Architecture
Figure 1–57. User Controlled Phase Compensation FIFO Clock
Channel 3
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[3]
TX Phase
Comp FIFO
TX
TX CLK
Div Block
tx_coreclk[3]
Channel 2
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[2]
TX Phase
Comp FIFO
tx_coreclk[2]
TX
TX CLK
Div Block
Channel 1
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[1]
TX Phase
Comp FIFO
TX
TX CLK
Div Block
tx_coreclk[1]
Channel 0
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[0]
tx_coreclk[0]
To user
logic
TX Phase
Comp FIFO
TX
TX CLK
Div Block
tx _clkout[0]
1
If the rx_clkout signal is used as a driver, it can only drive the
rx_coreclk ports. It cannot drive the tx_coreclk ports. If
tx_coreclk and rx_coreclk need to be driven with the
same clock, you must use the tx_clkout signal as the clock
driver.
If the clock signal on tx_coreclk is used to clock the write side of the
transmitter phase compensation FIFO, you must make sure that it is
frequency locked to the transmitter PCS clock reading from the FIFO. If
the clock signal on rx_coreclk is used to clock the read side of the
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PLD-Transceiver Interface Clocking
receiver phase compensation FIFO, you must make sure that it is
frequency locked to the receiver PCS clock writing into the FIFO. Any
frequency differences may cause data corruption.
To help guard against incorrect usage, the use of the tx_coreclk and
rx_coreclk options requires clock assignments in the assignment
organizer. If no assignments are used, the Quartus II software will issue a
compilation error.
There are four settings to enable the PLD interface clocking options:
■
■
■
■
Stratix II GX/Arria GX GXB Shared Clock Group Setting
Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting
Stratix II GX/Arria GX 0PPM Clock Group Setting
Stratix II GX/Arria GX 0PPM Clock Group Driver Setting
There are two main settings, Shared Clock and 0 PPM Clock, each with a
driver and clock group setting. When specifying clock groups, an integer
identifier is used as the group name to differentiate the different clock
group settings from each another.
The Stratix II GX/Arria GX GXB Shared Clock Group Setting is the
safest assignment. The Quartus II compiler analyzes the netlist during
compilation to ensure transmitter channel members are derived from the
same source. The Quartus II software gives a fitting error for
incompatible assignments. The software cannot check for the output of
the receiver frequency locked to the driving clock as the exact frequency
is dictated by the upstream transmitter’s source clock. You must ensure
that the rx_coreclk is derived from the same source clock as the
upstream transmitter.
The Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting
assignment must be made to the source channel of the tx_clkout or
coreclkout. Specifying anything but the transmitter channels (the
source for the tx_clkout or coreclkout) results in a Fitter error. If the
source clock is not from tx_clkout or coreclkout (for example, the
source is from rx_clkout or from a PLD clock input), the 0 PPM setting
must be used instead.
For example, in a synchronous system, the transmitter and receiver are
running off the same clock. To make tx_clkout[0] the clock driver, the
Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting is made
in the assignment editor on the tx_dataout[0] name. You can use a
group identifier value of “1” to identify the group that this driver feeds.
The Stratix II GX/Arria GX GXB Shared Clock Group Setting is made to
all the rx_datain channels that the tx_dataout[0] output clock
drives.
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Arria GX Transceiver Architecture
1
The other tx_dataout channels do not need an assignment
because the Quartus II software automatically groups the like
transmitters in a transceiver block. A group identifier value of
“1” is also made to the rx_datain assignments.
The assignments in the Assignment Editor are shown in Table 1–9.
Table 1–9. Assignment Editor
To:
tx_dataout[0]
Assignment name:
Stratix II GX/Arria GX GXB Shared Clock Group Driver
Setting
Value:
1
To:
rx_datain[] (note that the [] signifies the entire
rx_datain group)
Assignment name:
Stratix II GX/Arria GX GXB Shared Clock Group Setting
Value:
1
The Stratix II GX/Arria GX 0PPM Clock Group Setting is for more
advanced users that know the clocking configuration of the entire system
and want to reduce the PLD global clock resource and PLD interface clock
resource utilization. The Quartus II compiler does not perform any
checking on the clock source. It is up to you to ensure that there is no
frequency difference from the associated transceiver clock of the group
and the driving clock to the tx_coreclk and rx_coreclk ports.
The Stratix II GX/Arria GX 0PPM Clock Group Driver Setting can be
used with any of the transceiver output clocks (tx_clkout, rx_clkout,
and coreclkout) as well as any PLD clock input pins, transceiver
dedicated REFCLK pin, or PLD PLL output. User logic cannot be used as
a driver. As with the shared clock group setting, the driver setting for the
transceiver output clocks is made to the associated channel. For example,
for tx_clkout or coreclkout, the transmitter channel name is
specified. When the rx_clkout is the driver, the receiver channel name
of the associated rx_clkout is specified. For the PLD input clock pins
and the transceiver REFCLK pins, the name of the clock pin can be
specified. For the PLL output, the PLL clock output port of the PLL can be
found in the Node Finder and entered as the driver name. An integer
value is specified for the group identification.
The Stratix II GX/Arria GX 0PPM Clock Group Setting is made to the
transmitter or receiver channel names.
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Loopback Modes
The assignments in the Assignment Editor are shown in Table 1–10.
Table 1–10. Assignment Editor
f
Loopback Modes
To:
tx_dataout[0], pld_clk_pin_name,
refclk_pin, and pll_outclk
Assignment name:
Stratix II GX/Arria GX GXB 0PPM Clock Group Driver
Setting
Value:
1
To:
rx_datain[] and tx_dataout[]
Assignment name:
Stratix II GX/Arria GX GXB 0PPM Clock Group Setting
Value:
1
For a complete set of features supported in each protocol, refer to the
Arria GX Transceiver Protocol Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook.
There are several loopback modes available on the Arria GX transceiver
block that allow you to isolate portions of the circuit. All paths are
designed to run up to full speed. The available loopback paths are:
■
■
■
■
Serial loopback available in all functional modes except PCI Express
(PIPE)
Reverse serial loopback available in Basic mode with 8B/10B
PCI Express PIPE reverse parallel loopback available in PCI Express
protocol
Reverse serial pre-CDR loopback available in Basic mode with
8B/10B Reverse serial loopback available in Basic mode with 8B/10B
Serial Loopback
Figure 1–58 shows the data path for serial loopback. A data stream is fed
to the transmitter from the FPGA logic array and has the option of
utilizing all the blocks in the transmitter. The data, in serial form, then
traverses from the transmitter to the receiver. The serial data is the data
that is transmitted from the Arria GX device. Once the data enters the
receiver in serial form, it can use any of the receiver blocks and is then fed
into the FPGA logic array.
Use the rx_seriallpbken port to dynamically enable serial loopback
on a channel by channel basis. When rx_seriallpbken is high, all
blocks that are active when the signal is low are still active. When the
serial loopback is enabled, the tx_dataout port is still active and drives
out the output pins.
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Serial loopback is often used to check the entire path of the transceiver.
The data is retimed through different clock domains and an alignment
pattern is still necessary for the word aligner.
Figure 1–58. Arria GX Block in Serial Loopback Mode
Transmitter Digital Logic
TX Phase
Compensation
FIFO
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
Byte
Serializer
20
8B/10B
Encoder
Serializer
FPGA
Logic
Array
Serial
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
Byte
Ordering
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
PCI Express PIPE Reverse Parallel Loopback
Figure 1–59 shows the data path for the PCI Express PIPE reverse parallel
loopback. This data path is not flexible because it must be compliant with
the PCI Express PIPE specification. The data comes in from the
rx_datain ports. The receiver uses the CRU, deserializer, word aligner,
and rate matching FIFO buffer, loops back to the transmitter serializer,
and then goes out the transmitter tx_dataout ports. The data also goes
to the PLD fabric on the receiver side to the tx_dataout port. The
deskew FIFO buffer is not enabled in this loopback mode. This loopback
mode is optionally controlled dynamically through the
tx_detectrxloopback port.
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This is the only loopback allowed in the PIPE mode.
Altera Corporation
May 2008
Loopback Modes
Figure 1–59. Arria GX Block in PCI Express PIPE Reverse Parallel Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
BIST
PRBS
Generator
Byte
Serializer
8B/10B
Encoder
20
FPGA
Logic
Array
Serializer
PCI Express PIPE
Reverse Parallel
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Loopback
Reverse serial loopback is a subprotocol in Basic mode. It requires
8B/10B, and the word aligner pattern of K28.5. No dynamic pin control is
available to select or deselect reverse serial loopback. The active block of
the transmitter is only the buffer. The data sent to the receiver is retimed
with the recovered clock and sent out to the transmitter.
The data path for reverse serial loopback is shown in Figure 1–60. Data
comes in from the rx_datain ports in the receiver. The data is then fed
through the CDR block in serial form directly to the tx_dataout ports
in the transmitter block.
You can enable reverse serial loopback for all channels through the
MegaWizard Plug-In Manager. Any pre-emphasis setting on the
transmitter buffer is ignored in reverse serial loopback. The data flows
through the active blocks of the receiver and into the logic array.
Reverse serial loopback is often implemented when using a bit error rate
tester (BERT).
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Arria GX Transceiver Architecture
Figure 1–60. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
Reverse
Serial
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Pre-CDR Loopback
The reverse serial pre-CDR loopback uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, loops back before the CRU
unit, and is transmitted though the high-speed differential transmitter
output buffer. This loopback mode is for test or verification use only to
verify the signal being received after the gain and equalization
improvements of the input buffer. The signal at the output is not exactly
what is received, because the signal goes through the output buffer and
the VOD is changed to the VOD setting level. The pre-emphasis settings
have no effect.
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Loopback Modes
Figure 1–61. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
Reverse
Serial
Loopback
Pre-CDR
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Incremental Pattern Generator
The incremental data generator sweeps through all the valid 8B/10B data
and control characters. This mode is only available in Basic mode with the
BIST/parallel loopback subprotocol in the Quartus II software. You can
also enable the incremental BIST verifier to perform a quick verification
of the 8B/10B encoder/decoder paths.
In incremental mode, the BIST generator sends out the data pattern in the
following sequence: K28.5 (comma), K27.7 (start of frame, SOF), Data
(00 FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7,
K30.7, K29.7 (end of frame, EOF), and then repeats. You must enable the
8B/10B encoder for proper operation. No dynamic control pin is available
to enable or disable the loopback. Test result pins are rx_bistdone and
rx_bisterr. The rx_bistdone signal goes high at the end of the
sequence. If the verifier detects an error before it is finished, rx_bisterr
pulses high as long as the data is in error.
Built-In Self Test Modes
In addition to the regular data flow blocks, each transceiver channel
contains an embedded built-in self test (BIST) generator and
corresponding verifier block that you can use for quick device and setup
verification ( Figure 1–62). The generators reside in the transmitter block
and the verifier in the receiver block. The generators can generate PRBS
patterns. The verifiers are only available for the PRBS patterns. The BIST
modes are only available as subprotocols under Basic mode.
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Figure 1–62. Built-In Self Test Mode
rx_datain[]
tx_dataout
Buit-In Self Test
(BIST)
tx_digitalreset[]
rx_digitalreset[]
rx_bisterr(2)
rx_seriallpbken[](1)
rx_bistdone(2)
pll_inclk[]
Notes to Figure 1–62:
(1)
(2)
rx_seriallpbken[] is required in PRBS.
rx_bisterr[] and rx_bistdone[] are only available in PRBS and BIST modes.
Figure 1–63 shows the PRBS blocks with loopback used in the transceiver
channel.
Figure 1–63. PRBS Blocks With Loopback in Transceiver Channel
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
BIST
PRBS
Generator
Byte
Serializer
20
8B/10B
Encoder
Serializer
FPGA
Logic
Array
Serial
Loopback
BIST
Incremental
Verify
BIST
PRBS
Verify
Byte
Deserializer
RX Phase
Compensation
FIFO
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
BIST in Basic Mode
Basic mode supports PRBS10 pattern generation and verification. PRBS10
is supported with or without serial loopback.
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The PRBS10 pattern is only available when the SERDES factor is
10 bits.
Altera Corporation
May 2008
Loopback Modes
Table 1–11 shows the BIST patterns for Basic mode.
Table 1–11. Available BIST Patterns in Basic Mode
Pattern
PRBS10
Basic Mode
Word Aligner
Alignment Pattern
Byte Order Align
Pattern
Description
10’h3FF
N/A
X10 + X7 + 1
8 Bit
10 Bit
—
v
PRBS10
Pseudo-Random Bit Sequences (PRBS) are commonly used in systems to
verify the integrity and robustness of the data transmission paths. When
the SERDES factor is 10, use the PRBS10 pattern. The PRBS generator
yields 2^10-1 unique patterns. You can use PRBS with or without serial
loopback. In PRBS/ serial loopback mode, the rx_seriallpbken signal
is available. In the PRBS/no loopback mode, this control signal is not
available.
You enable PRBS mode in the Quartus II ALT2GXB MegaWizard Plug-In
Manager. PRBS10 does not use the 8B/10B encoder and decoder. The
8B/10B encoder and decoder are bypassed automatically in the PRBS
mode.
The advantage of using a PRBS data stream is that the randomness yields
an environment that stresses the transmission medium. In the data
stream, you can observe both random jitter and deterministic jitter using
a time interval analyzer, bit error rate tester, or oscilloscope.
The PRBS verifier can provide a quick check through the non-8B/10B
path of the transceiver block. The PRBS verifier is active once the receiver
channel is synchronized. Set the alignment pattern to 10'h3FF for the
10-bit SERDES modes.
The verifier stops checking the patterns after receiving all the PRBS
patterns (1023 patterns for 10-bit mode). The rx_bistdone signal goes
high, indicating that the verifier has completed. If the verifier detects an
error before it is finished, rx_bisterr pulses high for the time the data
is incorrect. Use the rx_digitalreset signal to re-start the PRBS
verification.
The 8B/10B encoder is enabled, so the data stream is DC balanced.
8B/10B encoding guarantees a run length of less than 5 UI, which yields
a less stressful pattern versus the PRBS data. However, since the PRBS
generator bypasses the 8B/10B paths, the incremental BIST can test this
path.
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Calibration
Blocks
The Arria GX gigabit transceiver block contains calibration circuits to
calibrate the on-chip termination, the PLLs, and the output buffers. The
calibration circuits are divided into two main blocks: the PLL and output
buffer calibration block and the termination resistor calibration block
(refer to Figure 1–64). Each transceiver block contains a PLL and output
buffer calibration block that calibrates the PLLs and output buffers within
that particular transceiver block. Each device contains one termination
resistor calibration block that calibrates all the termination resistors in the
transceiver channels of the entire device.
Figure 1–64. Calibration Block
rref
PLL and Output
Buffer Calibration Block
Reference
Signal
cal_blk_powerdown
calibration_clk
Termination Resistor
Calibration Block
PLL and Output Buffer Calibration Block
Each Arria GX transceiver block contains a PLL and output buffer
calibration circuit to counter the effects of PVT (process, voltage, and
temperature) on the PLL and output buffer. Each transceiver block's
calibration circuit uses a voltage reference derived from an external
reference resistor. There is one reference resistor required for each active
transceiver block in Arria GX devices. Unused transceiver blocks (except
the transceiver blocks feeding the termination resistor calibration block)
can be left unconnected or be tied to the 3.3 V transceiver analog VCC (if
the transceiver block’s 3.3 V analog supply is connected to 3.3 V).
Termination Resistor Calibration Block
The Arria GX transceiver's on-chip termination resistors in the
transceiver channels of the entire device are calibrated by a single
calibration block. This block ensures that process, voltage, and
temperature variations do not have an impact on the termination resistor
value. There is only one termination resistor calibration block per device.
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May 2008
Calibration Blocks
The calibration block uses the reference resistor of transceiver block 0 or
transceiver block 1, depending on the device and package. The calibration
block uses the reference resistor in transceiver block 0 for EP1AGX20/35
and EP1AGX50/60 devices (except in the F484 package). The reference
resistor in transceiver block 1 is used for EP1AGX20/35 and
EP1AGX50/60 devices in the F484 package, and for the EP1AGX90
device. A reference resistor must be connected to either transceiver block
0 or transceiver block 1 to ensure proper operation of the calibration
block, whether or not the transceiver block is in use. Failing to connect the
reference resistor of the transceiver block feeding the calibration block
results in incorrect termination values for all the termination resistors in
the transceivers of the entire device.
The termination resistor calibration circuit requires a calibration clock.
You can use a global clock line if the REFCLK pins are used for the
reference clock. You can instantiate a calibration clock port in the
MegaWizard Plug-In Manager to supply your own clock through the
cal_blk_clk port.
The frequency range of the cal_blk_clk is 10 MHz to 125 MHz. If there
are no slow speed clocks available, use a divide down circuit (for
example, a ripple counter) to divide the available clock to a frequency in
that range. The quality of the calibration clock is not an issue, so PLD local
routing is sufficient to route the calibration clock.
For multiple ALT2GXB instances in the same device, if all the instances
are the same, the calibration block must be active and the cal_blk_clk
port of all instances must be tied to a common clock. Physically, there is
one cal_blk_clk port per device. The Quartus II software provides an
error message if the cal_blk_clk port is tied to different clock sources,
because this would be impossible to fit into a device. If there are different
configurations of the ALT2GXB instance, only one must have the
calibration block instantiated. If multiple instances of the ALT2GXB
custom megafunction variation have the calibration block instantiated,
then all the cal_blk_clk ports must be tied to the same clock source.
The calibration block can be powered down through the optional
cal_blk_powerdown port (this is an active low input). Powering down
the calibration block during operations may yield transmit and receive
data errors. Only use this port to reset the calibration block to initiate a
recalibration of the termination resistors to account for variations in
temperature or voltage. The minimum pulse duration for this port is
determined by characterization. If external termination is used on all
signals, the calibration block in ALT2GXB need not be used.
Altera Corporation
May 2008
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Arria GX Transceiver Architecture
Referenced
Documents
This chapter references the following documents:
■
■
Arria GX Transceiver Protocol Support and Additional Features
Specifications and Additional Information
1–84
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Document Revision History
Document
Revision History
Table 1–12 shows the revision history for this chapter.
Table 1–12. Document Revision History
Date and Document
Version
May 2008, v2.0
Changes Made
●
●
August 2007, v1.2
Summary of Changes
Added sections “Transmitter PLL Bandwidth Setting”,
“Central Clock Divider Block”, “Transmitter Local Clock
Divider Block”, “Clock Synthesis”, “Transceiver Clock
Distribution”, “Single Lane”, “Four-Lane Mode”, “Channel
Clock Distribution”, “Individual Channels Clocking”,
“Transmitter Clocking (Bonded Channels)”, “Transmitter
Force Disparity”, “Transmitter Bit Reversal”, “Transmitter
Termination”, “PCI Express Receiver Detect”, “PCI
Express Electrical Idle”, “Receiver Buffer”, “Receiver
Termination”, “Signal Threshold Detection Circuit”,
“Receiver Common Mode”, “Programmable
Equalization”, “Clock Synthesis”, “PPM Frequency
Threshold Detector”, “Receiver Bandwidth Type”, “Basic
Mode”, “Pattern Detector Module”, “7-Bit Pattern Mode”,
“10-Bit Pattern Mode”, “7-bit Alignment Mode”, “Manual
10-Bit Alignment Mode”, “Manual Bit-Slip Alignment
Mode”, “Synchronization State Machine Mode”, “Run
Length Checker”, “Receiver Bit Reversal”, “Channel
Aligner (Deskew)”, “Basic Mode General Rate Matching”,
“Polarity Inversion”, “Receiver Phase Compensation
FIFO Error Flag”, “Serial Loopback”, “PCI Express PIPE
Reverse Parallel Loopback”, “Reverse Serial Loopback”,
“Reverse Serial Pre-CDR Loopback”, “Built-In Self Test
Modes”, “BIST in Basic Mode”, “PRBS10”, “Calibration
Blocks”, “PLL and Output Buffer Calibration Block”, and
“Termination Resistor Calibration Block”
Updated sections “Building Blocks”, “Port List”,
“Dedicated Reference Clock Input Pins”, “Byte
Serializer”, “8B/10B Encoder”, “Transmitter Polarity
Inversion”, “Serializer”, “Transmitter Buffer”, “Receiver
Channel Architecture”, “Code Group Error
Detection”,“Disparity Error Detection”, “Byte
Deserializer”, “Receiver Phase Compensation FIFO
Buffer”, and “Loopback Modes”
Major update. Addition of
new material.
Added the “Referenced Documents” section.
—
Minor text edits.
—
June 2007 v1.1
Added GIGE information.
—
May 2007 v1.0
Initial release.
—
Altera Corporation
May 2008
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Arria GX Transceiver Architecture
1–86
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
2. Arria GX Transceiver
Protocol Support and
Additional Features
AGX52002-2.0
Introduction
Arria™ GX transceivers have a dedicated physical coding sublayer (PCS)
and physical media attachment (PMA) circuitry to support PCI Express
(PIPE), Gigabit Ethernet (GIGE), and Serial RapidIO® protocols.
Table 2–1 lists the Arria GX transceiver datapath modules employed in
each mode.
Table 2–1. Arria GX Transceiver Datapath Modules
Functional
Mode
Transmitter
PLD/Receiver
Byte
8B/10B
Word
Rate
Transceiver
Phase
Serializer/ Encoder/
Aligner Matcher
Interface
Compensation Deserializer Decoder
Width (bits)
FIFO
PCI Express
(PIPE)
GIGE
Serial
RapidIO
(1.25Gbps)
Serial
RapidIO
(2.5Gbps)
v
v
v
v
v
v
v
v(1)
16
PLDTransceiver
Interface
Frequency
(MHz)
PCS
Frequency
(MHz)
125
250
—
v
v
v
8
125
125
v
v
v
—
16
62.5
125
v
v
v
—
16
125
250
Serial
RapidIO
(3.125Gbps)
v
v
v
v
—
16
156.25
312.5
SDI - HD
(1.483Gbps)
v
—
—
Bit-Slip
—
10/20
148.3
148.3/296.
6
SDI - HD
(1.485Gbps)
v
—
—
Bit-Slip
—
10/20
148.5
148.5/297
SDI - 3G
(2.967Gbps)
v
—
—
Bit-Slip
—
20
148.35
296.7
SDI - 3G
(2.97Gbps)
v
—
—
Bit-Slip
—
20
148.5
297
XAUI
(3.125Gbps)
v
v
v
v
v
16
156.25
312.5
Note to Table 2–1:
(1)
The rate matcher can be bypassed in low-latency (synchronous) PCI Express (PIPE) mode.
Altera Corporation
May 2008
2–1
Arria GX Transceiver Protocol Support and Additional Features
PCI Express
(PIPE) Mode
PCI Express is an evolution of peripheral component interconnect (PCI).
PCI is bandwidth-limited for today’s applications because it relies on
synchronous single-ended type signaling with a wide multi-drop data
bus. Clock and data-trace matching is required with PCI. PCI Express
uses differential serial signaling with an embedded clock to enable an
effective data rate of 2 Gbps per lane to overcome the limitations of PCI.
Arria GX transceivers support ×1 (single-lane) and ×4 (four-lane) link
widths when configured in PCI Express (PIPE) mode. The Arria GX
family supports up to twelve duplex (transmitter and receiver) ×1 links
and up to three ×4 links per device. Transceiver channels configured in ×4
PCI Express (PIPE) mode must be physically located in the same
transceiver block with logical Lane 0 assigned to physical Channel 0,
logical Lane 1 assigned to physical Channel 1 and so on.
In addition to providing the transceiver PCS and PMA circuitry, Arria GX
transceivers support the following protocol-specific features:
■
■
■
■
■
■
PCI Express synchronization state machine
Receiver detection
Electrical idle generation/detection
Beacon transmission
Polarity inversion
Power state management
1
f
This section is organized into transmitter and receiver data path
modules when configured for PCI Express (PIPE) mode. The
description for each module only covers details specific to PCI
Express (PIPE) functional mode support. Familiarity of PCI
Express protocol and PCI Express (PIPE) specifications is
assumed.
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
PCI Express (PIPE) Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
PCI Express (PIPE) mode (Figure 2–1). The sub-blocks are described in
order from the PLD transceiver parallel interface to the serial transmitter
buffer.
2–2
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May 2008
PCI Express (PIPE) Mode
Figure 2–1. PCI Express (PIPE) Transmitter Architecture
Transmitter PCS
PLD
Logic
Array
TX Phase
Compensation
FIFO
PIPE
Interface
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Reference
Clock
Clock Multiplier Unit
The clock multiplier unit (CMU) takes in a reference clock and
synthesizes the clocks that are used to clock the transmitter digital logic
(PCS), the serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
In ×1 PCI Express (PIPE) mode, the CMU block consists of the following
components:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
In ×4 PCI Express (PIPE) mode, the CMU block consists of the following
components:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Central clock divider block that generates low-speed parallel clock
for transmitter digital logic and PLD-transceiver interface of each
channel in the transceiver block
Input Reference Clock
In PCI Express (PIPE) mode, the only supported input reference clock
frequency is 100 MHz.
The reference clock input to the transmitter PLL can be derived from the
following pins:
Altera Corporation
May 2008
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Arria GX Transceiver Protocol Support and Additional Features
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide a reference clock for the
transmitter PLL.
Table 2–2 specifies the input reference clock options available in PCI
Express (PIPE) mode.
Table 2–2. PCI Express (PIPE) Mode Input Reference Clock Specifications
Frequency
100 MHz
I/O Standard
Coupling
Termination
1.2V PCML, 1.5V PCML, 3.3V PCML, Differential LVPECL, LVDS
AC
On-chip
HCSL (1)
DC (2)
Off-chip
Notes to Table 2–2:
(1)
(2)
In PCI Express (PIPE) mode, you have the option of selecting the HCSL standard for the reference clock if
compliance to PCI Express is required. The Quartus® II software automatically selects DC coupling with external
termination for the signal if configured as HCSL.
Refer to Figure 2–2 for an example termination scheme.
Figure 2–2 shows an example termination scheme for the reference clock
signal when configured as HCSL.
Figure 2–2. DC Coupling and External Termination Scheme for PCI Express Reference Clock
PCI Express
(HCSL)
REFCLK
Source
Arria GX
REFCLK +
Rs (1)
Rs (1)
REFCLK -
Rp = 50 Ω
Rp = 50 Ω
Note to Figure 2–2:
(1)
Select resistor values as recommended by the PCI Express clock source vendor.
2–4
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
Clock Synthesis
In PCI Express (PIPE) mode, the reference clock pre-divider divides the
100-MHz input reference clock by two. The resulting 50-MHz clock is fed
to the transmitter PLL. Because the transmitter PLL implements a
half-rate VCO, it multiplies the 50 MHz input clock by 25 to generate a
1250-MHz high-speed serial clock. This high-speed serial clock feeds the
central clock divider and four local clock dividers of the transceiver block.
In ×4 PCI Express (PIPE) mode, the central clock divider in the transceiver
block divides the 1250-MHz clock from the transmitter PLL by five to
generate a 250-MHz parallel clock. This low-speed parallel clock output
from the central clock divider block is used to clock the transmitter digital
logic (PCS) in all channels of the transceiver block. The central clock
divider block also forwards the high-speed serial clock from the
transmitter PLL to the serializer within each channel. Because all four
channels in the transceiver block are clocked with the same clock, the
channel-to-channel skew is minimized.
In ×1 PCI Express (PIPE) mode, the local clock divider in each channel of
the transceiver block divides the 1250-MHz clock from the transmitter
PLL by five to generate a 250-MHz parallel clock. This low-speed parallel
clock output from the local clock divider block is used to clock the
transmitter digital logic (PCS) of the associated channel. The local clock
divider block also forwards the high-speed serial clock from the
transmitter PLL to the serializer within its associated channel.
1
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for the PCI Express (PIPE)
data rate.
Figure 2–3 shows the CMU implemented in PCI Express (PIPE) mode.
Altera Corporation
May 2008
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Arria GX Transceiver Protocol Support and Additional Features
Figure 2–3. PCI Express (PIPE) Mode CMU
CMU Block
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
1250 MHz
Reference
Clock
100 MHz
/2
pre-divider
Transmitter
PLL
(x25)
50 MHz
1250 MHz
1250 MHz
Transmitter High-Speed
Serial (1250 MHz) and
Low-Speed Parallel (250 MHz)
Clock
Central Clock
Divider Block
(/5)
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
Transmitter Channels [1:0]
Transmitter High-Speed
Serial (1250 MHz) and
Low-Speed Parallel (250 MHz)
Clocks
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
f
Refer to the Transmitter Phase Compensation FIFO section in the
Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook for more details about transmitter phase compensation
FIFO buffer architecture.
In PCI Express (PIPE) mode, the 250-MHz clock generated by the CMU
clock divider block is divided by two. The resulting 125-MHz clock is
used to clock the read port of the FIFO buffer. This 125-MHz clock is also
forwarded to the PLD logic array (on the tx_clkout port in ×1 PCI
Express (PIPE) mode or the coreclkout port in ×4 PCI Express (PIPE)
mode). If the tx_coreclk port is not instantiated, the clock signal on the
tx_clkout port of channel 0 is routed back to clock the write side of the
transmitter phase compensation FIFO buffer in all channels with the
transceiver block. The 16-bit PLD-transceiver interface clocked at
125-MHz results in an effective PCI Express (PIPE) data rate of 2 Gbps.
In PCI Express (PIPE) mode, the transmitter phase compensation FIFO is
eight words deep. The latency through the FIFO is three to four
PLD-transceiver interface clock cycles.
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May 2008
PCI Express (PIPE) Mode
Figure 2–4 shows the block diagram of transmitter phase compensation
FIFO in PCI Express (PIPE) mode.
Figure 2–4. TX Phase Compensation FIFO in PCI Express (PIPE) Mode
Transmitter Channel
tx_datain[15:0]
Transmitter
Phase
Compensation
FIFO
From
PLD
wrclk
dataout[15:0]
To Byte Serializer
rdclk
250 MHz
tx_coreclk
125 MHz
125 MHz
/2
CMU
Local/Central Clock
Divider Block
tx_clkout or coreclkout
Byte Serializer
In PCI Express (PIPE) mode, the PLD-transceiver interface data is 16-bits
wide and is clocked into the transmitter phase compensation FIFO at
125 MHz. The byte serializer clocks in the 16-bit wide data from the
transmitter phase compensation FIFO at 125 MHz and clocks out 8-bit
data to the 8B/10B encoder at 250 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
f
For more details about byte serializer architecture, refer to the Byte
Serializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
The write port of the byte serializer is clocked by the divide-by-two
version of the low-speed parallel clock from the CMU. The read port is
clocked by the low-speed parallel clock from the CMU. The byte serializer
clocks out the least significant byte (LSByte) of the 16-bit data first and the
most significant byte (MSByte) last.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–5 shows the block diagram of the byte serializer in PCI Express
(PIPE) mode.
Figure 2–5. Byte Serializer in PCI Express (PIPE) Mode
dataout
datain
From Transmitter
Phase Compensation
FIFO
Byte Serializer
To 8B/10B
Encoder
wrclk
rdclk
125 MHz
250 MHz
125 MHz
/2
Divide-by-Two
Version of
Low-Speed
Parallel Clock
250 MHz
Low-Speed
Parallel Clock
CMU
Local/Central Clock
Divider Block
8B/10B Encoder
In PCI Express (PIPE) mode, the 8B/10B encoder clocks in 8-bit data and
1-bit control identifier from the byte serializer and generates 10-bit
encoded data. The 10-bit encoded data is fed to the serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
Compliance Pattern Transmission Support
PCI Express has an option to transmit a compliance pattern for testing
purposes. The compliance pattern must be transmitted beginning with a
negative disparity. In PCI Express (PIPE) mode, you set the negative
disparity with the tx_forcedispcompliance port.
Asserting the tx_forcedispcompliance port sets the LSByte of the
16-bit PLD-transmitter interface data to be encoded with a negative
disparity. The tx_forcedispcompliance port must be de-asserted
after the first word of the compliance pattern is clocked into the
transceiver.
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
1
The compliance pattern generator is not part of the Arria GX
transceiver and must be designed using the PLD logic. This
feature allows you to begin the compliance pattern only with a
negative disparity.
Serializer
In PCI Express (PIPE) mode, the 10-bit encoded data from the 8B/10B
encoder is clocked into the 10:1 serializer with the low-speed parallel
clock at 250 MHz. The 10-bit data is clocked out of the serializer LSByte to
MSByte at both edges of the high-speed serial clock at 1250 MHz. The
resulting 2.5 Gbps serial data output of the serializer is fed into the
transmitter output buffer.
f
Refer to the Serializer section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook for more details
about the serializer architecture.
Transmitter Buffer
Table 2–3 shows the transmitter buffer settings when configured in PCI
Express (PIPE) mode.
Table 2–3. Transmitter Buffer Settings in PCI Express (PIPE) Mode
Settings
Value
I/O Standard
1.2-V PCML (2)
Programmable Differential Output
Voltage (VOD)
320-960 mV
Common Mode Voltage (VCM)
600 mV (1)
Differential Termination
100 Ω (2)
Programmable Transmitter
Pre-Emphasis
Enabled (3)
VCCH (Transmitter Buffer Power)
1.2 V
Notes to Table 2–3:
(1)
(2)
(3)
Altera Corporation
May 2008
The common mode voltage (VCM) is fixed in the MegaWizard® Plug-In Manager
and cannot be changed.
The I/O standard and differential termination settings are defaulted to 1.2-V
PCML and 100 Ω , respectively. If you select any other setting for the I/O
standard or differential termination in the Assignment Editor, the Quartus II
compiler will issue an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
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Arria GX Transceiver Protocol Support and Additional Features
Transmitter Electrical Idle
In PCI Express (PIPE) mode, you can force the transmitter into electrical
idle condition during P0 and P2 power state by asserting the
tx_forceelecidle signal high. In electrical idle state, the transmitter
buffer is tri-stated. The tx_forceelecidle signal must always be
asserted high in P0 and P1 power states. Refer to “Power State
Management” on page 2–22 for more details about PCI Express (PIPE)
mode power states.
Receiver Detect
PCI Express Base Specification requires the transmitter to be capable of
detecting a far-end receiver before beginning link training. Arria GX
transceivers have dedicated receiver detect circuitry that is activated in
PCI Express (PIPE) mode.
The receiver detect circuitry is available only in the P1 power state, and is
set through the tx_detectrxloopback port, and requires a 125 MHz
fixedclk signal. Refer to “Power State Management” on page 2–22 for
more details about PCI Express (PIPE) mode power states.
In P1 power state, the transmitter output buffer is tri-stated, because the
transmitter is in electrical idle. A high on the tx_detectrxloopback
port triggers the receiver detect circuitry to alter the transmitter buffer
common mode voltage. The sudden change in common mode voltage
appears as a step voltage at the tri-stated transmitter buffer output. If a
receiver (that complies with PCI Express input impedance requirements)
is present at the far end, the time constant of the step voltage is higher. If
a receiver is not present or is powered down, the time constant of the step
voltage is lower. The receiver detect circuitry snoops the transmitter
buffer output for the time constant of the step voltage to detect the
presence of the receiver at the far end.
A high pulse is driven on the pipephydonestatus port and 3'b011 is
driven on the pipestatus port (refer to “Receiver Status” on page 2–21)
to indicate that a receiver has been detected. There is some latency after
asserting the tx_detectrxloopback signal, before the receiver
detection is indicated on the pipephydonestatus port.
1
The tx_forceelecidle port must be asserted at least 10
parallel clock cycles prior to the tx_detectrxloopback port
to ensure that the transmitter buffer is tri-stated.
Beacon Transmission
The beacon is an optional 30-kHz to 500-MHz in-band signal that wakes
the receiver from a P2 power state. This signal is optional; the Arria GX
device does not have dedicated beacon transmission circuitry. The
Arria GX device supports the transmission of the beacon signal through
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May 2008
PCI Express (PIPE) Mode
a 10-bit encoded code group that has a five 1’s pulse (for example, K28.5)
(10'b0101111100). Because the beacon signal is a pulse that ranges from
2 ns to 500 ns, sending out a K28.5 at 2.5 Gbps meets the lower
requirement with its five 1's pulse. (Though other 8B/10B code groups
might meet the beacon requirement, this document uses the K28.5 control
code group as the beacon signal.) The beacon transmission takes place
only in the P2 power state. The tx_forceelecidle port controls when
the transmitter is in Electrical Idle or not. This port must be de-asserted in
order to transmit the K28.5 code group for beacon transmission.
PCI Express (PIPE) Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in PCI
Express (PIPE) mode (Figure 2–6). The sub-blocks are described in order
from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 2–6. PCI Express (PIPE) Mode Receiver Architecture
Receiver PCS
PLD
Logic
Array
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
De-Serializer
8B/10B
Decoder
Rate
Match
FIFO
Receiver PMA
DeSerializer
Word
Aligner
Clock
Recovery
Unit
Receiver
PLL
Reference
Clocks
Receiver Buffer
Table 2–4 shows the receiver buffer settings when configured in PCI
Express (PIPE) mode.
Table 2–4. Receiver Buffer Settings in PCI Express (PIPE) Mode
(Part 1 of 2)
Settings
I/O Standard
Value
1.2-V PCML, 1.5-V PCML,
3.3-V PCML, Differential LVPECL,
LVDS
Input Common Mode Voltage (Rx VCM) 850 mV, 1200 mV (1)
Altera Corporation
May 2008
Differential Termination
100 Ω (2)
Programmable equalization
Enabled (3)
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–4. Receiver Buffer Settings in PCI Express (PIPE) Mode
(Part 2 of 2)
Settings
Coupling
Value
AC
Notes to Table 2–4:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard® Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω. If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler issues an error message.
The receiver buffer has five programmable equalization settings.
Signal Detect Threshold Circuitry
In PCI Express (PIPE) mode, the receiver buffer incorporates a signal
detect threshold circuitry. The signal detect threshold circuitry senses
whether the specified threshold voltage level exists at the receiver buffer.
This detector has a hysteresis response that filters out any high frequency
ringing caused by inter symbol interference or high frequency losses in
the transmission medium.
The rx_signaldetect signal indicates whether the signal at the
receiver buffer conforms to the signal detection settings. A high level on
the rx_signaldetect port indicates that the signal conforms to the
settings and a low level indicates that the signal does not conform to the
settings. The Quartus II software automatically defaults to the
appropriate signal detect threshold based on the PCI Express electrical
idle specifications.
Receiver PLL and Clock Recovery Unit (CRU)
In PCI Express (PIPE) mode, the receiver PLL in each transceiver channel
is fed by a 100 MHz input reference clock. The receiver PLL in
conjunction with the clock recovery unit generates two clocks: a
high-speed serial recovered clock at 1250 MHz (half-rate VCO) that feeds
the deserializer, and a low-speed parallel recovered clock at 250 MHz that
feeds the receiver’s digital logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switches the
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between
lock-to-reference and lock-to-data modes via the rx_locktorefclk
and rx_locktodata signals.
2–12
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
f
Refer to the Receiver PLL section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook for more details on
the CRU lock modes.
The reference clock input to the receiver PLL can be derived from the
following pins:
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Deserializer
The 1:10 deserializer clocks in serial data from the receiver buffer using
the high-speed recovered clock. The 10-bit deserialized data is clocked
out to the word aligner using the low-speed recovered clock at 250 MHz.
The deserializer assumes that the transmission bit order is LSB to MSB;
for example, the LSB of a data word is received earlier in time than its
MSB.
f
Refer to the Deserializer section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook for more details
about the deserializer architecture.
Word Aligner
The word aligner clocks in the 10-bit data from the deserializer and
restores the word boundary of the upstream transmitter. Besides
restoring the word boundary, it also implements a synchronization state
machine as specified in the PCI Express Base Specification to achieve lane
synchronization.
f
Refer to the section “Word Aligner” on page 2–13 in the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook for more details about the word aligner architecture.
In PCI Express (PIPE) mode, the word aligner consists of the following
three modules:
■
■
■
Altera Corporation
May 2008
Pattern detector module
Pattern aligner module
Run-length violation detector module
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Pattern Detector
In PCI Express (PIPE) mode, the Quartus II software automatically
configures 10-bit K28.5 (10'b0101111100) as the word alignment pattern.
After coming out of reset (rx_digitalreset), when the pattern
detector detects either disparities of the K28.5 control word, it asserts the
rx_patterndetect signal for one parallel clock cycle. When the
pattern aligner has aligned the incoming data to the desired word
boundary, the pattern detector asserts the rx_patterndetect signal
only if the word alignment pattern is found in the current word boundary.
Pattern Aligner
In PCI Express (PIPE) mode, the pattern aligner incorporates an
automatic synchronization state machine. The Quartus II software
automatically configures the synchronization state machine to indicate
lane synchronization when the receiver receives four good /K28.5/
control code groups. Synchronization can be accomplished through the
reception of four good PCI Express training sequences (TS1 or TS2) or
four fast training sequences (FTS). Lane synchronization is indicated on
the rx_syncstatus port of each channel. A high on the
rx_syncstatus port indicates that the lane is synchronized and a low
indicates that it has fallen out of synchronization.
Table 2–5 lists the synchronization state machine parameters when
configured in PCI Express (PIPE) mode.
Table 2–5. Synchronization State Machine Parameters in PCI Express (PIPE)
Mode
Number of valid /K28.5/ code groups received to achieve
synchronization (kcntr)
4
Number of errors received to lose synchronization (ecntr)
17
Number of continuous good code groups received to reduce the
error count by 1 (gcntr)
16
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 2–7 shows a state diagram of the PCI Express (PIPE)
synchronization.
Figure 2–7. PCI-Express (PIPE) Synchronization State Machine
Loss of Sync
Data = Comma
Data = !Valid
Comma Detect
if Data == Comma
kcntr++
else
kcntr=kcntr
Data = valid;
kcntr <3
kcntr = 3
Synchronized
Data=Valid
Data = !Valid
ecntr = 17
Synchronized Error
Detect
if Data == !valid
ecntr++
gcntr=0
else
if gcntr==16
ecntr-gcntr=0
else
gcntr++
ecntr = 0
Tables 2–6 and 2–7 list the TS1 and TS2 training sequences, respectively.
A PCI Express fast training sequence consists of a /K28.5/, followed by
three /K28.1/ code groups.
Table 2–6. PCI Express TS1 Ordered Set (Part 1 of 2)
Symbol
Number
Allowed Values
Encoded Values
0
—
K28.5
1
0–255
D0.0–D31.7, and K23.7
Link number with component
2
0–31
D0.0–D31.0, and K23.7
Lane number within port
Altera Corporation
May 2008
Description
Comma code group for symbol alignment
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–6. PCI Express TS1 Ordered Set (Part 2 of 2)
Symbol
Number
Allowed Values
Encoded Values
Description
3
0–255
D0.0–D31.7
N_FTS. The number of fast training ordered
sets required by the receiver to obtain
reliable bit and symbol lock.
4
2
D2.0
Data rate identifier
Bit 0–Reserved, set to 0
Bit 1 = 1, generation 1 (2.5Gbps) data rate
supported
Bit 2..7–Reserved, set to 0
5
Bit 0 = 0, 1
Bit 1 = 0, 1
Bit 2 = 0, 1
Bit 3 = 0, 1
Bit 4..7 = 0
D0.0, D1.0, D2.0, D4.0,
and D8.0
Training control
Bit 0 – Hot reset
Bit 0 = 0, de-assert
Bit 0 = 1, assert
Bit 1 – Disable link
Bit 1 = 0, de-assert
Bit 1 = 1, assert
Bit 1 – Loopback
Bit 2 = 0, de-assert
Bit 2 = 1, assert
Bit 3 – Disable scrambling
Bit 3 = 0, de-assert
Bit 3 = 1, assert
Bit 4..7 – Reserved
Bit 0 = 0, de-assert
Set to 0
6–15
—
D10.2
TS1 identifier
Table 2–7. PCI Express TS2 Ordered Set (Part 1 of 2)
Symbol
Number
Allowed Values
Encoded Values
K28.5
Description
0
—
1
0–255
D0.0–D31.7, and K23.7 Link number with component.
2
0–31
D0.0–D31.0, and K23.7 Lane number within port.
2–16
Arria GX Device Handbook, Volume 2
Comma code group for symbol alignment.
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 2–7. PCI Express TS2 Ordered Set (Part 2 of 2)
Symbol
Number
Allowed Values
Encoded Values
3
0–255
D0.0–D31.7
Description
N_FTS. The number of fast training ordered sets
required by the receiver to obtain reliable bit and
symbol lock.
4
2
D2.0
5
Bit 0 = 0, 1
Bit 1 = 0, 1
Bit 2 = 0, 1
Bit 3 = 0, 1
Bit 4..7 = 0
D0.0, D1.0, D2.0, D4.0,
and D8.0
Data rate identifier
Bit 0–Reserved, set to 0
Bit 1 = 1, generation 1 (2.5Gbps) data rate
supported
Bit 2..7–Reserved, set to 0
Training control
Bit 0 – Hot reset
Bit 0 = 0, de-assert
Bit 0 = 1, assert
Bit 1 – Disable link
Bit 1 = 0, de-assert
Bit 1 = 1, assert
Bit 1 – Loopback
Bit 2 = 0, de-assert
Bit 2 = 1, assert
Bit 3 – Disable scrambling
Bit 3 = 0, de-assert
Bit 3 = 1, assert
Bit 4..7 – Reserved
Bit 0 = 0, de-assert
Set to 0
6–15
—
D5.2
TS2 identifier
Rate Matcher
In PCI Express (PIPE) mode, the rate matcher can compensate up to
± 300 parts per million (PPM) (600 PPM total) frequency difference
between the upstream transmitter and the receiver. In ×1 and ×4 PCI
Express (PIPE) mode, the write port of the rate matcher FIFO in each
receiver channel is clocked by its low-speed parallel recovered clock. In
×1 PCI Express (PIPE) mode, the read port is clocked by the low-speed
parallel clock output of the CMU local clock divider block. In ×4 PCI
Express (PIPE) mode, the read port is clocked by the low-speed parallel
clock output of the CMU central clock divider block.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
The rate matcher logic looks for skip ordered sets (SKP), which contains
a /K28.5/ comma followed by three /K28.0/ skip characters. It deletes or
inserts /K28.0/ skip characters as necessary from or to the rate matcher
FIFO. The rate matcher can delete only one skip character in a consecutive
cluster of skip characters and can insert only one skip character per skip
cluster.
Figure 2–8 shows an example of a PCI Express (PIPE) mode rate matcher
deletion of two skip characters.
Figure 2–8. PCI Express (PIPE) Mode Rate Matcher Deletion
Skip Cluster
Skip Cluster
datain
K28.5
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
dataout
K28.5
K28.0
K28.0
Dx.y
K28.5
K28.0
Dx.y
Dx.y
Two Skips Deleted
The rate matcher in PCI Express (PIPE) mode has FIFO buffer overflow
and underflow protection. In the event of a FIFO buffer overflow, the rate
matcher deletes any data after detecting the overflow condition to
prevent FIFO pointer corruption until the rate matcher is not full. In an
underflow condition, the rate matcher inserts 9'h1FE (/K30.7/) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer can
gracefully exit the overflow/underflow condition without requiring a
FIFO reset. The rate matcher FIFO overflow and underflow condition is
indicated on the pipestatus port.
8B/10B Decoder
In PCI Express (PIPE) mode, the 8B/10B decoder clocks in 10-bit data
from the rate matcher and decodes it into 8-bit data + 1-bit control
identifier. The 8-bit decoded data is fed to the byte deserializer.
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups,
the 8B/10B decoder block asserts an error flag on rx_errdetect port.
The 8B/10B decoder replaces the invalid code group with /K30.7/ code
2–18
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
(8'hFE + 1'b1 after decoding). The error flag signal (rx_errdetect) has
the same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
If the received 10-bit code is detected with incorrect running disparity, the
8B/10B decoder block asserts an error flag on the rx_disperr and
rx_errdetect ports. The error flag signal (rx_disperr) has the same
delay from the 8B/10B decoder to the PLD-transceiver interface as the
received data.
Polarity Inversion
The 8B/10B decoder supports the PCI Express (PIPE) compatible polarity
inversion feature. This polarity inversion feature inverts the bits of the
incoming data stream prior to the 8B/10B decoding block to fix accidental
P-N polarity inversion on the differential input buffer. You use the
pipe8b10binvpolarity port to invert the inputs to the 8B/10B
decoder dynamically from the PLD.
1
You must not enable the receiver polarity inversion feature if
you enable the PCI Express polarity inversion.
Byte Deserializer
In PCI Express (PIPE) mode, the PLD-receiver interface data is 16-bits
wide and is clocked out of the receiver phase compensation FIFO at
125 MHz. The byte deserializer clocks in the 8-bit wide data from the
8B/10B decoder at 250 MHz and clocks out 16-bit wide data to the
receiver phase compensation FIFO at 125 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
f
For more details about byte deserializer architecture, refer to the Byte
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In ×1 PCI Express (PIPE) mode, the write port of the byte deserializer is
clocked by the low-speed parallel clock output from the CMU local clock
divider block (tx_clkout) and the read port is clocked by divide-by-two
version of this clock. In ×4 PCI Express (PIPE) mode, the write port of the
byte deserializer is clocked by the low-speed parallel clock output from
the CMU central clock divider block (coreclkout) and the read port is
clocked by divide-by-two version of this clock.
Due to 8-bit to 16-bit byte deserialization, the byte ordering at the
PLD-receiver interface might be incorrect. You implement the byte
ordering logic in the PLD core to correct for this situation.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–9 shows the block diagram of the byte serializer in PCI Express
(PIPE) mode.
Figure 2–9. Byte Deserializer in PCI Express (PIPE) Mode
dataout[15:0]
datain[7:0]
Byte
Deserializer
From 8B/10B
Decoder
wrclk
To Receiver Phase
Compensation
FIFO
rdclk
125 MHz
250 MHz
/2
Low-Speed Parallel CMU Clock
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In PCI Express (PIPE) mode, the 250-MHz clock generated by the CMU
clock divider block is divided by two. The resulting 125-MHz clock is
used to clock the write port of the FIFO buffer. This 125-MHz clock is also
forwarded to the PLD logic array (on the tx_clkout port in ×1 PCI
Express (PIPE) mode or the coreclkout port in ×4 PCI Express (PIPE)
mode). If the rx_coreclk port is not instantiated, the clock signal on the
tx_clkout/coreclkout port is routed back to clock the read side of
the receiver phase compensation FIFO buffer. The 16-bit PLD-receiver
interface, clocked at 125 MHz, results in an effective PCI Express (PIPE)
data rate of 2 Gbps.
In PCI Express (PIPE) mode, the receiver phase compensation FIFO is
eight words deep. The latency through the FIFO is two to three
PLD-transceiver interface clock cycles.
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 2–10 shows the block diagram of transmitter phase compensation
FIFO in PCI Express (PIPE) mode.
Figure 2–10. Receiver Phase Compensation FIFO in PCI Express (PIPE) Mode
Receiver Channel
datain[15:0]
From Byte
Deserializer
To PLD
wrclk
rdclk
125 MHz
250 MHz
rx_dataout[15:0]
Receiver Phase
Compensation
FIFO
125 MHz
/2
rx_coreclk
Low-Speed
Parallel CMU Clock
tx_clkout or
coreclkout
Receiver Status
PCI Express (PIPE) specifies a receiver status indicator that reports the
status of the PHY (PCS and PMA). In PCI Express (PIPE) mode, the
receiver status is communicated to the PLD logic by the three-bit
pipestatus port. This port reports the status, as shown in Table 2–8. If
more than one event occurs at the same time, the signal is resolved with
the higher priority status. The skip character added and removed flags
(3'b001 and 3'b010) are not supported. The pipestatus port may be
encoded to 3b'001 and 3'b010, which should be ignored. It does not
indicate that a skip has been added or removed and should be considered
the same as 3'b000—received data. If the upper MAC layer must know
when a skip character was added or removed, Altera recommends
monitoring the number of skip characters received. The transmitter
should send three skip characters in a standard skip-ordered set.
Table 2–8. pipestatus Description and Priority (Part 1 of 2)
pipestatus
Altera Corporation
May 2008
Description
Priority
3'b000
Received data
3'b001
One skip character added (not supported)
N/A
6
3'b010
One skip character removed (not supported)
N/A
3'b011
Receiver detected
1
3'b100
8B/10B decoder error
2
3'b101
Elastic buffer overflow
3
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–8. pipestatus Description and Priority (Part 2 of 2)
pipestatus
Description
Priority
3'b110
Elastic buffer underflow
4
3'b111
Received disparity error
5
Power State Management
The four supported power states in Arria GX when configured in PIPE
mode are:
■
■
■
■
PO — normal power state
POs — low recovery time
P1 — lower than PO
P2 — lowest power state
There are four supported power states in Arria GX transceivers when
configured in PIPE mode: P0, P0s, P1, and P2. P0 is the normal power
state. P0s is a low recovery time power state that is lower than P0. P1 is a
lower power state than P0s and has higher latency to come out of this
state. P2 is the lowest power state.
The powerdn port transitions the transceiver into different power states.
The encoded value is shown in Table 2–9. The pipephydonestatus
signal reacts to the powerdn request and pulses high for one parallel
clock cycle.
There are specific functions that are performed at each of the power
states. The power-down states are for PCI Express (PIPE) emulation. The
transceiver does not go into actual power saving mode, with the
exception of the transmitter buffer for Electrical Idle.
Table 2–9 shows each power state and its function.
Table 2–9. Power State Functions and Descriptions
Power State
powerdn
Function
P0
2'b00
Transmits normal data,
transmits Electrical Idle, or enters into
loopback mode.
Normal operation mode
P0s
2'b01
Only transmits Electrical Idle.
Low recovery time power saving state
P1
2'b10
Transmitter buffer is powered down and
High recovery time power saving state
can do a receiver detect while in this state.
P2
2'b11
Transmits Electrical Idle or a beacon to
wake up the downstream receiver.
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Arria GX Device Handbook, Volume 2
Description
Lowest power saving state
Altera Corporation
May 2008
PCI Express (PIPE) Mode
The two signals associated with the power states are:
tx_detectrxloopback and tx_forceelecidle. The
tx_detectrxloopback signal controls whether the channel goes into
loopback when the power state is in P0 or receiver detect when in P1 state.
This signal does not have any affect in any other power states. The
tx_forceelecidle signal governs when the transmitter goes into an
electrical idle state. The tx_forceelecidle signal is asserted in P0s
and P1 states and de-asserted in P0 state. In P2 state, under normal
conditions, the tx_forceelecidle signal is asserted and then
de-asserted when the beacon signal must be sent out, signifying the intent
to exit the P2 power-down state.
Table 2–10 shows the behavior of the tx_detectrxloopback and
tx_forceelecidle signals in the power states.
Table 2–10. Power States and Functions Allowed in Each Power State
Power State
tx_detectrxloopback
tx_forceelecidle
P0
0: normal mode
1: data path in loopback mode
0: Must be de-asserted.
1: Illegal mode
P0s
Don’t care
0: Illegal mode
1: Must be asserted in this state
P1
0: Electrical Idle
1: receiver detect
0: Illegal mode
1: Must be asserted in this state
P2
Don't care
De-asserted in this state for
sending beacon.
Otherwise asserted.
NFTS Fast Recovery IP (NFRI)
The PCI Express fast training sequences (FTS) are used for bit and byte
synchronization to transition from P0s state to P0 state. The PCI Express
standard specifies the required time period for this transition to be
between 16 ns and 4 μs. The default PCI Express (PIPE) settings do not
meet this requirement. You must enable the NFTS fast recovery IP (NFRI)
for the receiver to transition from P0s to P0 within 4 μs by selecting the
Enable fast recovery mode option in the MegaWizard Plug-In Manager.
PCI Express (PIPE) Mode Default Settings
In the PCI Express (PIPE) mode default settings (without NFRI enabled),
the receiver PLL is in automatic lock mode. The PLL moves from
lock-to-reference mode to lock-to-data mode based on the
rx_freqlocked being asserted. For the rx_freqlocked signal to be
asserted, the CRU clock should be within the PPM threshold settings of
the receiver PLL reference clock. The PPM detector checks the PPM
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
threshold settings by comparing the CRU PLL clock output with the
reference clock for approximately 32768 clock cycles. For a 250 MHz PLD
interface clock frequency, this comparison time period exceeds 4 μs,
which violates the PCI Express specification.
The NFRI, if enabled, controls the rx_locktorefclk and
rx_locktodata signals to meet the 4 μs transition time from P0s to P0
power state.
1
If you select the rx_locktorefclk and rx_locktodata
signals in the MegaWizard Plug-In Manager (CRU Manual Lock
mode), the Enable fast recovery mode option cannot be
selected.
When you select the Enable fast recovery mode option, you must
consider the following:
■
■
■
NFRI is created in the PLD side for each PCI Express (PIPE) channel
NFRI is a soft IP, so it consumes logic resources
This block is self-contained, so no input/output ports are available to
access the soft IP
Low-Latency (Synchronous) PCI Express (PIPE) Mode
The Arria GX receiver data path employs a rate match FIFO in PCI
Express (PIPE) mode to compensate up to ±300 PPM difference between
the upstream transmitter and the local receiver reference clock. The
low-latency (synchronous) PCI Express (PIPE) mode allows bypassing
the rate match FIFO in synchronous systems that derive the transmitter
and receiver reference clocks from the same source. You can bypass the
rate match FIFO by not selecting the Enable Rate Match FIFO option in
the ALT2GXB MegaWizard Plug-In Manager.
The rate match FIFO can be bypassed in both ×1 and ×4 PCI Express
(PIPE) modes. In normal PCI Express (PIPE) mode, the receiver blocks
following the rate match FIFO are clocked by tx_clkout (×1 mode) or
coreclkout (×4 mode) of the local port. In low-latency (synchronous)
PCI Express (PIPE) mode, because the rate match FIFO is bypassed, these
receiver blocks are clocked by the recovered clocks of the respective
channels.
Except for the rate match FIFO being bypassed and the resulting changes
in transceiver internal clocking, the low-latency (synchronous) PCI
Express (PIPE) mode shares the same data path and state machines as the
normal PCI Express (PIPE) mode. However, some features supported in
normal PCI Express (PIPE) mode are not supported in low-latency
(synchronous) PCI Express (PIPE) mode.
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May 2008
PCI Express (PIPE) Mode
PCI Express (PIPE) Reverse Parallel Loopback
In normal PCI Express (PIPE) mode, if the transceiver is in P0 power state,
a high value on the tx_rxdetectloop signal forces a reverse parallel
loopback, as discussed in PCI Express (PIPE) Reverse Parallel Loopback
section. Parallel data at the output of the receiver rate match FIFO gets
looped back to the input of the transmitter serializer.
In low-latency (synchronous) PCI Express (PIPE) mode, since the rate
match FIFO is bypassed, this feature is not supported. A high value on the
tx_rxdetectloop signal when the transceiver is in P1 power state will
not force it to perform reverse parallel loopback.
Link Width Negotiation
In normal ×4 PCI Express (PIPE) configuration, the receiver phase
compensation FIFO control signals (write/read enable, and so forth) are
shared among all lanes within the link. As a result, all lanes are truly
bonded and the lane-lane skew meets the PCI Express specification.
In low-latency (synchronous) PCI Express (PIPE) configuration, the
receiver phase compensation FIFO of individual lanes do not share
control signals. The write port of the receiver phase compensation FIFO
of each lane is clocked by its recovered clock. As a result, the lanes within
a link are not bonded. You should perform external lane de-skewing to
ensure proper link width negotiation.
Receiver Status
Because the rate match FIFO is bypassed in low-latency (synchronous)
PCI Express (PIPE) mode, status signal combinations related to the rate
match FIFO on the pipestatus[2:0] port become irrelevant and must
not be interpreted (Table 2–11).
Table 2–11. pipestatus Signal (Part 1 of 2)
Altera Corporation
May 2008
pipestatus[2:0]
Normal PIPE
Synchronous PIPE
000
Received Data OK
Received Data OK
001
Not supported
Not supported
010
Not supported
Not supported
011
Receiver Detected
Receiver Detected
100
8B/10B Decoder Error
8B/10B Decoder Error
101
Elastic Buffer Overflow
Not supported
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–11. pipestatus Signal (Part 2 of 2)
Gigabit Ethernet
(GIGE) mode
pipestatus[2:0]
Normal PIPE
Synchronous PIPE
110
Elastic Buffer Underflow
Not supported
111
Received Disparity Error
Received Disparity Error
IEEE 802.3 defines the 1000 Base-X PHY as an intermediate, or transition,
layer that interfaces various physical media with the media access control
(MAC) in a gigabit ethernet system. It shields the MAC layer from the
specific nature of the underlying medium. The 1000 Base-X PHY is
divided into three sub-layers:
■
■
■
Physical coding sublayer (PCS)
Physical media attachment (PMA)
Physical medium dependent (PMD)
The PCS sublayer interfaces to the MAC through the gigabit medium
independent interface (GMII). The 1000 Base-X PHY defines a physical
interface data rate of 1 Gbps.
Figure 2–11 shows the 1000 Base-X PHY position in a Gigabit Ethernet
OSI reference model.
Figure 2–11. GIGE OSI Reference Model
LAN
CSMA/CD Layers
OSI
Reference
Model Layers
Higher Layers
LLC
Application
MAC (Optional)
Presentation
MAC
Session
Transport
Network
Data Link
Reconciliation
GMII
PCS
PMA
PMD
1000 Base-X
PHY
Physical
Medium
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May 2008
Gigabit Ethernet (GIGE) mode
When Arria GX transceivers are configured in GIGE functional mode,
they provide many of the PCS and PMA functions defined in the IEEE
802.3 specification; for example:
■
■
■
■
■
1
f
8B/10B encoding/decoding
Synchronization
Upstream transmitter and local receiver clock frequency
compensation (rate matching)
Clock recovery from the encoded data forwarded by the receiver
PMD
Serialization/deserialization
Arria GX transceivers do not have built-in support for other PCS
functions, such as auto-negotiation, collision-detect, and
carrier-sense. If required, you must implement these functions
in PLD logic array or external circuits.
For more information about additional features available in the Arria GX
transceiver, refer to the GIGE-Enhanced sub-protocol in the Arria GX
Megafunction User Guide.
This section is organized into transmitter and receiver data path modules
when configured for GIGE mode. The description for each module only
covers details specific to GIGE functional mode support. This docuent
assumes that you are familiar with the IEEE 802.3 Ethernet specification.
f
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
GIGE Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
GIGE mode (Figure 2–12). The sub-blocks are described in order from the
PLD-Transceiver parallel interface to the serial transmitter buffer.
Figure 2–12. GIGE Transmitter Architecture
Transmitter PCS
PLD
Logic
Array
TX Phase
Compensation
FIFO
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Altera Corporation
May 2008
Reference
Clock
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Clock Multiplier Unit (CMU)
The clock multiplier unit takes in a reference clock and synthesizes the
clocks that are used to clock the transmitter digital logic (PCS), the
serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
In GIGE mode, the CMU block consists of:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
Input Reference Clock
You can select either a 62.5 MHz or 125 MHz input reference clock
frequency while configuring the transceiver in GIGE mode using the
Quartus II MegaWizard Plug-In Manager.
The reference clock input to the transmitter PLL can be derived from one
of three components:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide reference clock for the
transmitter PLL.
The reference clock divide-by-two pre-divider is bypassed in GIGE mode.
2–28
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May 2008
Gigabit Ethernet (GIGE) mode
Table 2–12 specifies the input reference clock options available in GIGE
mode.
Table 2–12. GIGE Mode Input Reference Clock Specification
Frequency
62.5 MHz
125 MHz
I/O Standard
1.2 V PCML,
1.5 V PCML,
3.3 V PCML, Differential LVPECL, LVDS
Coupling Termination
AC
On-chip
Clock Synthesis
In GIGE mode, the input reference clock of 125 MHz (or 62.5 MHz) is fed
to the transmitter PLL. Because the transmitter PLL implements a halfrate VCO, it multiplies the 125 MHz (or 62.5 MHz) input clock by 5 (or 10)
to generate a 625 MHz high-speed serial clock. This high-speed serial
clock feeds the local clock divider block in each GIGE channel
instantiated within the transceiver block.
The local clock divider in each channel of the transceiver block divides
the 625 MHz clock from the transmitter PLL by 5 to generate a 125 MHz
parallel clock. This low-speed parallel clock output from the local clock
divider block is used to clock the transmitter digital logic (PCS) of the
associated channel. The local clock divider block also forwards the
high-speed serial clock from the transmitter PLL to the serializer within
its associated channel.
1
Altera Corporation
May 2008
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for GIGE data rate.
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–13 shows the CMU implemented in GIGE mode.
Figure 2–13. GIGE Mode CMU
CMU Block
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider
Block
Gen(/5)
Block
625 MHz
125 MHz (62.5 MHz)
Reference
Clock
Transmitter
PLL
x5 (x10)
625 MHz
Transmitter High-Speed
Serial (625 MHz) and Low-Speed
Parallel (125 MHz) Clocks
625 MHz
Local Clock
TX Clock
Divider
Block
Gen
(/5)Block
Transmitter High-Speed
Serial (625 MHz) and Low-Speed
Parallel (125 MHz) Clocks
Transmitter Channels [1:0]
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
f
For more details about the transmitter phase compensation FIFO buffer
architecture, refer to the Transmitter Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In GIGE mode, the 125 MHz clock generated by the CMU local clock
divider is used to clock the read port of the FIFO buffer. This 125 MHz
clock is also forwarded to the PLD logic array (on the tx_clkout port).
If the tx_coreclk port is not instantiated, the clock signal on the
tx_clkout port is automatically routed back to clock the write side of
the transmitter phase compensation FIFO buffer. The 8-bit
PLD-transceiver interface clocked at 125 MHz results into an effective
GIGE data rate of 1 Gbps.
In GIGE mode, the transmitter phase compensation FIFO is four words
deep. The latency through the FIFO is two to three PLD-transceiver
interface clock cycles.
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–14 shows the block diagram of transmitter phase compensation
FIFO in GIGE mode.
Figure 2–14. Transmitter Phase Compensation FIFO in GIGE Mode
Transmitter Channel
tx_datain[7:0]
Transmitter
Phase
Compensation
FIFO
From
PLD
wrclk
dataout[7:0]
To 8B/10B
Encoder
rdclk
tx_coreclk
125 MHz
125 MHz
125 MHz
CMU
Local Clock Divider
Block
/2
tx_clkout
8B/10B Encoder
In GIGE mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control
identifier from the transmitter phase compensation FIFO and generates a
10-bit encoded data. The 10-bit encoded data is fed to the serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
GIGE Protocol — Ordered Sets and Special Code Groups
Table 2–13 lists ordered sets and special code groups used in the GIGE
functional mode.
Table 2–13. GIGE Ordered Sets (Part 1 of 2)
Altera Corporation
May 2008
Code
Group
Ordered Set
Number of
Code
Groups
Encoding
/C/
Configuration
—
Alternating /C1/ and /C2/
/C1/
Configuration 1
4
/K28.5/D21.5/Config_Reg
(1)
/C2/
Configuration 2
4
/K28.5/D2.2/Config_Reg
(1)
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–13. GIGE Ordered Sets (Part 2 of 2)
Code
Group
Ordered Set
Number of
Code
Groups
/I/
IDLE
—
/I1/
IDLE 1
2
/K28.5/D5.6
/I2/
IDLE 2
2
/K28.5/D16.2
Encapsulation
—
—
/R/
Carrier_Extend
1
/K23.7/
/S/
Start_of_Packet
1
/K27.7/
/T/
End_of_Packet
1
/K29.7/
/V/
Error_Propagation
1
/K30.7/
Encoding
Correcting /I1/, Preserving
/I2/
Note to Table 2–13:
(1)
Two data code groups representing the Config_Reg value.
Idle Ordered-Set Generation
IEEE 802.3 requires the GIGE PHY to transmit idle ordered sets (/I/)
continuously and repetitively whenever the GMII is idle. This ensures
that the receiver maintains bit and word synchronization whenever there
is no active data to be transmitted.
In GIGE functional mode, any /Dx.y/ following a /K28.5/ comma is
replaced by the transmitter with either a /D5.6/ (/I1/ ordered set) or a
/D16.2/ (/I2/ ordered set), depending on the current running disparity.
The exception is when the data following the /K28.5/ is /D21.5/ (/C1/
ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before
the /K28.5/ is positive, a /I1/ ordered set is generated. If the running
disparity is negative, a /I2/ ordered set is generated. The disparity at the
end of a /I1/ is the opposite of that at the beginning of the /I1/. The
disparity at the end of a /I2/ is the same as the beginning running
disparity (right before the idle code group). This ensures a negative
running disparity at the end of an idle ordered set. A /Kx.y/ following a
/K28.5/ is not replaced.
Figure 2–15 shows the automatic idle ordered set generation. Note that
/D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for
/I1/, /I2/ ordered sets). /D21.5/ (part of the /C1/ order set) is not
replaced.
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–15. Idle Ordered Set Generation in GIGE Mode
clock
tx_datain [ ]
K28.5
D14.3
K28.5
D24.0
K28.5
D15.8
K28.5
D21.5
Dx.y
tx_dataout
Dx.y
K28.5
D5.6
K28.5
D16.2
K28.5
D16.2
K28.5
D21.5
/I1/
Ordered Set
/I2/
/I2/
/C2/
Reset Condition
After power-up or reset, the GIGE transmitter outputs three /K28.5/
commas before user data can be sent. This affects the synchronization
ordered set transmission.
After reset (tx_digitalreset), the 8B/10B encoder automatically
sends three /K28.5/ commas. Depending on when you start outputting
the synchronization sequence, there could be an even or odd number of
/Dx.y/ sent as the transmitter before the synchronization sequence. The
last of the three automatically sent /K28.5/and the first user-sent /Dx.y/
are treated as one idle ordered set. This can be a problem if there are an
even number of /Dx.y/ transmitted before the start of the
synchronization sequence.
Figure 2–16 shows an example of even numbers of /Dx.y/ between the
last automatically sent /K28.5/ and the first user-sent /K28.5/. The first
user-sent ordered set is ignored, so three additional ordered sets are
required for proper synchronization. Figure 2–16 shows one don’t care
data between the tx_digitalreset signal going low and the first of
three automatic K28.5, but there could be more.
Figure 2–16. GIGE Synchronization Ordered Set Considerations After Reset
clock
tx_digitalreset
tx_dataout
K28.5
Altera Corporation
May 2008
xxx
K28.5
K28.5
K28.5
Dx.y
Dx.y
K28.5
Dx.y
K28.5
Dx.y
K28.5
Dx.y
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Arria GX Transceiver Protocol Support and Additional Features
Serializer
In GIGE mode, the 10-bit encoded data from the 8B/10B encoder is
clocked into the 10:1 serializer with the low-speed parallel clock at
125 MHz. The 10-bit data is clocked out of the serializer LSB to MSB at the
high-speed effective serial clock rate at 1250 MHz. The serial data output
of the serializer is fed into the transmitter output buffer.
f
For more details about the serializer architecture, refer to the Serializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
Transmitter Buffer
Table 2–14 shows the transmitter buffer settings when configured in
GIGE mode.
Table 2–14. Transmitter Buffer Settings in GIGE Mode
Settings
Value
I/O Standard
1.5-V PCML (1)
Programmable Differential Output
Voltage (VOD)
400 — 1200 mV
Common Mode Voltage (VCM)
Differential Termination
600 mV, 700 mV (1)
100 Ω (2)
Programmable Transmitter PreEmphasis
Enabled (3)
VCCH (Transmitter Buffer Power)
1.5 V
Notes to Table 2–14:
(1)
(2)
(3)
The common mode voltage (VCM) setting is selectable in the MegaWizard
Plug-In Manager.
The I/O standard and differential termination settings are defaulted to 1.5-V
PCML and 100 Ω , respectively. If you select any other setting for I/O standard
or differential termination in the Assignment Editor, the Quartus II compiler
will issue an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
GIGE Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in
GIGE mode (Figure 2–17). The sub-blocks are described in order from the
serial receiver input buffer to the receiver phase compensation FIFO
buffer at the transceiver-PLD interface.
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–17. GIGE Mode Receiver Architecture
Receiver PMA
Receiver PCS
PLD
Logic
Array
RX Phase
Compensation
FIFO
8B/10B
Decoder
Rate
Match
FIFO
DeSerializer
Word
Aligner
Clock
Recovery
Unit
Receiver
PLL
Reference
Clocks
Receiver Buffer
Table 2–15 shows the receiver buffer settings when configured in GIGE
mode.
Table 2–15. Receiver Buffer Settings in GIGE Mode
Settings
I/O Standard
Input Common Mode Voltage (Rx VCM)
Differential Termination
Programmable Equalization
Coupling
Value
1.2-V PCML, 1.5-V PCML,
3.3-V PCML, Differential LVPECL,
LVDS
850 mV, 1200 mV (1)
100 Ω (2)
Enabled (3)
AC
Notes to Table 2–15:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω . If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler will issue an error message.
The receiver buffer has five programmable equalization settings.
Receiver PLL and Clock Recovery Unit
In GIGE mode, the receiver PLL in each transceiver channel is fed by a
125 MHz or a 62.5 MHz input reference clock. The receiver PLL in
conjunction with the CRU generates two clocks: a high-speed serial
recovered clock at 625 MHz (half-rate PLL) that feeds the deserializer and
a low-speed parallel recovered clock at 125 MHz that feeds the receiver’s
digital logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switches the
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between
lock-to-reference and lock-to-data modes via the rx_locktorefclk
and rx_locktodata signals.
f
For more details about the CRU lock modes, refer to the Receiver PLL
and Clock Recovery Unit section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
The reference clock input to the receiver PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Table 2–16 specifies the input reference clock options available in GIGE
mode.
Table 2–16. GIGE Mode Input Reference Clock Specification
Frequency
125 MHz
62.5 MHz
I/O Standard
Coupling
Termination
1.2 V PCML,
1.5 V PCML,
3.3 V PCML, Differential LVPECL, LVDS
AC
On-chip
Deserializer
The 1:10 deserializer clocks in serial data from the receiver buffer using
the high-speed recovered clock. The 10-bit de-serialized data is clocked
out to the word aligner using the low-speed recovered clock at 125 MHz.
The deserializer assumes that the transmission bit order is LSB to MSB;
for example, the LSB of a data word is received earlier in time than its
MSB.
f
For more details about the deserializer architecture, refer to the
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
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May 2008
Gigabit Ethernet (GIGE) mode
Word Aligner
The word aligner clocks in the 10-bit data from the deserializer and
restores the word boundary of the upstream transmitter. Besides
restoring the word boundary, it also implements a synchronization state
machine as specified in the IEEE 802.3 specification to achieve receiver
synchronization.
In GIGE mode, the word aligner is comprised of the following three
modules:
■
■
■
Pattern detector module
Pattern aligner module
Run-length violation detector module
Pattern Detector
In GIGE mode, the Quartus II software automatically configures 10-bit
K28.5 (10'b0101111100) as the word alignment pattern. After coming out
of reset (rx_digitalreset), when the pattern detector detects either
disparities of the K28.5 control word, it asserts the rx_patterndetect
signal for one parallel clock cycle. When the pattern aligner has aligned
the incoming data to the desired word boundary, the pattern detector
asserts the rx_patterndetect signal only if the word alignment
pattern is found in the current word boundary.
Pattern Aligner
In GIGE mode, the pattern aligner incorporates an automatic
synchronization state machine. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization
when the receiver receives three consecutive synchronization ordered
sets. An ordered set defined for synchronization is a /K28.5/ code group
followed by an odd number of valid /Dx.y/ code groups. The fastest way
for the receiver to achieve synchronization is to receive three continuous
{/K28.5/, /Dx.y/} ordered sets.
Receiver synchronization is indicated on the rx_syncstatus port of
each channel. A high on the rx_syncstatus port indicates that the lane
is synchronized and a low indicates that it has fallen out of
synchronization. The receiver loses synchronization when it detects four
invalid code groups separated by less than three valid code groups or
when it is reset.
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–17 lists the synchronization state machine parameters when
configured in GIGE mode.
Table 2–17. Synchronization State Machine Parameters in GIGE Mode
Number of valid {/K28.5/, /Dx,y/} ordered-sets received to achieve synchronization
3
Number of errors received to lose synchronization
4
Number of continuous good code groups received to reduce the error count by 1
4
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–18 shows the synchronization state machine implemented in
GIGE mode.
Figure 2–18. GIGE Synchronization State Machine
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
The word aligner block asserts an error flag on the rx_disperr and
rx_errdetect ports if the received 10-bit code is detected with
incorrect running disparity. The error flag signal (rx_disperr) has the
same delay from the word aligner to the PLD-transceiver interface as the
received data.
Rate Matcher
In GIGE mode, the rate matcher can compensate up to ±100 PPM
(200 PPM total) frequency difference between the upstream transmitter
and the receiver. The write port of the rate matcher FIFO in each receiver
channel is clocked by its low-speed parallel recovered clock. The read
port is clocked by the low-speed parallel clock output of the CMU local
clock divider block.
The rate matcher logic inserts or deletes /I2/ idle ordered-sets to/from
the rate matcher FIFO during the inter-frame or inter-packet gap (IFG or
IPG). /I2/ is selected as the rate matching ordered-set since it maintains
the running disparity unlike /I1/ that alters the running disparity. Since
the /I2/ ordered-set contains two 10-bit code groups (/K28.5/, /D16.2/),
twenty bits are inserted or deleted at a time for rate matching.
1
f
The rate matcher logic has the capability to insert or delete /C1/
or /C2/ configuration ordered sets when GIGE-Enhanced mode
is chosen as the sub-protocol in the MegaWizard Plug-In
Manager.
Refer to the Arria GX ALT2GXB Megafunction User Guide for details on
GIGE-Enhanced mode.
Figure 2–19 shows an example of /I2/ deletion and Figure 2–20 shows an
example of /I2/ insertion in a GIGE mode rate matcher.
Figure 2–19. GIGE Rate Matcher /I2/ Deletion
/D/
/D/
/D/
From Rate Matcher
/D/
/D/
/D/
/S/
/D/
/I2/ /I2/
/D/
/D/
To Rate Matcher
/I1/
/D/
/D/
/S/
/I2/
/I1/
One /I2/ Code Removed
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Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–20. GIGE Rate Matcher /I2/ Insertion
/D/
/D/
From Rate Matcher
/D/
/D/
/D/
/D/
/S/
/D/
/I2/
/D/
/I2/
/D/
To Rate Matcher
/I1/
/D/
/D/
/S/
/I2/
/I2/
/I2/
/I1/
One /I2/ Code Added
If the frequency PPM difference between the upstream transmitter and
the local receiver is high or if the packet size is too large, the rate matcher
FIFO buffer can face an overflow or underflow situation.
8B/10B Decoder
In GIGE mode, the 8B/10B decoder clocks in 10-bit data from the rate
matcher and decodes it into 8-bit data + 1-bit control identifier. The 10-bit
decoded data is fed to the receiver phase compensation FIFO buffer.
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
Receiver Phase Compensation FIFO
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about the receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO section in
the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook.
In GIGE mode, the 125 MHz clock generated by the CMU local clock
divider block clocks the write port of the FIFO buffer. This 125 MHz clock
is also forwarded to the PLD logic array (on the corresponding
tx_clkout port). If the rx_coreclk port is not instantiated, the clock
signal on the tx_clkout port is automatically routed back to clock the
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
read side of the receiver phase compensation FIFO buffer. The 8-bit
PLD-receiver interface clocked at 125 MHz results in an effective GIGE
data rate of 1 Gbps.
In GIGE mode, the receiver phase compensation FIFO is four words deep.
The latency through the FIFO is one to two PLD-transceiver interface
clock cycles.
Figure 2–21 shows the block diagram of receiver phase compensation
FIFO in GIGE mode.
Figure 2–21. Receiver Phase Compensation FIFO in GIGE Mode
Receiver Channel
rx_dataout[7:0]
datain[7:0]
Receiver Phase
Compensation
FIFO
From 8B/10B
Decoder
To PLD
wrclk
Low-Speed Parallel
CMU Clock
125 MHz
125 MHz
/2
rdclk
rx_coreclk
125 MHz
tx_clkout
UNH-IOL Gigabit Ethernet Compliance
For UNH-IOL compliance in GIGE mode, the following architectural
features are available when GIGE-Enhanced sub-protocol is chosen in the
Megawizard Plug-In Manager.
■
■
f
7-bit word alignment using the synchronization state machine.
Insertion and deletion of /C1/ and /C2/configuration ordered sets
by the rate matcher during the Auto-negotiation phase.
Refer to the Arria GX ALT2GXB Megafunction User Guide for details
regarding additional ports generated for GIGE-Enhanced mode.
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Altera Corporation
May 2008
Serial RapidIO Mode
Serial RapidIO
Mode
The RapidIO standard is a high-performance, packet-switched
interconnect technology designed to pass data and control information
between microprocessors, digital signal, communications, and network
processors, system memories, and peripheral devices. Serial RapidIO
physical layer specification defines three line rates at 1.25 Gbps, 2.5 Gbps,
and 3.125 Gbps. It also supports two link widths — single-lane (×1) and
bonded four-lane (×4) at each line rate.
Arria GX transceivers support both single-lane (×1) and four-lane (×4)
Serial RapidIO link widths at 1.25 Gbps and 2.5 Gbps and single-lane link
widths at 3.125 Gbps. In ×4 Serial RapidIO mode, the four transceiver
channels are not bonded and are clocked independently, as four
individual channels.
When configured in Serial RapidIO functional mode, Arria GX
transceivers provide the following PCS and PMA functions:
■
■
■
■
■
1
8B/10B encoding/decoding
Word alignment
Lane Synchronization State Machine
Clock recovery from the encoded data
Serialization/deserialization
Arria GX transceivers do not have built-in support for other PCS
functions, such as clock frequency compensation between
upstream transmitter clock and local receiver clock (rate
matcher), idle sequence generation, and lane alignment in ×4
mode. Depending on your system requirements, you must
implement these functions in the logic array or external circuits.
This section is organized into transmitter and receiver data path modules
when configured for Serial RapidIO mode. The description for each
module only covers details specific to Serial RapidIO functional mode
support. This document assumes that you are familiar with the RapidIO
Interconnect Specification v1.3.
f
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
Serial RapidIO Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
Serial RapidIO mode (Figure 2–22). The sub-blocks are described from
the PLD-Transceiver parallel interface to the serial transmitter buffer.
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–22. Serial RapidIO Transmitter Architecture
Transmitter PCS
PLD
Logic
Array
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Reference
Clock
Clock Multiplier Unit (CMU)
The clock multiplier unit takes in a reference clock and synthesizes the
clocks that are used to clock the transmitter digital logic (PCS), the
serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
In Serial RapidIO mode, the CMU block consists of:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
Input Reference Clock
Table 2–18 lists the input reference clock frequencies allowed in Serial
RapidIO mode.
The reference clock input to the transmitter PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
2–44
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Altera Corporation
May 2008
Serial RapidIO Mode
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide reference clock for the
transmitter PLL.
Table 2–18. Serial RapidIO Mode Input Reference Clock Specifications
Data Rate
(Gbps)
Reference Clock Frequency (MHz)
I/O Standard
1.25
62.5, 78.125, 125, 156.25, 250, 312.5
2.5
50, 62.5, 78.125, 100, 125, 156.25, 250,
312.5, 500
3.125
Coupling Termination
1.2V PCML, 1.5V PCML, 3.3V
PCML, Differential LVPECL,
LVDS
AC
On-chip
62.5, 78.125, 97.6563, 125, 156.25,
195.3125, 312.5, 390.625
Clock Synthesis
In Serial RapidIO mode, the input reference clock is fed to the transmitter
PLL. Because the transmitter PLL implements a half-rate VCO, it
multiplies the input reference clock to generate a 625-MHz (1.25-Gbps
Serial RapidIO) or 1250-MHz (2.5 Gbps Serial RapidIO) or 1562.5-MHz
(3.125-Gbps Serial RapidIO) high-speed serial clock. This high-speed
serial clock feeds the local clock divider block in each Serial RapidIO
channel instantiated within the transceiver block. Table 2–19 lists the
transmitter PLL multiplication factors that the Quartus II software
automatically selects, depending on the Serial RapidIO data rate and
input reference clock frequency selection.
Table 2–19. Serial RapidIO Mode Transmitter PLL Multiplication Factors
(Part 1 of 2)
Data Rate
(Gbps)
1.25
Altera Corporation
May 2008
Reference Clock
Frequency (MHz)
Transmitter PLL Multiplication
Factor
62.5
10
78.125
8
125
5
156.25
4
250 (pre-divide by 2)
5
312.5
2
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–19. Serial RapidIO Mode Transmitter PLL Multiplication Factors
(Part 2 of 2)
Data Rate
(Gbps)
2.5
3.125
Reference Clock
Frequency (MHz)
Transmitter PLL Multiplication
Factor
50
25
62.5
20
78.125
16
100 (pre-divide by 2)
25
125
10
156.25
8
250
5
312.5
4
500 (pre-divide by 2)
5
62.5
25
78.125
20
97.6563
16
125 (pre-divide by 2)
25
156.25
10
195.3125
8
312.5
5
390.625 (pre-divide by 2)
8
In Serial RapidIO 1.25-Gbps (2.5-Gbps, 3.125-Gbps) mode, the local clock
divider in each channel of the transceiver block divides the 625-MHz
(1250-MHz, 1562.5-MHz) clock from the transmitter PLL by five to
generate a 125-MHz (250-MHz, 312.5-MHz) parallel clock. This
low-speed parallel clock output from the local clock divider block is used
to clock the transmitter digital logic (PCS) of the associated channel. The
local clock divider block also forwards the high-speed serial clock from
the transmitter PLL to the serializer within its associated channel.
1
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for Serial RapidIO data rate.
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
2–46
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
f
For more details about the transmitter phase compensation FIFO buffer
architecture, refer to the transmitter Phase Compensation FIFO section in
the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook.
In Serial RapidIO 1.25-Gbps (2.5-Gbps, 3.125-Gbps) mode, the 125-MHz
(250-MHz, 312.5-MHz) clock generated by the CMU clock divider block
is divided by 2. The resulting 62.5-MHz (125-MHz, 156.25-MHz) clock is
used to clock the read port of the FIFO buffer. This divide-by-two clock is
also forwarded to the PLD logic array (on the tx_clkout port of its
associated channel). If the tx_coreclk port is not instantiated, the clock
signal on the tx_clkout port is automatically routed back to clock the
write side of the transmitter phase compensation FIFO buffer. The 16-bit
PLD-transceiver interface clocked at 62.5 MHz (125 MHz, 156.25 MHz)
results into an effective Serial RapidIO data rate of 1.25 Gbps (2.5 Gbps,
3.125 Gbps).
In Serial RapidIO mode, the transmitter phase compensation FIFO is four
words deep. The latency through the FIFO is two to three
PLD-transceiver interface clock cycles.
Figure 2–23 shows the block diagram of transmitter phase compensation
FIFO in Serial RapidIO mode.
Figure 2–23. Transmitter Phase Compensation FIFO in Serial RapidIO Mode Note (1)
Transmitter Channel
From
PLD
tx_coreclk
dataout[15:0]
Transmitter
Phase
Compensation
FIFO
tx_datain[15:0]
wrclk
62.5 MHz
(125 MHz, 156.25 MHz)
To 8B/10B
Encoder
rdclk
62.5 MHz
(125 MHz, 156.25 MHz)
125 MHz (250 MHz, 312.5)
/2
CMU
Local Clock Divider
Block
tx_clkout
Note to Figure 2–23:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Byte Serializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the
PLD-transceiver interface data is 16 bits wide and is clocked into the
transmitter phase compensation FIFO at 62.5 MHz (125 MHz,
156.25 MHz). The byte serializer clocks in the 16-bit wide data from the
transmitter phase compensation FIFO at 62.5 MHz (125 MHz,
156.25 MHz) and clocks out 8-bit data to the 8B/10B encoder at 125 MHz
(250 MHz, 312.5 MHz). This allows clocking the PLD-transceiver
interface at half the speed.
f
For more details about the byte serializer architecture, refer to the Byte
Serializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
The write port of the byte serializer is clocked by the divide-by-two
version of the low-speed parallel clock from CMU. The read port is
clocked by the low-speed parallel clock from CMU. The byte serializer
clocks out the least significant byte of the 16-bit data first and the most
significant byte last.
Figure 2–24 shows the block diagram of the byte serializer in Serial
RapidIO mode.
Figure 2–24. Byte Serializer in Serial RapidIO Mode Note (1)
datain[15:0]
dataout[7:0]
Byte Serializer
From Transmitter
Phase Compensation
FIFO
To 8B/10B
Encoder
wrclk
rdclk
125 MHz (250 MHz, 312.5 MHz)
62.5 MHz (125 MHz, 156.25 MHz)
62.5 MHz
(125 MHz, 156.25 MHz)
Divide-by-Two Version
of Low-Speed
Parallel Clock
/2
125 MHz
(250 MHz, 312.5 MHz)
Low-Speed
Parallel Clock
CMU
Local/Central Clock
Divider Block
Note to Figure 2–24:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
2–48
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Altera Corporation
May 2008
Serial RapidIO Mode
8B/10B Encoder
In Serial RapidIO mode, the 8B/10B encoder clocks in 8-bit data and 1-bit
control identifier from the transmitter phase compensation FIFO and
generates a 10-bit encoded data. The 10-bit encoded data is fed to the
serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
Serializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the 10-bit
encoded data from the 8B/10B encoder is clocked into the 10:1 serializer
with the low-speed parallel clock at 125 MHz (250 MHz, 312.5 MHz). The
10-bit data is clocked out of the serializer LSB to MSB at the high-speed
effective serial clock rate at 1250 MHz (2500 MHz, 3125 MHz). The serial
data output of the serializer is fed into the transmitter output buffer.
f
For more details about the serializer architecture, refer to the Serializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
Transmitter Buffer
Table 2–20 shows the transmitter buffer settings when configured in
Serial RapidIO mode.
Table 2–20. Transmitter Buffer Settings in Serial RapidIO Mode
(Part 1 of 2)
Settings
I/O Standard
1.5-V PCML (1)
Programmable Differential Output
Voltage (VOD)
400 - 1200 mV
Common Mode Voltage (VCM)
Differential Termination
Programmable pre-emphasis
Altera Corporation
May 2008
Value
600 mV, 700 mV (1)
100 Ω (2)
Enabled (3)
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–20. Transmitter Buffer Settings in Serial RapidIO Mode
(Part 2 of 2)
Settings
Value
VCCH (Transmitter Buffer Power)
1.5 V
Notes to Table 2–20:
(1)
(2)
(3)
The common mode voltage (VCM) setting is selectable in the MegaWizard Plug-In
Manager.
The I/O standard and differential termination settings are defaulted to 1.5-V
PCML and 100 Ω , respectively. If you select any other setting for the I/O standard
or differential termination in the Assignment Editor, the Quartus II compiler
issues an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
Serial RapidIO Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in
Serial RapidIO mode (Figure 2–25). The sub-blocks are described in order
from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 2–25. Serial RapidIO Mode Receiver Architecture
Receiver PCS
PLD
Logic
Array
RX Phase
Compensation FIFO
Byte
DeSerializer
8B/10B
Decoder
Word
Aligner
Receiver PMA
DeSerializer
Clock
Recovery
Unit
Receiver
PLL
Reference
Clocks
Receiver Buffer
Table 2–21 shows the receiver buffer settings when configured in Serial
RapidIO mode.
Table 2–21. Receiver Buffer Settings in Serial RapidIO Mode (Part 1 of 2)
Settings
I/O Standard
Input Common Mode Voltage (Rx VCM)
2–50
Arria GX Device Handbook, Volume 2
Value
1.2-V PCML, 1.5-V PCML,
3.3-V PCML, Differential LVPECL,
LVDS
850 mV, 1200 mV (1)
Altera Corporation
May 2008
Serial RapidIO Mode
Table 2–21. Receiver Buffer Settings in Serial RapidIO Mode (Part 2 of 2)
Settings
Value
100 Ω (2)
Differential Termination
Enabled (3)
Programmable Equalization
Coupling
AC
Notes to Table 2–21:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω . If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler issues an error message.
The receiver buffer has five programmable equalization settings.
Receiver PLL and Clock Recovery Unit
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the receiver
PLL in each transceiver channel is fed by an input reference clock. The
receiver PLL in conjunction with the clock recovery unit generates two
clocks: a half-rate high-speed serial recovered clock at 625 MHz
(1250 MHz, 1562.5 MHz) that feeds the deserializer and a low-speed
parallel recovered clock at 125 MHz (250 MHz, 312.5 MHz) that feeds the
receiver’s digital logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switch the
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between
lock-to-reference and lock-to-data modes via the rx_locktorefclk
and rx_locktodata signals.
f
For more details about the CRU lock modes, refer to the Receiver PLL
section and Clock Recovery Unit (CRU) section in the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
The reference clock input to the receiver PLL can be derived from one of
the following components:
■
■
■
Altera Corporation
May 2008
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–22 specifies the receiver input reference clock options available in
Serial RapidIO mode.
Table 2–22. Serial RapidIO Mode Input Reference Clock Specifications
Data Rate
(Gbps)
Reference Clock Frequency
(MHz)
1.25
62.5, 78.125,125, 156.25,
250, 312.5
2.5
50, 62.5, 78.125, 100, 125,
156.25, 250, 312.5, 500
3.125
62.5, 78.125, 97.6563, 125,
156.25, 195.3125, 312.5,
390.625
I/O Standard
1.2 V PCML, 1.5 V PCML, 3.3 V PCML,
Differential LVPECL, LVDS
Coupling Termination
AC
On-chip
Deserializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the 1:10
deserializer clocks in serial data from the receiver buffer using the
high-speed serial recovered clock. The 10-bit de-serialized data is clocked
out to the word aligner using the low-speed parallel recovered clock at
125 MHz (250 MHz, 312.5 MHz). The deserializer assumes that the
transmission bit order is LSB to MSB; that is, the LSB of a data word is
received earlier in time than its MSB.
f
For more details on the deserializer architecture, refer to the Deserializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
Word Aligner
The word aligner clocks in the 10-bit data from the deserializer and
restores the word boundary of the upstream transmitter.
f
For more details about the word aligner architecture, refer to the section
“Word Aligner” on page 2–13 in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
In Serial RapidIO mode, the word aligner comprises of the following
three modules:
■
■
■
Pattern detector module
Pattern aligner module
Run-length violation detection module
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Altera Corporation
May 2008
Serial RapidIO Mode
Pattern Detector
In Serial RapidIO mode, the Quartus II software automatically configures
10-bit K28.5 (10'b0101111100) as the word alignment pattern. After
coming out of reset (rx_digitalreset), when the pattern detector
detects either disparities of the K28.5 control word, it asserts the
rx_patterndetect signal for one parallel clock cycle. When the
pattern aligner has aligned the incoming data to the desired word
boundary, the pattern detector asserts rx_patterndetect signal only
if the word alignment pattern is found in the current word boundary.
Pattern Aligner
In Serial RapidIO mode, the pattern aligner employs an automatic
synchronization state machine. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization
when the receiver receives 127 K28.5 (10'b0101111100 or 10'b1010000011)
synchronization code groups without receiving an intermediate invalid
code group. Once synchronized, the state machine indicates loss of
synchronization when it detects three invalid code groups separated by
fewer than 255 valid code groups or when it is reset.
Receiver synchronization is indicated on the rx_syncstatus port of
each channel. A high on the rx_syncstatus port indicates that the lane
is synchronized and a low indicates that it has fallen out of
synchronization.
Table 2–23 lists the synchronization state machine parameters when
configured in Serial RapidIO mode.
Table 2–23. Synchronization State Machine Parameters in Serial RapidIO
Mode
Number of valid K28.5 code groups received to achieve
synchronization
Number of errors received to lose synchronization
Number of continuous good code groups received to reduce
the error count by 1
1
Altera Corporation
May 2008
127
3
255
In an 8B/10B encoded data stream, a /K28.7/ special code
group followed by any of the data code groups /D3.y/,
/D11.y/, /D12.y/, /D19.y/, /D20.y/, /D28.y/ or /K28.y/
(where y ranges from 0 to 7), may cause the /K28.5/ alignment
pattern to appear across the word boundary. Serial RapidIO
protocol allows /K28.7/ transmission only during test and
debug.
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Arria GX Transceiver Protocol Support and Additional Features
Figure 2–26 shows the synchronization state machine implemented in
Serial RapidIO functional mode.
Figure 2–26. Synchronization State Machine in Serial RapidIO Mode
Loss of Sync
Data = Comma
Data = !Valid
Comma Detect
if Data == Comma
kcntr++
else
kcntr=kcntr
Data = valid;
kcntr <3
kcntr = 127
Synchronized
Data=Valid
Data = !Valid
ecntr = 3
Synchronized Error
Detect
if Data == !valid
ecntr++
gcntr=0
else
if gcntr==255
ecntr-gcntr=0
else
gcntr++
ecntr = 0
The word aligner block asserts an error flag on the rx_disperr and
rx_errdetect ports if the received 10-bit code is detected with
incorrect running disparity. The error flag signal (rx_disperr) has the
same delay from the word aligner to the PLD-transceiver interface as the
received data.
8B/10B Decoder
In Serial RapidIO mode, the 8B/10B decoder clocks in 10-bit data from the
word aligner and decodes it into 8-bit data + 1-bit control identifier. The
8-bit decoded data is fed to the byte deserializer.
2–54
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Altera Corporation
May 2008
Serial RapidIO Mode
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Decoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
Byte Deserializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the
PLD-receiver interface data is 16 bits wide and is clocked out of the
receiver phase compensation FIFO at 62.5 MHz (125 MHz, 156.25 MHz).
The byte deserializer clocks in the 8-bit wide data from the 8B/10B
decoder at 125 MHz (250 MHz, 312.5 MHz) and clocks out 16-bit wide
data to the receiver phase compensation FIFO at 62.5 MHz (125 MHz,
156.25 MHz). This allows clocking the PLD-transceiver interface at half
the speed.
f
For more details about byte deserializer architecture, refer to the Byte
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In Serial RapidIO mode, the write port of the byte deserializer is clocked
by the low-speed parallel recovered clock and the read port is clocked by
divide-by-two version of this clock.
Due to 8-bit to 16-bit byte deserialization, the byte ordering at the
PLD-receiver interface might be incorrect. If required, you must
implement the byte ordering logic in the PLD core to correct for this
situation.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–27 shows the block diagram of the byte deserializer in Serial
RapidIO mode.
Figure 2–27. Byte Deserializer in Serial RapidIO Mode Note (1)
dataout[15:0]
datain[7:0]
Byte
Deserializer
To Receiver Phase
Compensation
FIFO
From 8B/10B
Decoder
wrclk
rdclk
62.5 MHz (125 MHz, 156.25 MHz)
125 MHz (250 MHz, 312.5 MHz)
/2
Low-Speed Parallel Recovered Clock
Note to Figure 2–27:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about the receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the 125 MHz
(250 MHz, 312.5 MHz) low-speed parallel recovered clock is divided by
2. The resulting 62.5 MHz (125 MHz, 156.25 MHz) clock is used to clock
the write port of the FIFO buffer. This divide-by-two clock is also
forwarded to the PLD logic array (on the rx_clkout port). If the
rx_coreclk port is not instantiated, the recovered clock signal on the
rx_clkout port is automatically routed back to clock the read side of the
receiver phase compensation FIFO buffer. The 16-bit PLD-receiver
interface clocked at 62.5 MHz (125 MHz, 156.25 MHz) results into an
effective Serial RapidIO data rate of 1 Gbps (2 Gbps, 3.125 Gbps).
In Serial RapidIO mode, the receiver phase compensation FIFO is four
words deep. The latency through the FIFO is one to two PLD-transceiver
interface clock cycles.
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Altera Corporation
May 2008
Basic Single-Width Mode
Figure 2–28 shows the block diagram of receiver phase compensation
FIFO in Serial RapidIO mode.
Figure 2–28. Receiver Phase Compensation FIFO in RapidIO Mode Note (1)
Receiver Channel
datain[15:0]
From Byte
Deserializer
wrclk
62.5 MHz (125 MHz, 156.25 MHz)
125 MHz (250 MHz, 312.5 MHz)
/2
rx_dataout[15:0]
Receiver Phase
Compensation
FIFO
To PLD
rdclk
rx_coreclk
62.5 MHz (125 MHz, 156.25 MHz)
Low -speed parallel
recovered clock
rx_clkout
Note to Figure 2–28:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
Basic
Single-Width
Mode
Use the Basic single-width mode for custom protocols that are not part of
the pre-defined supported protocols; for example, PIPE. With some
restrictions, the following PCS blocks are available:
■
■
■
■
■
■
■
■
■
Transmitter phase compensation FIFO buffer
Transmitter byte serializer
8B/10B encoder
Word aligner
Rate matcher
8B/10B decoder
Byte deserializer
Byte ordering block
Receiver phase compensation FIFO buffer
The byte ordering block is available only in reverse serial loopback
configuration in Basic mode. The rate matcher is coupled with the 8B/10B
code groups, which requires the use of the 8B/10B encoder or decoder
either in the PCS or PLD logic array.
Basic Single-Width Mode with x4 Clocking
In Basic single-width mode, the ALT2GXB MegaWizard Plug-In Manager
provides a ×4 option under the Which subprotocol will you be using?
option. If you select this option, all four transmitter channels within the
Altera Corporation
May 2008
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Arria GX Transceiver Protocol Support and Additional Features
transceiver block are clocked by clocks generated from the central clock
divider block. The low-speed clock from the central clock divider block
clocks the bonded transmitter PCS logic in all four channels. This reduces
the transmitter channel-to-channel skew within the transceiver block.
Each receiver channel within the transceiver block is clocked individually
by the recovered clock from its own CRU.
1
Configuring transceivers in this mode yields low transmitter
channel-to-channel skew within a transceiver block. It does not
provide skew reduction for channels placed across transceiver
blocks.
Figure 2–29 shows the data path in this mode.
Figure 2–29. Basic Single-Width Mode with ×4 Clocking
Transmitter Digital Logic
TX Phase
Compensation
FIFO
Byte
Serializer
Analog Receiver and
Transmitter Logic
8B/10B
Encoder
Serializer
FPGA
Logic
Array
RX Phase
Compensation
FIFO
Byte
Ordering
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
The transmitter data path consists of a 16-bit PLD-transceiver interface,
transmitter phase compensation FIFO, 16:8-bit byte serializer, and 8:1
serializer.
The receiver data path consists of the CRU, 1:8 deserializer, bit-slip word
aligner, 8:16 byte deserializer, receiver phase compensation FIFO, and 16bit Transceiver-PLD interface.
Transceiver Placement Limitations
If one or more channels in a transceiver block are configured to Basic
single-width mode with ×4 clocking option enabled, the remaining
channels in that transceiver block must either have the same
configuration or must be unused. All used channels within a transceiver
block configured to this mode must also run at the same data rate. All
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May 2008
Basic Single-Width Mode
channels within the transceiver block configured to this mode must be
instantiated using the same ALT2GXB MegaWizard Plug-In Manager
instance.
Figures 2–30 and 2–31 show examples of legal and illegal transceiver
placements with respect to the Basic single-width mode with ×4 clocking
enabled.
Figure 2–30. Examples of Legal Transceiver Placement
Ch0
Basic Single-Width mode with x4
clocking option enabled
Ch0
Ch1
Basic Single-Width mode with x4
clocking option enabled
Ch1
Basic Single-Width mode with x4
clocking option disabled
Ch2
Unused Channel
Ch2
Serial RapidIO
Ch3
Unused Channel
Ch3
Basic Single-Width mode with x4
clocking option disabled
Serial RapidIO
Figure 2–31. Examples of Illegal Transceiver Placement
Ch0
Basic Single-Width mode with x4
clocking option enabled
Ch0
Basic Single-Width mode with x4
clocking option enabled
Ch1
Basic Single-Width mode with x4
clocking option enabled
Ch1
Basic Single-Width mode with x4
clocking option enabled
Ch2
Serial RapidIO
Ch2
Basic Single-Width mode with x4
clocking option disabled
Ch3
Serial RapidIO
Ch3
Basic Single-Width mode with x4
clocking option disabled
Clocking and Reset Recommendations
To minimize the transmitter channel to channel skew across transceiver
blocks, Altera recommends that you follow the protocols listed below:
■
■
Altera Corporation
May 2008
Using the dedicated REFCLK pins of the centrally located transceiver
block in your design to provide the input reference clock for all
transceiver blocks. This reduces the skew on the input reference
clock driving the CMU PLL in each transceiver block. For example,
in a design with 12 channels placed across Banks 13, 14, and 15, use
the REFCLK pins of Bank 14 to provide the input reference clock.
De-asserting the tx_digitalreset signal of all used transceiver
blocks simultaneously after pll_locked signal from all active
transceiver blocks goes high.
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–32 shows the recommended clocking for 12 transceiver channels
across transceiver banks 13, 14, and 15 in the EP1AGX90EF1152 device.
Figure 2–32. Clocking Recommendations to Minimize Transmitter
Channel-To-Channel Skew
Bank13
Four Channels in
Basic x4 clocking
mode
Inter-transceiver
block (IQ) clock
pll_inclk
Bank14
Four Channels in
Basic x4 clocking
mode
pll_inclk
REFCLK_B14
Bank15
Four Channels in
Basic x4 clocking
mode
Inter-transceiver
block (IQ) clock
XAUI Mode
pll_inclk
This section briefly introduces the XAUI standard and the code groups
and ordered sets associated with this self-managed interface. For full
details about the XAUI standard, refer to clause 47 and 48 in the 10
Gigabit Ethernet standard (IEEE 802.3ae).
Arria GX devices contain embedded macros dedicated to the XAUI
protocol, including synchronization, channel deskew, rate matching,
XGMII Extender Sublayer (XGXS) to 10 Gigabit Media Independent
Interface (XGMII) and XGMII to XGXS code-group conversion macros.
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May 2008
XAUI Mode
The XAUI standard is an optional self-managed interface that is inserted
between the reconciliation sublayer and the PHY layer to transparently
extend the physical reach of XGMII.
This section is organized into transmitter and receiver data path modules
when configured for XAUI mode. The description for each module only
covers details specific to XAUI functional mode support.
f
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
XAUI addresses several physical limitations of XGMII. XGMII signaling
is based on the HSTL Class I single-ended I/O standard, which has an
electrical distance limitation of approximately 7 cm. XAUI uses a
low-voltage differential signaling method, so the electrical limitation is
increased to approximately 50 cm. Another advantage of XAUI is the
simplification of backplane and board trace routing. XGMII is composed
of 32 transmit channels, 32 receive channels, one transmit clock, one
receive clock, four transmitter control characters, and four receive control
characters for a total of a 74-pin wide interface. XAUI consists of four
differential transmitter channels and four differential receiver channels
for a total of a 16-pin wide interface. This reduction in pin count
significantly simplifies the routing process in the layout design.
Figure 2–33 shows the relationships between the XGMII and XAUI layers.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–33. XGMII and XAUI Relationship
LAN
CSMA/CD Layers
Higher Layers
LLC
OSI
Reference
Model Layers
MAC (Optional)
MAC
Application
Reconciliation
Presentation
XGMII
XGXS
Session
XAUI
Transport
XGXS
Optional XGMII
Extender
XGMII
Network
PCS
Data Link
PMA
PHY
PMD
Physical
MDI
Medium
10 Gb/s
Media Access Control (MAC)
Medium Dependent Interface (MDI)
Physical Coding Sublayer (PCS)
Physical Layer Device (PHY)
Logical Link Control (LLC)
Physical Medium Attachment (PMA)
Physical Medium Dependent (PMD)
10 Gigabit Attachment Unit Interface (XAUI)
10 Gigabit Media Independent Interface (XGMII)
XGMII Extender Sublayer (XGXS)
The XGMII interface consists of four lanes of eight bits. At the transmit
side of the XAUI interface, the data and control characters are converted
within the XGXS into an 8B/10B encoded data stream. Each data stream
is then transmitted across a single differential pair running at 3.125 Gbps.
At the XAUI receiver, the incoming data is decoded and mapped back to
the 32-bit XGMII format. This provides a transparent extension of the
physical reach of the XGMII and also reduces the interface pin count.
XAUI functions as a self-managed interface because code group
synchronization, channel deskew, and clock domain decoupling is
handled with no upper layer support requirements. This functionality is
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Altera Corporation
May 2008
XAUI Mode
based on the PCS code groups that are used during the IPG time and idle
periods. PCS code groups are mapped by the XGXS to XGMII characters
specified in Table 2–24.
Table 2–24. XGMII Character to PCS Code-Group Mapping
XGMII TXC
XGMII TXD (1)
PCS Code Group
0
00 through FF
Dxx.y
1
07
K28.0, K28.3, or
K28.5
Description
Normal data
transmission
Idle in ||I||
1
07
K28.5
Idle in ||T||
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
Other value
—
1
Any other value
K30.7
Reserved XGMII
character
Deleted XGMII
character
Note to Table 2–24:
(1)
Values in TXD column are in hexadecimal.
Figure 2–34 shows an example of the mapping between XGMII characters
and the PCS code groups that are used in XAUI. The idle characters are
mapped to a pseudo random sequence of /A/, /R/, and /K/ code
groups.
Figure 2–34. XGMII Character to PCS Code-Group Mapping
XGMII
T/RxD<7:0>
|
|
S
Dp
D
D
D
---
D
D
D
D
|
|
|
|
|
|
T/RxD<15:8>
|
|
Dp
Dp
D
D
D
---
D
D
D
T
|
|
|
|
|
|
T/RxD<23:16>
|
|
Dp
Dp
D
D
D
---
D
D
D
|
|
|
|
|
|
|
T/RxD<31:24>
|
|
Dp
Dp
D
D
D
---
D
D
D
|
|
|
|
|
|
|
PCS
Lane 0
K
R
S
Dp
D
D
D
---
D
D
D
D
A
R
R
K
K
R
Lane 1
K
R
Dp
Dp
D
D
D
---
D
D
D
T
A
R
R
K
K
R
Lane 2
K
R
Dp
Dp
D
D
D
---
D
D
D
K
A
R
R
K
K
R
Lane 3
K
R
Dp
Dp
D
D
D
---
D
D
D
K
A
R
R
K
K
R
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
The PCS code-groups are sent via PCS ordered sets. PCS ordered sets
consist of combinations of special and data code groups defined as a
column of code groups. These ordered sets are composed of four code
groups beginning in Lane 0. Table 2–25 lists the defined idle ordered sets
(||I||) that are used for the self managed properties of XAUI.
Table 2–25. Defined Idle Ordered Set
Code
Ordered Set
||I||
Idle
||K||
Synchronization
column
Number of
Code Groups
4
Encoding
Substitute for XGMII Idle
/K28.5/K28.5/K28.5/K28.5
||R||
Skip column
4
/K28.0/K28.0/K28.0/K28.0
||A||
Align column
4
/K28.3/K28.3/K28.3/K28.3
XAUI Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
XAUI mode (Figure 2–35). The sub-blocks are described in order from the
PLD-Transceiver parallel interface to the serial transmitter buffer.
Figure 2–35. XAUI Transmitter Architecture
Transmitter PCS
TX Phase
Compensation
FIFO
PLD
Logic
Array
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Reference
Clock
Clock Multiplier Unit (CMU)
The clock multiplier unit takes in a reference clock and synthesizes the
clocks that are used to clock the transmitter digital logic (PCS), the
serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
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Altera Corporation
May 2008
XAUI Mode
In XAUI mode, the CMU block consists of the following components:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
Input Reference Clock
In XAUI mode for Arria GX devices, the only supported input reference
clock frequency is 156.25 MHz.
The reference clock input to the transmitter PLL can be derived from the
following components:
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Altera recommends using the dedicated reference clock input pins
(REFCLK0 or REFCLK1) to provide reference clock for the transmitter
PLL.
Dedicated Reference Clock Pin Specifications
Table 2–26 shows the I/O standards allowed for the reference clock pins.
Table 2–26. Xaui Mode Reference Clock Specifications
Frequency
156.25 MHz
I/O Standard
Coupling
Termination
1.2-V PCML,
1.5-V PCML,
3.3-V PCML,
Differential LVPECL,
LVDS
AC
On-chip
In ×4 mode for XAUI, the central clock divider in the transceiver block
divides the 1562.5 MHz clock from the transmitter PLL by 5 to generate a
312.5 MHz parallel clock. This low-speed parallel clock output from the
central clock divider block is used to clock the transmitter digital logic
(PCS) in all channels of the transceiver block. The central clock divider
block also forwards the high-speed serial clock from the transmitter PLL
to the serializer within each channel. Because all four channels in the
transceiver block are clocked with the same clock, the channel-to-channel
skew is minimized.
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
1
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for the XAUI data rate.
Figure 2–36 shows the CMU implemented in XAUI mode.
Figure 2–36. XAUI Mode CMU
CMU Block
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
1562.5 MHz
Reference
Clock
Transmitter
PLL
(x10)
156.25 MHz
1562.5 MHz
1562.5 MHz
Transmitter High-Speed
Serial (1562.5 MHz) and
Low-Speed Parallel (312.5 MHz)
Clock
Central Clock
Divider Block
(/5)
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
Transmitter Channels [1:0]
Transmitter High-Speed
Serial (1562.5 MHz) and
Low-Speed Parallel (312.5 MHz)
Clocks
Clock Synthesis
In XAUI mode, the 156.25-input reference clock is fed to the transmitter
PLL. Since the transmitter PLL implements a half-rate VCO, it multiplies
the 156.25-MHz input clock by 10 to generate a 1562.5-MHz (3.125-Gbps)
high speed serial clock. This high-speed serial clock feeds the central
clock divider and four local clock dividers of the transceiver block.
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
f
For more details about the transmitter phase compensation FIFO buffer
architecture, refer to the Transmitter Phase Compensation FIFO section
in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In XAUI 3.125 Gbps mode, the 312.5 MHz clock generated by the CMU
clock divider block is divided by two. The resulting 156.25 MHz clock is
used to clock the read port of the FIFO buffer. This divide-by-two clock is
also forwarded to the PLD logic array (on the tx_clkout port of its
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May 2008
XAUI Mode
associated channel). If the tx_coreclk port is not instantiated, the clock
signal on the tx_clkout port is automatically routed back to clock the
write side of the transmitter phase compensation FIFO buffer. The 16-bit
PLD-transceiver interface clocked at 156.25 MHz results in an effective
XAUI data rate of 3.125 Gbps.
In XAUI mode, the transmitter phase compensation FIFO is four words
deep. The latency through the FIFO is two to three PLD transceiver
interface clock cycles.
Figure 2–37 shows the block diagram of transmitter phase compensation
FIFO in XAUI mode.
Figure 2–37. Transmitter Phase Compensation FIFO in XAUI Mode
Transmitter Channel
tx_datain[7:0]
Transmitter
Phase
Compensation
FIFO
From
PLD
wrclk
tx_coreclk
156.25 MHz
dataout [7:0]
To 8B/10B
Encoder
rdclk
156.25 MHz
312.5 MHz
/2
CMU
Local Clock Divider
Block
tx_clkout
Byte Serializer
In XAUI 3.125 Gbps mode the PLD-transceiver interface data is 16 bits
wide and is clocked into the transmitter phase compensation FIFO at
156.25 MHz. The byte serializer clocks in the 16-bit wide data from the
transmitter phase compensation FIFO at 156.25 MHz and clocks out 8-bit
data to the 8B/10B encoder at 312.5 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
f
Altera Corporation
May 2008
For more details about the byte serializer architecture, refer to the Byte
Serializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
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Arria GX Transceiver Protocol Support and Additional Features
The write port of the byte serializer is clocked by the divide-by-two
version of the low-speed parallel clock from CMU. The read port is
clocked by the low-speed parallel clock from CMU. The byte serializer
clocks out the least significant byte of the 16-bit data first and the most
significant byte last.
Figure 2–38 shows the block diagram of the byte serializer in XAUI mode.
Figure 2–38. Byte Serializer in XAUI Mode
dataout
datain
Byte Serializer
From Transmitter
Phase Compensation
FIFO
To 8B/10B
Encoder
wrclk
rdclk
156.25 MHz
312.5 MHz
156.25 MHz
/2
Divide-by-Two
Version of
Low-Speed
Parallel Clock
312.5 MHz
Low-Speed
Parallel Clock
CMU
Local/Central Clock
Divider Block
8B/10B Encoder
In XAUI mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control
identifier from the transmitter phase compensation FIFO and generates a
10-bit encoded data. The 10-bit encoded data is fed to the serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
XGMII Character to PCS Code-Group Mapping
In XAUI mode, the 8B/10B encoder in Arria GX devices is controlled by
a global transmitter state machine that maps various 8-bit XGMII codes
to 10-bit PCS code groups. This state machine complies with the IEEE
802.3ae PCS transmit specification. Figure 2–39 shows the PCS transmit
source state diagram specified in clause 48 of the IEEE P802.3ae.
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Altera Corporation
May 2008
XAUI Mode
Figure 2–39. IEEE 802.3ae PCS Transmit Source State Diagram
!reset
!(TX=||IDLE|| + TX=||Q||
SEND_Q
IF TX=||T|| THEN cvtx_terminate
tx_code_group<39:0> ⇐
ENCODE(TX)
PUDR
(next_ifg + A_CNT≠0)
next_ifg = A_CNT≠0
reset
SEND_A
SEND_K
tx_code_group<39:0> ⇐ ||A||
next_ifg ⇐ K
PUDR
Q_det
tx_code_group<39:0> ⇐ ||K||
next_ifg ⇐ A
PUDR
!Q_det
UCT
B
SEND_Q
tx_code_group<39:0> ⇐ TQMSG
Q_det ⇐ K
PUDR
A
A_CNT≠0 *
cod_sel=1
B
UCT
SEND_RANDOM_K
tx_code_group<39:0> ⇐ ||K||
PUDR
SEND_RANDOM_R
tx_code_group<39:0> ⇐ ||R||
A_CNT≠0 *
cod_sel=1
B
A_CNT≠0 *
cod_sel=1 A
A_CNT=0
A_CNT=0
A
SEND_RANDOM_A
A_CNT≠0 *
cod_sel=1
tx_code_group<39:0> ⇐ ||A||
PUDR
Q_det
B
!Q_det *
cod_sel=1
SEND_RANDOM_Q
tx_code_group<39:0> ⇐ TQMSG
Q_det ⇐ FALSE
PUDR
B
A
Altera Corporation
May 2008
A
!Q_det *
cod_set=1
cod_set=1
cod_set=1
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–27 lists the XGMII character to PCS code-group mapping.
Table 2–27. XGMII Character to PCS Code-Group Mapping
XGMII TXC
XGMII TXD (1)
PCS Code Group
0
00 through FF
Dxx.y
1
07
K28.0, K28.3, or
K28.5
Description
Normal data
transmission
Idle in ||I||
1
07
K28.5
Idle in ||T||
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
Other value
1
Any other value
Reserved XGMII
character
K30.7
Invalid XGMII
character
Note to Table 2–27:
(1)
Values in TXD column are in hexadecimal.
Serializer
In XAUI 3.125 Gbps mode, the 10-bit encoded data from the 8B/10B
encoder is clocked into the 10:1 serializer with the low speed parallel
clock at 312.5 MHz. The 10-bit data is clocked out of the serializer LSB to
MSB at the high-speed effective serial clock rate at 3125 MHz. The serial
data output of the serializer is fed into the transmitter output buffer.
f
For more details about the serializer architecture, refer to the serializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
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May 2008
XAUI Mode
Transmitter Buffer
Table 2–28 shows the transmitter buffer settings when configured in
XAUI mode.
Table 2–28. Transmitter Buffer Settings in XAUI Mode
Settings
Value
I/O Standard
1.5-V PCML (1)
Programmable Differential Output
Voltage (VOD)
400 - 1200 mV
600 mV, 700 mV (1)
Common Mode Voltage (VCM)
100 Ω (2)
Differential Termination
Enabled (3)
Programmable pre-emphasis
VCCH (Transmitter Buffer Power)
1.5 V
Notes to Table 2–28:
(1)
(2)
(3)
The common mode voltage (VCM) settings are selectable in the MegaWizard
Plug-In Manager.
The I/O standard and differential termination settings are defaulted to 1.5-V
PCML and 100 Ω, respectively. If you select any other setting for the I/O standard
or differential termination in the Assignment Editor, the Quartus II compiler
issues an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
XAUI Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in
XAUI mode (Figure 2–40). The sub-blocks are described in order from the
serial receiver input buffer to the receiver phase compensation FIFO
buffer at the transceiver-PLD interface.
Figure 2–40. XAUI Mode Receiver Architecture
FPGA
Logic
Array
RX Phase
Compensation
FIFO
Altera Corporation
May 2008
Byte
Ordering
Byte DeSerializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
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Arria GX Transceiver Protocol Support and Additional Features
Receiver Buffer
Table 2–29 shows the receiver buffer settings when configured in XAUI
mode.
Table 2–29. Receiver Buffer Settings in XAUI Mode
Settings
Value
I/O Standard
1.2-V PCML,
1.5-V PCML,
3.3-V PCML,
Differential LVPECL,
LVDS
Input Common Mode Voltage (Rx VCM)
850 mV, 1200 mV (1)
Differential Termination
Programmable equalization
Coupling
100 Ω (2)
Enabled (3)
AC
Notes to Table 2–29:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω. If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler issues an error message.
The receiver buffer has five programmable equalization settings.
Receiver PLL and Clock Recovery Unit
In XAUI 3.125 Gpbs mode, the receiver PLL in each transceiver channel is
fed by an input reference clock. The receiver PLL in conjunction with the
clock recovery unit generates two clocks: a half-rate high-speed serial
recovered clock at 1562.5 MHz that feeds the deserializer and a low-speed
parallel recovered clock at 312.5 MHz that feeds the receiver's digital
logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switch the
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between lock
to-reference and lock-to-data modes via the rx_locktorefclk and
rx_locktodata signals.
f
For more details about the CRU lock modes, refer to the Receiver PLL
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
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May 2008
XAUI Mode
The reference clock input to the receiver PLL can be derived from one of
the following pins:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Deserializer
In XAUI 3.125 Gbps mode, the 1:10 deserializer clocks in serial data from
the receiver buffer using the high-speed serial recovered clock. The 10-bit
deserialized data is clocked out to the word aligner using the low-speed
parallel recovered clock at 312.5 MHz. The deserializer assumes that the
transmission bit order is LSB to MSB; that is, the LSB of a data word is
received earlier in time than its MSB.
f
For more details about the deserializer architecture, refer to the
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
Word Aligner
The word aligner clocks in 10-bit data from the deserializer and restores
the word boundary of the upstream transmitter.
f
For more details about the word aligner architecture, refer to the Word
Aligner section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In XAUI mode, the word aligner comprises of the following three
modules:
■
■
■
Pattern detector module
Pattern aligner module
Run-length violation detection module
Pattern Detector
In XAUI mode, the Quartus II software automatically configures 10-bit
K28.5 (10'b0101111100) as the word alignment pattern. After coming out
of reset (rx_digitalreset), when the pattern detector detects either
disparities of the K28.5 control word, it asserts the rx_patterndetect
signal for one parallel clock cycle. When the pattern aligner has aligned
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
the incoming data to the desired word boundary, the pattern detector
asserts rx_patterndetect signal only if the word alignment pattern is
found in the current word boundary.
Pattern Aligner
In XAUI mode, the pattern aligner employs an automatic synchronization
state machine. The Quartus II software automatically configures the
synchronization state machine to indicate synchronization when the
receiver receives 4 K28.5 (10'b0101111100 or 10'b1010000011)
synchronization code groups without receiving an intermediate invalid
code group. Once synchronized, the state machine indicates loss of
synchronization when it detects 4 invalid code groups separated by less
than 4 valid code groups or when it is reset.
Receiver synchronization is indicated on the rx_syncstatus port of
each channel. A high on the rx_syncstatus port indicates that the lane
is synchronized and a low indicates that it has fallen out of
synchronization.
Table 2–30 lists the synchronization state machine parameters when
configured in XAUI mode.
Table 2–30. Synchronization State Machine Parameters in XAUI Mode
Number of valid K28.5 code groups received to achieve synchronization
4
Number of errors received to lose synchronization
4
Number of continuous good code groups received to reduce the error count 4
by 1
Synchronization State Machine in XAUI Mode
When XAUI mode is used, the synchronization and word alignment is
handled automatically by a built-in state machine that adheres to either
the IEEE 802.3ae or IEEE 802.3 synchronization specifications,
respectively. If you specify either standard, the alignment pattern is
automatically defaulted to /K28.5/ (b'0011111010).
XAUI uses an embedded clocking scheme that re-times the data that
potentially can alter the code-group boundary. The boundaries of the
code groups are re-aligned through a synchronization process specified
in clause 48 of the IEEE P802.3ae standard, which states that
synchronization is achieved upon the reception of four /K28.5/ commas.
When you specify the XAUI protocol, code-group synchronization is
achieved upon the reception of four /K28.5/ commas. Each comma can
be followed by any number of valid code groups. Invalid code groups are
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May 2008
XAUI Mode
not allowed during the synchronization stage. When code-group
synchronization is achieved the optional rx_syncstatus signal is
asserted.
Refer to clause 47-48 of the IEEE P802.3ae standard or “XAUI Mode” on
page 2–60 for more information about the operation of the
synchronization phase.
When you configure Arria GX devices to the XAUI protocol, the built in
pattern detector, word aligner, and XAUI state machines adhere to the
PCS synchronization specification. After all the conditions for
synchronization have been met, the rx_syncstatus signal is asserted
and only de-asserts if synchronization is lost.
Figure 2–41 shows the PCS synchronization state diagram specified in
clause 48 of the IEEE P802.3ae.
Figure 2–41. IEEE 802.3ae PCS Synchronization State Diagram
reset +
(signal_detectCHANGE<n> *PUDI)
LOSS_OF_SYNC
PUDI * signal_detect<n>=FAIL)+
PUDI(![/COMMA/])
lane_sync_status<n> ⇐ FAIL
enable_cgalign ⇐TRUE
SUDI
(signal_detect<n>=OK)*
PUDI([/COMMA/]
COMMA_DETECT_1
PUDI([/COMMA/]
*∉[/INVALID/]
enable_cgalign ⇐ FALSE
SUDI
PUDI([/INVALID/])
PUDI([/COMMA/]
COMMA_DETECT_2
PUDI([/COMMA/]
*∉[/INVALID/]
SUDI
PUDI([/INVALID/])
PUDI([/COMMA/]
COMMA_DETECT_3
PUDI([/COMMA/]
*∉[/INVALID/]
SUDI
PUDI([/INVALID/])
PUDI([/COMMA/]
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_1
lane_sync_status<n> ⇐ OK
SUDI
PUDI([/INVALID/])
1
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_2
SYNC_ACQUIRED_2A
good_cgs ⇐ 0
SUDI
good_cgs ⇐ good_cgs + 1
SUDI
PUDI([/INVALID/])
PUDI(∉[/INVALID/])*good_cgs = 3
PUDI([/INVALID/])
2
PUDI(∉[/INVALID/])*
good_cgs ≠ 3
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_3
SYNC_ACQUIRED_3A
good_cgs ⇐ 0
SUDI
good_cgs ⇐ good_cgs + 1
SUDI
PUDI([/INVALID/])
PUDI([/INVALID/])
1
PUDI(∉[/INVALID/])*
good_cgs ≠ 3
PUDI(∉[/INVALID/])*good_cgs = 3
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_4
SYNC_ACQUIRED_4A
good_cgs ⇐ 0
SUDI
PUDI([/INVALID/])
good_cgs ⇐ good_cgs + 1
SUDI
PUDI([/INVALID/])
2
Altera Corporation
May 2008
PUDI(∉[/INVALID/])*
good_cgs ≠ 3
PUDI(∉[/INVALID/])*good_cgs = 3
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
The word aligner block asserts an error flag on the rx_disperr and
rx_errdetect ports if the received 10-bit code is detected with
incorrect running disparity. The error flag signal (rx_disperr) has the
same delay from the word aligner to the PLD-transceiver interface as the
received data.
Channel Aligner (Deskew)
It is possible for ordered sets to be misaligned with respect to one another
because of board skew or differences between the independent clock
recoveries per serial lane. Channel alignment, also referred to as deskew
or channel bonding, realigns the ordered sets by using the alignment code
group, referred to as /A/. The /A/ code group is transmitted
simultaneously on all four lanes, constituting an ||A|| ordered set,
during idles or IPG. XAUI receivers use these code groups to resolve any
lane to lane skew. Skew between the lanes can be up to 40 UI (12.8 ns) as
specified in the standard, which relaxes the board design constraints.
Figure 2–42 shows lane skew at the receiver input and how the deskew
circuitry uses the /A/ code group to deskew the channels.
Figure 2–42. Lane Deskew with the /A/ Code Group
Lane 0
K
Lane 2
K
R
A
K
R
R
K
K
R
K
R
Lane 1
K
K
R
A
K
R
R
K
K
R
K
K
R
A
K
R
R
K
K
R
K
R
K
K
R
A
K
R
R
K
K
R
K
K
Lane 3
R
Lanes Skew at
Receiver Input
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Lane 1
K
K
R
A
K
R
R
K
K
R
K
R
Lane 2
K
K
R
A
K
R
R
K
K
R
K
R
Lane 3
K
K
R
A
K
R
R
K
K
R
K
R
Lanes are
Deskewed by
Lining up
the "Align"/A/,
Code Groups
Arria GX devices manage XAUI channel alignment with a dedicated
deskew macro that consists of a 16-word-deep FIFO buffer controlled by
a XAUI deskew state machine. The XAUI deskew state machine first
looks for the /A/ code group within each channel. When the XAUI
deskew state machine detects /A/ in each channel, the deskew FIFO
buffer is enabled. The deskew state machine now monitors the reception
of /A/ code groups. When four aligned /A/ code groups have been
received the rx_channelaligned is asserted. The deskew state
machine continues to monitor the reception of /A/ code groups and
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Altera Corporation
May 2008
XAUI Mode
de-asserts the rx_channelaligned signal if alignment conditions are
lost. This built-in deskew macro is only enabled for the XAUI protocol.
Figure 2–43 shows the PCS deskew state diagram specified in clause 48 of
the IEEE P802.3ae.
Figure 2–43. IEEE 802.3ae PCS Deskew State Diagram
reset +
(sync_status=FAIL * SUDI)
LOSS_OF_ALIGNMENT
align_status ⇐ FAIL
enable_deskew ⇐TRUE
SUDI(![/||A||/])
AUDI
sync_status OK * SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
ALIGN_DETECT_1
enable_deskew ⇐ FALSE
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
ALIGN_DETECT_2
!deskew_error
* SUDI(![/||A||/])
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
ALIGN_DETECT_3
AUDI
deskew_error * SUDI
1
SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
ALIGN_ACQUIRED_1
enable_deskew ⇐ FALSE
AUDI
deskew_error * SUDI
2
SUDI(![/||A||/])
ALIGN_ACQUIRED_2
!deskew_error
* SUDI(![/||A||/])
AUDI
deskew_error * SUDI
3
SUDI(![/||A||/])
1
!deskew_error
* SUDI(![/||A||/])
ALIGN_ACQUIRED_3
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
2
!deskew_error
* SUDI(![/||A||/])
ALIGN_ACQUIRED_4
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
3
Rate Matcher
XAUI can operate in multi-crystal environments, which can tolerate
frequency variations of 100 PPM between crystals. Arria GX devices
contain embedded circuitry to perform clock rate compensation, which is
achieved by inserting or removing the PCS SKIP code group (/R/) from
the IPG or idle stream. This process is called rate matching and is
sometimes referred to as clock rate compensation.
Altera Corporation
May 2008
2–77
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
The rate matcher in Arria GX devices consists of a 12-word-deep FIFO
buffer, with control logic that you can configure to support XAUI, GIGE,
or custom modes. In XAUI mode the controller begins to write data into
the FIFO buffer whenever the rx_channelaligned signal is asserted.
Within the control logic there is a FIFO counter that keeps track of the
read and write executions. When the FIFO counter reaches a value of
greater than nine, the receivers delete the /R/ code-group
simultaneously across all channels during IPG or idle conditions. If the
FIFO counter is fewer than five, the receivers insert the /R/ code-group
simultaneously across all channels during IPG or idle conditions.
The rate matcher in XAUI mode operates in a synchronized four mode
and supports up to a 100 PPM clock difference between the upstream
transmitter and receiver. In this mode, the rate matcher can insert or
delete a column of /R/ characters as denoted by the ||R|| designation,
depending on whether the FIFO buffer is approaching an empty or full
condition. The rate matcher does not operate until the XAUI
synchronization state machine achieves word alignment and channel
alignment. Until that point, the rate matcher is not active (read and write
pointers do not move).
If the ||R|| code words are not received on all channels, rate matching
does not occur and may lead to over/underflow conditions in the
rate-matching FIFO buffer. If this situation occurs, the data output of the
receiver outputs a constant 9'h19C (8'h9C on the rx_dataout output
and 1'b1 on the rx_ctrldetect output) in Lane 0 (rest of the lane are
data 8'h00). The receiver digital reset must be asserted and the lanes
resynchronized before data can be received.
1
This circuitry compensates for 100 PPM frequency variations.
8B/10B Decoder
In XAUI mode, the 8B/10B decoder clocks in 10-bit data from the word
aligner and decodes it into 8-bit data + 1-bit control identifier. The 8-bit
decoded data is fed to the byte deserializer.
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
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Altera Corporation
May 2008
XAUI Mode
If the received 10-bit code group is detected with incorrect running
disparity, the 8B/10B decoder block asserts an error flag on the
rx_disperr and rx_errdetect ports. The error flag signal
(rx_disperr) has the same delay from the 8B/10B decoder to the
PLD-transceiver interface as the received data.
PCS Code Group to XGMII Character Mapping
In XAUI mode, the 8B/10B decoder in Arria GX devices is controlled by
a global receiver state machine that maps various PCS code groups into
specific 8-bit XGMII codes. Table 2–31 lists the PCS code group to XGMII
character mapping.
Table 2–31. PCS Code Group to XGMII Character Mapping
XGMII RXC
XGMII RXD
PCS Code Group
Description
0
00 through FF
Dxx.y
Normal data transmission
1
07
K28.0, K28.3, or K28.5
Idle in [[I]]
1
07
K28.5
Idle in [[T]]
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
FE
Invalid code group
Received code group
Note to Table 2–31:
(1)
Values in RXD column are in hexadecimal.
Byte Deserializer
In XAUI 3.125 Gbps mode, the PLD-receiver interface data is 16 bits wide
and is clocked out of the receiver phase compensation FIFO at
156.25 MHz. The byte deserializer clocks in the 8-bit wide data from the
8B/10B decoder at 312.5 MHz and clocks out 16-bit wide data to the
receiver phase compensation FIFO at 156.25 MHz. This allows clocking
the PLD-transceiver interface at half the speed.
f
For more details about byte deserializer architecture, refer to the Byte
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In XAUI mode, the write port of the byte deserializer is clocked by the
low-speed parallel recovered clock and the read port is clocked by
divide-by-two version of this clock.
Altera Corporation
May 2008
2–79
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Due to 8- to 16-bit byte deserialization, the byte ordering at the PLD
receiver interface might be incorrect. If required, you must implement the
byte ordering logic in the PLD core to correct for this situation.
Figure 2–44 shows the block diagram of the byte deserializer in XAUI
mode.
Figure 2–44. Byte Deserializer in XAUI Mode
dataout
datain
Byte
Deserializer
From 8B/10B
Decoder
wrclk
To Receiver Phase
Compensation
FIFO
rdclk
156.25 MHz
312.5 MHz
/2
Low-Speed Parallel CMU Clock
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about the receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In XAUI 3.125 Gbps mode, the 312.5 MHz low-speed parallel recovered
clock is divided by 2. The resulting 156.25 MHz clock is used to clock the
write port of the FIFO buffer. This divide-by-two clock is also forwarded
to the PLD logic array (on the rx_clkout port). If the rx_coreclk port
is not instantiated, the recovered clock signal on the rx_clkout port is
automatically routed back to clock the read side of the receiver phase
compensation FIFO buffer. The 16-bit PLD-receiver interface clocked at
156.25 MHz results in an effective XAUI data rate of 3.125 Gbps.
In XAUI mode, the receiver phase compensation FIFO is four words deep.
The latency through the FIFO is one to two PLD-transceiver interface
clock cycles.
2–80
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial Digital Interface (SDI) Mode
Figure 2–45 shows the block diagram of receiver phase compensation
FIFO in XAUI mode.
Figure 2–45. Receiver Phase Compensation FIFO in XAUI Mode
Receiver Channel
datain[15:0]
From Byte
Deserializer
Receiver Phase
Compensation
FIFO
To PLD
wrclk
156.25 MHz
312.5 MHz
rx_dataout[15:0]
rdclk
156.25 MHz
/2
rx_coreclk
Low-Speed
Parallel CMU Clock
tx_clkout or
coreclkout
Serial Digital
Interface (SDI)
Mode
The Society of Motion Picture and Television Engineers (SMPTE) defines
various Serial Digital Interface (SDI) standards for transmission of
uncompressed video.
The following three SMPTE standards are popular in video broadcasting
applications:
■
■
■
SMPTE 259M standard— more popularly known as the standard
definition (SD) SDI, is defined to carry video data at 270 Mbps.
SMPTE 292M standard— more popularly known as the high
definition (HD) SDI, is defined to carry video data at either
1485 Mbps or 1483.5 Mbps.
SMPTE 424M standard— more popularly known as the third
generation (3G) SDI, is defined to carry video data at either
2970 Mbps or 2967 Mbps.
You can configure Arria GX transceivers in HD SDI or 3G SDI
configuration using the ALT2GXB MegaWizard Plug-In Manager.
Figure 2–46 shows the ALT2GXB transceiver data path in SDI mode.
Altera Corporation
May 2008
2–81
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–46. SDI Mode Data Path
Transmitter Digital Logic
TX Phase
Compensation
FIFO
Analog Receiver and
Transmitter Logic
Byte
Serializer
8B/10B
Encoder
Serializer
FPGA
Logic
Array
RX Phase
Compensation
FIFO
Byte
Deserializer
Byte
Ordering
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Table 2–32 shows ALT2GXB configurations supported by the Arria GX
transceivers in SDI mode.
Table 2–32. ALT2GXB Configuration in SDI Mode
Configuration
Data Rate (Mbps)
REFCLK
Frequencies
(MHz)
74.25, 148.5
Channel Width
HD
1485
10 bit, 20 bit
1483.5
74.175, 148.35
10 bit, 20 bit
3G
2970
148.5, 297
Only 20-bit
interface allowed
in 3G
2967
148.35, 296.7
Only 20-bit
interface allowed
in 3G
Transmitter Data Path
In the 10-bit channel width SDI configuration, the transmitter data path
consists of the transmitter phase compensation FIFO and the 10:1
serializer. In the 20-bit channel width SDI configuration, the transmitter
data path also includes the byte serializer.
1
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Arria GX Device Handbook, Volume 2
In SDI mode, the transmitter is purely a parallel-to-serial
converter. SDI transmitter functions, such as scrambling and
cyclic redundancy check (CRC) code generation, must be
implemented in the FPGA logic array.
Altera Corporation
May 2008
Reset Control and Power-Down
Receiver Data Path
In the 10-bit channel width SDI configuration, the receiver data path is
comprised of the CRU, the 1:10 deserializer, the word aligner in bit-slip
mode, and the receiver phase compensation FIFO. In the 20-bit channel
width SDI configuration, the receiver data path also includes the byte
deserializer.
1
SDI receiver functions, such as descrambling, framing, and CRC
checker, must be implemented in the FPGA logic array.
Receiver Word Alignment/Framing
In SDI systems, because the word alignment and framing happens after
descrambling, the word aligner in the receiver data path is not useful.
Altera recommends driving the ALT2GXB rx_bitslip signal low to
avoid the word aligner from inserting bits in the received data stream.
1
f
Reset Control
and
Power-Down
Altera offers SDI MegaCore® function that can be configured at
SD-SDI, HD-SDI, and 3G-SDI data rates. The SDI MegaCore
function implements system level functions such as scrambling
and de-scrambling and CRC generation and checking. It also
offers the capability of configuring the three SDI data rates (SD,
HD, and 3G) dynamically on the same transceiver channel.
For more information about the SDI MegaCore function, refer to the SDI
MegaCore Function User Guide.
Arria GX transceivers provide multiple reset signals to reset the analog
and digital circuits in the transceiver channels. Besides individual
channel resets, Arria GX transceivers also provide power-down signals
that you can assert to power-down the entire transceiver block to reduce
power consumption (Figure 2–47).
Figure 2–47. Reset Signals
tx_digitalreset
rx_digitalreset
rx_analogreset
Reset Control
gxb_powerdown
Altera Corporation
May 2008
2–83
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
User Reset and Power-Down Signals
Each transceiver block and each channel in the transceiver block of the
Arria GX device has individual reset signals to reset the digital and
analog circuits in the channel. The tx_digitalreset,
rx_digitalreset, and rx_analogreset signals affect the channels
individually. The gxb_powerdown signal affects the entire transceiver
block.
1
■
■
■
■
All reset and power-down signals are optional. Altera strongly
recommends using the reset and power-down signals and
following the reset sequence detailed in this section.
tx_digitalreset—This signal resets all digital logic in the
transmitter. This signal operates independently from the other reset
signals. The minimum pulse width is two parallel cycles.
●
In Basic mode, Altera recommends de-asserting the
tx_digitalreset signal of all used transceiver blocks
simultaneously after the pll_locked signal from all active
transceiver blocks goes high.
rx_digitalreset—This signal resets all digital logic in the
receiver. This signal operates independently from the other reset
signals. The minimum pulse width is two parallel cycles.
rx_analogreset—This signal resets part of the analog portion of
the receiver CRU. This signal operates independently from the other
reset signals. The minimum pulse width is two parallel cycles.
gxb_powerdown—This signal powers down the entire transceiver
block, including the transmitter PLL. All digital and analog circuits
are also reset. This signal operates independently from the other reset
signals. The minimum pulse width is 100 ns.
Table 2–33 lists the transceiver modules that get affected by each reset and
power-down signal.
Table 2–33. Blocks Affected by Reset and Power-Down Signals (Part 1 of 2)
Transceiver Blocks
rx_digitalreset
rx_analogreset
tx_digitalreset
gxb_powerdown
Transmitter phase compensation
FIFO buffer and byte serializer
—
—
v
v
Transmitter 8B/10B encoder
—
—
v
v
Transmitter serializer
—
—
—
v
Transmitter analog circuits
—
—
—
v
Transmitter PLLs
—
—
—
v
Transmitter analog circuits
—
—
—
v
Receiver deserializer
—
—
—
v
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Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Reset Control and Power-Down
Table 2–33. Blocks Affected by Reset and Power-Down Signals (Part 2 of 2)
Transceiver Blocks
rx_digitalreset
rx_analogreset
tx_digitalreset
gxb_powerdown
Receiver word aligner
v
—
—
v
Receiver rate matcher
v
—
—
v
Receiver 8B/10B decoder
v
—
—
v
Receiver phase compensation
FIFO buffer and byte deserializer
v
—
—
v
Receiver PLL and CRU
—
v
—
v
Receiver analog circuits
—
—
—
v
The recommended reset sequence varies depending on whether the CRU
is configured in automatic lock mode or manual lock mode.
Recommended Reset Sequence for GIGE and Serial RapidIO in
CRU Automatic Lock Mode
Figure 2–48 shows a sample reset sequence for GIGE, Serial RapidIO,
XAUI, SDI, and Basic modes when the CRU is configured in automatic
lock mode.
Figure 2–48. Reset Sequence for GIGE, Serial RapidIO, XAUI, SDI and Basic in Automatic Mode
100 ns
Reset/Power Down Signals
1
2
gxb_powerdown
4
tx_digitalreset
4
rx_analogreset
7
rx_digitalreset
Output Status Signals
3
pll_locked
5
rx_pll_locked
6
rx_freqlocked
Altera Corporation
May 2008
4 μs
2–85
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
After power on, follow these steps:
1.
Assert the gxb_powerdown port for a minimum period of 100 ns
(time between markers 1 and 2).
2.
Keep the tx_digitalreset, rx_digitalreset, and
rx_analogreset asserted during this time period.
3.
After you de-assert the gxb_powerdown signal, the transmitter PLL
starts locking to the transmitter input reference clock. Once the
transmitter PLL locks (as indicated by the pll_locked signal
going high), you de-assert the tx_digitalreset signal.
4.
After you de-assert the rx_analogreset signal, the receiver PLL
starts locking to the receiver input reference clock (in automatic lock
mode).
5.
Once the receiver PLL locks to the input reference clock, the
rx_pll_locked signal goes high. The internal PPM detector takes
some time to calculate the PPM difference between the receiver PLL
output clock and the input reference clock.
6.
Once it calculates the PPM difference to be within the pre-defined
limits, the rx_freqlocked signal goes high. At this point the CRU
enters lock-to-data mode and the receiver PLL starts locking to the
received data.
7.
You de-assert the rx_digitalreset 4 μs after the
rx_freqlocked signal goes high.
Recommended Reset Sequence for GIGE, Serial RapidIO, XAUI,
SDI, and Basic Modes in CRU Manual Lock Mode
Figure 2–49 shows a sample reset sequence for GIGE, Serial RapidIO,
XAUI, SDI, and Basic modes when the CRU is configured in manual lock
mode.
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Altera Corporation
May 2008
Reset Control and Power-Down
Figure 2–49. Reset Sequence for GIGE and Serial RapidIO in Manual Mode
100 ns
Reset/Power Down Signals
1
2
gxb_powerdown
4
tx_digitalreset
4
rx_analogreset
7
rx_digitalreset
4 μs
Output Status Signals
3
pll_locked
5
rx_pll_locked
CRU Control Signals
6
rx_locktorefclk
rx_locktodata
15 μs
After power-on, follow these steps:
Altera Corporation
May 2008
1.
Assert the gxb_powerdown port for a minimum period of 100 ns
(time between markers 1 and 2). Keep the tx_digitalreset,
rx_digitalreset, rx_analogreset, and rx_locktorefclk
signals asserted during this time period.
2.
After you de-assert the gxb_powerdown signal, the transmitter PLL
starts locking to the transmitter input reference clock.
3.
Once the transmitter PLL locks (as indicated by the pll_locked
signal going high), you de-assert the tx_digitalreset signal.
4.
After you de-assert the rx_analogreset signal, the receiver PLL
starts locking to the receiver input reference clock since
rx_locktorefclk is asserted.
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Arria GX Transceiver Protocol Support and Additional Features
5.
Wait for at least 15 μs (time between markers 5 and 6) after the
rx_pll_locked signal goes high and then de-assert the
rx_locktorefclk signal.
6.
At the same time assert the rx_locktodata signal. At this point
the CRU enters lock-to-data mode and the receiver PLL starts
locking to the received data.
7.
You de-assert the rx_digitalreset at least 4 μs (time between
markers 6 and 7) after asserting the rx_locktodata signal.
Recommended Reset Sequence for PCI Express (PIPE) Mode
In PCI Express (PIPE) mode, the rx_freqlocked signal does not go
high during the PCI Express (PIPE) compliance testing phase because of
receiving Electrical Idle. For all other modes, the reset sequence looks for
the rx_freqlocked signal to de-assert rx_digitalreset.
Figure 2–50 shows the reset sequence for PCI Express (PIPE) mode.
Figure 2–50. Reset Sequence for PCI Express (PIPE) Mode
Initialization/PCI-E Compliance Phase
Normal Operation Phase
100 ns
1
2
gxb_powerdown
4
tx_digitalreset
4
rx_analogreset
6
10
11
rx_digitalreset
T3
3
pll_locked
5
rx_pll_locked
7
8
9
rx_freqlocked
T2
T1
Ignore Receive Data
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Reset Control and Power-Down
Initialization and PCI Express Compliance Phase
After the device is powered up, a PCI Express-compliant device may
perform compliance testing. Because rx_digitalreset must be
de-asserted during compliance testing, waiting for the rx_freqlocked
signal to de-assert rx_digitalreset is not recommended.
De-assert the tx_digitalreset signal after the pll_locked signal
goes high. De-assert the rx_digitalreset when the rx_pll_locked
signal goes high (unlike GIGE and Serial RapidIO modes, where you wait
until rx_freqlocked goes high).
The parallel data sent to the PLD logic array in the receive side may not
be valid until 4 μs after rx_freqlocked goes high.
Normal Operation Phase
During normal operation, the receive data is valid and the
rx_freqlocked signal is high. In this situation, when rx_freqlocked
is de-asserted, (marker 8 in Figure 2–50), wait for the rx_freqlocked
signal to go high again and assert rx_digitalreset (marker 10 in
Figure 2–50) for two parallel receive clock cycles.
The data from the transceiver block is not valid between the time when
rx_freqlocked goes low until rx_digitalreset is de-asserted. The
PLD logic should ignore the data during this time period (the time period
between markers 8 and 11 in Figure 2–50).
1
Minimum T1 and T2 period is 4 μs. Minimum T3 period is two
parallel receive clock cycles.
Rate Matcher FIFO Buffer Overflow and Underflow Condition
During the normal operation phase, monitor the overflow and underflow
status of the rate matcher FIFO buffer. If there is overflow and underflow
on the rate matcher FIFO buffer, assert the rx_digitalreset signal for
two receive parallel clock cycles. You can monitor the rate matcher FIFO
buffer status through the pipestatus[2:0] signal from the PCI
Express (PIPE) interface. This condition is shown in Figure 2–51.
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Figure 2–51. PCI Express (PIPE) Mode Reset During Rate Matcher FIFO Buffer Overflow & Underflow
Condition
tx_digitalreset
1
0
rx_analogreset
1
0
rx_digitalreset
1
0
T3
rx_freqlocked
T3
1
0
000
pipestatus
101
000
110
000
Notes to Figure 2–51:
(1)
(2)
Pipestatus = 101 represents elastic overflow (not available in Low-Latency [Synchronous] PCI Express [PIPE]
mode).
Pipestatus = 110 represents elastic overflow (not available in Low-Latency [Synchronous] PCI Express [PIPE] mode).
Power-Down
The Quartus II software automatically selects the power-down channel
feature, which takes effect when you configure the Arria GX device. All
unused transceiver channels and blocks in a design are powered down to
reduce the overall power consumption.
1
The gxb_powerdown port is optional. In simulation, if the
gxb_powerdown port is not instantiated, you must assert the
tx_digitalreset, rx_digitalreset and
rx_analogreset signals appropriately for correct simulation
behavior. If the gxb_powerdown port is instantiated and other
reset signals are not used, you must assert the gxb_powerdown
signal for at least one parallel clock cycle for correct simulation
behavior. In simulation, you can de-assert the
rx_digitalreset immediately after rx_freqlocked signal
goes high to reduce the simulation run time. It is not necessary
to wait for 4 µs (as suggested in the actual reset sequence).
1
In PCI Express (PIPE) mode simulation, you must assert the
tx_forceelecidle signal for at least one parallel clock cycle
before transmitting normal data for correct simulation behavior.
TimeQuest Timing Analyzer
Quartus II software designs targeted towards the Arria GX device family
use the TimeQuest Timing Analyzer for static timing analysis. Starting
with Quartus II software versions 7.1 and 7.1 sp1, the TimeQuest Timing
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Reset Control and Power-Down
Analyzer does not automatically constrain the transceiver reset ports and
asynchronous input/output ports. As a result, the TimeQuest Timing
Analyzer does not perform timing analysis on these paths.
The TimeQuest Timing Analyzer reports these unconstrained paths in
RED in the Timing Analyzer report. You must manually add the
constraints in the Synopsys Design Constraints (.sdc) file for the
TimeQuest Timing Analyzer to analyze these paths.
Unconstrained Reset Ports
In the Quartus II software versions 7.1 and 7.1 sp1, the TimeQuest Timing
Analyzer does not constrain the following transceiver reset ports:
■
■
■
■
gxb_powerdown
tx_digitalreset
rx_digitalreset
rx_analogreset
Identifying Unconstrained Reset Ports
To identify the unconstrained reset/powerdown ports, follow these
steps:
1.
After compiling your design, in the Tools drop-down menu, select
the TimeQuest Timing Analyzer. This opens up the Quartus II
TimeQuest Timing Analyzer window.
2.
In the Tasks pane, execute Report Unconstrained Paths. This
reports all unconstrained paths in RED in the Report pane.
3.
In the Report pane, expand the Unconstrained Paths option and
further expand the Setup Analysis or Hold Analysis option.
4.
Under Setup Analysis or Hold Analysis, appears Unconstrained
Input Port Paths, Unconstrained Output Port Paths, or both,
depending on how the reset/powerdown ports are driven.
5.
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May 2008
a.
If a reset/powerdown port is driven by an input pin, it is listed
in the Unconstrained Input Port Paths report.
b.
If a reset/powerdown port is driven by synchronous logic, it is
listed in the Unconstrained Output Port Paths report.
In the Unconstrained Input Port Paths and Unconstrained Output
Port Paths reports, the unconstrained reset/powerdown ports of
your ALT2GXB instances are listed under the To column.
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Consider the design example in Figure 2–52.
Figure 2–52. Example Design for TimeQuest Timing Analyzer Constraints
top_tx_digitalreset
gxb_powerdown
Reset Controller
ALT2GXB
Channel 0
rx_digitalreset
rx_analogreset
ALT2GXB
Channel 1
In the design example in Figure 2–52, all reset/powerdown ports for the
two channels are driven by the reset controller (except the
tx_digitalreset port). The tx_digitalreset port is driven from
an input pin.
Figures 2–53 and 2–54 show the TimeQuest Timing Analyzer Report for
Unconstrained Input Port Paths and Unconstrained Output Port Paths,
respectively.
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Figure 2–53. Unconstrained Input Port Paths
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Figure 2–54. Unconstrained Output Port Paths
Having identified the unconstrained reset/powerdown ports in the
design, the next step is to constrain these ports.
Setting Reset/Powerdown Port Timing Constraints
You must add the reset/powerdown port timing constraints either
directly in the .sdc file or through the TimeQuest Timing Analyzer GUI.
To add the timing constraints using the TimeQuest GUI, follow these
steps:
1.
In either the Unconstrained Input Port Paths or Unconstrained
Output Port Paths report, locate the reset/powerdown ports.
2.
In the To column, right-click the reset/powerdown port and select
Set Max Delay.
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Reset Control and Power-Down
3.
On the resulting window, enter an initial Delay Value of 4 ns.
4.
In the To column, right click on the reset/powerdown port again
and select Set Min Delay.
5.
On the resulting window, enter an initial Delay Value of 1.2 ns.
1
The difference between the maximum delay and minimum
delay is set to 2.8 ns, which is the maximum skew allowed on
reset/powerdown ports.
6.
Set the maximum and minimum delay for all transceiver
reset/powerdown ports in your design, according to steps 1-5.
7.
In the Tasks pane of the TimeQuest Timing Analyzer, double-click
Update Timing Netlist and Write SDC File. Double-clicking on
each of these causes them to execute.
8.
Confirm that the above timing constraints were added to the .sdc
file linked with your design.
9.
Run the Quartus II Fitter.
10. After the Quartus II Fitter operation completes, in the Tasks pane of
the TimeQuest Timing Analyzer window, double-click on Update
Timing Netlist. The Update Timing Netlist task then executes.
11. Execute Report Top Failing Paths by double-clicking this option in
the Tasks pane of the TimeQuest Timing Analyzer window.
12. Assuming all other paths in your design meet timing, one or more
of the paths involving reset/powerdown ports might report timing
violations. This is because the design is not able to meet the
preliminary timing constraints of 4 ns (maximum delay) and 1.2 ns
(minimum delay).
13. Note the slack in the timing report for all failing paths and adjust the
maximum delay and the minimum delay values in the file. Maintain
a difference of 2.8 ns between the maximum delay and the
minimum delay for each reset/powerdown port.
14. After adjusting the delay values, execute Update Timing Netlist
and run the Quartus II Fitter again.
15. After the Quartus II Fitter operation completes, execute Update
Timing Netlist.
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16. Execute Report Top Failing Paths once again. If there are any failing
paths involving the reset/powerdown ports, adjust the delay values
in the .sdc file and repeat the procedure until no failing paths are
reported.
Consider the previous design example in which all unconstrained ports
were identified. The following example shows how to set the constraints
for the gxb_powerdown port. The same procedure must be followed for
all other reset ports.
After setting the maximum and minimum delay for the gxb_powerdown
port, the .sdc file should have the constraints detailed in Example 2–1 and
Example 2–2:
Example 2–1. Settings for Maximum Delay in the gxb_powerdown Port
#****************************************************
# Set Maximum Delay
#****************************************************
set_max_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 4.000
Example 2–2. Settings for Minimum Delay in the gxb_powerdown Port
#****************************************************
# Set Minimum Delay
#****************************************************
set_min_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 1.200
After running the Quartus II fitter with the above timing constraints for
the gxb_powerdown port, the following slack is reported on this path
after executing Report Top Failing Paths (Figure 2–55).
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Reset Control and Power-Down
Figure 2–55. Slack Reported for the gxb_powerdown Port
Because the data arrival time is later than the data required time by
0.798 ns, the maximum delay and minimum delay should both be
incremented by 0.8 ns in the .sdc file. The new .sdc file should have the
modified constraints for the gxb_powerdown port indicated in
Example 2–3 and Example 2–4.
Example 2–3. Modified Settings for Maximum Delay for the gxb_powerdown Port
#***************************************************
# Set Maximum Delay
#****************************************************
set_max_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 4.8
Example 2–4. Modified Settings for Minimum Delay for the gxb_powerdown Port
#****************************************************
# Set Minimum Delay
#****************************************************
set_min_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 2.000
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After modifying the .sdc file and running the Quartus II Fitter, the Update
Timing Netlist option should be executed, followed by Report Top
Failing Paths. If the gxb_powerdown port still shows in the failing paths,
modify the slack appropriately in the .sdc file and repeat the procedure
until timing is met on this path.
Follow the same procedure to set timing constraints on all transceiver
reset/powerdown ports in your design.
1
You should set constraints and meet timing for both fast and
slow timing models. The same maximum and minimum delay
constraints might not be able to meet timing for both timing
models. This is acceptable as long as the skew is within the
specified period (2.8 ns) for each path in the .sdc file for each
timing model.
Unconstrained Asynchronous ALT2GXB Ports
In the Quartus II software versions 7.1 and 7.1 sp1, the TimeQuest Timing
Analyzer does not automatically constrain transceiver asynchronous
input/output ports. These ports are listed in Table 2–34.
Table 2–34. TImeQuest Timing Analyzer Port Names Versus ALT2GXB Port
Names
TimeQuest Timing Analyzer Port
Name
ALT2GXB Port Name
ala2size
rx_ala2size
enapatternalign
rx_enapatternalign
bitslip
rx_bitslip
rlv
rx_rlv
invpol
rx_invpolarity
enabyteord
rx_enabyteord
pipe8b10binvpolarity
pipe8b10binvpolarity
revbitorderwa
rx_revbitorderwa
bisterr
rx_bisterr
bistdone
rx_bitstdone
phaselockloss
rx_pll_locked
freqlock
rx_freqlocked
seriallpbkben
rx_seriallpbken
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Referenced Document
You must add the timing constraints manually in the .sdc file or for the
TimeQuest Timing Analyzer to analyze these paths. For these
asynchronous ports, you only need to set a maximum delay constraint of
10 ns in the .sdc file.
To identify all unconstrained ALT2GXB asynchronous ports, execute
Report Unconstrained Paths in TimeQuest Timing Analyzer after
running the Quartus II Fitter. Set a maximum delay of 10 ns for all such
ports in the .sdc file.
For example, if the rx_invpolarity signal is driven by the signal
top_rx_invpolarity on an input pin, the .sdc file constraint for this
port should be set as shown in Example 2–5.
Example 2–5. Constraints for the rx_invpolarity Port
set_max_delay -from [get_ports {top_rx_invpolarity}]
-to [get_keepers
{xcvr_inst.receive~OBSERVABLEINVPOL}] 10.000
Follow the same procedure to constrain all asynchronous ALT2GXB ports
in your design before closing timing analysis for your design.
Referenced
Document
Altera Corporation
May 2008
This chapter references the following documents:
■
■
■
Arria GX ALT2GXB Megafunction User Guide
Arria GX Transceiver Architecture
SDI MegaCore Function User Guide
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Arria GX Transceiver Protocol Support and Additional Features
Document
Revision History
Table 2–35 shows the revision history for this chapter.
Table 2–35. Document Revision History
Date and Document
Version
Changes Made
Summary of Changes
May 2008, v2.0
Added “Basic Single-Width Mode”, “Serial Digital Interface
(SDI) Mode”, “XAUI Mode” and “UNH-IOL Gigabit Ethernet
Compliance” sections.
Updated “Serial RapidIO Mode Transmitter Architecture”
section.
—
August 2007, v1.2
Added the “Referenced Document” section.
—
Minor text edits.
—
June 2007 v1.1
Added “TimeQuest Timing Analyzer” section.
—
Added GIGE information.
—
May 2007 v1.0
Initial release.
—
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3. Arria GX ALT2GXB
Megafunction User Guide
AGX52003-2.0
Introduction
The MegaWizard® Plug-In Manager in the Quartus® II software creates or
modifies design files that contain custom megafunction variations that
can then be instantiated in a design file. The MegaWizard Plug-In
Manager provides a wizard that allows you to specify options for the
ALT2GXB megafunction. You can use the wizard to set the ALT2GXB
megafunction features in the design.
Start the MegaWizard Plug-In Manager using one of the following
methods:
■
■
■
Choose the MegaWizard Plug-In Manager command (Tools menu).
In the Block Editor, click MegaWizard Plug-In Manager in the
Symbol dialog box (Edit menu).
Start the stand-alone version of the MegaWizard Plug-In Manager by
typing the following command at the command prompt: qmegawiz.
The ALT2GXB MegaWizard Plug-In Manager allows you to configure
one or more transceiver channels.
This chapter contains the following sections:
■
■
■
■
■
■
“Basic Mode” on page 3–3
“PCI Express (PIPE) Mode” on page 3–25
“XAUI Mode” on page 3–46
“GIGE Mode” on page 3–64
“SDI Mode” on page 3–86
“Serial RapidIO Mode” on page 3–117
Figure 3–1 shows the first page of the MegaWizard Plug-In Manager. To
generate an ALT2GXB custom megafunction variation, select Create a
new custom megafunction variation and click Next.
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Preliminary
Arria GX ALT2GXB Megafunction User Guide
Figure 3–1. MegaWizard Plug-In Manager (Page 1)
Figure 3–2 shows the second page of the MegaWizard Plug-In Manager.
Select Arria GX as the device family.
Figure 3–2. MegaWizard Plug-In Manager (Page 2)
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Basic Mode
Basic Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
Basic mode. The MegaWizard Plug-In Manager provides a warning if any
of the settings you choose are illegal.
Figure 3–3 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
in Basic mode.
Figure 3–3. MegaWizard Plug-In Manager - ALT2GXB (General)
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Table 3–1 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–1. MegaWizard Plug-In Manager Options (Page 3 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Which protocol will you be
using?
Determines the specific protocol or modes under
which the transceiver operates. For Basic mode, you
must select the Basic protocol.
Which subprotocol will you
be using?
In Basic mode, the subprotocols are the diagnostic
modes. The available options are as follows:
● No loopback – This is the normal operation of the
transceiver.
● Serial loopback – This mode loops the user data
from the transmitter path back to the receiver path
right before the buffers. Serial loopback can be
controlled dynamically.
● Reverse serial loopback – This is a loopback after
the receiver’s CDR block to the transmitter buffer.
The RX path in the PCS is active but the TX side
is not.
● Reverse serial loopback (pre-CDR) – This is the
loopback before the receiver’s CDR block to the
transmitter buffer. The RX path in the PCS is
active but the TX side is not.
● PRBS/Serial loopback – This is another serial
loopback mode, but with the PRBS BIST block
active. The PRBS pattern depends on the
serializer/deserializer (SERDES) factor.
● ×4 – This mode can be used to implement the
SFI-5 interface. In this mode, all four channels
within the transceiver block are clocked from its
central clock divider block to minimize transmitter
channel-to-channel skew.
Enforce default settings for
this protocol
This selection is not active in Basic mode because
there is no pre-defined protocol.
Reference
Loopback Modes and
Built-In Self-Test Modes
sections in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the operation mode? The available operation modes are receiver only,
transmitter only, and receiver and transmitter.
What is the number of
channels?
This option determines how many duplicate channels
this ALT2GXB instance contains.
What is the deserializer
block width?
This option sets the transceiver data path width and
defaults to single width mode.
Single width—In this mode, the transceiver operates
between 600 Mbps to 3.125 Gbps.
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Basic Mode
Table 3–1. MegaWizard Plug-In Manager Options (Page 3 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
What is the channel width?
Description
Reference
This option determines the transceiver-to-PLD
interface width.
In single-width mode, selecting 8 or 10 bits bypasses
the byte serializer/deserializer. If you select 16 or 20
bits, the byte serializer/deserializer is used.
What would you like to base
the setting on?
●
What is the data rate?
Determines the TX and RX PLL VCO frequency.
What is the input clock
frequency?
Determines the input clock frequency you want as a
reference clock for the transceiver.
Byte Serializer and
Deserializer sections in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This option allows you to do one of following:
Enter a data rate and select an input clock
frequency through a pull-down menu (with the
data rate selection).
● Enter your input clock frequency through a
pull-down menu (with the data rate selection) or
enter your input clock frequency and select from
the available data rates for a clock frequency.
What is the data rate division This setting, in conjunction with the selected data
factor?
rate, determines the effective data rate for the
transceiver channel. Division factors of 1, 2, and 4 are
available. For example, a data rate setting of
3000 Mbps and at data rate division factor of 2 yields
an effective data rate of 1500 Mbps.
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Arria GX ALT2GXB Megafunction User Guide
Figure 3–4 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–4. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
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Basic Mode
Table 3–2 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–2. MegaWizard Plug-In Manager Options (Page 4 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Train Receiver PLL clock
from PLL inclk
Description
Reference
If you turn this option on, your design uses the input
reference clock to the transmitter PLL to train the
receiver PLL. This reduces the need to supply a
separate receiver PLL reference clock.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the GXB Transmitter This option selects the transmitter PLL bandwidth and Clock Multiplier Unit
PLL bandwidth mode?
the allowed options are low, medium and high.
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Receiver PLL
bandwidth mode?
This option selects the receiver PLL bandwidth and the Clock Recovery Unit
allowed options are low, medium and high.
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the acceptable PPM
threshold between the
Receiver PLL VCO and the
CRU clock?
This option determines the parts per million (PPM)
difference that affects the automatic receiver clock
recovery unit (CRU) switchover between lock-to-data
and lock-to-reference. There are additional factors that
affect the CRU’s transition.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create gxb_powerdown
port to power down the
Quad
This signal can be used to reset and power down all
circuits in the transceiver block. It does not power
down the REFCLK buffers and reference clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port
to enable the Quad
This signal can be used to enable Arria GX transceiver Reset Control and Power
Down section in the
blocks. If instantiated, this port must be tied to the
Arria GX Transceiver
dedicated gigabit transceiver block enable input pin.
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_analogreset
port
Receiver analog reset port.
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May 2008
Reset Control and Power
Down” section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
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Table 3–2. MegaWizard Plug-In Manager Options (Page 4 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
Create
rx_digitalreset port
Create
tx_digitalreset port
Description
Reference
Receiver digital reset port. Resets the PCS portion of
the receiver. Altera® recommends using this port along
with logic to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Transmitter digital reset port. Resets the PCS portion
of the transmitter. Altera recommends using this port
along with logic to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create pll_locked port PLL locked indicator for the transmitter PLLs.
to indicate PLL is in lock with
the reference input clock
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create
Lock-to-reference lock mode for the CRU. Use with
rx_locktorefclk port
rx_locktodata.
rx_locktodata/rx_locktorefclk
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
to lock the RX PLL to the
reference clock
Create rx_locktodata
port to lock the RX PLL to
the received data
0/0—CRU is in automatic mode
0/1—CRU is in lock-to-reference clock
1/0—CRU is in lock-to-data mode
1/1—CRU is in lock-to-data mode
Lock-to-data control for the CRU. Use with
rx_locktorefclk.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Receiver PLL locked signal. Indicates if the receiver
Create rx_pll_locked
port to indicate RX PLL is in PLL is phase locked to the CRU reference clock.
lock with the reference clock
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
CRU mode indicator port. Indicates if the CRU is
locked to data mode or locked to the reference clock
mode.
0—Receiver CRU is in lock-to-reference clock
mode
1—Receiver CRU is in lock-to-data mode
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_freqlocked
port to indicate RX PLL is in
lock with the received data
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May 2008
Basic Mode
Figure 3–5 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–5. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
Altera Corporation
May 2008
3–9
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–3 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–3. MegaWizard Plug-In Manager Options (Page 5 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
to indicated data input
signal detection
Signal detect port. In PCI Express (PIPE) mode,
indicates if a signal that meets the specified range is
present at the input of the receiver buffer. In all other
modes, rx_signaldetect is forced high and must
not be used as an indication of a valid signal at
receiver input.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create
This optional output port indicates Receiver Phase
Receiver Phase
Create
rx_signaldetect port
Compensation FIFO
debug_rx_phase_comp Compensation FIFO overflow/under run condition.
_fifo_error output port Note that no PPM difference is allowed between FIFO section in the Arria GX
Create
read and write clocks. Use this port for debug
purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter Phase
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp Compensation FIFO overflow/under run condition.
_fifo_error output port Note that no PPM difference is allowed between FIFO section in the Arria GX
Create rx_coreclk port
to connect to the read clock
of the RX phase
compensation FIFO
read and write clocks. Use this port for debug
purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional input port allows you to clock the read
side of the Receiver Phase Compensation FIFO with
a non-transceiver PLD clock.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create tx_coreclk port This optional input port allows you to clock the write
to connect to the write clock side of the Transmitter Phase Compensation FIFO
with a non-transceiver PLD clock.
of the TX phase
compensation FIFO
3–10
Arria GX Device Handbook, Volume 2
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
Basic Mode
Table 3–3. MegaWizard Plug-In Manager Options (Page 5 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance of the
ALT2GXB megafunction instantiates the calibration
block. Only one instance of the ALT2GXB
megafunction is required to instantiate the calibration
block.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create active low
Power-down signal for the calibration block. Assertion
of this signal may interrupt data transmission and
reception. Use this signal to re-calibrate the
termination resistors if temperature and/or voltage
changes warrant it.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
cal_blk_powerdown to
power down the calibration
block
Altera Corporation
May 2008
3–11
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–6 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–6. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
3–12
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–4 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–4. MegaWizard Plug-In Manager Options (Page 6 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for manual Receiver Buffer section
equalizer control.
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the equalizer DC
gain?
This enables the DC gain option and the legal settings Receiver Buffer section
are 0, 1, 2, and 3.
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the Receiver
Common Mode Voltage
(RX VC M )?
The receiver common mode voltage is programmable. Receiver Buffer section
The selections available are 0.85 V and 1.2 V.
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
Force signal detection
This option is not available in Basic mode.
Receiver Buffer Section
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the signal detect and
signal loss threshold?
This option is not available in Basic mode.
Receiver Buffer section
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–13
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–4. MegaWizard Plug-In Manager Options (Page 6 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip termination
(OCT). If checked, this option turns off the receiver
OCT.
Receiver Buffer section
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the receiver
termination resistance?
This option selects the receiver termination value. The Receiver Buffer section
only supported receiver termination resistance value in the Arria GX
Transceiver
is 100 Ω .
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
3–14
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Figure 3–7 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–7. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–15
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–5 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–5. MegaWizard Plug-In Manager Options (Page 7 for Basic Mode)
ALT2GXB Setting
Description
Reference
What is the Transmitter
Buffer Power (VCCH)?
This setting is for information only and is used to
calculate the VOD from the buffer power supply (VCCH)
and the transmitter termination to derive the proper
VOD range. In Basic mode, this option is fixed at 1.5 V
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Transmitter
Common Mode Voltage
(VC M )?
The transmitter common mode voltage setting is
selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the OCT. Checking this
option turns off the transmitter OCT.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Select the Transmitter
termination resistance
This option selects the transmitter termination value.
This option defaults to 100 Ω for Arria GX devices.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter buffer.
The differential output voltage is programmable
between 400 mV and 1200 mV in steps of 200 mV. The
available VO D settings change based on VC C H .
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Pre-emphasis pre-tap
setting (% of VOD)
This option is not available in Arria GX devices and is
fixed at 0.
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on the
transmitter buffer using first post-tap. The options
available are 0, 1, 2, 3, 4, and 5.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Pre-emphasis second
This option is not available in Arria GX devices and is
post-tap setting (% of VOD) fixed at 0.
3–16
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Figure 3–8 shows page 8 of the MegaWizard Plug-In Manager for Basic
protocol mode set up.
Figure 3–8. MegaWizard Plug-In Manager - ALT2GXB (Basic 1)
Table 3–6 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–6. MegaWizard Plug-In Manager Options (Page 8 for Basic Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
Enable byte ordering block
This option is not available in Arria GX devices.
—
What do you want the byte
ordering to be based on?
This option is not available in Arria GX devices.
—
Altera Corporation
May 2008
3–17
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–6. MegaWizard Plug-In Manager Options (Page 8 for Basic Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
What is the byte ordering
pattern?
This option is not available in Arria GX devices.
—
What is the byte ordering
pad pattern?
This option is not available in Arria GX devices.
—
Enable 8B/10B
decoder/encoder
This option enables the 8B/10B encoder and
decoder. This option is only available if the
channel width is 8 or 16 bits.
—
Create tx_forcedisp to This option allows you to force positive or
enable Force disparity and negative disparity on transmitted data in 8B/10B
use tx_dispval to code configurations.
up the incoming word using
positive or negative
disparity
8B/10B Encoder section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Enable rate match FIFO
This option enables the rate matcher and is only
available with the 8B/10B decoder.
Rate Matcher section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
What is the 20-bit rate
match pattern1? (usually
used for +ve disparity
pattern)
Enter the positive disparity rate matcher pattern
and control code pattern. The skip pattern is used
for insertion or deletion. The control pattern
identifies which group of skip patterns to use for
rate matching. If only one disparity is needed for
rate matching, enter the same pattern for both
rate matching patterns (pattern1 and pattern2).
Rate Matcher section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
What is the 20-bit rate
match pattern2? (usually
used for -ve disparity
pattern)
Enter the negative disparity rate matcher pattern
and control code pattern. The skip pattern is used
for insertion or deletion. The control pattern
identifies which group of skip patterns to use for
rate matching. If only one disparity is needed for
rate matching, enter the same pattern for both
rate matching patterns (pattern1 and pattern2).
Rate Matcher section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Flip Receiver output data
bits
This option reverses the bit order of the data at
the receiver-PLD interface at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
Flip Transmitter input data
bits
This option reverses the bit order of the data bits
at the input of the transmitter at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
3–18
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–6. MegaWizard Plug-In Manager Options (Page 8 for Basic Mode) (Part 3 of 3)
ALT2GXB Setting
Enable Transmitter bit
reversal
Description
Reference
This option inverts (flips) the bit order of the data
bits at the transmitter PCS-PMA interface at a
byte level to support MSBit-to-LSBit transmission
protocols. The default transmission is
LSBit-to-MSBit.
8B/10B encoder section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Create rx_invpolarity This optional port allows you to dynamically
reverse the polarity of the received data at the
to enable word aligner
input of the word aligner.
polarity inversion
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Create tx_invpolarity This optional port allows you to dynamically
to allow Transmitter polarity reverse the polarity of the data to be transmitted
at the transmitter PCS-PMA interface.
inversion
8B/10B Encoder section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Altera Corporation
May 2008
3–19
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–9 shows page 9 of the MegaWizard Plug-In Manager for Basic
protocol mode set up.
Figure 3–9. MegaWizard Plug-In Manager - ALT2GXB (Basic 2)
3–20
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–7 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–7. MegaWizard Plug-In Manager Options (Page 9 for Basic Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
This option sets the word aligner in manual
alignment mode. (Manual alignment, bit-slipping,
and built-in state machine are mutually exclusive
options.)
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
When should the word aligner This option sets the behavior of the
realign?
rx_enapatternalign signal to either edge
or level sensitive. Altera recommends using edge
sensitive for scrambled data (non-8B/10B) traffic
and level sensitive for 8B/10B traffic.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use manual bit slipping mode This option sets the word aligner to use the
bit-slip port to alter the byte boundary one bit at
a time.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use manual word alignment
mode
Use the built-in
'synchronization state
machine'
This option sets the word aligner to use the
built-in synchronization state machine. The
behavior is similar to the PIPE synchronization
state machine with adjustable synchronization
thresholds.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Number of bad data words
before loss of synch state
Use this option with the built-in state machine to
transition from a synchronized state to an
unsynchronized state.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Number of consecutive valid
words before synch state is
reached
This option sets the word aligner to check for a
given number of good code groups. Use this
option with the built-in state machine in
conjunction with the Number of valid patterns
before synchronization state is reached
option to achieve synchronization.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Number of valid patterns
This option checks for the number of valid
before synch state is reached alignment patterns seen. Use this option with the
built-in state machine in conjunction with the
Number of consecutive valid words before
synch state is reached option to achieve
synchronization.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
3–21
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–7. MegaWizard Plug-In Manager Options (Page 9 for Basic Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
What is the word alignment
pattern length?
This option sets the word alignment length. The
available choices depend on whether 8B/10B is
used and which word alignment mode is used.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the word alignment
pattern?
Enter the word alignment pattern here. The
length of the alignment pattern is based on the
word alignment pattern length. In bit-slip mode,
this option triggers rx_patterndetect.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Flip word alignment pattern
bits
This option reverses the bit order of the
alignment pattern at a byte level to support
MSB-to-LSB transmission protocols. The default
transmission order is LSB-to-MSB.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Enable run-length violation
checking with a run length of
This option activates the run-length violation
circuit. You can program the run length at which
the circuit triggers the rx_rlv signal.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Enable word aligner output
reverse bit ordering
In manual bit-slip mode, this option creates an
input port rx_revbitorderwa to dynamically
reverse the bit order at the output of the receiver
word aligner. In Basic mode, this option statically
configures the receiver to always reverse the bit
order of the data at the output of the word aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_syncstatus
output port for pattern
detector and word aligner
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create
Refer to the Arria GX Transceiver Architecture
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
rx_patterndetect port to chapter in volume 2 of the Arria GX Device
indicate pattern detected
Handbook for information about this port.
Create rx_ctrldetect
port to indicate 8B/10B
decoder has detected a
control code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
3–22
Arria GX Device Handbook, Volume 2
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
Basic Mode
Table 3–7. MegaWizard Plug-In Manager Options (Page 9 for Basic Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Reference
Create rx_errdetect port
to indicate 8B/10B decoder
has detected an error code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create
This option is not available for Arria GX devices. Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
rx_revbyteorderwa to
enable receiver symbol swap
Altera Corporation
May 2008
3–23
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–10 shows page 10 of the MegaWizard Plug-In Manager for Basic
protocol mode set up. The Generate simulation model creates a
behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate Netlist option generates a netlist for the third
party EDA synthesis tool to estimate timing and resource utilization for
the ALT2GXB instance.
Figure 3–10. MegaWizard Plug-In Manager - ALT2GXB (EDA)
3–24
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–11 shows page 11 (last page) of the MegaWizard Plug-In
Manager for Basic protocol mode set up. You can select optional files on
this page. After you make your selections, click Finish to generate the
files.
Figure 3–11. MegaWizard Plug-In Manager - ALT2GXB (Summary)
PCI Express
(PIPE) Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for the
PCI Express (PIPE) mode. The MegaWizard Plug-In Manager provides a
warning if any of the settings you choose are illegal.
Altera Corporation
May 2008
3–25
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–12 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–12. MegaWizard Plug-In Manager - ALT2GXB (General)
3–26
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–8 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–8. MegaWizard Plug-In Manager Options (Page 3 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
—
Which protocol will you be
using?
Determines the specific protocol or modes under
which the transceiver operates. For PCI Express
(PIPE) mode, you must select the PCI Express
(PIPE) protocol.
Which subprotocol will you
be using?
In PCI Express (PIPE) mode, the subprotocols are
the supported link widths: 1 or 4.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook.
Enforce default settings for
this protocol
Selecting this option skips the PCI screen in the
PCI Express (PIPE) MegaWizard Plug-In Manager.
The PCI screen allows you to select the PCI
Express (PIPE) specific ports for your design. If you
select this option, all PCI Express (PIPE) specific
ports are used.
—
What is the operation mode? Only the receiver and transmitter (full duplex) mode
is allowed in the PCI Express (PIPE) mode.
Receiver-only and transmitter only modes are not
allowed.
—
What is the number of
channels?
—
This determines how many duplicate channels this
ALT2GXB instance contains. In a x4 subprotocol,
the number of channels increments by 4.
What is the deserializer block This option is unavailable in PCI Express (PIPE)
width?
mode.
—
Byte Serializer and Byte
Deserializer sections in the
Arria GX Architecture
chapter in volume 1 of the
Arria GX Device Handbook
What is the channel width?
This option determines the PLD-transceiver
interface width. Only 16-bit interface width is
supported.
What would you like to base
the setting on?
This option is unavailable because the data rate is
fixed at 2500 Mbps for PCI Express (PIPE) mode.
—
What is the data rate?
This option is unavailable because the data rate is
fixed at 2500 Mbps for PCI Express (PIPE) mode.
—
Altera Corporation
May 2008
3–27
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–8. MegaWizard Plug-In Manager Options (Page 3 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
What is the input clock
frequency?
Description
Reference
Determines the input reference clock frequency for PCI Express (PIPE) Mode
the transceiver. In PCI Express (PIPE) mode, only section in the Arria GX
Architecture chapter in
100 MHz is allowed.
volume 1 of the Arria GX
Device Handbook
What is the data rate division This option is unavailable in PCI Express (PIPE)
factor?
mode.
—
Figure 3–13 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–13. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
3–28
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–9 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–9. MegaWizard Plug-In Manager Options (Page 4 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
If you select this option, the transmitter input
reference clock (pll_inclk) drives the
receiver PLL input reference clock also.
If you do not select this option, the signal on the
rx_cruclk port drives the receiver PLL input
reference clock.
—
What is the GXB Transmitter
PLL bandwidth mode?
This option is not available in PCI Express
(PIPE) mode because the transmitter PLL
bandwidth is fixed at high.
—
What is the Receiver PLL
bandwidth mode?
This option is not available in PCI Express
(PIPE) mode because the receiver PLL
bandwidth is fixed at medium.
—
Train Receiver PLL clock from
PLL_inclk
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver clock recovery
PLL VCO and the CRU clock? unit (CRU) switchover between lock-to-data
and lock-to-reference. (There are additional
factors that affect the CRU’s transition.)
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create gxb_powerdown port This signal can be used to reset and power
down all circuits in the transceiver block. It
to power down the Quad
does not power down the REFCLK buffers and
reference clock lines.
Reset Control and Power
Down section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook.
Create gxb_enable port to
enable the Quad
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port
must be tied to the dedicated gigabit
transceiver block enable input pin.
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
Create rx_digitalreset
port for the digital portion of the
receiver
Altera Corporation
May 2008
Reset Control and Power
Down section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Receiver digital reset port. Resets the PCS
logic of the receiver. Altera recommends using
this port to implement the recommended reset
sequence.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
3–29
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–9. MegaWizard Plug-In Manager Options (Page 4 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS
logic of the transmitter. Altera recommends
using this port to implement the recommended
reset sequence.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
PLL locked indicator for the transmitter PLLs.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Lock-to-reference lock mode for the CRU. Use
with rx_locktodata.
rx_locktodata/rx_locktorefclk
0/0—CRU is in automatic mode
0/1—CRU is in lock-to-reference clock
1/0—CRU is in lock-to-data mode
1/1—CRU is in lock-to-data mode
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_locktodata port
to lock the RX PLL to the
received data
Lock-to-data control for the CRU. Use with
rx_locktorefclk.
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_pll_locked port Receiver PLL locked signal. Indicates if the
to indicate RX PLL is in lock with receiver PLL is phase locked to the CRU
reference clock.
the reference clock
Reset Control and Power
Down section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_freqlocked port CRU mode indicator port. Indicates if the CRU
to indicate RX PLL is in lock with is locked to data mode or locked to the
reference clock mode.
the received data
0—Receiver CRU is in lock-to-reference clock
mode
1—Receiver CRU is in lock-to-data mode
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
3–30
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–14 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–14. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
Altera Corporation
May 2008
3–31
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–10 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–10. MegaWizard Plug-In Manager Options (Page 5 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Signal detect port. In PCI Express (PIPE)
Create rx_signaldetect
port to indicate data input signal mode, indicates if a signal that meets the
specified range is present at the input of the
detection
receiver buffer. In all other modes,
rx_signaldetect is forced high and must
not be used as an indication of a valid signal at
receiver input.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create
This optional output port indicates Receiver
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is
allowed between FIFO read and write clocks.
Use this port for debugging purposes only.
Receiver Phase
Compensation FIFO section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is
allowed between FIFO read and write clocks.
Use this port for debug purposes only.
Transmitter Phase
Compensation FIFO section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase
Compensation FIFO with a non-transceiver
PLD clock.
PLD-Transceiver Interface
Clocking section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
This optional input port allows you to clock the
write side of the Transmitter Phase
Compensation FIFO with a non-transceiver
PLD clock.
PLD-Transceiver Interface
Clocking section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
3–32
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–10. MegaWizard Plug-In Manager Options (Page 5 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance
of the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to
instantiate the calibration block.
Calibration Block section in
the Arria GX Transceiver
Protocol Support and
Additional Features chapter
in volume 2 of the Arria GX
Device Handbook
Create active low
Power-down signal for the calibration block.
Calibration Block section in
the Arria GX Transceiver
powerdown the calibration block transmission and reception. Use this signal to Protocol Support and
Additional Features chapter
re-calibrate the termination resistors if
temperature and/or voltage changes warrant it. in volume 2 of the Arria GX
Device Handbook
cal_blk_powerdown port to Assertion of this signal may interrupt data
Altera Corporation
May 2008
3–33
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–12 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–15. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
3–34
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–11 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–11. MegaWizard Plug-In Manager Options (Page 6 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
In PIPE mode, a DC gain setting of 1 is forced.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage (RX
VC M )?
The receiver common mode voltage is
programmable. The options available are 0.85 V
and 1.2 V.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Force signal detection
This option disables the signal detect circuit. You
must not select this option as signal detect circuitry
is required for electrical idle detection at the
receiver.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
What is the signal detect and This option sets the trip point of the signal detect
signal loss threshold?
circuit. You must select a threshold level of 2 in PCI
Express (PIPE) mode.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Altera Corporation
May 2008
3–35
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–11. MegaWizard Plug-In Manager Options (Page 6 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Description
Reference
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the OCT. If checked,
this option turns off the receiver OCT.
—
What is the receiver
termination resistance?
In PCI Express (PIPE) mode, the only supported
receiver termination resistance is 100 Ω.
3–36
Arria GX Device Handbook, Volume 2
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–16 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–16. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–37
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–12 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–12. MegaWizard Plug-In Manager Options (Page 7 for PCI Express [PIPE] Mode)
ALT2GXB Setting
What is the Transmitter Buffer
Power (VCCH)?
Description
In PCI Express (PIPE) mode, the transmitter
buffer power is fixed at 1.2 V. You must connect
the VC C H power pins of a PCI Express (PIPE)
transceiver bank to a 1.2 V power supply. You
must select 1.2 V PCML I/O standard for the
transmitter data output pins.
What is the Transmitter Common In PCI Express (PIPE) mode, the transmitter
Mode Voltage (VCM)?
common mode voltage is fixed at 0.6 V.
Reference
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Use external Transmitter
termination
This option is available if you want to use an
external termination resistor instead of the OCT.
Checking this option turns off the transmitter
OCT.
—
Select the Transmitter
termination resistance
In PCI Express (PIPE) mode, the only supported
receiver termination resistance is 100 Ω.
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV in
steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
3–38
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–12. MegaWizard Plug-In Manager Options (Page 7 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Description
Reference
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on
the transmitter buffer using first post-tap. The
options available are 0, 1, 2, 3, 4, and 5.
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
Altera Corporation
May 2008
3–39
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–17 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode. If the Enforce default settings for this
protocol option is selected, this page does not appear in the MegaWizard
Plug-In Manager.
Figure 3–17. MegaWizard Plug-In Manager - ALT2GXB (PCI Express [PIPE] 1)
3–40
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–13 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–13. MegaWizard Plug-In Manager Options (Page 8 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Enable Rate match FIFO
This option enables bypassing of the rate match Low-latency
(Synchronous) PCI
FIFO in the receiver data path (Low-latency
Express (PIPE) Mode in
[Synchronous] PCI Express [PIPE] mode).
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Enable run-length violation
checking with a run length of
This option activates the run length violation
Word Aligner section in the
circuit. You can program the run length at which Arria GX Transceiver
Architecture chapter in
the circuit triggers the rx_rlv signal.
volume 2 of the Arria GX
Device Handbook
Enable fast recovery mode
This option creates the NFTS fast recovery IP
required to meet the PCI Express (PIPE)
specification in the PLD logic array.
NFTS Fast Recovery IP
(NFRI) section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_syncstatus output Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
port for pattern detector and
volume 2 of the Arria GX Device Handbook for
word aligner
information about this port.
Word Aligner section under
PCI Express (PIPE) Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Word Aligner section under
PCI Express (PIPE) Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_ctrldetect output Refer to the Arria GX Transceiver Protocol
port to indicate 8B/10B decoder Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
has detected a control code
information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_patterndetect
output port to indicate pattern
detected
Altera Corporation
May 2008
3–41
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–13. MegaWizard Plug-In Manager Options (Page 8 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Refer to the Arria GX Transceiver Protocol
Create tx_forceelecidle
input port to force the transmitter Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
to send Electrical Idle signals
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create tx_detectrxloop
input port as receiver detect or
loopback enable, depending on
the power state
tx_forcedispcompliance
input port to force negative
running disparity
Create tx_invpolarity to
allow Transmitter polarity
inversion
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook 2
for information about this port.
8B/10B Encoder section in
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted the Arria GX Transceiver
Architecture chapter in
at the transmitter PCS-PMA interface.
volume 2 of the Arria GX
Device Handbook\
3–42
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–18 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode. If the Enforce default settings for this
protocol option is selected, this page does not appear in the MegaWizard
Plug-In Manager.
Figure 3–18. MegaWizard Plug-In Manager - ALT2GXB (PCI Express [PIPE] 2)
Altera Corporation
May 2008
3–43
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–13 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–14. MegaWizard Plug-In Manager Options (Page 9 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Create pipestatus output
port for PIPE interface status
signal
Description
Reference
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Receiver Status section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create pipedatavalid output Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
port to indicate valid data from
volume 2 of the Arria GX Device Handbook for
the receiver
information about this port.
PCI Express (PIPE) Mode
section Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create pipeelecidle output
port for Electrical Idle detect
status signal
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create pipephydonestatus
output port to indicate PIPE
completed power state
transitions
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create
Refer to the Arria GX Transceiver Protocol
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
pipe8b/10binvpolarity to Support and Additional Features chapter in
enable polarity inversion in PIPE volume 2 of the Arria GX Device Handbook for
information about this port.
Create powerdn input port for
PIPE powerdown directive
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
3–44
Arria GX Device Handbook, Volume 2
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–19 shows page 10 of the MegaWizard Plug-In Manager for the
PCI Express (PIPE) protocol selection. The Generate simulation model
option creates a behavioral model (.vo or .vho) of the transceiver instance
for third-party simulators. The Generate a netlist for synthesis area and
timing estimation option creates a netlist file (.syn) for third-party
synthesis tools.
Figure 3–19. MegaWizard Plug-In Manager - ALT2GXB (EDA)
Altera Corporation
May 2008
3–45
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–20 shows page 11 (the last page) of the MegaWizard Plug-In
Manager for the PCI Express (PIPE) protocol set up. You can select
optional files on this page. After you make your selections, click Finish to
generate the files.
Figure 3–20. MegaWizard Plug-In Manager - ALT2GXB (Summary)
XAUI Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
XAUI mode. The MegaWizard Plug-In Manager provides a warning if
any of the settings you choose are illegal.
1
3–46
Arria GX Device Handbook, Volume 2
The word aligner and rate matcher operations and patterns are
pre-configured for XAUI mode and cannot be altered.
Altera Corporation
May 2008
XAUI Mode
Figure 3–21 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–21. MegaWizard Plug-In Manager - ALT2GXB (General)
Table 3–15 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–15. MegaWizard Plug-In Manager Options (Page 3 for XAUI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Which protocol will you be
using?
Determines the specific protocol or modes under
which the transceiver operates. For XAUI mode you
must select the XAUI.
—
Which subprotocol will you
be using?
Not applicable to XAUI mode.
—
Altera Corporation
May 2008
3–47
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–15. MegaWizard Plug-In Manager Options (Page 3 for XAUI Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Selecting this option skips the XAUI screen of the
XAUI MegaWizard Plug-In Manager. The XAUI
screen allows you to select the XAUI-specific ports
for your design. If you select this option, all
XAUI-specific ports are used.
—
What is the operation mode? Only receiver and transmitter (full duplex) is allowed
in the XAUI protocol. Receiver only and transmitter
only modes are not allowed.
—
What is the number of
channels?
—
Enforce default settings for
this protocol
This selects how many duplicate channels this
ALT2GXB instance contains. In XAUI mode, the
number of channels increments by 4.
What is the deserializer block XAUI mode only operates in a single-width mode.
width?
—
What is the channel width?
Byte Serializer and Byte
This option determines the transceiver-to-PLD
interface width. Only 16-bit channel width is allowed Deserializer sections in the
Arria GX Transceiver
in XAUI mode.
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What would you like to base
the setting on?
This option is not available in XAUI mode.
—
What is the data rate?
The data rate is fixed at 3.125 Gbps for the XAUI
protocol.
—
What is the input clock
frequency?
Determines the input reference clock frequency for
the transceiver. The Quartus II software
automatically selects the input reference clock
frequency based on the entered data rate.
—
What is the data rate division This option is not available in XAUI mode.
factor?
3–48
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
XAUI Mode
Figure 3–22 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–22. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
Altera Corporation
May 2008
3–49
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–16 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–16. MegaWizard Plug-In Manager Options (Page 4 for XAUI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Train Receiver PLL clock from
PLL inclk
If you turn this option on, your design uses the
input reference clock to the transmitter PLL to train
the receiver PLL. This reduces the need to supply
a separate receiver PLL reference clock.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the GXB Transmitter
PLL bandwidth mode?
In XAUI mode, only high bandwidth is supported
for the transmitter PLL.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Receiver PLL
bandwidth mode?
In XAUI mode, only medium bandwidth is
supported for the receiver PLL and VCO.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect CRU’s
transition.)
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
3–50
Arria GX Device Handbook, Volume 2
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
XAUI Mode
Table 3–16. MegaWizard Plug-In Manager Options (Page 4 for XAUI Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS portion
of the receiver. Altera recommends using this port
along with logic to implement the recommended
reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS
portion of the transmitter. Altera recommends
using this port along with logic to implement the
recommended reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_pll_locked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the reference clock
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_freqlocked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the received data
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–51
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–22 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–23. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
3–52
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
XAUI Mode
Table 3–17 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–17. MegaWizard Plug-In Manager Options (Page 5 for XAUI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Refer to the Arria GX Transceiver Architecture
Create rx_signaldetect
port to indicate data input signal chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
detection
Create
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This optional output port indicates Receiver Phase Receiver Phase
debug_rx_phase_comp_fi Compensation FIFO overflow/under run condition. Compensation FIFO
Note that no PPM difference is allowed between section in the Arria GX
fo_error output port
Create
FIFO read and write clocks. Use this port for
debug purpose only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp_fi Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed section in the Arria GX
fo_error output port
between FIFO read and write clocks. Use this port Transceiver Architecture
chapter in volume 2 of the
for debug purposes only.
Arria GX Device
Handbook.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
Transmitter Phase
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Compensation FIFO
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–53
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–17. MegaWizard Plug-In Manager Options (Page 5 for XAUI Mode) (Part 2 of 2)
ALT2GXB Setting
Use calibration block
Description
Reference
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create cal_blk_powerdown Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
to power down the calibration
Handbook. for information about this port.
block
3–54
Arria GX Device Handbook, Volume 2
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
XAUI Mode
Figure 3–24 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–24. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
Altera Corporation
May 2008
3–55
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–18 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–18. MegaWizard Plug-In Manager Options (Page 6 for XAUI Mode)
ALT2GXB Setting
Description
Reference
Enable static equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
What is the Receiver
Common Mode Voltage (RX
VCM)?
Receiver Buffer section in
The receiver common mode voltage is
programmable. The selections available are 0.85 V the Arria GX Transceiver
Architecture chapter in
or 1.2 V.
volume 2 of the Arria GX
Device Handbook.
Force signal detection
This option is available only in PCI Express (PIPE)
mode.
Receiver Buffer Section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the signal detect and This option is available only in PCI Express (PIPE)
signal loss threshold?
mode.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. If checked, this option turns off the
receiver OCT.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
termination resistance?
This option selects the receiver termination value.
In Arria GX devices, the receiver termination value
is fixed at 100 Ω.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
3–56
Arria GX Device Handbook, Volume 2
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
XAUI Mode
Figure 3–25 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–25. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–57
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–19 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–19. MegaWizard Plug-In Manager Options (Page 7 for XAUI Mode)
ALT2GXB Setting
Description
Reference
This setting is for information only and is used
to calculate the VO D from the buffer power
supply (VC C H ) and the transmitter termination
to derive the proper VO D range. In XAUI mode,
this option is fixed at 1.5 V
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Transmitter Common The transmitter common mode voltage setting
Mode Voltage (VCM)?
is selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. Checking this option turns off
the transmitter OCT.
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Select the Transmitter
termination resistance
This option selects the transmitter termination Transmitter Buffer section
value. This option is also used in the calculation in the Arria GX Transceiver
of the available VOD.
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV
in steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on Transmitter Buffer section
in the Arria GX Transceiver
the transmitter buffer using first post-tap. The
Architecture chapter in
options available are 0, 1, 2, 3, 4, and 5.
volume 2 of the Arria GX
Device Handbook.
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
What is the Transmitter Buffer
Power (VCCH)?
3–58
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
XAUI Mode
Figure 3–26 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–26. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
Altera Corporation
May 2008
3–59
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–20 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–20. MegaWizard Plug-In Manager Options (Page 8 for XAUI Mode)
ALT2GXB Setting
Description
Reference
Which loopback option would
you like?
There are two option available in XAUI mode:
no loopback and serial loopback.
● No loopback - this is the default mode.
● Serial loopback - if you select serial
loopback, the rx_seriallpbken port is
available to control the serial loopback
feature dynamically. A 1'b1 enables serial
loopback and a 1'b0 disables loopback on a
channel-by-channel basis. Altera
recommends controlling all four channels
simultaneously. A digital reset must be
asserted for the transceiver.
Loopback Modes section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Which reverse loopback option
would you like?
This option is not available in XAUI mode.
Loopback Modes section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
3–60
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
XAUI Mode
Figure 3–27 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode. If the Enforce default settings for this protocol option is
selected, this page does not appear in the MegaWizard Plug-In Manager.
Figure 3–27. MegaWizard Plug-In Manager - ALT2GXB (XAUI)
Altera Corporation
May 2008
3–61
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–21 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–21. MegaWizard Plug-In Manager Options (Page 9 for XAUI Mode)
ALT2GXB Setting
Enable run-length violation
checking with a run length of
Description
Reference
Word Aligner section in the
This option activates the run-length violation
circuit. You can program the run length at which Arria GX Transceiver
Architecture chapter in
the circuit triggers the rx_rlv signal.
volume 2 of the Arria GX
Device Handbook.
Create rx_syncstatus output Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
port for pattern detector and
Handbook for information about this port.
word aligner
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_patterndetect
port to indicate pattern detected
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_invpolarity to
enable word aligner polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the received data at the
input of the word aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_ctrldetect port
to indicate 8B/10B decoder has
detected a control code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_errdetect port to
indicate 8B/10B decoder has
detected an error code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create tx_invpolarity to
allow Transmitter polarity
inversion
8B/10B Encoder section in
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted the Arria GX Transceiver
Architecture chapter in
at the transmitter PCS-PMA interface.
volume 2 of the Arria GX
Device Handbook.
3–62
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
XAUI Mode
Figure 3–28 shows page 10 of the MegaWizard Plug-In Manager for the
XAUI protocol selection. The Generate simulation model option creates
a behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate Netlist option generates a netlist for the third
party EDA synthesis tool to be able to estimate timing and resource
utilization for the ALT2GXB instance.
Figure 3–28. MegaWizard Plug-In Manager - ALT2GXB (EDA)
Altera Corporation
May 2008
3–63
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–29 shows page 11 (the last page) of the MegaWizard Plug-In
Manager for the XAUI protocol set up. You can select optional files on this
page. After you make your selections, click Finish to generate the files.
Figure 3–29. MegaWizard Plug-In Manager - ALT2GXB (Summary)
GIGE Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
GIGE mode. The MegaWizard Plug-In Manager provides a warning if
any of the settings you choose are illegal.
3–64
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Figure 3–30 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–30. MegaWizard Plug-In Manager - ALT2GXB (General)
Altera Corporation
May 2008
3–65
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–22 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–22. MegaWizard Plug-In Manager Options (Page 3 for GIGE Mode) (Part 1 of 2)
ALT2GXB Setting
Which protocol will you be
using?
Which subprotocol will you
be using?
Description
Reference
Determines the specific protocol or modes under
which the transceiver operates. For GIGE mode,
you must select the GIGE.
—
The options available here are:
None: Select this option for GIGE mode, when
UNH-IOL Compliance is not required.
● GIGE-Enhanced: Select this option when your
system implementation has Auto-Negotiation
phase or if either /K28.1/, /K28.7/ code group is
used in the synchronization ordered set /K/D/.
—
●
Selecting the GIGE-Enhanced mode enables
7-bit word alignment mode and Rate matcher
insertion/deletion of C1/C2 configuration
ordered sets as required by the Auto negotiation
test suite used for UNH-IOL compliance. Three
additional output ports: rx_runningdisp,
rx_rmfifodatainserted and
rx_rmfifodatadeleted are also enabled
automatically when this option is selected.
Enforce default settings for
this protocol
Selecting this option skips the GIGE screen of the
GIGE MegaWizard Plug-In Manager. The GIGE
screen allows you to select the GIGE-specific ports
for your design. If you select this option, all
GIGE-specific ports are used.
—
What is the operation mode? The transmitter only and receiver and transmitter
(full duplex) modes are allowed in GIGE protocol.
The receiver only mode is not available.
—
What is the number of
channels?
—
This selects how many duplicate channels this
ALT2GXB instance contains. In GIGE mode, the
number of channels increments by 1.
What is the deserializer block This option is unavailable in GIGE mode.
width?
What is the channel width?
This option determines the PLD-transceiver
interface width. Only 8-bit interface width is
supported.
What would you like to base
the setting on?
This option is unavailable because the data rate is
fixed at 1250 Mbps for GIGE mode.
3–66
Arria GX Device Handbook, Volume 2
—
Byte Serializer and Byte
Deserializer sections in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
—
Altera Corporation
May 2008
GIGE Mode
Table 3–22. MegaWizard Plug-In Manager Options (Page 3 for GIGE Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
What is the data rate?
This option is unavailable because the data rate is
fixed at 1250 Mbps for GIGE mode.
—
What is the input clock
frequency?
Determines the input reference clock frequency for
the transceiver. In GIGE mode, input reference
clock frequencies of 62.5 MHz and 125 MHz are
supported.
GIGE Mode section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the data rate division This option is unavailable in GIGE mode.
factor?
Altera Corporation
May 2008
—
3–67
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–31 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–31. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
3–68
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–23 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–23. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
If you select this option, the transmitter input
reference clock (pll_inclk) drives the receiver
PLL input reference clock also.
If you do not select this option, the signal on the
rx_cruclk port drives the receiver PLL input
reference clock.
—
What is the GXB Transmitter
PLL bandwidth mode?
This option is not available in GIGE mode because
the transmitter PLL bandwidth is fixed at high.
—
What is the Receiver PLL
bandwidth mode?
This option is not available in GIGE mode because
the receiver PLL bandwidth is fixed at medium.
—
Train Receiver PLL clock from
PLL_inclk
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect the CRU’s
transition.)
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
Altera Corporation
May 2008
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–69
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–23. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS logic of Reset Control and Power
the receiver. Altera recommends using this port to Down section in the
Arria GX Transceiver
implement the recommended reset sequence.
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS logic
of the transmitter. Altera recommends using this
port to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_pll_locked port Refer to the Arria GX Transceiver Protocol
to indicate RX PLL is in lock with Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
the reference clock
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–70
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–23. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Reference
Create rx_freqlocked port Refer to the Arria GX Transceiver Protocol
to indicate RX PLL is in lock with Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
the received data
information about this port.
This option is not available in GIGE mode.
Create rx_signaldetect
port to indicate data input signal
detection
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–71
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–31 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–32. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
3–72
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–23 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–24. MegaWizard Plug-In Manager Options (Page 5 for GIGE Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
This option is not available in GIGE mode.
Create rx_signaldetect
port to indicate data input signal
detection
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–73
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–24. MegaWizard Plug-In Manager Options (Page 5 for GIGE Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create active low
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
cal_blk_powerdown to
power down the calibration
block
3–74
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Figure 3–33 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–33. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
Altera Corporation
May 2008
3–75
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–25 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–25. MegaWizard Plug-In Manager Options (Page 6 for GIGE Mode)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
This enables the DC gain option and the legal
settings are 0, 1, 2, and 3.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage (RX
VCM)?
The receiver common mode voltage is
programmable. The selections available are 0.85 V
and 1.2 V.
Receiver Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Force signal detection
This option is unavailable in GIGE mode and is
always forced selected.
—
What is the signal detect and This option is unavailable in GIGE mode as signal
signal loss threshold?
detection is forced.
—
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip termination
OCT. If checked, this option turns off the receiver
OCT.
—
What is the Receiver
termination resistance?
In GIGE mode, the only supported receiver
termination resistance is 100 Ω.
3–76
Arria GX Device Handbook, Volume 2
Receiver Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Altera Corporation
May 2008
GIGE Mode
Figure 3–34 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–34. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–77
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–26 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–26. MegaWizard Plug-In Manager Options (Page 7 for GIGE Mode)
ALT2GXB Setting
What is the Transmitter Buffer
Power (VCCH)?
Description
Reference
In GIGE mode, the transmitter buffer power can
be either 1.2 V or 1.5 V.
You must connect the VC C H power pins of a GIGE
transceiver bank to a 1.2 V or 1.5 V power supply.
You must select 1.2 V PCML or 1.5 V PCML I/O
standard for the transmitter data output pins.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
What is the Transmitter Common In GIGE mode, the transmitter common mode
Mode Voltage (VCM)?
voltage is selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
—
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. Checking this option turns off
the transmitter OCT.
Select the Transmitter
termination resistance
In GIGE mode, the only supported receiver
termination resistance is 100 Ω.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV to 1200 mV in
steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
3–78
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–26. MegaWizard Plug-In Manager Options (Page 7 for GIGE Mode)
ALT2GXB Setting
Description
Reference
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on
the transmitter buffer using first post-tap. The
options available are 0, 1, 2, 3, 4, and 5.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
Altera Corporation
May 2008
3–79
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–35 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–35. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
3–80
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–27 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–27. MegaWizard Plug-In Manager Options (Page 8 for GIGE Mode)
ALT2GXB Setting
Which loopback option would
you like?
Altera Corporation
May 2008
Description
Reference
No loopback and serial loopback options are
available in GIGE mode.
No loopback is the default mode. If you select
serial loopback, the rx_seriallpbken port is
available to control the serial loopback feature
dynamically. A 1'b1 enables serial loopback and
a 1'b0 disables loopback on a
channel-by-channel basis.
Loopback Modes section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
3–81
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–36 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode. If the Enforce default settings for this protocol option is
selected, this page does not appear in the MegaWizard Plug-In Manager.
Figure 3–36. MegaWizard Plug-In Manager - ALT2GXB (GIGE)
3–82
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–28 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–28. MegaWizard Plug-In Manager Options (Page 9 for GIGE Mode)
ALT2GXB Setting
Enable run-length violation
checking with a run length of
Description
Reference
Word Aligner section in the
This option activates the run-length violation
circuit. You can program the run length at which Arria GX Transceiver
Architecture chapter in
the circuit triggers the rx_rlv signal.
volume 2 of the Arria GX
Device Handbook
Create rx_syncstatus output Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
port for pattern detector and
volume 2 of the Arria GX Device Handbook for
word aligner
information about this port.
Word Aligner section under
GIGE mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Create rx_patterndetect
output port to indicate pattern
detected
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Word Aligner section under
GIGE Mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Create rx_invpolarity to
enable word aligner polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the received data at the
input of the word aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_ctrldetect output Refer to the Arria GX Transceiver Architecture
port to indicate 8B/10B decoder chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
has detected a control code
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_errdetect port to
indicate 8B/10B decoder has
detected an error code
Altera Corporation
May 2008
3–83
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–28. MegaWizard Plug-In Manager Options (Page 9 for GIGE Mode)
ALT2GXB Setting
Description
Reference
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create tx_invpolarity to
allow Transmitter polarity
inversion
8B/10B Encoder section in
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted the Arria GX Transceiver
Protocol Support and
at the transmitter PCS-PMA interface.
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
3–84
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Figure 3–37 shows page 10 of the MegaWizard Plug-In Manager for the
GIGE protocol selection. The Generate simulation model option creates
a behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate a netlist for synthesis area and timing
estimation option creates a netlist file (.syn) for third-party synthesis
tools.
Figure 3–37. MegaWizard Plug-In Manager - ALT2GXB (EDA)
Altera Corporation
May 2008
3–85
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–38 shows page 11 (the last page) of the MegaWizard Plug-In
Manager for the GIGE protocol set up. You can select optional files on this
page. After you make your selections, click Finish to generate the files.
Figure 3–38. MegaWizard Plug-In Manager - ALT2GXB (Summary)
SDI Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for SDI
mode. The MegaWizard Plug-In Manager provides a warning if any of
the settings you choose are illegal.
3–86
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–39 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–39. MegaWizard Plug-In Manager - ALT2GXB (General)
Altera Corporation
May 2008
3–87
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–29 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–29. MegaWizard Plug-In Manager Options (Page 3 for SDI Mode)
ALT2GXB Setting
Which protocol will you be
using?
Which subprotocol will you
be using?
Enforce default settings for
this protocol
Description
Reference
Determines the specific protocol or modes under
which the transceiver operates. For SDI mode, you
must select the SDI protocol.
—
In SDI mode, the two available subprotocols are:
3G: third-generation (3 Gbps) SDI at 2970 Mbps
or 2967 Mbps
● HD: high-definition SDI at 1485 Mbps or
1483.5 Mbps
—
This option is not available in SDI mode.
—
●
What is the operation mode? The transmitter only, receiver only, and receiver and
transmitter (full duplex) modes are allowed in SDI
protocol.
—
What is the number of
channels?
This selects how many duplicate channels this
ALT2GXB instance contains.
—
What is the deserializer block SDI mode only operates in single-width mode.
width?
Double-width mode is not supported.
—
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the channel width?
This option determines the transceiver-to-PLD
interface width. In SDI mode, 10-bit and 20-bit
channel widths are allowed. In 10-bit configuration,
the byte serializer is not used. In 20-bit
configuration, the byte serializer is used.
What would you like to base
the setting on?
This option not available in SDI mode.
—
What is the data rate?
This field is automatically set based on the
subprotocol (3G or HD) and the input clock
frequency selection.
—
What is the input clock
frequency?
Four input reference clock options are available,
depending on the subprotocol (3G or HD).
● For 3G subprotocol, the available options are:
148.5 MHz and 297 MHz for 2970 Mbps data
rate and 148.35 MHz and 296.7 MHz for
2967 Mbps data rate
● For HD subprotocol, the available option are:
74.25 MHz and 148.5 MHz for 1485 Mbps data
rate and 74.175 MHz and 148.35 MHz for
1483.5 Mbps data rate
—
What is the data rate division This option is not available in SDI Mode.
factor?
3–88
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
SDI Mode
Figure 3–40 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–40. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
Altera Corporation
May 2008
3–89
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–30 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–30. MegaWizard Plug-In Manager Options (Page 4 for SDI Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
Train Receiver PLL clock from
PLL inclk
If you turn this option on, your design uses the
input reference clock to the transmitter PLL to train
the receiver PLL. This reduces the need to supply
a separate receiver PLL reference clock.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the GXB Transmitter
PLL bandwidth mode?
Three available bandwidth options are high,
medium, and low. The default transmitter PLL
bandwidth is high.
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Receiver PLL
bandwidth mode?
Three available bandwidth options are high,
medium, and low. The default receiver PLL
bandwidth is medium.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect CRU’s
transition.)
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
3–90
Arria GX Device Handbook, Volume 2
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
SDI Mode
Table 3–30. MegaWizard Plug-In Manager Options (Page 4 for SDI Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS portion
of the receiver. Altera recommends using this port
along with logic to implement the recommended
reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create tx_digitalreset
port for the digital portion of the
receiver
Transmitter digital reset port. Resets the PCS
portion of the transmitter. Altera recommends
using this port along with logic to implement the
recommended reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_pll_locked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the reference clock
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_freqlocked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the received data
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–91
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–30. MegaWizard Plug-In Manager Options (Page 4 for SDI Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Refer to the Arria GX Transceiver Architecture
Create rx_signaldetect
port to indicate data input signal chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
detection
Create
Reference
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This optional output port indicates Receiver Phase Receiver Phase
debug_rx_phase_comp_fi Compensation FIFO overflow/under run condition. Compensation FIFO
Note that no PPM difference is allowed between section in the Arria GX
fo_error output port
Create
FIFO read and write clocks. Use this port for
debug purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp_fi Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed section in the Arria GX
fo_error output port
between FIFO read and write clocks. Use this port Transceiver Architecture
chapter in volume 2 of the
for debug purposes only.
Arria GX Device
Handbook.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
Transceiver Clocking
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation section in the Arria GX
Transceiver Architecture
FIFO with a non-transceiver PLD clock.
chapter in volume 2 of the
Arria GX Device
Handbook.
3–92
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–40 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–41. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
Altera Corporation
May 2008
3–93
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–30 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–31. MegaWizard Plug-In Manager Options (Page 5 for SDI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Refer to the Arria GX Transceiver Architecture
Create rx_signaldetect
port to indicate data input signal chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
detection
Create
Reference
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This optional output port indicates Receiver Phase Receiver Phase
debug_rx_phase_comp_fi Compensation FIFO overflow/under run condition. Compensation FIFO
Note that no PPM difference is allowed between section in the Arria GX
fo_error output port
Create
FIFO read and write clocks. Use this port for
debug purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp_fi Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed section in the Arria GX
fo_error output port
between FIFO read and write clocks. Use this port Transceiver Architecture
chapter in volume 2 of the
for debug purposes only.
Arria GX Device
Handbook.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
Transceiver Clocking
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation section in the Arria GX
Transceiver Architecture
FIFO with a non-transceiver PLD clock.
chapter in volume 2 of the
Arria GX Device
Handbook.
3–94
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–31. MegaWizard Plug-In Manager Options (Page 5 for SDI Mode) (Part 2 of 2)
ALT2GXB Setting
Use calibration block
Description
Reference
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create cal_blk_powerdown Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
to power down the calibration
Handbook for information about this port.
block
Altera Corporation
May 2008
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
3–95
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–42 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–42. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
3–96
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–32 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–32. MegaWizard Plug-In Manager Options (Page 6 for SDI Mode)
ALT2GXB Setting
Description
Reference
Enable static equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
This enables the DC gain option. The legal settings
are 0, 1, 2, 3.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage (RX
VCM)?
The receiver common mode voltage is
programmable. The selections available are 0.85 V
and 1.2 V.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Force signal detection
This option is not available in SDI mode.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the signal detect and This option is not available in SDI mode.
signal loss threshold?
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use external receiver
termination
This option is available if you want to use an external
termination resistor instead of the on-chip termination
OCT. If checked, this option turns off the receiver
OCT.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the receiver
termination resistance?
This option selects the receiver termination value.
The receiver termination value is fixed at 100 Ω in
Arria GX devices.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
3–97
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–43 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–43. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
3–98
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–33 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–33. MegaWizard Plug-In Manager Options (Page 7 for SDI Mode)
ALT2GXB Setting
Description
Reference
This setting is for information only and is used to
calculate the VO D from the buffer power supply
(VC C H ) and the transmitter termination to derive
the proper VO D range. In SDI mode, this option is
fixed at 1.5 V.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Transmitter Common The transmitter common mode voltage setting is
Mode Voltage (VCM)?
selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. Checking this option turns off
the transmitter OCT.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Select the Transmitter
termination resistance
This option selects the transmitter termination
value. This option is also used in the calculation
of the available VOD.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV in
steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on
the transmitter buffer using first post-tap. The
options available are 0, 1, 2, 3, 4, and 5.
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
What is the Transmitter Buffer
Power (VCCH)?
Altera Corporation
May 2008
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
3–99
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–44 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–44. MegaWizard Plug-In Manager - ALT2GXB (Reconfig)
3–100
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–34 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–34. MegaWizard Plug-In Manager Options (Page 8 for SDI Mode)
Description
Reference
What do you want to be
able to dynamically
reconfigure in the
transceiver?
ALT2GXB Setting
Available options are:
● Analog controls: Dynamically reconfigures the
PMA control settings like Vod, Pre-emphasis,
Equalization, etc.
● Channel Internals: Enables MIF-based
reconfiguration among modes that have different
data paths within the channel but same PLD
interface signals. When this option is enabled,
two mutually exclusive options, Enable Channel
and Transmitter PLL Reconfiguration and
Use alternate reference clock, are available.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is the starting
channel number?
The range for the dynamic reconfiguration starting
channel number setting is 0—156, in multiples of 4.
It is in multiples of 4 because the dynamic
reconfiguration interface is per transceiver block.
The range of 0—156 is the logical channel address,
based purely on the number of possible ALT2GXB
instances.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Figure 3–45 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode. This page appears only when the Enable Channel and
Transmitter PLL Reconfiguration option is selected in the Reconfig page
(Page 8).
Altera Corporation
May 2008
3–101
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–45. MegaWizard Plug-In Manager - ALT2GXB (Reconfig Alt PLL)
Table 3–35 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–35. MegaWizard Plug-In Manager Options (Page 9 for SDI Mode)
ALT2GXB Setting
Use alternate Transmitter
PLL and Receiver PLL
Description
Selecting this option sets up the transmitter
channel to listen to one of the two PLLs in its
transceiver block. The information regarding
which PLL it listens to is stored in the MIF.
3–102
Arria GX Device Handbook, Volume 2
Reference
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Altera Corporation
May 2008
SDI Mode
Figure 3–46 shows page 10 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode. This page appears only when the Enable
Channel and Transmitter PLL Reconfiguration option is selected in the
Reconfig page (Page 8).
Figure 3–46. MegaWizard Plug-In Manager - ALT2GXB (Reconfig Clks 1)
Altera Corporation
May 2008
3–103
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–36 describes the available options on page 10 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–36. MegaWizard Plug-In Manager Options (Page 10 for SDI Mode)
ALT2GXB Setting
Description
Reference
This option allows you to select the logical index for the
PLL that you intend to use with the current configuration.
This option is meaningful only if you select the Use
alternate Transmitter PLL and Receiver PLL option on
the Reconfig Alt PLL page.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
How many input clocks? This field allows you to select the number of reference
clock inputs needed to meet your CMU PLL
reconfiguration design goals. A maximum of five input
reference clocks are allowed.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is the main PLL
logical reference clock
index?
What is the selected
input clock source for
the Transmitter PLL and
Receiver PLL?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL, this
option allows you to select the clock source for the
current configuration.
If you select the Use alternate Transmitter PLL and
What is the selected
Receiver PLL option, you can select the clock source for
input clock source for
the alternate Transmitter the alternate Transmitter PLL and the Receiver PLL.
PLL and Receiver PLL?
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Stratix II GX
Device Handbook.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is the reconfig
protocol driven by clock
0?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL, these
options allow you to select the functional mode for the
respective reference clock source.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is clock 0 input
frequency?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL, these
options allow you to select the reference clock
frequencies for each clock source.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Use clock 0 reference
clock divider
If you select more than one input reference clock source
for the transmitter and/or receiver PLL, these options
allow you to instruct the MegaWizard about the REFCLK
pre-divider on input reference clocks.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Figure 3–47 shows page 11 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode. This page appears only when the Enable
Channel and Transmitter PLL Reconfiguration option is selected in the
Reconfig page (Page 8).
3–104
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–47. MegaWizard Plug-In Manager - ALT2GXB (Reconfig 2)
Altera Corporation
May 2008
3–105
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–37 describes the available options on page 11 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–37. MegaWizard Plug-In Manager Options (Page 11 for SDI Mode)
ALT2GXB Setting
Description
Reference
How should the receivers
be clocked?
Three options are available:
● Share a single transmitter core clock between
receivers
● Use the respective channel transmitter core clock
● Use the respective channel receiver core clocks
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
How should the
transmitters be clocked?
Two options are available:
● Share a single transmitter core clock between
transmitters
● Use the respective channel transmitter core clocks
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Create
This optional input port allows you to dynamically
reverse the bit order at the output of the receiver word
aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Stratix II GX
Device Handbook.
You can select various control and status signals
depending on what protocol(s) you intend to
dynamically reconfigure the transceiver to.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
rx_revbitorderwa
input port to use receiver
enable bit reversal
Check a control box to use
the corresponding control
port
3–106
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–48 shows page 12 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode.
Figure 3–48. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
Altera Corporation
May 2008
3–107
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–38 describes the available options on page 12 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–38. MegaWizard Plug-In Manager Options (Page 12 for SDI Mode)
ALT2GXB Setting
Description
Reference
Which loopback option would
you like?
There are two options available in SDI mode: no
loopback and serial loopback.
● No loopback - this is the default mode.
● Serial loopback - if you select serial loopback,
the rx_seriallpbken port is available to
control the serial loopback feature
dynamically. A 1'b1 enables serial loopback
and a 1'b0 disables loopback on a
channel-by-channel basis. Altera
recommends controlling all four channels
simultaneously. A digital reset must be
asserted for the transceiver.
Loopback Modes section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Reverse Loopback option
This option is not available in SDI mode.
Loopback Modes section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
3–108
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–49 shows page 13 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode. If the Enforce default settings for this protocol
option is selected, this page does not appear in the MegaWizard.
Figure 3–49. MegaWizard Plug-In Manager - ALT2GXB (SDI 1)
Altera Corporation
May 2008
3–109
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–39 describes the available options on page 13 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–39. MegaWizard Plug-In Manager Options (Page 13 for SDI Mode) (Part 1 of 2)
ALT2GXB Setting
Enable byte ordering block
Description
This option is not available in Arria GX devices.
Enable 8B/10B decoder/encoder This option is force-selected in SDI mode since
8B/10B decoder/encoder is always used.
Reference
—
8B/10 Encoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
8B/10 Encoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create tx_forcedisp to
enable Force disparity and use
tx_dispval to code up the
incoming word using positive or
negative disparity
This option allows you to force positive or
negative disparity on transmitted data in 8B/10B
configurations.
Enable rate match FIFO
This option is not available in SDI mode since the Rate Matcher section in
rate match FIFO is always bypassed.
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Flip Receiver output data bits
This option reverses the bit order of the data at
the receiver-PLD interface at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
Flip Transmitter input data bits
This option reverses the bit order of the data bits
at the input of the transmitter at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
Enable Transmitter bit reversal
This option inverts (flips) the bit order of the data
bits at the transmitter PCS-PMA interface at a
byte level to support MSBit-to-LSBit transmission
protocols. The default transmission is
LSBit-to-MSBit.
3–110
Arria GX Device Handbook, Volume 2
8B/10B Encoder section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Altera Corporation
May 2008
SDI Mode
Table 3–39. MegaWizard Plug-In Manager Options (Page 13 for SDI Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create rx_invpolarity to
enable word aligner polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the received data at the
input of the word aligner.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create tx_invpolarity to
allow Transmitter polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted
at the transmitter PCS-PMA interface.
8B/10B Encoder section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Altera Corporation
May 2008
3–111
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–50 shows page 14 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode.
Figure 3–50. MegaWizard Plug-In Manager - ALT2GXB (SDI 2)
3–112
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–40 describes the available options on page 14 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–40. MegaWizard Plug-In Manager Options (Page 14 for SDI Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
Use manual word alignment
mode
Word Aligner section in
This option is not available in SDI mode as the
word aligner uses the bit-slip port to alter the byte the Arria GX Transceiver
Architecture chapter in
boundary one bit at a time.
volume 2 of the
Stratix II GX Device
Handbook.
Use manual bitslipping mode
Word Aligner section in
This option sets the word aligner to use the
bit-slip port to alter the byte boundary one bit at a the Arria GX Transceiver
time. This option is force selected in SDI mode. Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Use the built-in 'synchronization
state machine'
Word Aligner section in
This option is not available in SDI mode as the
word aligner uses the bit-slip port to alter the byte the Arria GX Transceiver
Architecture chapter in
boundary one bit at a time.
volume 2 of the
Stratix II GX Device
Handbook.
Number of bad data words before This option is not available in SDI mode.
loss of synch state
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Number of consecutive valid
words before synch state is
reached
This option is not available in SDI mode.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Number of valid patterns before
synch state is reached
This option is not available in SDI mode.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
What is the word alignment
pattern length?
This option sets the word alignment length. The
available choices are 7 bit and 10 bit.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Altera Corporation
May 2008
3–113
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–40. MegaWizard Plug-In Manager Options (Page 14 for SDI Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
What is the word alignment
pattern?
Enter the word alignment pattern here. The
length of the alignment pattern is based on the
word alignment pattern length.
Flip word alignment pattern bits
This option reverses the bit order of the alignment
pattern at a byte level to support MSB-to-LSB
transmission protocols. The default transmission
order is LSB-to-MSB.
Enable run-length violation
checking with a run length of
This option activates the run-length violation
circuit. You can program the run length at which
the circuit triggers the rx_rlv signal.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Enable word aligner output
reverse bit ordering
This option statically configures the receiver to
reverse the bit order of the data at the output of
the word aligner.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create rx_syncstatus output Refer to the Stratix II GX Transceiver Architecture Word Aligner section in
Overview chapter in volume 2 of the Stratix II GX the Arria GX Transceiver
port for pattern detector and
Device Handbook for information about this port. Architecture chapter in
word aligner
volume 2 of the
Stratix II GX Device
Handbook.
Create rx_patterndetect
port to indicate pattern detected
Refer to the Stratix II GX Transceiver Architecture Word Aligner section in
Overview chapter in volume 2 of the Stratix II GX the Arria GX Transceiver
Device Handbook for information about this port. Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create rx_ctrldetect port
to indicate 8B/10B decoder has
detected a control code
This option is not available in SDI mode.
Create rx_errdetect port to
indicate 8B/10B decoder has
detected an error code
This option is not available in SDI mode.
3–114
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–40. MegaWizard Plug-In Manager Options (Page 14 for SDI Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Reference
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity code
This option is not available in SDI mode.
Create rx_revbyteorderwa
to enable receiver symbol swap
This option is not available in SDI mode.
Altera Corporation
May 2008
3–115
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–51 shows page 15 of the MegaWizard Plug-In Manager for the
SDI protocol selection. The Generate simulation model option creates a
behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate Netlist option generates a netlist for third party
EDA synthesis tool to be able to estimate timing and resource utilization
for the ALT2GXB instance.
Figure 3–51. MegaWizard Plug-In Manager - ALT2GXB (EDA)
3–116
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Figure 3–52 shows page 16 (the last page) of the MegaWizard Plug-In
Manager for the SDI protocol set up. You can select optional files on this
page. After you make your selections, click Finish to generate the files.
Figure 3–52. MegaWizard Plug-In Manager - ALT2GXB (Summary)
Serial RapidIO
Mode
Altera Corporation
May 2008
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
Serial RapidIO mode. The MegaWizard Plug-In Manager provides a
warning if any of the settings you choose are illegal.
3–117
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–53 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
in Serial RapidIO mode.
Figure 3–53. MegaWizard Plug-In Manager - ALT2GXB (General)
3–118
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–41 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–41. MegaWizard Plug-In Manager Options (Page 3 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Which protocol will you be
using?
Determines the specific protocol or modes under which
the transceiver operates. For Serial RapidIO mode, you
must select the Serial RapidIO.
—
Which subprotocol will you
be using?
Not applicable to Serial RapidIO mode.
—
Enforce default settings for
this protocol
Not applicable to Serial RapidIO mode.
—
What is the operation mode? The available operation modes are receiver only,
transmitter only, and receiver and transmitter.
—
What is the number of
channels?
This option determines how many duplicate channels
this ALT2GXB instance contains.
—
What is the deserializer
block width?
This option is unavailable in Serial RapidIO mode.
—
What is the channel width?
This option determines the PLD-transceiver interface
width. Only 16-bit interface width is supported.
What would you like to base
the setting on?
This option is unavailable in Serial RapidIO mode.
—
What is the data rate?
In Serial RapidIO mode, data rates of 1250 Mbps,
2500 Mbps, and 3125 Mbps are supported.
—
What is the input clock
frequency?
Determines the input reference clock frequency for the
transceiver. The following input reference clock
frequencies are supported for each data rate option:
● 1250 Mbps: 62.5 MHz, 78.125 MHz, 125 MHz,
156.25MHz, 250 MHz, 312.5 MHz
● 2500 Mbps: 50 MHz, 62.5 MHz, 78.125 MHz,
100 MHz, 125 MHz, 156.25MHz, 250 MHz,
312.5 MHz, 500 Mhz.
● 3125 Mbps: 62.5 MHz, 78.125 MHz, 97.6563 MHz,
125 MHz, 156.25MHz, 195.3125 MHz, 312.5 MHz,
390.625 MHz.
What is the data rate division This option is unavailable in Serial RapidIO mode.
factor?
Altera Corporation
May 2008
Byte Serializer and Byte
Deserializer sections in
the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook
Serial RapidIO Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the
Arria GX Device
Handbook
—
3–119
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–54 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–54. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
3–120
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–42 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–42. MegaWizard Plug-In Manager Options (Page 4 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Train Receiver PLL clock from
PLL inclk
If you select this option, the transmitter input
reference clock (pll_inclk) drives the receiver
PLL input reference clock also.
If you do not select this option, the signal on the
rx_cruclk port drives the receiver PLL input
reference clock.
—
What is the GXB Transmitter
PLL bandwidth mode?
This option is not available in Serial RapidIO mode
because the transmitter PLL bandwidth is fixed at
high.
—
What is the Receiver PLL
bandwidth mode?
This option is not available in Serial RapidIO mode
because the receiver PLL bandwidth is fixed at
medium.
—
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect the CRU’s
transition.)
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
Altera Corporation
May 2008
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–121
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–42. MegaWizard Plug-In Manager Options (Page 4 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS logic of Reset Control and Power
the receiver. Altera recommends using this port to Down section in the
Arria GX Transceiver
implement the recommended reset sequence.
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS logic
of the transmitter. Altera recommends using this
port to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
(CRU) section in the Arria
GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
(CRU) section in the Arria
GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_pll_locked port Refer to the Arria GX Transceiver Protocol
to indicate RX PLL is in lock with Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
the reference clock
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–122
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Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–42. MegaWizard Plug-In Manager Options (Page 4 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Create rx_freqlocked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the received data
This option is not available in Serial RapidIO
Create rx_signaldetect
port to indicate data input signal mode.
detection
Clock Recovery Unit
(CRU) section in the Arria
GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–123
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–54 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–55. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
3–124
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–42 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–43. MegaWizard Plug-In Manager Options (Page 5 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
This option is not available in Serial RapidIO
Create rx_signaldetect
port to indicate data input signal mode.
detection
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–125
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–43. MegaWizard Plug-In Manager Options (Page 5 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create active low
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook, for information about
this port.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
cal_blk_powerdown to
power down the calibration
block
3–126
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Figure 3–56 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–56. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
Altera Corporation
May 2008
3–127
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–44 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–44. MegaWizard Plug-In Manager Options (Page 6 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
This enables the DC gain option and the legal
settings are 0, 1, 2, and 3.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage
(RX VCM)?
The receiver common mode voltage is
programmable, and the selections available are 0.85
V and 1.2 V.
Receiver Buffer section
under Serial RapidIO
Mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Force signal detection
This option is not available in Serial RapidIO mode
and is always forced selected.
—
What is the signal detect and This option is not available in Serial RapidIO mode as
signal loss threshold?
signal detection is forced.
—
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip termination
OCT. If checked, this option turns off the receiver
OCT.
—
What is the receiver
termination resistance?
In Serial RapidIO mode, the only supported receiver
termination resistance is 100 Ω.
Receiver Buffer section
under Serial RapidIO
Mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
3–128
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Figure 3–57 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–57. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–129
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–45 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–45. MegaWizard Plug-In Manager Options (Page 7 for Serial RapidIO Mode)
ALT2GXB Setting
What is the Transmitter Buffer
Power (VCCH)?
Description
Reference
This setting is for information only and is used
to calculate the VO D from the buffer power
supply (VC C H ) and the transmitter termination
to derive the proper VO D range. In serial
RapidIO mode, this option is fixed at 1.5 V
Transmitter Buffer section
under Serial RapidIO Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the Transmitter Common In Serial RapidIO mode, the transmitter
Mode Voltage (VCM)?
common mode voltage is selectable between
0.6 V and 0.7 V.
Transmitter Buffer section
under Serial RapidIO mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
—
Use external Transmitter
termination
This option is available if you want to use an
external termination resistor instead of the
on-chip termination OCT. Checking this option
turns off the transmitter OCT.
Select the Transmitter
termination resistance
In Serial RapidIO mode, the only supported
receiver termination resistance is 100 Ω.
Transmitter Buffer section
under Serial RapidIO mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV
in steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
under Serial RapidIO Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
3–130
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–45. MegaWizard Plug-In Manager Options (Page 7 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on Transmitter Buffer section
under Serial RapidIO Mode
the transmitter buffer using first post-tap. The
in the Arria GX Transceiver
options available are 0, 1, 2, 3, 4, and 5.
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
Altera Corporation
May 2008
—
3–131
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–58 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–58. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
3–132
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–46 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–46. MegaWizard Plug-In Manager Options (Page 8 for Serial RapidIO Mode)
ALT2GXB Setting
Which loopback option would
you like?
Description
Reference
No loopback and serial loopback options are
available in Serial RapidIO mode.
● No loopback is the default mode.
● If you select serial loopback, the
rx_seriallpbken port is available to
control the serial loopback feature
dynamically. A 1'b1 enables serial loopback
and a 1'b0 disables loopback on a
channel-by-channel basis.
Loopback Modes section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Figure 3–59 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Altera Corporation
May 2008
3–133
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–59. MegaWizard Plug-In Manager - ALT2GXB (SR I/O 1)
Table 3–47 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–47. MegaWizard Plug-In Manager Options (Page 9 for Serial RapidIO Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Enable byte ordering block
This option is not available in Arria GX devices.
—
Enable 8B/10B
decoder/encoder
This option is unavailable in Serial RapidIO mode and
is always forced selected to enable 8B/10B
decoder/encoder.
—
3–134
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–47. MegaWizard Plug-In Manager Options (Page 9 for Serial RapidIO Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create tx_forcedisp to This option is unavailable in Serial RapidIO mode.
enable Force disparity and
use tx_dispval to code
up the incoming word using
positive or negative
disparity
—
Enable rate match FIFO
This option is unavailable in Serial RapidIO mode as
the rate matcher is not supported.
—
Flip Receiver output data
bits
This option reverses the bit order of the data at the
receiver-PLD interface at a byte level.
—
Flip Transmitter input data
bits
This option reverses the bit order of the data bits at the
input of the transmitter at a byte level.
—
Enable Transmitter bit
reversal
This option is unavailable in Serial RapidIO mode.
—
Word Aligner section in
Create rx_invpolarity This optional port allows you to dynamically reverse
the polarity of the received data at the input of the word the Arria GX Transceiver
to enable word aligner
Architecture chapter in
aligner.
polarity inversion
volume 2 of the Arria GX
Device Handbook
Create tx_invpolarity This optional port allows you to dynamically reverse
to allow Transmitter polarity the polarity of the data to be transmitted at the
transmitter PCS-PMA interface.
inversion
Altera Corporation
May 2008
8B/10B Encoder section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
3–135
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–60 shows page 10 of the MegaWizard Plug-In Manager for Serial
RapidIO protocol set up.
Figure 3–60. MegaWizard Plug-In Manager - ALT2GXB (SR I/O 2)
Table 3–48 describes the available options on page 10 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 1 of 4)
ALT2GXB Setting
Description
Reference
This option is unavailable in Serial RapidIO mode.
—
Use manual bit slipping mode. This option is unavailable in Serial RapidIO mode.
—
Use manual word alignment
mode
3–136
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 2 of 4)
ALT2GXB Setting
Description
Reference
Use the built-in
'synchronization state
machine'
This option is forced selected in Serial RapidIO
mode.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Number of bad data words
before loss of synch state
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Number of consecutive valid
words before synch state is
reached
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Number of valid patterns
Refer to the Arria GX Transceiver Protocol Support
before synch state is reached and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the word alignment
pattern length?
The word alignment pattern length is fixed to 10 in
Serial RapidIO mode.
Word Aligner section under
Serial RapidIO mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the word alignment
pattern?
Enter the 10-bit word alignment pattern here.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Altera Corporation
May 2008
3–137
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 3 of 4)
ALT2GXB Setting
Description
Reference
Flip word alignment pattern
bits
This option reverses the bit order of the alignment
pattern at a byte level to support MSB-to-LSB
transmission protocols. The default transmission
order is LSB-to-MSB.
—
Enable run-length violation
checking with a run length of
This option activates the run-length violation
circuit. You can program the run length at which
the circuit triggers the rx_rlv signal.
Enable word aligner output
reverse bit ordering
This option is unavailable in Serial RapidIO mode.
—
Create rx_syncstatus
output port for pattern
detector and word aligner
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create
Refer to the Arria GX Transceiver Protocol Support Word Aligner section under
Word Aligner section n the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
rx_patterndetect output and Additional Features chapter in volume 2 of the Serial RapidIO Mode in the
port to indicate pattern
detected
Arria GX Device Handbook for information about
this port.
Refer to the Arria GX Transceiver Architecture
Create rx_ctrldetect
output port to indicate 8B/10B chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
decoder has detected a
control code
Create rx_errdetect port
to indicate 8B/10B decoder
has detected an error code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
3–138
Arria GX Device Handbook, Volume 2
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
8B/10B Decoder section n
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 4 of 4)
ALT2GXB Setting
Description
Reference
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Create
This option is unavailable in Serial RapidIO mode.
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
—
rx_revbyteorderwa to
enable receiver symbol swap
Figure 3–61 shows page 11 of the MegaWizard Plug-In Manager for the
Serial RapidIO protocol selection. The Generate simulation model
option creates a behavioral model (.vo or .vho) of the transceiver instance
for third-party simulators. The Generate a netlist for synthesis area and
timing estimation option creates a netlist file (.syn) for third-party
synthesis tools.
Altera Corporation
May 2008
3–139
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–61. MegaWizard Plug-In Manager - ALT2GXB (EDA)
3–140
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Referenced Documents
Figure 3–62 shows page 12 (last page) of the MegaWizard Plug-In
Manager for Serial RapidIO protocol set up. You can select optional files
on this page. After you make your selections, click Finish to generate the
files.
Figure 3–62. MegaWizard Plug-In Manager - ALT2GXB (Summary)
Referenced
Documents
This chapter references the following documents:
■
■
■
Altera Corporation
May 2008
Arria GX Architecture chapter in volume 1 of the Arria GX Device
Handbook
Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook
Arria GX Transceiver Protocol Support and Additional Features chapter
in volume 2 of the Arria GX Device Handbook
3–141
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
■
Document
Revision History
Stratix II GX Transceiver Architecture Overview chapter in volume 2 of
the Stratix II GX Device Handbook
Table 3–49 shows the revision history for this chapter.
Table 3–49. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
August 2007,
v1.2
Added the “Referenced Documents” section.
—
Minor text edits.
—
June 2007,
v1.1
Added GIGE information.
—
May 2007, v1.0 Initial Release.
3–142
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
4. Specifications and
Additional Information
AGX52004-1.0
8B/10B Code
This section provides information about the data and control codes for
Arria™ GX devices.
Code Notation
The 8B/10B data and control codes are referred to as Dx.y and Kx.y,
respectively. The 8-bit byte – H G F E D C B A, where H is the most
significant bit (MSB) and A is the significant bit (LSB) – is broken up into
two groups, x and y, where x is the five lower bits (E D C B A) and y is the
three upper bits (H G F). Figure 4–1 shows the designation for 3C hex.
Figure 4–1. Sample Notation for 3C hex
y=1
D28.1 =
(3C hex)
x = 28
0
0
1
1
1
1
0
0
H
G
F
E
D
C
B
A
There are 256 Dx.y and 12 Kx.y valid 8-bit codes. These codes have two
10-bit equivalent codes associated with each 8-bit code. The 10-bit codes
have either a neutral disparity or a non-neutral disparity. With neutral
disparity, two neutral disparity 10-bit codes are associated with an 8-bit
code. With non-neutral disparity 10-bit code, a positive and a negative
disparity code are associated with the 8-bit code.
The positive disparity 10-bit code is associated in the RD– column. The
negative disparity 10-bit code is associated in the RD+ column.
Disparity Calculation
Running disparity is calculated based on the sub-blocks of the 10-bit code.
The 10-bit code is divided into two sub-blocks, a 6-bit sub-block (abcdei)
and a 4-bit sub-block (fghj), as shown in Figure 4–2.
Altera Corporation
May 2007
4–1
8B/10B Code
Figure 4–2. 10-Bit Grouping of 6-bit & 4-Bit Sub-Blocks
10-Bit Code
D28.1 =
(3C hex)
j
h
g
f
i
e
d
c
b
a
0
0
1
1
1
1
1
0
0
0
4-Bit Block
6-Bit Block
The running disparity at the beginning of the 6-bit sub-block is the
running disparity at the end of the previous 10-bit code. The running
disparity of the 4-bit sub-block is the running disparity at the end of the
6-bit sub-block. The running disparity at the end of the 4-bit sub-block is
the running disparity of the 10-bit code (refer to Figure 4–3).
Figure 4–3. Running Disparity Between Sub-Blocks
10-Bit Code
D28.1 =
(3C hex)
j
h
g
f
i
e
d
c
b
a
0
0
1
1
1
1
1
0
0
0
4-Bit Block
6-Bit Block
The running disparity calculation rules are as follows:
■
The current running disparity at the end of a sub-block is positive if
any of the following is true:
●
The sub-block contains more ones than zeros
●
The 6-bit sub-block is 6'b000111
●
The 4-bit sub-block is 4'b0011
■
The current running disparity at the end of a sub-block is negative if
any of the following is true:
●
The sub-block contains more zeros than ones
●
The 6-bit sub-block is 6'b111000
●
The 4-bit sub-block is 4'b1100
If those conditions are not met, the running disparity at the end of the
sub-block is the same as at the beginning of the sub-block.
4–2
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Supported Codes
The 8B/10B scheme defines the 12 control codes listed in Table 4–1 for
synchronization, alignment, and general application purposes.
Table 4–1. Supported K Codes
8-Bit Code
K Code
10-Bit Code RD–
10-Bit Code RD+
Octal Value
HGF_EDCBA
abcdei_fghj
K28.0
1C
8'b000_11100
10'b001111_0100
10'b110000_1011
K28.1
3C
8'b001_11100
10'b001111_1001
10'b110000_0110
K28.2
5C
8'b010_11100
10'b001111_0101
10'b110000_1010
K28.3
7C
8'b011_11100
10'b001111_0011
10'b110000_1100
K28.4
9C
8'b100_11100
10'b001111_0010
10'b110000_1101
K28.5 (1)
BC
8'b101_11100
10'b001111_1010
10'b110000_0101
K28.6
DC
8'b110_11100
10'b001111_0110
10'b110000_1001
K28.7
FC
8'b111_11100
10'b001111_1000
10'b110000_0111
K23.7
F7
8'b111_10111
10'b111010_1000
10'b000101_0111
K27.7
FB
8'b111_11011
10'b110110_1000
10'b001001_0111
K29.7
FD
8'b111_11101
10'b101110_1000
10'b010001_0111
K30.7
FE
8'b111_11110
10'b011110_1000
10'b100001_0111
Note to Table 4–1:
(1)
K28.5 is a comma code used for word alignment and indicates an IDLE state.
Table 4–2 shows the valid data code-groups.
Table 4–2. Valid Data Code-Groups (Part 1 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D0.0
00
000 00000
100111 0100
011000 1011
D1.0
01
000 00001
011101 0100
100010 1011
D2.0
02
000 00010
101101 0100
010010 1011
D3.0
03
000 00011
110001 1011
110001 0100
D4.0
04
000 00100
110101 0100
001010 1011
D5.0
05
000 00101
101001 1011
101001 0100
D6.0
06
000 00110
011001 1011
011001 0100
D7.0
07
000 00111
111000 1011
000111 0100
Altera Corporation
May 2007
4–3
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 2 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D8.0
08
000 01000
111001 0100
000110 1011
D9.0
09
000 01001
100101 1011
100101 0100
D10.0
0A
000 01010
010101 1011
010101 0100
D11.0
0B
000 01011
110100 1011
110100 0100
D12.0
0C
000 01100
001101 1011
001101 0100
D13.0
0D
000 01101
101100 1011
101100 0100
D14.0
0E
000 01110
011100 1011
011100 0100
D15.0
0F
000 01111
010111 0100
101000 1011
D16.0
10
000 10000
011011 0100
100100 1011
D17.0
11
000 10001
100011 1011
100011 0100
D18.0
12
000 10010
010011 1011
010011 0100
D19.0
13
000 10011
110010 1011
110010 0100
D20.0
14
000 10100
001011 1011
001011 0100
D21.0
15
000 10101
101010 1011
101010 0100
D22.0
16
000 10110
011010 1011
011010 0100
D23.0
17
000 10111
111010 0100
000101 1011
D24.0
18
000 11000
110011 0100
001100 1011
D25.0
19
000 11001
100110 1011
100110 0100
D26.0
1A
000 11010
010110 1011
010110 0100
D27.0
1B
000 11011
110110 0100
001001 1011
D28.0
1C
000 11100
001110 1011
001110 0100
D29.0
1D
000 11101
101110 0100
010001 1011
D30.0
1E
000 11110
011110 0100
100001 1011
D31.0
1F
000 11111
101011 0100
010100 1011
D0.1
20
001 00000
100111 1001
011000 1001
D1.1
21
001 00001
011101 1001
100010 1001
D2.1
22
001 00010
101101 1001
010010 1001
D3.1
23
001 00011
110001 1001
110001 1001
D4.1
24
001 00100
110101 1001
001010 1001
D5.1
25
001 00101
101001 1001
101001 1001
D6.1
26
001 00110
011001 1001
011001 1001
D7.1
27
001 00111
111000 1001
000111 1001
D8.1
28
001 01000
111001 1001
000110 1001
4–4
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 3 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D9.1
29
001 01001
100101 1001
100101 1001
D10.1
2A
001 01010
010101 1001
010101 1001
D11.1
2B
001 01011
110100 1001
110100 1001
D12.1
2C
001 01100
001101 1001
001101 1001
D13.1
2D
001 01101
101100 1001
101100 1001
D14.1
2E
001 01110
011100 1001
011100 1001
D15.1
2F
001 01111
010111 1001
101000 1001
D16.1
30
001 10000
011011 1001
100100 1001
D17.1
31
001 10001
100011 1001
100011 1001
D18.1
32
001 10010
010011 1001
010011 1001
D19.1
33
001 10011
110010 1001
110010 1001
D20.1
34
001 10100
001011 1001
001011 1001
D21.1
35
001 10101
101010 1001
101010 1001
D22.1
36
001 10110
011010 1001
011010 1001
D23.1
37
001 10111
111010 1001
000101 1001
D24.1
38
001 11000
110011 1001
001100 1001
D25.1
39
001 11001
100110 1001
100110 1001
D26.1
3A
001 11010
010110 1001
010110 1001
D27.1
3B
001 11011
110110 1001
001001 1001
D28.1
3C
001 11100
001110 1001
001110 1001
D29.1
3D
001 11101
101110 1001
010001 1001
D30.1
3E
001 11110
011110 1001
100001 1001
D31.1
3F
001 11111
101011 1001
010100 1001
D0.2
40
010 00000
100111 0101
011000 0101
D1.2
41
010 00001
011101 0101
100010 0101
D2.2
42
010 00010
101101 0101
010010 0101
D3.2
43
010 00011
110001 0101
110001 0101
D4.2
44
010 00100
110101 0101
001010 0101
D5.2
45
010 00101
101001 0101
101001 0101
D6.2
46
010 00110
011001 0101
011001 0101
D7.2
47
010 00111
111000 0101
000111 0101
D8.2
48
010 01000
111001 0101
000110 0101
D9.2
49
010 01001
100101 0101
100101 0101
Altera Corporation
May 2007
4–5
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 4 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D10.2
4A
010 01010
010101 0101
010101 0101
D11.2
4B
010 01011
110100 0101
110100 0101
D12.2
4C
010 01100
001101 0101
001101 0101
D13.2
4D
010 01101
101100 0101
101100 0101
D14.2
4E
010 01110
011100 0101
011100 0101
D15.2
4F
010 01111
010111 0101
101000 0101
D16.2
50
010 10000
011011 0101
100100 0101
D17.2
51
010 10001
100011 0101
100011 0101
D18.2
52
010 10010
010011 0101
010011 0101
D19.2
53
010 10011
110010 0101
110010 0101
D20.2
54
010 10100
001011 0101
001011 0101
D21.2
55
010 10101
101010 0101
101010 0101
D22.2
56
010 10110
011010 0101
011010 0101
D23.2
57
010 10111
111010 0101
000101 0101
D24.2
58
010 11000
110011 0101
001100 0101
D25.2
59
010 11001
100110 0101
100110 0101
D26.2
5A
010 11010
010110 0101
010110 0101
D27.2
5B
010 11011
110110 0101
001001 0101
D28.2
5C
010 11100
001110 0101
001110 0101
D29.2
5D
010 11101
101110 0101
010001 0101
D30.2
5E
010 11110
011110 0101
100001 0101
D31.2
5F
010 11111
101011 0101
010100 0101
D0.3
60
011 00000
100111 0011
011000 1100
D1.3
61
011 00001
011101 0011
100010 1100
D2.3
62
011 00010
101101 0011
010010 1100
D3.3
63
011 00011
110001 1100
110001 0011
D4.3
64
011 00100
110101 0011
001010 1100
D5.3
65
011 00101
101001 1100
101001 0011
D6.3
66
011 00110
011001 1100
011001 0011
D7.3
67
011 00111
111000 1100
000111 0011
D8.3
68
011 01000
111001 0011
000110 1100
D9.3
69
011 01001
100101 1100
100101 0011
D10.3
6A
011 01010
010101 1100
010101 0011
4–6
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 5 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D11.3
6B
011 01011
110100 1100
110100 0011
D12.3
6C
011 01100
001101 1100
001101 0011
D13.3
6D
011 01101
101100 1100
101100 0011
D14.3
6E
011 01110
011100 1100
011100 0011
D15.3
6F
011 01111
010111 0011
101000 1100
D16.3
70
011 10000
011011 0011
100100 1100
D17.3
71
011 10001
100011 1100
100011 0011
D18.3
72
011 10010
010011 1100
010011 0011
D19.3
73
011 10011
110010 1100
110010 0011
D20.3
74
011 10100
001011 1100
001011 0011
D21.3
75
011 10101
101010 1100
101010 0011
D22.3
76
011 10110
011010 1100
011010 0011
D23.3
77
011 10111
111010 0011
000101 1100
D24.3
78
011 11000
110011 0011
001100 1100
D25.3
79
011 11001
100110 1100
100110 0011
D26.3
7A
011 11010
010110 1100
010110 0011
D27.3
7B
011 11011
110110 0011
001001 1100
D28.3
7C
011 11100
001110 1100
001110 0011
D29.3
7D
011 11101
101110 0011
010001 1100
D30.3
7E
011 11110
011110 0011
100001 1100
D31.3
7F
011 11111
101011 0011
010100 1100
D0.4
80
100 00000
100111 0010
011000 1101
D1.4
81
100 00001
011101 0010
100010 1101
D2.4
82
100 00010
101101 0010
010010 1101
D3.4
83
100 00011
110001 1101
110001 0010
D4.4
84
100 00100
110101 0010
001010 1101
D5.4
85
100 00101
101001 1101
101001 0010
D6.4
86
100 00110
011001 1101
011001 0010
D7.4
87
100 00111
111000 1101
000111 0010
D8.4
88
100 01000
111001 0010
000110 1101
D9.4
89
100 01001
100101 1101
100101 0010
D10.4
8A
100 01010
010101 1101
010101 0010
D11.4
8B
100 01011
110100 1101
110100 0010
Altera Corporation
May 2007
4–7
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 6 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D12.4
8C
100 01100
001101 1101
001101 0010
D13.4
8D
100 01101
101100 1101
101100 0010
D14.4
8E
100 01110
011100 1101
011100 0010
D15.4
8F
100 01111
010111 0010
101000 1101
D16.4
90
100 10000
011011 0010
100100 1101
D17.4
91
100 10001
100011 1101
100011 0010
D18.4
92
100 10010
010011 1101
010011 0010
D19.4
93
100 10011
110010 1101
110010 0010
D20.4
94
100 10100
001011 1101
001011 0010
D21.4
95
100 10101
101010 1101
101010 0010
D22.4
96
100 10110
011010 1101
011010 0010
D23.4
97
100 10111
111010 0010
000101 1101
D24.4
98
100 11000
110011 0010
001100 1101
D25.4
99
100 11001
100110 1101
100110 0010
D26.4
9A
100 11010
010110 1101
010110 0010
D27.4
9B
100 11011
110110 0010
001001 1101
D28.4
9C
100 11100
001110 1101
001110 0010
D29.4
9D
100 11101
101110 0010
010001 1101
D30.4
9E
100 11110
011110 0010
100001 1101
D31.4
9F
100 11111
101011 0010
010100 1101
D0.5
A0
101 00000
100111 1010
011000 1010
D1.5
A1
101 00001
011101 1010
100010 1010
D2.5
A2
101 00010
101101 1010
010010 1010
D3.5
A3
101 00011
110001 1010
110001 1010
D4.5
A4
101 00100
110101 1010
001010 1010
D5.5
A5
101 00101
101001 1010
101001 1010
D6.5
A6
101 00110
011001 1010
011001 1010
D7.5
A7
101 00111
111000 1010
000111 1010
D8.5
A8
101 01000
111001 1010
000110 1010
D9.5
A9
101 01001
100101 1010
100101 1010
D10.5
AA
101 01010
010101 1010
010101 1010
D11.5
AB
101 01011
110100 1010
110100 1010
D12.5
AC
101 01100
001101 1010
001101 1010
4–8
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 7 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D13.5
AD
101 01101
101100 1010
101100 1010
D14.5
AE
101 01110
011100 1010
011100 1010
D15.5
AF
101 01111
010111 1010
101000 1010
D16.5
B0
101 10000
011011 1010
100100 1010
D17.5
B1
101 10001
100011 1010
100011 1010
D18.5
B2
101 10010
010011 1010
010011 1010
D19.5
B3
101 10011
110010 1010
110010 1010
D20.5
B4
101 10100
001011 1010
001011 1010
D21.5
B5
101 10101
101010 1010
101010 1010
D22.5
B6
101 10110
011010 1010
011010 1010
D23.5
B7
101 10111
111010 1010
000101 1010
D24.5
B8
101 11000
110011 1010
001100 1010
D25.5
B9
101 11001
100110 1010
100110 1010
D26.5
BA
101 11010
010110 1010
010110 1010
D27.5
BB
101 11011
110110 1010
001001 1010
D28.5
BC
101 11100
001110 1010
001110 1010
D29.5
BD
101 11101
101110 1010
010001 1010
D30.5
BE
101 11110
011110 1010
100001 1010
D31.5
BF
101 11111
101011 1010
010100 1010
D0.6
C0
110 00000
100111 0110
011000 0110
D1.6
C1
110 00001
011101 0110
100010 0110
D2.6
C2
110 00010
101101 0110
010010 0110
D3.6
C3
110 00011
110001 0110
110001 0110
D4.6
C4
110 00100
110101 0110
001010 0110
D5.6
C5
110 00101
101001 0110
101001 0110
D6.6
C6
110 00110
011001 0110
011001 0110
D7.6
C7
110 00111
111000 0110
000111 0110
D8.6
C8
110 01000
111001 0110
000110 0110
D9.6
C9
110 01001
100101 0110
100101 0110
D10.6
CA
110 01010
010101 0110
010101 0110
D11.6
CB
110 01011
110100 0110
110100 0110
D12.6
CC
110 01100
001101 0110
001101 0110
D13.6
CD
110 01101
101100 0110
101100 0110
Altera Corporation
May 2007
4–9
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 8 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D14.6
CE
110 01110
011100 0110
011100 0110
D15.6
CF
110 01111
010111 0110
101000 0110
D16.6
D0
110 10000
011011 0110
100100 0110
D17.6
D1
110 10001
100011 0110
100011 0110
D18.6
D2
110 10010
010011 0110
010011 0110
D19.6
D3
110 10011
110010 0110
110010 0110
D20.6
D4
110 10100
001011 0110
001011 0110
D21.6
D5
110 10101
101010 0110
101010 0110
D22.6
D6
110 10110
011010 0110
011010 0110
D23.6
D7
110 10111
111010 0110
000101 0110
D24.6
D8
110 11000
110011 0110
001100 0110
D25.6
D9
110 11001
100110 0110
100110 0110
D26.6
DA
110 11010
010110 0110
010110 0110
D27.6
DB
110 11011
110110 0110
001001 0110
D28.6
DC
110 11100
001110 0110
001110 0110
D29.6
DD
110 11101
101110 0110
010001 0110
D30.6
DE
110 11110
011110 0110
100001 0110
D31.6
DF
110 11111
101011 0110
010100 0110
D0.7
E0
111 00000
100111 0001
011000 1110
D1.7
E1
111 00001
011101 0001
100010 1110
D2.7
E2
111 00010
101101 0001
010010 1110
D3.7
E3
111 00011
110001 1110
110001 0001
D4.7
E4
111 00100
110101 0001
001010 1110
D5.7
E5
111 00101
101001 1110
101001 0001
D6.7
E6
111 00110
011001 1110
011001 0001
D7.7
E7
111 00111
111000 1110
000111 0001
D8.7
E8
111 01000
111001 0001
000110 1110
D9.7
E9
111 01001
100101 1110
100101 0001
D10.7
EA
111 01010
010101 1110
010101 0001
D11.7
EB
111 01011
110100 1110
110100 1000
D12.7
EC
111 01100
001101 1110
001101 0001
D13.7
ED
111 01101
101100 1110
101100 1000
D14.7
EE
111 01110
011100 1110
011100 1000
4–10
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 9 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D15.7
EF
111 01111
010111 0001
101000 1110
D16.7
F0
111 10000
011011 0001
100100 1110
D17.7
F1
111 10001
100011 0111
100011 0001
D18.7
F2
111 10010
010011 0111
010011 0001
D19.7
F3
111 10011
110010 1110
110010 0001
D20.7
F4
111 10100
001011 0111
001011 0001
D21.7
F5
111 10101
101010 1110
101010 0001
D22.7
F6
111 10110
011010 1110
011010 0001
D23.7
F7
111 10111
111010 0001
000101 1110
D24.7
F8
111 11000
110011 0001
001100 1110
D25.7
F9
111 11001
100110 1110
100110 0001
D26.7
FA
111 11010
010110 1110
010110 0001
D27.7
FB
111 11011
110110 0001
001001 1110
D28.7
FC
111 11100
001110 1110
001110 0001
D29.7
FD
111 11101
101110 0001
010001 1110
D30.7
FE
111 11110
011110 0001
100001 1110
D31.7
FF
111 11111
101011 0001
010100 1110
Document
Revision History
Table 4–3 shows the revision history for this document.
Table 4–3. Document Revision History
Date and Document Version
May 2007 v1.0
Altera Corporation
May 2007
Changes Made
Initial Release
Summary of Changes
N/A
4–11
Arria GX Device Handbook, Volume 2
Document Revision History
4–12
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Section II. Clock
Management
This section provides information on clock management in Arria™ GX
devices. It describes the enhanced and fast phase-locked loops (PLLs) that
support clock management and synthesis for on-chip clock management,
external system clock management, and high-speed I/O interfaces.
This section includes the following chapter:
■
Revision History
Altera Corporation
Chapter 5, PLLs in Arria GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section II–1
Preliminary
Clock Management
Section II–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
5. PLLs in Arria GX Devices
AGX52005-1.2
Introduction
ArriaTM GX device phase-locked loops (PLLs) provide robust clock
management and synthesis for device clock management, external
system clock management, and high-speed I/O interfaces. These PLLs
are highly versatile and can be used as a zero delay buffer, a jitter
attenuator, low skew fan out buffer, or a frequency synthesizer.
Arria GX devices feature up to four enhanced PLLs and up to four fast
PLLs. Both enhanced and fast PLLs are feature rich, supporting advanced
capabilities such as clock switchover, reconfigurable phase shift, PLL
reconfiguration, and reconfigurable bandwidth. You can use PLLs for
general-purpose clock management, supporting multiplication, phase
shifting, and programmable duty cycle. In addition, enhanced PLLs
support external clock feedback mode, spread-spectrum clocking, and
counter cascading. Fast PLLs offer high-speed outputs to manage
high-speed differential I/O interfaces.
Arria GX devices also support power-down mode where clock networks
that are not being used can easily be turned off, reducing overall power
consumption of the device. In addition, Arria GX PLLs support dynamic
selection of the PLL input clock from up to five possible sources, giving
you the flexibility to choose from multiple (up to four) clock sources to
feed the primary and secondary clock input ports.
The Altera® Quartus® II software enables the PLLs and their features
without requiring any external devices.
This chapter contains the following sections:
■
■
■
■
■
■
■
■
■
■
■
■
■
Altera Corporation
May 2008
“Enhanced PLLs” on page 5–5
“Fast PLLs” on page 5–14
“Clock Feedback Modes” on page 5–18
“Hardware Features” on page 5–23
“Advanced Features” on page 5–30
“Reconfigurable Bandwidth” on page 5–42
“PLL Reconfiguration” on page 5–49
“Spread-Spectrum Clocking” on page 5–49
“Board Layout” on page 5–54
“PLL Specifications” on page 5–59
“Clocking” on page 5–59
“Clock Control Block” on page 5–77
“Conclusion” on page 5–81
5–1
PLLs in Arria GX Devices
Table 5–1 shows the PLLs available for each Arria GX device.
Table 5–1. Arria GX Device PLL Availability Note (1)
Device
Fast PLLs
Enhanced PLLs
1
2
7
8
5
6
11
12
EP1AGX20 (2)
v
v
—
—
v
v
—
—
EP1AGX35 (2)
v
v
—
—
v
v
—
—
EP1AGX50 (2)
v
v
v
v
v
v
v
v
EP1AGX60 (3)
v
v
v
v
v
v
v
v
EP1AGX90
v
v
v
v
v
v
v
v
Notes for Table 5–1:
(1)
(2)
(3)
The global or regional clocks in a fast PLL’s transceiver block can drive the fast
PLL input. A pin or other PLL must drive the global or regional source. The
source cannot be driven by internally generated logic before driving the fast PLL.
EP1AGX20, EP1AGX35, EP1AGX50 and EP1AGX60 devices only have two fast
PLLs (PLLs 1 and 2).
EP1AGX60 devices in F484 and F780 devices have two fast PLLs (PLL 1 and 2)
and two enhanced PLLs. Arria GX devices in the F1152 package support all eight
PLLs.
Table 5–2 shows the enhanced PLL and fast PLL features in Arria GX
devices.
Table 5–2. Arria GX PLL Features (Part 1 of 2)
Feature
Clock multiplication and division
Enhanced PLL
Fast PLL
m/(n post-scale counter) (1)
m/(n post-scale counter) (2)
Down to 125-ps increments (3)
Down to 125-ps increments (3)
Clock switchover
v
v(4)
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread-spectrum clocking
v
—
Programmable duty cycle
v
v
Phase shift
Number of clock outputs per PLL (5)
Number of dedicated external clock outputs
per PLL
5–2
Arria GX Device Handbook, Volume 1
6
4
Three differential or six
single-ended
(6)
Altera Corporation
May 2008
Introduction
Table 5–2. Arria GX PLL Features (Part 2 of 2)
Feature
Number of feedback clock inputs per PLL
Enhanced PLL
Fast PLL
1 (7)
—
Notes to Table 5–2:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For enhanced PLLs, m and n range from 1 to 512 with a 50% duty cycle. Post-scale counters range from 1 to 512
with a 50% duty cycle. For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256.
Fast PLLs can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle clock
outputs, post-scale counters range from 1 to 16.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The
supported phase-shift range is from 125 to 250 ps. Arria GX devices can shift all output frequencies in increments
of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. For
non-50% duty cycle clock outputs post-scale counters range from 1 to 256.
Arria GX fast PLLs only support manual clock switchover.
Clock outputs can be driven to internal clock networks or to a pin.
PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For high-speed
differential I/O pins, the device uses a data channel to generate the transmitter output clock (txclkout).
If the design uses external feedback input pins, you will lose one (or two, if fbin is differential) dedicated output
clock pins.
Altera Corporation
May 2008
5–3
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–1 shows a top-level diagram of the Arria GX device and PLL
locations. See “Clock Control Block” on page 5–77 for more information
about PLL connections to global and regional clocks networks.
Figure 5–1. Arria GX PLL Locations
CLK[15..12]
FPLL7CLK
7
CLK[3..0]
1
2
FPLL8CLK
8
11
5
12
6
CLK[7..4]
Notes to Figure 5–1:
(1)
(2)
(3)
(4)
(5)
EP1AGX20 and EP1AGX35 devices have two enhanced and two fast PLLs.
EP1AGX50 devices in the F484 package have two enhanced PLLs (5 and 6), two fast PLLs (1 and 2), two enhanced
and two fast PLLs (1 and 2) in the F780 package, and four enhanced, four fast PLLs in the F1152 package.
EP1AGX60 devices in the F484 and F780 packages have two enhanced and two fast PLLs, and four enhanced and
four fast PLLs in the F1152 package.
EP1AGX60 devices have four enhanced and four fast PLLs in the F1152 package.
The corner fast PLLs (7 and 8) are enabled only in the F1152 package offering.
5–4
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Enhanced PLLs
Enhanced PLLs
Arria GX devices contain up to four enhanced PLLs with advanced clock
management features. The main goal of a PLL is to synchronize the phase
and frequency of an internal and external clock to an input reference
clock. There are a number of components that comprise a PLL to achieve
this phase alignment.
Enhanced PLL Hardware Overview
Arria GX PLLs align the rising edge of the reference input clock to a
feedback clock using the phase-frequency detector (PFD). The falling
edges are determined by duty-cycle specifications. The PFD produces an
up or down signal that determines whether the VCO needs to operate at
a higher or lower frequency.
PFD output is applied to the charge pump and loop filter, which produces
a control voltage for setting the VCO frequency. If the PFD produces an
up signal, the VCO frequency increases; a down signal decreases the VCO
frequency. The PFD outputs these up and down signals to a charge pump.
If the charge pump receives an up signal, current is driven into the loop
filter. Conversely, if the charge pump receives a down signal, current is
drawn from the loop filter.
The loop filter converts these up and down signals to a voltage that is
used to bias the VCO. The loop filter also removes glitches from the
charge pump and prevents voltage over-shoot, which filters the jitter on
the VCO.
The voltage from the loop filter determines how fast the VCO operates.
The VCO is implemented as a four-stage differential ring oscillator. A
divide counter (m) is inserted in the feedback loop to increase the VCO
frequency above the input reference frequency. VCO frequency (fVCO) is
equal to (m) times the input reference clock (fREF). The input reference
clock (fREF) to the PFD is equal to the input clock (fIN) divided by the
pre-scale counter (n). Therefore, the feedback clock (fFB) applied to one
input of the PFD is locked to the fREF that is applied to the other input of
the PFD.
The VCO output can feed up to six post-scale counters (C0, C1, C2, C3, C4,
and C5). These post-scale counters allow a number of harmonically
related frequencies to be produced within the PLL.
Altera Corporation
May 2008
5–5
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–2 shows a simplified block diagram of the major components of
the Arria GX enhanced PLL. Figure 5–3 shows the enhanced PLL’s
outputs and dedicated clock outputs.
Figure 5–2. Arria GX Enhanced PLL Note (3), (4)
From Adjacent PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
Clock
Switchover
Circuitry
Post-Scale
Counters
Spread
Spectrum
Phase Frequency
Detector
÷C0
inclk[3..0]
÷C1
4
÷n
PFD
Charge
Pump
Loop
Filter
Global or
Regional
Clock
8
VCO
4
Global
Clocks
8
Regional
Clocks
÷C2
6
÷C3
6
(1)
÷m
I/O Buffers (2)
÷C4
÷C5
fbin
Shaded Portions of the
PLL are Reconfigurable
Lock Detect
& Filter
to I/O or general
routing
VCO Phase Selection
Affecting All Outputs
Notes to Figure 5–2:
(1)
(2)
(3)
(4)
Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
PLLs 5, 6, 11, and 12 each have six single-ended dedicated clock outputs or three differential dedicated clock
outputs.
If the design uses external feedback input pins, you will lose one (or two, if fbin is differential) dedicated output
clock pin. Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external
feedback input per PLL.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
5–6
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Enhanced PLLs
External Clock Outputs
Enhanced PLLs 5, 6, 11, and 12 each support up to six single-ended clock
outputs (or three differential pairs), as shown in Figure 5–3.
Figure 5–3. External Clock Outputs for Enhanced PLLs 5, 6, 11, and 12
C0
C1
Enhanced
PLL
C2
C3
C4
C5
extclken0
(3)
extclken2
(3)
extclken3
(3)
extclken1
(3)
PLL#_OUT0p
(1)
PLL#_OUT0n
(1)
extclken4
(3)
extclken5
(3)
PLL#_OUT1p
(1)
PLL#_OUT2p
(1), (2)
PLL#_OUT1n
(1)
PLL#_OUT2n
(1), (2)
Notes to Figure 5–3:
(1)
(2)
(3)
These clock output pins can be fed by any one of the C[5..0] counters.
These clock output pins are used as either external clock outputs or for external feedback. If the design uses external
feedback input pins, you will lose one (or two, if fbin is differential) dedicated output clock pin.
These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Any of the six output counters C[5..0] can feed the dedicated external
clock outputs, as shown in Figure 5–5. Therefore, one counter or
frequency can drive all output pins available from a given PLL. The
dedicated output clock pins (PLL#_OUT) from each enhanced PLL are
powered by a separate power pin (for example, VCC_PLL5_OUT,
VCC_PLL6_OUT, etc.), reducing the overall output jitter by providing
improved isolation from switching I/O pins.
Altera Corporation
May 2008
5–7
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–4. External Clock Output Connectivity to PLL Output Counters for Enhanced PLLs 5, 6, 11, and 12
Note (1)
C0
C1
6
6
To I/O pins (1)
C3
C4
From internal logic
or IOE
C5
6
Multiplexer Selection
Set in Configuration File
C6
Note to Figure 5–4:
(1)
The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins
are multiplexed with I/O element (IOE) outputs.
Each pin of a single-ended output pair can either be in phase or 180o out
of phase. The Quartus II software places the NOT gate in the design into
the IOE to implement 180o phase with respect to the other pin in the pair.
The clock output pin pairs support the same I/O standards as standard
output pins (in the top and bottom banks) as well as LVDS, LVPECL,
differential HSTL, and differential SSTL. See Table 5–5, under “Enhanced
PLL Pins” on page 5–11 to determine which I/O standards the enhanced
PLL clock pins support.
When in single-ended or differential mode, one power pin supports six
single-ended or three differential outputs. Both outputs use the same I/O
standard in single-ended mode to maintain performance. You can also
use the external clock output pins as user output pins if external
enhanced PLL clocking is not needed.
The enhanced PLL can also drive out to any regular I/O pin through the
global or regional clock network. For this case, jitter on the output clock
is pending characterization
Enhanced PLL Software Overview
Arria GX enhanced PLLs are enabled in the Quartus II software by using
the ALTPLL megafunction. Figure 5–5 shows the available ports (as they
are named in the Quartus II ALTPLL megafunction) of the Arria GX
enhanced PLL.
5–8
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Enhanced PLLs
Figure 5–5. Enhanced PLL Ports
(1)
Physical Pin
pllena
(2), (3)
inclk0
(2), (3)
inclk1
C[5..0]
(4)
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
locked
scanwrite
clkloss
activeclock
scanread
scandataout
scandata
clkbad[1..0]
scanclk
scandone
fbin
clkswitch
areset
pfdena
(5)
pll#_out0p
pll#_out0n
(5)
pll#_out1p
(5)
pll#_out1n
(5)
pll#_out2p
(5)
pll#_out2n
(5)
Notes to Figure 5–5:
(1)
(2)
(3)
(4)
(5)
Enhanced and fast PLLs share this input pin.
These are either single-ended or differential pins.
The primary and secondary clock input can be fed from any one of four clock pins located on the same side of the
device as the PLL.
C[5..0] can drive to the global or regional clock networks or the dedicated external clock output pins.
These dedicated output clocks are fed by the C[5..0] counters.
Tables 5–3 and 5–4 describe all the enhanced PLL ports.
Table 5–3. Enhanced PLL Input Signals (Part 1 of 2)
Port
Description
Source
Destination
inclk0
Primary clock input to the PLL.
Pin or another PLL
counter
inclk1
Secondary clock input to the PLL.
Pin or another PLL
counter
fbin
External feedback input to the PLL.
Pin
PFD
pllena
Enable pin for enabling or disabling
all or a set of PLLs. Active high.
Pin
General PLL control
signal
clkswitch
Switch-over signal used to initiate
external clock switch-over control.
Active high.
Logic array
PLL switch-over circuit
Altera Corporation
May 2008
5–9
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Table 5–3. Enhanced PLL Input Signals (Part 2 of 2)
Port
Description
Source
Destination
areset
Signal used to reset the PLL which
resynchronizes all the counter
outputs. Active high.
Logic array
General PLL control
signal
pfdena
Enables the outputs from the phase
frequency detector. Active high.
Logic array
PFD
scanclk
Serial clock signal for the real-time
PLL reconfiguration feature.
Logic array
Reconfiguration circuit
scandata
Serial input data stream for the real- Logic array
time PLL reconfiguration feature.
Reconfiguration circuit
scanwrite
Enables writing the data in the scan
chain into the PLL. Active high.
Logic array
Reconfiguration circuit
scanread
Enables scan data to be written into
the scan chain. Active high.
Logic array
Reconfiguration circuit
Table 5–4. Enhanced PLL Output Signals (Part 1 of 2)
Port
Description
Source
Destination
C[5..0]
PLL output counters driving regional, PLL counter
global or external clocks.
Internal or external clock
pll#_out[2..0]p
pll#_out[2..0]n
PLL counter
These are three differential or six
single-ended external clock output
pins fed from the C[5..0]PLL
counters, and every output can be
driven by any counter. p and n are
the positive (p) and negative (n) pins
for differential pins.
Pin(s)
clkloss
Signal indicating the switch-over
circuit detected a switch-over
condition.
PLL switch-over
circuit
Logic array
clkbad[1..0]
PLL switch-over
Signals indicating which reference
circuit
clock is no longer toggling.
clkbad1 indicates inclk1 status,
clkbad0 indicates inclk0 status.
1= good; 0 = bad
Logic array
locked
Lock or gated lock output from lock
detect circuit. Active high.
Logic array
5–10
Arria GX Device Handbook, Volume 1
PLL lock detect
Altera Corporation
May 2008
Enhanced PLLs
Table 5–4. Enhanced PLL Output Signals (Part 2 of 2)
Port
Description
Source
Destination
activeclock
Signal to indicate which clock
PLL clock
multiplexer
(0 = inclk0 or 1 = inclk1) is
driving the PLL. If this signal is low,
inclk0 drives the PLL, If this signal
is high, inclk1 drives the PLL
Logic array
scandataout
Output of the last shift register in the PLL scan chain
scan chain.
Logic array
scandone
Signal indicating when the PLL has
completed reconfiguration. 1 to 0
transition indicates that the PLL has
been reconfigured.
PLL scan chain
Logic array
Enhanced PLL Pins
Table 5–5 lists the I/O standards support by enhanced PLL clock outputs.
Table 5–5. I/O Standards Supported for Enhanced PLL Pins Note (1)
(Part 1 of 2)
Input
inclk
fbin
Output
extclk
LVTTL
v
v
v
LVCMOS
v
v
v
2.5 V
v
v
v
1.8 V
v
v
v
1.5 V
v
v
v
3.3-V PCI
v
v
v
3.3-V PCI-X
v
v
v
SSTL-2 Class I
v
v
v
SSTL-2 Class II
v
v
v
SSTL-18 Class I
v
v
v
SSTL-18 Class II
v
v
v
1.8-V HSTL Class I
v
v
v
1.8-V HSTL Class II
v
v
v
1.5-V HSTL Class I
v
v
v
1.5-V HSTL Class II
v
v
v
Differential SSTL-2 Class I
v
v
v
Differential SSTL-2 Class II
v
v
v
I/O Standard
Altera Corporation
May 2008
5–11
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Table 5–5. I/O Standards Supported for Enhanced PLL Pins Note (1)
(Part 2 of 2)
Input
inclk
fbin
Output
extclk
Differential SSTL-18 Class I
v
v
v
Differential SSTL-18 Class II
v
v
v
1.8-V differential HSTL Class I
v
v
v
1.8-V differential HSTL Class II
v
v
v
1.5-V differential HSTL Class I
v
v
v
1.5-V differential HSTL Class II
v
v
v
LVDS
v
v
v
HyperTransport technology
—
—
—
Differential LVPECL
v
v
v
I/O Standard
Note to Table 5–5:
(1)
The enhanced PLL external clock output bank does not allow a mixture of both
single-ended and differential I/O standards.
Table 5–6 shows the physical pins and their purpose for Arria GX
enhanced PLLs. For inclk port connections to pins, see “Clock Control
Block” on page 5–77.
Table 5–6. Arria GX Enhanced PLL Pins Note (1) (Part 1 of 2)
Pin
Description
CLK4p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK5p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK6p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK7p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK12p/
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK13p/
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK14p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK15p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
PLL5_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 5.
PLL6_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 6.
PLL11_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 11.
PLL12_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 12.
pllena
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do
not use this pin, connect it to ground.
5–12
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Enhanced PLLs
Table 5–6. Arria GX Enhanced PLL Pins Note (1) (Part 2 of 2)
Pin
Description
PLL5_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0]ports from PLL 5.
PLL6_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0]ports from PLL 6.
PLL11_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0]ports from PLL 11.
PLL12_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0] ports from PLL 12.
VCCA_PLL5
Analog power for PLL 5. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL5
Analog ground for PLL 5. You can connect this pin to the GND plane on the board.
VCCA_PLL6
Analog power for PLL 6. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL6
Analog ground for PLL 6. You can connect this pin to the GND plane on the board.
VCCA_PLL11
Analog power for PLL 11. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL11
Analog ground for PLL 11. You can connect this pin to the GND plane on the
board.
VCCA_PLL12
Analog power for PLL 12. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL12
Analog ground for PLL 12. You can connect this pin to the GND plane on the
board.
VCCD_PLL
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not
used.
VCC_PLL5_OUT
External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n,
PLL5_OUT1p, PLL5_OUT1n, PLL5_OUT2p, and PLL5_OUT2n outputs from PLL
5.
VCC_PLL6_OUT
External clock output VCCIO power for PLL6_OUT0p, PLL6_OUT0n,
PLL6_OUT1p, PLL6_OUT1n and PLL6_OUT2p, PLL6_OUT2n outputs from PLL
6.
VCC_PLL11_OUT
External clock output VCCIO power for PLL11_OUT0p, PLL11_OUT0n,
PLL11_OUT1p, PLL11_OUT1n and PLL11_OUT2p, PLL11_OUT2n outputs from
PLL 11.
VCC_PLL12_OUT
External clock output VCCIO power for PLL12_OUT0p, PLL12_OUT0n,
PLL12_OUT1p, PLL12_OUT1n and PLL12_OUT2p, PLL12_OUT2n outputs from
PLL 12.
Note to Table 5–6:
(1)
The negative leg pins (CLKn, PLL_FBn, and PLL_OUTn) are only required with differential signaling.
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May 2008
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PLLs in Arria GX Devices
Fast PLLs
Arria GX devices contain up to four fast PLLs. Fast PLLs have high-speed
differential I/O interface capability along with general purpose features.
Fast PLL Hardware Overview
Figure 5–6 shows a diagram of the fast PLL for Arria GX devices.
Figure 5–6. Arria GX Fast PLL Block Diagram
Global or
regional clock (2)
Clock (1)
Switchover
Circuitry
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
diffioclk0 (3)
Clock
Input
loaden0 (4)
÷c0
(5)
÷n
4
Post-Scale
Counters
PFD
Charge
Pump
Loop
Filter
VCO
÷k
diffioclk1 (3)
8
loaden1 (4)
÷c1
4
Global clocks
÷c2
4
Global or
regional clock (2)
8
Regional clocks
÷c3
÷m
8
Shaded Portions of the
PLL are Reconfigurable
to DPA block
Notes to Figure 5–6:
(1)
(2)
(3)
(4)
(5)
Arria GX fast PLLs only support manual clock switchover.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock.
In high-speed differential I/O support mode, this high-speed PLL clock feeds SERDES. Arria GX devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
If the design enables this ÷2 counter, the device can use a VCO frequency range of 150 to 520 MHz.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for
source-synchronous transmitters or general-purpose external clocks.
There are no dedicated external clock output pins. The fast PLL global or
regional outputs can drive any I/O pin as an external clock output pin.
The I/O standards supported by any particular bank determines what
standards are possible for an external clock output driven by the fast PLL
in that bank.
f
For more information, see the Selectable I/O Standards in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook.
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May 2008
Fast PLLs
Fast PLL Software Overview
Arria GX fast PLLs are enabled in the Quartus II software by using the
ALTPLL megafunction. Figure 5–7 shows the available ports (as they are
named in the Quartus II ALTPLL megafunction) of the Arria GX fast PLL.
Figure 5–7. Arria GX Fast PLL Ports and Physical Destinations
Physical Pin
inclk0 (1)
C[3..0]
inclk1 (1)
Signal Driven by Internal Logic
Signal Driven to Internal Logic
pllena (2)
Internal Clock Signal
locked
areset
pfdena
scanclk
scandata
scanwrite
scandataout
scandone
scanread
Notes to Figure 5–7:
(1)
(2)
This input pin is either single-ended or differential.
This input pin is shared by all enhanced and fast PLLs.
Tables 5–7 and 5–8 show the description of all fast PLL ports.
Table 5–7. Fast PLL Input Signals
Name
Description
Source
Destination
inclk0
Primary clock input to the fast PLL.
Pin or another PLL
counter
inclk1
Secondary clock input to the fast PLL.
Pin or another PLL
counter
pllena
Enable pin for enabling or disabling all or a set
of PLLs. Active high.
Pin
PLL control signal
clkswitch
Switch-over signal used to initiate external clock Logic array
switch-over control. Active high.
Reconfiguration circuit
areset
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
PLL control signal
pfdena
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
PFD
scanclk
Serial clock signal for the real-time PLL control
feature.
Logic array
Reconfiguration circuit
scandata
Serial input data stream for the real-time PLL
control feature.
Logic array
Reconfiguration circuit
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May 2008
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Table 5–7. Fast PLL Input Signals
Name
Description
Source
Destination
scanwrite
Enables writing the data in the scan chain into
the PLL Active high.
Logic array
Reconfiguration circuit
scanread
Enables scan data to be written into the scan
chain Active high.
Logic array
Reconfiguration circuit
Table 5–8. Fast PLL Output Signals
Name
Description
Source
Destination
C[3..0]
PLL outputs driving regional or global clock.
PLL counter
Internal clock
locked
Lock or gated lock output from lock detect circuit. Active
high.
PLL lock detect
Logic array
scandataout
Output of the last shift register in the scan chain.
PLL scan chain
Logic array
scandone
Signal indicating when the PLL has completed
reconfiguration. 1 to 0 transition indicates the PLL has
been reconfigured.
PLL scan chain
Logic array
Fast PLL Pins
Table 5–9 shows the I/O standards supported by the fast PLL input pins.
Table 5–9. I/O Standards Supported for Arria GX Fast PLL Pins (Part 1 of 2)
I/O Standard
inclk
LVTTL
v
LVCMOS
v
2.5 V
v
1.8 V
v
1.5 V
v
3.3-V PCI
—
3.3-V PCI-X
—
SSTL-2 Class I
v
SSTL-2 Class II
v
SSTL-18 Class I
v
SSTL-18 Class II
v
1.8-V HSTL Class I
v
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May 2008
Fast PLLs
Table 5–9. I/O Standards Supported for Arria GX Fast PLL Pins (Part 2 of 2)
I/O Standard
inclk
1.8-V HSTL Class II
v
1.5-V HSTL Class I
v
1.5-V HSTL Class II
v
Differential SSTL-2 Class I
—
Differential SSTL-2 Class II
—
Differential SSTL-18 Class I
—
Differential SSTL-18 Class II
—
1.8-V differential HSTL Class I
—
1.8-V differential HSTL Class II
—
1.5-V differential HSTL Class I
—
1.5-V differential HSTL Class II
—
LVDS
v
HyperTransport technology
v
Differential LVPECL
—
Table 5–10 shows the physical pins and their purpose for the fast PLLs.
For inclk port connections to pins, see “Clocking” on page 5–59.
Table 5–10. Fast PLL Pins Note (1)
Pin
Description
CLK0p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
CLK1p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
CLK2p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
CLK3p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
FPLL7CLKp/n
Single-ended or differential pins that can drive the inclk port for PLL 7.
FPLL8CLKp/n
Single-ended or differential pins that can drive the inclk port for PLL 8.
pllena
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not use
this pin, connect it to GND.
VCCD_PLL
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not used.
VCCA_PLL1
Analog power for PLL 1. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL1
Analog ground for PLL 1. Your can connect this pin to the GND plane on the board.
VCCA_PLL2
Analog power for PLL 2. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL2
Analog ground for PLL 2. You can connect this pin to the GND plane on the board.
GNDA_PLL7
Analog ground for PLL 7. You can connect this pin to the GND plane on the board.
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May 2008
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Table 5–10. Fast PLL Pins Note (1)
Pin
Description
VCCA_PLL8
Analog power for PLL 8. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL8
Analog ground for PLL 8. You can connect this pin to the GND plane on the board.
Note to Table 5–10:
(1)
The negative leg pins (CLKn and FPLL_CLKn) are only required with differential signaling.
Clock Feedback
Modes
Arria GX PLLs support up to five different clock feedback modes. Each
mode allows clock multiplication and division, phase shifting, and
programmable duty cycle. Each PLL must be driven by one of its own
dedicated clock input pins for proper clock compensation. The clock
input pin connections for each PLL are listed in Table 5–20 on page 5–68.
Table 5–11 shows which modes are supported by which PLL type.
Table 5–11. Clock Feedback Mode Availability
Mode Available in
Enhanced PLLs
Fast PLLs
Source synchronous mode
Yes
Yes
No compensation mode
Yes
Yes
Normal mode
Yes
Yes
Zero delay buffer mode
Yes
No
External feedback mode
Yes
No
Clock Feedback Mode
Source-Synchronous Mode
If data and clock arrive at the same time at the input pins, they are
guaranteed to keep the same phase relationship at the clock and data
ports of any IOE input register. Figure 5–8 shows an example waveform
of clock and data in this mode. Source-synchronous mode is
recommended for source-synchronous data transfers. Data and clock
signals at the IOE experience similar buffer delays as long as you use the
same I/O standard.
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May 2008
Clock Feedback Modes
Figure 5–8. Phase Relationship Between Clock and Data in
Source-Synchronous Mode
Data pin
inclk
Data at register
Clock at register
In source-synchronous mode, enhanced PLLs compensate for clock delay
to the top and bottom I/O registers and fast PLLs compensate for clock
delay to the side I/O registers. While implementing source-synchronous
receivers in these I/O banks, use the corresponding PLL type for best
matching between clock and data delays (from input pins to register
ports).
1
Set the input pin to the register delay chain within the IOE to
zero in the Quartus II software for all data pins clocked by a
source-synchronous mode PLL.
No Compensation Mode
In this mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because the clock feedback into the
PFD does not pass through as much circuitry. Both the PLL internal and
external clock outputs are phase shifted with respect to the PLL clock
input. Figure 5–9 shows an example waveform of the PLL clocks’ phase
relationship in this mode.
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May 2008
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Figure 5–9. Phase Relationship between PLL Clocks in No Compensation
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port (1), (2)
External PLL Clock Outputs (2)
Notes to Figure 5–9:
(1)
(2)
Internal clocks fed by the PLL are phase-aligned to each other.
The PLL clock outputs can lead or lag the PLL input clocks.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin.
The external clock output pin will have a phase delay relative to the clock
input pin if connected in this mode. In normal mode, the delay
introduced by the Global Clock or Regional Clock network is fully
compensated. Figure 5–10 shows an example waveform of the PLL
clocks’ phase relationship in normal mode.
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Clock Feedback Modes
Figure 5–10. Phase Relationship Between PLL Clocks in Normal Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
External PLL Clock Outputs (1)
Note to Figure 5–10:
(1)
The external clock output can lead or lag the PLL internal clock signals.
Zero Delay Buffer Mode
In zero delay buffer mode, the external clock output pin is phase-aligned
with the clock input pin for zero delay through the device. Figure 5–11
shows an example waveform of the PLL clocks’ phase relationship in zero
delay buffer mode. When using this mode, Altera requires that you use
the same I/O standard on the input clock and output clocks. When using
single-ended I/O standards, the inclk port of the PLL must be fed by the
dedicated CLKp input pin.
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May 2008
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Figure 5–11. Phase Relationship Between PLL Clocks in Zero Delay Buffer
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
External PLL
Clock Outputs (1)
Note to Figure 5–11:
(1)
The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In external feedback mode, the external feedback input pin, fbin, is
phase-aligned with the clock input pin, (see Figure 5–12). Aligning these
clocks allows you to remove clock delay and skew between devices.
External feedback mode is possible on all enhanced PLLs. PLLs 5, 6, 11,
and 12 support feedback for one of the dedicated external outputs, either
one single-ended or one differential pair. In this mode, one C counter
feeds back to the PLL fbin input, becoming part of the feedback loop. In
external feedback mode, you will use one of the dedicated external clock
outputs (two if a differential I/O standard is used) as the PLL fbin input
pin. When using external feedback mode, Altera requires that you use the
same I/O standard on the input clock, feedback input, and output clocks.
When using single-ended I/O standards, the inclk port of the PLL must
be fed by the dedicated CLKp input pin.
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Hardware Features
Figure 5–12. Phase Relationship Between PLL Clocks in External Feedback
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at
the Register
Clock Port (1)
External PLL
Clock Outputs (1)
fBIN Clock Input
Note to Figure 5–12:
(1)
Hardware
Features
The PLL clock outputs can lead or lag the fbin clock input.
Arria GX PLLs support a number of features for general purpose clock
management. This section discusses clock multiplication and division
implementation, phase-shifting implementations, and programmable
duty cycles. Table 5–12 shows which feature is available in which type of
Arria GX PLL.
Table 5–12. Arria GX PLL Hardware Features (Part 1 of 2)
Availability
Enhanced PLL
Fast PLL
Clock multiplication and division
m (n × post-scale counter)
m (n × post-scale counter)
m counter value
Ranges from 1 through 512
Ranges from 1 through 32
counter value
Ranges from 1 through 512
Ranges from 1 through 4
Hardware Features
Post-scale counter values
Ranges from 1 through 512 (1)
Ranges from 1 through 32 (2)
Phase shift
Down to 125-ps increments (3)
Down to 125-ps increments (3)
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May 2008
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PLLs in Arria GX Devices
Table 5–12. Arria GX PLL Hardware Features (Part 2 of 2)
Hardware Features
Programmable duty cycle
Availability
Enhanced PLL
Fast PLL
Yes
Yes
Notes to Table 5–12:
(1)
(2)
(3)
Post-scale counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using
a non-50% duty cycle, the post-scale counters range from 1 through 256.
Post-scale counters range from 1 through 32 if the output clock uses a 50% duty cycle. For any output clocks using
a non-50% duty cycle, the post-scale counters range from 1 through 16.
The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Arria GX
device can shift all output frequencies in increments of at least 45. Smaller degree increments are possible
depending on the frequency and divide parameters.
Clock Multiplication and Division
Each Arria GX PLL provides clock synthesis for PLL output ports using
m/(n × post-scale counter) scaling factors. The input clock is divided by a
pre-scale factor, n, and is then multiplied by the m feedback factor. The
control loop drives VCO to match fin (m/n). Each output port has a
unique post-scale counter that divides down the high-frequency VCO.
For multiple PLL outputs with different frequencies, the VCO is set to the
least common multiple of the output frequencies that meets its frequency
specifications. For example, if output frequencies required from one PLL
are 33 and 66 MHz, the Quartus II software sets VCO to 660 MHz (the
least common multiple of 33 and 66 MHz within VCO range). Then, the
post-scale counters scale down the VCO frequency for each output port.
There is one pre-scale counter, n, and one multiply counter, m, per PLL,
with a range of 1 to 512 for both m and n in enhanced PLLs. For fast PLLs,
m ranges from 1 to 32 while n ranges from 1 to 4. There are six generic
post-scale counters in enhanced PLLs that can feed regional clocks, global
clocks, or external clock outputs, all ranging from 1 to 512 with a 50%
duty cycle setting for each PLL. The post-scale counters range from
1 to 256 with any non-50% duty cycle setting. In fast PLLs, there are four
post-scale counters (C0, C1, C2, and C3) for the regional and global clock
output ports. All post-scale counters range from 1 to 32 with a 50% duty
cycle setting. For non-50% duty cycle clock outputs, the post-scale
counters range from 1 to 16. If the design uses a high-speed I/O interface,
you can connect the dedicated dffioclk clock output port to allow the
high-speed VCO frequency to drive the serializer/deserializer (SERDES).
The Quartus II software automatically chooses the appropriate scaling
factors according to the input frequency, multiplication, and division
values entered into the ALTPLL megafunction.
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Hardware Features
Phase-Shift Implementation
Phase shift is used to implement a robust solution for clock delays in
Arria GX devices. Phase shift is implemented by using a combination of
the VCO phase output and counter starting time. VCO phase output and
counter starting time is the most accurate method of inserting delays
Because it is purely based on counter settings, which are independent of
process, voltage, and temperature.
You can phase shift the output clocks from Arria GX enhanced PLLs in
either:
■
■
Fine resolution using VCO phase taps
Coarse resolution using counter starting time
The VCO phase tap and counter starting time is implemented by allowing
any of the output counters (C[5..0] or m) to use any of the eight phases
of the VCO as the reference clock. This allows you to adjust the delay time
with a fine resolution. The minimum delay time that you can insert using
this method is defined by:
1 - = ------------------N
Φfine = -------------8f VCO
8Mf REF
where fREF is input reference clock frequency.
■
For example, if fREF is 100 MHz, n is 1, and m is 8, then fVCO is 800
MHz and Φfine equals 156.25 ps. This phase shift is defined by the PLL
operating frequency, which is governed by the reference clock
frequency and the counter settings.
You can also delay the start of the counters for a predetermined number
of counter clocks. You can express phase shift as:
C–1
( C – 1 )N
Φcoarse = ------------- = ---------------------f VCO
Mf REF
where C is the count value set for the counter delay time, (this is the initial
setting in the PLL usage section of the compilation report in the
Quartus II software). If the initial value is 1, C – 1 = 0o phase shift.
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May 2008
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PLLs in Arria GX Devices
1
Figure 5–13 shows an example of phase shift insertion using the
fine resolution and VCO phase taps method. The eight phases
from the VCO are shown and labeled for reference. For this
example, CLK0 is based off the 0phase from the VCO and has
the C value for the counter set to one. The CLK1 signal is divided
by four, two VCO clocks for high time and two VCO clocks for
low time. CLK1 is based off the 135 phase tap from the VCO and
also has the C value for the counter set to one. The CLK1 signal
is also divided by four. In this case, the two clocks are offset by
3Φ fine. CLK2 is based off the 0o phase from the VCO but has the
C value for the counter set to three. This creates a delay of
2Φcoarse, (two complete VCO periods).
Figure 5–13. Delay Insertion Using VCO Phase Output and Counter Delay Time
1/8 tVCO
tVCO
0
45
90
135
180
225
270
315
CLK0
td0-1
CLK1
td0-2
CLK2
You can use the coarse and fine phase shifts as described above to
implement clock delays in Arria GX devices. The phase-shift parameters
are set in the Quartus II software.
Programmable Duty Cycle
The programmable duty cycle allows enhanced and fast PLLs to generate
clock outputs with a variable duty cycle. This feature is supported on
each enhanced and fast PLL post-scale counter C[]. The duty cycle
setting is achieved by a low- and high-time count setting for post-scale
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Hardware Features
counters. The Quartus II software uses the frequency input and required
multiply or divide rate to determine the duty cycle choices. The post-scale
counter value determines the precision of the duty cycle. The precision is
defined by 50% divided by the post-scale counter value. The closest value
to 100% is not achievable for a given counter value. For example, if the C0
counter is ten, steps of 5% are possible for duty cycle choices between 5 to
90%.
If the device uses external feedback, you must set the duty cycle for the
counter driving the fbin pin to 50%. Combining the programmable duty
cycle with programmable phase shift allows the generation of precise
non-overlapping clocks.
Advanced Clear and Enable Control
There are several control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PLL resynchronization and
gate PLL output clocks for low-power applications.
Enhanced Lock Detect Circuit
The lock output indicates that the PLL has locked onto the reference clock.
Without any additional circuitry, the lock signal may toggle as the PLL
begins tracking the reference clock. You may need to gate the lock signal
for use as a system control. Either a gated lock signal or an ungated lock
signal from the locked port can drive the logic array or an output pin.
Arria GX enhanced and fast PLLs include a programmable counter that
holds the lock signal low for a user-selected number of input clock
transitions. This allows the PLL to lock before enabling the lock signal.
You can use the Quartus II software to set the 20-bit counter value.
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May 2008
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PLLs in Arria GX Devices
Figure 5–14 shows the timing waveform for lock and gated lock signals.
Figure 5–14. Timing Waveform for Lock and Gated Lock Signals
PLL_ENA
Reference Clock
Feedback Clock
Lock
Filter Counter
Reaches
Value Count
Gated Lock
The device resets and enables both the counter and the PLL
simultaneously when the pllena signal is asserted or the areset signal
is deasserted. Enhanced PLLs and fast PLLs support this feature. To
ensure correct circuit operation, and to ensure that the output clocks have
the correct phase relationship with respect to the input clock, Altera
recommends that the input clock be running before the Arria GX device
is finished configuring.
pllena
The pllena pin is a dedicated pin that enables or disables all PLLs on the
Arria GX device. When the pllena pin is low, the clock output ports are
driven low and all the PLLs go out of lock. When the pllena pin goes
high again, the PLLs relock and resynchronize to the input clocks. You
can choose which PLLs are controlled by the pllena signal by
connecting the pllena input port of the ALTPLL megafunction to the
common pllena input pin.
Also, whenever the PLL loses lock for any reason (for example, excessive
inclk jitter, clock switchover, PLL reconfiguration, power supply noise,
etc.), the PLL must be reset with the areset signal to guarantee correct
phase relationship between the PLL output clocks. If the phase
relationship between the input clock versus output clock, and between
different output clocks from the PLL is not important in your design, the
PLL need not be reset.
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Hardware Features
The level of the VCCSEL pin selects the pllena input buffer power.
Therefore, if VCCSEL is high, the pllena pin’s 1.8/1.5-V input buffer is
powered by VCCIO of the bank that pllena resides in. If VCCSEL is low
(GND), the pllena pin's 3.3/2.5-V input buffer is powered by VCCPD.
f
For more information about the VCCSEL pin, refer to the Configuring
Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook.
pfdena
The pfdena signals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO operates at
its last set value of control voltage and frequency with some long-term
drift to a lower frequency. The system continues running when the PLL
goes out of lock or the input clock is disabled. By maintaining the last
locked frequency, the system has time to store its current settings before
shutting down. You can either use your own control signal or clkloss
or gated locked status signals, to trigger pfdena.
areset
The areset signal is the reset or resynchronization input for each PLL.
The device input pins or internal logic can drive these input signals.
When driven high, the PLL counters reset, clearing the PLL output and
placing the PLL out of lock. The VCO is set back to its nominal setting
(~700 MHz). When driven low again, the PLL will resynchronize to its
input as it relocks. If the target VCO frequency is below this nominal
frequency, the output frequency starts at a higher value than desired as
the PLL locks.
The areset signal should be asserted every time the PLL loses lock to
guarantee the correct phase relationship between the PLL input clock and
output clocks. You should include the areset signal in designs if any of
the following conditions are true:
■
■
■
1
Altera Corporation
May 2008
PLL reconfiguration or clock switchover is enabled in the design.
Phase relationships between the PLL input clock and output clocks
need to be maintained after a loss of lock condition.
If the input clock to the PLL is not toggling or is unstable upon power
up, assert the areset signal after the input clock is toggling, making
sure to stay within the input jitter specification.
Altera recommends that you use the areset and locked
signals in your designs to control and observe the status of your
PLL.
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clkena
If the system cannot tolerate the higher output frequencies when using
pfdena higher value, the clkena signals can disable the output clocks
until the PLL locks. The clkena signals control the regional, global, and
external clock outputs. The clkena signals are registered on the falling
edge of the counter output clock to enable or disable the clock without
glitches. See Figure 5–53 on page 5–81 for more information about the
clkena signals.
Advanced
Features
Arria GX PLLs offer a variety of advanced features, such as counter
cascading, clock switchover, PLL reconfiguration, reconfigurable
bandwidth, and spread-spectrum clocking. Table 5–13 shows which
advanced features are available in which type of Arria GX PLL.
Table 5–13. Arria GX PLL Advanced Features
Advanced Feature
Availability
Enhanced PLLs
Fast PLLs(1)
Counter cascading
v
—
Clock switchover
v
v
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread-spectrum clocking
v
—
Note to Table 5–13:
(1)
Arria GX fast PLLs only support manual clock switchover, not automatic clock
switchover.
Counter Cascading
The Arria GX enhanced PLL supports counter cascading to create
post-scale counters larger than 512. This is implemented by feeding the
output of one counter into the input of the next counter in a cascade chain,
as shown in Figure 5–15.
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Advanced Features
Figure 5–15. Counter Cascading
VCO Output
VCO Output
VCO Output
C0
C1
C2
VCO Output
C3
VCO Output
C4
VCO Output
C5
When cascading counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter
with the product of the individual counter settings. For example, if
C0 = 4 and C1 = 2, the cascaded value is C0 × C1 = 8.
1
Arria GX fast PLLs do not support counter cascading.
Counter cascading is set in the configuration file, meaning they can not be
cascaded using PLL reconfiguration.
Clock Switchover
The clock switchover feature allows the PLL to switch between two
reference input clocks. Use the clock switchover feature for clock
redundancy or for a dual clock domain application such as in a system
that turns on the redundant clock if the primary clock stops running. The
design can perform clock switchover automatically, when the clock is no
longer toggling, or based on a user control signal, clkswitch.
1
Enhanced PLLs support both automatic and manual switchover,
while fast PLLs only support manual switchover.
Automatic Clock Switchover
Arria GX device PLLs support a fully configurable clock switchover
capability. Figure 5–16 shows the block diagram of the switch-over circuit
built into the enhanced PLL. When the primary clock signal is not present,
the clock sense block automatically switches from the primary to the
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May 2008
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secondary clock for PLL reference. The design sends out the clkbad0,
clkbad1, and clkloss signals from the PLL to implement a custom
switchover circuit.
Figure 5–16. Automatic Clock Switchover Circuit Block Diagram
clkbad0
clksw
clkbad1
Activeclock
clkloss
Switch-Over
State
Machine
Clock
Sense
clkswitch
Provides manual
switchover support.
inclk0
n Counter
inclk1
muxout
PFD
refclk
fbclk
There are two possible ways to use the clock switchover feature.
■
Use the switchover circuitry for switching from a primary to
secondary input of the same frequency. For example, in applications
that require a redundant clock with the same frequency as the
primary clock, the switchover state machine generates a signal that
controls the multiplexer select input shown on the bottom of
Figure 5–16. In this case, the secondary clock becomes the reference
clock for the PLL. This automatic switchover feature only works for
switching from the primary to secondary clock.
■
Use the CLKSWITCH input for user- or system-controlled switch
conditions. This is possible for same-frequency switchover or to
switch between inputs of different frequencies. For example, if
inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the
switchover because the automatic clock-sense circuitry cannot
monitor primary and secondary clock frequencies with a frequency
difference of more than 20%. This feature is useful when clock
sources can originate from multiple cards on the backplane,
requiring a system-controlled switchover between frequencies of
operation. You should choose the secondary clock frequency so the
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Advanced Features
VCO operates within the recommended range of 500 to 1,000 MHz.
You should also set the m and n counters accordingly to keep the
VCO operating frequency in the recommended range.
Figure 5–17 shows an example waveform of the switchover feature when
using automatic clkloss detection. Here, the inclk0 signal gets stuck
low. After the inclk0 signal is stuck at low for approximately two clock
cycles, the clock sense circuitry drives the clkbad0 signal high. Also,
because the reference clock signal is not toggling, the clkloss signal
goes low, indicating a switch condition. Then, the switchover state
machine controls the multiplexer through the clksw signal to switch to
the secondary clock.
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May 2008
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Figure 5–17. Automatic Switchover Upon Clock Loss Detection
inclk0
inclk1
(1)
(2)
muxout
refclk
fbclk
clkbad0
(3)
(4)
clkbad1
lock
activeclock
clkloss
PLL Clock
Output
Notes to Figure 5–17:
(1)
(2)
(3)
(4)
The number of clock edges before allowing switchover is determined by the counter setting.
Switchover is enabled on the falling edge of inclk1.
The rising edge of fbclk causes the VCO frequency to decrease.
The rising edge of refclk starts the PLL lock process again, and the VCO frequency increases.
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Advanced Features
The switch-over state machine has two counters that count the edges of
the primary and secondary clocks; counter0 counts the number of
inclk0 edges and counter1 counts the number of inclk1 edges. The
counters get reset to zero when the count values reach 1, 1; 1, 2; 2, 1; or 2, 2
for inclk0 and inclk1, respectively. For example, if counter0 counts
two edges, its count is set to two and if counter1 counts two edges
before counter0 sees another edge, they are both reset to 0. If for some
reason one of the counters counts to three, it means the other clock missed
an edge. The clkbad0 or clkbad1 signal goes high and the switchover
circuitry signals a switch condition. See Figure 5–18.
Figure 5–18. Clock-Edge Detection for Switchover
Reset
Count of three on
single clock indicates
other missed edge.
inclk0
inclk1
clkbad0
Manual Override
When using automatic switchover, you can switch input clocks by using
the manual override feature with clkswitch input.
1
The manual override feature available in automatic clock
switchover is different from manual clock switchover.
Figure 5–19 shows an example of a waveform illustrating the switchover
feature when controlled by clkswitch. In this case, both clock sources
are functional and inclk0 is selected as the primary clock. clkswitch
goes high, which starts the switchover sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent
any clock glitching. On the falling edge of inclk1, the reference clock
multiplexer switches from inclk0 to inclk1 as the PLL reference. This
is also when the clkswitch signal changes to indicate which clock is
selected as primary and which is secondary.
The clkloss signal mirrors the clkswitch signal and activeclock
mirrors clkswitch in manual override mode. Because both clocks are
still functional during the manual switch, neither clkbad signal goes
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high. Because the switchover circuit is edge-sensitive, the falling edge of
the clkswitch signal does not cause the circuit to switch back from
inclk1 to inclk0. When the clkswitch signal goes high again, the
process repeats. clkswitch and automatic switch only work if the clock
being switched to is available. If the clock is not available, the state
machine waits until the clock is available.
Figure 5–19. Clock Switchover Using the CLKSWITCH Control
inclk0
inclk1
muxout
clkswtch
activeclock
clkloss
clkbad0
clkbad1
Figure 5–20 shows a simulation of using switchover for two different
reference frequencies. In this example simulation, the reference clock is
either 100 or 66 MHz. The PLL begins with fin=100 MHz and is allowed to
lock. At 20 ms, the clock is switched to the secondary clock, which is at
66 MHz.
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Advanced Features
Figure 5–20. Switchover Simulation Note (1)
10
9
8
7
6
PLL Output
5
Frequency (x10 MHz)
4
3
2
1
0
0
5
10
15
20
25
30
35
40
Time (μs)
Note to Figure 5–20:
(1)
This simulation was performed under the following conditions: the counter is set to 2, the m counter is set to 16, and
the output counter is set to 8. Therefore, the VCO operates at 800 MHz for the 100-MHz input references and at
528 MHz for the 66-MHz reference input.
Lock Signal-Based Switchover
The lock circuitry can initiate automatic switchover. This is useful for
cases where the input clock is still clocking, but its characteristics have
changed so that the PLL is not locked to it. The switchover enable is based
on both the gated and ungated lock signals. If the ungated lock is low,
switchover is not enabled until the gated lock has reached its terminal
count. You must activate switchover enable if the gated lock is high, but
the ungated lock goes low. The switchover timing for this mode is similar
to the waveform shown in Figure 5–19 for clkswitch control, except
switchover enable replaces clkswitch. Figure 5–21 shows the
switchover enable circuit when controlled by lock and gated lock.
Figure 5–21. Switchover Enable Circuit
Lock
Gated Lock
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May 2008
Switchover
Enable
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Manual Clock Switchover
Arria GX enhanced and fast PLLs support manual switchover, where the
clkswitch signal controls whether inclk0 or inclk1 is the input
clock to the PLL. If clkswitch is low, inclk0 is selected; if clkswitch
is high, inclk1 is selected. Figure 5–22 shows the block diagram of the
manual switchover circuit in fast PLLs. The block diagram of the manual
switchover circuit in enhanced PLLs is shown in Figure 5–22.
Figure 5–22. Manual Clock Switchover Circuitry in Fast PLLs
clkswitch
inclk0
n Counter
PFD
inclk1
muxout
refclk
fbclk
Figure 5–23 shows an example of a waveform illustrating the switchover
feature when controlled by clkswitch. In this case, both clock sources
are functional and inclk0 is selected as the primary clock. clkswitch
goes high, which starts the switchover sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent
any clock glitching. On the rising edge of inclk1, the reference clock
multiplex switches from inclk0 to inclk1 as the PLL reference. When
the clkswitch signal goes low, the process repeats, causing the circuit to
switch back from inclk1 to inclk0.
Figure 5–23. Manual Switchover
inclk0
inclk1
muxout
clkswitch
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Advanced Features
Software Support
Table 5–14 summarizes the signals used for clock switchover.
Table 5–14. ALTPLL Megafunction Clock Switchover Signals
Port
Description
Source
Destination
inclk0
Reference clk0 to the PLL.
I/O pin
Clock switchover
circuit
inclk1
Reference clk1 to the PLL.
I/O pin
Clock switchover
circuit
clkbad0 (1)
Signal indicating that inclk0 is no
longer toggling.
Clock switchover
circuit
Logic array
clkbad1 (1)
Signal indicating that inclk1 is no
longer toggling.
Clock switchover
circuit
Logic array
clkswitch
Switchover signal used to initiate clock
Logic array or I/O
switchover asynchronously. When used in pin
manual switchover, clkswitch is used
as a select signal between inclk0 and
inclk1 clkswitch = 0 inclk0 is
selected and vice versa.
Clock switchover
circuit
clkloss (1)
Signal indicating that the switchover
circuit detected a switch condition.
Clock switchover
circuit
Logic array
locked
Signal indicating that the PLL has lost
lock.
PLL
Clock switchover
circuit
Signal to indicate which clock (0 =
PLL
Logic array
activeclock (1)
inclk0, 1= inclk1) is driving the PLL.
Note for Table 5–14:
(1)
These ports are only available for enhanced PLLs, in automatic mode, and when using automatic switchover.
All the switchover ports shown in Table 5–14 are supported in the
ALTPLL megafunction in the Quartus II software. The ALTPLL
megafunction supports two methods for clock switchover:
■
■
When selecting an enhanced PLL, you can enable both automatic and
manual switchover, making all the clock switchover ports available.
When selecting a fast PLL, you can only enable the manual clock
switchover option to select between inclk0 or inclk1. The
clkloss, activeclock, clkbad0, and clkbad1 signals are not
available when you select manual switchover.
If the primary and secondary clock frequencies are different, the
Quartus II software selects the proper parameters to keep the VCO within
the recommended frequency range.
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May 2008
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f
For more information about PLL support in the Quartus II software, see
the altpll Megafunction User Guide.
Guidelines
Use the following guidelines to design with clock switchover in PLLs:
■
When using automatic switchover, the clkswitch signal has a
minimum pulse width based on the two reference clock periods. The
clkswitch pulse width must be greater than or equal to the period
of the current reference clock (tfrom_clk) multiplied by two plus the
rounded-up version of the ratio of the two reference clock periods.
For example, if tto_clk is equal to tfrom_clk, the clkswitch pulse width
should be at least three times the period of the clock pulse.
tclkswitchmin ≥ tfrom_clk × [2 + intround_up (tto_clk ÷ tfrom_clk)]
■
■
■
■
Applications that require a clock switchover feature and a small
frequency drift should use a low-bandwidth PLL. The
low-bandwidth PLL reacts slower than a high-bandwidth PLL to
reference input clock changes. When switchover happens, a
low-bandwidth PLL propagates the stopping of the clock to the
output slower than a high-bandwidth PLL. A low-bandwidth PLL
filters out jitter on the reference clock. However, be aware that the
low-bandwidth PLL also increases lock time.
Arria GX device PLLs can use both automatic clock switchover and
clkswitch input simultaneously. Therefore, the switchover
circuitry can automatically switch from the primary to the secondary
clock. Once the primary clock stabilizes again, the clkswitch signal
can switch back to the primary clock. During switchover, PLL_VCO
continues to run and slows down, generating frequency drift on the
PLL outputs. The clkswitch signal controls switchover with its
rising edge only.
If the clock switchover event is glitch-free, after the switch occurs,
there is still a finite resynchronization period to lock onto a new clock
as the VCO ramps up. The exact amount of time it takes for the PLL
to relock depends on the PLL configuration. Use the PLL
programmable bandwidth feature to adjust the relock time.
If the phase relationship between the input clock to the PLL and
output clock from the PLL is important in your design, assert
areset for 10 ns after performing a clock switchover. Wait for the
locked signal (or gated lock) to go high before re-enabling the output
clocks from the PLL.
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Advanced Features
■
Figure 5–24 shows how the VCO frequency gradually decreases
when the primary clock is lost and then increases as the VCO locks
on to the secondary clock. After the VCO locks on to the secondary
clock, some overshoot can occur (an over-frequency condition) in the
VCO frequency.
Figure 5–24. VCO Switchover Operating Frequency
Primary Clock Stops Running
Frequency Overshoot
Switchover Occurs
VCO Tracks Secondary Clock
ΔFvco
■
■
Altera Corporation
May 2008
Disable the system during switchover if it is not tolerant to frequency
variations during the PLL resynchronization period. There are two
ways to disable the system. First, the system may require some time
to stop before switchover occurs. The switchover circuitry includes
an optional five-bit counter to delay when the reference clock is
switched. You have the option to control the time-out setting on this
counter (up to 32 cycles of latency) before the clock source switches.
You can use these cycles for disaster recovery. The clock output
frequency varies slightly during those 32 cycles because the VCO can
still drift without an input clock. Programmable bandwidth can
control the PLL response to limit drift during this 32 cycle period.
A second option available is the ability to use the PFD enable signal
(pfdena) along with user-defined control logic. In this case you can
use the clk0_bad and clk1_bad status signals to turn off PFD so
the VCO maintains its last frequency. You can also use the state
machine to switch over to the secondary clock. Upon re-enabling the
PFD, the output clock enable signals (clkena) can disable clock
outputs during the switchover and resynchronization period. Once
the lock indication is stable, the system can re-enable the output
clock(s).
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Reconfigurable
Bandwidth
Arria GX enhanced and fast PLLs provide advanced control of the PLL
bandwidth using the PLL loop’s programmable characteristics, including
loop filter and charge pump.
Background
PLL bandwidth is the measure of the PLL’s ability to track the input clock
and jitter. The closed-loop gain 3-dB frequency in the PLL determines the
PLL bandwidth. The bandwidth is approximately the unity gain point for
open loop PLL response. As Figure 5–25 shows, these points correspond
to approximately the same frequency.
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Reconfigurable Bandwidth
Figure 5–25. Open- and Closed-Loop Response Bode Plots
Open-Loop Reponse Bode Plot
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
0 dB
Gain
Frequency
Closed-Loop Reponse Bode Plot
Gain
Frequency
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May 2008
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A high-bandwidth PLL provides a fast lock time and tracks jitter on the
reference clock source, passing it through to the PLL output. A
low-bandwidth PLL filters out reference clock, but increases lock time.
Arria GX enhanced and fast PLLs allow you to control the bandwidth
over a finite range to customize the PLL characteristics for a particular
application. The programmable bandwidth feature in Arria GX PLLs
benefits applications requiring clock switchover (for example, TDMA
frequency hopping wireless and redundant clocking).
The bandwidth and stability of such a system is determined by the charge
pump current, loop filter resistor value, high-frequency capacitor value
(in the loop filter), and m-counter value. You can use the Quartus II
software to control these factors and to set the bandwidth to the desired
value within a given range.
You can set the bandwidth to the appropriate value to balance the need
for jitter filtering and lock time. Figures 5–26 and 5–27 show the output of
a low- and high-bandwidth PLL, respectively, as it locks onto the input
clock.
Figure 5–26. Low-Bandwidth PLL Lock Time
160
155
Lock Time = 8 μs
150
145
Frequency (MHz)
140
135
130
125
120
0
5
10
15
Time (μs)
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Reconfigurable Bandwidth
Figure 5–27. High-Bandwidth PLL Lock Time
160
155
Lock Time = 4 μs
150
145
Frequency (MHz)
140
135
130
125
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (μs)
A high-bandwidth PLL can benefit a system that has two cascaded PLLs.
If the first PLL uses spread spectrum (as user-induced jitter), the second
PLL can track the jitter that is feeding it by using a high-bandwidth
setting. A low-bandwidth PLL can, in this case, lose lock due to the
spread-spectrum-induced jitter on the input clock.
A low-bandwidth PLL benefits a system using clock switchover. When
clock switchover happens, the PLL input temporarily stops. A
low-bandwidth PLL would react more slowly to changes to its input
clock and take longer to drift to a lower frequency (caused by the input
stopping) than a high-bandwidth PLL. Figures 5–28 and 5–29
demonstrate this property. The two plots show the effects of clock
switchover with a low- or high-bandwidth PLL. When clock switchover
happens, the output of the low-bandwidth PLL (see Figure 5–28) drifts to
a lower frequency more slowly than the high-bandwidth PLL output (see
Figure 5–29).
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May 2008
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Figure 5–28. Effect of Low Bandwidth on Clock Switchover
164
162
160
158
Frequency (MHz)
Input Clock Stops
Re-lock
156
Initial Lock
154
152
Switchover
150
0
5
10
15
20
25
30
35
40
Time (μs)
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Reconfigurable Bandwidth
Figure 5–29. Effect of High Bandwidth on Clock Switchover
160
Input Clock Stops
Re-lock
155
Initial Lock
150
145
Frequency (MHz)
140
135
Switchover
130
125
0
2
4
6
8
10
12
14
16
18
20
Time (μs)
Implementation
Traditionally, external components such as the VCO or loop filter control
a PLL’s bandwidth. Most loop filters are made up of passive components
such as resistors and capacitors that take up unnecessary board space and
increase cost. With Arria GX PLLs, all the components are contained
within the device to increase performance and decrease cost.
Arria GX PLLs implement reconfigurable bandwidth by giving you
control of the charge pump current, loop filter resistor (R), and
high-frequency capacitor CH values (see Table 5–15). The Arria GX
enhanced PLL bandwidth ranges from 130 kHz to 16.9 MHz. The
Arria GX fast PLL bandwidth ranges from 1.16 to 28 MHz.
The charge pump current directly affects PLL bandwidth. The higher the
charge pump current, the higher the PLL bandwidth. You can choose
from a fixed set of values for the charge pump current. Figure 5–30 shows
the loop filter and the components that can be set through the Quartus II
software. The components are the loop filter resistor, R, and high
frequency capacitor, CH, and the charge pump current, IUP or IDN.
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Figure 5–30. Loop Filter Programmable Components
IUP
PFD
R
Ch
IDN
C
Software Support
The Quartus II software provides two levels of bandwidth control:
Megafunction-Based Bandwidth Setting
The first level of programmable bandwidth allows you to enter a value
for the desired bandwidth directly into the Quartus II software using the
ALTPLL megafunction. You can also set the bandwidth parameter in the
ALTPLL megafunction to the desired bandwidth. The Quartus II
software selects the best bandwidth parameters available to match your
bandwidth request. If the individual bandwidth setting request is not
available, the Quartus II software selects the closest achievable value.
Advanced Bandwidth Setting
An advanced level of control is also possible using advanced loop filter
parameters. You can dynamically change the charge pump current, loop
filter resistor value, and loop filter (high frequency) capacitor value. The
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PLL Reconfiguration
parameters for these changes are: charge_pump_current,
loop_filter_r, and loop_filter_c. Each parameter supports the
specific range of values listed in Table 5–15.
Table 5–15. Advanced Loop Filter Parameters
Parameter
Values
Resistor values (kΩ)
(1)
High-frequency capacitance values (pF)
(1)
Charge pump current settings (μΑ)
(1)
Note to Table 5–15:
(1)
f
For more information, see AN 367: Implementing PLL Reconfiguration in Stratix II
Devices. The information presented in AN 367 applies to Arria GX enhanced and
fast PLLs as well.
For more information about Quartus II software support of
reconfigurable bandwidth, see the PLL Reconfiguration section in the
Embedded Peripherals section of the Quartus II Handbook.
PLL
Reconfiguration
PLLs use several divide counters and different VCO phase taps to
perform frequency synthesis and phase shifts. In Arria GX enhanced and
fast PLLs, the counter value and phase are configurable in real time. In
addition, you can change the loop filter and charge pump components,
which affect the PLL bandwidth, on-the-fly. You can control these PLL
components to update the output clock frequency, PLL bandwidth, and
phase-shift variation in real time, without the need to reconfigure the
entire FPGA.
f
For more information about PLL reconfiguration in Arria GX devices,
see AN 367: Implementing PLL Reconfiguration in Stratix II Devices. The
information presented in AN 367 applies to Arria GX enhanced and fast
PLLs as well.
SpreadSpectrum
Clocking
Digital clocks are square waves with short rise times and a 50% duty
cycle. These high-speed clocks concentrate a significant amount of energy
in a narrow bandwidth at the target frequency and at higher frequency
harmonics. This results in high energy peaks and increased
electromagnetic interference (EMI). The radiated noise from the energy
peaks travels in free air and, if not minimized, can lead to corrupted data
and intermittent system errors, which can jeopardize system reliability.
Traditional methods for limiting EMI include shielding, filtering, and
multi-layer printed circuit boards (PCBs). However, these methods
significantly increase overall system cost and sometimes are not enough
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to meet EMI compliance. Spread-spectrum technology provides you with
a simple and effective technique for reducing EMI without additional cost
and the trouble of re-designing a board.
Spread-spectrum technology modulates the target frequency over a small
range. For example, if a 100-MHz signal has a 0.5% down-spread
modulation, the frequency is swept from 99.5 to 100 MHz. Figure 5–31
gives a graphical representation of the energy present in a
spread-spectrum signal versus a non-spread spectrum-signal. It is
apparent that instead of concentrating the energy at the target frequency,
the energy is re-distributed across a wider band of frequencies, which
reduces peak energy. Not only is there a reduction in fundamental peak
EMI components, but there is also a reduction in EMI of the higher order
harmonics. Because some regulations focus on peak EMI emissions rather
than average EMI emissions, spread-spectrum technology is a valuable
method of EMI reduction.
Figure 5–31. Spread-Spectrum Signal Energy Versus Non-Spread-Spectrum Signal Energy
Spread-Spectrum Signal
Non-Spread-Spectrum Signal
Δ = ~5 dB
Amplitude
(dB)
δ = 0.5%
Frequency
(MHz)
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Spread-Spectrum Clocking
Spread-spectrum technology would benefit a design with high EMI
emissions and/or strict EMI requirements. Device-generated EMI is
dependent on frequency and output voltage swing amplitude and edge
rate. For example, a design using LVDS already has low EMI emissions
because of low-voltage swing. The differential LVDS signal also allows
for EMI rejection within the signal. Therefore, this situation may not
require spread-spectrum technology.
1
Spread-spectrum clocking is only supported in Arria GX
enhanced PLLs, not fast PLLs.
Implementation
Arria GX device enhanced PLLs feature spread-spectrum technology to
reduce the EMIs emitted from the device. The enhanced PLL provides
approximately 0.5% down spread using a triangular, also known as
linear, modulation profile. The modulation frequency is programmable
and ranges from approximately 100 to 500 kHz. The spread percentage is
based on the clock input to the PLL and the m and n settings.
Spread-spectrum technology reduces peak energy by four to six dB at the
target frequency. However, this number is dependent on bandwidth and
m and n counter values and can vary from design to design.
Spread percentage, also known as modulation width, is defined as the
percentage that the design modulates the target frequency. A negative (–)
percentage indicates a down spread, a positive (+) percentage indicates
an up spread, and a (±) indicates a center spread. Modulation frequency
is the frequency of the spreading signal, or how fast the signal sweeps
from the minimum to the maximum frequency. Down-spread
modulation shifts target frequency down by half the spread percentage,
centering the modulated waveforms on a new target frequency.
The m and n counter values are toggled at the same time between two
fixed values. The loop filter then slowly changes the VCO frequency to
provide the spreading effect, which results in a triangular modulation. An
additional spread-spectrum counter (shown in Figure 5–32) sets the
modulation frequency. Figure 5–32 shows how spread-spectrum
technology is implemented in the Arria GX device enhanced PLL.
Altera Corporation
May 2008
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PLLs in Arria GX Devices
Figure 5–32. Arria GX Spread-Spectrum Circuit Block
÷n
refclk
Up
PFD
Down
SpreadSpectrum
Counter
÷m
n count1
n count2
m count1
m count2
Figure 5–33 shows a VCO frequency waveform when toggling between
different counter values. Because the enhanced PLL switches between
two different m and n values, the result is a straight line between two
frequencies, which gives a linear modulation. The magnitude of
modulation is determined by the ratio of two m/n sets. The percent
spread is determined by:
percent spread =(fVCOmax - fVCOmin)/fVCOmax = 1 - [(m2 × n1)/(m1 × n2)].
The maximum and minimum VCO frequency is defined as:
■
■
fVCOmax = (m1/n1) × fREF
fVCOmin = (m2/n2) × fREF
Figure 5–33. VCO Frequency Modulation Waveform
count2 values
count1 values
VCO Frequency
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May 2008
Spread-Spectrum Clocking
Software Support
You can enter the desired down-spread percentage and modulation
frequency in the ALTPLL megafunction through the Quartus II software.
Alternatively, you can set the downspread parameter in the ALTPLL
megafunction to the desired down-spread percentage. Timing analysis
ensures the design operates at the maximum spread frequency and meets
all timing requirements.
f
For more information about PLL support in the Quartus II software, see
the altpll Megafunction User Guide.
Guidelines
If the design cascades PLLs, the source (upstream) PLL must have a
low-bandwidth setting while the destination (downstream) PLL must
have a high-bandwidth setting. The upstream PLL must have a
low-bandwidth setting because a PLL does not generate jitter higher than
its bandwidth. The downstream PLL must have a high bandwidth setting
to track the jitter. The design must use the spread-spectrum feature in a
low-bandwidth PLL so the Quartus II software will automatically set the
spread-spectrum PLL bandwidth to low.
1
If you use the programmable or reconfigurable bandwidth
features, you cannot use spread spectrum.
Arria GX devices can accept a spread-spectrum input with typical
modulation frequencies. However, the device cannot automatically
detect that the input is a spread-spectrum signal. Instead, the input signal
looks like deterministic jitter at the input of the downstream PLL.
Spread spectrum can have a minor effect on the output clock by
increasing period jitter. Period jitter is the deviation of a clock’s cycle time
from its previous cycle position. Period jitter measures the variation of the
clock output transition from its ideal position over consecutive edges.
With down-spread modulation, the peak of the modulated waveform is
the actual target frequency. Therefore, the system never exceeds the
maximum clock speed. To maintain reliable communication, the entire
system and subsystem should use the Arria GX device as the clock source.
Communication could fail if the Arria GX logic array is clocked by the
spread-spectrum clock, but the data it receives from another device is not
clocked by the spread spectrum.
Because spread-spectrum affects the m counter values, all spreadspectrum PLL outputs are effected. Therefore, if only one spreadspectrum signal is needed, the clock signal should use a separate PLL
without other outputs from that PLL.
Altera Corporation
May 2008
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PLLs in Arria GX Devices
No special considerations are needed when using spread-spectrum with
the clock switchover feature. This is because the clock switchover feature
does not affect the m and n counter values, which are the counter values
switching when using the spread-spectrum feature.
Board Layout
The enhanced and fast PLL circuits in Arria GX devices contain analog
components embedded in a digital device. These analog components
have separate power and ground pins to minimize noise generated by the
digital components. Arria GX enhanced and fast PLLs use separate VCC
and ground pins to isolate circuitry and improve noise resistance.
VCCA and GNDA
Each enhanced and fast PLL uses separate VCC and ground pin pairs for
their analog circuitry. The analog circuit power and ground pin for each
PLL is called VCCA_PLL<PLL number> and GNDA_PLL<PLL number>.
Connect the VCCA power pin to a 1.2-V power supply, even if you do not
use the PLL. Isolate the power connected to VCCA from the power to the
rest of the Arria GX device or any other digital device on the board. You
can use one of three different methods of isolating the VCCA pin: separate
VCCA power planes, a partitioned VCCA island within the VCCINT plane,
and thick VCCA traces.
Separate VCCA Power Plane
A mixed signal system is already partitioned into analog and digital
sections, each with its own power planes on the board. To isolate the VCCA
pin using a separate VCCA power plane, connect the VCCA pin to the
analog 1.2-V power plane.
Partitioned VCCA Island Within the VCCINT Plane
Fully digital systems do not have a separate analog power plane on the
board. Because it is expensive to add new planes to the board, you can
create islands for VCCA_PLL. Figure 5–34 shows an example board layout
with an analog power island. The dielectric boundary that creates the
island should be 25 mils thick. Figure 5–35 shows a partitioned plane
within VCCINT for VCCA.
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May 2008
Board Layout
Figure 5–34. VCCINT Plane Partitioned for VCCA Island
Thick VCCA Trace
Because of board constraints, you may not be able to partition a VCCA
island. Instead, run a thick trace from the power supply to each VCCA pin.
The traces should be at least 20 mils thick.
In each of these three cases, you should filter each VCCA_PLL pin with a
decoupling circuit, as shown in Figure 5–35. Place a ferrite bead that
exhibits high impedance at frequencies of 50 MHz or higher and a 10-μF
tantalum parallel capacitor where the power enters the board. Decouple
each VCCA_PLL pin with a 0.1-μF and 0.001-μF parallel combination of
ceramic capacitors located as close as possible to the Arria GX device. You
can connect the GNDA_PLL pins directly to the same ground plane as the
device’s digital ground.
Altera Corporation
May 2008
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PLLs in Arria GX Devices
Figure 5–35. PLL Power Schematic for Arria GX PLLs
Ferrite
Bead
1.2-V
Supply
10 μF
GND
VCCA_PLL #
(1)
GNDA_PLL #
(1)
0.001 μF
0.1 μF
GND
GND
VCCINT
VCCD_PLL #
GND
GND
Repeat for Each
PLL Power &
Ground Set
Arria GX Device
Note to Figure 5–35:
(1)
This applies to all Arria GX PLLs.
VCCD
The digital power and ground pins are labeled VCCD_PLL<PLL number>
and GND_PLL<PLL number>. The VCCD pin supplies the power for the
digital circuitry in the PLL. Connect these VCCD pins to the quietest
digital supply on the board. In most systems, this is the digital 1.2-V
supply supplied to the device’s VCCINT pins. Connect the VCCD pins to a
power supply even if you do not use the PLL. When connecting the VCCD
pins to VCCINT, you do not need any filtering or isolation. You can
connect the GND pins directly to the same ground plane as the device’s
digital ground (see Figure 5–35).
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May 2008
Board Layout
External Clock Output Power
Enhanced PLLs 5, 6, 11, and 12 also have isolated power pins for their
dedicated external clock outputs (VCC_PLL5_OUT, VCC_PLL6_OUT,
VCC_PLL11_OUT, and VCC_PLL12_OUT, respectively). Because the
dedicated external clock outputs from a particular enhanced PLL are
powered by separate power pins, they are less susceptible to noise. They
also reduce the overall jitter of the output clock by providing improved
isolation from switching I/O pins.
1
I/O pins that reside in PLL banks 9 through 12 are powered by
the VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. If a
particular device does not support PLLs 11 or 12, any I/O pins
that reside in bank 11 are powered by the VCCIO3 pin, and any
I/O pins that reside in bank 12 are powered by the VCCIO8 pin.
The VCC_PLL_OUT pins can by powered by 3.3, 2.5, 1.8, or 1.5 V,
depending on the I/O standard for the clock output from a particular
enhanced PLL, as shown in Figure 5–36.
Figure 5–36. External Clock Output Pin Association with Output Power
VCC_PLL5_OUT
PLL5_OUT0p
PLL5_OUT0n
PLL5_OUT1p
PLL5_OUT1n
PLL5_OUT2p
PLL5_OUT2n
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May 2008
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PLLs in Arria GX Devices
1
Filter each isolated power pin with a decoupling circuit shown
in Figure 5–37. Decouple the isolated power pins with parallel
combination of 0.1- and 0.001-μF ceramic capacitors located as
close as possible to the Arria GX device.
Figure 5–37. Arria GX PLL External Clock Output Power Ball Connection
Note (1)
VCCIO
Supply
VCC_PLL#_OUT (1)
0.001 μF
0.1 μF
GND
GND
VCC_PLL#_OUT (1)
0.001 μF
0.1 μF
GND
GND
Arria GX Device
Note to Figure 5–37:
(1)
This applies only to enhanced PLLs 5, 6, 11, and 12.
Guidelines
Use the following guidelines for optimal jitter performance on the
external clock outputs from enhanced PLLs 5, 6, 11, and 12. If all outputs
are running at the same frequency, these guidelines are not necessary to
improve performance.
■
■
Use phase shift to ensure edges are not coincident on all the clock
outputs.
Use phase shift to skew clock edges with respect to each other for
best jitter performance.
If you cannot drive multiple clocks of different frequencies and phase
shifts or isolate banks, you should control the drive capability on the
lower-frequency clock. Reducing how much current the output buffer has
to supply can reduce noise. Minimize capacitive load on the slower
frequency output and configure the output buffer to lower current
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May 2008
PLL Specifications
strength. The higher-frequency output should have an improved
performance, but this may degrade the performance of your
lower-frequency clock output.
PLL
Specifications
f
Clocking
For information about PLL timing specifications, refer to the DC &
Switching Characteristics chapter in volume 1 of the Arria GX Device
Handbook.
Arria GX devices provide a hierarchical clock structure and multiple
PLLs with advanced features. The large number of clocking resources in
combination with clock synthesis precision provided by enhanced and
fast PLLs provides a complete clock-management solution.
Global and Hierarchical Clocking
Arria GX devices provide 16 dedicated global clock networks and
32 regional clock networks. These clocks are organized into a hierarchical
clock structure that allows for 24 unique clock sources per device
quadrant with low skew and delay. This hierarchical clocking scheme
provides up to 48 unique clock domains within the entire Arria GX
device. Table 5–16 lists the clock resources available on Arria GX devices.
There are 12 dedicated clock pins on Arria GX devices to drive either the
global or regional clock networks. Four clock pins drive three sides of the
Arria GX device, as shown in Figures 5–38 and 5–39. Enhanced and fast
PLL outputs can also drive the global and regional clock networks.
Table 5–16. Clock Resource Availability in Arria GX Devices
(Part 1 of 2)
Altera Corporation
May 2008
Description
Arria GX Device Availability
Number of clock input pins
12
Number of global clock networks
16
Number of regional clock
networks
32
Global clock input sources
Clock input pins, PLL outputs, logic
array, inter-transceiver clocks
Regional clock input sources
Clock input pins, PLL outputs, logic
array, inter-transceiver clocks
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PLLs in Arria GX Devices
Table 5–16. Clock Resource Availability in Arria GX Devices
(Part 2 of 2)
Description
Arria GX Device Availability
Number of unique clock sources
in a quadrant
24 (16 GCLK and 8 RCLK clocks)
Number of unique clock sources
in the entire device
48 (16 GCLK and 32 RCLK clocks)
Power-down mode
GCLK, RCLK networks, dualregional clock region
Clocking regions for high fan-out
applications
Quadrant region, dual-regional,
entire device via GCLK or RCLK
networks
Global Clock Network
Global clocks drive throughout the entire device, feeding all device
quadrants. All resources within the device IOEs, adaptive logic modules
(ALMs), digital signal processing (DSP) blocks, and all memory blocks
can use the global clock networks as clock sources. These resources can
also be used for control signals, such as clock enables and synchronous or
asynchronous clears fed by an external pin. Internal logic can also drive
the global clock networks for internally generated global clocks and
asynchronous clears, clock enables, or other control signals with large
fanout. Figure 5–38 shows the 12 dedicated CLK pins driving global clock
networks.
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May 2008
Clocking
Figure 5–38. Global Clocking Note (1)
CLK12-15
11
5
7
GCLK12 - 15
16
CLK0-3
16
1 GCLK0-3
2
GCLK8-11
16
16
GCLK4-7
8
12
6
CLK4-7
Note to Figure 5–38:
(1)
Arria GX devices do not have PLLs 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11.
Regional Clock Network
Eight regional clock networks within each quadrant of the Arria GX
device are driven by dedicated CLK input pins or from PLL outputs. The
regional clock networks only pertain to the quadrant they drive into. The
regional clock networks provide the lowest clock delay and skew for logic
contained within a single quadrant. Internal logic can also drive the
regional clock networks for internally generated regional clocks and
asynchronous clears, clock enables, or other control signals with large
fanout. The CLK pins symmetrically drive the RCLK networks within a
particular quadrant, as shown in Figure 5–39. Refer to Table 5–17 on
page 5–65 and Table 5–18 on page 5–65 for RCLK connections from CLK
pins and PLLs.
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May 2008
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PLLs in Arria GX Devices
Figure 5–39. Regional Clocking Note (1)
CLK12-15
11
5
7
RCLK28-31
RCLK24-27
RCLK20-23
RCLK0-3
CLK0 -3
Q1 Q2
1
2
Q4 Q3
RCLK16-19
RCLK4-7
RCLK12-15
8
12
6
CLK4-7
Note to Figure 5–39:
(1)
Arria GX devices do not have PLLs 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11.
Clock Sources Per Region
Each Arria GX device has 16 global clock networks and 32 regional clock
networks that provide 48 unique clock domains for the entire device.
There are 24 unique clocks available in each quadrant (16 global clocks
and 8 regional clocks) as the input resources for registers (see
Figure 5–40).
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Clocking
Figure 5–40. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Clock [23..0]
Lab Row Clock [5..0]
Regional Clock Network [7..0]
Row I/O Cell
IO_CLK[7..0]
Arria GX clock networks provide three different clocking regions:
■
■
■
Entire device clock region
Quadrant clock region
Dual-regional clock region
These clock network options provide more flexibility for routing signals
that have high fan-out to improve interface timing. By having various
sized clock regions, it is possible to prioritize the number of registers the
network can reach versus the total delay of the network.
In the first clock scheme, a source (not necessarily a clock signal) drives a
global clock network that can be routed through the entire device. This
has the maximum delay for a low-skew high-fan-out signal but allows the
signal to reach every block within the device. This is a good option for
routing global resets or clear signals.
In the second clock scheme, a source drives a single-quadrant region. This
represents the fastest, low-skew, high-fan-out signal routing resource
within a quadrant. The limitation to this resource is that it only covers a
single quadrant.
In the third clock scheme, a single source (clock pin or PLL output) can
generate a dual-regional clock by driving two regional clock network
lines (one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low-skew clock. The routing of this signal
on an entire side has approximately the same speed as in a quadrant clock
region. The internal logic-array routing that can drive a regional clock
also supports this feature. This means internal logic can drive a
dual-regional clock network. Corner fast PLL outputs only span one
quadrant and hence cannot form a dual-regional clock network.
Figure 5–41 shows this feature pictorially.
Altera Corporation
May 2008
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PLLs in Arria GX Devices
Figure 5–41. Arria GX Dual-Regional Clock Region
Clock pins or PLL outputs
can drive half of the device to
create dual-reginal clocking
regions for improved I/O
interface timing.
The 12 clock input pins, enhanced or fast PLL outputs, and internal logic
array can be the clock input sources to drive onto either global or regional
clock networks. The CLKn pins also drive the global clock network, as
shown in Table 5–20 on page 5–68. Tables 5–17 and 5–18 show the
connectivity between the CLK pins as well as the global and regional clock
networks.
Clock Inputs
The 12 clock input pins (CLK) are also used for high-fan-out control
signals, such as asynchronous clears, presets, clock enables, or protocol
signals such as TRDY and IRDY for PCI through global or regional clock
networks.
Internal Logic Array
Each global and regional clock network can also be driven by logic-array
routing to enable internal logic to drive a high-fan-out, low-skew signal.
PLL Outputs
All clock networks can be driven by the PLL counter outputs.
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Clocking
Table 5–17 shows the connection of clock pins to global clock resources.
The reason for the higher level of connectivity is to support
user-controllable global clock multiplexing.
Table 5–17. Clock Input Pin Connectivity to Global Clock Networks
Clock Resource
CLK(p) (Pin)
0
1
2
3
4
5
6
7
12
13
14
15
GCLK0
v
v
—
—
—
—
—
—
—
—
—
—
GCLK1
v
v
—
—
—
—
—
—
—
—
—
—
GCLK2
—
—
v
v
—
—
—
—
—
—
—
—
GCLK3
—
—
v
v
—
—
—
—
—
—
—
—
GCLK4
—
—
—
—
v
v
—
—
—
—
—
—
GCLK5
—
—
—
—
v
v
—
—
—
—
—
—
GCLK6
—
—
—
—
—
—
v
v
—
—
—
—
GCLK7
—
—
—
—
—
—
v
v
—
—
—
—
GCLK8
—
—
—
—
—
—
—
—
—
—
—
—
GCLK9
—
—
—
—
—
—
—
—
—
—
—
—
GCLK10
—
—
—
—
—
—
—
—
—
—
—
—
GCLK11
—
—
—
—
—
—
—
—
—
—
—
—
GCLK12
—
—
—
—
—
—
—
—
—
—
v
v
GCLK13
—
—
—
—
—
—
—
—
—
—
v
v
GCLK14
—
—
—
—
—
—
—
—
v
v
—
—
GCLK15
—
—
—
—
—
—
—
—
v
v
—
—
Note to Table 5–17:
(1)
Clock pins 8, 9, 10, and 11 are not available in Arria GX devices.
Table 5–18 summarizes the connectivity between the clock pins and the
regional clock networks. Here, each clock pin can drive two regional clock
networks, facilitating stitching of the clock networks to support the
ability to drive two quadrants with the same clock or signal.
Table 5–18. Clock Input Pin Connectivity to Regional Clock Networks Note (1) (Part 1 of 2)
CLK(p) (Pin)
Clock Resource
0
1
2
3
4
5
6
7
12
13
14
15
RCLK0
v
—
—
—
—
—
—
—
—
—
—
—
RCLK1
—
v
—
—
—
—
—
—
—
—
—
—
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May 2008
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PLLs in Arria GX Devices
Table 5–18. Clock Input Pin Connectivity to Regional Clock Networks Note (1) (Part 2 of 2)
CLK(p) (Pin)
Clock Resource
0
1
2
3
4
RCLK2
—
—
v
RCLK3
—
—
RCLK4
v
RCLK5
RCLK6
5
6
7
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
—
RCLK7
—
—
—
v
—
—
—
—
—
—
—
—
RCLK8
—
—
—
—
v
—
—
—
—
—
—
—
RCLK9
—
—
—
—
—
v
—
—
—
—
—
—
RCLK10
—
—
—
—
—
—
v
—
—
—
—
—
RCLK11
—
—
—
—
—
—
—
v
—
—
—
—
RCLK12
—
—
—
—
v
—
—
—
—
—
—
—
RCLK13
—
—
—
—
—
v
—
—
—
—
—
—
RCLK14
—
—
—
—
—
—
—
—
—
RCLK15
—
—
—
—
—
—
—
v
—
—
—
—
RCLK16
—
—
—
—
—
—
—
—
—
—
—
—
RCLK17
—
—
—
—
—
—
—
—
—
—
—
—
RCLK18
—
—
—
—
—
—
—
—
—
—
—
—
RCLK19
—
—
—
—
—
—
—
—
—
—
—
—
RCLK20
—
—
—
—
—
—
—
—
—
—
—
—
RCLK21
—
—
—
—
—
—
—
—
—
—
—
—
RCLK22
—
—
—
—
—
—
—
—
—
—
—
—
RCLK23
—
—
—
—
—
—
—
—
—
—
—
—
RCLK24
—
—
—
—
—
—
—
—
—
—
v
RCLK25
—
—
—
—
—
—
—
—
—
—
—
v
RCLK26
—
—
—
—
—
—
—
—
v
—
—
—
RCLK27
—
—
—
—
—
—
—
—
—
v
—
—
RCLK28
—
—
—
—
—
—
—
—
—
—
v
—
RCLK29
—
—
—
—
—
—
—
—
—
—
—
v
RCLK30
—
—
—
—
—
—
—
—
v
—
—
—
RCLK31
—
—
—
—
—
—
—
—
—
v
—
—
v
12
13
14
15
Note to Table 5–18:
(1)
Clock pins 8, 9, 10, and 11 are not available in Arria GX devices.
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Clocking
Clock Input Connections
Four CLK pins drive each enhanced PLL. You can use any of the pins for
clock switchover inputs into the PLL. The CLK pins are the primary clock
source for clock switchover, which is controlled in the Quartus II
software. Enhanced PLLs 5, 6, 11, and 12 also have feedback input pins.
Input clocks for fast PLLs 1, 2, 3, and 4 come from the CLK pins. A
multiplexer chooses one of two possible CLK pins to drive each PLL. This
multiplexer is not a clock switchover multiplexer and is only used for
clock input connectivity.
Either an FPLLCLK input pin or a CLK pin can drive the fast PLLs in the
corners (7 and 8) when used for general-purpose applications. CLK pins
cannot drive these fast PLLs in high-speed differential I/O mode.
Table 5–19 shows which PLLs are available in each Arria GX device and
which input clock pin drives which PLLs.
Table 5–19. Arria GX Device PLLs and PLL Clock Pin Drivers (Part 1 of 2)
All Devices
Input Pin
Fast PLLs
EP1AGX50 to EP1AGX90 Devices
Enhanced PLLs
Fast PLLs
Enhanced PLLs
1
2
5
6
7
8
11
12
CLK0
v
v
—
—
v
v
—
—
CLK1
v
v
—
—
v
v
—
—
CLK2
v
v
—
—
v
v
—
—
CLK3
v
v
—
—
v
v
—
—
CLK4
—
—
—
v
—
—
—
v
CLK5
—
—
—
v
—
—
—
v
CLK6
—
—
—
v
—
—
—
v
CLK7
—
—
—
v
—
—
—
v
CLK12
—
—
v
—
—
—
v
—
CLK13
—
—
v
—
—
—
v
—
CLK14
—
—
v
—
—
—
v
—
CLK15
—
—
v
—
—
—
v
—
PLL5_FB
—
—
v
—
—
—
—
—
PLL6_FB
—
—
—
v
—
—
—
—
PLL11_FB
—
—
—
—
—
—
v
—
PLL12_FB
—
—
—
—
—
—
—
v
Altera Corporation
May 2008
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PLLs in Arria GX Devices
Table 5–19. Arria GX Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
All Devices
Input Pin
Fast PLLs
EP1AGX50 to EP1AGX90 Devices
Enhanced PLLs
Fast PLLs
Enhanced PLLs
1
2
5
6
7
8
11
12
PLL_ENA
v
v
v
v
v
v
v
v
FPLL7CLK
—
—
—
—
v
—
—
—
FPLL8CLK
—
—
—
—
—
v
—
—
FPLL9CLK
—
—
—
—
—
—
—
—
FPLL10CLK
—
—
—
—
—
—
—
—
Notes to Table 5–19:
(1)
(2)
(3)
(4)
PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
Clock connection is available. For more information about the maximum frequency, contact Altera Applications
Group.
This is a dedicated high-speed clock input. For more information about the maximum frequency, contact Altera
Applications.
Input pins CLK[11..8] are not available in Arria GX devices.
CLK(n) Pin Connectivity to Global Clock Networks
In Arria GX devices, the clk(n) pins can also feed the global clock
network. Table 5–20 shows the clk(n) pin connectivity to global clock
networks.
Table 5–20. CLK(n) Pin Connectivity to Global Clock Network
Clock
Resource
CLK(n)
pin
4
5
6
7
12
13
14
15
GCLK4
v
—
—
—
—
—
—
—
GCLK5
—
v
—
—
—
—
—
—
GCLK6
—
—
v
—
—
—
—
—
GCLK7
—
—
—
v
—
—
—
—
GCLK12
—
—
—
—
—
—
v
—
GCLK13
—
—
—
—
—
—
—
v
GCLK14
—
—
—
—
v
—
—
—
GCLK15
—
—
—
—
—
v
—
—
5–68
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Clocking
Clock Source Control For Enhanced PLLs
The clock input multiplexer for enhanced PLLs is shown in Figure 5–42.
This block allows selection of the PLL clock reference from several
different sources. The clock source to an enhanced PLL can come from
any one of four clock input pins CLK[3..0], or from a logic-array clock.
Clock input pin connections to respective enhanced PLLs are shown in
Table 5–20. The multiplexer-select lines are set in the configuration file
only. Once programmed, this block cannot be changed without loading a
new configuration file. The Quartus II software automatically sets the
multiplexer-select signals depending on the clock sources that you select
in your design.
Figure 5–42. Enhanced PLL Clock Input Multiplex Logic
(1)
4
clk[3..0]
inclk0
core_inclk
To the Clock
Switchover Block
(1)
inclk1
4
Note to Figure 5–42:
(1)
Input clock multiplexing is controlled through a configuration file only and cannot
be dynamically controlled in user mode.
Clock Source Control for Fast PLLs
Each center fast PLL has five clock input sources, four from clock input
pins and one from a logic array signal. When using clock input pins as the
clock source, you can perform manual clock switchover among the input
clock sources. The clock input multiplexer control signals for performing
clock switchover are from core signals. Figure 5–43 shows the clock input
multiplexer control circuit for a center fast PLL.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–43. Center Fast PLL Clock Input Multiplexer Control
(1)
core_inclk
clk[3..0]
4
inclk0
To the Clock
Switchover
Block
core_inclk
inclk1
(1)
Note to Figure 5–43:
(1)
Input clock multiplexing is controlled through a configuration file only and cannot
be dynamically controlled in user mode.
Each corner fast PLL has three clock input sources, one from a dedicated
corner clock input pin, one from a center clock input pin, and one from a
logic array clock. Figure 5–44 shows a block diagram of the clock input
multiplexer control circuit for a corner fast PLL. Only the corner FPLLCLK
pin is fully compensated.
Figure 5–44. Corner Fast PLL Clock Input Multiplexer Control
core_inclk
(1)
FPLLCLK
Center
Clocks
4
inclk0
To the Clock
Switchover
Block
inclk1
(1)
core_inclk
Note to Figure 5–44:
(1)
Input clock multiplexing is controlled through a configuration file only and cannot
be dynamically controlled in user mode.
Delay Compensation for Fast PLLs
Each center fast PLL can be fed by any one of four possible input clock
pins. Among the four clock input signals, only two are fully
compensated; for example, the clock delay to the fast PLL matches the
delay in the data input path when used in the LVDS receiver mode. The
two clock inputs that match the data input path are located next to the fast
PLL. The two clock inputs that do not match the data input path are
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Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Clocking
located next to the neighboring fast PLL. Figure 5–45 shows the above
description for the left-side center fast PLL pair. If the PLL is used in
non-LVDS modes, you can use any of the four dedicated clock inputs and
are compensated.
Fast PLL 1 and PLL 2 can choose among CLK[3..0] as the clock input
source. However, for fast PLL 1, only CLK0 and CLK1 have their delay
matched to the data input path delay when used in LVDS receiver mode
operation. The delay from CLK2 or CLK3 to fast PLL 1 does not match the
data input delay. For fast PLL 2, only CLK2 and CLK3 have their delay
matched to the data input path delay in LVDS receiver mode operation.
The delay from CLK0 or CLK1 to fast PLL 2 does not match the data input
delay. The same arrangement applies to the right-side center fast PLL
pair. For corner fast PLLs, only the corner FPLLCLK pins are fully
compensated. For LVDS receiver operation, Altera recommends using the
delay compensated clock pins only.
Figure 5–45. Delay Compensated Clock Input Pins for Center Fast PLL Pair
CLK0
CLK1
Fast PLL 1
Fast PLL 2
CLK2
CLK3
Clock Output Connections
Enhanced PLLs have outputs for eight regional clock outputs and four
global clock outputs. There is line sharing between clock pins, global and
regional clock networks, and all PLL outputs. See Table 5–17 through
Table 5–21 and Figure 5–46 through Figure 5–50 to validate your clocking
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
scheme. The Quartus II software automatically maps to regional and
global clocks to avoid any restrictions. Enhanced PLLs 5, 6, 11, and 12
drive out to single-ended pins, as shown in Table 5–21.
You can connect each fast PLL 1, 2 output (C0, C1, C2, and C3) to either a
global or regional clock. There is line sharing between clock pins,
FPLLCLK pins, global and regional clock networks, and all PLL outputs.
The Quartus II software automatically maps to regional and global clocks
to avoid any restrictions.
Figure 5–46 shows clock input and output connections from the enhanced
PLLs.
1
EP1AGX20, EP1AGX35, and EX1AGX50 devices in the F484
package have only two enhanced PLLs (5 and 6), but the
connectivity from these two PLLs to the global or regional clock
networks remains the same.
EP1AGX50, EP1AGX60, and EP1AGX90 devices in the 1,152-pin package
contain eight PLLs.
5–72
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Clocking
Figure 5–46. Arria GX Top and Bottom Enhanced PLLs, Clock Pin, and Logic Array Signal Connectivity to
Global and Regional Clock Networks Note (1)
CLK15
CLK13
CLK12
CLK14
PLL5_FB
PLL11_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
Regional
Clocks
RCLK27
RCLK26
RCLK25
RCLK24
G15
G14
G13
G12
Global
Clocks
Regional
Clocks
G4
G5
G6
G7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
PLL12_FB
PLL6_FB
CLK4
CLK6
CLK5
CLK7
Note to Figure 5–46:
(1)
Redundant connection dots facilitate stitching of the clock networks to support the ability to drive two quadrants
with the same clock.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Table 5–21 shows the global and regional clocks that the PLL outputs
drive.
Table 5–21. Arria GX Global and Regional Clock Outputs From PLLs (Part 1 of 2)
All Devices (1)
EP1AGX50 and Higher Devices (2)
Fast PLLs
Enhanced PLLs
Clock Network
Fast PLLs
Enhanced PLLs
PLL Number and Type
1
2
5
6
7
8
11
12
GCLK0
v
v
—
—
v
v
—
—
GCLK1
v
v
—
—
v
v
—
—
GCLK2
v
v
—
—
v
v
—
—
GCLK3
v
v
—
—
v
v
—
—
GCLK4
—
—
—
v
—
—
—
v
GCLK5
—
—
—
v
—
—
—
v
GCLK6
—
—
—
v
—
—
—
v
GCLK7
—
—
—
v
—
—
—
v
GCLK8
—
—
—
—
—
—
—
—
GCLK9
—
—
—
—
—
—
—
—
GCLK10
—
—
—
—
—
—
—
—
GCLK11
—
—
—
—
—
—
—
—
GCLK12
—
—
v
—
—
—
v
—
GCLK13
—
—
v
—
—
—
v
—
GCLK14
—
—
v
—
—
—
v
—
GCLK15
—
—
v
—
—
—
v
—
RCLK0
v
v
—
—
v
—
—
—
RCLK1
v
v
—
—
v
—
—
—
RCLK2
v
v
—
—
v
—
—
—
RCLK3
v
v
—
—
v
—
—
—
RCLK4
v
v
—
—
—
v
—
—
RCLK5
v
v
—
—
—
v
—
—
RCLK6
v
v
—
—
—
v
—
—
RCLK7
v
v
—
—
—
v
—
—
RCLK8
—
—
—
v
—
—
—
v
RCLK9
—
—
—
v
—
—
—
v
RCLK10
—
—
—
v
—
—
—
v
5–74
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Clocking
Table 5–21. Arria GX Global and Regional Clock Outputs From PLLs (Part 2 of 2)
All Devices (1)
EP1AGX50 and Higher Devices (2)
Fast PLLs
Enhanced PLLs
Clock Network
Fast PLLs
Enhanced PLLs
PLL Number and Type
1
2
5
6
7
8
11
12
RCLK11
—
—
—
v
—
—
—
v
RCLK12
—
—
—
v
—
—
—
v
RCLK13
—
—
—
v
—
—
—
v
RCLK14
—
—
—
v
—
—
—
v
RCLK15
—
—
—
v
—
—
—
v
RCLK16
—
—
—
—
—
—
—
—
RCLK17
—
—
—
—
—
—
—
—
RCLK18
—
—
—
—
—
—
—
—
RCLK19
—
—
—
—
—
—
—
—
RCLK20
—
—
—
—
—
—
—
—
RCLK21
—
—
—
—
—
—
—
—
RCLK22
—
—
—
—
—
—
—
—
RCLK23
—
—
—
—
—
—
—
—
RCLK24
—
—
v
—
—
—
v
—
RCLK25
—
—
v
—
—
—
v
—
RCLK26
—
—
v
—
—
—
v
—
RCLK27
—
—
v
—
—
—
v
—
RCLK28
—
—
v
—
—
—
v
—
RCLK29
—
—
v
—
—
—
v
—
RCLK30
—
—
v
—
—
—
v
—
RCLK31
—
—
v
—
—
—
v
—
PLL5_OUT[3..0]p/n
—
—
v
—
—
—
—
—
PLL6_OUT[3..0]p/n
—
—
—
v
—
—
—
—
PLL11_OUT[3..0]p/n
—
—
—
—
—
—
v
—
PLL12_OUT[3..0]p/n
—
—
—
—
—
—
—
v
External Clock Output
Notes to Table 5–21:
(1)
(2)
PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
EP1AGX60 devices in 1,152-pin packages contain eight PLLs. EP1AGX60 devices in 484-pin and 780-pin packages
contain fast PLLs 1 and 2, and enhanced PLLs 5, 6, 11, and 12.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Fast PLLs also drive high-speed SERDES clocks for differential I/O
interfacing. For information about these FPLLCLK pins, contact Altera
Applications Group.
Figure 5–48 shows the global and regional clock input and output
connections from Arria GX fast PLLs.
Figure 5–47. Arria GX Center Fast PLLs, Clock Pin, and Logic Array Signal Connectivity to Global and
Regional Clock Networks
C0
CLK0
CLK1
Fast
PLL 1
C1
C2
C3
Logic Array
Signal Input
To Clock
Network
C0
CLK2
CLK3
Fast
PLL 2
C1
C2
C3
RCK0
RCK2
RCK1
RCK4
RCK3
RCK6
RCK5
GCK0
RCK7
GCK2
GCK1
GCK3
Notes to Figure 5–47:
(1)
Redundant connection dots facilitate stitching of the clock networks to support the ability to drive two quadrants
with the same clock.
5–76
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Clock Control Block
Figure 5–48. Arria GX Corner Fast PLLs, Clock Pin, and Logic Array Signal Connectivity to Global and
Regional Clock Networks Note (1)
RCK1
RCK3
RCK0
RCK2
RCK4
RCK6
C0
FPLL7CLK
Fast
PLL 7
C1
C2
C3
C0
FPLL8CLK
Fast
PLL 8
C1
C2
C3
RCK5
GCK0
RCK7
GCK2
GCK1
GCK3
Note to Figure 5–48:
(1)
Corner fast PLLs can also be driven through the global or regional clock networks. Global or regional clock input to
the fast PLL can be driven from another PLL or a pin-driven global or regional clock.
Clock Control
Block
Each global and regional clock has its own clock control block. The
control block has two functions:
■
■
Clock source selection (dynamic selection for global clocks)
Clock power down (dynamic clock enable or disable)
Figures 5–49 and 5–50 show global clock- and regional clock-select
blocks, respectively.
Altera Corporation
May 2008
5–77
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–49. Arria GX Global Clock Control Block
CLKp
Pins
PLL Counter
Outputs
2
2
CLKn
Pin
Internal
Logic
2
CLKSELECT[1..0]
(1)
Static Clock
Select (2)
This Multiplexer
Supports User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 5–49:
(1)
(2)
These clock-select signals can only be dynamically controlled through internal
logic when the device is operating in user mode.
These clock select signals can only be set through a configuration file and cannot
be dynamically controlled during user-mode operation.
Figure 5–50. Arria GX Regional Clock Control Block
CLKp
Pin
PLL Counter
Outputs
CLKn
Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 5–50:
(1)
(2)
These clock-select signals can only be dynamically controlled through a
configuration file and cannot be dynamically controlled during user-mode
operation.
Only the CLK pins on the top and bottom for the device feed to regional clock
select blocks.
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Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Clock Control Block
For the global clock select block, you can control the clock source selection
either statically or dynamically. You have the option to statically select the
clock source in the configuration file generated by the Quartus II
software, or you can control the selection dynamically by using internal
logic to drive the multiplexer select inputs. When selecting statically, you
can set the clock source to any of the inputs to the select multiplexer.
When selecting the clock source dynamically, you can either select two
PLL outputs (such as CLK0 or CLK1), or a combination of clock pins or
PLL outputs.
When using the ALTCLKCTRL megafunction to implement the clock
source dynamic selection, the inputs from the clock pins feed the
inclk[0..1] ports of the multiplexer, while the PLL outputs feed the
inclk[2..3] ports. You can choose from among these inputs using the
CLKSELECT[1..0] signal.
For the regional clock select block, you can only control the clock source
selection statically using configuration bits. You can set any of the inputs
to the clock select multiplexer the clock source.
You can disable (power down) Arria GX clock networks by both static
and dynamic approaches. When a clock net is powered down, all the logic
fed by the clock net is in an off-state, thereby reducing the overall power
consumption of the device.
Global and regional clock networks that are not used are automatically
powered down through configuration bit settings in the configuration file
(SRAM Object File (.sof) or Programmer Object File (.pof)) generated by
the Quartus II software.
The dynamic clock enable or disable feature allows the internal logic to
control power up or down synchronously on GCLK and RCLK nets,
including dual-regional clock regions. This function is independent of the
PLL and is applied directly on the clock network, as shown in Figure 5–49
on page 78 and Figure 5–50 on page 5–78.
You can set the input clock sources and the clkena signals for the global
and regional clock network multiplexers through the Quartus II software
using the ALTCLKCTRL megafunction. You can also enable or disable the
dedicated external clock output pins using the ALTCLKCTRL
megafunction. Figure 5–51 shows the external PLL output clock control
block.
Altera Corporation
May 2008
5–79
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–51. Arria GX External PLL Output Clock Control Block
PLL Counter
Outputs (c[5..0])
6
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
Notes to Figure 5–51:
(1)
(2)
Clock select signals can only be set through a configuration file and cannot be
dynamically controlled during user mode operation.
The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The
PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an
internal signal or the output of the clock control block.
clkena Signals
Figure 5–52 shows how clkena is implemented.
Figure 5–52. clkena Implementation
clkena
D
Q
clkena_out
clk
clk_out
In Arria GX devices, the clkena signals are supported at the clock
network level. This allows you to gate off the clock even when a PLL is
not being used.
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Altera Corporation
May 2008
Conclusion
The clkena signals can also be used to control the dedicated external
clocks from enhanced PLLs. Upon re-enabling, the PLL does not need a
resynchronization or relock period unless the PLL is using external
feedback mode. Figure 5–53 shows the waveform example for a clock
output enable. clkena is synchronous to the falling edge of the counter
output.
Figure 5–53. clkena Signals
counter
output
clkena
clkout
Note to Figure 5–53
(1)
You can use the clkena signals to enable or disable the global and regional networks or the PLL_OUT pins.
The PLL can remain locked independent of the clkena signals because
the loop-related counters are not affected. This feature is useful for
applications that require a low power or sleep mode. Upon re-enabling,
the PLL does not need a resynchronization or relock period. The clkena
signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during resynchronization.
Conclusion
The Arria GX device’s enhanced and fast PLLs provide you with
complete control of device clocks and system timing. These PLLs are
capable of offering flexible system-level clock management that was
previously only available in discrete PLL devices. The embedded PLLs
meet and exceed the features offered by these high-end discrete devices,
reducing the need for other timing devices in the system.
Referenced
Documents
This chapter references the following documents:
Altera Corporation
May 2008
■
■
■
altpll Megafunction User Guide
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
Configuring Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook
5–81
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PLLs in Arria GX Devices
■
■
■
Document
Revision History
DC & Switching Characteristics chapter in volume 1 of the Arria GX
Device Handbook
Embedded Peripherals section of the Quartus II Handbook
Selectable I/O Standards in Arria GX Devices chapter in volume 2 of the
Arria GX Device Handbook
Table 5–22 shows the revision history for this chapter.
Table 5–22. Document Revision History
Date and
Document
Version
May 2008
v1.2
Changes Made
●
●
Updated note 3 from Table 5–1.
Updated notes 2 and 3 from Figure 5–1.
Summary of Changes
—
Minor text edits.
—
August 2007
v1.1
Added the “Referenced Documents” section.
—
Minor text edits.
—
May 2007
v1.0
Initial Release
—
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Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Section III. Memory
This section provides information on the TriMatrix™ embedded memory
blocks internal to Arria™ GX devices and the supported external
memory interfaces.
This section contains the following chapters:
Revision History
Altera Corporation
■
Chapter 6, TriMatrix Embedded Memory Blocks in Arria GX Devices
■
Chapter 7, External Memory Interfaces in Arria GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section III–1
Preliminary
Memory
Section III–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
6. TriMatrix Embedded
Memory Blocks in Arria GX
Devices
AGX52006-1.2
Introduction
Arria™ GX devices feature the TriMatrix memory structure, consisting of
three sizes of embedded RAM blocks that efficiently address the memory
needs of FPGA designs.
TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and
512-Kbit M-RAM blocks, which are each configurable to support many
features. TriMatrix memory provides up to 4,477,824 bits of RAM at up to
380 MHz operation.
This chapter contains the following sections:
■
■
■
■
■
■
TriMatrix
Memory
Overview
“TriMatrix Memory Overview” on page 6–1
“Memory Modes” on page 6–9
“Clock Modes” on page 6–19
“Designing With TriMatrix Memory” on page 6–30
“Read-During-Write Operation at the Same Address” on page 6–32
“Conclusion” on page 6–34
TriMatrix architecture provides complex memory functions for different
applications in FPGA designs. For example, M512 blocks are used for
first-in first-out (FIFO) functions and clock domain buffering where
memory bandwidth is critical; M4K blocks are ideal for applications
requiring medium-sized memory, such as asynchronous transfer mode
(ATM) cell processing; and M-RAM blocks are suitable for large buffering
applications, such as internet protocol (IP) packet buffering and system
cache.
TriMatrix memory blocks support various memory configurations,
including single-port, simple dual-port, true dual-port (also known as
bidirectional dual-port), shift register, and ROM modes. TriMatrix
memory architecture also includes advanced features and capabilities,
such as parity-bit support, byte enable support, pack mode support,
address clock enable support, mixed port width support, and mixed clock
mode support.
When applied to output registers, the asynchronous clear signal clears the
output registers and the effects are seen immediately. Register clears are
only supported on output registers.
Altera Corporation
May 2008
6–1
TriMatrix Memory Overview
Table 6–1 summarizes the features supported by the three sizes of
TriMatrix memory.
Table 6–1. Summary of TriMatrix Memory Features
Feature
Maximum performance
Total RAM bits (including parity bits)
M512 Blocks
M4K Blocks
M-RAM Blocks
345 MHz
380 MHz
290 MHz
576
4,608
589,824
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
8K × 64
8K × 72
4K × 128
4K × 144
Parity bits
v
v
v
Byte enable
v
v
v
Pack mode
v
v
Address clock enable
v
v
Configurations
Single-port memory
v
v
v
Simple dual-port memory
v
v
v
v
v
True dual-port memory
Embedded shift register
v
v
ROM
v
v
FIFO buffer
v
v
Simple dual-port mixed width support
v
v
v
v
v
True dual-port mixed width support
Memory initialization file (.mif)
v
v
Mixed-clock mode
v
v
v
v
Power-up condition
Outputs cleared
Outputs cleared
Outputs unknown
Register clears
Output registers only
Output registers
only
Output registers
only
Same-port read-during-write
New data available at
positive clock edge
New data available
at positive clock
edge
New data available
at positive clock
edge
Mixed-port read-during-write
Outputs set to
unknown or old data
Outputs set to
Unknown output
unknown or old data
6–2
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Table 6–2 shows the capacity of the TriMatrix memory blocks for each
device in the Arria GX family.
Table 6–2. TriMatrix Memory Capacity in Arria GX Devices
Device
M-RAM
Total RAM Bits
Blocks
M512 Blocks
M4K Blocks
EP1AGX20
166
118
1
1,229,184
EP1AGX35
197
140
1
1,348,416
EP1AGX50
313
242
2
2,475,072
EP1AGX60
326
252
2
2,528,640
EP1AGX90
478
400
4
4,477,824
Parity Bit Support
All TriMatrix memory blocks (M512, M4K, and M-RAM) support one
parity bit for each byte.
Parity bits add to the amount of memory in each RAM block. For
example, the M512 block has 576 bits, 64 of which are optionally used for
parity bit storage. The parity bit, along with logic implemented in
adaptive logic modules (ALMs), implements parity checking for error
detection to ensure data integrity. Parity-size data words can also be used
for other purposes such as storing user-specified control bits.
Byte Enable Support
All TriMatrix memory blocks support byte enables that mask the input
data so that only specific bytes, nibbles, or bits of data are written. The
unwritten bytes or bits retain the previous written value. The write enable
(wren) signals, along with the byte enable (byteena) signals, control the
RAM blocks’ write operations. The default value for the byte enable
signals is high (enabled), in which case writing is controlled only by the
write enable signals. There is no clear port to the byte enable registers.
M512 Blocks
M512 blocks support byte enables for data widths of 16 and 18 bits only.
The byte-enable feature for memory block configurations with widths of
less than two bytes (×16/×18) is not supported. For memory
configurations less than two bytes wide, the write enable or clock enable
signals can optionally be used to control the write operation.
Altera Corporation
May 2008
6–3
Arria GX Device Handbook, Volume 2
TriMatrix Memory Overview
Table 6–3 summarizes the byte selection.
Table 6–3. Byte Enable for Arria GX M512 Blocks Note (1)
byteena[1..0]
data ×16
data ×18
[0] = 1
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
Note to Table 6–3:
(1)
Any combination of byte enables is possible.
M4K Blocks
M4K blocks support byte enables for any combination of data widths of
16, 18, 32, and 36 bits only. The byte-enable feature for memory block
configurations with widths of less than two bytes (×16/×18) is not
supported. For memory configurations less than two bytes wide, the
write enable or clock enable signals can optionally be used to control the
write operation. Table 6–4 summarizes the byte selection.
Table 6–4. Byte Enable for Arria GX M4K Blocks Note (1)
byteena[3..0]
data ×16
data ×18
data ×32
data ×36
[0] = 1
[7..0]
[8..0]
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
[15..8]
[17..9]
[2] = 1
-
-
[23..16]
[26..18]
[3] = 1
-
-
[31..24]
[35..27]
Note to Table 6–4:
(1)
Any combination of byte enables is possible.
M-RAM Blocks
M-RAM blocks support byte enables for any combination of data widths
of 16, 18, 32, 36, 64, and 72 bits. The byte-enable feature for memory block
configurations with widths of less than two bytes (×16/×18) is not
supported. In the ×128 and ×144 simple dual-port modes, the two sets of
byte enable signals (byteena_a and byteena_b) combine to form the
necessary 16 byte enables. In ×128 and ×144 modes, byte enables are only
supported when using single clock mode. However, the Quartus® II
software can implement byte enable in other clocking modes for ×128 or
×144 widths but will use twice as many M-RAM resources.
6–4
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
If clock enables are used in ×128 or ×144 mode, you must use the same
clock enable setting for both A and B ports. Table 6–5 summarizes the
byte selection for M-RAM blocks.
Table 6–5. Byte Enable for Arria GX M-RAM Blocks Note (1)
byteena
data ×16
data ×18
data ×32
data ×36
data ×64
data ×72
[0] = 1
[7..0]
[8..0]
[7..0]
[8..0]
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
[15..8]
[17..9]
[15..8]
[17..9]
[2] = 1
-
-
[23..16]
[26..18]
[23..16]
[26..18]
[3] = 1
-
-
[31..24]
[35..27]
[31..24]
[35..27]
[4] = 1
-
-
-
-
[39..32]
[44..36]
[5] = 1
-
-
-
-
[47..40]
[53..45]
[6] = 1
-
-
-
-
[55..48]
[62..54]
[7] = 1
-
-
-
-
[63..56]
[71..63]
Note to Table 6–5:
(1)
Any combination of byte enables is possible.
Table 6–6 summarizes the byte selection for ×144 mode.
Table 6–6. Arria GX M-RAM Combined Byte for ×144 Mode (Part 1 of 2)
Note (1)
byteena
Altera Corporation
May 2008
data ×128
data ×144
[0] = 1
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
[2] = 1
[23..16]
[26..18]
[3] = 1
[31..24]
[35..27]
[4] = 1
[39..32]
[44..36]
[5] = 1
[47..40]
[53..45]
[6] = 1
[55..48]
[62..54]
[7] = 1
[63..56]
[71..63]
[8] = 1
[71..64]
[80..72]
[9] = 1
[79..72]
[89..73]
[10] = 1
[87..80]
[98..90]
[11] = 1
[95..88]
[107..99]
[12] = 1
[103..96]
[116..108]
[13] = 1
[111..104]
[125..117]
6–5
Arria GX Device Handbook, Volume 2
TriMatrix Memory Overview
Table 6–6. Arria GX M-RAM Combined Byte for ×144 Mode (Part 2 of 2)
Note (1)
byteena
data ×128
data ×144
[14] = 1
[119..112]
[134..126]
[15] = 1
[127..120]
[143..135]
Note to Table 6–6:
(1)
Any combination of byte enables is possible.
Byte Enable Functional Waveform
Figure 6–1 shows how the write enable (wren) and byte enable
(byteena) signals control the operations of the RAM.
When a byte enable bit is de-asserted during a write cycle, the
corresponding data byte output appears as a "don't care" or unknown
value. When a byte enable bit is asserted during a write cycle, the
corresponding data byte output will be the newly written data.
Figure 6–1. Arria GX Byte Enable Functional Waveform
inclock
wren
address
data
byteena
contents at a0
contents at a1
a0
an
a2
a0
a1
ABCD
XXXX
10
XX
a2
XXXX
01
11
FFFF
XX
ABFF
FFFF
FFCD
FFFF
contents at a2
q (asynch)
a1
doutn
ABXX
6–6
Arria GX Device Handbook, Volume 2
ABCD
XXCD
ABCD
ABFF
FFCD
ABCD
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Pack Mode Support
Arria GX M4K and M-RAM memory blocks support pack mode. In M4K
and M-RAM memory blocks, you can implement two single-port
memory blocks in a single block under the following conditions:
■
■
Each of the two independent block sizes is equal to or less than half
of the M4K or M-RAM block size.
Each of the single-port memory blocks is configured in single-clock
mode.
Thus, each of the single-port memory blocks access up to half of the M4K
or M-RAM memory resources such as clock, clock enables, and
asynchronous clear signals.
1
For more information, refer to “Single-Port Mode” on page 6–10
and “Single-Clock Mode” on page 6–27.
Address Clock Enable Support
Arria GX M4K and M-RAM memory blocks support address clock
enable, which is used to hold the previous address value for as long as the
signal is enabled. When the memory blocks are configured in dual-port
mode, each port has its own independent address clock enable.
Figure 6–2 shows an address clock enable block diagram. Placed in the
address register, the address signal output by the address register is fed
back to the input of the register via a multiplexer. The multiplexer output
is selected by the address clock enable (addressstall) signal. Address
latching is enabled when the addressstall signal turns high. The
output of the address register is then continuously fed into the input of
the register; therefore, the address value can be held until the
addressstall signal turns low.
Altera Corporation
May 2008
6–7
Arria GX Device Handbook, Volume 2
TriMatrix Memory Overview
Figure 6–2. Arria GX Address Clock Enable Block Diagram
address[0]
1
0
address[N]
1
0
address[0]
register
address[0]
address[N]
register
address[N]
addressstall
clock
Address clock enable is typically used for cache memory applications,
which require one port for read and another port for write. The default
value for the address clock enable signals is low (disabled). Figures 6–3
and 6–4 show the address clock enable waveform during read and write
cycles, respectively.
Figure 6–3. Arria GX Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory)
an
q (synch) doutn-1
q (asynch)
doutn
a1
a0
doutn
dout0
6–8
Arria GX Device Handbook, Volume 2
dout0
dout1
dout1
dout1
dout1
dout1
a4
a5
dout1
dout4
dout4
dout5
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–4. Arria GX Address Clock Enable During Write Cycle Waveform
inclock
wraddress
a0
a1
a2
a3
a4
a5
a6
00
01
02
03
04
05
06
data
wren
addressstall
latched address
(inside memory)
contents at a0
an
a1
a0
XX
01
XX
contents at a3
XX
contents at a4
03
02
contents at a2
04
XX
XX
contents at a5
Memory Modes
a5
00
XX
contents at a1
a4
05
Arria GX TriMatrix memory blocks include input registers that
synchronize writes and output registers to pipeline data to improve
system performance. All TriMatrix memory blocks are fully synchronous,
meaning that all inputs are registered, but outputs can be either registered
or unregistered.
1
TriMatrix memory does not support asynchronous memory
(unregistered inputs).
Depending on which TriMatrix memory block you use, the memory has
various modes, including:
■
■
■
■
■
■
1
Altera Corporation
May 2008
Single-port
Simple dual-port
True dual-port (bidirectional dual-port)
Shift-register
ROM
FIFO
Violating the setup or hold time on the memory block address
registers could corrupt memory contents. This applies to both
read and write operations.
6–9
Arria GX Device Handbook, Volume 2
Memory Modes
Single-Port Mode
All TriMatrix memory blocks support single-port mode that supports
non-simultaneous read and write operations. Figure 6–5 shows the
single-port memory configuration for TriMatrix memory.
Figure 6–5. Single-Port Memory Note (1)
data[ ]
address[ ]
wren
byteena[]
addressstall
inclock
inclocken
q[]
outclock
outclocken
outaclr
Note to Figure 6–5:
(1)
Two single-port memory blocks can be implemented in a single M4K or M-RAM
block.
M4K and M-RAM memory blocks can also be halved and used for two
independent single-port RAM blocks. The Altera® Quartus II software
automatically uses this single-port memory packing when running low
on memory resources. To force two single-port memories into one M4K
or M-RAM block, first ensure that each of the two independent RAM
blocks is equal to or less than half the size of the M4K or M-RAM block.
Second, assign both single-port RAMs to the same M4K or M-RAM block.
In single-port RAM configuration, the outputs can only be in
read-during-write mode, which means that during the write operation,
data written to the RAM flows through to the RAM outputs. When the
output registers are bypassed, the new data is available on the rising edge
of the same clock cycle on which it was written. For more information
about read-during-write mode, refer to “Read-During-Write Operation at
the Same Address” on page 6–32.
6–10
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Table 6–7 shows the port width configurations for TriMatrix blocks in
single-port mode.
Table 6–7. Arria GX Port Width Configurations for M512, M4K, and M-RAM
Blocks (Single-Port Mode)
Port Width
Configurations
M512 Blocks
M4K Blocks
M-RAM Blocks
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Figure 6–6 shows timing waveforms for read and write operations in
single-port mode.
Figure 6–6. Arria GX Single-Port Timing Waveforms Note (1)
inclock
wren
address
an-1
an
data (1)
din-1
din
q (synch)
q (asynch)
din-2
din-1
a0
a1
a2
a3
a4
din4
din-1
din
din
dout0
dout0
dout1
dout1
dout2
dout2
dout3
a5
a6
din5
din6
dout3
din4
din4
din5
Note to Figure 6–6:
(1)
The crosses in the data waveform during read mean "don't care."
Simple Dual-Port Mode
All TriMatrix memory blocks support simple dual-port mode which
supports a simultaneous read and write operation. Figure 6–7 shows the
simple dual-port memory configuration for TriMatrix memory.
Altera Corporation
May 2008
6–11
Arria GX Device Handbook, Volume 2
Memory Modes
Figure 6–7. Arria GX Simple Dual-Port Memory Note (1)
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
rdaddress[ ]
rden
q[ ]
rd_addressstall
rdclock
rdclocken
rd_aclr
Note to Figure 6–7:
(1)
Simple dual-port RAM supports input and output clock mode in addition to the
read and write clock mode shown.
TriMatrix memory supports mixed-width configurations, allowing
different read and write port widths. Tables 6–8 through 6–10 show
mixed-width configurations for M512, M4K, and M-RAM blocks,
respectively.
Table 6–8. Arria GX M512 Block Mixed-Width Configurations (Simple
Dual-Port Mode)
Write Port
Read Port
512 × 1 256 × 2 128 × 4
64 × 8
32 × 16
64 × 9
32 × 18
64 × 9
v
v
32 × 18
v
v
512 × 1
v
v
v
v
v
256 × 2
v
v
v
v
v
128 × 4
v
v
v
v
v
64 × 8
v
v
v
v
v
32 × 16
v
v
v
v
v
Table 6–9. Arria GX M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Write Port
Read Port
4K × 1
2K × 2
1K × 4
4K × 1
v
v
v
v
v
v
2K × 2
v
v
v
v
v
v
6–12
Arria GX Device Handbook, Volume 2
512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Table 6–9. Arria GX M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Write Port
Read Port
4K × 1
2K × 2
1K × 4
512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
1K × 4
v
v
v
v
v
v
512 × 8
v
v
v
v
v
v
256 × 16
v
v
v
v
v
v
128 × 32
v
v
v
v
v
v
512 × 9
v
v
v
256 × 18
v
v
v
128 × 36
v
v
v
Table 6–10. Arria GX M-RAM Block Mixed-Width Configurations (Simple
Dual-Port Mode)
Write Port
Read Port
64K × 9
32K × 18
18K × 36
8K × 72
64K × 9
v
v
v
v
32K × 18
v
v
v
v
18K × 36
v
v
v
v
8K × 72
v
v
v
v
4K × 144
4K × 144
v
In simple dual-port mode, M512 and M4K blocks have one write enable
and one read enable signal. However, M-RAM blocks contain only a write
enable signal, which is held high to perform a write operation. M-RAM
blocks are always enabled for read operations. The Quartus II software
can emulate a read-enable signal for M-RAM blocks by using the
clock-enable signal if it is not already used. If the read address and write
address select the same address location during a write operation,
M-RAM block output is unknown.
TriMatrix memory blocks do not support a clear port on the write enable
and read enable registers. When the read enable is deactivated, the
current data is retained at the output ports. If the read enable is activated
during a write operation with the same address location selected, the
Altera Corporation
May 2008
6–13
Arria GX Device Handbook, Volume 2
Memory Modes
simple dual-port RAM output is either unknown or can be set to output
the old data stored at the memory address. For more information, refer to
“Read-During-Write Operation at the Same Address” on page 6–32.
Figure 6–8 shows timing waveforms for read and write operations in
simple dual-port mode.
Figure 6–8. Arria GX Simple Dual-Port Timing Waveforms Notes (1), (2)
wrclock
wren
wraddress
an-1
data (1)
din-1
a0
an
a1
a2
din
a3
a4
a5
din4
din5
a6
din6
rdclock
rden (2)
rdaddress
bn
q (synch) doutn-2
q (asynch)
doutn-1
b1
b0
doutn-1
b3
dout0
doutn
doutn
b2
dout0
Notes to Figure 6–8:
(1)
(2)
The crosses in the data waveform during read mean "don't care."
The read enable rden signal is not available in M-RAM blocks. The M-RAM block in simple dual-port mode always
reads out the data stored at the current read address location.
True Dual-Port Mode
Arria GX M4K and M-RAM memory blocks support true dual-port
mode. True dual-port mode supports any combination of two-port
operations: two reads, two writes, or one read and one write at two
different clock frequencies. Figure 6–9 shows Arria GX true dual-port
memory configuration.
6–14
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–9. Arria GX True Dual-Port Memory Note (1)
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clock_a
enable_a
aclr_a
q_a[]
data_b[ ]
address_b[]
wren_b
byteena_b[]
addressstall_b
clock_b
enable_b
aclr_b
q_b[]
Note to Figure 6–9:
(1)
True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
The widest bit configuration of the M4K and M-RAM blocks in true
dual-port mode is as follows:
■
■
256 × 16-bit (×18-bit with parity) (M4K)
8K × 64-bit (×72-bit with parity) (M-RAM)
The 128 × 32-bit (×36-bit with parity) configuration of the M4K block and
the 4K × 128-bit (×144-bit with parity) configuration of the M-RAM block
are unavailable because the number of output drivers is equivalent to the
maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, the maximum width of the true
dual-port RAM equals half of the total number of output drivers.
Table 6–11 lists the possible M4K block mixed-port width configurations.
Table 6–11. Arria GX M4K Block Mixed-Port Width Configurations (True Dual-Port)
Write Port
Read Port
4K × 1
2K × 2
1K × 4
512 × 8
256 × 16
512 × 9
256 × 18
4K × 1
v
v
v
v
v
2K × 2
v
v
v
v
v
1K × 4
v
v
v
v
v
512 × 8
v
v
v
v
v
256 × 16
v
v
v
v
v
512 × 9
v
v
256 × 18
v
v
Altera Corporation
May 2008
6–15
Arria GX Device Handbook, Volume 2
Memory Modes
Table 6–12 lists the possible M-RAM block mixed-port width
configurations.
Table 6–12. Arria GX M-RAM Block Mixed-Port Width Configurations (True
Dual-Port)
Write Port
Read Port
64K × 9
32K × 18
18K × 36
8K × 72
64K × 9
v
v
v
v
32K × 18
v
v
v
v
18K × 36
v
v
v
v
8K × 72
v
v
v
v
In true dual-port configuration, the RAM outputs can only be configured
for read-during-write mode. This means that during write operation,
data being written to the A or B port of the RAM flows through to the A
or B outputs, respectively. When the output registers are bypassed, the
new data is available on the rising edge of the same clock cycle on which
it was written. For waveforms and information on mixed-port
read-during-write mode, refer to “Read-During-Write Operation at the
Same Address” on page 6–32.
Potential write contentions must be resolved external to the RAM because
writing to the same address location at both ports results in unknown
data storage at that location. For a valid write operation to the same
address of the M-RAM block, the rising edge of the write clock for port A
must occur following the maximum write cycle time interval after the
rising edge of the write clock for port B. Data is written on the rising edge
of the write clock for the M-RAM block.
Because data is written into the M512 and M4K blocks at the falling edge
of the write clock, the rising edge of the write clock for port A should
occur following half of the maximum write cycle time interval after the
falling edge of the write clock for port B. If this timing is not met, the data
stored in that particular address will be invalid.
1
6–16
Arria GX Device Handbook, Volume 2
For the maximum synchronous write cycle time, refer to the
Arria GX Device Family Data Sheet in volume 1 of the
Arria GX Device Handbook.
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–10 shows true dual-port timing waveforms for the write
operation at port A and the read operation at port B.
Figure 6–10. Arria GX True Dual-Port Timing Waveforms Note (1)
clk_a
wren_a
address_a
an-1
an
data_a (1)
din-1
din
din-2
q_a (synch)
q_a (asynch)
a0
din-1
din-1
din
a1
a2
dout0
din
dout0
dout1
a3
a4
a5
a6
din4
din5
din6
dout2
dout1
dout2
dout3
din4
dout3
din5
din4
clk_b
wren_b
address_b
bn
q_b (synch)
doutn-2
q_b (asynch)
doutn-1
b1
b0
doutn-1
doutn
doutn
dout0
b2
dout0
b3
dout1
dout1
dout2
Note to Figure 6–10:
(1)
The crosses in the data_a waveform during write mean "don't care."
Shift-Register Mode
All Arria GX memory blocks support shift-register mode.
Embedded memory block configurations can implement shift registers
for digital signal processing (DSP) applications, such as finite impulse
response (FIR) filters, pseudo-random number generators, multi-channel
filtering, and auto-correlation and cross-correlation functions. These and
other DSP applications require local data storage, traditionally
implemented with standard flip flops that quickly exhaust many logic
cells for large shift registers. A more efficient alternative is to use
embedded memory as a shift-register block, which saves logic cell and
routing resources.
The size of a (w m n) shift register is determined by the input data width
(w), the length of the taps (m), and the number of taps (n), and must be
less than or equal to the maximum number of memory bits in the
respective block: 576 bits for the M512 block, 4,608 bits for the M4K block,
and 589,824 bits for the MRAM block. In addition, the size of w n must be
less than or equal to the maximum width of the respective block: 18 bits
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Memory Modes
for the M512 block, 36 bits for the M4K block, and 144 bits for the MRAM
block. If a larger shift register is required, the memory blocks can be
cascaded.
In M512 and M4K blocks, data is written into each address location at the
falling edge of the clock and read from the address at the rising edge of
the clock. Shift-register mode logic automatically controls the positive
and negative edge clocking to shift the data in one clock cycle. The
MRAM block performs reads and writes on the rising edge. Figure 6–11
shows the TriMatrix memory block in the shift-register mode.
Figure 6–11. Arria GX Shift-Register Memory Configuration
w × m × n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
n Number of Taps
m-Bit Shift Register
W
W
m-Bit Shift Register
W
6–18
Arria GX Device Handbook, Volume 2
W
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
ROM Mode
M512 and M4K memory blocks support ROM mode. A memory
initialization file (.mif) initializes the ROM contents of these blocks. The
address lines of the ROM are registered. The outputs can be registered or
unregistered. The ROM read operation is identical to the read operation
in the single-port RAM configuration.
FIFO Buffers Mode
TriMatrix memory blocks support FIFO mode. M512 memory blocks are
ideal for designs with many shallow FIFO buffers. All memory
configurations have synchronous inputs; however, the FIFO buffer
outputs are always combinational. Simultaneous read and write from an
empty FIFO buffer is not supported.
f
Clock Modes
For more information about FIFO buffers, refer to the Single- and DualClock FIFO Megafunctions User Guide and FIFO Partitioner Megafunction
User Guide.
Depending on which TriMatrix memory mode you select, the following
clock modes are available:
■
■
■
■
Independent
Input and output
Read and write
Single-clock
Table 6–13 shows these clock modes supported by all TriMatrix blocks
when configured as respective memory modes.
Table 6–13. Arria GX TriMatrix Memory Clock Modes
Clocking Modes
True Dual-Port
Mode
Independent
v
Input/output
v
Altera Corporation
May 2008
v
v
v
Read/write
Single clock
Simple Dual-Port
Single-Port Mode
Mode
v
v
v
6–19
Arria GX Device Handbook, Volume 2
Clock Modes
Independent Clock Mode
TriMatrix memory blocks can implement independent clock mode for
true dual-port memory. In this mode, a separate clock is available for each
port (A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port also supports
independent clock enables for port A and B registers. Asynchronous clear
signals for the registers; however, are not supported.
Figure 6–12 shows a TriMatrix memory block in independent clock mode.
6–20
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
(1)
Altera Corporation
May 2008
clock_a
enable_a
wren_a
addressstall_a
address_a[ ]
byteena_a[ ]
data_a[ ]
6
ENA
D
ENA
D
ENA
D
ENA
D
6 LAB Row Clocks
Q
Q
Q
Q
Write
Pulse
Generator
Q
Data Out
Write/Read
Enable
Data In
B
q_a[ ] q_b[ ]
Q
D
ENA
Data Out
Write/Read
Enable
Address Clock
Enable B
Address B
Byte Enable B
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Address Clock
Enable A
Address A
ENA
D
A
Byte Enable A
Data In
Write
Pulse
Generator
Q
Q
Q
Q
D
ENA
ENA
D
ENA
D
ENA
D
6
clock_b
enable_b
wren_b
addressstall_b
address_b[ ]
byteena_b[ ]
data_b[ ]
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–12. Arria GX TriMatrix Memory Block in Independent Clock Mode
Note (1)
Note to Figure 6–12:
Violating the setup or hold time on the memory block address registers could
corrupt the memory contents. This applies to both read and write operations.
6–21
Arria GX Device Handbook, Volume 2
Clock Modes
Input and Output Clock Mode
Arria GX TriMatrix memory blocks can implement input and output
clock mode for true and simple dual-port memory. On each of the two
ports, A and B, one clock controls all registers for the following inputs
into the memory block: data input, write enable, and address. The other
clock controls the blocks’ data output registers. Each memory block port
also supports independent clock enables for input and output registers.
Asynchronous clear signals for the registers; however, are not supported.
Figures 6–13 through 6–15 show the memory block in input and output
clock mode for true dual-port, simple dual-port, and single-port modes,
respectively.
6–22
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
(1)
Altera Corporation
May 2008
inclock
inclocken
wren_a
addressstall_a
address_a[ ]
byteena_a[ ]
data_a[ ]
6
ENA
D
ENA
D
ENA
D
ENA
D
6 LAB Row Clocks
Q
Q
Q
Q
Write
Pulse
Generator
Q
Data Out
Write/Read
Enable
Data In
B
q_a[ ] q_b[ ]
Q
D
ENA
Data Out
Write/Read
Enable
Address Clock
Enable B
Address B
Byte Enable B
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Address Clock
Enable A
Address A
ENA
D
A
Byte Enable A
Data In
Write
Pulse
Generator
Q
Q
Q
Q
ENA
D
ENA
D
ENA
D
ENA
D
6
outclock
outclocken
wren_b
addressstall_b
address_b[ ]
byteena_b[ ]
data_b[ ]
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–13. Arria GX Input/Output Clock Mode in True Dual-Port Mode
Note (1)
Note to Figure 6–13:
Violating the setup or hold time on the memory block address registers could
corrupt the memory contents. This applies to both read and write operations.
6–23
Arria GX Device Handbook, Volume 2
Clock Modes
Figure 6–14. Arria GX Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2), (3)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
rdaddress[ ]
D
Q
ENA
Read Address
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
wraddress[ ]
D
Q
ENA
Write Address
rd_addressstall
Read Address
Clock Enable
wr_addressstall
Write Address
Clock Enable
D
Q
ENA
To MultiTrack
Interconnect (3)
rden (2)
Read Enable
D
Q
ENA
wren
Write Enable
outclocken
inclocken
inclock
D
Q
ENA
Write
Pulse
Generator
outclock
Notes to Figure 6–14:
(1)
(2)
(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading out the data stored at the current read address location.
For more information about the MultiTrack interconnect, refer to the Arria GX Device Family Data Sheet in volume 1
of the Arria GX Device Handbook.
6–24
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–15. Arria GX Input/Output Clock Mode in Single-Port Mode Notes (1), (2)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
address[ ]
D
Q
ENA
Address
Data Out
byteena[ ]
Byte Enable
D
Q
ENA
D
Q
ENA
To MultiTrack
Interconnect (2)
Address
Clock Enable
addressstall
wren
Write Enable
outclocken
inclocken
inclock
D
Q
ENA
Write
Pulse
Generator
outclock
Notes to Figure 6–15:
(1)
(2)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
For more information about the MultiTrack interconnect, refer to the Arria GX Device Family Data Sheet in volume 1
of the Arria GX Device Handbook.
Read and Write Clock Mode
Arria GX TriMatrix memory blocks can implement read and write clock
mode for simple dual-port memory. This mode uses up to two clocks. The
write clock controls the blocks’ data inputs, write address, and write
enable signals. The read clock controls the data output, read address, and
read-enable signals. The memory blocks support independent clock
enables for each clock for the read- and write-side registers. However,
asynchronous clear signals for the registers are not supported.
Figure 6–16 shows a memory block in read and write clock mode.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Clock Modes
Figure 6–16. ArriaGX Read and Write Clock Mode Notes (1), (2), (3)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
rdaddress[ ]
D
Q
ENA
Read Address
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
wraddress[ ]
D
Q
ENA
Write Address
rd_addressstall
Read Address
Clock Enable
wr_addressstall
Write Address
Clock Enable
D
Q
ENA
To MultiTrack
Interconnect (3)
rden (2)
Read Enable
D
Q
ENA
wren
Write Enable
rdclocken
wrclocken
wrclock
D
Q
ENA
Write
Pulse
Generator
rdclock
Notes to Figure 6–16:
(1)
(2)
(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading the data stored at the current read address location.
For more information about the MultiTrack interconnect, refer to the Arria GX Device Family Data Sheet in volume 1
of the Arria GX Device Handbook.
6–26
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Single-Clock Mode
Arria GX TriMatrix memory blocks implement single-clock mode for true
dual-port, simple dual-port, and single-port memory. In this mode, a
single clock, together with clock enable, is used to control all registers of
the memory block. However, asynchronous clear signals for the registers
are not supported. Figures 6–17 through 6–19 show the memory block in
single-clock mode for true dual-port, simple dual-port, and single-port
modes, respectively.
Altera Corporation
May 2008
6–27
Arria GX Device Handbook, Volume 2
(1)
6–28
Arria GX Device Handbook, Volume 2
clock
enable
wren_a
addressstall_a
address_a[ ]
byteena_a[ ]
data_a[ ]
6
ENA
D
ENA
D
ENA
D
ENA
D
6 LAB Row Clocks
Q
Q
Q
Q
Write
Pulse
Generator
Q
Data Out
Write/Read
Enable
Data In
B
q_a[ ] q_b[ ]
Q
D
ENA
Data Out
Write/Read
Enable
Address Clock
Enable B
Address B
Byte Enable B
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Address Clock
Enable A
Address A
ENA
D
A
Byte Enable A
Data In
Write
Pulse
Generator
Q
Q
Q
Q
ENA
D
ENA
D
ENA
D
ENA
D
6
wren_b
addressstall_b
address_b[ ]
byteena_b[ ]
data_b[ ]
Clock Modes
Figure 6–17. ArriaGX Single-Clock Mode in True Dual-Port Mode Note (1)
Note to Figure 6–17:
Violating the setup or hold time on the memory block address registers could
corrupt the memory contents. This applies to both read and write operations.
Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–18. ArriaGX Single-Clock Mode in Simple Dual-Port Mode Note (1), (2), (3)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
rdaddress[ ]
D
Q
ENA
Read Address
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
wraddress[ ]
D
Q
ENA
Write Address
rd_addressstall
Read Address
Clock Enable
wr_addressstall
Write Address
Clock Enable
D
Q
ENA
To MultiTrack
Interconnect (3)
rden (2)
Read Enable
D
Q
ENA
wren
Write Enable
enable
clock
D
Q
ENA
Write
Pulse
Generator
Notes to Figure 6–18:
(1)
(2)
(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is
always reading the data stored at the current read address location.
For more information about the MultiTrack interconnect, refer to the Arria GX Device Family Data Sheet in volume 1
of the Arria GX Device Handbook.
Altera Corporation
May 2008
6–29
Arria GX Device Handbook, Volume 2
Designing With TriMatrix Memory
Figure 6–19. Figure7–19.ArriaGX Single-Clock Mode in Single-Port Mode Note (1), (2)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
address[ ]
D
Q
ENA
Address
Data Out
byteena[ ]
Byte Enable
D
Q
ENA
D
Q
ENA
To MultiTrack
Interconnect (2)
Address
Clock Enable
addressstall
wren
Write Enable
D
Q
ENA
enable
clock
Write
Pulse
Generator
Notes to Figure 6–19:
(1)
(2)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
For more information about the MultiTrack interconnect, refer to the Arria GX Device Family Data Sheet in volume 1
of the Arria GX Device Handbook.
Designing With
TriMatrix
Memory
When instantiating TriMatrix memory, it is important to understand the
features that set it apart from other memory architectures. The following
sections describe the unique attributes and functionality of TriMatrix
memory.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions user-defined memory
into embedded memory blocks using the most efficient size
combinations. The memory can also be manually assigned to a specific
block size or a mixture of block sizes. Table 6–1 on page 6–2 is a guide for
selecting a TriMatrix memory block size based on supported features.
6–30
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Altera Corporation
May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
f
For more information about selecting the appropriate memory block,
refer to AN 207: TriMatrix Memory Selection Using the Quartus II Software.
Synchronous and Pseudo-Asynchronous Modes
TriMatrix memory architecture implements synchronous RAM by
registering the input and output signals to the RAM block. The inputs to
all TriMatrix memory blocks are registered providing synchronous write
cycles, while the output registers can be bypassed. In a synchronous
operation, RAM generates its own self-timed strobe write-enable signal
derived from the global or regional clock. In contrast, a circuit using an
asynchronous RAM must generate the RAM write enable signal while
ensuring that its data and address signals meet setup and hold time
specifications relative to the write enable signal. During a synchronous
operation, the RAM is used in pipelined mode (inputs and outputs
registered) or flow-through mode (only inputs registered). However, in
an asynchronous memory, neither the input nor the output is registered.
While Arria GX devices do not support asynchronous memory, they do
support a pseudo-asynchronous read where the output data is available
during the clock cycle when the read address is driven into it.
Pseudo-asynchronous reading is possible in the simple and true
dual-port modes of the M512 and M4K blocks by clocking the read-enable
and read-address registers on the negative clock edge and bypassing the
output registers.
f
For more information, refer to AN 210: Converting Memory from
Asynchronous to Synchronous for Stratix & Stratix GX Designs.
Power-Up Conditions & Memory Initialization
Upon power up, TriMatrix memory is in an idle state. The M512 and M4K
block outputs always power up to zero, regardless of whether the output
registers are used or bypassed. Even if a MIF (.mif) is used to pre-load the
contents of the RAM block, the outputs will still power up as cleared. For
example, if address 0 is pre-initialized to FF, the M512 and M4K blocks
power up with the output at 00.
M-RAM blocks do not support .mif files; therefore, they cannot be
pre-loaded with data upon power up. M-RAM blocks asynchronous
outputs and memory controls always power up to an unknown state. If
M-RAM block outputs are registered, the registers power up as cleared.
When a read is performed immediately after power up, the output from
the read operation is undefined since the M-RAM contents are not
initialized. The read operation continues to be undefined for a given
address until a write operation is performed for that address.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Read-During-Write Operation at the Same Address
Read-DuringWrite Operation
at the Same
Address
The “Same-Port Read-During-Write Mode” and “Mixed-Port ReadDuring-Write Mode” sections describe the functionality of the various
RAM configurations when reading from an address during a write
operation at that same address. There are two read-during-write data
flows: same-port and mixed-port. Figure 6–20 shows the difference
between these flows.
Figure 6–20. ArriaGX Read-During-Write Data Flow
Port A
data in
Port B
data in
Mixed-port
data flow
Same-port
data flow
Port A
data out
Port B
data out
Same-Port Read-During-Write Mode
For a read-during-write operation of a single-port RAM or the same port
of a true dual-port RAM, the new data is available on the rising edge of
the same clock cycle on which it was written. This behavior is valid on all
memory block sizes. Figure 6–21 shows a sample functional waveform.
When using byte enables in true dual-port RAM mode, the outputs for
the masked bytes on the same port are unknown (refer to Figure 6–1 on
page 6–6). The non-masked bytes are read out, as shown in Figure 6–21.
6–32
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May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Figure 6–21. Arria GX Same-Port Read-During-Write Functionality Note (1)
inclock
data
A
B
wren
q Old
A
Note to Figure 6–21:
(1)
Outputs are not registered.
Mixed-Port Read-During-Write Mode
This mode is used when a RAM in simple or true dual-port mode has one
port reading and the other port writing to the same address location with
the same clock.
The READ_DURING_WRITE_MODE_MIXED_PORTS parameter for M512
and M4K memory blocks determines whether to output the old data at
the address or a "don’t care" value. Setting this parameter to OLD_DATA
outputs the old data at that address. Setting this parameter to DONT_CARE
outputs a "don’t care" or unknown value. Figures 6–22 and 6–23 show
sample functional waveforms where both ports have the same address.
These figures assume that the outputs are not registered.
The DONT_CARE setting allows memory implementation in any TriMatrix
memory block, whereas the OLD_DATA setting restricts memory
implementation to only M512 or M4K memory blocks. Selecting
DONT_CARE gives the compiler more flexibility when placing memory
functions into TriMatrix memory.
The RAM outputs are unknown for a mixed-port read-during-write
operation of the same address location of an M-RAM block, as shown in
Figure 6–23.
Altera Corporation
May 2008
6–33
Arria GX Device Handbook, Volume 2
Conclusion
Figure 6–22. Arria GX Mixed-Port Read-During-Write: OLD_DATA
inclock
address_a and
address_b
data_a
Address Q
A
B
wren_a
wren_b
q_b
Old
A
B
Figure 6–23. Arria GX Mixed-Port Read-During-Write: DONT_CARE
inclock
address_a and
address_b
data_a
Address Q
A
B
wren_a
wren_b
q_b
Unknown
B
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value is unknown during a
mixed-port read-during-write operation.
Conclusion
The TriMatrix memory structure of Arria GX devices provides an
enhanced RAM architecture with high memory bandwidth. It addresses
the needs of different memory applications in FPGA designs with
features such as different memory block sizes and modes, byte enables,
parity bit storage, address clock enables, mixed clock mode, shift register
mode, mixed-port width support, and true dual-port mode.
6–34
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May 2008
TriMatrix Embedded Memory Blocks in Arria GX Devices
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
Document
Revision History
AN 207: TriMatrix Memory Selection Using the Quartus II Software
AN 210: Converting Memory from Asynchronous to Synchronous for
Stratix & Stratix GX Designs
Arria GX Device Family Data Sheet in volume 1 of the Arria GX Device
Handbook
FIFO Partitioner Megafunction User Guide
Single- and Dual-Clock FIFO Megafunctions User Guide
Table 6–14 shows the revision history for this chapter.
Table 6–14. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
May 2008,
v1.2
Updated the “Introduction” section.
Minor text edits.
—
August 2007,
v1.1
Added the “Referenced Documents” section.
—
May 2007,
v1.0
Initial release.
—
Altera Corporation
May 2008
—
6–35
Arria GX Device Handbook, Volume 2
Document Revision History
6–36
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
7. External Memory
Interfaces in Arria GX Devices
AGX52007-1.2
Introduction
ArriaTM GX devices support external memory interfaces, including DDR
SDRAM, DDR2 SDRAM, and SDR SDRAM. Its dedicated phase-shift
circuitry allows the Arria GX device to interface with an external memory
at twice the system clock speed (up to 233 MHz/466 megabits per second
(Mbps) with DDR2 SDRAM). In addition to external memory interfaces,
you can also use the dedicated phase-shift circuitry for other applications
that require a shifted input clock signal.
Most new memory architectures use a DDR I/O interface. Although
Arria GX devices also support the mature and well established SDR
external memory, this chapter focuses on DDR memory standards. These
DDR memory standards cover a broad range of applications for
embedded processor systems, image processing, storage,
communications, and networking.
Arria GX devices offer external memory support in top and bottom I/O
banks. Figure 7–1 shows Arria GX device memory support.
1
If your system requires memory interface support, you must use
the ALTMEMPHY megafunction.
This chapter contains the following sections:
■
■
■
Altera Corporation
May 2008
“External Memory Standards” on page 7–3
“Arria GX DDR Memory Support Overview” on page 7–7
“Conclusion” on page 7–26
7–1
External Memory Interfaces in Arria GX Devices
Figure 7–1. External Memory Support
DQS8T
VREF0B3
DQS7T
VREF1B3
DQS6T
VREF2B3
VREF3B3
DQS5T
VREF4B3
PLL11
PLL5
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL7
Bank 4
Bank 2
Supports DLL-Based Implementation
VREF 0B2
VR EF1B2
VR EF2B2
VR EF3B 2
VREF 4B2
Bank 3
PLL1
Bank 1
Supports DLL-Based Implementation
VREF 0B1
VREF 1B1
VREF 2B1
VR EF3B1
VR EF4B1
PLL2
Bank 8
Bank 12
Bank 10
PLL12
PLL6
Bank 7
PLL8
VREF4B8
DQS8B
VREF3B8
VREF2B8
DQS7B
VREF1B8
DQS6B
VREF0B8
DQS5B
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Notes to Figure 7–1:
(1)
(2)
For more information about the ALTMEMPHY megafunction data path, refer to the ALTMEMPHY Megafunction
User Guide.
EP1AGX20/35 and EP1AGX50/60 devices in the F484 package support external memory interfaces in the top I/O
banks only.
7–2
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Altera Corporation
May 2008
External Memory Standards
Table 7–1 summarizes the maximum clock rate Arria GX devices support
with external memory devices.
Table 7–1. Arria GX Maximum Clock Rate Support for External Memory
Interfaces Notes (1), (2)
Memory Standards
–6 Speed Grade (MHz)
DDR2 SDRAM (3), (4)
233
DDR SDRAM (3), (4)
200
Notes to Table 7–1:
(1)
(2)
Memory interface timing specifications are dependent on the memory, board,
physical interface, and core logic. Refer to each memory interface application note
for more details about how each specification is generated.
Numbers are preliminary until characterization is final. The timing information
(3)
(4)
featured in the Quartus® II software version 7.1 was used to define these clock
rates.
This applies to interfaces with both modules and components.
These memory interfaces are supported using the ALTMEMPHY megafunction.
This chapter describes the hardware features in Arria GX devices that
facilitate high-speed memory interfacing for each DDR memory
standard.
External
Memory
Standards
The following sections briefly describe external memory standards
supported by Arria GX devices. Altera® offers a complete solution for
these memories, including clear-text data path, memory controller, and
timing analysis.
DDR and DDR2 SDRAM
DDR SDRAM is a memory architecture that transmits and receives data
at twice the clock speed. These devices transfer data on both the rising
and falling edges of the clock signal. DDR2 SDRAM is a
second-generation memory based on the DDR SDRAM architecture. It
transfers data to Arria GX devices at up to 233 MHz/466 Mbps. Arria GX
devices can support DDR SDRAM at up to 200 MHz/400 Mbps.
Interface Pins
DDR and DDR2 SDRAM devices use interface pins such as data (DQ),
data strobe (DQS), clock, command, and address pins. Data is sent and
captured at twice the system clock rate by transferring data on the clock’s
positive and negative edges. The commands and addresses still use only
one active (positive) edge of a clock. DDR and DDR2 SDRAM use
single-ended data strobes (DQS). DDR2 SDRAM can also use optional
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May 2008
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External Memory Interfaces in Arria GX Devices
differential data strobes (DQS and DQS#). However, Arria GX devices do
not support the optional differential data strobes for DDR2 SDRAM
interfaces. You can leave the DDR SDRAM memory DQS# pin
unconnected. Only the shifted DQS signal from the DQS logic block is
used to capture data.
DDR and DDR2 SDRAM ×16 devices use two DQS pins. Each DQS pin is
associated with eight DQ pins. However, this is not the same as the
×16/×18 mode in Arria GX devices (see “Data and Data Strobe Pins” on
page 7–8). To support a ×16 DDR2 SDRAM device, you need to configure
Arria GX devices to use two sets of DQ pins in ×8/×9 mode. Similarly, if
your ×32 memory device uses four DQS pins, where each DQS pin is
associated with eight DQ pins, you need to configure the Arria GX
devices to use four sets of DQS/DQ groups in ×8/×9 mode.
Connect the memory device’s DQ and DQS pins to Arria GX DQ and
DQS pins, respectively, as listed in the Arria GX pin tables. DDR and
DDR2 SDRAM also use active-high data mask, DM, and pins for writes.
You can connect the memory’s DM pins to any of Arria GX I/O pins in
the same bank as the DQ pins of the FPGA. There is one DM pin per
DQS/DQ group in a DDR or DDR2 SDRAM device.
f
For more information about interfacing with DDR SDRAM, refer to AN
327: Interfacing DDR SDRAM with Stratix II Devices and AN 328:
Interfacing DDR2 SDRAM with Stratix II Devices.
You can use any of the user I/O pins for commands and addresses to the
DDR and DDR2 SDRAM. You may need to generate these signals from
the system clock’s negative edge.
The clocks to the SDRAM device are called CK and CK# pins. Use any of
the user I/O pins via the DDR registers to generate the CK and CK#
signals to meet the DDR SDRAM or DDR2 SDRAM device’s tDQSS
requirement. The memory device’s tDQSS specification requires that the
write DQS signal’s positive edge must be within 25% of the positive edge
of the DDR SDRAM or DDR2 SDRAM clock input. Using regular I/O
pins for CK and CK# also ensures that any PVT variations on the DQS
signals are tracked the same way by these CK and CK# pins. Figure 7–2
shows a diagram that illustrates how to generate these clocks.
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Altera Corporation
May 2008
External Memory Standards
Figure 7–2. Clock Generation for External Memory Interfaces in Arria GX Devices
VCC
LE
IOE
GND
D
Q
D
Q
D
Q
D
Q
VCC
CK (1)
VCC
GND
VCC
CK# (1)
clk
Note to Figure 7–2:
(1)
CK and CK# are the clocks to the memory devices.
Read and Write Operations
When reading from the memory, DDR and DDR2 SDRAM devices send
the data edge-aligned with respect to the data strobe. To properly read the
data in, the data strobe needs to be center-aligned with respect to the data
inside the FPGA. Arria GX devices feature dedicated circuitry to shift this
data strobe to the middle of the data window. Figure 7–3 shows an
example of how the memory sends out the data and data strobe for a
burst-of-two operation.
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May 2008
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External Memory Interfaces in Arria GX Devices
Figure 7–3. Example of a 90o Shift on the DQS Signal Notes (1), (2)
DQS pin to
register delay
DQS at
FPGA pin
Preamble
Postamble
DQ at
FPGA pin
90˚ degree (3)
DQS at
IOE registers
DQ at
IOE registers
DQ pin to
register delay
Notes to Figure 7–3:
(1)
(2)
DDR2 SDRAM does not support a burst length of two.
The phase shift required for your system should be based on your timing analysis and may not be 90o.
During write operations to a DDR or DDR2 SDRAM device, the FPGA
needs to send the data to the memory center-aligned with respect to the
data strobe. Arria GX devices use a PLL to center-align the data by
generating a 0o phase-shifted system clock for the write data strobes and
a –90o phase-shifted write clock for the write data pins for DDR and
DDR2 SDRAM. Figure 7–4 shows an example of the relationship between
the data and data strobe during a burst-of-four write.
Figure 7–4. DQ and DQS Relationship During a DDR and DDR2 SDRAM Write Note (1)
DQS at
FPGA Pin
DQ at
FPGA Pin
Note to Figure 7–4:
(1)
This example shows a write for a burst length of two. DDR SDRAM devices do not support burst lengths of two.
7–6
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May 2008
Arria GX DDR Memory Support Overview
f
Arria GX DDR
Memory Support
Overview
For more information about DDR SDRAM and DDR2 SDRAM
specifications, refer to the JEDEC standard publications JESD79C and
JESD79-2, respectively, at www.jedec.org.
This section describes Arria GX features that enable high-speed memory
interfacing. It first describes Arria GX memory pins and then DQS
phase-shift circuitry and DDR I/O registers. Table 7–2 shows the I/O
standard associated with the external memory interfaces.
Table 7–2. External Memory Support in Arria GX Devices
Memory Standard
I/O Standard
DDR2 SDRAM
SSTL-18 Class II (1)
DDR SDRAM
SSTL-2 Class II
Note to Table 7–2:
(1)
Arria GX devices support 1.8-V HSTL/SSTL-18 Class I and II I/O standards in
I/O banks 3, 4, 7, and 8.
Arria GX devices support data strobe or read clock signal (DQS) used in
DDR SDRAM and DDR2 SDRAM devices with dedicated circuitry.
f
For more information about memory interfaces, see the appropriate
Stratix II or Stratix II GX memory interfaces application note available at
www.altera.com.
Arria GX devices contain dedicated circuitry to shift incoming DQS
signals by 0o, 22.5o, 30o, 36o, 45o, 60o, 67.5o, 72o, 90o, 108o, 120o, or 144o,
depending on the delay-locked loop (DLL) mode. There are four DLL
modes. The DQS phase-shift circuitry uses a frequency reference to
dynamically generate control signals for the delay chains in each of the
DQS pins, allowing it to compensate for process, voltage, and
temperature (PVT) variations. This phase-shift circuitry has been
enhanced in Arria GX devices to support more phase-shift options with
less jitter.
Besides DQS dedicated phase-shift circuitry, each DQS pin has its own
DQS logic block that sets the delay for the signal input to the pin. Using
DQS dedicated phase-shift circuitry with the DQS logic block allows for
phase-shift fine-tuning. Additionally, every IOE in an Arria GX device
contains six registers and one latch to achieve DDR operation.
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May 2008
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External Memory Interfaces in Arria GX Devices
DDR Memory Interface Pins
Arria GX devices use data (DQ), data strobe (DQS), and clock pins to
interface with external memory.
Figure 7–5 shows DQ and DQS pins in the Arria GX I/O banks on the top
of the device. A similar arrangement is repeated at the bottom of the
device.
Figure 7–5. DQ and DQS Pins Per I/O Bank
Up to 8 Sets of
DQ & DQS Pins
Up to 10 Sets of
DQ & DQS Pins
DQ
Pins
DQ
Pins
I/O
Bank 3
DQS
Pin
PLL 11
PLL 5
I/O
Bank 11
I/O
Bank 9
DQS
Pin
DQS
Phase
Shift
Circuitry
I/O
Bank 4
DQS
Pin
DQS
Pin
Data and Data Strobe Pins
Arria GX data pins for DDR memory interfaces are called DQ pins.
Arria GX devices can use either bidirectional data strobes or
unidirectional read clocks. Depending on the external memory interface,
either the memory device’s read data strobes or read clocks feed the
Arria GX DQS pins.
Arria GX DQS pins connect to the DQS pins in DDR and DDR2 SDRAM
interfaces. In every Arria GX device, the I/O banks at the top (I/O banks
3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR
memory up to 233 MHz/466 Mbps (with DDR2). These I/O banks
support DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or
×32/×36.
In ×4 mode, each DQS pin drives up to four DQ pins within that group.
In ×8/×9 mode, each DQS pin drives up to nine DQ pins within that
group to support one parity bit and eight data bits. If the parity bit or any
data bit is not used, you can use the extra DQ pins as regular user I/O
pins. Similarly, with ×16/×18 and ×32/×36 modes, each DQS pin drives
up to 18 and 36 DQ pins, respectively. There are two parity bits in the
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May 2008
Arria GX DDR Memory Support Overview
×16/×18 mode and four parity bits in the ×32/×36 mode. Table 7–3 shows
the number of DQS/DQ groups supported in each Arria GX package for
DLL-based implementations.
Table 7–3. Arria GX DQS and DQ Bus Mode Support Note (1)
Number of
×4 Groups
Number of
×8/×9 Groups
484-pin FineLine BGA
2
0
0
0
780-pin FineLine BGA
18
8
4
0
1,152-pin FineLine BGA
36
18
8
4
Package
Number of ×16/ Number of ×32/
×18 Groups
×36 Groups
Note to Table 7–3:
(1)
Check the pin table for each DQS/DQ group in the different modes.
The DQS pins are listed in the Arria GX pin tables as DQS[17..0]T or
DQS[17..0]B. The T denotes pins on the top of the device; the B denotes
pins on the bottom of the device. Corresponding DQ pins are marked as
DQ[17..0]. The numbering scheme starts from right to left on the
package bottom view. When not used as DQ or DQS pins, these pins are
available as regular I/O pins. Figure 7–6 shows the DQS pins in Arria GX
I/O banks.
Figure 7–6. DQS Pins in Arria GX I/O Banks Note (1), (2)
Top I/O Banks
DQS17T
DQS16T
DQS15T
DQS10T
PLL 11
PLL 5
I/O Bank
3
I/O Bank
11
I/O Bank
9
I/O Bank
8
I/O Bank
12
I/O Bank
10
PLL 12
PLL 6
DQS
Phase
Shift
Circuitry
DQS9T
DQS8T
DQS0T
I/O Bank
4
Bottom I/O Banks
DQS17B DQS16B DQS15B
DQS10B
DQS
Phase
Shift
Circuitry
I/O Bank
7
DQS9B
DQS8B
DQS0B
Notes to Figure 7–6:
(1)
(2)
There are up to 18 pairs of DQS pins on both the top and bottom of the device.
See Table 7–3 for DQS bus mode support based on the package.
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May 2008
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External Memory Interfaces in Arria GX Devices
The DQ pin numbering is based on ×4 mode. There are up to eight
DQS/DQ groups in ×4 mode in I/O banks 3 and 8 and up to 10 DQS/DQ
groups in ×4 mode in I/O banks 4 and 7. In ×8/×9 mode, two adjacent ×4
DQS/DQ groups plus one parity pin are combined; one DQS pin from the
combined groups can drive all the DQ and parity pins. Since there is an
even number of DQS/DQ groups in an I/O bank, combining groups is
efficient. Similarly, in ×16/×18 mode, four adjacent ×4 DQS/DQ groups
plus two parity pins are combined and one DQS pin from the combined
groups can drive all the DQ and parity pins. In ×32/×36 mode, eight
adjacent DQS/DQ groups are combined and one DQS pin can drive all
the DQ and parity pins in the combined groups.
1
On the top and bottom side of the device, the DQ and DQS pins
must be configured as bidirectional DDR pins to enable the DQS
phase-shift circuitry. You must use the ALTMEMPHY
megafunction to configure the DQ and DQS paths, respectively.
Clock Pins
You can use any of the DDR I/O registers to generate clocks to the
memory device. For better performance, use the same I/O bank as the
data and address and command pins.
Address and Command Pins
You can use any of the user I/O pins in the top or bottom bank of the
device for addresses and commands. For better performance, use the
same I/O bank as the data pins.
Other Pins (Parity, DM Pins)
You can use any of the DQ pins for parity pins in Arria GX devices. The
Arria GX device family has support for parity in ×8/×9, ×16/×18, and
×32/×36 mode. There is one parity bit available per eight bits of data pins.
The data mask and DM pins are only required when writing to DDR
SDRAM and DDR2 SDRAM devices. A low signal on the DM pins
indicates that the write is valid. If the DM signal is high, the memory
masks the DQ signals. You can use any I/O pins in the same bank as the
DQ pins for DM signals. Each group of DQS and DQ signals in DDR and
DDR2 SDRAM devices requires a DM pin. The DDR I/O output registers,
clocked by the –90o shifted clock, creates the DM signals, similar to DQ
output signals.
1
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Perform timing analysis to calculate write clock phase shift.
Altera Corporation
May 2008
Arria GX DDR Memory Support Overview
DQS Phase-Shift Circuitry
Arria GX phase-shift circuitry and DQS logic block controls the DQS pins.
Each Arria GX device contains two phase-shifting circuits. There is one
circuit for I/O banks 3 and 4 and another circuit for I/O banks 7 and 8.
The phase-shifting circuit on the top of the device can control all the DQS
pins in the top I/O banks; the phase-shifting circuit on the bottom of the
device can control all the DQS pins in the bottom I/O banks. Figure 7–7
shows DQS pin connections to the DQS logic block and DQS phase-shift
circuitry.
Figure 7–7. DQS Pins and DQS Phase-Shift Circuitry Note (1)
From PLL 5 (3)
DQS
Pin
DQS
Pin
Δt
Δt
to IOE
to IOE
CLK[15..12]p (2)
DQS
Phase Shift
Circuitry
DQS
Pin
DQS
Pin
Δt
Δt
to IOE
to IOE
DQS Logic
Blocks
Notes to Figure 7–7:
(1)
(2)
(3)
There are up to 18 pairs of DQS pins available on the top or bottom of the Arria GX device, up to eight on the left
side of the DQS phase-shift circuitry (I/O banks 3 and 8) and up to ten on the right side (I/O banks 4 and 7).
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device; clock pins CLK[7..4]p feed the
phase-shift circuitry on the bottom of the device. You can also use a phase-locked loop (PLL) clock output as a
reference clock to the phase-shift circuitry. You can also use the reference clock in the logic array.
You can only use PLL 5 to feed DQS phase-shift circuitry on the top of the device and PLL 6 to feed DQS phase-shift
circuitry on the bottom of the device.
Figure 7–8 shows the connections between the DQS phase-shift circuitry
and the DQS logic block.
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May 2008
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External Memory Interfaces in Arria GX Devices
To DQS
bus
Q
Input Reference
Clock (2)
Q
D
6
DQS Delay
Settings from the
Logic Array
DQS Delay
Settings from the
DQS Phase
Shift Circuitry
Phase Offset
Settings
6
6
6
DQS
Pin
Bypass
EN
6
6
6
D
EN
6
6
1/4
Stage
DQS Delay Chain
1/2
Stage
Update
Enable
Circuitry
3/4
Stage
Full
Stage
Postamble Circuitry
NOT
use_postamble
control
DQS Postamble
Control
Figure 7–8. DQS Phase-Shift Circuitry and DQS Logic Block Connections Note (1)
Notes to Figure 7–8:
(1)
(2)
(3)
(4)
(5)
(6)
All features of the DQS phase-shift circuitry and DQS logic block are controlled from the ALTMEMPHY
megafunction in the Quartus II software.
DQS logic block is available on every DQS pin.
There is one DQS phase-shift circuit on the top and bottom side of the device.
The input reference clock can come from CLK[15..12]p or PLL 5 for the DQS phase-shift circuitry on the top side
of the device or from CLK[7..4]p or PLL 6 for the DQS phase-shift circuitry on the bottom side of the device.
Each individual DQS pin can have individual DQS delay settings to and from the logic array.
This register is one of the DQS IOE input registers.
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May 2008
Arria GX DDR Memory Support Overview
Phase-shift circuitry is only used during read transactions where the DQS
pins are acting as input clocks or strobes. Phase-shift circuitry can shift the
incoming DQS signal by 0o, 22.5o, 30o, 36o, 45o, 60o, 67.5o, 72o, 90o, 108o,
120o, or 144o. The shifted DQS signal is then used as clocks at the DQ IOE
input registers.
Figure 7–3 on page 7–6 shows an example where the DQS signal is shifted
by 90o. The DQS signal goes through the 90o shift delay set by the DQS
phase-shift circuitry and the DQS logic block and some routing delay
from the DQS pin to the DQ IOE registers. DQ signals only goes through
routing delay from the DQ pin to the DQ IOE registers and maintains the
90o relationship between the DQS and DQ signals at the DQ IOE registers
since the software automatically sets delay chains to match the routing
delay between the pins and the IOE registers for the DQ and DQS input
paths.
All 18 DQS pins on either the top or bottom of the device can have their
input signal phase shifted by a different degree amount but all must be
referenced at one particular frequency. For example, you can have a 90o
phase shift on DQS0T and have a 60o phase shift on DQS1T, both
referenced from a 200-MHz clock. Not all phase-shift combinations are
supported, however. The phase shifts on the same side of the device must
all be a multiple of 22.5o (up to 90o), a multiple of 30o (up to 120o), or a
multiple of 36o (up to 144o).
In order to generate the correct phase shift with the DLL used, you must
provide a clock signal of the same frequency as the DQS signal to the DQS
phase-shift circuitry. Any of the CLK[15..12]p clock pins can feed the
phase circuitry on the top of the device (I/O banks 3 and 4) or any of the
CLK[7..4]p clock pins can feed the phase circuitry on the bottom of the
device (I/O banks 7 and 8). Arria GX devices can also use PLLs 5 or 6 as
the reference clock to the DQS phase-shift circuitry on the top or bottom
of the device, respectively. PLL 5 is connected to the DQS phase-shift
circuitry on the top side of the device; PLL 6 is connected to the DQS
phase-shift circuitry on the bottom side of the device. Both the top and
bottom phase-shift circuits need unique clock pins or PLL clock outputs
for the reference clock.
1
Altera Corporation
May 2008
When you have a PLL dedicated only to generate the DLL input
reference clock, you must set the PLL mode to No
Compensation or the Quartus II software will change the
setting automatically. Because there are no other PLL outputs
used, the PLL does not need to compensate for any clock paths.
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External Memory Interfaces in Arria GX Devices
DLL
DQS phase-shift circuitry uses a delay-locked loop (DLL) to dynamically
measure the clock period needed by the DQS pin (see Figure 7–8). DQS
phase-shift circuitry then uses the clock period to generate the correct
phase shift. The DLL in the Arria GX DQS phase-shift circuitry can
operate between 100 and 233 MHz. Phase-shift circuitry needs a
maximum of 256 clock cycles to calculate the correct input clock period.
Data sent during these clock cycles may not be properly captured.
1
Although the DLL can run up to 233 MHz, other factors may
prevent you from interfacing with a 233-MHz external memory
device.
1
You can still use DQS phase-shift circuitry for any memory
interfaces that are less than 100 MHz. The DQS signal is shifted
by 2.5 ns. You can add more shift by using the phase offset
module. Even if the DQS signal is not shifted exactly to the
middle of the DQ valid window, the IOE is still be able to
capture the data in this low frequency application.
There are three different frequency modes for the Arria GX DLL. Each
frequency mode provides different phase shift, as shown in Table 7–4.
Table 7–4. Arria GX DLL Frequency Modes
Frequency
Mode
Frequency Range (MHz)
0
1
2
Available Phase
Shift
Number of
Delay Chains
100–175
30, 60, 90, 120
12
150–230
22.5, 45, 67.5, 90
16
200–310
30, 60, 90, 120
12
In frequency mode 0, Arria GX devices use a 6-bit setting to implement
phase-shift delay. In frequency modes 1 and 2, Arria GX devices only use
a 5-bit setting to implement phase-shift delay.
You can reset the DLL from either the logic array or a user I/O pin. This
signal is not shown in Figure 7–9. Each time the DLL is reset, you must
wait for 256 clock cycles before you can capture the data properly.
Additionally, if the DLL reference clock is stopped and restarted
thereafter, such as during SDRAM refresh cycles, a minimum of 16 clock
cycles is needed before capturing data properly.
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May 2008
Arria GX DDR Memory Support Overview
Figure 7–9. Simplified Diagram of the DQS Phase-Shift Circuitry Note (1)
addnsub
Phase offset settings
from the logic array
DLL
6
Input reference
clock (2)
Phase
Offset
Control
upndn
Phase
Comparator
clock enable
Up/Down
Counter
6
Phase offset
settings (3)
6
Delay Chains
6
DQS delay
settings (4)
6
Notes to Figure 7–9:
(1)
(2)
(3)
(4)
All features of the DQS phase-shift circuitry are accessible from the ALTMEMPHY megafunction in the Quartus II
software.
The input reference clock for DQS phase-shift circuitry on the top side of the device can come from CLK[15..12]p
or PLL 5. The input reference clock for DQS phase-shift circuitry on the bottom side of the device can come from
CLK[7..4]p or PLL 6.
Phase offset settings can only go to DQS logic blocks.
DQS delay settings can go to the logic array and/or the DQS logic block.
The input reference clock goes into the DLL to a chain of up to 16 delay
elements. The phase comparator compares the signal coming out of the
end of the delay element chain to the input reference clock. The phase
comparator then issues the upndn signal to the up/down counter. This
signal increments or decrements a 6-bit delay setting (DQS delay settings)
that increases or decreases the delay through the delay element chain to
bring the input reference clock and the signals coming out of the delay
element chain in phase.
DQS delay settings contain control bits to shift the signal on the input
DQS pin by the amount set in the ALTMEMPHY megafunction. For
0 shift, both the DLL and DQS logic blocks are bypassed. Since Arria GX
DQS and DQ pins are designed such that the pin-to-IOE delays are
matched, the skew between the DQ and DQS pins at the DQ IOE registers
is negligible when you implement 0 shift. You can feed the DQS delay
settings to the DQS logic block and logic array.
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May 2008
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External Memory Interfaces in Arria GX Devices
Phase Offset Control
DQS phase-shift circuitry also contains a phase offset control module that
can add or subtract a phase offset amount from the DQS delay setting
(phase offset settings from the logic array in Figure 7–10). You should use
the phase offset control module for making small shifts to the input signal
and use the DQS phase-shift circuitry for larger signal shifts.
You can either use a static phase offset or a dynamic phase offset to
implement the additional phase shift. The available additional phase shift
is implemented in 2s-complement between settings –64 to +63 for
frequency mode 0 and between settings –32 to +31 for frequency modes
1, 2, and 3.
f
For more information about the value for each step, refer to the DC &
Switching Characteristics chapter in volume 1 of the Arria GX Device
Handbook. If you need one additional degree phase shift, you must
convert the delay amount to degrees in the operating frequency.
When using the static phase offset, you can specify the phase offset
amount in the ALTMEMPHY megafunction as a positive number for
addition or a negative number for subtraction. You can also have a
dynamic phase offset that is always added to, subtracted from, or both
added to and subtracted from the DLL phase shift. When you always add
or subtract, you can dynamically input the phase offset amount into the
dll_offset[5..0] port. When you want to both add and subtract
dynamically, you control the addnsub signal in addition to the
dll_offset[5..0] signals.
DQS Logic Block
Each DQS pin is connected to a separate DQS logic block (see
Figure 7–10). The logic block contains DQS delay chains and postamble
circuitry.
7–16
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Altera Corporation
May 2008
Arria GX DDR Memory Support Overview
To DQS
bus
EN
Input Reference
Clock (2)
EN
D
6
DQS Delay
Settings from the
Logic Array
DQS Delay
Settings from the
DQS Phase
Shift Circuitry
Phase Offset
Settings
6
6
6
DQS
Pin
Bypass
Q
6
6
6
D
Q
6
6
1/4
Stage
DQS Delay Chain
1/2
Stage
Update
Enable
Circuitry
3/4
Stage
Full
Stage
Postamble Circuitry
NOT
use_postamble
control
DQS Postamble
Control
Figure 7–10. Simplified Diagram of the DQS Logic Block Note (1)
Notes to Figure 7–10:
(1)
(2)
(3)
All features of the DQS logic block are controllable from the ALTMEMPHY megafunction in the Quartus II software.
The input reference clock for DQS phase-shift circuitry on the top side of the device can come from CLK[15..12]p
or PLL 5. The input reference clock for DQS phase-shift circuitry on the top side of the device can come from
CLK[7..4]p or PLL 6.
This register is one of the DQS IOE input registers.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
External Memory Interfaces in Arria GX Devices
DQS Delay Chains
DQS delay chains consist of a set of variable delay elements to allow the
input DQS signals to be shifted by the amount given by the DQS
phase-shift circuitry or the logic array. There are four delay elements in
the DQS delay chain; the first delay chain closest to the DQS pin can either
be shifted by the DQS delay settings or by the sum of the DQS delay
setting and the phase-offset setting. The number of delay chains used is
transparent to the users because the ALTMEMPHY megafunction
automatically sets it. DQS delay settings can come from DQS phase-shift
circuitry on the same side of the device as the target DQS logic block or
from the logic array. When you apply a 0o shift in the ALTMEMPHY
megafunction, DQS delay chains are bypassed.
The delay elements in the DQS logic block mimic the delay elements in
the DLL. The amount of delay is equal to the sum of the delay element’s
intrinsic delay and the product of the number of delay steps and the value
of the delay steps.
Both the DQS delay settings and the phase-offset settings pass through a
latch before going into the DQS delay chains. The latches are controlled
by the update enable circuitry to allow enough time for any changes in
the DQS delay setting bits to arrive to all the delay elements. This allows
them to be adjusted at the same time. The update enable circuitry enables
the latch to allow enough time for the DQS delay settings to travel from
the DQS phase-shift circuitry to all the DQS logic blocks before the next
change. It uses the input reference clock to generate the update enable
output. The ALTMEMPHY megafunction uses this circuit by default. See
Figure 7–11 for an example waveform of the update enable circuitry
output.
The shifted DQS signal then goes to the DQS bus to clock the IOE input
registers of the DQ pins. It can also go into the logic array for
resynchronization purposes.
Figure 7–11. DQS Update Enable Waveform
DLL Counter Update
(Every Eight Cycles)
DLL Counter Update
(Every Eight Cycles)
System Clock
DQS Delay Settings
(Updated every 8 cycles)
6 bit
Update Enable
Circuitry Output
7–18
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Altera Corporation
May 2008
Arria GX DDR Memory Support Overview
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe like
DDR and DDR2 SDRAM, the DQS signal is low before going to or coming
from a high-impedance state. See Figure 7–3 on page 7–6. The state where
DQS is low, just after a high-impedance state, is called the preamble; the
state where DQS is low, just before it returns to a high-impedance state, is
called the postamble. There are preamble and postamble specifications
for both read and write operations in DDR and DDR2 SDRAM. DQS
postamble circuitry ensures data is not lost when there is noise on the
DQS line at the end of a read postamble time. It is to be used with one of
the DQS IOE input registers such that the DQS postamble control signal
can ground the shifted DQS signal used to clock the DQ input registers at
the end of a read operation. This ensures that any glitches on the DQS
input signals at the end of the read postamble time do not affect the DQ
IOE registers.
f
For more information about DDR SDRAM and DDR2 SDRAM, refer to
AN 327: Interfacing DDR SDRAM with Stratix II Devices and AN 328:
Interfacing DDR2 SDRAM with Stratix II Devices.
DDR Registers
Each IOE in an Arria GX device contains six registers and one latch. Two
registers and a latch are used for input, two registers are used for output,
and two registers are used for output enable control. The second output
enable register provides the write preamble for the DQS strobe in DDR
external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by a half clock cycle to
provide the external memory’s DQS write preamble time specification.
Figure 7–12 shows the six registers and the latch in the Arria GX IOE.
Figure 7–13 shows how the second OE register extends the DQS
high-impedance state by half a clock cycle during a write operation.
Altera Corporation
May 2008
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External Memory Interfaces in Arria GX Devices
Figure 7–12. Bidirectional DDR I/O Path in Arria GX Devices Note (1)
DFF
oe
(2)
D
Q
OR2
OE Register AOE (3)
1
0
(4)
DFF
D
Q
OE Register BOE (5)
DFF
datain_l
D
Q
0
1
TRI (6)
I/O Pin (7)
Output Register AO
DFF
Logic Array
datain_h
D
Q
Output Register BO
outclock
combout
DFF
dataout_h
Q
D
Input Register AI
LatchTCHLA
dataout_l
Q
D
DFF
neg_reg_out
Q
D
ENA
Latch C I
Input Register BI
inclock
Notes to Figure 7–12:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
All control signals can be inverted at the IOE. The signal names used here match the Quartus II software naming
convention.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before input to the AOE register during compilation.
The AOE register generates the enable signal for general-purpose DDR I/O applications.
This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.
The BOE register generates the delayed enable signal for the write strobes or write clocks for memory interfaces.
The tri-state enable is active low by default. However, you can design it to be active high. The combinational control
path for the tri-state is not shown in this diagram.
You can also have combinational output to the I/O pin; this path is not shown in the diagram.
On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted).
7–20
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Altera Corporation
May 2008
Arria GX DDR Memory Support Overview
Figure 7–13. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction Note (1)
System clock
(outclock for DQS)
OE for DQS
(from logic array)
DQS
90˚
Delay
by Half
a Clock
Cycle
Preamble
Postamble
Write Clock
(outclock for DQ,
−90° phase shifted
from System Clock)
datain_h
(from logic array)
D0
D2
datain_l
(from logic array)
D1
D3
OE for DQ
(from logic array)
DQ
D0
D1
D2
D3
Note to Figure 7–13:
(1)
This waveform reflects the software simulation result. The OE signal is active low on the device. However, the
Quartus II software implements this signal as active high and automatically adds an inverter before the AOE register
D input.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
External Memory Interfaces in Arria GX Devices
Figures 7–14 and 7–15 summarize the IOE registers used for the DQ and
DQS signals.
Figure 7–14. DQ Configuration in Arria GX IOE Note (1)
DFF
(1)
D
oe
Q
OE Register AOE
DFF
D
datain_l
Q
0
1
Output Register AO
TRI
DQ Pin
DFF
Logic Array
D
datain_h
Q
Output Register BO
outclock (2)
DFF
Q
D
dataout_h
Input Register AI
Latch
TCH
LA
Q
dataout_l
D
DFF
neg_reg_out
Q
D
ENA
Latch C I
Input Register BI
inclock (from DQS bus)
(3)
Notes to Figure 7–14:
(1)
(2)
(3)
(4)
(5)
You should use the ALTMEMPHY megafunction to generate the data path for your memory interface.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register AOE during compilation.
The outclock signal for DDR and DDR2 SDRAM interfaces has a 90o phase-shift relationship with the system
clock. The shifted DQS signal can clock this register.
The shifted DQS signal must be inverted before going to the DQ IOE. The inversion is automatic if you use the
ALTMEMPHY megafunction to generate the DQ signals.
On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted).
7–22
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Altera Corporation
May 2008
Arria GX DDR Memory Support Overview
Figure 7–15. DQS Configuration in Arria GX IOE Note (1)
DFF
oe
(1)
D
Q
OE Register AOE
OR2
1
0
(2)
DFF
D
Q
OE Register BOE
DFF
Logic Array
datain_h (3)
D
Q
0
Output Register AO
TRI
DQS Pin (4)
1
DFF
datain_l (3)
system clock
combout
D
Q
Output Register BO
DQS Logic
Block (5)
Notes to Figure 7–15:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Use the ALTMEMPHY megafunction to generate the data path for your memory interface.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before OE register AOE during compilation.
The select line can be chosen in the ALTMEMPHY megafunction.
The datain_l and datain_h pins are usually connected to ground and VCC, respectively.
DQS postamble circuitry and handling is not shown in this diagram. For more information, refer to AN 327:
Interfacing DDR SDRAM with Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II Devices.
DQS logic blocks are only available with DQS pins.
You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the
ALTMEMPHY megafunction to generate the DQ signals.
Altera Corporation
May 2008
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External Memory Interfaces in Arria GX Devices
For interfaces to DDR SDRAM and DDR2 SDRAM, the Arria GX DDR
IOE structure requires you to invert the incoming DQS signal to ensure
proper data transfer. By default, the ALTMEMPHY megafunction adds
the inverter to the inclock port when it generates DQ blocks. As shown
in Figure 7–12 on page 7–20, the inclock signal’s rising edge clocks the
AI register, inclock signal’s falling edge clocks the BI register, and latch
CI is opened when inclock is 1. In a DDR memory read operation, the
last data coincides with DQS being low. If you do not invert the DQS pin,
you will not get this last data as the latch does not open until the next
rising edge of the DQS signal.
Figure 7–16 shows waveforms of the circuit shown in Figure 7–14 on
page 7–22.
The first set of waveforms in Figure 7–16 shows the edge-aligned
relationship between the DQ and DQS signals at the Arria GX device
pins. The second set of waveforms in Figure 7–16 shows what happens if
the shifted DQS signal is not inverted; the last data, Dn, does not get
latched into the logic array as DQS goes to tri-state after the read
postamble time. The third set of waveforms in Figure 7–16 shows a
proper read operation with the DQS signal inverted after the 90o shift; the
last data, Dn, does get latched. In this case the outputs of register AI and
latch CI, which correspond to dataout_h and dataout_l ports, are
now switched because of the DQS inversion. Register AI, register BI, and
latch CI refer to the nomenclature in Figure 7–14 on page 7–22.
7–24
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Altera Corporation
May 2008
Arria GX DDR Memory Support Overview
Figure 7–16. DQ Captures with Non-Inverted and Inverted Shifted DQS
DQ & DQS Signals
DQ at the pin
Dn − 1
Dn
DQS at the pin
Shifted DQS Signal is Not Inverted
DQS shifted by
90˚
Output of register A1
(dataout_h)
Output of register B1
Output of latch C1
(dataout_l)
Dn − 1
Dn − 2
Dn
Dn − 2
Shifted DQS Signal is Inverted
DQS inverted and
shifted by 90˚
Output of register A1
(dataout_h)
Output of register B1
Output of latch C1
(dataout_l)
Altera Corporation
May 2008
Dn − 2
Dn
Dn − 1
Dn − 3
Dn − 1
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Arria GX Device Handbook, Volume 2
External Memory Interfaces in Arria GX Devices
PLL
When using the Arria GX top and bottom I/O banks (I/O banks 3, 4, 7, or
8) to interface with a DDR memory, at least one PLL with two outputs is
needed to generate the system clock and write clock. The system clock
generates the DQS write signals, commands, and addresses. The write
clock is either shifted by –90o or 90o from the system clock and is used to
generate the DQ signals during writes.
For DDR and DDR2 SDRAM interfaces above 200 MHz, Altera also
recommends a second read PLL to help ease resynchronization.
Conclusion
Arria GX devices support SDR SDRAM, DDR SDRAM, and DDR2
SDRAM external memories. Arria GX devices feature high-speed
interfaces that transfer data between external memory devices at up to
233 MHz/466 Mbps. DQS phase-shift circuitry and DQS logic blocks
within Arria GX devices allow you to fine-tune the phase shifts for the
input clocks or strobes to properly align clock edges as needed to capture
data.
Referenced
Documents
This chapter references the following documents:
Document
Revision History
Table 7–5 shows the revision history for this chapter.
■
■
■
■
ALTMEMPHY Megafunction User Guide
AN 327: Interfacing DDR SDRAM with Stratix II Devices
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices
DC & Switching Characteristics chapter in volume 1 of the Arria GX
Device Handbook
Table 7–5. Document Revision History
Date and
Document
Version
May 2008
v1.2
Changes Made
Summary of Changes
Updated the “DLL” section.
—
Minor text edits.
—
August 2007
v1.1
Added the “Referenced Documents” section.
—
May 2007
v1.0
Initial Release
—
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Altera Corporation
May 2008
Section IV. I/O Standards
This section provides information on Arria™ GX single-ended,
voltage-referenced, and differential I/O standards.
This section contains the following chapters:
Revision History
Altera Corporation
■
Chapter 8, Selectable I/O Standards in Arria GX Devices
■
Chapter 9, High-Speed Differential I/O Interfaces with DPA in Arria
GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section IV–1
Preliminary
I/O Standards
Section IV–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
8. Selectable I/O Standards in
Arria GX Devices
AGX52008-1.2
Introduction
This chapter provides guidelines for using industry I/O standards in
Arria™ GX devices, including:
■
■
■
■
■
I/O features
I/O standards
External memory interfaces
I/O banks
Design considerations
This chapter contains the following sections:
■
■
■
■
■
■
■
Arria GX I/O
Features
“Arria GX I/O Features” on page 8–1
“Arria GX I/O Standards Support” on page 8–2
“Arria GX External Memory Interfaces” on page 8–19
“Arria GX I/O Banks” on page 8–20
“On-Chip Termination” on page 8–25
“Design Considerations” on page 8–28
“Conclusion” on page 8–37
Arria GX devices contain an abundance of adaptive logic modules
(ALMs), embedded memory, high-bandwidth digital signal processing
(DSP) blocks, and extensive routing resources, all of which can operate at
very high core speed.
The Arria GX device’s I/O structure is designed to ensure that these
internal capabilities are fully utilized. There are numerous I/O features to
assist in high-speed data transfer into and out of the device including:
■
■
1
Altera Corporation
May 2008
Single-ended, non-voltage-referenced and voltage-referenced I/O
standards
High-speed differential I/O standards featuring
serializer/deserializer (SERDES), dynamic phase alignment (DPA),
capable of 840 megabit per second (Mbps) performance for
low-voltage differential signaling (LVDS), Hypertransport
technology, high-speed transceiver logic (HSTL), stub-series
terminated logic (SSTL), and LVPECL
HSTL, SSTL, and LVPECL I/O standards are used only for PLL
clock inputs and outputs in differential mode.
8–1
Arria GX I/O Standards Support
■
■
■
■
■
■
■
■
■
f
Arria GX I/O
Standards
Support
Double data rate (DDR) I/O pins
Programmable output drive strength for voltage-referenced and
non-voltage-referenced single-ended I/O standards
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination
On-chip differential termination
Peripheral component interconnect (PCI) clamping diode
Hot socketing
For a detailed description of each I/O feature, refer to the Arria GX
Architecture chapter in volume 1 of the Arria GX Device Handbook.
Arria GX devices support a wide range of industry I/O standards.
Table 8–1 shows which I/O standards Arria GX devices support as well
as typical applications.
Table 8–1. Arria GX I/O Standard Applications (Part 1 of 2)
I/O Standard
Application
LVTTL
General purpose
LVCMOS
General purpose
2.5 V
General purpose
1.8 V
General purpose
1.5 V
General purpose
3.3-V PCI
PC and embedded system
3.3-V PCI-X
PC and embedded system
SSTL-2 Class I
DDR SDRAM
SSTL-2 Class II
DDR SDRAM
SSTL-18 Class I
DDR2 SDRAM
SSTL-18 Class II
DDR2 SDRAM
1.8-V HSTL Class I
SRAM interfaces
1.8-V HSTL Class II
SRAM interfaces
1.5-V HSTL Class I
SRAM interfaces
1.5-V HSTL Class II
SRAM interfaces
1.2-V HSTL
General purpose
Differential SSTL-2 Class I
DDR SDRAM
Differential SSTL-2 Class II
DDR SDRAM
Differential SSTL-18 Class I
DDR2 SDRAM
8–2
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Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Table 8–1. Arria GX I/O Standard Applications (Part 2 of 2)
I/O Standard
Differential SSTL-18 Class II
Application
DDR2 SDRAM
1.8-V differential HSTL Class I
Clock interfaces
1.8-V differential HSTL Class II
Clock interfaces
1.5-V differential HSTL Class I
Clock interfaces
1.5-V differential HSTL Class II
Clock interfaces
LVDS
High-speed communications
HyperTransport technology
PCB interfaces
Differential LVPECL
Video graphics and clock distribution
Single-Ended I/O Standards
In non-voltage-referenced single-ended I/O standards, the voltage at the
input must be above a set voltage to be considered "on" (high, or logic
value 1) or below another voltage to be considered "off" (low, or logic
value 0). Voltages between the limits are undefined logically, and may fall
into either a logic value 0 or 1. The non-voltage-referenced single-ended
I/O standards supported by Arria GX devices are:
■
■
■
■
■
■
■
Low-voltage transistor-transistor logic (LVTTL)
Low-voltage complementary metal-oxide semiconductor (LVCMOS)
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X
Voltage-referenced, single-ended I/O standards provide faster data rates.
These standards use a constant reference voltage at the input levels. The
incoming signals are compared with this constant voltage and the
difference between the two defines "on" and "off" states.
1
Arria GX devices support SSTL and HSTL voltage-referenced
I/O standards.
LVTTL
The LVTTL standard is formulated under the EIA/JEDEC Standard,
JESD8-B (Revision of JESD8-A): Interface Standard for Nominal
3-V/3.3-V Supply Digital Integrated Circuits.
Altera Corporation
May 2008
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Arria GX I/O Standards Support
The standard defines DC interface parameters for digital circuits
operating from a 3.0- or 3.3-V power supply and driving or being driven
by LVTTL-compatible devices. The 3.3-V LVTTL standard is a
general-purpose, single-ended standard used for 3.3-V applications. This
I/O standard does not require input reference voltages (VREF) or
termination voltages (VTT).
1
Arria GX devices support both input and output levels for 3.3-V
LVTTL operation.
Arria GX devices support a VCCIO voltage level of 3.3 V ±5% as specified
as the narrow range for the voltage supply by the EIA/JEDEC standard.
LVCMOS
The LVCMOS standard is formulated under the EIA/JEDEC Standard,
JESD8-B (Revision of JESD8-A): Interface Standard for Nominal
3-V/3.3-V Supply Digital Integrated Circuits.
The standard defines DC interface parameters for digital circuits
operating from a 3.0- or 3.3-V power supply and driving or being driven
by LVCMOS-compatible devices. The 3.3-V LVCMOS I/O standard is a
general-purpose, single-ended standard used for 3.3-V applications.
While LVCMOS has its own output specification, it specifies the same
input voltage requirements as LVTTL. These I/O standards do not
require VREF or VTT.
1
Arria GX devices support both input and output levels for 3.3-V
LVCMOS operation.
Arria GX devices support a VCCIO voltage level of 3.3 V ±5% as specified
as the narrow range for the voltage supply by the EIA/JEDEC standard.
1.5 V
The 1.5-V I/O standard is formulated under the EIA/JEDEC Standard,
JESD8-11: 1.5-V ±0.1-V (Normal Range) and 0.9-V – 1.6-V (Wide Range)
Power Supply Voltage and Interface Standard for Non-Terminated
Digital Integrated Circuit.
The standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 1.5-V devices. This standard is a general-purpose, single-ended
standard used for 1.5-V applications. It does not require the use of a VREF
or a VTT.
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May 2008
Selectable I/O Standards in Arria GX Devices
1
Arria GX devices support both input and output levels for 1.5-V
operation VCCIO voltage level support of 1.8 V ±5%, which is
narrower than defined in the Normal Range of the EIA/JEDEC
standard.
1.8 V
The 1.8-V I/O standard is formulated under the EIA/JEDEC Standard,
EIA/JESD8-7: 1.8-V ±0.15-V (Normal Range), and 1.2-V – 1.95-V (Wide
Range) Power Supply Voltage and Interface Standard for
Non-Terminated Digital Integrated Circuit.
The standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 1.8-V devices. This standard is a general-purpose, single-ended
standard used for 1.8-V applications. It does not require the use of a VREF
or a VTT.
1
Arria GX devices support both input and output levels for 1.8-V
operation with VCCIO voltage level support of 1.8 V ±5%, which
is narrower than defined in the Normal Range of the
EIA/JEDEC standard.
2.5 V
The 2.5-V I/O standard is formulated under the EIA/JEDEC Standard,
EIA/JESD8-5: 2.5-V ± 0.2-V (Normal Range), and 1.8-V – 2.7-V (Wide
Range) Power Supply Voltage and Interface Standard for
Non-Terminated Digital Integrated Circuit.
The standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 2.5-V devices. This standard is a general-purpose, single-ended
standard used for 2.5-V applications. It does not require the use of a VREF
or a VTT.
1
Altera Corporation
May 2008
Arria GX devices support both input and output levels for 2.5-V
operation with VCCIO voltage level support of 2.5 V ±5%, which
is narrower than defined in the Normal Range of the
EIA/JEDEC standard.
8–5
Arria GX Device Handbook, Volume 2
Arria GX I/O Standards Support
3.3-V PCI
The 3.3-V PCI I/O standard is formulated under the PCI Local Bus
Specification Revision 2.2 developed by the PCI Special Interest Group
(SIG).
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
specification revision 2.2 defines the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expansion boards. This standard
requires 3.3-V VCCIO. Arria GX devices are fully compliant with the 3.3-V
PCI Local Bus Specification Revision 2.2 and meet 64-bit/33-MHz
operating frequency and timing requirements.
1
The 3.3-V PCI standard does not require input reference
voltages or board terminations. Arria GX devices support both
input and output levels.
3.3-V PCI-X
The 3.3-V PCI-X I/O standard is formulated under the PCI-X Local Bus
Specification Revision 1.0a developed by the PCI SIG.
The PCI-X 1.0 standard is used for applications that interface to the PCI
local bus. The standard enables the design of systems and devices that
operate at clock speeds up to 133 MHz, or 1 Gbps for a 64-bit bus. The
PCI-X 1.0 protocol enhancements enable devices to operate much more
efficiently, providing more usable bandwidth at any clock frequency. By
using the PCI-X 1.0 standard, you can design devices to meet PCI-X 1.0
requirements and operate as conventional 33- and 66-MHz PCI devices
when installed in those systems. This standard requires 3.3-V VCCIO.
Arria GX devices are fully compliant with the 3.3-V PCI-X Specification
Revision 1.0a and meet the 133-MHz operating frequency and timing
requirements. The 3.3-V PCI-X standard does not require input reference
voltages or board terminations.
1
8–6
Arria GX Device Handbook, Volume 2
Arria GX devices support both input and output levels
operation.
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
SSTL-2 Class I & SSTL-2 Class II
The 2.5-V SSTL-2 standard is formulated under the JEDEC Standard,
JESD8-A: Stub Series Terminated Logic for 2.5-V (SSTL_2).
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
SSTL-2 requires a 1.25-V VREF and a 1.25-V VTT to which the series and
termination resistors are connected (Figures 8–1 and 8–2).
1
Arria GX devices support both input and output levels
operation.
Figure 8–1. 2.5-V SSTL Class I Termination
VTT = 0.75 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
Figure 8–2. 2.5-V SSTL Class II Termination
VTT = 1.25 V
VTT = 1.25 V
Output Buffer
50 Ω
25 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.25 V
SSTL-18 Class I & SSTL-18 Class II
The 1.8-V SSTL-18 standard is formulated under the JEDEC Standard,
JESD8-15: Stub Series Terminated Logic for 1.8-V (SSTL_18).
The SSTL-18 I/O standard is a 1.8-V memory bus standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
is similar to SSTL-2 and defines input and output specifications for
Altera Corporation
May 2008
8–7
Arria GX Device Handbook, Volume 2
Arria GX I/O Standards Support
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT to which the
series and termination resistors are connected.
There are no class definitions for the SSTL-18 standard in the JEDEC
specification. The specification of this I/O standard is based on an
environment that consists of both series and parallel terminating
resistors. Altera® provides solutions to two derived applications in the
JEDEC specification, and names them Class I and Class II to be consistent
with other SSTL standards. Figures 8–3 and 8–4 show SSTL-18 Class I and
II termination, respectively.
1
Arria GX devices support both input and output levels
operation.
Figure 8–3. Figure9–3.1.8-V SSTL Class I Termination
VTT = 0.9 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Figure 8–4. Figure9–4.1.8-V SSTL Class II Termination
VTT = 0.9 V
VTT = 0.9 V
50 Ω
50 Ω
Output Buffer
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
1.8-V HSTL Class I & 1.8-V HSTL Class II
The HSTL standard is a technology-independent I/O standard
developed by JEDEC to provide voltage scalability. It is used for
applications designed to operate in the 0.0- to 1.8-V HSTL logic switching
range.
Although JEDEC specifies a maximum VCCIO value of 1.6 V, there are
various memory chip vendors with HSTL standards that require a VCCIO
of 1.8 V. Arria GX devices support interfaces to chips with VCCIO of 1.8 V
8–8
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
for HSTL. Figures 8–5 and 8–6 show the nominal VREF and VTT required
to track the higher value of VCCIO. The value of VREF is selected to provide
optimum noise margin in the system.
1
Arria GX devices support both input and output levels
operation.
Figure 8–5. 1.8-V HSTL Class I Termination
VTT = 0.9 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Figure 8–6. 1.8-V HSTL Class II Termination
VTT = 0.9 V
VTT = 0.9 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
1.5-V HSTL Class I & 1.5-V HSTL Class II
The 1.5-V HSTL standard is formulated under the EIA/JEDEC Standard,
EIA/JESD8-6: A 1.5-V Output Buffer Supply Voltage Based Interface
Standard for Digital Integrated Circuits.
The 1.5-V HSTL I/O standard is used for applications designed to operate
in the 0.0- to 1.5-V HSTL logic nominal switching range. This standard
defines single-ended input and output specifications for all
HSTL-compliant digital integrated circuits. The 1.5-V HSTL I/O standard
in Arria GX devices are compatible with the 1.8-V HSTL I/O standard in
APEX 20KE, APEX20KC, and in Arria GX devices themselves because the
input and output voltage thresholds are compatible (Figures 8–7 and
8–8).
1
Altera Corporation
May 2008
Arria GX devices support both input and output levels with
VREF and VTT.
8–9
Arria GX Device Handbook, Volume 2
Arria GX I/O Standards Support
Figure 8–7. 1.5-V HSTL Class I Termination
VTT = 0.75 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
Figure 8–8. 1.5-V HSTL Class II Termination
VTT = 0.75 V
VTT = 0.75 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
1.2-V HSTL
Although there is no EIA/JEDEC standard available for the 1.2-V HSTL
standard, Altera supports it for applications that operate in the 0.0 to
1.2-V HSTL logic nominal switching range. 1.2-V HSTL can be terminated
through series on-chip termination (OCT). Figure 8–9 shows the
termination scheme.
Figure 8–9. 1.2-V HSTL Termination
Output Buffer
Z = 50 Ω
Input Buffer
OCT
VREF = 0.6 V
Differential I/O Standards
Differential I/O standards are used to achieve even faster data rates with
higher noise immunity. Apart from LVDS, LVPECL, and HyperTransport
technology, Arria GX devices also support differential versions of SSTL
and HSTL standards.
8–10
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
f
For detailed information about differential I/O standards, refer to the
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter
in volume 2 of the Arria GX Device Handbook.
Differential SSTL-2 Class I & Differential SSTL-2 Class II
The 2.5-V differential SSTL-2 standard is formulated under the JEDEC
Standard, JESD8-9A: Stub Series Terminated Logic for 2.5-V (SSTL_2).
This I/O standard is a 2.5-V standard used for applications such as
high-speed DDR SDRAM clock interfaces. This standard supports
differential signals in systems using the SSTL-2 standard and
supplements the SSTL-2 standard for differential clocks. Arria GX
devices support both input and output levels. Figures 8–10 and 8–11
show details about differential SSTL-2 termination.
1
Arria GX devices support differential SSTL-2 I/O standards in
pseudo-differential mode, which is implemented by using two
SSTL-2 single-ended buffers.
The Quartus® II software only supports pseudo-differential standards on
the INCLK, FBIN, and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support pseudo-differential
SSTL-2 I/O standards on the left I/O banks, you can implement these
standards on these banks. You need to create two pins in the designs and
configure the pins with single-ended SSTL-2 standards. However, this is
limited only to pins that support the differential pin-pair I/O function
and is dependent on the single-ended SSTL-2 standards support at these
banks.
Altera Corporation
May 2008
8–11
Arria GX Device Handbook, Volume 2
Arria GX I/O Standards Support
Figure 8–10. Differential SSTL-2 Class I Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
Differential
Receiver
50 Ω
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Figure 8–11. Differential SSTL-2 Class II Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Differential SSTL-18 Class I & Differential SSTL-18 Class II
The 1.8-V differential SSTL-18 standard is formulated under the JEDEC
Standard, JESD8-15: Stub Series Terminated Logic for 1.8-V (SSTL_18).
The differential SSTL-18 I/O standard is a 1.8-V standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
supports differential signals in systems using the SSTL-18 standard and
supplements the SSTL-18 standard for differential clocks.
1
8–12
Arria GX Device Handbook, Volume 2
Arria GX devices support both input and output levels
operation.
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Figures 8–12 and 8–13 show details about differential SSTL-18
termination. Arria GX devices support differential SSTL-18 I/O
standards in pseudo-differential mode, which is implemented by using
two SSTL-18 single-ended buffers.
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBIN, and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support pseudo-differential
SSTL-18 I/O standards on the left and I/O banks, you can implement
these standards at these banks. You need to create two pins in the designs
and configure the pins with single-ended SSTL-18 standards. However,
this is limited only to pins that support the differential pin-pair I/O
function and is dependent on the single-ended SSTL-18 standards
support at these banks.
Figure 8–12. Differential SSTL-18 Class I Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Altera Corporation
May 2008
8–13
Arria GX Device Handbook, Volume 2
Arria GX I/O Standards Support
Figure 8–13. Differential SSTL-18 Class II Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
1.8-V Differential HSTL Class I & 1.8-V Differential HSTL Class II
The 1.8-V differential HSTL specification is the same as the 1.8-V
single-ended HSTL specification. It is used for applications designed to
operate in the 0.0- to 1.8-V HSTL logic switching range such as QDR
memory clock interfaces. Arria GX devices support both input and
output levels operation. Figures 8–14 and 8–15 show details about 1.8-V
differential HSTL termination.
Arria GX devices support 1.8-V differential HSTL I/O standards in
pseudo-differential mode, which is implemented by using two 1.8-V
HSTL single-ended buffers.
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBIN, and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support 1.8-V
pseudo-differential HSTL I/O standards on left I/O banks, you can
implement these standards at these banks. You need to create two pins in
the designs and configure the pins with single-ended 1.8-V HSTL
standards. However, this is limited only to pins that support the
differential pin-pair I/O function and is dependent on the single-ended
1.8-V HSTL standards support at these banks.
8–14
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Figure 8–14. 1.8-V Differential HSTL Class I Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
Differential
Receiver
50 Ω
Z0 = 50 Ω
Z0 = 50 Ω
Figure 8–15. 1.8-V Differential HSTL Class II Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
1.5-V Differential HSTL Class I & 1.5-V Differential HSTL Class II
The 1.5-V differential HSTL standard is formulated under the
EIA/JEDEC Standard, EIA/JESD8-6: A 1.5-V Output Buffer Supply
Voltage Based Interface Standard for Digital Integrated Circuits.
The 1.5-V differential HSTL specification is the same as the 1.5-V
single-ended HSTL specification. It is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range, such as QDR
memory clock interfaces. Arria GX devices support both input and
output levels operation. Figures 8–16 and 8–17 show details on the 1.5-V
differential HSTL termination.
Arria GX devices support 1.5-V differential HSTL I/O standards in
pseudo-differential mode, which is implemented by using two 1.5-V
HSTL single-ended buffers.
Altera Corporation
May 2008
8–15
Arria GX Device Handbook, Volume 2
Arria GX I/O Standards Support
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBIN, and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support 1.5-V
pseudo-differential HSTL I/O standards on left I/O banks, you can
implement these standards at these banks. You need to create two pins in
the designs and configure the pins with single-ended 1.5-V HSTL
standards. However, this is limited only to pins that support the
differential pin-pair I/O function and is dependent on the single-ended
1.5-V HSTL standards support at these banks.
Figure 8–16. 1.5-V Differential HSTL Class I Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
8–16
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Figure 8–17. 1.5-V Differential HSTL Class II Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
50 Ω
VTT = 0.75 V
50 Ω
VTT = 0.75 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
LVDS
The LVDS standard is formulated under the ANSI/TIA/EIA Standard,
ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage
Differential Signaling Interface Circuits.
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard. In Arria GX devices,
the LVDS I/O standard requires a 2.5-V VCCIO level. However, LVDS clock
output pins in the top and bottom I/O banks require a 3.3-V VCCIO level.
This standard is used in applications requiring high-bandwidth data
transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Arria GX devices are
capable of running at a maximum data rate of 840 Mbps and still meet the
ANSI/TIA/EIA-644 standard.
Because of the low-voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than
complementary metal-oxide semiconductor (CMOS),
transistor-to-transistor logic (TTL), and positive (or pseudo) emitter
coupled logic (PECL). This low EMI makes LVDS ideal for applications
with low EMI requirements or noise immunity requirements. The LVDS
standard does not require an input reference voltage. However, it does
require a 100-Ω termination resistor between the two signals at the input
buffer. Arria GX devices provide an optional 100-Ω differential LVDS
termination resistor in the device using on-chip differential termination.
Arria GX devices support both input and output levels operation.
Altera Corporation
May 2008
8–17
Arria GX Device Handbook, Volume 2
Arria GX I/O Standards Support
Differential LVPECL
The low-voltage positive (or pseudo) emitter coupled logic (LVPECL)
standard is a differential interface standard requiring a 3.3-V VCCIO. The
standard is used in applications involving video graphics,
telecommunications, data communications, and clock distribution. The
high-speed, low-voltage swing LVPECL I/O standard uses a positive
power supply and is similar to LVDS. However, LVPECL has a larger
differential output voltage swing than LVDS. The LVPECL standard does
not require an input reference voltage, but it does require a 100-Ω
termination resistor between the two signals at the input buffer.
Figures 8–18 and 8–19 show two alternate termination schemes for
LVPECL.
1
Arria GX devices support both input and output levels
operation.
Figure 8–18. LVPECL DC Coupled Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
Figure 8–19. LVPECL AC Coupled Termination
VCCIO
VCCIO
Output Buffer
10 to 100 nF
Z = 50 Ω
R1
R1
R2
R2
Input Buffer
100 Ω
10 to 100 nF
8–18
Arria GX Device Handbook, Volume 2
Z = 50 Ω
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
HyperTransport Technology
The HyperTransport standard is formulated by the HyperTransport
Consortium.
The HyperTransport I/O standard is a differential high-speed,
high-performance I/O interface standard requiring a 2.5- or 3.3-V VCCIO.
This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport I/O
standard is a point-to-point standard in which each HyperTransport bus
consists of two point-to-point unidirectional links. Each link is 2 to 32 bits.
The HyperTransport standard does not require an input reference
voltage. However, it does require a 100-Ω termination resistor between
the two signals at the input buffer. Figure 8–20 shows HyperTransport
termination. Arria GX devices include an optional 100-Ω differential
HyperTransport termination resistor in the device using on-chip
differential termination.
1
Arria GX devices support both input and output levels
operation.
Figure 8–20. HyperTransport Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
Arria GX
External
Memory
Interfaces
The increasing demand for higher-performance data processing systems
often requires memory-intensive applications. Arria GX devices can
interface with many types of external memory.
f
Altera Corporation
May 2008
Refer to the External Memory Interfaces in Arria GX Devices chapter in
volume 2 of the Arria GX Device Handbook for more information about
the external memory interface support in Arria GX devices.
8–19
Arria GX Device Handbook, Volume 2
Arria GX I/O Banks
Arria GX I/O
Banks
Arria GX devices have six general I/O banks and four enhanced
phase-locked loop (PLL) external clock output banks (Figure 8–21). I/O
banks 9 through 12 are enhanced PLL external clock output banks located
on the top and bottom of the device.
Figure 8–21. Arria GX I/O Banks Note (1), (2), (3), (4), (5), (6)
Bank 2
DQSx8
DQSx8
DQSx8
DQSx8
DQSx8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
Bank 4
Bank 9
This I/O bank supports LVDS and LVPECL
This I/O bank supports LVDS and LVPECL
standards for input clock operations.
standards for input clock operation.
Differential HSTL and differential SSTL
Differential HSTL and differential SSTL
standards are supported for both input
standards are supported for both input
and output operations. (3)
and output operations. (3)
I/O Banks 3, 4, 9 & 11 support all
single-ended I/O standards for both
input and output operation. All
differential I/O standards are supported
for both input and output operation at
I/O banks 9 & 10.
I/O Banks 1, & 2, support LVTTL, LVCMOS, 2.5 -V, 1.9 -]V, 1.5 -V, SSTL -2, SSTL-18 class I,
LVDS, pseudo-differential SSTL -2, and pseudo-differential SSTL-18 class I standards for both
input and output operations. HSTL, SSTL-18 class II, pseudo-differential HSTL, and
pseudo-differential SSTL-18 class II standards are only supported for input operations. (4)
PLL1
PLL2
PLL8
This I/O bank supports LVDS and LVPECL
standards for input clock operations.
Differential HSTL and differential SSTL
standards are supported for both input
and output operations. (3)
Bank 16
I/O Banks 7, 8, 10 and 12 support all
single-ended I/O standards for both input
and output operation. All differential I/O
standards are supported for both input and output
operations at I/O bank 10 and 12.
Bank 1
VREF0B1 VREF1B1 VREF2B1 VREF3B1 VREF4B1
Bank 11
PLL5
This I/O bank supports LVDS and LVPECL
standards for input clock operations.
Differential HSTL and differential SSTL
standards are supported for both input
and output operations. (3)
Bank 15
VREF0B2 VREF1B2 VREF2B2 VREF3B2 VREF4B2
Bank 3
PLL11
Bank 8
Bank 12
Bank 10
Bank 7
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
PLL12
PLL6
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQSx8
DQSx8
DQSx8
DQSx8
Bank 13
DQSx8
Bank 14
DQSx8
DQSx8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
Bank 17
DQSx8
PLL7
DQSx8
DQSx8
DQSx8
DQSx8
DQSx8
Notes to Figure 8–21:
(1)
(2)
(3)
(4)
(5)
(6)
Figure 8–21 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a
graphical representation only.
Depending on size of the device, different device members have different number of VREF groups. Refer to the pin
list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
Horizontal I/O banks feature transceiver and DPA circuitry for high speed differential I/O standards. Refer to the
High-Speed Differential I/O Interfaces in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook, or
the Arria GX Transceiver User Guide for more information about differential I/O standards.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks.
Refer to the “Differential I/O Standards” on page 8–10 if you need to implement these standards at these I/O banks.
PLLs 7, 8, 11, and 12 are available only in EP1AGX50D, EP1AGX60E, and EP1AGX90E devices.
8–20
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Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Programmable I/O Standards
Arria GX device programmable I/O standards deliver high-speed and
high-performance solutions in many complex design systems. This
section discusses the I/O standard support in the I/O banks of Arria GX
devices.
Regular I/O Pins
Most Arria GX device pins are multi-function pins. These pins support
regular inputs and outputs as their primary function, and offer an
optional function such as DQS, differential pin-pair, or PLL external clock
outputs. For example, you can configure a multi-function pin in the
enhanced PLL external clock output bank as a PLL external clock output
when it is not used as a regular I/O pin.
1
I/O pins that reside in PLL banks 9 through 12 are powered by
the VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. Some
devices/packages do not support PLLs 11 and 12. Therefore,
any I/O pins that reside in bank 11 are powered by the VCCIO3
pin, and any I/O pins that reside in bank 12 are powered by the
VCCIO8 pin.
Table 8–2 shows the I/O standards supported when a pin is used as a
regular I/O pin in the I/O banks of Arria GX devices.
Table 8–2. Arria GX Regular I/O Standards Support (Part 1 of 2)
I/O Standard
Enhanced PLL External
Clock Output Bank (2)
General I/O Bank (1)
1
2
3
4
7
8
9
10
11
12
LVTTL
v
v
v
v
v
v
v
v
v
v
LVCMOS
v
v
v
v
v
v
v
v
v
v
2.5 V
v
v
v
v
v
v
v
v
v
v
1.8 V
v
v
v
v
v
v
v
v
v
v
1.5 V
v
v
v
v
v
v
v
v
v
v
3.3-V PCI
v
v
v
v
v
v
v
v
3.3-V PCI-X
v
v
v
v
v
v
v
v
SSTL-2 Class I
v
v
v
v
v
v
v
v
v
v
SSTL-2 Class II
v
v
v
v
v
v
v
v
v
v
SSTL-18 Class I
v
v
v
v
v
v
v
v
v
v
SSTL-18 Class II
(3)
(3)
v
v
v
v
v
v
v
v
1.8-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
Altera Corporation
May 2008
8–21
Arria GX Device Handbook, Volume 2
Arria GX I/O Banks
Table 8–2. Arria GX Regular I/O Standards Support (Part 2 of 2)
I/O Standard
Enhanced PLL External
Clock Output Bank (2)
General I/O Bank (1)
1
2
3
4
7
8
9
10
11
12
1.8-V HSTL Class II
(3)
(3)
v
v
v
v
v
v
v
v
1.5-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
1.5-V HSTL Class II
(3)
(3)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
1.2-V HSTL
Differential SSTL-2 Class I
(4)
(4)
(5)
(5)
(5)
(5)
Differential SSTL-2 Class II
(4)
(4)
(5)
(5)
(5)
(5)
Differential SSTL-18 Class I
(4)
(4)
(5)
(5)
(5)
(5)
Differential SSTL-18 Class II
(4)
(4)
(5)
(5)
(5)
(5)
1.8-V differential HSTL Class I
(4)
(4)
(5)
(5)
(5)
(5)
1.8-V differential HSTL Class II
(4)
(4)
(5)
(5)
(5)
(5)
1.5-V differential HSTL Class I
(4)
(4)
(5)
(5)
(5)
(5)
1.5-V differential HSTL Class II
(4)
(4)
(5)
(5)
(5)
(5)
LVDS
v
v
(6)
(6)
(6)
(6)
HyperTransport technology
v
v
(6)
(6)
(6)
(6)
Differential LVPECL
v
v
v
v
Notes to Table 8–2:
(1)
(2)
(3)
(4)
(5)
(6)
Banks 5 and 6 are not available in Arria GX Devices.
A mixture of single-ended and differential I/O standards is not allowed in enhanced PLL external clock output
bank.
This I/O standard is only supported for the input operation in this I/O bank.
Although the Quartus II software does not support pseudo-differential SSTL-2 I/O standards on the left and
right I/O banks, you can implement these standards at these banks. Refer to “Differential I/O Standards” on
page 8–10 for details.
This I/O standard is supported for both input and output operations for pins that support the DQS function.
Refer to “Differential I/O Standards” on page 8–10 for details.
This I/O standard is only supported for the input operation for pins that support PLL INCLK function in this I/O
bank.
Clock I/O Pins
The PLL clock I/O pins consist of clock inputs (INCLK), external feedback
inputs (FBIN), and external clock outputs (EXTCLK). Clock inputs are
located on the left I/O banks (banks 1 and 2) to support fast PLLs, and at
the top and bottom I/O banks (banks 3, 4, 7, and 8) to support enhanced
PLLs. Both external clock outputs and external feedback inputs are
located at enhanced PLL external clock output banks (banks 9, 10, 11, and
12) to support enhanced PLLs.
8–22
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Table 8–3 shows the PLL clock I/O support in the I/O banks of Arria GX
devices.
Table 8–3. I/O Standards Supported for Arria GX PLL Pins
Enhanced PLL (1)
I/O Standard
Input
Fast PLL
Output
Input
INCLK
FBIN
EXTCLK
INCLK
LVTTL
v
v
v
v
LVCMOS
v
v
v
v
2.5 V
v
v
v
v
1.8 V
v
v
v
v
1.5 V
v
v
v
v
3.3-V PCI
v
v
v
3.3-V PCI-X
v
v
v
SSTL-2 Class I
v
v
v
v
SSTL-2 Class II
v
v
v
v
SSTL-18 Class I
v
v
v
v
SSTL-18 Class II
v
v
v
v
1.8-V HSTL Class I
v
v
v
v
1.8-V HSTL Class II
v
v
v
v
1.5-V HSTL Class I
v
v
v
v
1.5-V HSTL Class II
v
v
v
v
Differential SSTL-2 Class I
v
v
v
Differential SSTL-2 Class II
v
v
v
Differential SSTL-18 Class I
v
v
v
Differential SSTL-18 Class II
v
v
v
1.8-V differential HSTL Class I
v
v
v
1.8-V differential HSTL Class II
v
v
v
1.5-V differential HSTL Class I
v
v
v
1.5-V differential HSTL Class II
v
v
v
LVDS
v
v
v
Differential LVPECL
v
v
HyperTransport technology
v
v
v
Note to Table 8–3:
(1)
The enhanced PLL external clock output bank does not allow a mixture of both single-ended and differential I/O
standards.
Altera Corporation
May 2008
8–23
Arria GX Device Handbook, Volume 2
Arria GX I/O Banks
f
For more information, refer to the PLLs in Arria GX Devices chapter in
volume 2 of the Arria GX Device Handbook.
Voltage Levels
Arria GX devices specify a range of allowed voltage levels for supported
I/O standards. Table 8–4 shows only typical values for input and output
VCCIO, VREF, as well as the board VTT.
Table 8–4. Arria GX I/O Standards & Voltage Levels (Part 1 of 2) Note (1)
Arria GX
VCCIO (V)
I/O Standard
Input Operation
Top &
Bottom I/O
Banks
VREF (V)
VTT (V)
Input
Termination
Output Operation
Left & Right Top & Bottom Left & Right
I/O Banks (3)
I/O Banks I/O Banks (3)
LVTTL
3.3/2.5
3.3/2.5
3.3
3.3
NA
NA
LVCMOS
3.3/2.5
3.3/2.5
3.3
3.3
NA
NA
2.5 V
3.3/2.5
3.3/2.5
2.5
2.5
NA
NA
1.8 V
1.8/1.5
1.8/1.5
1.8
1.8
NA
NA
1.5 V
1.8/1.5
1.8/1.5
1.5
1.5
NA
NA
3.3-V PCI
3.3
NA
3.3
NA
NA
NA
3.3-V PCI-X
3.3
NA
3.3
NA
NA
NA
SSTL-2 Class I
2.5
2.5
2.5
2.5
1.25
1.25
SSTL-2 Class II
2.5
2.5
2.5
2.5
1.25
1.25
SSTL-18 Class I
1.8
1.8
1.8
1.8
0.90
0.90
SSTL-18 Class II
1.8
1.8
1.8
NA
0.90
0.90
1.8-V HSTL Class I
1.8
1.8
1.8
1.8
0.90
0.90
1.8-V HSTL Class II
1.8
1.8
1.8
NA
0.90
0.90
1.5-V HSTL Class I
1.5
1.5
1.5
1.5
0.75
0.75
1.5-V HSTL Class II
1.5
1.5
1.5
NA
0.75
0.75
1.2-V HSTL (4)
1.2
NA
1.2
NA
0.6
NA
Differential SSTL-2
Class I
2.5
2.5
2.5
2.5
1.25
1.25
Differential SSTL-2
Class II
2.5
2.5
2.5
2.5
1.25
1.25
Differential SSTL-18
Class I
1.8
1.8
1.8
1.8
0.90
0.90
8–24
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Table 8–4. Arria GX I/O Standards & Voltage Levels (Part 2 of 2) Note (1)
Arria GX
VCCIO (V)
Input Operation
I/O Standard
Top &
Bottom I/O
Banks
VREF (V)
VTT (V)
Input
Termination
Output Operation
Left & Right Top & Bottom Left & Right
I/O Banks (3)
I/O Banks I/O Banks (3)
Differential SSTL-18
Class II
1.8
1.8
1.8
NA
0.90
0.90
1.8-V differential
HSTL Class I
1.8
1.8
1.8
NA
0.90
0.90
1.8-V differential
HSTL Class II
1.8
1.8
1.8
NA
0.90
0.90
1.5-V differential
HSTL Class I
1.5
1.5
1.5
NA
0.75
0.75
1.5-V differential
HSTL Class II
1.5
1.5
1.5
NA
0.75
0.75
LVDS (2)
3.3/2.5/1.8/1.5
2.5
3.3
2.5
NA
NA
NA
2.5
NA
2.5
NA
NA
3.3/2.5/1.8/1.5
NA
3.3
NA
NA
NA
HyperTransport
technology
Differential LVPECL
(2)
Notes to Table 8–4:
(1)
(2)
(3)
(4)
Any input pins with PCI-clamping-diode enabled force the VCCIO to 3.3 V.
LVDS and LVPECL output operation in the top and bottom banks is only supported in PLL banks 9-12. The VCCIO
level for differential output operation in the PLL banks is 3.3 V. The VCCIO level for output operation in the left and
right I/O banks is 2.5 V.
The right I/O bank on Arria GX devices consists of transceivers.
1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
f
On-Chip
Termination
Altera Corporation
May 2008
Refer to the DC & Switching Characteristics chapter in volume 1 of the
Arria GX Device Handbook for detailed electrical characteristics of each
I/O standard.
Arria GX devices feature on-chip series termination to provide I/O
impedance matching and termination capabilities. Apart from
maintaining signal integrity, this feature also minimizes the need for
external resistor networks, thereby saving board space and reducing
costs.
8–25
Arria GX Device Handbook, Volume 2
On-Chip Termination
Arria GX devices support on-chip series (RS) termination for single-ended
I/O standards and on-chip differential termination (RD) for differential
I/O standards. This section discusses the on-chip series termination
support.
f
For more information about differential on-chip termination, refer to the
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter
in volume 2 of the Arria GX Device Handbook.
Arria GX devices support I/O driver on-chip series (RS) termination
through drive strength control for single-ended I/Os.
On-Chip Series Termination without Calibration
Arria GX devices support driver impedance matching to provide the I/O
driver with controlled output impedance that closely matches the
impedance of the transmission line. As a result, reflections can be
significantly reduced. Arria GX devices support on-chip series
termination for single-ended I/O standards (see Figure 8–22). The RS
shown in Figure 8–22 is the intrinsic impedance of transistors. The typical
RS values are 25 Ω and 50 Ω . Once matching impedance is selected,
current drive strength is no longer selectable.
Figure 8–22. Arria GX On-Chip Series Termination without Calibration
Stratix II Driver
Series Impedance
Receiving
Device
VCCIO
RS
ZO
RS
GND
8–26
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Table 8–5 shows the list of output standards that support on-chip series
termination without calibration.
Table 8–5. Selectable I/O Drivers with On-Chip Series Termination without
Calibration
On-chip Series Termination Setting
I/O Standard
Row I/O
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
Column I/O
Unit
50
50
Ω
25
25
Ω
50
50
Ω
25
25
Ω
50
50
Ω
25
25
Ω
50
50
Ω
25
25
Ω
50
50
50
Ω
25
Ω
50
Ω
25
Ω
1.5-V LVTTL
50
50
Ω
1.5-V LVCMOS
50
50
Ω
SSTL-2 Class I
50
50
Ω
SSTL-2 Class II
25
25
Ω
SSTL-18 Class I
50
SSTL-18 Class II
1.8-V HSTL Class I
50
1.8-V HSTL Class II
1.5-V HSTL Class I
50
1.2-V HSTL (1)
50
Ω
25
Ω
50
Ω
25
Ω
50
Ω
50
Ω
Note to Table 8–5:
(1)
1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
To use on-chip termination for the SSTL Class I standard, select the 50-Ω
on-chip series termination setting for replacing the external 25-Ω RS (to
match the 50-Ω transmission line). For the SSTL Class II standard, select
the 25-Ω on-chip series termination setting (to match the 50-Ω
transmission line and the near end 50-Ω pull-up to VTT).
Altera Corporation
May 2008
8–27
Arria GX Device Handbook, Volume 2
Design Considerations
f
Design
Considerations
For more information about tolerance specifications for on-chip
termination without calibration, refer to the DC & Switching
Characteristics chapter in volume 1 of the Arria GX Device Handbook.
While Arria GX devices feature various I/O capabilities for
high-performance and high-speed system designs, there are several other
considerations that require attention to ensure the success of those
designs.
I/O Termination
I/O termination requirements for single-ended and differential I/O
standards are discussed in this section.
Single-Ended I/O Standards
Although single-ended, non-voltage-referenced I/O standards do not
require termination, impedance matching is necessary to reduce
reflections and improve signal integrity.
Voltage-referenced I/O standards require both an input reference
voltage, VREF, and a termination voltage, VTT. The reference voltage of the
receiving device tracks the termination voltage of the transmitting device.
Each voltage-referenced I/O standard requires a unique termination
setup. For example, a proper resistive signal termination scheme is critical
in SSTL standards to produce a reliable DDR memory system with
superior noise margin.
Arria GX on-chip series termination provides the convenience of no
external components. External pull-up resistors can be used to terminate
the voltage-referenced I/O standards such as SSTL-2 and HSTL.
1
Refer to “Arria GX I/O Standards Support” on page 8–2 for
more information about the termination scheme of various
single-ended I/O standards.
Differential I/O Standards
Differential I/O standards typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the bus. Arria GX devices
provide an optional differential on-chip resistor when using LVDS and
HyperTransport standards.
8–28
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
I/O Banks Restrictions
Each I/O bank can simultaneously support multiple I/O standards. The
following sections provide guidelines for mixing non-voltage-referenced
and voltage-referenced I/O standards in Arria GX devices.
Non-Voltage-Referenced Standards
Each Arria GX device I/O bank has its own VCCIO pins and supports only
one VCCIO, either 1.5, 1.8, 2.5, or 3.3 V. An I/O bank can simultaneously
support any number of input signals with different I/O standard
assignments, as shown in Table 8–6.
For output signals, a single I/O bank supports non-voltage-referenced
output signals that are driving at the same voltage as VCCIO. Since an I/O
bank can only have one VCCIO value, it can only drive out that one value
for non-voltage-referenced signals. For example, an I/O bank with a
2.5-V VCCIO setting can support 2.5-V standard inputs and outputs and
3.3-V LVCMOS inputs (not output or bidirectional pins).
Table 8–6. Acceptable Input Levels for LVTTL & LVCMOS
Acceptable Input Levels (V)
Bank VCCIO
(V)
3.3
2.5
3.3
v
v (1)
1.8
1.5
2.5
v
v
1.8
v (2)
v (2)
v
v (1)
1.5
v (2)
v (2)
v
v
Notes to Table 8–6:
(1)
(2)
Altera Corporation
May 2008
Because the input signal does not drive to the rail, the input buffer does not
completely shut off, and the I/O current is slightly higher than the default value.
These input values overdrive the input buffer, so the pin leakage current is
slightly higher than the default value. To drive inputs higher than VCCIO but less
than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL and
LVCMOS input levels to overdrive input buffer option in the Quartus II
software.
8–29
Arria GX Device Handbook, Volume 2
Design Considerations
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Arria GX
device’s I/O bank supports multiple VREF pins feeding a common VREF
bus. The number of available VREF pins increases as device density
increases. If these pins are not used as VREF pins, they cannot be used as
generic I/O pins. However, each bank can only have a single VCCIO
voltage level and a single VREF voltage level at a given time.
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards
use the same VREF setting.
Because of performance reasons, voltage-referenced input standards use
their own VCCIO level as the power source. For example, you can only
place 1.5-V HSTL input pins in an I/O bank with a 1.5-V VCCIO.
1
Refer to “Arria GX I/O Banks” on page 8–20 for details about
input VCCIO for voltage-referenced standards.
Voltage-referenced bidirectional and output signals must be the same as
the I/O bank’s VCCIO voltage. For example, you can only place SSTL-2
output pins in an I/O bank with a 2.5-V VCCIO.
1
Refer to “I/O Placement Guidelines” on page 8–30 for details
about voltage-referenced I/O standards placement.
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both non-voltage-referenced and
voltage-referenced pins by applying each of the rule sets individually. For
example, an I/O bank can support SSTL-18 inputs and 1.8-V inputs and
outputs with a 1.8-V VCCIO and a 0.9-V VREF. Similarly, an I/O bank can
support 1.5-V standards, 2.5-V (inputs, but not outputs), and HSTL I/O
standards with a 1.5-V VCCIO and 0.75-V VREF.
I/O Placement Guidelines
The I/O placement guidelines help to reduce noise issues that may be
associated with a design such that Arria GX devices can maintain an
acceptable noise level on the VCCIO supply. Because Arria GX devices
require each bank to be powered separately for VCCIO, these noise issues
have no effect when crossing bank boundaries and, as such, these rules
need not be applied.
8–30
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
This section provides I/O placement guidelines for the programmable
I/O standards supported by Arria GX devices and includes essential
information for designing systems using their devices’ selectable I/O
capabilities.
VREF Pin Placement Restrictions
There are at least two dedicated VREF pins per I/O bank to drive the VREF
bus. Larger Arria GX devices have more VREF pins per I/O bank. All VREF
pins within one I/O bank are shorted together at device die level.
There are limits to the number of pins that a VREF pin can support. For
example, each output pin adds some noise to the VREF level and an
excessive number of outputs make the level too unstable to be used for
incoming signals.
Restrictions on the placement of single-ended voltage-referenced I/O
pads with respect to VREF pins help maintain an acceptable noise level on
the VCCIO supply and prevent output switching noise from shifting the
VREF rail.
Input Pins
Each VREF pin supports a maximum of 40 input pads.
Output Pins
When a voltage-referenced input or bidirectional pad does not exist in a
bank, the number of output pads that can be used in that bank depends
on the total number of available pads in that same bank. However, when
a voltage-referenced input exists, a design can use up to 20 output pads
per VREF pin in a bank.
Bidirectional Pins
Bidirectional pads must satisfy both input and output guidelines
simultaneously. The general formulas for input and output rules are
shown in Table 8–7.
Table 8–7. Bidirectional Pin Limitation Formulas
Rules
Altera Corporation
May 2008
Formulas
Input
<Total number of bidirectional pins> + <Total number of VREF
input pins, if any> ≤ 40 per VREF pin
Output
<Total number of bidirectional pins> + <Total number of
output pins, if any> – <Total number of pins from smallest
OE group, if more than one OE groups> ≤ 20 per VREF pin
8–31
Arria GX Device Handbook, Volume 2
Design Considerations
■
If the same output enable (OE) controls all the bidirectional pads
(bidirectional pads in the same OE group are driving in and out at the
same time) and there are no other outputs or voltage-referenced
inputs in the bank, the voltage-referenced input is never active at the
same time as an output. Therefore, the output limitation rule does
not apply. However, since the bidirectional pads are linked to the
same OE, the bidirectional pads will all act as inputs at the same time.
Therefore, there is a limit of 40 input pads, as follows:
<Total number of bidirectional pins> + <Total number of VREF input pins>
≤ 40 per VREF pin
■
If any of the bidirectional pads are controlled by different OE and
there are no other outputs or voltage-referenced inputs in the bank,
one group of bidirectional pads can be used as inputs and another
group is used as outputs. In such cases, the formula for the output
rule is simplified, as follows:
<Total number of bidirectional pins> – <Total number of pins from smallest
OE group> ≤ 20 per VREF pin
■
Consider a case where eight bidirectional pads are controlled by
OE1, eight bidirectional pads are controlled by OE2, six bidirectional
pads are controlled by OE3, and there are no other outputs or
voltage-referenced inputs in the bank. While this totals 22
bidirectional pads, it is safely allowable because there would be a
possible maximum of 16 outputs per VREF pin, assuming the worst
case where OE1 and OE2 are active and OE3 is inactive. This is useful
for DDR SDRAM applications.
■
When at least one additional voltage-referenced input and no other
outputs exist in the same VREF group, the bidirectional pad limitation
must simultaneously adhere to the input and output limitations. The
input rule becomes:
<Total number of bidirectional pins> + <Total number of VREF input pins>
≤ 40 per VREF pin
Whereas the output rule is simplified as:
<Total number of bidirectional pins> 20 per VREF pin
■
When at least one additional output exists but no voltage-referenced
inputs exist, the output rule becomes:
<Total number of bidirectional pins> + <Total number of output pins> –
<Total number of pins from smallest OE group> ≤ 0 per VREF pin
8–32
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
■
When additional voltage-referenced inputs and other outputs exist
in the same VREF group, the bidirectional pad limitation must again
simultaneously adhere to the input and output limitations. The input
rule is:
<Total number of bidirectional pins> + <Total number of VREF input pins>
≤ 40 per VREF pin
Whereas the output rule is given as:
<Total number of bidirectional pins> + <Total number of output pins> –
<Total number of pins from smallest OE group> ≤ 0 per VREF pin
I/O Pin Placement with Respect to High-Speed Differential I/O Pins
Regardless of whether or not the SERDES circuitry is utilized, there is a
restriction on the placement of single-ended output pins with respect to
high-speed differential I/O pins. As shown in Figure 8–23, all
single-ended outputs must be placed at least one LAB row away from the
differential I/O pins. There are no restrictions on the placement of
single-ended input pins with respect to differential I/O pins.
Single-ended input pins may be placed within the same LAB row as
differential I/O pins. However, the single-ended input’s IOE register is
not available. The input must be implemented within the core logic.
This single-ended output pin placement restriction only applies when
using the LVDS or HyperTransport I/O standards in the left I/O banks.
There are no restrictions for single-ended output pin placement with
respect to differential clock pins in the top and bottom I/O banks.
Altera Corporation
May 2008
8–33
Arria GX Device Handbook, Volume 2
Design Considerations
Figure 8–23. Single-Ended Output Pin Placement with Respect to Differential
I/O Pins
Single-Ended Output Pin
Differential I/O Pin
Single_Ended Input
Single-Ended Outputs
Not Allowed
Row Boundary
DC Guidelines
Power budgets are essential to ensure the reliability and functionality of
a system application. You are often required to perform power
dissipation analysis on each device in the system to come out with the
total power dissipated in that system, which is composed of a static
component and a dynamic component.
The static power consumption of a device is the total DC current flowing
from VCCIO to ground.
For any ten consecutive pads in an I/O bank of an Arria GX device, Altera
recommends a maximum current of 250 mA, as shown in Figure 8–24,
because the placement of VCCIO/ground (GND) bumps are regular,
10 I/O pins per pair of power pins. This limit is on the static power
consumed by an I/O standard, as shown in Table 8–8. Limiting static
power is a way to improve reliability over the lifetime of the device.
8–34
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Figure 8–24. DC Current Density Restriction Notes (1), (2)
I/O Pin Sequence
of an I/O Bank
VCC
Any 10 Consecutive Output Pins
pin+9
∑ I pin
≤ 250mA
pin
GND
VCC
Notes to Figure 8–24:
(1)
(2)
The consecutive pads do not cross I/O banks.
VREF pins do not affect DC current calculation because there are no VREF pads.
Table 8–8 shows the I/O standard DC current specification.
Table 8–8. Arria GX I/O Standard DC Current Specification (Part 1 of 2) Note (1)
IPIN (mA), Top & Bottom I/O Banks
IPIN (mA), Left I/O Banks (2)
LVTTL
(3)
(3)
LVCMOS
(3)
(3)
I/O Standard
Altera Corporation
May 2008
8–35
Arria GX Device Handbook, Volume 2
Design Considerations
Table 8–8. Arria GX I/O Standard DC Current Specification (Part 2 of 2) Note (1)
IPIN (mA), Top & Bottom I/O Banks
IPIN (mA), Left I/O Banks (2)
2.5 V
(3)
(3)
1.8 V
(3)
(3)
I/O Standard
1.5 V
(3)
(3)
3.3-V PCI
1.5
NA
3.3-V PCI-X
SSTL-2 Class I
1.5
NA
12 (4)
12 (4)
SSTL-2 Class II
24 (4)
16 (4)
SSTL-18 Class I
12 (4)
10 ((4)
SSTL-18 Class II
20 (4)
NA
1.8-V HSTL Class I
12 (4)
12
1.8-V HSTL Class II
20 (4)
NA
1.5-V HSTL Class I
12 (4)
8
1.5-V HSTL Class II
20 (4)
NA
12
12
Differential SSTL-2 Class I
Differential SSTL-2 Class II
24
16
Differential SSTL-18 Class I
12
10
Differential SSTL-18 Class II
20
NA
1.8-V differential HSTL Class I
12
12
1.8-V differential HSTL Class II
20
NA
1.5-V differential HSTL Class I
12
8
1.5-V differential HSTL Class II
20
NA
LVDS
12
12
HyperTransport technology
NA
16
Differential LVPECL
10
10
Notes to Table 8–8:
(1)
(2)
(3)
(4)
The current value obtained for differential HSTL and differential SSTL standards is per pin and not per differential
pair, as opposed to the per-pair current value of LVDS and HyperTransport standards.
This does not apply to the right I/O banks of Arria GX devices. Arria GX devices have transceivers on the right
I/O banks.
The DC power specification of each I/O standard depends on the current sourcing and sinking capabilities of the
I/O buffer programmed with that standard, as well as the load being driven. LVTTL, LVCMOS, 2.5-V, 1.8-V, and
1.5-V outputs are not included in the static power calculations because they normally do not have resistor loads in
real applications. The voltage swing is rail-to-rail with capacitive load only. There is no DC current in the system.
This IPIN value represents the DC current specification for the default current strength of the I/O standard. The IPIN
varies with programmable drive strength and is the same as the drive strength as set in Quartus II software. Refer
to the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook for a detailed description of the
programmable drive strength feature of voltage-referenced I/O standards.
8–36
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Selectable I/O Standards in Arria GX Devices
Table 8–8 only shows the limit on the static power consumed by an I/O
standard. The amount of power used at any given moment could be
much higher, and is based on the switching activities.
Conclusion
Arria GX devices provide I/O capabilities that allow you to work in
compliance with current and emerging I/O standards and requirements.
With the Arria GX device features, such as programmable driver
strength, you can reduce board design interface costs and increase the
development flexibility.
References
Refer to the following references for more information:
■
■
■
■
■
■
■
■
■
■
Altera Corporation
May 2008
Interface Standard for Nominal 3V/ 3.3-V Supply Digital Integrated
Circuits, JESD8-B, Electronic Industries Association, September 1999.
2.5-V +/- 0.2V (Normal Range) and 1.8-V to 2.7V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-5, Electronic Industries
Association, October 1995.
1.8-V +/- 0.15 V (Normal Range) and 1.2 V - 1.95 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-7, Electronic Industries
Association, February 1997.
1.5-V +/- 0.1 V (Normal Range) and 0.9 V - 1.6 V (Wide Range) Power
Supply Voltage and Interface Standard for Non-terminated Digital
Integrated Circuits, JESD8-11, Electronic Industries Association,
October 2000.
PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group,
December 1998.
PCI-X Local Bus Specification, Revision 1.0a, PCI Special Interest
Group.
Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9A,
Electronic Industries Association, December 2000.
Stub Series Terminated Logic for 1.8 V (SSTL-18), Preliminary JC42.3,
Electronic Industries Association.
High-Speed Transceiver Logic (HSTL)—A 1.5-V Output Buffer
Supply Voltage Based Interface Standard for Digital Integrated
Circuits, EIA/JESD8-6, Electronic Industries Association, August
1995.
Electrical Characteristics of Low Voltage Differential Signaling
(LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National
Standards Institute/Telecommunications Industry/Electronic
Industries Association, October 1995.
8–37
Arria GX Device Handbook, Volume 2
Referenced Documents
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
Document
Revision History
Arria GX Architecture chapter in volume 1 of the Arria GX Device
Handbook
DC & Switching Characteristics chapter in volume 1 of the Arria GX
Device Handbook
External Memory Interfaces in Arria GX Devices chapter in volume 2 of
the Arria GX Device Handbook
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook
PLLs in Arria GX Devices chapter in volume 2 of the Arria GX Device
Handbook
Table 8–9 shows the revision history for this chapter.
Table 8–9. Document Revision History
Date and
Document
Version
May 2008
v1.2
Changes Made
Updated “1.5-V HSTL Class I & 1.5-V HSTL Class II”
section.
Summary of Changes
—
Minor text edits.
—
August 2007
v1.1
Added the “Referenced Documents” section.
—
Minor text edits.
—
May 2007
v1.0
Initial release.
—
8–38
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
9. High-Speed Differential I/O
Interfaces with DPA in Arria GX
Devices
AGX52009-1.2
Introduction
The Arria™ GX device family offers up to 840-Mbps differential I/O
capabilities to support source-synchronous communication protocols
such as HyperTransport™ technology, Rapid I/O, XSBI, and SPI.
Arria GX devices have the following dedicated circuitry for high-speed
differential I/O support:
■
■
■
■
■
■
■
Differential I/O buffer
Transmit serializer
Receive deserializer
Data realignment circuit
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Analog phased locked loop (PLLs) and fast PLLs
For high-speed differential interfaces, Arria GX devices can
accommodate different differential I/O standards, including the
following:
■
■
■
■
■
1
LVDS
HyperTransport technology
HSTL
SSTL
LVPECL
HSTL, SSTL, and LVPECL I/O standards can be used only for
PLL clock inputs and outputs in differential mode.
This chapter contains the following sections:
■
■
■
■
■
■
■
■
Altera Corporation
May 2008
“I/O Banks” on page 9–2
“Differential Transmitter” on page 9–3
“Differential Receiver” on page 9–6
“Differential I/O Termination” on page 9–10
“Fast PLL ” on page 9–10
“Clocking” on page 9–11
“Differential Pin Placement Guidelines” on page 9–18
“Board Design Considerations” on page 9–23
9–1
I/O Banks
I/O Banks
Arria GX inputs and outputs are partitioned into banks located on the
periphery of the die. The inputs and outputs that support LVDS and
HyperTransport technology are located in row I/O banks, on the left side
of the Arria GX device. LVPECL, HSTL, and SSTL standards are
supported on certain top and bottom banks of the die (banks 9 to 12)
when used as differential clock inputs/outputs. Differential HSTL and
SSTL standards can be supported on banks 3, 4, 7, and 8 if the pins on
these banks are used as DQS pins. Figure 9–1 shows where the banks and
the PLLs are located on the die.
Figure 9–1. Arria GX I/O Banks Notes (1), (2), (3), (4), (5), and (6)
DQS ×8
PLL7
DQS ×8
DQS ×8
DQS ×8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
Bank 2
VREF0B2 VREF1B2
VREF2B2
VREF3B2 VREF4B2
Bank 3
Bank 11
VREF3B1 VREF4B1
Bank 1
VREF2B1
DQS ×8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
Bank 4
Bank 9
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output
operations. HSTL, SSTL-18 class II,
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
PLL2
VREF0B1 VREF1B1
PLL5
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
PLL1
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 12
Bank 10
PLL12
PLL6
Transmitter: Bank 13
Receiver: Bank 13
REFCLK: Bank 13
Transmitter: Bank 14
Receiver: Bank 14
REFCLK: Bank 14
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
This I/O bank supports LVDS
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
and LVPECL standards for input clock
Differential HSTL and differential
operation. Differential HSTL and differential
SSTL standards are supported
SSTL standards are supported
for both input and output operations. (3)
for both input and output operations. (3)
Bank 8
PLL8
PLL11
Transmitter: Bank 15
Receiver: Bank 15
REFCLK: Bank 15
Bank 7
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Notes to Figure 9–1:
(1)
(2)
(3)
(4)
(5)
(6)
Figure 9–1 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
Depending on size of the device, different device members have different numbers of VREF groups. Refer to the pin
list and the Quartus® II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
Horizontal I/O banks feature transceiver and dynamic phase alignment (DPA) circuitry for high speed differential
I/O standards.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks.
Number of available PLLs and corresponding I/O banks vary with package options.
9–2
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Table 9–1 shows the total number of differential channels available in
Arria GX devices. Non-dedicated clocks in the left bank can also be used
as data receiver channels. The total number of receiver channels includes
these four non-dedicated clock channels. Pin migration is available for
different size devices in the same package.
Table 9–1. Differential Channels in Arria GX Devices
Notes (1), (2)
484-Pin FineLine
BGA
780-Pin FineLine
BGA
1,152-Pin FineLine
BGA
EP1AGX20
29 transmitters
31receivers
29 transmitters
31receivers
—
EP1AGX35
29 transmitters
31 receivers
29 transmitters
31receivers
—
EP1AGX50
29 transmitters
31 receivers
29 transmitters
31 receivers
42 transmitters
42 receivers
EP1AGX60
29 transmitters
31 receivers
29 transmitters
31 receivers
42 transmitters
42 receivers
EP1AGX90
—
—
47 transmitters
47 receivers
Device
Notes to Table 9–1:
(1)
(2)
Differential
Transmitter
Altera Corporation
May 2008
Pin count does not include dedicated PLL input pins.
The total number of receiver channels includes the four non-dedicated clock
channels that can optionally be used as data channels.
The Arria GX transmitter has dedicated circuitry to provide support for
LVDS and HyperTransport signaling. The dedicated circuitry consists of
a differential buffer, a serializer, and a shared fast PLL. The differential
buffer can drive out LVDS or HyperTransport signal levels that are
statically set in the Quartus II software. The serializer takes data from a
parallel bus up to 10-bits wide from the internal logic, clocks it into the
load registers, and serializes it using the shift registers before sending the
data to the differential buffer. The most significant bit (MSB) is
transmitted first. The load and shift registers are clocked by the
diffioclk (a fast PLL clock running at the serial rate) and controlled by
the load enable signal generated from the fast PLL. The serialization
factor can be statically set to × 4, × 5, × 6, × 7, × 8, × 9, or × 10 using the
Quartus II software. The load enable signal is automatically generated by
the fast PLL and is derived from the serialization factor setting. Figure 9–2
is a block diagram of the Arria GX transmitter.
9–3
Arria GX Device Handbook, Volume 2
Differential Transmitter
Figure 9–2. Transmitter Block Diagram
Serializer
10
TX_OUT
Internal
Logic
diffioclk
Fast PLL
load_en
Each Arria GX transmitter data channel can be configured to operate as a
transmitter clock output. This flexibility allows the designer to place the
output clock near the data outputs to simplify board layout and reduce
clock-to-data skew. Different applications often require specific
clock-to-data alignments or specific data-rate to clock-rate factors. The
transmitter can output a clock signal at the same rate as the data with a
maximum frequency of 717 MHz. The output clock can also be divided by
a factor of 2, 4, 8, or 10, depending on the serialization factor. The phase
of the clock in relation to the data can be set at 0° or 180° (edge or center
aligned). The fast PLL provides additional support for other phase shifts
in 45° increments. These settings are made statically in the Quartus II
MegaWizard® software. Figure 9–3 shows the transmitter in clock output
mode.
9–4
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Figure 9–3. Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
tx_outclock
Internal
Logic
diffioclk
load_en
The serializer can be bypassed to support DDR (× 2) and SDR (× 1)
operations. The I/O element (IOE) contains two data output registers that
each can operate in either DDR or SDR mode. The clock source for the
registers in the IOE can come from any routing resource, from the fast
PLL, or from the enhanced PLL. Figure 9–4 shows the bypass path.
Figure 9–4. Serializer Bypass
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
Internal Logic
tx_out
Serializer
Not used (connection exists)
Altera Corporation
May 2008
9–5
Arria GX Device Handbook, Volume 2
Differential Receiver
Differential
Receiver
The receiver has dedicated circuitry to support high-speed LVDS and
HyperTransport signaling, along with enhanced data reception. Each
receiver consists of a differential buffer, dynamic phase aligner (DPA),
synchronization FIFO buffer, data realignment circuit, deserializer, and a
shared fast PLL. The differential buffer receives LVDS or HyperTransport
signal levels, which are statically set by the Quartus II software. The DPA
block aligns the incoming data to one of eight clock phases to maximize
the receiver’s skew margin. The DPA circuit can be bypassed on a
channel-by-channel basis if it is not needed. Set the DPA bypass statically
in the Quartus II MegaWizard Plug-In Manager or dynamically by using
the optional RX_DPLL_ENABLE port.
The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that
compensates for any phase difference between the DPA block and the
deserializer. If necessary, the data realignment circuit inserts a single bit
of latency in the serial bitstream to align the word boundary. The
deserializer includes shift registers and parallel load registers, and sends
a maximum of 10 bits to the internal logic. The data path in the receiver is
clocked by either the diffioclk signal or the DPA recovered clock. The
deserialization factor can be statically set to 4, 5, 6, 7, 8, 9, or 10 by using
the Quartus II software. The fast PLL automatically generates the load
enable signal, which is derived from the deserialization factor setting.
Figure 9–5 shows a block diagram of the receiver.
Figure 9–5. Receiver Block Diagram
DPA Bypass Multiplexer
Up to 840 Mbps
+
–
D
Q
Data
Realignment
Circuitry
10
Internal
Logic
Dedicated
Receiver
Interface
data retimed_data
DPA
Synchronizer
DPA_clk
Eight Phase Clocks
8
rx_inclk
Fast
PLL
9–6
Arria GX Device Handbook, Volume 2
diffioclk
load_en
Regional or
Global Clock
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
The deserializer, like the serializer, can also be bypassed to support DDR
(× 2) and SDR (× 1) operations. The DPA and data realignment circuit
cannot be used when the deserializer is bypassed. The IOE contains two
data input registers that can operate in DDR or SDR mode. The clock
source for the registers in the IOE can come from any routing resource,
from the fast PLL, or from the enhanced PLL. Figure 9–6 shows the
bypass path.
Figure 9–6. Deserializer Bypass
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
rx_in
Deserializer
PLD Logic
Array
DPA
Circuitry
Receiver Data Realignment Circuit
The data realignment circuit aligns the word boundary of the incoming
data by inserting bit latencies into the serial stream. An optional
RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each
receiver independently controlled from the internal logic. The data slips
one bit for every pulse on the RX_CHANNEL_DATA_ALIGN port. The
following are requirements for the RX_CHANNEL_DATA_ALIGN port:
■
■
■
■
Altera Corporation
May 2008
The minimum pulse width is one period of the parallel clock in the
logic array.
The minimum low time between pulses is one period of parallel
clock.
There is no maximum high or low time.
Valid data is available two parallel clock cycles after the rising edge
of RX_CHANNEL_DATA_ALIGN.
9–7
Arria GX Device Handbook, Volume 2
Differential Receiver
Figure 9–7 shows receiver output (RX_OUT) after one bit slip pulse with
the deserialization factor set to 4.
Figure 9–7. Data Realignment Timing
inclk
rx_in
3
1
2
0
3
2
1
0
3
2
1
0
rx_outclock
rx_channel_data_align
3210
rx_out
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion
before a rollover occurs. The programmable bit rollover point can be from
1 to 11 bit-times independent of the deserialization factor. An optional
status port, RX_CDA_MAX, is available to the FPGA from each channel to
indicate when the preset rollover point is reached.
Dynamic Phase Aligner
The DPA block takes in high-speed serial data from the differential input
buffer and selects one of eight phase clocks to sample the data. The DPA
chooses a phase closest to the phase of the serial data. The maximum
phase offset between the data and the phase-aligned clock is 1/8 UI,
which is the maximum quantization error of the DPA. The eight phases
are equally divided, giving a 45° resolution. Figure 9–8 shows the
possible phase relationships between the DPA clocks and the incoming
serial data.
9–8
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Figure 9–8. DPA Clock Phase to Data Bit Relationship
rx_in
D0
D1
D2
D3
D4
Dn
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
Tvco
0.125Tvco
Each DPA block continuously monitors the phase of the incoming data
stream and selects a new clock phase if needed. The selection of a new
clock phase can be prevented by the optional RX_DPLL_HOLD port, which
is available for each channel.
The DPA block requires a training pattern and a training sequence of at
least 256 repetitions of the training pattern. The training pattern is not
fixed, so you can use any training pattern with at least one transition on
each channel. An optional output port, RX_DPA_LOCKED, is available to
the internal logic, to indicate when the DPA block has settled on the
closest phase to the incoming data phase. The RX_DPA_LOCKED
de-asserts, depending on what is selected in the Quartus II MegaWizard
Plug-In, when either a new phase is selected, or when the DPA has moved
two phases in the same direction. The data may still be valid even when
the RX_DPA_LOCKED is deasserted. Use data checkers to validate the data
when RX_DPA_LOCKED is deasserted.
An independent reset port, RX_RESET, is available to reset the DPA
circuitry. The DPA circuit must be retrained after reset.
Synchronizer
The synchronizer is a 1-bit × 6-bit deep FIFO buffer that compensates for
the phase difference between the recovered clock from the DPA circuit
and the diffioclk that clocks the rest of the logic in the receiver. The
synchronizer can only compensate for phase differences, not frequency
differences between the data and the receiver’s INCLK. An optional port,
Altera Corporation
May 2008
9–9
Arria GX Device Handbook, Volume 2
Differential I/O Termination
RX_FIFO_RESET, is available to the internal logic to reset the
synchronizer. The synchronizer is automatically reset when the DPA first
locks to the incoming data. Altera® recommends using RX_FIFO_RESET
to reset the synchronizer when the DPA signals a loss-of-lock condition
beyond the initial locking condition.
Differential I/O
Termination
f
Arria GX devices provide an on-chip 100-Ω differential termination
option on each differential receiver channel for LVDS and
HyperTransport standards. The on-chip termination (OCT) eliminates the
need to supply an external termination resistor, simplifying the board
design and reducing reflections caused by stubs between the buffer and
the termination resistor. You can enable on-chip termination in the
Quartus II assignments editor. Differential on-chip termination is
supported across the full range of supported differential data rates.
For more information regarding differential on-chip termination, refer to
the High-Speed I/O Specifications section of the DC & Switching
Characteristics chapter in volume 1 of the Arria GX Device Handbook.
Figure 9–9 illustrates on-chip termination.
Figure 9–9. On-Chip Differential Termination
Arria GX Differential
Receiver with On-Chip
100 Ω Termination
LVDS/HT
Transmitter
Z0 = 50 Ω
RD
Z0 = 50 Ω
On-chip differential termination is supported on all row I/O pins and on
clock pins CLK[0, 2, 8, 10]. The clock pins CLK[1, 3, 9, 11],
and FPLL[7..10]CLK, and the clocks in the top and bottom I/O banks
(CLK[4..7, 12..15]) do not support differential on-chip termination.
Fast PLL
The high-speed differential I/O receiver and transmitter channels use fast
PLL to generate the parallel global clocks (rx- or tx- clock) and highspeed clocks (diffioclk). Figure 9–10 shows the locations of the fast
PLLs. The fast PLL VCO operates at the clock frequency of the data rate.
Each fast PLL offers a single serial data rate support, but up to two
separate serialization and/or deserialization factors (from the C0 and C1
9–10
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
fast PLL clock outputs) can be used. Clock switchover and dynamic fast
PLL reconfiguration is available in high-speed differential I/O support
mode.
f
For additional information about the fast PLL, refer to the PLLs in
Arria GX Devices chapter in volume 2 of the Arria GX Handbook.
Figure 9–10 shows a block diagram of the fast PLL in high-speed
differential I/O support mode.
Figure 9–10. Fast PLL Block Diagram
Global or
regional clock (2)
Clock (1)
Switchover
Circuitry
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
diffioclk0 (3)
4
loaden0 (4)
÷c0
(5)
Clock
Input
Post-Scale
Counters
÷n
PFD
Charge
Pump
Loop
Filter
VCO
÷k
diffioclk1 (3)
8
loaden1 (4)
÷c1
4
Global clocks
÷c2
4
Global or
regional clock (2)
8
Regional clocks
÷c3
÷m
Shaded Portions of the
PLL are Reconfigurable
8
to DPA block
Notes to Figure 9–10:
(1)
(2)
(3)
(4)
(5)
Arria GX fast PLLs only support manual clock switchover.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or pin-driven dedicated global or regional clock.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Arria GX devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
If the design enables this ÷2 counter, the device can use a VCO frequency range of 150 to 520 MHz.
Clocking
Altera Corporation
May 2008
The fast PLLs feed in to the differential receiver and transmitter channels
through the LVDS/DPA clock network. The center fast PLLs can
independently feed the banks above and below them. The corner PLLs
can feed only the banks adjacent to them.
9–11
Arria GX Device Handbook, Volume 2
Clocking
Figures 9–11 and 9–12 show the Fast PLL and LVDS/DPA clock of the
Arria GX devices.
Figure 9–11. Fast PLL and LVDS/DPA Clock for EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, and
EP1AGX60C/D Devices
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
2
Fast
PLL 1
No Fast PLLs on
Right Side of
Arria GX Devices
Fast
PLL 2
4
4
LVDS
Clock
DPA
Clock
9–12
Arria GX Device Handbook, Volume 2
Quadrant
Quadrant
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Figure 9–12. Fast PLL and LVDS/DPA Clocks for EP1AGX60E and EP1AGX90E Devices
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 1
No Fast PLLs on
Right Side of
Arria GX Devices
Fast
PLL 2
2
Quadrant
4
LVDS
Clock
Quadrant
DPA
Clock
2
Fast
PLL 8
Source Synchronous Timing Budget
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Arria GX devices. LVDS and
HyperTransport I/O standards enable high-speed data transmission.
This high data transmission rate results in better overall system
performance. To take advantage of fast system performance, it is
important to understand how to analyze timing for these high-speed
signals. Timing analysis for the differential block is different from
traditional synchronous timing analysis techniques.
Rather than focusing on clock-to-output and setup times,
source-synchronous timing analysis is based on the skew between the
data and the clock signals. High-speed differential data transmission
requires the use of timing parameters provided by IC vendors and is
strongly influenced by board skew, cable skew, and clock jitter. This
section defines the source-synchronous differential data orientation
timing parameters, the timing budget definitions for Arria GX devices,
and how to use these timing parameters to determine a design’s
maximum performance.
Altera Corporation
May 2008
9–13
Arria GX Device Handbook, Volume 2
Clocking
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 840 Mbps and SERDES factor of 10, the external
clock is multiplied by 10, and phase-alignment can be set in the PLL to
coincide with the sampling window of each data bit. The data is sampled
on the falling edge of the multiplied clock. Figure 9–13 shows the data bit
orientation of the × 10 mode.
Figure 9–13. Bit Orientation in the Quartus II Software
inclock/outclock
10 LVDS Bits
MSB
data in
n-1
n-0
9
8
7
6
5
4
3
LSB
2
1
0
high-frequency clock
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies. Figure 9–14 shows the data bit orientation for a channel
operation. These figures are based on the following:
■
■
■
SERDES factor equals clock multiplication factor
Edge alignment is selected for phase alignment
Implemented in hard SERDES
For other serialization factors use the Quartus II software tools and find
the bit position within the word. The bit positions after deserialization are
listed in Table 9–2.
9–14
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Figure 9–14 also shows a functional waveform. Timing waveforms may
produce different results. Altera recommends performing a timing
simulation to predict actual device behavior.
Figure 9–14. Bit Order for One Channel of Differential Data
Transmitter Channel
Operation (x8 Mode)
tx_outclock
Previous Cycle
tx_out
X
X
X
X
X
X
X
Current Cycle
7
X
6
5
4
3
Next Cycle
2
1
MSB
0
X
X
X
X
X
X
X
X
X
X
X
X
LSB
Receiver Channel
Operation (x4 Mode)
rx_inclock
rx_in
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
XXXX
rx_out [3..0]
XXXX
XXXX
3210
Receiver Channel
Operation (x8 Mode)
rx_inclock
rx_in
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
rx_out [7..0]
XXXXXXXX
XXXXXXXX
XXXX7654
3210XXXX
Table 9–2 shows the conventions for differential bit naming for
18 differential channels. The MSB and LSB positions increase with the
number of channels used in a system.
Table 9–2. LVDS Bit Naming (Part 1 of 2)
Altera Corporation
May 2008
Internal 8-Bit Parallel Data
Receiver Channel Data
Number
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
9–15
Arria GX Device Handbook, Volume 2
Clocking
Table 9–2. LVDS Bit Naming (Part 2 of 2)
Receiver Channel Data
Number
Internal 8-Bit Parallel Data
MSB Position
LSB Position
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
17
135
128
18
143
136
Receiver Skew Margin for Non-DPA
Changes in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, the receiver’s setup and hold times, and
internal skew, reduce the sampling window for the receiver. The timing
margin between the receiver’s clock input and the data input sampling
window is called Receiver Skew Margin (RSKM). Figure 9–15 shows the
relationship between the RSKM and the receiver’s sampling window.
TCCS, RSKM, and the sampling window specifications are used for
high-speed source-synchronous differential signals without DPA. When
using DPA, these specifications are exchanged for the simpler single DPA
jitter tolerance specification. For instance, the receiver skew is why each
input with DPA selects a different phase of the clock, thus removing the
requirement for this margin.
9–16
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Figure 9–15. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
Receiver
Input Data
TCCS
/
SW 2
RSKM
/
SW 2
Internal
Clock
Falling Edge
Timing Budget
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
TCCS
/
/
SW 2
SW 2
TCCS
2
Receiver
Input Data
RSKM
Altera Corporation
May 2008
9–17
Arria GX Device Handbook, Volume 2
Differential Pin Placement Guidelines
Differential Pin
Placement
Guidelines
In order to ensure proper high-speed operation, differential pin
placement guidelines have been established. The Quartus II compiler
automatically checks that these guidelines are followed and will issue an
error message if these guidelines are not met. PLL driving distance
information is separated into guidelines with and without DPA usage.
High-Speed Differential I/Os and Single-Ended I/Os
When a differential channel or channels of side banks are used (with or
without DPA), you must adhere to the guidelines described in the
following sections.
■
■
■
■
Single-ended I/Os are allowed in the same bank as the LVDS
channels (with or without DPA) as long as the single-ended I/O
standard uses the same VCCIO as the LVDS bank.
Single-ended inputs can be in the same logic array block (LAB) row.
Outputs cannot be on the same LAB row with LVDS I/Os. If input
registers are used in the I/O cell (IOC), single-ended inputs cannot
be in the same LAB row as an LVDS SERDES block.
LVDS (non-SERDES) I/Os are allowed in the same row as LVDS
SERDES but the use of IOC registers are not allowed.
Single-ended outputs are limited to 120 mA drive strength on LVDS
banks (with or without DPA).
●
LVTTL equation for maximum number of I/Os in an LVDS
bank:
• 120 mA = (number of LVTTL outputs) × (drive strength of
each LVTTL output)
●
SSTL-2 equation:
• 120 mA = (number of SSTL-2 I/Os) × (drive strength of each
output) ÷ 2
LVTTL and SSTL-2 mix equation:
• 120 mA= (total drive strength of all LVTTL outputs) + (total
drive strength of all SSTL2 outputs) ÷ 2
Single-ended inputs can be in the same LAB row as a differential
channel using the SERDES circuitry; however, IOE input registers are
not available for the single-ended I/Os placed in the same LAB row
as differential I/Os. The same rule for input registers applies for
non-SERDES differential inputs placed within the same LAB row as
a SERDES differential channel. The input register must be
implemented within the core logic. The same rule for input registers
applies for non-SERDES differential inputs placed within the same
LAB row as a SERDES differential channel.
Single-ended output pins must be at least one LAB row away from
differential output pins, as shown in Figure 9–16.
●
■
■
9–18
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Figure 9–16. Single-Ended Output Pin Placement with Respect to Differential I/O Pins
Single-Ended Output Pin
Differential I/O Pin
Single_Ended Input
Single-Ended Outputs
Not Allowed
Row Boundary
DPA Usage Guidelines
Arria GX devices have differential receivers and transmitters on the Row
banks of the device. Each receiver has a dedicated DPA circuit to align the
phase of the clock to the data phase of its associated channel. When a
channel or channels are used in DPA mode, the guidelines listed below
must be adhered to.
Fast PLL/DPA Channel Driving Distance
■
■
Altera Corporation
May 2008
If the number of DPA channels driven by each center or corner fast
PLL exceeds 25 LAB rows, Altera recommends you implement data
realignment (bit-slip) circuitry for all the DPA channels.
If one center fast PLL drives DPA channels in the upper and lower
banks, the other center fast PLL cannot be used for DPA.
9–19
Arria GX Device Handbook, Volume 2
Differential Pin Placement Guidelines
Using Corner and Center Fast PLLs
■
■
If a differential bank is being driven by two fast PLLs, where the
corner PLL is driving one group and the center fast PLL is driving
another group, there must be at least one row of separation between
the two groups of DPA channels (see Figure 9–17). The two groups
can operate at independent frequencies. Not all the channels are
bonded out of the die. Each LAB row is considered a channel,
whether or not it has I/O support.
No separation is necessary if a single fast PLL is driving DPA
channels as well as non-DPA channels as long as the DPA channels
are contiguous.
Figure 9–17. Usage of Corner and Center Fast PLLs Driving DPA Channels in a
Single Bank
Fast PLL
Corner PLL
Used for DPA
Ref CLK
Ref Clk
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Channels Driven
by Corner PLL
Diff I/O
Unused
One Unused
Channel for Buffer
Diff I/O
Diff I/O
Channels Driven
by Center PLL
Diff I/O
Diff I/O
Diff I/O
Ref CLK
Fast PLL
9–20
Arria GX Device Handbook, Volume 2
Ref Clk
Center PLL
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Using Both Center Fast PLLs
■
■
Both center fast PLLs can be used for DPA as long as they drive DPA
channels in their adjacent quadrant only (see Figure 9–18).
Both center fast PLLs cannot be used for DPA if one of the fast PLLs
drives the top and bottom banks, or if they are driving cross banks
(for example, the lower fast PLL drives the top bank and the top fast
PLL drives the lower bank).
Figure 9–18. Center Fast PLL Usage When Driving DPA Channels
DPA
DPA
Channels Driven by
the Upper Center PLL
DPA
DPA
DPA
Ref CLK
Ref Clk
Fast PLL
Center PLL
Driving Top Bank
Fast PLL
Center PLL
Driving Lower Bank
Ref CLK
Ref Clk
DPA
DPA
DPA
DPA
Channels Driven by
the Lower Center PLL
DPA
Altera Corporation
May 2008
9–21
Arria GX Device Handbook, Volume 2
Differential Pin Placement Guidelines
Non-DPA Differential I/O Usage Guidelines
When a differential channel or channels of left or right banks are used in
non-DPA mode, you must adhere to the guidelines in the following
sections.
Fast PLL/Differential I/O Driving Distance
■
Each fast PLL can drive all the channels in the entire bank, as shown
in Figure 9–19.
Figure 9–19. Fast PLL Driving Capability When Driving Non-DPA Differential
Channels
Fast PLL
Corner PLL
Ref CLK
Ref CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Each PLL Can Drive
the Entire Bank
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
9–22
Arria GX Device Handbook, Volume 2
Ref CLK
Ref CLK
Fast PLL
Center PLL
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Using Corner and Center Fast PLLs
■
■
■
The corner and center fast PLLs can be used as long as the channels
driven by separate fast PLLs do not have their transmitter or receiver
channels interleaved. Figure 9–20 shows illegal placement of
differential channels when using corner and center fast PLLs.
If one fast PLL is driving transmitter channels only, and the other fast
PLL drives receiver channels only, the channels driven by those fast
PLLs can overlap each other.
Center fast PLLs can be used for both transmitter and receiver
channels.
Figure 9–20. Illegal Placement of Interlaced Duplex Channels in an I/O Bank
Fast PLL
Corner PLL
Ref CLK
Ref CLK
Duplex Channel Driven
by Center PLL
Duplex Channel Driven
by Corner PLL
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Interleaved Duplex
Channel is Not Allowed
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Board Design
Considerations
f
Altera Corporation
May 2008
Ref CLK
Ref CLK
Fast PLL
Center PLL
This section explains how to achieve the optimal performance from the
Arria GX high-speed I/O block and ensure first-time success in
implementing a functional design with optimal signal quality.
For more information about board layout recommendations and I/O pin
terminations, refer to AN 224: High-Speed Board Layout Guidelines.
9–23
Arria GX Device Handbook, Volume 2
Conclusion
To achieve the best performance from the device, pay attention to the
impedances of traces and connectors, differential routing, and
termination techniques.
The Arria GX high-speed module generates signals that travel over the
media at frequencies as high as 840 Mbps. Board designers should use the
following guidelines:
■
■
■
■
■
■
■
■
■
■
■
■
■
Conclusion
Base board designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
Place external reference resistors as close to receiver input pins as
possible.
Use surface mount components.
Avoid 90° or 45° corners.
Use high-performance connectors such as HMZD or VHDM
connectors for backplane designs. Two suppliers of
high-performance connectors are Teradyne Corp
(www.teradyne.com) and Tyco International Ltd. (www.tyco.com).
Design backplane and card traces so that trace impedance matches
the connector’s or the termination’s impedance.
Keep an equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins when the transmitter-channel-to-channel skew (TCCS)
value increases.
Limit vias, because they cause impedance discontinuities.
Use the common bypass capacitor values such as 0.001, 0.01, and
0.1 μF to decouple the fast PLL power and ground planes. You can
also use 0.0047 μF and 0.047 μF.
Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
Do not route transistor-to-transistor logic (TTL) clock signals to areas
under or above the differential signals.
Route signals on adjacent layers orthogonally to each other.
Arria GX high-speed differential inputs and outputs, with their DPA and
data realignment circuitry, allow users to build a robust multi-Gigabit
system. The DPA circuitry allows users to compensate for any timing
skews resulting from physical layouts. The data realignment circuitry
allows the devices to align the data packet between the transmitter and
receiver. Together with the on-chip differential termination, Arria GX
devices can be used as a single-chip solution for high-speed applications.
9–24
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Referenced
Documents
This chapter references the following documents:
■
■
■
Document
Revision History
AN 224: High-Speed Board Layout Guidelines
DC & Switching Characteristics chapter in volume 1 of the Arria GX
Device Handbook
PLLs in Arria GX Devices chapter in volume 2 of the Arria GX
Handbook
Table 9–3 shows the revision history for this chapter.
Table 9–3. Document Revision History
Date and
Document Version
May 2008
v1.2
Changes Made
Updated:
● “DPA Usage Guidelines”
● “Fast PLL/DPA Channel Driving Distance”
Summary of Changes
—
Updated Figure 9–15.
—
Minor text edits.
—
August 2007
v1.1
Added the “Referenced Documents” section.
—
Minor text edits.
—
May 2007
v1.0
Initial release.
—
Altera Corporation
May 2008
9–25
Arria GX Device Handbook, Volume 2
Document Revision History
9–26
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Section V. Digital Signal
Processing (DSP)
This section provides information for design and optimization of digital
signal processing (DSP) functions and arithmetic operations in the
on-chip DSP blocks.
This section contains the following chapter:
■
Revision History
Altera Corporation
Chapter 10, DSP Blocks in Arria GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section V–1
Preliminary
Digital Signal Processing (DSP)
Section V–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
10. DSP Blocks in Arria GX
Devices
AGX52010-1.2
Introduction
ArriaTM GX devices have dedicated digital signal processing (DSP) blocks
optimized for DSP applications requiring high data throughput. These
DSP blocks combined with the flexibility of programmable logic devices
(PLDs), provide you with the ability to implement various high
performance DSP functions easily. Complex systems such as CDMA2000,
voice over Internet protocol (VoIP), and high-definition television
(HDTV) require high performance DSP blocks to process data. These
system designs typically use DSP blocks as finite impulse response (FIR)
filters, complex FIR filters, fast Fourier transform (FFT) functions, discrete
cosine transform (DCT) functions, and correlators.
Arria GX DSP blocks consist of a combination of dedicated blocks that
perform multiplication, addition, subtraction, accumulation, and
summation operations. You can configure these blocks to implement
arithmetic functions like multipliers, multiply-adders and multiplyaccumulators which are necessary for most DSP functions.
Along with the DSP blocks, the TriMatrixTM memory structures in Arria
GX devices also support various soft multiplier implementations. The
combination of soft multipliers and dedicated DSP blocks increases the
number of multipliers available in Arria GX devices and provides you
with a wide variety of implementation options and flexibility when
designing your systems.
f
For more information about Arria GX devices respectively, see the Arria
GX Device Family Data Sheet in volume 1 of the Arria GX Device Handbook.
This chapter contains the following sections:
■
■
■
■
■
■
■
■
Altera Corporation
May 2008
“DSP Block Overview” on page 10–2
“Architecture” on page 10–7
“Accumulator” on page 10–16
“Operational Modes” on page 10–18
“Complex Multiply” on page 10–26
“FIR Filter” on page 10–29
“Software Support” on page 10–31
“Conclusion” on page 10–31
10–1
Preliminary
DSP Blocks in Arria GX Devices
DSP Block
Overview
Each Arria GX device has two to four columns of DSP blocks that
efficiently implement multiplication, multiply-accumulate (MAC) and
multiply-add functions. Figure 10–1 shows the arrangement of one of the
DSP block columns with the surrounding LABs. Each DSP block can be
configured to support:
■
■
■
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
Figure 10–1. DSP Blocks Arranged in Columns with Adjacent LABs
DSP Block
Column
4 LAB
Rows
10–2
Arria GX Device Handbook, Volume 2
DSP Block
Altera Corporation
May 2008
DSP Block Overview
The multipliers then feed an adder or accumulator block within the DSP
block. Arria GX device multipliers support rounding and saturation on
Q1.15 input formats. The DSP block also has input registers that can be
configured to operate in a shift register chain for efficient implementation
of functions such as FIR filters. The accumulator within the DSP block can
be initialized to any value and supports rounding and saturation on
Q1.15 input formats to the multiplier. A single DSP block can be broken
down to operate different configuration modes simultaneously.
1
For more information on Q1.15 formatting, see the section
“Saturation and Rounding” on page 10–11.
The number of DSP blocks per column and the number of columns
available increases with device density.
Table 10–1 shows the number of DSP blocks in each Arria GX device and
the multipliers that you can implement.
Table 10–1. Number of DSP Blocks in Arria GX Devices Note (1)
DSP
Blocks
9×9
Multipliers
18 × 18
Multipliers
36 × 36
Multipliers
EP1AGX20C
10
80
40
10
EP1AGX35C/D
14
112
56
14
EP1AGX50C/D
26
208
104
26
Device
EP1AGX60C/D/E
32
256
128
32
EP1AGX90E
44
352
176
44
Note to Table 10–1:
(1)
Altera Corporation
May 2008
Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
10–3
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
In addition to the DSP block multipliers, you can use the Arria GX
device's TriMatrix memory blocks for soft multipliers. The availability of
soft multipliers increases the number of multipliers available within the
device. Table 10–2 shows the total number of multipliers available in
Arria GX devices using DSP blocks and soft multipliers.
Table 10–2. Number of Multipliers in Arria GX Devices
DSP Blocks
(18 × 18)
Soft Multipliers
(16 × 16) (1), (2)
Total Multipliers
(3), (4)
40
102
142 (3.55)
EP1AGX35C/D
56
122
178 (3.18)
EP1AGX50C/D
104
202
306 (2.94)
Device
EP1AGX20C
EP1AGX60C/D/E
128
211
339 (2.65)
EP1AGX90E
176
324
500 (2.84)
Notes to Table 10–2:
(1)
(2)
(3)
(4)
Soft multipliers implemented in sum of multiplication mode. RAM blocks are
configured with 18-bit data widths and sum of coefficients up to 18-bits.
Soft multipliers are only implemented in M4K and M512 TriMatrix memory
blocks, not M-RAM blocks.
The number in parentheses represents the increase factor, which is the total
number of multipliers with soft multipliers divided by the number of 18 × 18
multipliers supported by DSP blocks only.
The total number of multipliers may vary according to the multiplier mode used.
f
Refer to the Arria GX Architecture chapter in volume 1 of the Arria GX
Device Handbook for more information about Arria GX TriMatrix memory
blocks.
f
Refer to AN 306: Implementing Multipliers in FPGA Devices for more
information on soft multipliers.
10–4
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
DSP Block Overview
Figure 10–2 shows the DSP block configured for 18 × 18 multiplier mode.
Figure 10–2. DSP Block in 18 × 18 Mode
Optional Serial Shift
Register Inputs from
Previous DSP Block
Output
Selection
Multiplexer
Adder Output Block
PRN
D
Multiplier Block
Q
ENA
CLRN
From the row
interface block
PRN
Q1.15
Round/
Saturate
PRN
D
Q
D
Q
ENA
CLRN
ENA
CLRN
D
Adder/
Subtractor/
Accumulator
1
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
D
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
PRN
Q1.15
Round/
Saturate
PRN
Q
D
Q
ENA
CLRN
Summation
Block
ENA
CLRN
Adder
D
Q
ENA
CLRN
D
PRN
Q
ENA
CLRN
PRN
Q1.15
Round/
Saturate
PRN
D
Q
D
Q
ENA
CLRN
D
D
Adder/
Subtractor/
Accumulator
2
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
Optional Serial Shift
Register Outputs to
Next DSP Block
in the Column
Summation Stage
for Adding Four
Multipliers Together
ENA
CLRN
PRN
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
D
Q
ENA
CLRN
Optional Pipline
Register Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
Altera Corporation
May 2008
10–5
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
Figure 10–3 shows the 9 × 9 multiplier configuration of the DSP block.
Figure 10–3. DSP Block in 9 × 9 Mode
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Adder/
Subtractor/
1a
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
CLRN
Summation
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Adder/
Subtractor/
1b
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Output
Selection
Multiplexer
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
D
Q
ENA
CLRN
Adder/
Subtractor/
2a
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
CLRN
Summation
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Adder/
Subtractor/
2b
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
CLRN
To MultiTrack
Interconnect
10–6
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Architecture
Architecture
The DSP block consists of the following elements:
■
■
■
■
■
A multiplier block
An adder/subtractor/accumulator block
A summation block
Input and output interfaces
Input and output registers
Multiplier Block
Each multiplier block has the following elements:
■
■
■
■
Input registers
A multiplier block
A rounding and/or saturation stage for Q1.15 input formats
A pipeline output register
Figure 10–4 shows the multiplier block architecture.
Figure 10–4. Multiplier Block Architecture
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
shiftinb
clock[3..0]
shiftina
ena[3..0]
sourcea
D
Data A
Data Out
Q
ENA
CLRN
sourceb
Q1.15
Round/
Saturate
(3)
D
Data B
Q
ENA
D
Q
ENA
CLRN
(2)
Output
Register
Pipeline
Register
mult_is_saturated
CLRN
D
Q
ENA
CLRN
Multiplier Block
DSP Block
shiftoutb shiftouta
Notes to Figure 10–4:
(1)
(2)
(3)
These signals are not registered or registered once to match the data path pipeline.
You can send these signals through either one or two pipeline registers.
The rounding and/or saturation is only supported in 18 × 18-bit signed multiplication for Q1.15 inputs.
Altera Corporation
May 2008
10–7
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
Input Registers
Each multiplier operand can feed an input register or directly to the
multiplier. The following DSP block signals control each input register
within the DSP block:
■
■
■
clock[3..0]
ena[3..0]
aclr[3..0]
The input registers feed the multiplier and drive two dedicated shift
output lines, shiftouta and shiftoutb. The dedicated shift outputs
from one multiplier block directly feed input registers of the adjacent
multiplier below it within the same DSP block or the first multiplier in the
next DSP block to form a shift register chain, as shown in Figure 10–5. The
dedicated shift register chain spans a single column but longer shift
register chains requiring multiple columns can be implemented using
regular FPGA routing resources. Therefore, this shift register chain can be
of any length up to 768 registers in the largest member of the Arria GX
device family.
Shift registers are useful in DSP functions such as FIR filters. When
implementing 9 × 9 and 18 × 18 multipliers, you do not need external
logic to create the shift register chain because the input shift registers are
internal to the DSP block. This implementation significantly reduces the
LE resources required, avoids routing congestion, and results in
predictable timing.
Arria GX DSP blocks allow you to dynamically select whether a
particular multiplier operand is fed by regular data input or the dedicated
shift register input using the sourcea and sourceb signals. A logic 1
value on the sourcea signal indicates that data A is fed by the dedicated
scan-chain; a logic 0 value indicates that it is fed by regular data input.
This feature allows the implementation of a dynamically loadable shift
register where the shift register operates normally using the scan-chains
and can also be loaded dynamically in parallel using the data input value.
Figure 10–5 shows the shift register chain.
10–8
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Architecture
Figure 10–5. Shift Register Chain Note (1)
DSP Block 0
Data A
D
Q
A[n] × B[n]
ENA
CLRN
Data B
D
Q1.15
Round/
Saturate
D
Q
ENA
CLRN
Q
ENA
CLRN
shiftoutb
shiftouta
D
Q
A[n − 1] × B[n − 1]
ENA
CLRN
D
Q1.15
Round/
Saturate
D
Q
ENA
CLRN
Q
ENA
CLRN
shiftoutb
shiftouta
DSP Block 1
D
Q
A[n − 2] × B[n − 2]
ENA
CLRN
D
Q1.15
Round/
Saturate
D
Q
ENA
CLRN
Q
ENA
CLRN
shiftoutb
shiftouta
Note to Figure 10–5:
(1)
Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication.
Altera Corporation
May 2008
10–9
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
Table 10–3 shows the summary of input register modes for the DSP block.
Table 10–3. Input Register Modes
Register Input
Mode
9×9
18 × 18
36 × 36
Parallel input
v
v
v
Shift register input
v
v
-
Multiplier Stage
The multiplier stage supports 9 × 9, 18 × 18, or 36 × 36 multipliers as well
as other smaller multipliers in between these configurations. See
“Operational Modes” on page 10–18 for details. Depending on the data
width of the multiplier, a single DSP block can perform many
multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number.
Two signals, signa and signb, control the representation of each
operand respectively. A logic 1 value on the signa signal indicates that
data A is a signed number while a logic 0 value indicates an unsigned
number. Table 10–4 shows the sign of the multiplication result for the
various operand sign representations. The result of the multiplication is
signed if any one of the operands is a signed value.
Table 10–4. Multiplier Sign Representation
Data A (signa Value)
Data B (signb Value)
Result
Unsigned (logic 0)
Unsigned (logic 0)
Unsigned
Unsigned (logic 0)
Signed (logic 1)
Signed
Signed (logic 1)
Unsigned (logic 0)
Signed
Signed (logic 1)
Signed (logic 1)
Signed
There is only one signa and one signb signal for each DSP block.
Therefore, all of the data A inputs feeding the same DSP block must have
the same sign representation. Similarly, all of the data B inputs feeding the
same DSP block must have the same sign representation. The multiplier
offers full precision regardless of the sign representation.
1
10–10
Arria GX Device Handbook, Volume 2
When the signa and signb signals are unused, the Quartus® II
software sets the multiplier to perform unsigned multiplication
by default.
Altera Corporation
May 2008
Architecture
Saturation and Rounding
The DSP blocks have hardware support to perform optional saturation
and rounding after each 18 × 18 multiplier for Q1.15 input formats.
1
Designs must use 18 × 18 multipliers for the saturation and
rounding options because the Q1.15 input format requires 16-bit
input widths.
1
Q1.15 input format multiplication requires signed multipliers.
The most significant bit (MSB) in the Q1.15 input format
represents the value's sign bit. Use signed multipliers to ensure
the proper sign extension during multiplication.
The Q1.15 format uses 16 bits to represent each fixed point input. The
MSB is the sign bit, and the remaining 15-bits are used to represent the
value after the decimal place (or the fractional value). This Q1.15 value is
equivalent to an integer number representation of the 16-bits divided by
215, as shown in the following equations.
−
1
2
1
8
= 1 100 0000 0000 0000 = −
= 0 001 0000 0000 0000 =
0x4000
215
0x1000
215
All Q1.15 numbers are between –1 and 1.
When performing multiplication, even though the Q1.15 input only uses
16 of the 18 multiplier inputs, the entire 18-bit input bus is transmitted to
the multiplier. This is similar to a 1.17 input, where the two least
significant bits (LSBs) are always 0.
The multiplier output will be a 2.34 value (36 bits total) before performing
any rounding or saturation. The two MSBs are sign bits. Since the output
only requires one sign bit, you can ignore one of the two MSBs, resulting
in a Q1.34 value before rounding or saturation.
When the design performs saturation, the multiplier output gets
saturated to 0x7FFFFFFF in a 1.31 format. This uses bits [34..3] of the
overall 36-bit multiplier output. The three LSBs are set to 0.
The DSP block obtains the mult_is_saturated or
accum_is_saturated overflow signal value from the LSB of the
multiplier or accumulator output. Therefore, whenever saturation occurs,
the LSB of the multiplier or accumulator output sends a 1 to the
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
mult_is_saturated or accum_is_saturated overflow signal. At
all other times, this overflow signal is 0 when saturation is enabled or
reflects the value of the LSB of the multiplier or accumulator output.
When the design performs rounding, it adds 0x00008000 in 1.31 format to
the multiplier output, and it only uses bits [34..15] of the overall 36-bit
multiplier output. Adding 0x00008000 in 1.31 format to the 36-bit
multiplier result is equivalent to adding 0x0 0004 0000 in 2.34 format. The
16 LSBs are set to 0. Figure 10–6 shows which bits are used when the
design performs rounding and saturation for the multiplication.
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Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Architecture
Figure 10–6. Rounding and Saturation Bits
18 × 18 Multiplication
1 Sign
Bit
15 Bits
2 LSBs
18
00
2 Sign
Bits (1)
31 Bits
3 LSBs
36
000
1 Sign
Bit
15 Bits
2 LSBs
18
00
Saturated Output Result
2 Sign
Bits (1)
31 Bits
1 11
3 LSBs
111000
Rounded Output Result
2 Sign
Bits (1)
31 Bits
2 Sign
Bits (1)
3 LSBs
000
+
15 Bits
18 Bits
0000 000 0 0000 000001 0000 000 0 0000 000000
19 LSBs
are Ignored
=
00 0000 000 0 0000 00000
Note to Figure 10–6:
(1)
Both sign bits are the same. The design only uses one sign bit, and the other one is ignored.
If the design performs a multiply_accumulate or multiply_add
operation, the multiplier output is input to the
adder/subtractor/accumulator blocks as a 2.31 value, and the three LSBs
are 0.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
Pipeline Registers
The output from the multiplier can feed a pipeline register or this register
can be bypassed. Pipeline registers may be implemented for any
multiplier size and increase the DSP block's maximum performance,
especially when using the subsequent DSP block adder stages. Pipeline
registers split up the long signal path between the
adder/subtractor/accumulator block and the adder/output block,
creating two shorter paths.
Adder/Output Block
The adder/output block has the following elements:
■
■
■
■
An adder/subtractor/accumulator block
A summation block
An output select multiplexer
Output registers
The adder/output block can be configured as:
■
■
■
■
■
An output interface
An accumulator which can be optionally loaded
A one-level adder
A two-level adder with dynamic addition/subtraction control on the
first-level adder
The final stage of a 36-bit multiplier, 9 × 9 complex multiplier, or
18 × 18 complex multiplier
The output select multiplexer sets the output configuration of the DSP
block. The output registers can be used to register the output of the
adder/output block.
1
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Arria GX Device Handbook, Volume 2
The adder/output block cannot be used independently from the
multiplier.
Altera Corporation
May 2008
Architecture
Figure 10–7 shows the adder/output block architecture.
Figure 10–7. Adder/Output Block Architecture
adder1_round (2)
Accumulator Feedback
Output Select
Multiplexer
Result A /
accum_sload_upper_data
Output Registers
accum_sload0 (2)
addnsub1 (2)
Adder/
Subtractor/
Accumulator 1
overflow0
Q1.15
Rounding
(3)
Result B
signa (2)
Summation
Output
Register Block
signb (2)
Result C /
accum_sload_upper_data
accum_sload1 (2)
addnsub3 (2)
Adder/
Subtractor/
Accumulator 2
Q1.15
Rounding
(3)
overflow1
Result D
adder3_round (2)
Accumulator Feedback
Notes to Figure 10–7:
(1)
(2)
(3)
The adder/output block is in 18 × 18 mode. In 9 × 9 mode, there are four adder/subtractor blocks and two
summation blocks.
You can send these signals through a pipeline register. The pipeline length can be set to 1 or 2.
Q1.15 inputs are not available in 9 × 9 or 36 × 36 modes.
Adder/Subtractor/Accumulator Block
The adder/subtractor/accumulator block is the first level adder stage of
the adder/output block. This block can be configured as an accumulator
or as an adder/subtractor.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Accumulator
Accumulator
When the adder/subtractor/accumulator is configured as an
accumulator, the output of the adder/output block feeds back to the
accumulator as shown in Figure 10–7. The accumulator can be set up to
perform addition only, subtraction only or the addnsub signal can be
used to dynamically control the accumulation direction. A logic 1 value
on the addnsub signal indicates that the accumulator is performing
addition while a logic 0 value indicates subtraction.
Each accumulator can be cleared by either clearing the DSP block output
register or by using the accum_sload signal. The accumulator clear
using the accum_sload signal is independent from the resetting of the
output registers so the accumulation can be cleared and a new one can
begin without losing any clock cycles. The accum_sload signal controls
a feedback multiplexer that specifies that the output of the multiplier
should be summed with a zero instead of the accumulator feedback path.
The accumulator can also be initialized/preloaded with a non-zero value
using the accum_sload signal and the accum_sload_upper_data
bus with one clock cycle latency. Preloading the accumulator is done by
adding the result of the multiplier with the value specified on the
accum_sload_upper_data bus. As in the case of the accumulator
clearing, the accum_sload signal specifies to the feedback multiplexer
that the accum_sload_upper_data signal should feed the
accumulator instead of the accumulator feedback signal. The
accum_sload_upper_data signal only loads the upper 36-bits of the
accumulator. To load the entire accumulator, the value for the lower
16-bits must be sent through the multiplier feeding that accumulator with
the multiplier set to perform a multiplication by one.
The overflow signal will go high on the positive edge of the clock when
the accumulator detects an overflow or underflow. The overflow signal
will stay high for only one clock cycle after an overflow or underflow is
detected even if the overflow or underflow condition is still present. A
latch external to the DSP block has to be used to preserve the overflow
signal indefinitely or until the latch is cleared.
The DSP blocks support Q1.15 input format saturation and rounding in
each accumulator. The following signals are available that can control if
saturation or rounding or both is performed to the output of the
accumulator:
■
■
■
Altera Corporation
May 2008
accum_round
accum_saturation
accum_is_saturated output
10–16
Arria GX Device Handbook, Volume 2
Accumulator
Each DSP block has two sets of accum_round and accum_saturation
signals which control if rounding or saturation is performed on the
accumulator output respectively (one set of signals for each
accumulator). Rounding and saturation of the accumulator output is only
available when implementing a 16 × 16 multiplier-accumulator to
conform to the bit widths required for Q1.15 input format computation.
A logic 1 value on the accum_round and accum_saturation signal
indicates that rounding or saturation is performed while a logic 0
indicates that no rounding or saturation is performed. A logic 1 value on
the accum_is_saturated output signal tells you that saturation has
occurred to the result of the accumulator.
Figure 10–10 shows the DSP block configured to perform multiplieraccumulator operations.
Adder/Subtractor
The addnsub1 or addnsub3 signals specify whether you are performing
addition or subtraction. A logic 1 value on the addnsub1 or addnsub3
signals indicates that the adder/subtractor is performing addition while
a logic 0 value indicates subtraction. These signals can be dynamically
controlled using logic external to the DSP block. If the first stage is
configured as a subtractor, the output is A – B and C – D.
The adder/subtractor block share the same signa and signb signals as
the multiplier block. The signa and signb signals can be pipelined with
a latency of one or two clock cycles or not.
The DSP blocks support Q1.15 input format rounding (not saturation)
after each adder/subtractor. The addnsub1_round and
addnsub3_round signals determine if rounding is performed to the
output of the adder/subtractor.
The addnsub1_round signal controls the rounding of the top
adder/subtractor and the addnsub3_round signal controls the
rounding of the bottom adder/subtractor. Rounding of the adder output
is only available when implementing a 16 × 16 multiplier-adder to
conform to the bit widths required for Q1.15 input format computation.
A logic 1 value on the addnsub_round signal indicates that rounding is
performed while a logic 0 indicates that no rounding is performed.
Summation Block
The output of the adder/subtractor block feeds an optional summation
block, which is an adder block that sums the outputs of both
adder/subtractor blocks. The summation block is used when more than
two multiplier results are summed. This is useful in applications such as
FIR filtering.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Operational Modes
Output Select Multiplexer
The outputs of the different elements of the adder/output block are
routed through an output select multiplexer. Depending on the
operational mode of the DSP block, the output multiplexer selects
whether the outputs of the DSP blocks comes from the outputs of the
multiplier block, the outputs of the adder/subtractor/accumulator, or the
output of the summation block. The output select multiplier
configuration is set automatically by software, based on the DSP block
operational mode you specify.
Output Registers
You can use the output registers to register the DSP block output. The
following signals can control each output register within the DSP block:
■
■
■
clock[3..0]
ena[3..0]
aclr[3..0]
The output registers can be used in any DSP block operational mode.
1
f
Operational
Modes
Altera Corporation
May 2008
The output registers form part of the accumulator in the
multiply-accumulate mode.
Refer to the Arria GX Architecture chapter in volume 1 of the Arria GX
Device Handbook for more information on the DSP block routing and
interface.
The DSP block can be used in one of four basic operational modes, or a
combination of two modes, depending on the application needs.
Table 10–5 shows the four basic operational modes and the number of
multipliers that can be implemented within a single DSP block
depending on the mode.
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Arria GX Device Handbook, Volume 2
Operational Modes
Table 10–5. DSP Block Operational Modes
Mode
Number of
Multipliers
9×9
Simple multiplier
Eight multipliers
with eight product
outputs
18 × 18
Four multipliers
with four product
outputs
36 × 36
One multiplier
Two 52-bit
multiplyaccumulate blocks
-
Two-multiplier
adder
Four two-multiplier Two two-multiplier
adder (one 18 18
adder (two 9 9
complex multiply) complex multiply)
-
Four-multiplier
adder
Two four-multiplier
adder
-
Multiply
accumulate
-
One four-multiplier
adder
The Quartus II software includes megafunctions used to control the mode
of operation of the multipliers. After you make the appropriate parameter
settings using the megafunction's MegaWizard® Plug-In Manager, the
Quartus II software automatically configures the DSP block.
Arria GX DSP blocks can operate in different modes simultaneously. For
example, a single DSP block can be broken down to operate a 9 × 9
multiplier as well as an 18 × 18 multiplier-adder where both multiplier's
input a and input b have the same sign representations. This increases
DSP block resource efficiency and allows you to implement more
multipliers within an Arria GX device. The Quartus II software
automatically places multipliers that can share the same DSP block
resources within the same block.
Additionally, you can set up each Arria GX DSP block to dynamically
switch between the following three modes:
■
■
■
Altera Corporation
May 2008
Up to four 18-bit independent multipliers
Up to two 18-bit multiplier-accumulators
One 36-bit multiplier
10–19
Arria GX Device Handbook, Volume 2
Operational Modes
Each half of an Arria GX DSP block has separate mode control signals,
which allows you to implement multiple 18-bit multipliers or
multiplier-accumulators within the same DSP block and dynamically
switch them independently (if they are in separate DSP block halves). If
the design requires a 36-bit multiplier, you must switch the entire DSP
block to accommodate it since the multiplier requires the entire DSP
block. The smallest input bit width that supports dynamic mode
switching is 18 bits.
Simple Multiplier Mode
In simple multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers and for
applications such as computing equalizer coefficient updates which
require many individual multiplication operations.
9- and 18-Bit Multipliers
Each DSP block multiplier can be configured for 9- or 18-bit
multiplication. A single DSP block can support up to eight individual
9 × 9 multipliers or up to four individual 18 × 18 multipliers. For operand
widths up to 9-bits, a 9 × 9 multiplier will be implemented and for
operand widths from 10- to 18-bits, an 18 × 18 multiplier will be
implemented. Figure 10–8 shows the DSP block in the simple multiplier
operation mode.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Operational Modes
Figure 10–8. Simple Multiplier Mode
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
shiftinb
clock[3..0]
shiftina
ena[3..0]
sourcea
Output Register
D
Data A
Data Out
Q
ENA
CLRN
D
Q
ENA
Q1.15
Round/
Saturate
sourceb
(3)
D
Data B
CLRN
Q
mult_is_saturated (2)
D
Q
ENA
ENA
D
Q
ENA
CLRN
CLRN
CLRN
Multiplier Block
DSP Block
shiftoutb
shiftouta
Notes to Figure 10–8:
(1)
(2)
(3)
These signals are not registered or registered once to match the data path pipeline.
This signal has the same latency as the data path.
The rounding and saturation is only supported in 18 × 18-bit signed multiplication for Q1.15 inputs.
The multiplier operands can accept signed integers, unsigned integers or
a combination of both. The signa and signb signals can be changed
dynamically and can be registered in the DSP block. Additionally, the
multiplier inputs and result can be registered independently. The pipeline
registers within the DSP block can be used to pipeline the multiplier
result, increasing the performance of the DSP block.
36-Bit Multiplier
The 36-bit multiplier is also a simple multiplier mode but uses the entire
DSP block, including the adder/output block to implement the
36 × 36-bit multiplication operation. The device inputs 18-bit sections of
the 36-bit input into the four 18-bit multipliers. The adder/output block
adds the partial products obtained from the multipliers using the
summation block. Pipeline registers can be used between the multiplier
stage and the summation block to speed up the multiplication. The
36 × 36-bit multiplier supports signed, unsigned as well as mixed sign
multiplication. Figure 10–9 shows the DSP block configured to
implement a 36-bit multiplier.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Operational Modes
Figure 10–9. 36-Bit Multiplier
signa (1)
signb (1)
aclr
clock
ena
18
A[17..0]
D
Q
ENA
CLRN
Q
CLRN
18
B[17..0]
D
ENA
D
Q
ENA
CLRN
18
A[35..18]
D
Q
D
ENA
ENA
CLRN
B[35..18]
D
ENA
Q
36 × 36
Multiplier
Adder
CLRN
18
D
Q
Data Out
CLRN
Q
signa (2)
ENA
signb (2)
CLRN
18
A[35..18]
D
Q
ENA
CLRN
Q
CLRN
18
B[17..0]
D
ENA
D
Q
ENA
CLRN
18
A[17..0]
D
Q
ENA
CLRN
Q
CLRN
18
B[35..18]
D
ENA
D
Q
ENA
CLRN
Notes to Figure 10–9:
(1)
(2)
These signals are either not registered or registered once to match the pipeline.
These signals are either not registered, registered once, or registered twice to match the data path pipeline.
Altera Corporation
May 2008
10–22
Arria GX Device Handbook, Volume 2
Operational Modes
The 36-bit multiplier is useful for applications requiring more than 18-bit
precision, for example, for mantissa multiplication of precision
floating-point arithmetic applications.
Multiply Accumulate Mode
In multiply accumulate mode, the output of the multiplier stage feeds the
adder/output block which is configured as an accumulator or subtractor.
Figure 10–10 shows the DSP block configured to operate in multiply
accumulate mode.
Figure 10–10. Multiply Accumulate Mode
aclr[3..0]
clock[3..0]
ena[3..0]
Data A
accum_sload_upper_data (3)
accum_sload (3)
shiftina
shiftinb
D
Q
D
ENA
CLRN
D
Q1.15
Round/
Saturate
Q
ENA
Q1.15
Round/
Saturate
Q
Data Out
ENA
Accumulator
CLRN
CLRN
accum_is_saturated (4)
Data B
D
D
Q
ENA
Q
ENA
CLRN
D
Q
overflow
ENA
D
Q
ENA
shiftoutb
shiftouta
signb (1), (2)
signa (1), (2)
mult_round (2)
mult_saturate (2)
D
Q
ENA
mult_is_saturated (4)
addnsub (3)
signb (1), (3)
signa (1), (3)
accum_round (3)
accum_saturate (3)
Notes to Figure 10–10:
(1)
(2)
(3)
(4)
The signa and signb signals are the same in the multiplier stage and the adder/output block.
These signals are not registered or registered once to match the data path pipeline.
You can send these signals through either one or two pipeline registers.
These signals match the latency of the data path.
A single DSP block can implement up to two independent 18-bit
multiplier accumulators. The Quartus II software implements smaller
multiplier accumulators by tying the unused lower-order bits of the 18-bit
multiplier to ground.
Altera Corporation
May 2008
10–23
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
The multiplier accumulator output can be up to 52-bits wide to account
for a 36-bit multiplier result with 16-bits of accumulation. In this mode,
the DSP block uses output registers and the accum_sload and overflow
signals. The accum_sload signal can be used to clear the accumulator so
that a new accumulation operation can begin without losing any clock
cycles. This signal can be unregistered or registered once or twice. The
accum_sload signal can also be used to preload the accumulator with a
value specified on the accum_sload_upper_data signal with a one
clock cycle penalty. The accum_sload_upper_data signal only loads
the upper 36-bits (bits [51..16] of the accumulator). To load the entire
accumulator, the value for the lower 16-bits (bits [15..0]) must be sent
through the multiplier feeding that accumulator with the multiplier set to
perform a multiplication by one. Bits [17..16] are overlapped by both the
accum_sload_upper_data signal and the multiplier output. Either
one of these signals can be used to load bits [17..16].
The overflow signal indicates an overflow or underflow in the
accumulator. This signal gets updated every clock cycle due to a new
accumulation operation every cycle. To preserve the signal, an external
latch can be used. The addnsub signal can be used to specify if an
accumulation or subtraction is performed dynamically.
1
The DSP block can implement just an accumulator (without
multiplication) by specifying a multiply by one at the multiplier
stage followed by an accumulator to force the Quartus II
software to implement the function within the DSP block.
Multiply Add Mode
In multiply add mode, the output of the multiplier stage feeds the
adder/output block which is configured as an adder or subtractor to sum
or subtract the outputs of two or more multipliers. The DSP block can be
configured to implement either a two-multiply add (where the outputs of
two multipliers are added/subtracted together) or a four-multiply add
function (where the outputs of four multipliers are added or subtracted
together).
1
10–24
Arria GX Device Handbook, Volume 2
The adder block within the DSP block can only be used if it
follows multiplication operations.
Altera Corporation
May 2008
Operational Modes
Two-Multiplier Adder
In the two-multiplier adder configuration, the DSP block can implement
four 9-bit or smaller multiplier adders or two 18-bit multiplier adders.
The adders can be configured to take the sum of both multiplier outputs
or the difference of both multiplier outputs. You have the option to vary
the summation/subtraction operation dynamically. These multiply add
functions are useful for applications such as FFTs and complex FIR filters.
Figure 10–11 shows the DSP block configured in the two-multiplier adder
mode.
Figure 10–11. Two-Multiplier Adder Mode
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
clock[3..0]
ena[3..0]
shiftina
signb (2)
signa (2)
addnsub_round (2)
addnsub1 (2)
shiftinb
mult0_is_saturated (3)
D
Q
ENA
D
Q
ENA
D
Data A 1
Q
ENA
CLRN
D
Data B 1
D
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
Q
ENA
Adder/
Subtractor/
Accumulator
1
CLRN
D
Data A 2
Q
ENA
CLRN
D
Data B 2
D
Q
ENA
Data Out 1
CLRN
PRN
Q
ENA
CLRN
Q
ENA
shiftoutb
D
Q1.15
Round/
Saturate
Q1.15
Rounding
mult1_is_saturated (3)
D
Q
ENA
D
Q
ENA
shiftouta
Notes to Figure 10–11:
(1)
(2)
(3)
These signals are not registered or registered once to match the data path pipeline.
You can send these signals through a pipeline register. The pipeline length can be set to 1 or 2.
These signals match the latency of the data path.
Altera Corporation
May 2008
10–25
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
Complex
Multiply
The DSP block can be configured to implement complex multipliers using
the two-multiplier adder mode. A single DSP block can implement one
18 × 18-bit complex multiplier or two 9 × 9-bit complex multipliers.
A complex multiplication can be written as:
(a + jb) (c + jd) = ((ac) – (bd)) + j ((ad) + (bc))
To implement this complex multiplication within the DSP block, the real
part ((ac) – (bd)) is implemented using two multipliers feeding one
subtractor block while the imaginary part ((ad) + (bc)) is implemented
using another two multipliers feeding an adder block, for data up to
18-bits. Figure 10–12 shows an 18-bit complex multiplication. For data
widths up to 9-bits, a DSP block can perform two separate complex
multiplication operations using eight 9-bit multipliers feeding four
adder/subtractor/accumulator blocks. Resources external to the DSP
block must be used to route the correct real and imaginary input
components to the appropriate multiplier inputs to perform the correct
computation for the complex multiplication operation.
Figure 10–12. Complex Multiplier Using Two-Multiplier Adder Mode
DSP Block
18
18
A
36
18
18
C
18
37
Subtractor
18
B
(A × C) − (B × D)
(Real Part)
36
18
18
D
18
A
36
18
D
37
Adder
18
B
(A × D) + (B × C)
(Imaginary Part)
36
18
C
10–26
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Complex Multiply
Four-Multiplier Adder
In the four-multiplier adder configuration, the DSP block can implement
one 18 × 18 or two individual 9 × 9 multiplier adders. These modes are
useful for implementing one-dimensional and two-dimensional filtering
applications. The four-multiplier adder is performed in two addition
stages. The outputs of two of the four multipliers are initially summed in
the two first-stage adder/subtractor/accumulator blocks. The results of
these two adder/subtractor/accumulator blocks are then summed in the
final stage summation block to produce the final four-multiplier adder
result. Figure 10–13 shows the DSP block configured in the fourmultiplier adder mode.
Altera Corporation
May 2008
10–27
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
Figure 10–13. Four-Multiplier Adder Mode
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
clock[3..0]
ena[3..0]
shiftina
shiftinb
D
PRN
Q
D
ENA
CLRN
D
Data A 1
Q
ENA
CLRN
Q1.15
Round/
Saturate
(4)
D
Data B 1
D
PRN
Q
mult0_is_saturated (3)
ENA
CLRN
PRN
Q
ENA
CLRN
Q
ENA
Adder/
Subtractor/
Accumulator
1
CLRN
D
Data A 2
Q
ENA
CLRN
Q1.15
Round/
Saturate
(4)
D
Data B 2
D
Q1.15
Rounding
(4)
PRN
Q
D
ENA
CLRN
PRN
D
Q
ENA
CLRN
D
addnsub1 (2)
addnsub1/3_round (2)
signa (2)
signb (2)
addnsub3 (2)
Adder
Q
ENA
CLRN
Q1.15
Round/
Saturate
(4)
D
Data B 1
D
CLRN
Q1.15
Round/
Saturate
D
Q1.15
Rounding
(4)
PRN
Q
ENA
CLRN
Q
ENA
D
PRN
Q
ENA
CLRN
shiftoutb
mult0_is_saturated (3)
ENA
CLRN
Adder/
Subtractor/
Accumulator
1
(4)
D
PRN
Q
ENA
CLRN
Q
ENA
Data B 2
D
Q
CLRN
D
Data Out 1
CLRN
PRN
Q
ENA
Data A 2
D
Q
ENA
PRN
Q
ENA
CLRN
D
mult1_is_saturated (3)
ENA
CLRN
Q
ENA
Data A 1
PRN
Q
D
PRN
Q
mult1_is_saturated (3)
ENA
CLRN
shiftouta
Notes to Figure 10–13:
(1)
(2)
(3)
(4)
These signals are not registered or registered once to match the data path pipeline.
You should send these signals through the pipeline register to match the latency of the data path.
These signals match the latency of the data path.
The rounding and saturation is only supported in 18 × 18-bit signed multiplication for Q1.15 inputs.
10–28
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
FIR Filter
FIR Filter
Altera Corporation
May 2008
The four-multiplier adder mode can be used to implement FIR filter and
complex FIR filter applications. To do this, the DSP block is set up in a
four-multiplier adder mode with one set of input registers configured as
shift registers using the dedicated shift register chain. The set of input
registers configured as shift registers will contain the input data while the
inputs configured as regular inputs will hold the filter coefficients.
Figure 10–14 shows the DSP block configured in the four-multiplier
adder mode using input shift registers.
10–29
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
Figure 10–14. FIR Filter Implemented Using the Four-Multiplier Adder Mode with Input Shift Registers
Data A
D
18
Q
ENA
CLRN
Coefficient 0
D
18
Q
D
ENA
Q
A[n] × Coefficient 0
(to Adder)
CLRN
ENA
CLRN
D
Q
ENA
CLRN
Coefficient 1
D
18
Q
D
ENA
Q
A[n − 1] × Coefficient 1
(to Adder)
CLRN
ENA
CLRN
D
Q
ENA
CLRN
Coefficient 2
D
18
Q
D
ENA
Q
A[n − 2] × Coefficient 2
(to Adder)
CLRN
ENA
CLRN
10–30
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Software Support
The built-in input shift register chain within the DSP block eliminates the
need for shift registers externally to the DSP block in logic elements (LEs).
This architecture feature simplifies the filter design and improves the
filter performance because all the filter circuitry is localized within the
DSP block.
1
Input shift registers for the 36-bit simple multiplier mode have
to be implemented using external registers to the DSP block.
A single DSP block can implement a four tap 18-bit FIR filter. For filters
larger than four taps, the DSP blocks can be cascaded with additional
adder stages implemented using LEs.
Software
Support
Altera provides two distinct methods for implementing various modes of
the DSP block in your design: instantiation and inference. Both methods
use the following three Quartus II megafunctions:
■
■
■
lpm_mult
altmult_add
altmult_accum
You can instantiate the megafunctions in the Quartus II software to use
the DSP block. Alternatively, with inference, you can create a HDL design
and synthesize it using a third-party synthesis tool like
LeonardoSpectrumTM or Synplify or Quartus II Native Synthesis that
infers the appropriate megafunction by recognizing multipliers,
multiplier adders, and multiplier accumulators. Using either method, the
Quartus II software maps the functionality to the DSP blocks during
compilation.
f
See Quartus II On-Line Help for instructions on using the megafunctions
and the MegaWizard Plug-In Manager.
f
For more information, see the Design and Synthesis section in volume 1 of
the Quartus II Development Software Handbook.
Conclusion
Altera Corporation
May 2008
The Arria GX device DSP blocks are optimized to support DSP
applications requiring high data throughput such as FIR filters, FFT
functions and encoders. These DSP blocks are flexible and can be
configured to implement one of several operational modes to suit a
particular application. The built-in shift register chain,
adder/subtractor/accumulator block and the summation block
minimizes the amount of external logic required to implement these
functions, resulting in efficient resource utilization and improved
performance and data throughput for DSP applications. The Quartus II
10–31
Arria GX Device Handbook, Volume 2
DSP Blocks in Arria GX Devices
software, together with the LeonardoSpectrumTM and Synplify software
provide a complete and easy-to-use flow for implementing these
multiplier functions in the DSP blocks.
Referenced
Documents
This chapter references the following documents:
■
■
■
■
Document
Revision History
AN 306: Implementing Multipliers in FPGA Devices
Arria GX Architecture chapter in volume 1 of the Arria GX Device
Handbook
Arria GX Device Family Data Sheet in volume 1 of the Arria GX Device
Handbook
Design and Synthesis section in volume 1 of the Quartus II Development
Software Handbook
Table 10–6 shows the revision history for this chapter.
Table 10–6. Document Revision History
Date and
Document
Version
May 2008,
v1.2
Changes Made
Minor text edits.
Summary of Changes
—
August 2007, Added the “Referenced Documents” section.
v1.1
Minor text edits.
—
May 2007,
v1.0
—
Initial Release
10–32
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
Section VI. Configuration&
Remote System Upgrades
This section provides configuration information for all of the supported
configuration schemes for Arria™ GX devices. These configuration
schemes use either a microprocessor, configuration device, or download
cable. There is detailed information on how to design with Altera
enhanced configuration devices which includes information on how to
manage multiple configuration files and access the on-chip FLASH
memory space. The last chapter shows designers how to perform remote
and local upgrades for their designs.
This section contains the following chapters:
Revision History
Altera Corporation
■
Chapter 11, Configuring Arria GX Devices
■
Chapter 12, Remote System Upgrades with Arria GX Devices
■
Chapter 13, IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX
Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section VI–1
Preliminary
Configuration& Remote System Upgrades
Section VI–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
11. Configuring Arria GX
Devices
AGX52011-1.3
Introduction
Arria™ GX II devices use SRAM cells to store configuration data. Because
SRAM memory is volatile, configuration data must be downloaded to
Arria GX devices each time the device powers up. Arria GX devices can
be configured using one of five configuration schemes: the fast passive
parallel (FPP), active serial (AS), passive serial (PS), passive parallel
asynchronous (PPA), and Joint Test Action Group (JTAG) configuration
schemes. All configuration schemes use either an external controller (for
example, a MAX® II device or microprocessor) or a configuration device.
This chapter contains the following sections:
■
■
■
■
■
■
■
■
“Configuration Features” on page 11–4
“Fast Passive Parallel Configuration” on page 11–13
“Active Serial Configuration (Serial Configuration Devices)” on
page 11–32
“Passive Serial Configuration” on page 11–44
“Passive Parallel Asynchronous Configuration” on page 11–71
“JTAG Configuration” on page 11–82
“Device Configuration Pins” on page 11–90
“Conclusion” on page 11–104
Configuration Devices
The Altera® enhanced configuration devices (EPC16, EPC8, and EPC4)
support a single-device configuration solution for high-density devices
and can be used in the FPP and PS configuration schemes. They are
ISP-capable through their JTAG interface. The enhanced configuration
devices are divided into two major blocks, the controller and the flash
memory.
f
For information on enhanced configuration devices, refer to the Enhanced
Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet and the Altera
Enhanced Configuration Devices chapters in volume 2 of the Configuration
Handbook.
The Altera serial configuration devices (EPCS64, EPCS16, and EPCS4)
support a single-device configuration solution for Arria GX devices and
are used in the AS configuration scheme. Serial configuration devices
offer a low cost, low pin count configuration solution.
Altera Corporation
May 2008
11–1
Introduction
f
For information on serial configuration devices, refer to the Serial
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128)
Data Sheet chapter in volume 2 of the Configuration Handbook.
The EPC2 configuration devices provide configuration support for the PS
configuration scheme. The EPC2 device is ISP-capable through its JTAG
interface. The EPC2 device can be cascaded to hold large configuration
files.
f
For more information on EPC2 configuration devices, refer to the
Configuration Devices for SRAM-Based LUT Devices Data Sheet chapter in
volume 2 of the Configuration Handbook.
Configuration Schemes
The configuration scheme is selected by driving the Arria GX device
MSEL pins either high or low, as shown in Table 11–1. The MSEL pins are
powered by the VCCINT power supply of the bank they reside in. The
MSEL[3..0] pins have 5-kΩ internal pull-down resistors that are always
active. During power-on reset (POR) and during reconfiguration, the
MSEL pins have to be at LVTTL VIL and VIH levels to be considered a logic
low and logic high.
1
To avoid any problems with detecting an incorrect configuration
scheme, hard-wire the MSEL[] pins to VCCPD and GND, without
any pull-up or pull-down resistors. Do not drive the MSEL[]
pins by a microprocessor or another device.
Table 11–1. Arria GX Configuration Schemes (Part 1 of 2)
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
Fast passive parallel (FPP)
0
0
0
0
Passive parallel asynchronous (PPA)
0
0
0
1
Passive serial (PS)
0
0
1
0
Remote system upgrade FPP (1)
0
1
0
0
Remote system upgrade PPA (1)
0
1
0
1
Remote system upgrade PS (1)
0
1
1
0
Fast AS (40 MHz) (2)
1
0
0
0
Remote system upgrade fast AS (40 MHz) (2)
1
0
0
1
FPP with decompression feature enabled (3)
1
0
1
1
Remote system upgrade FPP with decompression
feature enabled (1), (3)
1
1
0
0
AS (20 MHz) (2)
1
1
0
1
11–2
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
Table 11–1. Arria GX Configuration Schemes (Part 2 of 2)
Configuration Scheme
Remote system upgrade AS (20 MHz) (2)
JTAG-based configuration (5)
MSEL3
MSEL2
MSEL1
MSEL0
1
1
1
0
(4)
(4)
(4)
(4)
Notes to Table 11–1:
(1)
(2)
(3)
(4)
(5)
These schemes require that you drive the RUnLU pin to specify either remote update or local update. For more
information about remote system upgrades in Arria GX devices, refer to the Remote System Upgrades With Arria GX
Devices chapter in volume 2 of the Arria GX Device Handbook.
Only the EPCS16 and EPCS64 devices support up to a 40 MHz DCLK. Other EPCS devices support up to a 20 MHz
DCLK. Refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet in
volume 2 of the Configuration Handbook for more information.
These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is 4× the data rate.
Do not leave the MSEL pins floating. Connect them to VCCPD or ground. These pins support the non-JTAG
configuration scheme used in production. If only JTAG configuration is used, you should connect the MSEL pins to
ground.
JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings are
ignored.
Arria GX devices offer decompression and remote system upgrade
features. Arria GX devices can receive a compressed configuration
bitstream and decompress this data in real-time, reducing storage
requirements and configuration time. You can make real-time system
upgrades from remote locations of your Arria GX designs with the
remote system upgrade feature.
Table 11–2 shows the uncompressed configuration file sizes for Arria GX
devices.
Table 11–2. Arria GX Uncompressed .rbf Sizes
Device
Note (1)
Data Size (Bits)
Data Size (MBytes)
EP1AGX20
9,640,672
1.205
EP1AGX35
9,640,672
1.205
EP1AGX50
16,951,824
2.119
EP1AGX60
16,951,824
2.119
EP1AGX90
25,699,104
3.212
Note to Table 11–2:
(1)
Altera Corporation
May 2008
.rbf: Raw Binary File.
11–3
Arria GX Device Handbook, Volume 2
Configuration Features
Use the data in Table 11–2 to estimate the file size before design
compilation. Different configuration file formats, such as a Hexidecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
However, for any specific version of the Quartus® II software, any design
targeted for the same device will have the same uncompressed
configuration file size. If you are using compression, the file size can vary
after each compilation because the compression ratio is dependent on the
design.
This chapter explains the Arria GX device configuration features and
describes how to configure Arria GX devices using the supported
configuration schemes. This chapter provides configuration pin
descriptions and the Arria GX device configuration file formats. In this
chapter, the generic term device(s) includes all Arria GX devices.
f
Configuration
Features
For more information on setting device configuration options or creating
configuration files, refer to the Software Settings section in volume 2 of
the Configuration Handbook.
Arria GX devices offer configuration data decompression to reduce
configuration file storage and remote system upgrades to allow you to
remotely update your Arria GX designs. Table 11–3 summarizes which
configuration features can be used in each configuration scheme.
Table 11–3. Arria GX Configuration Features
Configuration
Scheme
FPP
Decompression
Remote System
Upgrade
MAX II device or a Microprocessor with flash memory
v (1)
v
Enhanced Configuration Device
v (2)
v
Configuration Method
AS
Serial Configuration Device
v
v (3)
PS
MAX II device or a Microprocessor with flash memory
v
v
Enhanced Configuration Device
v
v
Download cable
v
PPA
MAX II device or a Microprocessor with flash memory
JTAG
MAX II device or a Microprocessor with flash memory
v
Notes to Table 11–3:
(1)
(2)
(3)
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Arria GX decompression feature
is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
11–4
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
Configuration Data Decompression
Arria GX devices support configuration data decompression, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
memory and transmit this compressed bitstream to Arria GX devices.
During configuration, Arria GX devices decompress the bitstream in real
time and programs its SRAM cells.
1
Preliminary data indicates that compression typically reduces
configuration bitstream size by 35 to 55%.
Arria GX devices support decompression in the FPP (when using a
MAX II device/microprocessor + flash), AS, and PS configuration
schemes. Decompression is not supported in the PPA configuration
scheme nor in JTAG-based configuration.
1
When using FPP mode, the intelligent host must provide a DCLK
that is 4× the data rate. Therefore, the configuration data must be
valid for four DCLK cycles.
The decompression feature supported by Arria GX devices is different
from the decompression feature in enhanced configuration devices
(EPC16, EPC8, and EPC4 devices), although they both use the same
compression algorithm. The data decompression feature in the enhanced
configuration devices allows them to store compressed data and
decompress the bitstream before transmitting it to the target devices.
When using Arria GX devices in FPP mode with enhanced configuration
devices, the decompression feature is available only in the enhanced
configuration device, not the Arria GX device.
In PS mode, use the Arria GX decompression feature because sending
compressed configuration data reduces configuration time. Do not use
both the Arria GX device and the enhanced configuration device
decompression features simultaneously. The compression algorithm is
not intended to be recursive and could expand the configuration file
instead of compressing it further.
When you enable compression, the Quartus II software generates
configuration files with compressed configuration data. This compressed
file reduces the storage requirements in the configuration device or flash
memory, and decreases the time needed to transmit the bitstream to the
Arria GX device. The time required by an Arria GX device to decompress
a configuration file is less than the time needed to transmit the
configuration data to the device.
Altera Corporation
May 2008
11–5
Arria GX Device Handbook, Volume 2
Configuration Features
There are two ways to enable compression for Arria GX bitstreams: before
design compilation (in the Compiler Settings menu) and after design
compilation (in the Convert Programming Files window).
To enable compression in the project’s compiler settings, select Device
under the Assignments menu to bring up the Settings window. After
selecting your Arria GX device, open the Device & Pin Options window,
and in the General settings tab, enable the check box for Generate
compressed bitstreams (as shown in Figure 11–1).
Figure 11–1. Enabling Compression for Arria GX Bitstreams in Compiler
Settings
11–6
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
Compression can also be enabled when creating programming files from
the Convert Programming Files window by following these steps:
1.
Click Conv ert Programming Files (File menu).
2.
Select the programming file type (POF, SRAM HEXOUT, RBF, or
TTF).
3.
For POF output files, select a configuration device.
4.
In the Input files to convert box, select SOF Data.
5.
Select Add File and add an Arria GX device SOF(s).
6.
Select the name of the file you added to the SOF Data area and click
Properties.
7.
Check the Compression check box.
When multiple Arria GX devices are cascaded, you can selectively enable
the compression feature for each device in the chain if you are using a
serial configuration scheme. Figure 11–2 depicts a chain of two Arria GX
devices. The first Arria GX device has compression enabled and receives
a compressed bitstream from the configuration device. The second Arria
GX device has the compression feature disabled and receives
uncompressed data.
In a multi-device FPP configuration chain, all Arria GX devices in the
chain must either enable of disable the decompression feature. You can
not selectively enable the compression feature for each device in the chain
because of the DATA and DCLK relationship.
Altera Corporation
May 2008
11–7
Arria GX Device Handbook, Volume 2
Configuration Features
Figure 11–2. Compressed & Uncompressed Configuration Data in the Same
Configuration File
Serial Configuration Data
Serial or Enhanced
Configuration
Device
Uncompressed
Configuration
Data
Compressed
Configuration
Data
Decompression
Controller
Arria GX
FPGA
nCE
Arria GX
FPGA
nCEO
nCE
nCEO
N.C.
GND
You can generate programming files for this setup from the Convert
Programming Files window (File menu) in the Quartus II software.
Remote System Upgrade
Arria GX devices feature remote and local update.
f
For more information about this feature, refer to the Remote System
Upgrades with Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook.
Power-On Reset Circuit
The POR circuit keeps the entire system in reset until the power supply
voltage levels have stabilized on power-up. Upon power-up, the device
does not release nSTATUS until VCCINT, VCCPD, and VCCIO of banks 3, 4, 7,
and 8 are above the device’s POR trip point. On power down, VCCINT is
monitored for brown-out conditions.
The passive serial mode (MSEL[3..0] = 0010) and the Fast passive
parallel mode (MSEL[3..0] = 0000) always enable bank 3 to use the
lower POR trip point consistent with 1.8- and 1.5-V signaling, regardless
of the VCCSEL setting. For all other configuration modes, VCCSEL selects
the POR trip point level. Refer to “VCCSEL Pin” on page 11–9 for more
details.
11–8
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
In Arria GX devices, the pin-selectable option PORSEL allows you to
select between a typical POR time setting of 12 ms or 100 ms. In both
cases, you can extend the POR time by using an external component to
assert the nSTATUS pin low.
VCCPD Pins
Arria GX devices also offer a new power supply, VCCPD, which must be
connected to 3.3-V in order to power the 3.3-V/2.5-V buffer available on
the configuration input pins and JTAG pins. VCCPD applies to all the JTAG
input pins (TCK, TMS, TDI, and TRST) and the configuration pins when
VCCSEL is connected to ground. Refer to Table 11–4 for information on
the pins affected by VCCSEL.
1
VCCPD must ramp-up from 0-V to 3.3-V within 100 ms. If VCCPD
is not ramped up within this specified time, your Arria GX
device will not configure successfully. If your system does not
allow for a VCCPD ramp-up time of 100 ms or less, you must hold
nCONFIG low until all power supplies are stable.
VCCSEL Pin
The VCCSEL pin selects the type of input buffer used on configuration
input pins and it selects the POR trip point voltage level for VCCIO bank 3
powered by VCCIO3 pins.
The configuration input pins and the PLL_ENA pin (Table 11–4) have a
dual buffer design. These pins have a 3.3-V/2.5-V input buffer and a
1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input
buffer is used during configuration. The 3.3-V/2.5-V input buffer is
powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Configuration Features
VCCIO. After configuration, the dual-purpose configuration pins are
powered by the VCCIO pins. Table 11–4 shows the pins affected by
VCCSEL.
Table 11–4. Pins Affected by the Voltage Level at VCCSEL
VCCSEL = LOW (connected to GND) VCCSEL = HIGH (connected to VCCPD)
Pin
3.3/2.5-V input buffer is selected.
Input buffer is powered by VC C P D .
nSTATUS (when used as an
input)
nCONFIG
1.8/1.5-V input buffer is selected.
Input buffer is powered by VC C I O of
the I/O bank. These input buffers are
3.3-V tolerant.
CONF_DONE (when used as an
input)
DATA[7..0]
nCE
DCLK (when used as an input)
CS
nWS
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on-the-fly or during a reconfiguration. The VCCSEL input
buffer is powered by VCCINT and has an internal 5-kΩ pull-down resistor
that is always active.
1
VCCSEL must be hardwired to VCCPD or GND.
A logic high selects the 1.8-V/1.5-V input buffer, and a logic low selects
the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the
logic levels driven out of the configuration device or MAX II device or a
microprocessor with flash memory.
VCCSEL also sets the POR trip point for I/O bank 3 to ensure that this I/O
bank has powered up to the appropriate voltage levels before
configuration begins. For passive serial (PS) mode (MSEL[3..0] =
0010) and for Fast passive parallel (FPP) mode (MSEL[3..0] = 0000)
11–10
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Altera Corporation
May 2008
Configuring Arria GX Devices
the POR circuitry selects the trip point associated with 1.5/1.8-V
signaling. For all other configuration modes defined by MSEL[3..0]
settings other than 00X0 (MSEL[1] = X, don't care), VCCSEL=GND
selects the higher I/O Bank 3 POR trip point for 2.5V/3.3V signaling and
VCCSEL=VCCPD selects the lower I/O Bank 3 POR trip point associated
with 1.5V/1.8V signaling.
For all configuration modes with MSEL[3..0] not equal to 00X0
(MSEL[1] = X, don't care), if VCCIO of configuration bank 3 is
powered by 1.8-V or 1.5-V and VCCSEL = GND, the voltage supplied to
this I/O bank(s) may never reach the POR trip point, which prevents the
device from beginning configuration.
1
The fast passive parallel (FPP) and passive serial (PS) modes
always enable bank 3 to use the POR trip point to be consistent
with 1.8- and 1.5-V signaling, regardless of the VCCSEL setting.
If the VCCIO of I/O bank 3 is powered by 1.5 or 1.8-V and the configuration
signals used require 3.3- or 2.5-V signaling, you should set VCCSEL to
VCCPD to enable the 1.8/1.5-V input buffers for configuration. The 1.8-V/
1.5-V input buffers are 3.3-V tolerant.
Table 11–5 shows how you should set the VCCSEL, depending on the
configuration mode, the voltage level on VCCIO3 pins that power bank
3, and the supported configuration input voltages.
Table 11–5. Supported VCCSEL Setting based on Mode, VCCIO3, and Input
Configuration Voltage
Configuration
Mode
VCCIO (Bank 3)
Configuration Input
Signaling Voltage
VCCSEL
All modes
3.3-V/2.5-V
3.3-V/2.5-V
GND
All modes
1.8-V/1.5-V
3.3-V/2.5-V
VCCPD (1)
All modes
1.8-V/1.5-V
1.8-V/1.5-V
VCCPD
-
3.3-V/2.5-V
1.8-V/1.5-V
Not Supported
Note to Table 11–5:
(1)
The VCCSEL pin can also be connected to GND for PS (MSEL[3..0]=0010) and
FPP (MSEL[3..0]=0000) modes.
The key is to ensure the VCCIO voltage of bank 3 is high enough to trip
VCCIO3 POR trip point on power-up. Also, to make sure the
configuration device meets the VIH for the configuration input pins based
on the selected input buffer.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Configuration Features
Table 11–6 shows the configuration mode support for banks 4, 7, and 8.
Table 11–6. Arria GX Configuration Mode Support for Banks 4, 7, & 8
Configuration Voltage/VC C I O Support for Banks 4, 7, & 8
Configuration Mode
3.3/3.3
1.8/1.8
3.3/1.8
VCCSEL = GND
VCCSEL = VCCPD
VCCSEL = GND
Fast passive parallel
Y
Y
Y
Passive parallel asynchronous
Y
Y
Y
Passive serial
Y
Y
Y
Remote system upgrade FPP
Y
Y
Y
Remote system upgrade PPA
Y
Y
Y
Remote system upgrade PS
Y
Y
Y
Fast AS (40 MHz)
Y
Y
Y
Remote system upgrade fast AS (40 MHz)
Y
Y
Y
FPP with decompression
Y
Y
Y
Remote system upgrade FPP with
decompression feature enabled
Y
Y
Y
AS (20 MHz)
Y
Y
Y
Remote system upgrade AS (20 MHz)
Y
Y
Y
You must verify the configuration output pins for your chosen
configuration modes meet the VIH of the configuration device. Refer to
Table 11–22 for a consolidated list of configuration output pins.
The VIH of 3.3 or 2.5 V configuration devices will not be met when the
VCCIO of the output configuration pins is 1.8 V or 1.5 V. Level shifters will
be required to meet the input high level voltage threshold VIH.
Note that AS mode is only applicable for 3.3-V configuration. If I/O bank
3 is less than 3.3V then level shifters are required on the output pins
(DCLK, nCSO, ASDO) from the Arria GX device back to the EPCS device.
The VCCSEL signal does not control TDO or nCEO. During configuration,
these pins drive out voltage levels corresponding to the VCCIO supply
voltage that powers the I/O bank containing the pin.
f
For more information on multi-volt support, including information on
using TDO and nCEO in multi-volt systems, refer to the Arria GX
Architecture chapter in volume 1 of the Arria GX Device Handbook.
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Altera Corporation
May 2008
Configuring Arria GX Devices
Fast Passive
Parallel
Configuration
Fast passive parallel (FPP) configuration in Arria GX devices is designed
to meet the continuously increasing demand for faster configuration
times. Arria GX devices are designed with the capability of receiving
byte-wide configuration data per clock cycle. Table 11–7 shows the MSEL
pin settings when using the FFP configuration scheme.
Table 11–7. Arria GX MSEL Pin Settings for FPP Configuration Schemes
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
FPP when not using remote system upgrade or decompression feature
0
0
0
0
FPP when using remote system upgrade (1)
0
1
0
0
FPP with decompression feature enabled (2)
1
0
1
1
FPP when using remote system upgrade and decompression feature (1),
(2)
1
1
0
0
Notes to Table 11–7:
(1)
(2)
These schemes require that you drive the RUnLU pin to specify either remote update or local update. For more
information about remote system upgrade in Arria GX devices, refer to the Remote System Upgrades with Arria GX
Devices chapter in volume 2 of the Arria GX Device Handbook.
These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is 4× the data rate.
FPP configuration of Arria GX devices can be performed using an
intelligent host, such as a MAX II device, a microprocessor, or an Altera
enhanced configuration device.
FPP Configuration Using a MAX II Device as an External Host
FPP configuration using compression and an external host provides the
fastest method to configure Arria GX devices. In the FPP configuration
scheme, a MAX II device can be used as an intelligent host that controls
the transfer of configuration data from a storage device, such as flash
memory, to the target Arria GX device. Configuration data can be stored
in RBF, HEX, or TTF format. When using the MAX II devices as an
intelligent host, a design that controls the configuration process, such as
fetching the data from flash memory and sending it to the device, must be
stored in the MAX II device.
1
If you are using the Arria GX decompression feature, the
external host must be able to send a DCLK frequency that is 4×
the data rate.
The 4× DCLK signal does not require an additional pin and is sent on the
DCLK pin. The maximum DCLK frequency is 100 MHz, which results in a
maximum data rate of 200 Mbps. If you are not using the Arria GX
decompression feature, the data rate is 8× the DCLK frequency.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
Figure 11–3 shows the configuration interface connections between the
Arria GX device and a MAX II device for single device configuration.
Figure 11–3. Single Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCC (1)
VCC (1)
Arria GX Device
10 kΩ
10 kΩ
MSEL[3..0]
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCEO
nCE
N.C.
GND
DATA[7..0]
nCONFIG
DCLK
Note to Figure 11–3:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for the device. VCC should be high enough to meet the VIH
specification of the I/O on the device and the external host.
Upon power-up, the Arria GX devices go through a power-on reset
(POR). The POR delay is dependent on the PORSEL pin setting: when
PORSEL is driven low, the POR time is approximately 100 ms; when
PORSEL is driven high, the POR time is approximately 12 ms. During
POR, the device resets, holds nSTATUS low, and tri-states all user I/O
pins. Once the device successfully exits POR, all user I/O pins continue
to be tri-stated. If nIO_pullup is driven low during power-up and
configuration, the user I/O pins and dual-purpose I/O pins have weak
pull-up resistors, which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors
are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Arria GX Device Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in the
reset stage. To initiate configuration, the MAX II device must drive the
nCONFIG pin from low to high.
1
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Arria GX Device Handbook, Volume 2
VCCINT, VCCIO, and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
Altera Corporation
May 2008
Configuring Arria GX Devices
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device places the configuration data, one byte at
a time, on the DATA[7..0] pins.
1
Arria GX devices receive configuration data on the
DATA[7..0] pins and the clock is received on the DCLK pin.
Data is latched into the device on the rising edge of DCLK. If you
are using the Arria GX decompression feature, configuration
data is latched on the rising edge of every fourth DCLK cycle.
After the configuration data is latched in, it is processed during
the following three DCLK cycles.
Data is continuously clocked into the target device until CONF_DONE goes
high. The CONF_DONE pin goes high one byte early in parallel
configuration (FPP and PPA) modes. The last byte is required for serial
configuration (AS and PS) modes. After the device has received the next
to last byte of the configuration data successfully, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ
pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin. The
CONF_DONE pin must have an external 10-kΩ pull-up resistor in order for
the device to initialize.
In Arria GX devices, the initialization clock source is either the internal
oscillator (typically 10 MHz) or the optional CLKUSR pin. By default, the
internal oscillator is the clock source for initialization. If the internal
oscillator is used, the Arria GX device provides itself with enough clock
cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to
the device after configuration is complete does not affect device
operation.
You can also synchronize initialization of multiple devices or to delay
initialization with the CLKUSR option. The Enable user-supplied start-up
clock (CLKUSR) option can be turned on in the Quartus II software from
the General tab of the Device & Pin Options dialog box. Supplying a
clock on CLKUSR does not affect the configuration process. The
CONF_DONE pin goes high one byte early in parallel configuration (FPP
and PPA) modes. The last byte is required for serial configuration (AS and
PS) modes. After the CONF_DONE pin transitions high, CLKUSR is enabled
after the time specified as tCD2CU. After this time period elapses, Arria GX
devices require 299 clock cycles to initialize properly and enter user
mode. Arria GX devices support a CLKUSR fMAX of 100 MHz.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it is high because of an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. The MAX II device must be
able to detect this low-to-high transition, which signals the device has
entered user mode. When initialization is complete, the device enters user
mode. In user-mode, the user I/O pins no longer have weak pull-up
resistors and function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[7..0] pins are
available as user I/O pins after configuration. When you select the FPP
scheme in the Quartus II software, as a default, these I/O pins are
tri-stated in user mode. To change this default option in the Quartus II
software, select the Pins tab of the Device & Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
1
If you are using the Arria GX decompression feature and need
to stop DCLK, it can only be stopped three clock cycles after the
last data byte was latched into the Arria GX device.
By stopping DCLK, the configuration circuit allows enough clock cycles to
process the last byte of latched configuration data. When the clock
restarts, the MAX II device must provide data on the DATA[7..0] pins
prior to sending the first DCLK rising edge.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options dialog box) is turned
on, the device releases nSTATUS after a reset time-out period (maximum
of 100 µs). After nSTATUS is released and pulled high by a pull-up
resistor, the MAX II device can try to reconfigure the target device
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Altera Corporation
May 2008
Configuring Arria GX Devices
without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse
of at least 2 µs) on nCONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but the
CONF_DONE or INIT_DONE signals have not gone high, the MAX II
device will reconfigure the target device.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 100 µs).
When the device is in user-mode, initiating a reconfiguration is done by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 2 µs. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
Figure 11–4 shows how to configure multiple devices using a MAX II
device. This circuit is similar to the FPP configuration circuit for a single
device, except the Arria GX devices are cascaded for multi-device
configuration.
Figure 11–4. Multi-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCC (1) VCC (1)
Arria GX Device 1
10 kΩ
Arria GX Device 2
10 kΩ
MSEL[3..0]
MSEL[3..0]
CONF_DONE
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nCEO
GND
nSTATUS
nCE
nCEO
N.C.
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Note to Figure 11–4:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O standard on the device and the external
host.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
In multi-device FPP configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. The configuration signals may require buffering to ensure
signal integrity and prevent clock skew problems. Ensure that the DCLK
and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
All nSTATUS and CONF_DONE pins are tied together and if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). After all nSTATUS pins are released and pulled
high, the MAX II device can try to reconfigure the chain without pulsing
nCONFIG low. If this option is turned off, the MAX II device must
generate a low-to-high transition (with a low pulse of at least 2 µs) on
nCONFIG to restart the configuration process.
In a multi-device FPP configuration chain, all Arria GX devices in the
chain must either enable or disable the decompression feature. You can
not selectively enable the decompression feature for each device in the
chain because of the DATA and DCLK relationship.
If a system has multiple devices that contain the same configuration data,
tie all device nCE inputs to GND, and leave nCEO pins floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals may require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time. Figure 11–5
shows multi-device FPP configuration when both Arria GX devices are
receiving the same configuration data.
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Altera Corporation
May 2008
Configuring Arria GX Devices
Figure 11–5. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the
Same Data
Memory
ADDR DATA[7..0]
VCC (1) VCC (1)
10 kΩ
Arria GX
Device
10 kΩ
Arria GX
Device
MSEL[3..0]
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
MSEL[3..0]
CONF_DONE
GND
nCEO
GND
GND
nSTATUS
nCE
N.C. (2)
nCEO
N.C. (2)
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Notes to Figure 11–5:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pins of both Arria GX devices are left unconnected when configuring the same configuration data into
multiple devices.
You can use a single configuration chain to configure Arria GX devices
with other Altera devices that support FPP configuration, such as Stratix®
devices. To ensure that all devices in the chain complete configuration at
the same time or that an error flagged by one device initiates
reconfiguration in all devices, tie all of the device CONF_DONE and
nSTATUS pins together.
f
For more information about configuring multiple Altera devices in the
same configuration chain, refer to the Configuring Mixed Altera FPGA
Chains chapter in volume 2 of the Configuration Handbook.
FPP Configuration Timing
Figure 11–6 shows the timing waveform for FPP configuration when
using a MAX II device as an external host. This waveform shows the
timing when the decompression feature is not enabled.
Altera Corporation
May 2008
11–19
Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
Figure 11–6. FPP Configuration Timing Waveform
Notes (1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (4)
tCF2CD
tST2CK
tCH tCL
(5)
DCLK
tDH
DATA[7..0]
(5)
Byte 0 Byte 1 Byte 2 Byte 3
Byte n
User Mode
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 11–6:
(1)
(2)
(3)
(4)
(5)
(6)
This timing waveform should be used when the decompression feature is not used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Arria GX device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the
dual-purpose pin settings.
Table 11–8 defines the timing parameters for Arria GX devices for FPP
configuration when the decompression feature is not enabled.
Table 11–8. FPP Timing Parameters for Arria GX Devices (Part 1 of 2)
Symbol
Parameter
Min
Notes (1), (2)
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG low to nSTATUS low
800
ns
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
10
100 (3)
µs
tCF2ST1
nCONFIG high to nSTATUS high
100 (3)
µs
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
100
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
µs
tDSU
Data setup time before rising edge on DCLK
5
ns
11–20
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
Table 11–8. FPP Timing Parameters for Arria GX Devices (Part 2 of 2)
Symbol
Parameter
Min
Notes (1), (2)
Max
Units
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
ns
fMAX
DCLK frequency
100
MHz
tR
Input rise time
40
ns
tF
Input fall time
tCD2UM
CONF_DONE high to user mode (4)
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
20
40
ns
100
µs
4 × maximum
DCLK period
tC D 2 C U +(299 ×
CLKUSR period)
Notes to Table 11–8:
(1)
(2)
(3)
(4)
This information is preliminary.
These timing parameters should be used when the decompression feature is not used.
This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
Altera Corporation
May 2008
11–21
Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
Figure 11–7 shows the timing waveform for FPP configuration when
using a MAX II device as an external host. This waveform shows the
timing when the decompression feature is enabled.
Figure 11–7. FPP Configuration Timing Waveform With Decompression Feature Enabled
Notes (1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
(3) nSTATUS
tSTATUS
tCF2ST0
(4) CONF_DONE
tCF2CD
DCLK
tCL
tST2CK
tCH
1
2
3
4
1
2
3
4
(6)
1
(6)
Byte 2
(5)
4
tCLK
DATA[7..0]
Byte 0
tDSU
User I/O
tDH
Byte 1
(5)
User Mode
Byte n
tDH
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 11–7:
(1)
(2)
(3)
(4)
(5)
(6)
This timing waveform should be used when the decompression feature is used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Arria GX device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the
dual-purpose pin settings. If needed, DCLK can be paused by holding it low. When DCLK restarts, the external host
must provide data on the DATA[7..0] pins prior to sending the first DCLK rising edge.
11–22
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
Table 11–9 defines the timing parameters for Arria GX devices for FPP
configuration when the decompression feature is enabled.
Table 11–9. FPP Timing Parameters for Arria GX Devices With Decompression Feature
Enabled
Notes (1), (2)
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
tCF2ST0
nCONFIG low to nSTATUS low
Min
Max
Units
800
ns
800
ns
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
100
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
µs
tDSU
Data setup time before rising edge on DCLK
5
ns
tDH
Data hold time after rising edge on DCLK
30
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
fMAX
tD ATA
µs
100 (3)
µs
100 (3)
µs
ns
DCLK frequency
100
MHz
Data rate
200
Mbps
tR
Input rise time
40
ns
tF
Input fall time
tCD2UM
CONF_DONE high to user mode (4)
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
20
40
ns
100
µs
4 × maximum
DCLK period
tC D 2 C U + (299 ×
CLKUSR period)
Notes to Table 11–9:
(1)
(2)
(3)
(4)
This information is preliminary.
These timing parameters should be used when the decompression feature is used.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
f
Altera Corporation
May 2008
Device configuration options and how to create configuration files are
discussed further in the Software Settings section in the Configuration
Handbook.
11–23
Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
FPP Configuration Using a Microprocessor
In the FPP configuration scheme, a microprocessor can control the
transfer of configuration data from a storage device, such as flash
memory, to the target Arria GX device.
1
All information in “FPP Configuration Using a MAX II Device
as an External Host” on page 11–13 is also applicable when
using a microprocessor as an external host. Refer to that section
for all configuration and timing information.
FPP Configuration Using an Enhanced Configuration Device
In the FPP configuration scheme, an enhanced configuration device sends
a byte of configuration data every DCLK cycle to the Arria GX device.
Configuration data is stored in the configuration device.
1
When configuring your Arria GX device using FPP mode and an
enhanced configuration device, the enhanced configuration
device decompression feature is available while the Arria GX
decompression feature is not.
Figure 11–8 shows the configuration interface connections between a
Arria GX device and the enhanced configuration device for single device
configuration.
1
f
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the device.
For more information on the enhanced configuration device and flash
interface pins, such as PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0], refer to the Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet in the Configuration Handbook.
11–24
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
Figure 11–8. Single Device FPP Configuration Using an Enhanced
Configuration Device
VCC (1)
Arria GX
Device
10 kΩ
(3) (3)
nCEO
GND
10 kΩ
Enhanced
Configuration
Device
DCLK
DATA[7..0]
OE (3)
nCS (3)
nINIT_CONF (2)
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
VCC (1)
N.C.
nCE
GND
Notes to Figure 11–8:
(1)
(2)
(3)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active. This means an external pull-up
resistor should not be used on the nINIT_CONF-nCONFIG line. The nINIT_CONF
pin does not need to be connected if its functionality is not used. If nINIT_CONF
is not used, nCONFIG must be pulled to VCC either directly or through a resistor. If
reconfiguration is required, a resistor is necessary.
The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.
The value of the internal pull-up resistors on the enhanced configuration
devices can be found in the Enhanced Configuration Devices (EPC4, EPC8
& EPC16) Data Sheet in the Configuration Handbook.
When using enhanced configuration devices, you can connect the
device’s nCONFIG pin to nINIT_CONF pin of the enhanced configuration
device, which allows the INIT_CONF JTAG instruction to initiate device
configuration. The nINIT_CONF pin does not need to be connected if its
functionality is not used. If nINIT_CONF is not used, nCONFIG must be
pulled to VCC either directly or through a resistor. An internal pull-up
resistor on the nINIT_CONF pin is always active in the enhanced
configuration devices, which means an external pull-up resistor should
not be used if nCONFIG is tied to nINIT_CONF.
Upon power-up, the Arria GX device goes through a POR. The POR delay
is dependent on the PORSEL pin setting: when PORSEL is driven low, the
POR time is approximately 100 ms; when PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
nSTATUS low, and tri-state all user I/O pins. The configuration device
also goes through a POR delay to allow the power supply to stabilize. The
POR time for enhanced configuration devices can be set to either 100 ms
or 2 ms, depending on its PORSEL pin setting. If the PORSEL pin is
connected to GND, the POR delay is 100 ms. If the PORSEL pin is
connected to VCC, the POR delay is 2 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device's
nSTATUS pin.
1
When selecting a POR time, you need to ensure that the device
completes power-up before the enhanced configuration device
exits POR. Altera recommends that you use a 12-ms POR time
for the Arria GX device, and use a 100-ms POR time for the
enhanced configuration device.
When both devices complete POR, they release their open-drain OE or
nSTATUS pin, which is then pulled high by a pull-up resistor. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors, which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Arria GX Device Handbook.
When the power supplies have reached the appropriate operating
voltages, the target device senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
VCCINT, VCCIO, and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration devices have an optional internal pull-up resistor on the OE
pin. This option is available in the Quartus II software from the General
tab of the Device & Pin Options dialog box. If this internal pull-up
resistor is not used, an external 10-kΩ pull-up resistor on the
OE-nSTATUS line is required. Once nSTATUS is released, the device is
ready to receive configuration data and the configuration stage begins.
11–26
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Altera Corporation
May 2008
Configuring Arria GX Devices
When nSTATUS is pulled high, the configuration device’s OE pin also
goes high and the configuration device clocks data out to the device using
the Arria GX device’s internal oscillator. The Arria GX devices receive
configuration data on the DATA[7..0] pins and the clock is received on
the DCLK pin. A byte of data is latched into the device on each rising edge
of DCLK.
After the device has received all configuration data successfully, it
releases the open-drain CONF_DONE pin which is pulled high by a pull-up
resistor. Because CONF_DONE is tied to the configuration device's nCS pin,
the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration devices have an optional internal pull-up
resistor on the nCS pin. This option is available in the Quartus II software
from the General tab of the Device & Pin Options dialog box. If this
internal pull-up resistor is not used, an external 10-kΩ pull-up resistor on
the nCS-CONF_DONE line is required. A low-to-high transition on
CONF_DONE indicates configuration is complete and initialization of the
device can begin.
In Arria GX devices, the initialization clock source is either the internal
oscillator (typically 10 MHz) or the optional CLKUSR pin. By default, the
internal oscillator is the clock source for initialization. If the internal
oscillator is used, the Arria GX device provides itself with enough clock
cycles for proper initialization. You also have the flexibility to
synchronize initialization of multiple devices or to delay initialization
with the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
CLKUSR will be enabled after the time specified as tCD2CU. After this time
period elapses, Arria GX devices require 299 clock cycles to initialize
properly and enter user mode. Arria GX devices support a CLKUSR fMAX
of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. In user-mode, the user
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
I/O pins will no longer have weak pull-up resistors and will function as
assigned in your design. The enhanced configuration device will drive
DCLK low and DATA[7..0] high at the end of configuration.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. Because the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-restart configuration
after error option (available in the Quartus II software from the General
tab of the Device & Pin Options dialog box) is turned on, the device will
automatically initiate reconfiguration if an error occurs. The Arria GX
device releases its nSTATUS pin after a reset time-out period (maximum
of 100 µs). When the nSTATUS pin is released and pulled high by a
pull-up resistor, the configuration device reconfigures the chain. If this
option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low for at least 2 µs to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the device
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. In this case, the configuration device pulls its OE pin
low, which in turn drives the target device’s nSTATUS pin low. If the
Auto-restart configuration after error option is set in the software, the
target device resets and then releases its nSTATUS pin after a reset
time-out period (maximum of 100 µs). When nSTATUS returns to a logic
high level, the configuration device will try to reconfigure the device.
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully.
Therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, you should use the CLKUSR option to synchronize
the initialization of multiple devices that are not in the same
configuration chain. Devices in the same configuration chain will
initialize together if their CONF_DONE pins are tied together.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, ensure
CLKUSR continues toggling during the time nSTATUS is low
(maximum of 100 µs).
When the device is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIG pin low. The nCONFIG pin should be low for at least
2 µs. When nCONFIG is pulled low, the device also pulls nSTATUS and
CONF_DONE low and all I/O pins are tri-stated. Because CONF_DONE is
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Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
pulled low, this activates the configuration device because it sees its nCS
pin drive low. Once nCONFIG returns to a logic high level and nSTATUS
is released by the device, reconfiguration begins.
Figure 11–9 shows how to configure multiple Arria GX devices with an
enhanced configuration device. This circuit is similar to the configuration
device circuit for a single device, except the Arria GX devices are
cascaded for multi-device configuration.
Figure 11–9. Multi-Device FPP Configuration Using an Enhanced Configuration Device
VCC (1)
VCC (1)
10 kΩ
(3)
(3)
Arria GX
Device 2
N.C.
nCEO
MSEL[3..0]
DATA[7..0]
DATA[7..0]
OE (3)
nCS (3)
nSTATUS
GND
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCE
DCLK
DCLK
DATA[7..0]
nSTATUS
GND
Enhanced
Configuration Device
Arria GX
Device 1
DCLK
MSEL[3..0]
nCEO
10 kΩ
nINIT_CONF (2)
nCE
GND
Notes to Figure 11–9:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-up resistors on configuration device option when generating programming files.
1
Enhanced configuration devices cannot be cascaded.
When performing multi-device configuration, you must generate the
configuration device’s POF from each project’s SOF. You can combine
multiple SOFs using the Convert Programming Files window in the
Quartus II software.
f
Altera Corporation
May 2008
For more information on how to create configuration files for multidevice configuration chains, refer to the Software Settings section in
volume 2 of the Configuration Handbook.
11–29
Arria GX Device Handbook, Volume 2
Fast Passive Parallel Configuration
In multi-device FPP configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA[7..0], and CONF_DONE) are connected to every device in the
chain. Pay special attention to the configuration signals because they may
require buffering to ensure signal integrity and prevent clock skew
problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Because all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the enhanced configuration device and
drives nSTATUS low on all devices, which causes them to enter a reset
state. This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
devices will release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the
Auto-restart configuration after error option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low
for at least 2 µs to restart configuration. The external system can pulse
nCONFIG if nCONFIG is under system control rather than tied to VCC.
Your system may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals may require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Devices must be the same density and package. All
devices will start and complete configuration at the same time.
Figure 11–10 shows multi-device FPP configuration when both Arria GX
devices are receiving the same configuration data.
11–30
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Altera Corporation
May 2008
Configuring Arria GX Devices
Figure 11–10. Multiple-Device FPP Configuration Using an Enhanced Configuration Device When Both
Devices Receive the Same Data
VCC (1)
VCC (1)
10 kΩ
(3)
(3)
Arria GX
Device 2
nSTATUS
N.C.
MSEL[3..0]
DATA[7..0]
CONF_DONE
nCONFIG
nCONFIG
nCE
DATA[7..0]
OE (3)
nCS (3)
nSTATUS
GND
CONF_DONE
nCEO
DCLK
DCLK
DATA[7..0]
GND
Enhanced
Configuration Device
Arria GX
Device 1
DCLK
MSEL[3..0]
nCEO
10 kΩ
nINIT_CONF (2)
nCE
GND
Notes to Figure 11–10:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single enhanced configuration chain to configure multiple
Arria GX devices with other Altera devices that support FPP
configuration, such as Arria GX devices. To ensure that all devices in the
chain complete configuration at the same time or that an error flagged by
one device initiates reconfiguration in all devices, all of the device
CONF_DONE and nSTATUS pins must be tied together.
f
Altera Corporation
May 2008
For more information about configuring multiple Altera devices in the
same configuration chain, refer to the Configuring Mixed Altera FPGA
Chains chapter in volume 2 of the Configuration Handbook.
11–31
Arria GX Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 11–11 shows the timing waveform for the FPP configuration
scheme using an enhanced configuration device.
Figure 11–11. Arria GX FPP Configuration Using an Enhanced Configuration Device Timing Waveform
nINIT_CONF or
VCC/nCONFIG
tLOE
OE/nSTATUS
nCS/CONF_DONE
tHC
tCE
tLC
DCLK
DATA[7..0]
Driven High
byte
1
byte
2
byte
n
tOE
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
tCD2UM (1)
Note to Figure 11–11:
(1)
The initialization clock can come from the Arria GX device’s internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8 & EPC16) Data Sheet in volume 2 of the Configuration
Handbook.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings section of the Configuration
Handbook.
Active Serial
Configuration
(Serial
Configuration
Devices)
f
In the AS configuration scheme, Arria GX devices are configured using a
serial configuration device. These configuration devices are low-cost
devices with non-volatile memory that feature a simple four-pin interface
and a small form factor. These features make serial configuration devices
an ideal low-cost configuration solution.
For more information on serial configuration devices, refer to the Serial
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128)
Data Sheet in volume 2 of the Configuration Handbook.
Serial configuration devices provide a serial interface to access
configuration data. During device configuration, Arria GX devices read
configuration data via the serial interface, decompresses data if necessary,
and configures their SRAM cells. This scheme is referred to as the AS
11–32
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
configuration scheme because the device controls the configuration
interface. This scheme contrasts with the PS configuration scheme, where
the configuration device controls the interface.
1
The Arria GX decompression feature is fully available when
configuring your Arria GX device using AS mode.
Table 11–10 shows the MSEL pin settings when using the AS configuration
scheme.
Table 11–10. Arria GX MSEL Pin Settings for AS Configuration Schemes
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
Fast AS (40 MHz) (1)
1
0
0
0
Remote system upgrade fast AS (40 MHz)
(1)
1
0
0
1
AS (20 MHz) (1)
1
1
0
1
Remote system upgrade AS (20 MHz) (1)
1
1
1
0
Note to Table 11–10:
(1)
Only the EPCS16 and EPCS64 devices support a DCLK up to 40 MHz clock; other
EPCS devices support a DCLK up to 20 MHz. Refer to the Serial Configuration
Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet in volume 2 of
the Configuration Handbook for more information.
Serial configuration devices have a four-pin interface: serial clock input
(DCLK), serial data output (DATA), AS data input (ASDI), and an
active-low chip select (nCS). This four-pin interface connects to Arria GX
device pins, as shown in Figure 11–12.
Altera Corporation
May 2008
11–33
Arria GX Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 11–12. Single Device AS Configuration
VCC (1)
VCC (1)
10 kΩ
10 kΩ
VCC (1)
10 kΩ
Serial Configuration
Device
Arria GX FPGA
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
VCC
GND
DATA
DATA0
(3) MSEL3
DCLK
DCLK
(3) MSEL2
nCS
nCSO
(3) MSEL1
ASDI
ASDO
(3) MSEL0
(2)
N.C.
GND
Notes to Figure 11–12:
(1)
(2)
(3)
Connect the pull-up resistors to a 3.3-V supply.
Arria GX devices use the ASDO to ASDI path to control the configuration device.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 11–10
for more details.
Upon power-up, Arria GX devices go through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. If PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS and CONF_DONE low, and tri-state all user I/O pins. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Arria GX Device Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
After POR, the Arria GX devices release nSTATUS, which is pulled high
by an external 10-kΩ pull-up resistor, and enters configuration mode.
1
11–34
Arria GX Device Handbook, Volume 2
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
Altera Corporation
May 2008
Configuring Arria GX Devices
The serial clock (DCLK) generated by Arria GX devices controls the entire
configuration cycle and provides the timing for the serial interface. Arria
GX devices use an internal oscillator to generate DCLK. Using the MSEL[]
pins, you can select to use either a 40- or 20-MHz oscillator.
1
f
Only the EPCS16 and EPCS64 devices support a DCLK up to
40-MHz clock; other EPCS devices support a DCLK up to
20-MHz.
Refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64,
and EPCS128) Data Sheet in volume 2 of the Configuration Handbook for
more information.
The EPCS4 device only supports the smallest Arria GX (EP2S15) device,
which is when the SOF compression is enabled. Because of its insufficient
memory capacity, the EPCS1 device does not support any Arria GX
devices.
Table 11–11 shows the active serial DCLK output frequencies.
Table 11–11. Active Serial DCLK Output Frequency
Note (1)
Oscillator
Minimum
Typical
Maximum
Units
40 MHz (2)
20
26
40
MHz
20 MHz
10
13
20
MHz
Notes to Table 11–11:
(1)
(2)
These values are preliminary.
Only the EPCS16 and EPCS64 devices support a DCLK up to 40-MHz clock; other
EPCS devices support a DCLK up to 20-MHz. Refer to the Serial Configuration
Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet in volume 2 of
the Configuration Handbook for more information.
In both AS and fast AS configuration schemes, the serial configuration
device latches input and control signals on the rising edge of DCLK and
drives out configuration data on the falling edge. Arria GX devices drive
out control signals on the falling edge of DCLK and latch configuration
data on the falling edge of DCLK.
In configuration mode, Arria GX devices enable the serial configuration
device by driving the nCSO output pin low, which connects to the chip
select (nCS) pin of the configuration device. Arria GX devices use the
serial clock (DCLK) and serial data output (ASDO) pins to send operation
commands and/or read address signals to the serial configuration device.
The configuration device provides data on its serial data output (DATA)
pin, which connects to the DATA0 input of the Arria GX devices.
Altera Corporation
May 2008
11–35
Arria GX Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
After all configuration bits are received by the Arria GX device, it releases
the open-drain CONF_DONE pin, which is pulled high by an external
10-kΩ resistor. Initialization begins only after the CONF_DONE signal
reaches a logic high level. All AS configuration pins (DATA0, DCLK, nCSO,
and ASDO) have weak internal pull-up resistors that are always active.
After configuration, these pins are set as input tri-stated and are driven
high by the weak internal pull-up resistors. The CONF_DONE pin must
have an external 10-kΩ pull-up resistor in order for the device to initialize.
In Arria GX devices, the initialization clock source is either the 10-MHz
(typical) internal oscillator (separate from the active serial internal
oscillator) or the optional CLKUSR pin. By default, the internal oscillator
is the clock source for initialization. If the internal oscillator is used, the
Arria GX device provides itself with enough clock cycles for proper
initialization. You also have the flexibility to synchronize initialization of
multiple devices or to delay initialization with the CLKUSR option. The
Enable user-supplied start-up clock (CLKUSR) option can be turned on
in the Quartus II software from the General tab of the Device & Pin
Options dialog box. When you Enable the user supplied start-up clock
option, the CLKUSR pin is the initialization clock source. Supplying a
clock on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
CLKUSR is enabled after 600 ns. After this time period elapses, Arria GX
devices require 299 clock cycles to initialize properly and enter user
mode. Arria GX devices support a CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the device has entered user mode. When initialization is
complete, the device enters user mode. In user mode, the user I/O pins
no longer have weak pull-up resistors and function as assigned in your
design.
If an error occurs during configuration, Arria GX devices assert the
nSTATUS signal low, indicating a data frame error, and the CONF_DONE
signal stays low. If the Auto-restart configuration after error option
(available in the Quartus II software from the General tab of the Device
& Pin Options dialog box) is turned on, the Arria GX device resets the
configuration device by pulsing nCSO, releases nSTATUS after a reset
11–36
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
time-out period (maximum of 100 µs), and retries configuration. If this
option is turned off, the system must monitor nSTATUS for errors and
then pulse nCONFIG low for at least 2 µs to restart configuration.
When the Arria GX device is in user mode, you can initiate
reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin
should be low for at least 2 µs. When nCONFIG is pulled low, the device
also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Once nCONFIG returns to a logic high level and nSTATUS is released by
the Arria GX device, reconfiguration begins.
You can configure multiple Arria GX devices using a single serial
configuration device. You can cascade multiple Arria GX devices using
the chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in
the chain must have its nCE pin connected to ground. You must connect
its nCEO pin to the nCE pin of the next device in the chain. When the first
device captures all of its configuration data from the bitstream, it drives
the nCEO pin low, enabling the next device in the chain. You must leave
the nCEO pin of the last device unconnected. The nCONFIG, nSTATUS,
CONF_DONE, DCLK, and DATA0 pins of each device in the chain are
connected (refer to Figure 11–13).
This first Arria GX device in the chain is the configuration master and
controls configuration of the entire chain. You must connect its MSEL pins
to select the AS configuration scheme. The remaining Arria GX devices
are configuration slaves and you must connect their MSEL pins to select
the PS configuration scheme. Any other Altera device that supports PS
configuration can also be part of the chain as a configuration slave.
Figure 11–13 shows the pin connections for this setup.
Altera Corporation
May 2008
11–37
Arria GX Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 11–13. Multi-Device AS Configuration
VCC (1)
VCC (1)
10 kΩ
VCC (1)
10 kΩ
10 kΩ
Serial Configuration
Device
Arria GX
FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
VCC
(2) MSEL3
Arria GX
FPGA Slave
nSTATUS
CONF_DONE
nCEO
nCONFIG
nCE
DATA0
(2) MSEL2
DCLK
(2) MSEL1
(2) MSEL0
N.C.
MSEL3
VCC
MSEL2
MSEL1
MSEL0
GND
GND
Notes to Figure 11–13:
(1)
(2)
Connect the pull-up resistors to a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 11–10 on page 11–33 for more details.
As shown in Figure 11–13, the nSTATUS and CONF_DONE pins on all
target devices are connected together with external pull-up resistors.
These pins are open-drain bidirectional pins on the devices. When the
first device asserts nCEO (after receiving all of its configuration data), it
releases its CONF_DONE pin. But the subsequent devices in the chain keep
this shared CONF_DONE line low until they have received their
configuration data. When all target devices in the chain have received
their configuration data and have released CONF_DONE, the pull-up
resistor drives a high level on this line and all devices simultaneously
enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is
driven low by the failing device. If you enable the Auto-restart
configuration after error option, reconfiguration of the entire chain begins
after a reset time-out period (a maximum of 100 µs). If the Auto-restart
configuration after error option is turned off, the external system must
monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under
system control rather than tied to VCC.
1
11–38
Arria GX Device Handbook, Volume 2
While you can cascade Arria GX devices, serial configuration
devices cannot be cascaded or chained together.
Altera Corporation
May 2008
Configuring Arria GX Devices
If the configuration bitstream size exceeds the capacity of a serial
configuration device, you must select a larger configuration device
and/or enable the compression feature. When configuring multiple
devices, the size of the bitstream is the sum of the individual devices’
configuration bitstreams.
A system may have multiple devices that contain the same configuration
data. In active serial chains, this can be implemented by storing two
copies of the SOF in the serial configuration device. The first copy would
configure the master Arria GX device; the second copy would configure
all remaining slave devices concurrently. All slave devices must be the
same density and package. The setup is similar to Figure 11–13, where the
master is set up in active serial mode and the slave devices are set up in
passive serial mode.
To configure four identical Arria GX devices with the same SOF, you
could set up the chain similar to the example shown in Figure 11–14. The
first device is the master device and its MSEL pins should be set to select
AS configuration. The other three slave devices are set up for concurrent
configuration and its MSEL pins should be set to select PS configuration.
The nCEO pin from the master device drives the nCE input pins on all
three slave devices, and the DATA and DCLK pins connect in parallel to all
four devices. During the first configuration cycle, the master device reads
its configuration data from the serial configuration device while holding
nCEO high. After completing its configuration cycle, the master drives
nCE low and transmits the second copy of the configuration data to all
three slave devices, configuring them simultaneously.
Altera Corporation
May 2008
11–39
Arria GX Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 11–14. Multi-Device AS Configuration When devices Receive the Same Data
Arria GX
FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC (1)
VCC (1)
10 kΩ
N.C.
VCC (1)
MSEL3
DATA0
10 kΩ
nCEO
10 kΩ
VCC
MSEL2
DCLK
MSEL1
MSEL0
GND
Serial Configuration
Device
Arria GX
FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
Arria GX
FPGA Slave
VCC
(2) MSEL3
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC
MSEL2
DCLK
(2) MSEL1
N.C.
MSEL3
DATA0
(2) MSEL2
nCEO
MSEL1
(2) MSEL0
MSEL0
GND
GND
Arria GX
FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nCEO
N.C.
MSEL3
VCC
MSEL2
MSEL1
MSEL0
GND
Notes to Figure 11–14:
(1)
(2)
Connect the pull-up resistors to a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 11–10 on page 11–33 for more details.
11–40
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
Estimating Active Serial Configuration Time
Active serial configuration time is dominated by the time it takes to
transfer data from the serial configuration device to the Arria GX device.
This serial interface is clocked by the Arria GX DCLK output (generated
from an internal oscillator). As listed in Table 11–11 on page 11–35, the
DCLK minimum frequency when choosing to use the 40-MHz oscillator is
20 MHz (50 ns). Therefore, the maximum configuration time estimate for
an EP2S15 device (5 MBits of uncompressed data) is:
RBF Size (minimum DCLK period / 1 bit per DCLK cycle) = estimated
maximum configuration time
5 Mbits × (50 ns / 1 bit) = 250 ms
To estimate the typical configuration time, use the typical DCLK period as
listed in Table 11–11. With a typical DCLK period of 38.46 ns, the typical
configuration time is 192 ms. Enabling compression reduces the amount
of configuration data that is transmitted to the Arria GX device, which
also reduces configuration time. On average, compression reduces
configuration time by 50%.
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based
devices. You can program these devices in-system using the USB-Blaster™
or ByteBlaster™ II download cable. Alternatively, you can program them
using the Altera Programming Unit (APU), supported third-party
programmers, or a microprocessor with the SRunner software driver.
You can perform in-system programming of serial configuration devices
via the AS programming interface. During in-system programming, the
download cable disables device access to the AS interface by driving the
nCE pin high. Arria GX devices are also held in reset by a low level on
nCONFIG. After programming is complete, the download cable releases
nCE and nCONFIG, allowing the pull-down and pull-up resistors to drive
GND and VCC, respectively. Figure 11–15 shows the download cable
connections to the serial configuration device.
f
Altera Corporation
May 2008
For more information about the USB Blaster download cable, refer to the
USB-Blaster USB Port Download Cable User Guide. For more information
about the ByteBlaster II cable, refer to the ByteBlaster II Download Cable
User Guide.
11–41
Arria GX Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 11–15. In-System Programming of Serial Configuration Devices
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Arria GX FPGA
CONF_DONE
nSTATUS
Serial
Configuration
Device
nCEO
N.C.
nCONFIG
nCE
10 kΩ
VCC
DATA
DATA0
(3) MSEL3
DCLK
DCLK
nCS
nCSO
(3) MSEL1
ASDI
ASDO
(3) MSEL0
(3) MSEL2
GND
Pin 1
VCC (2)
USB Blaster or ByteBlaser II
(AS Mode)
10-Pin Male Header
Notes to Figure 11–15:
(1)
(2)
Connect these pull-up resistors to 3.3-V supply.
Power up the ByteBlaster II cable's VCC with a 3.3-V supply.
(3)
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 11–10
on page 11–33 for more details.
You can program serial configuration devices with the Quartus II
software with the Altera programming hardware and the appropriate
configuration device programming adapter. The EPCS1 and EPCS4
devices are offered in an eight-pin small outline integrated circuit (SOIC)
package.
In production environments, serial configuration devices can be
programmed using multiple methods. Altera programming hardware or
other third-party programming hardware can be used to program blank
serial configuration devices before they are mounted onto printed circuit
11–42
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
boards (PCBs). Alternatively, you can use an on-board microprocessor to
program the serial configuration device in-system using C-based
software drivers provided by Altera.
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming,
which can be easily customized to fit in different embedded systems.
SRunner is able to read a raw programming data (.rpd) file and write to
the serial configuration devices. The serial configuration device
programming time using SRunner is comparable to the programming
time with the Quartus II software.
f
For more information about SRunner, refer to AN 418: SRunner: An
Embedded Solution for Serial Configuration and the source code on the
Altera web site at www.altera.com.
f
For more information on programming serial configuration devices,
refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64,
and EPCS128) Data Sheet in volume 2 of the Configuration Handbook.
Figure 11–16 shows the timing waveform for the AS configuration
scheme using a serial configuration device.
Figure 11–16. AS Configuration Timing
tCF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
tCL
DCLK
tCH
tDH
ASDO
Read Address
tDSU
DATA0
bit N
bit N − 1
bit 1
bit 0
tCD2UM (1)
INIT_DONE
User Mode
User I/O
Note to Figure 11–16:
(1)
The initialization clock can come from the Arria GX device’s internal oscillator or the CLKUSR pin.
Altera Corporation
May 2008
11–43
Arria GX Device Handbook, Volume 2
Passive Serial Configuration
Table 11–12 shows the AS timing parameters for Arria GX devices.
Table 11–12. AS Timing Parameters for Arria GX Devices
Symbol
Parameter
Condition
Minimum
tC F 2 S T 1
nCONFIG high to nSTATUS high
tD S U
Data setup time before falling edge
on DCLK
7
tD H
Data hold time after falling edge on
0
Typical
Maximum
100
DCLK
tC H
DCLK high time
10
tC L
DCLK low time
10
tC D 2 U M
CONF_DONE high to user mode
20
Passive Serial
Configuration
100
PS configuration of Arria GX devices can be performed using an
intelligent host, such as a MAX II device or microprocessor with flash
memory, an Altera configuration device, or a download cable. In the PS
scheme, an external host (MAX II device, embedded processor,
configuration device, or host PC) controls configuration. Configuration
data is clocked into the target Arria GX device via the DATA0 pin at each
rising edge of DCLK.
1
The Arria GX decompression feature is fully available when
configuring your Arria GX device using PS mode.
Table 11–13 shows the MSEL pin settings when using the PS configuration
scheme.
Table 11–13. Arria GX MSEL Pin Settings for PS Configuration Schemes
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
PS
0
0
1
0
PS when using Remote System Upgrade (1)
0
1
1
0
Note to Table 11–13:
(1)
This scheme requires that you drive the RUnLU pin to specify either remote
update or local update. For more information about remote system upgrade in
Arria GX devices, refer to the Remote System Upgrades with Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook.
11–44
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Configuring Arria GX Devices
PS Configuration Using a MAX II Device as an External Host
In the PS configuration scheme, a MAX II device can be used as an
intelligent host that controls the transfer of configuration data from a
storage device, such as flash memory, to the target Arria GX device.
Configuration data can be stored in RBF, HEX, or TTF format.
Figure 11–17 shows the configuration interface connections between a
Arria GX device and a MAX II device for single device configuration.
Figure 11–17. Single Device PS Configuration Using an External Host
Memory
ADDR
DATA0
(1) VCC
10 k Ω
VCC (1)
Arria GX
Device
10 k Ω
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCEO
nCE
N.C.
MSEL3
GND
DATA0
MSEL2
nCONFIG
MSEL1
DCLK
VCC
MSEL0
GND
Note to Figure 11–17:
(1)
Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. VCC should be high
enough to meet the VIH specification of the I/O on the device and the external host.
Upon power-up, Arria GX devices go through a POR. The POR delay is
dependent on the PORSEL pin setting: when PORSEL is driven low, the
POR time is approximately 100 ms; when PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device resets, holds
nSTATUS low, and tri-states all user I/O pins. Once the device
successfully exits POR, all user I/O pins continue to be tri-stated. If
nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors
which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
Altera Corporation
May 2008
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Arria GX Device Handbook.
11–45
Arria GX Device Handbook, Volume 2
Passive Serial Configuration
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the MAX II device must generate a low-to-high
transition on the nCONFIG pin.
1
VCCINT, VCCIO, and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device should place the configuration data, one
bit at a time, on the DATA0 pin. If you are using configuration data in RBF,
HEX, or TTF format, you must send the least significant bit (LSB) of each
data byte first. For example, if the RBF contains the byte sequence 02 1B
EE 01 FA, the serial bitstream you should transmit to the device is
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
Arria GX devices receive configuration data on the DATA0 pin and the
clock is received on the DCLK pin. Data is latched into the device on the
rising edge of DCLK. Data is continuously clocked into the target device
until CONF_DONE goes high. After the device has received all
configuration data successfully, it releases the open-drain CONF_DONE
pin, which is pulled high by an external 10-kΩ pull-up resistor. A
low-to-high transition on CONF_DONE indicates configuration is complete
and initialization of the device can begin. The CONF_DONE pin must have
an external 10-kΩ pull-up resistor in order for the device to initialize.
In Arria GX devices, the initialization clock source is either the internal
oscillator (typically 10 MHz) or the optional CLKUSR pin. By default, the
internal oscillator is the clock source for initialization. If the internal
oscillator is used, the Arria GX device provides itself with enough clock
cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to
the device after configuration is complete does not affect device
operation.
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. The Enable
user-supplied start-up clock (CLKUSR) option can be turned on in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR will not affect the configuration
process. After all configuration data has been accepted and CONF_DONE
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May 2008
Configuring Arria GX Devices
goes high, CLKUSR will be enabled after the time specified as tCD2CU. After
this time period elapses, Arria GX devices require 299 clock cycles to
initialize properly and enter user mode. Arria GX devices support a
CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The MAX II device
must be able to detect this low-to-high transition which signals the device
has entered user mode. When initialization is complete, the device enters
user mode. In user-mode, the user I/O pins will no longer have weak
pull-up resistors and will function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[0] pin is available as
a user I/O pin after configuration. When the PS scheme is chosen in the
Quartus II software, as a default, this I/O pin is tri-stated in user mode
and should be driven by the MAX II device. To change this default option
in the Quartus II software, select the Dual-Purpose Pins tab of the Device
& Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options dialog box) is turned
on, the Arria GX device releases nSTATUS after a reset time-out period
(maximum of 100 µs). After nSTATUS is released and pulled high by a
pull-up resistor, the MAX II device can try to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse
of at least 2 µs) on nCONFIG to restart the configuration process.
Altera Corporation
May 2008
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Passive Serial Configuration
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but CONF_DONE