Si5368 Data Sheet

Si5368 Data Sheet
Si5368
A N Y - F REQUENCY P RECISION C L O C K M ULTIPLIER / J ITTER
A TTENUATOR
Features
Copyright © 2012 by Silicon Laboratories
VDD
CKOUT3+
CKOUT3–
VDD
NC
VDD
CKOUT1–
CKOUT1+
VDD
NC
FS_OUT–
VDD
FS_OUT+
VDD
CMODE
VDD
CKOUT2+
CKOUT2–
74
NC
3
73
NC
4
72
NC
VDD
5
71
SDI
VDD
6
70
A2_SS
GND
GND
7
69
A1
8
68
A0
C1B
9
67
NC
C2B
C3B
10
66
NC
11
65
T_ALM
12
64
GND
GND
0_C3A
13
63
VDD
GND
14
62
VDD
VDD
15
61
SDA_SDO
XA
60
SCL
XB
16
17
59
C2A
GND
18
58
C1A
GND
19
57
CS1_C4A
NC
20
56
NC
ALIGN
21
55
INC
NC
22
23
54
53
DEC
NC
Si5368
GND PAD
NC
NC
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LOL
NC
NC
CKIN1–
GND
CKIN1+
GND
RATE1
GND
CKIN3–
CKIN3+
GND
NC
GND
CKIN2–
24
25
NC
52
CKIN2+
NC
Rev. 1.0 8/12
NC
VDD
NC
2
NC
NC
The Si5368 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock
inputs ranging from 2 kHz to 710 MHz and generates five clock outputs
ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation combination across this
operating range. The outputs are divided down separately from a common
source. The Si5368 input clock frequency and clock multiplication ratio are
programmable through an I2C or SPI interface. The Si5368 is based on
Silicon Laboratories' third-generation DSPLL® technology, which provides
any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and loop filter
components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating
from a single 1.8, 2.5 ,or 3.3 V supply, the Si5368 is ideal for providing
clock multiplication and jitter attenuation in high performance timing
applications.
VDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
GND
Description
NC
NC
RST
RATE0
Data converter clocking
OTN/WDM Muxponder, MSPP,
ROADM line cards
SONET/SDH + PDH clock
synthesis
Test and measurement
Synchronous Ethernet
 Broadcast video
GND
SONET/SDH OC-48/STM-16/OC- 

192/STM-64 line cards
 GbE/10GbE, 1/2/4/8/10/16G Fibre
Channel

 ITU G.709 and custom FEC line

cards
 Wireless basestations


CKOUT4–
VDD
Applications
CKOUT4+
Pin Assignments
CKIN4–

VDD

Ordering Information:
See page 79.
CKIN4+

VDD

Supports holdover and freerun
modes of operation
Five clock outputs with
selectable signal format
(LVPECL, LVDS, CML, CMOS)
SONET frame sync switching
and regeneration
Support for ITU G.709 and
custom FEC ratios (253/226,
239/237, 255/238, 255/237,
255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjust
I2C or SPI programmable
settings
Pb-free, RoHS compliant
GND

Generates any frequency from

2 kHz to 945 MHz and select

frequencies to 1.4 GHz from an
input frequency of 2 kHz to
710 MHz
Ultra-low jitter clock outputs with

jitter generation as low as 300 fs

rms (12 kHz–20 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter

specifications
Four clock inputs with manual or 
automatically controlled hitless
switching and phase build-out

Small size: 14 x 14 mm 100-pin
TQFP

GND

Si5368
Si5368
Functional Block Diagram
Xtal or Refclock
CKIN1
÷ N31
CKIN2
÷ N32
CKIN3/FSYNC1
÷ N33
CKIN4
÷ N34
DSPLL
®
÷ NC1_LS
CKOUT1
÷ NC2_LS
CKOUT2
÷ NC3_LS
CKOUT3
÷ NC4_LS
CKOUT4
÷ NC5_LS
CKOUT5/FS_OUT
÷ N1_HS
÷ N2
2
I C/SPI Port
Rate Select
Clock Select
Skew Control
Control
FSYNC Realignment
Device Interrupt
LOL/LOS/FOS Alarms
2
Frame sync
mode only
{
Rev. 1.0
Input Clock 3
VDD (1.8, 2.5, or 3.3 V)
Input Clock 4
Output Clock 2
GND
Si5368
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7. Pin Descriptions: Si5368 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9. Package Outline: 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11. Top Marking: 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.1. Si5368 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Document Change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Rev. 1.0
3
Si5368
1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Parameter
Symbol
Ambient Temperature
TA
Supply Voltage during
Normal Operation
VDD
Test Condition
Min
Typ
Max
Unit
–40
25
85
C
3.3 V Nominal2
2.97
3.3
3.63
V
2.5 V Nominal
2.25
2.5
2.75
V
1.8 V Nominal
1.71
1.8
1.89
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
2. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Table 2. DC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Supply Current1,6
Symbol
Test Condition
Min
Typ
Max
Unit
IDD
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
—
394
435
mA
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
—
253
284
mA
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
—
278
400
mA
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
—
229
261
mA
Disable Mode
—
165
—
mA
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
4
Rev. 1.0
Si5368
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VICM
1.8 V ± 5%
0.9
—
1.4
V
2.5 V ± 10%
1
—
1.7
V
3.3 V ± 10%
1.1
—
1.95
V
CKNRIN
Single-ended
20
40
60
k
Single-Ended Input
Voltage Swing
(See Absolute Specs)
VISE
fCKIN < 212.5 MHz
See Figure 1.
0.2
—
—
VPP
fCKIN > 212.5 MHz
See Figure 1.
0.25
—
—
VPP
Differential Input
Voltage Swing
(See Absolute Specs)
VID
fCKIN < 212.5 MHz
See Figure 1.
0.2
—
—
VPP
fCKIN > 212.5 MHz
See Figure 1.
0.25
—
—
VPP
CKOVCM
LVPECL 100  load
line-to-line
VDD –1.42
—
VDD –1.25
V
Differential Output
Swing
CKOVD
LVPECL 100  load
line-to-line
1.1
—
1.9
VPP
Single Ended Output
Swing
CKOVSE
LVPECL 100  load
line-to-line
0.5
—
0.93
VPP
Differential Output Voltage
CKOVD
CML 100  load lineto-line
350
425
500
mVPP
Common Mode Output
Voltage
CKOVCM
CML 100  load lineto-line
—
VDD-0.36
—
V
CKINn Input Pins2
Input Common Mode
Voltage (Input Threshold Voltage)
Input Resistance
Output Clocks (CKOUTn)3,5,6
Common Mode
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Rev. 1.0
5
Si5368
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Differential Output Voltage
CKOVD
LVDS
100  load line-to-line
500
700
900
mVPP
Low Swing LVDS
100  load line-to-line
350
425
500
mVPP
CKOVCM
LVDS 100 load lineto-line
1.125
1.2
1.275
V
CKORD
CML, LVPECL, LVDS
—
200
—

Output Voltage Low
CKOVOLLH
CMOS
—
—
0.4
V
Output Voltage High
CKOVOHLH
VDD = 1.71 V
CMOS
0.8 x VDD
—
—
V
CKOIO
ICMOS[1:0] =11
VDD = 1.8 V
—
7.5
—
mA
ICMOS[1:0] =10
VDD = 1.8 V
—
5.5
—
mA
ICMOS[1:0] =01
VDD = 1.8 V
—
3.5
—
mA
ICMOS[1:0] =00
VDD = 1.8 V
—
1.75
—
mA
ICMOS[1:0] =11
VDD = 3.3 V
—
32
—
mA
ICMOS[1:0] =10
VDD = 3.3 V
—
24
—
mA
ICMOS[1:0] =01
VDD = 3.3 V
—
16
—
mA
ICMOS[1:0] =00
VDD = 3.3 V
—
8
—
mA
Common Mode Output
Voltage
Differential Output
Resistance
Output Drive Current
(CMOS driving into
CKOVOL for output low
or CKOVOH for output
high. CKOUT+ and
CKOUT– shorted
externally)
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
6
Rev. 1.0
Si5368
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD = 1.71 V
—
—
0.5
V
VDD = 2.25 V
—
—
0.7
V
VDD = 2.97 V
—
—
0.8
V
VDD = 1.89 V
1.4
—
—
V
VDD = 2.25 V
1.8
—
—
V
VDD = 3.63 V
2.5
—
—
V
2-Level LVCMOS Input Pins
Input Voltage Low
Input Voltage High
VIL
VIH
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Rev. 1.0
7
Si5368
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3-Level Input Pins4
Input Voltage Low
VILL
—
—
0.15 x VDD
V
Input Voltage Mid
VIMM
0.45 x
VDD
—
0.55 x VDD
V
Input Voltage High
VIHH
0.85 x
VDD
—
—
V
Input Low Current
IILL
See Note 4
–20
—
—
µA
Input Mid Current
IIMM
See Note 4
–2
—
+2
µA
Input High Current
IIHH
See Note 4
—
—
20
µA
VOL
IO = 2 mA
VDD = 1.71 V
—
—
0.4
V
IO = 2 mA
VDD = 2.97 V
—
—
0.4
V
IO = –2 mA
VDD = 1.71 V
VDD –0.4
—
—
V
IO = –2 mA
VDD = 2.97 V
VDD –0.4
—
—
V
LVCMOS Output Pins
Output Voltage Low
Output Voltage Low
Output Voltage High
Output Voltage High
VOH
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
8
Rev. 1.0
Si5368
Table 3. AC Specifications
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XARIN
RATE[1:0] = LM, MH,
ac coupled
—
12
—
k
Input Voltage Swing
XAVPP
RATE[1:0] = LM, MH,
ac coupled
0.5
—
1.2
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
XA/XBVPP
RATE[1:0] = LM, MH
0.5
—
2.4
VPP
CKNF
Input frequency and clock
multiplication ratio determined by programming
device PLL dividers. Consult Silicon Laboratories
configuration software
DSPLLsim or Any-Frequency Precision Clock
Family Reference Manual
at www.silabs.com/timing
(click on Documentation)
to determine PLL divider
settings for a given input
frequency/clock multiplication ratio combination
0.002
—
710
MHz
0.002
—
0.512
MHz
40
—
60
%
2
—
—
ns
—
—
3
pF
—
—
11
ns
CKINn Input Pins
Input Frequency
Input Clock Frequency
(CKIN3, CKIN4 used
as FSYNC inputs)
CKF
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC
Input Capacitance
CKNCIN
Input Rise/Fall Time
CKNTRF
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
20–80%
See Figure 2
*Note: Input to output phase skew after an ICAL is not controlled and can assume any value.
Rev. 1.0
9
Si5368
Table 3. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
N1  6
0.002
—
945
MHz
N1 = 5
970
—
1134
MHz
N1 = 4
1.213
—
1.4
GHz
—
—
212.5
MHz
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not configured for CMOS or
Disabled)
Maximum Output
Frequency in CMOS
Format
CKOF
CKOF
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKOTRF
Output not configured for
CMOS or Disabled
See Figure 2
—
230
350
ps
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD = 1.71
CLOAD = 5 pF
—
—
8
ns
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD = 2.97
CLOAD = 5 pF
—
—
2
ns
Output Duty Cycle
Uncertainty @
622.08 MHz
CKODC
100  Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
—
—
±40
ps
LVCMOS Input Pins
Minimum Reset Pulse
Width
tRSTMN
Reset to Microprocessor Access Ready
tREADY
Input Capacitance
1
Cin
µs
10
ms
—
—
3
pF
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD = 20pf
See Figure 2
—
25
—
ns
LOSn Trigger Window
LOSTRIG
From last CKINn to 
Internal detection of LOSn
N3 ≠ 1
—
—
4.5 x N3
TCKIN
Time to Clear LOL
after LOS Cleared
tCLRLOL
LOS to LOL
Fold = Fnew
Stable Xa/XB reference
—
10
—
ms
*Note: Input to output phase skew after an ICAL is not controlled and can assume any value.
10
Rev. 1.0
Si5368
Table 3. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clock Skew
tSKEW
 of CKOUTn to  of
CKOUT_m, CKOUTn
and CKOUT_m at same
frequency and signal
format
PHASEOFFSET = 0
CKOUT_ALWAYS_ON = 1
SQ_ICAL = 1
—
—
100
ps
Phase Change due to
Temperature
Variation*
tTEMP
Max phase changes from
–40 to +85 °C
—
300
500
ps
Device Skew
PLL Performance
(fin = fout = 622.08 MHz; BW = 120 Hz; LVPECL)
Lock Time
tLOCKMP
Start of ICAL to of LOL
—
35
1200
ms
Output Clock Phase
Change
tP_STEP
After clock switch
f3  128 kHz
—
200
—
ps
—
0.05
0.1
dB
Jitter Frequency Loop
Bandwidth
5000/BW
—
—
ns pk-pk
1 kHz Offset
—
–106
—
dBc/Hz
10 kHz Offset
—
–121
—
dBc/Hz
100 kHz Offset
—
–132
—
dBc/Hz
1 MHz Offset
—
–132
—
dBc/Hz
Max spur @ n x F3
(n  1, n x F3 < 100 MHz)
—
–93
–70
dBc
Closed Loop Jitter
Peaking
JPK
Jitter Tolerance
JTOL
Phase Noise
fout = 622.08 MHz
CKOPN
Spurious Noise
SPSPUR
*Note: Input to output phase skew after an ICAL is not controlled and can assume any value.
Rev. 1.0
11
Si5368
Table 4. Microprocessor Control
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
I2C Bus Lines (SDA, SCL)
Input Voltage Low
VILI2C
—
—
0.25 x VDD
V
Input Voltage High
VIHI2C
0.7 x VDD
—
VDD
V
VDD = 1.8V
0.1 x VDD
—
—
V
VDD = 2.5 or 3.3 V
0.05 x VDD
—
—
V
VDD = 1.8 V
IO = 3 mA
—
—
0.2 x VDD
V
VDD = 2.5 or 3.3 V
IO = 3 mA
—
—
0.4
V
Hysteresis of Schmitt
trigger inputs
Output Voltage Low
12
VHYSI2C
VOLI2C
Rev. 1.0
Si5368
Table 4. Microprocessor Control (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Duty Cycle, SCLK
tDC
SCLK = 10 MHz
40
—
60
%
Cycle Time, SCLK
tc
100
—
—
ns
Rise Time, SCLK
tr
20–80%
—
—
25
ns
Fall Time, SCLK
tf
20–80%
—
—
25
ns
Low Time, SCLK
tlsc
20–20%
30
—
—
ns
High Time, SCLK
thsc
80–80%
30
—
—
ns
Delay Time, SCLK Fall
to SDO Active
td1
—
—
25
ns
Delay Time, SCLK Fall
to SDO Transition
td2
—
—
25
ns
Delay Time, SS Rise
to SDO Tri-state
td3
—
—
25
ns
Setup Time, SS to
SCLK Fall
tsu1
25
—
—
ns
Hold Time, SS to
SCLK Rise
th1
20
—
—
ns
Setup Time, SDI to
SCLK Rise
tsu2
25
—
—
ns
Hold Time, SDI to
SCLK Rise
th2
20
—
—
ns
Delay Time between
Slave Selects
tcs
25
—
—
ns
SPI Specifications
Rev. 1.0
13
Si5368
Table 5. Jitter Generation
Parameter
Jitter Gen
OC-192
Symbol
JGEN
Test Condition*
Measurement
Filter
DSPLL
BW2
0.02–80 MHz
120 Hz
4–80 MHz
0.05–80 MHz
Jitter Gen
OC-48
JGEN
0.12–20 MHz
Min
Typ
Max
GR-253Specification
Unit
—
4.2
6.2
30
psPP
—
.27
0.42
N/A
psrms
—
3.7
6.4
10
psPP
—
.14
0.31
N/A
psrms
—
4.4
6.9
10
psPP
—
.26
0.41
1.0
ps rms
—
3.5
5.4
40.2
psPP
—
.27
0.41
4.02
ps rms
120 Hz
120 Hz
120 Hz
*Note: Test conditions:
1. fIN = fOUT = 622.08 MHz
2.
Clock input: LVPECL
3.
Clock output: LVPECL
4.
PLL bandwidth: 120 Hz
5.
114.285 MHz 3rd OT crystal used as XA/XB input
6.
VDD = 2.5 V
7.
TA = 85 °C
8.
Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs per Telecordia
GR-253-CORE.
Table 6. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Thermal Resistance Junction to Ambient
14
Symbol
Test Condition
Value
Unit
JA
Still Air
31
C°/W
Rev. 1.0
Si5368
Table 7. Absolute Maximum Limits
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
3.8
V
VDD+0.3
V
DC Supply Voltage
VDD
–0.5
LVCMOS Input Voltage
VDIG
–0.3
CKINn Voltage Level Limits
CKNVIN
0
—
VDD
V
XA/XB Voltage Level Limits
XAVIN
0
—
1.2
V
Operating Junction Temperature
TJCT
–55
—
150
ºC
Storage Temperature Range
TSTG
–55
—
150
ºC
2
—
—
kV
ESD MM Tolerance; All pins
except CKIN+/CKIN–
150
—
—
V
ESD HBM Tolerance
(100 pF, 1.5 k); CKIN+/CKIN–
700
—
—
V
ESD MM Tolerance;
CKIN+/CKIN–
100
—
—
V
ESD HBM Tolerance
(100 pF, 1.5 k); All pins except
CKIN+/CKIN–
Latch-up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operations sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Rev. 1.0
15
Si5368
SIGNAL +
Differential I/Os VICM , VOCM
V
VISE , VOSE
SIGNAL –
(SIGNAL +) – (SIGNAL –)
Differential Peak-to-Peak Voltage
VID,VOD
VICM, VOCM
Single-Ended
Peak-to-Peak Voltage
t
SIGNAL +
VID = (SIGNAL+) – (SIGNAL–)
SIGNAL –
Figure 1. Differential Voltage Characteristics
80%
CKIN, CKOUT
20%
tF
tR
Figure 2. Rise/Fall Time Characteristics
16
Rev. 1.0
Si5368
2. Typical Phase Noise Performance
Figure 3. Typical Phase Noise Plot
Table 8. RMS Jitter by Band
Jitter Band
Jitter, RMS
SONET_OC48, 12 kHz to 20 MHz
249 fs
SONET_OC192_A, 20 kHz to 80 MHz
274 fs
SONET_OC192_B, 4 MHz to 80 MHz
166 fs
SONET_OC192_C, 50 kHz to 80 MHz
267 fs
Brick Wall_800 Hz to 80 MHz
274 fs
*Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass
(–60 dB/Dec) roll-offs per Telecordia GR-253-CORE.
Rev. 1.0
17
Si5368
3. Typical Application Circuits
C10
System
Power
Supply
Ferrite
Bead
Option 1:
Crystal
1 µF
Option 2:
Ext. Refclk
114.285 MHz
C1–9
0.1 µF
0.1 µF
VDD = 3.3 V
CKIN1+
XA
XB
XA
XB
GND
130 
VDD
0.1 µF
130 
CKOUT1+
CKOUT1–
82 
CKOUT4+
Input
Clock
Sources*
0.1 µF
0.1 µF
–
+
Clock
Outputs
100 
VDD = 3.3 V
130 
CKOUT4–
130 
FS_OUT+
CKIN4+
Si5368
82 
INC
DEC
DEC
Rate
RATE[1:0]
Reset
0.1 µF
0.1 µF
INT_ALM
82 
INC
Control Mode (L)
0.1 µF
–
+
100 
FS_OUT–
CKIN4–
–
Interrupt/Alarm Output
Indicator
CnB
CKINn Invalid Indicator
(n = 1 to 3)
LOL
PLL Loss of Lock
Indicator
A[2:0]
Serial Port
Address
CMODE
SDA
Serial Data
RST
SCL
Serial Clock
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 4. Si5368 Typical Application Circuit (I2C Control Mode)
18
+
100 
CKIN1–
82 
0.1 µF
Rev. 1.0
I2C
Interface
Si5368
C10
System
Power
Supply
Ferrite
Bead
Option 1:
Crystal
1 µF
Option 2:
Ext. Refclk
114.285 MHz
C1–9
0.1 µF
0.1 µF
VDD = 3.3 V
CKIN1+
XA
XB
XA
XB
GND
130 
VDD
0.1 µF
130 
CKOUT1+
CKOUT1–
82 
CKOUT4+
Input
Clock
Sources*
CKOUT4–
130 
FS_OUT+
CKIN4+
CKIN4–
82 
0.1 µF
0.1 µF
–
+
Clock
Outputs
100 
VDD = 3.3 V
130 
+
100 
CKIN1–
82 
0.1 µF
Si5368
0.1 µF
0.1 µF
–
+
100 
FS_OUT–
82 
0.1 µF
INT_ALM
–
Interrupt/Alarm Output
Indicator
CnB
CKINn Invalid Indicator
(n = 1 to 3)
INC
INC
LOL
PLL Loss of Lock
Indicator
DEC
DEC
SS
Slave Select
Rate
RATE[1:0]
Control Mode (H)
Reset
CMODE
RST
SDO
Serial Data
Out
SDI
Serial Data
In
SCL
Serial Clock
SPI
Interface
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 5. Si5368 Typical Application Circuit (SPI Control Mode)
Rev. 1.0
19
Si5368
4. Functional Description
The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter
performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five clock
outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any
frequency translation combination across this operating range. Independent dividers are available for every input
clock and output clock, so the Si5368 can accept input clocks at different frequencies and it can generate output
clocks at different frequencies. The Si5368 input clock frequency and clock multiplication ratio are programmable
through an I2C or SPI interface. Optionally, the fifth clock output can be configured as a 2 to 512 kHz SONET/SDH
frame synchronization output that is phase aligned with one of the high-speed output clocks. Silicon Laboratories
offers a PC-based software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a
given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption.
This utility can be downloaded from http://www.silabs.com/timing (click on Documentation).
The Si5368 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The Si5368 PLL loop bandwidth is digitally programmable and supports a range from 60 Hz
to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input
clock frequency/clock multiplication ratio.
The Si5368 supports hitless switching between input clocks in compliance with GR-253-CORE and GR-1244CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock
transition (<200 ps typ). Manual, automatic revertive and non-revertive input clock switching options are available.
The Si5368 monitors the four input clocks for loss-of-signal and provides a LOS alarm when it detects missing
pulses on any of the four input clocks. The device monitors the lock status of the PLL. The lock detect algorithm
works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The
Si5368 monitors the frequency of CKIN1, CKIN2, CKIN3, and CKIN4 with respect to a selected reference
frequency and generates a frequency offset alarm (FOS) if the threshold is exceeded. This FOS feature is available
for SONET applications in which both the monitored frequency on CKIN1, CKIN3, and CKIN4 and the reference
frequency are integer multiples of 19.44 MHz. Both Stratum 3/3E and SONET Minimum Clock (SMC) FOS
thresholds are supported.
The Si5368 provides a digital hold capability that allows the device to continue generation of a stable output clock
when the selected input reference is lost. During digital hold, the DSPLL generates an output frequency based on
a historical average that existed a fixed amount of time before the error event occurred, eliminating the effects of
phase and frequency transients that may occur immediately preceding digital hold.
Fine phase adjustment is available and is set using the FLAT register bits. The nominal range and resolution of the
FLAT[14:0] latency adjustment word are: ±110 ps and 3 ps, respectively.
The Si5368 has five differential clock outputs. The electrical format of the clock outputs is programmable to support
LVPECL, LVDS, CML, or CMOS loads. If not required, unused clock outputs can be powered down to minimize
power consumption. The phase difference between the selected input clock and the output clocks is adjustable in
200 ps increments for system skew control. In addition, the phase of one output clock may be adjusted in relation
to the phase of the other output clock. The resolution varies from 800 ps to 2.2 ns depending on the PLL divider
settings. Consult the DSPLLsim configuration software to determine the phase offset resolution for a given input
clock/clock multiplication ratio combination. For system-level debugging, a bypass mode is available which drives
the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
4.1. External Reference
An external, 38.88 MHz clock or a low-cost 114.285 MHz 3rd overtone crystal is used as part of a fixed-frequency
oscillator within the DSPLL. This external reference is required for the device to operate. Silicon Laboratories
recommends using a high-quality crystal. Specific recommendations may be found in the Family Reference
Manual. An external clock from a high-quality OCXO or TCXO can also be used as a reference for the device.
In digital hold, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference
when the DSPLL is in digital hold, will be tracked by the output of the device. Note that crystals can have
temperature sensitivities.
20
Rev. 1.0
Si5368
4.2. Further Documentation
Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed
information about the Si5368. Additional design support is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration,
including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from
http://www.silabs.com/timing; click on Documentation.
Rev. 1.0
21
Si5368
5. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, such as Register 64, should never be written to.
Register
D7
0
1
D6
D5
FREE_RUN
CKOUT_
ALWAYS_
ON
CK_PRIOR4 [1:0]
2
D4
D3
D2
D1
CK_CONFIG_REG
CK_PRIOR3 [1:0]
D0
BYPASS_
REG
CK_PRIOR2 [1:0]
CK_PRIOR1 [1:0]
BWSEL_REG [3:0]
3
CKSEL_REG [1:0]
4
AUTOSEL_REG [1:0]
5
ICMOS [1:0]
DHOLD
SQ_ICAL
HIST_DEL [4:0]
SFOUT2_REG [2:0]
SFOUT1_REG [2:0]
6
SFOUT4_REG [2:0]
SFOUT3_REG [2:0]
7
SFOUT5_REG [2:0]
FOSREFSEL [2:0]
8
HLOG_4 [1:0]
HLOG_3 [1:0]
9
HIST_AVG [4:0]
10
DSBL5_
REG
11
HLOG_2 [1:0]
HLOG_5 [1:0]
ALIGN_THR [2:0]
12
FPW_VALID
FSYNC_
ALIGN_REG
FSYNC_
ALIGN_
MODE
FSYNC_
SWTCH_
REG
DSBL4_
REG
DSBL3_
REG
DSBL2_
REG
DSBL1_
REG
PD_CK4
PD_CK3
PD_CK2
PD_CK1
FSKEW_
VALID
FSYNC_
SKEW
[16:16]
13
FSYNC_PW [7:0]
14
FSYNC_SKEW [15:8]
15
FSYNC_SKEW [7:0]
16
CLAT [7:0]
17
HLOG_1 [1:0]
FLAT_VALID
FSYNC_PW [9:8]
FLAT [14:8]
18
FLAT [7:0]
19
FOS_EN
FOS_THR [1:0]
20
21
INCDEC_
PIN
22
FSYNC_
ALIGN_POL
22
FSYNC_
POL
VALTIME [1:0]
LOCKT [2:0]
ALRMOUT_PIN
CK3_BAD_
PIN
CK2_BAD_
PIN
CK1_BAD_
PIN
LOL_PIN
INT_PIN
FSYNC_
ALIGN_PIN
CK4_ACTV_PIN
CK3_ACTV_PIN
CK2_ACTV_PIN
CK1_ACTV_PIN
CKSEL_PIN
FSYNCOUT_POL
CK_ACTV_
POL
CK_BAD_
POL
LOL_POL
INT_POL
Rev. 1.0
Si5368
Register
D4
D3
D2
D1
D0
23
LOS4_MSK
LOS3_MSK
LOS2_MSK
LOS1_MSK
LOSX_MSK
24
ALIGN_MSK FOS4_MSK
FOS3_MSK
FOS2_MSK
FOS1_MSK
LOL_MSK
25
D7
D6
D5
N1_HS [2:0]
NC1_LS [19:16]
26
NC1_LS [15:8]
27
NC1_LS [7:0]
28
NC2_LS [19:16]
29
NC2_LS [15:8]
30
NC2_LS [7:0]
31
NC3_LS [19:16]
32
NC3_LS [15:8]
33
NC3_LS [7:0]
34
NC4_LS [19:16]
35
NC4_LS [15:8]
36
NC4_LS [7:0]
37
NC5_LS [19:16]
38
NC5_LS [15:8]
39
NC5_LS [7:0]
40
N2_HS [2:0]
N2_LS [19:16]
41
N2_LS [15:8]
42
N2_LS [7:0]
43
N31_ [18:16]
44
N31_[15:8]
45
N31_ [7:0]
46
N32_ [18:16]
47
N31_ [15:8]
48
N32_[7:0]
49
N33_[18:16]
50
N33_[15:8]
51
N33_[7:0]
52
53
N34_[18:16]
N34_[15:8]
Rev. 1.0
23
Si5368
Register
D7
D6
D5
D4
54
D3
D2
D1
D0
N34_[7:0]
55
CLKIN2RATE_[2:0]
CLKIN1RATE[2:0]
56
CLKIN4RATE_[2:0]
CLKIN3RATE[2:0]
128
129
130
CLATPROGRESS
DIGHOLDVALID
ALIGN_INT
131
132
ALIGN_FLG
FOS4_FLG
CK4_ACTV_REG
CK3_ACTV_REG
CK2_ACTV_REG
CK1_ACTV_REG
LOS4_INT
LOS3_INT
LOS2_INT
LOS1_INT
LOSX_INT
FOS4_INT
FOS3_INT
FOS2_INT
FOS1_INT
LOL_INT
LOS4_FLG
LOS3_FLG
LOS2_FLG
LOS1_FLG
LOSX_FLG
FOS3_FLG
FOS2_FLG
FOS1_FLG
LOL_FLG
AIGN_ERR
[8:8]
133
ALIGN_ERR [7:0]
134
PARTNUM_RO [11:4]
135
136
PARTNUM_RO [3:0]
RST_REG
REVID_RO [3:0]
ICAL
138
139
LOS4_EN
[0:0]
LOS3_EN
[0:0]
LOS2_EN
[0:0]
LOS1_EN
[0:0]
LOS4_EN
[1:1]
LOS3_EN
[1:1]
LOS2_EN
[1:1]
LOS1_EN
[1:1]
FOS4_EN
FOS3_EN
FOS2_EN
FOS1_EN
140
INDEPENDENTSKEW1 [7:0]
141
INDEPENDENTSKEW2 [7:0]
142
INDEPENDENTSKEW3 [7:0]
143
INDEPENDENTSKEW4 [7:0]
144
INDEPENDENTSKEW5 [7:0]
24
Rev. 1.0
Si5368
6. Register Descriptions
Register 0.
Bit
D7
Name
Type
D6
D5
FREE_
RUN
CKOUT_
ALWAYS_ON
R/W
R/W
R
D4
D3
D2
CK_CONFIG_REG
R
R/W
D1
D0
BYPASS_
REG
R
R/W
R
Reset value = 0001 0100
Bit
Name
7
Reserved
6
FREE_RUN
5
Function
Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its external
reference.
0: Disable Free Run
1: Enable
CKOUT_
CKOUT Always On.
ALWAYS_ON This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on
and ICAL is not complete or successful. See Table 9.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output. Note: The frequency may be significantly off until the part is
calibrated.
4
Reserved
3
CK_CONFIG_REG
2
Reserved
1
BYPASS_
REG
0
Reserved
CK_CONFIG_REG.
This bit controls the input clock configuration for either normal CLKIN function or FSYNC
operation. Whenever CK_CONFIG_REG = 1, FSYNC_ALIGN_MODE must not be set to
1.
0: CKIN_1, 2, 3, 4 inputs do not have a synchronized relationship. CLKOUT5 is an independent output. There is no FSYNCOUT.
1: CKIN_1, 3 and CKIN_2, 4 Clock/FSYNC pairs. CKOUT5 is configured as the FSYNC
output.
Bypass Register.
This bit enables or disables the PLL bypass mode. Use is only valid when the part is in
digital hold or before the first ICAL.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.
Bypass mode does not support CMOS clock outputs.
Rev. 1.0
25
Si5368
Register 1.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CK_PRIOR4 [1:0]
CK_PRIOR3 [1:0]
CK_PRIOR2 [1:0]
CK_PRIOR1 [1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 1110 0100
Bit
26
Name
Function
7:6
CK_PRIOR4 [1:0] Selects which of the input clocks will be 4th priority in the autoselection state
machine.
00: CKIN1 is 4th priority
01: CKIN2 is 4th priority
10: CKIN3 is 4th priority
11: CKIN4 is 4th priority
5:4
CK_PRIOR3 [1:0] Selects which of the input clocks will be 3rd priority in the autoselection state
machine.
00: CKIN1 is 3rd priority
01: CKIN2 is 3rd priority
10: CKIN3 is 3rd priority
11: CKIN4 is 3rd priority
3:2
CK_PRIOR2 [1:0] CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state
machine.
00: CKIN1 is 2nd priority
01: CKIN2 is 2nd priority
10: CKIN3 is 2nd priority
11: CKIN4 is 2nd priority
1:0
CK_PRIOR1 [1:0] CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state
machine.
00: CKIN1 is 1st priority
01: CKIN2 is 1st priority
10: CKIN3 is 1st priority
11: CKIN4 is 1st priority
Rev. 1.0
Si5368
Register 2.
Bit
D7
D6
D5
Name
BWSEL_REG [3:0]
Type
R/W
D4
D3
D2
D1
D0
R
R
R
R
Reset value = 0100 0010
Bit
7:4
3:0
Name
Function
BWSEL_REG [3:0] BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to take
effect.
Reserved
Rev. 1.0
27
Si5368
Register 3.
Bit
D7
D6
D5
D4
Name
CKSEL_REG [1:0]
DHOLD
SQ_ICAL
Type
R/W
R/W
R/W
D3
D2
D1
D0
R
R
R
R
Reset value = 0000 0101
Bit
7:6
28
Name
Function
CKSEL_REG [1:0] CKSEL_REG.
If the device is operating in manual register-based clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input
clock will be the active input clock. If CKSEL_PIN = 1, the CKSEL[1:0] input pins
continue to control clock selection and CKSEL_REG is of no consequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: CKIN_3 selected.
11: CKIN_4 selected.
5
DHOLD
4
SQ_ICAL
3:0
Reserved
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic
clock selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all
of the input clocks.
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. See Table 9.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
Rev. 1.0
Si5368
Register 4.
Bit
D7
D6
Name
AUTOSEL_REG [1:0]
Type
R/W
D5
D4
D3
D2
D1
D0
HIST_DEL [4:0]
R
R/W
Reset value = 0001 0010
Bit
Name
7:6
AUTOSEL_REG [1:0]
5
Reserved
4:0
HIST_DEL [4:0]
Function
AUTOSEL_REG [1:0].
Selects method of input clock selection to be used.
00: Manual (either register or pin controlled. See CKSEL_PIN).
01: Automatic Non-Revertive
10: Automatic Revertive
11: Reserved
HIST_DEL [4:0].
Selects amount of delay to be used in generating the history information
MHIST, the value of M used during Digital Hold.
Rev. 1.0
29
Si5368
Register 5.
Bit
D7
D6
D5
D4
D3
D2
D1
Name
ICMOS [1:0]
SFOUT2_REG [2:0]
SFOUT1_REG [2:0]
Type
R/W
R/W
R/W
D0
Reset value = 1110 1101
Bit
7:6
Name
ICMOS [1:0]
5:3
SFOUT2_
REG [2:0]
2:0
SFOUT1_
REG [2:0]
Function
ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buffer drive
strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation.
These values assume CKOUT+ is tied to CKOUT–.
00: 8 mA/2 mA
01: 16 mA/4 mA
10: 24 mA/6 mA
11: 32 mA (3.3 V operation)/8 mA (1.8 V operation)
SFOUT2_REG [2:0].
Controls output signal format and disable for CKOUT2 output buffer. The LVPECL and
CMOS output formats draw more current than either LVDS or CML; however, there are
restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four
enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are
five enabled outputs, there can be no more than three outputs that are either LVPECL or
CMOS.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported.)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
SFOUT1_REG [2:0].
Controls output signal format and disable for CKOUT1 output buffer. The LVPECL and
CMOS output formats draw more current than either LVDS or CML; however, there are
restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four
enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are
five enabled outputs, there can be no more than three outputs that are either LVPECL or
CMOS.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported.)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
30
Rev. 1.0
Si5368
Register 6.
Bit
D7
D6
Name
Type
R
R
D5
D4
D3
D2
D1
SFOUT4_REG [2:0]
SFOUT3_REG [2:0]
R/W
R/W
D0
Reset value = 0010 1100
Bit
7:6
5:3
2:0
Name
Reserved
SFOUT4_REG [2:0]
SFOUT3_REG [2:0]
Function
SFOUT4_REG [2:0].
Controls output signal format and disable for CKOUT4 output buffer. The
LVPECL and CMOS output formats draw more current than either LVDS or
CML; however, there are restrictions in the allowed output format pin settings so
that the maximum power dissipation for the TQFP devices is limited when they
are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs,
the fifth output must be disabled. When there are five enabled outputs, there can
be no more than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported.)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
SFOUT3_REG [2:0].
Controls output signal format and disable for CKOUT3 output buffer. The
LVPECL and CMOS output formats draw more current than either LVDS or
CML; however, there are restrictions in the allowed output format pin settings so
that the maximum power dissipation for the TQFP devices is limited when they
are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs,
the fifth output must be disabled. When there are five enabled outputs, there can
be no more than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported.)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Rev. 1.0
31
Si5368
Register 7.
Bit
D7
D6
D5
Name
Type
R
R
D4
D3
D2
D1
SFOUT5_REG [2:0]
FOSREFSEL [2:0]
R/W
R/W
D0
Reset value = 0010 1010
Bit
Name
7:6
Reserved.
5:3
Function
Reserved.
SFOUT5_REG [2:0] SFOUT5_REG [2:0]
Controls output signal format and disable for CKOUT5 output buffer. The
LVPECL and CMOS output formats draw more current than either LVDS or CML;
however, there are restrictions in the allowed output format pin settings so that
the maximum power dissipation for the TQFP devices is limited when they are
operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the
fifth output must be disabled. When there are five enabled outputs, there can be
no more than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0
32
FOSREFSEL [2:0]
FOSREFSEL [2:0].
Selects which input clock is used as the reference frequency for Frequency OffSet (FOS) alarms.
000: XA/XB (External reference)
001: CKIN1
010: CKIN2
011: CKIN3
100: CKIN4
101: Reserved
110: Reserved
111: Reserved
Rev. 1.0
Si5368
Register 8.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
HLOG_4[1:0]
HLOG_3[1:0]
HLOG_2[1:0]
HLOG_1[1:0]
Type
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7:6
HLOG_4 [1:0] HLOG_4 [1:0].
00: Normal operation
01: Holds CKOUT4 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT4 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
5:4
HLOG_3 [1:0] HLOG_3 [1:0].
00: Normal operation
01: Holds CKOUT3 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT3 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved.
3:2
HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved.
1:0
HLOG_1 [1:0] HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
Rev. 1.0
33
Si5368
Register 9.
Bit
D7
D6
D5
Name
HIST_AVG [4:0]
Type
R/W
D4
D3
D2
D1
D0
HLOG_5 [1:0]
R
R/W
Reset value = 1100 0000
34
Bit
Name
7:3
HIST_AVG [4:0]
2
Reserved
1:0
HLOG_5 [1:0]
Function
HIST_AVG [4:0].
Selects amount of averaging time to be used in generating MHIST, the value of M
used
during digital hold. See Family Reference Manual for settings.
HLOG_5 [1:0].
00: Normal Operation
01: Holds CKOUT5 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT5 output at static logic 1. Entrance and exit from this state will
occur without glitches or runt pulses.
11: Reserved
Rev. 1.0
Si5368
Register 10.
Bit
D7
D6
D4
DSBL5_
REG
Name
Type
D5
R
R
R/W
R
D3
D2
D1
D0
DSBL4_
REG
DSBL3_
REG
DSBL2_
REG
DSBL1_
REG
R/W
R/W
R
R
Reset value = 0000 0000
Bit
Name
7:6
Reserved
5
4
Function
DSBL5_REG DSBL5_REG.
This bit controls the powerdown and disable of the CKOUT5 output buffer. If disable
mode is selected, the NC5_LS output divider is also powered down.
0: CKOUT5 enabled.
1: CKOUT5 disabled.
Reserved
3
DSBL4_REG DSBL4_REG.
This bit controls the powerdown and disable of the CKOUT4 output buffer. If disable
mode is selected, the NC4 output divider is also powered down.
0'b=CKOUT4 enabled
1'b=CKOUT4 disabled
2
DSBL3_REG DSBL3_REG.
This bit controls the powerdown and disable of the CKOUT3 output buffer. If disable
mode is selected, the NC3 output divider is also powered down.
0: CKOUT3 enabled
1: CKOUT3 disabled
1
DSBL2_REG DSBL2_REG.
This bit controls the powerdown and disable of the CKOUT2 output buffer. If disable
mode is selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
0
DSBL1_REG DSBL1_REG.
This bit controls the powerdown and disable of the CKOUT1 output buffer. If disable
mode is selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
Rev. 1.0
35
Si5368
Register 11.
Bit
D7
D5
D4
ALIGN_THR [2:0]
Name
Type
D6
R/W
R/W
R/W
R
D3
D2
D1
D0
PD_CK4
PD_CK3
PD_CK2
PD_CK1
R/W
R/W
R/W
R/W
Reset value = 0100 0000
36
Bit
Name
Function
7:5
ALIGN_THR [2:0]
ALIGN_THR [2:0].
These bits control the threshold for the alignment error alarm. Input to output sync
phase skews that deviate more than the alignment threshold from the ideal value
(set by FSYNC_SKEW[16:0]) in either the leading or lagging direction trigger the
alignmentalarm. Value is in units of Tclkout2.
000: 4
001: 8
010: 16
011: 32
100: 48
101: 64
110: 96
111: 128
4
Reserved
3
PD_CK4
PD_CK4.
This bit controls the powerdown of the CKIN4 input buffer.
0: CKIN4 enabled
1: CKIN4 disabled
2
PD_CK3
PD_CK3.
This bit controls the powerdown of the CKIN3 input buffer.
0: CKIN3 enabled
1: CKIN3 disabled
1
PD_CK2
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
0
PD_CK1
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
Rev. 1.0
Si5368
Register 12.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
FPW_
VALID
FSYNC_
ALIGN_
REG
FSYNC_
ALIGN_
MODE
FSYNC_
SWTCH_
REG
FSKEW_
VALID
FSYNC_
SKEW
[16:16]
FSYNC_PW [9:8]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 1000 1000
Bit
Name
Function
7
FPW_VALID
FPW_VALID.
When in frame sync mode (CK_CONFIG_REG=1), before writing either a new FSYNC_PW[9:0] or NC5_LS [19:0] value, this bit must be set to zero. This causes the existing
FSYNC_PW [9:0] or NC5_LS[19:0] value to be held by the internal state machine for use
while the new values are written. Once the new FSYNC_PW [9:0] or NC5_LS [19:0] values are completely written, set FPW_VALID = 1 to enable their use.
0: Memorize existing FSYNC_PW[9:0] and NC5_LS [19:0] values and ignore
intermediate register values during write of new FSYNC_PW [9:0] and NC5_LS [19:0]
values.
1: Use FSYNC_PW[9:0] value directly from registers
6
5
4
3
FSYNC_
FSYNC_ALIGN_REG.
ALIGN_REG If FSYNC_ALIGN_PIN=0, this bit controls realignment of FSYNCOUT to the active sync
input (CKIN_3 or CKIN_4). If FSYNC_ALIGN_PIN=1, the FSYNC_ALIGN pin controls
this function.
0: No realignment
1: Active
FSYNC_
ALIGN_
MODE
FSYNC_ALIGN_MODE.
This bit must be set to 1 when in frame sync mode (when CK_CONFIG_REG = 1).
FSYNC_
FSYNC_SWTCH_REG.
SWTCH_REG Enables or disables the use of the CKIN3 and CKIN4 loss-of-signal indicators as inputs to
the automatic clock selection state machine for the clock configuration mode supporting
frame sync switching (CK_CONFIG=1 or CK_CONFIG_REG=1).
0: CKIN3 and CKIN4 status not used in clock selection
1: CKIN3 and CKIN4 status used in clock selection
FSKEW_
VALID
FSKEW_VALID.
Before writing a new FSYNC_SKEW[16:0] value, this bit must be set to zero, which
causes the existing FSYNC_SKEW[16:0] value to be held internally by the skew
alignment state machine for use while the new value is being written. Once the new
FSYNC_SKEW[16:0] is completely written, set FSKEW_VALID=1 to enable its use.
0: Memorize existing FSYNC_SKEW[16:0] value and ignore intermediate register values
during write of new FSYNC_SKEW value.
1: Use FSYNC_SKEW[[16:0] value directly from registers.
Rev. 1.0
37
Si5368
Bit
2
1:0
Name
Function
FSYNC_
FSYNC_SKEW [16:0].
SKEW [16:0] Phase skew control for FSYNCOUT. The resolution of the skew control is 1/fCKOUT2.
Entered values should be less than the FSYNCOUT period.
0 0000 0000 0000 0000=Zero phase skew.
0 0000 0000 0000 0001=Delay of 1 period of CLKOUT_2.
1 0010 1111 1011 1111=Delay of 77,759 periods of CKOUT2. If CKOUT2=622.08 MHz
and FSYNCOUT=8 kHz, this delay equals 125 ms - 1/fCKOUT2 and is the maximum
value that should be entered.
1 1111 1111 1111 1111=Delay of 131,071 periods of CKOUT2.
FSYNC_
PW [9:0]
FSYNC_PW [9:0].
These bits control the pulse width of the FSYNCOUT signal. The resolution of the pulse
width control is 1/fCKOUT2.
0000000000=50% duty cycle.
0000000001=1 period of CKOUT2.
0000000010=2 periods of CKOUT2.
1111111111=1023 periods of CKOUT2.
Register 13.
Bit
D7
D6
D5
D4
D3
Name
FSYNC_PW [7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0001
Bit
7:0
Name
Function
FSYNC_PW [7:0] FSYNC_PW [7:0].
See Register 12.
Register 14.
Bit
D7
D6
D5
D4
D3
Name
FSYNC_SKEW [15:8]
Type
R/W
Reset value = 0000 0000
Bit
7:0
38
Name
Function
FSYNC_SKEW [15:8] FSYNC_SKEW [15:8].
See Register 12.
Rev. 1.0
Si5368
Register 15.
Bit
D7
D6
D5
D4
D3
Name
FSYNC_SKEW [7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
Name
Function
7:0
FSYNC_SKEW [7:0]
FSYNC_SKEW [7:0].
See Register 12.
Register 16.
Bit
D7
D6
D5
D4
D3
Name
CLAT [7:0]
Type
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0
CLAT [7:0]
CLAT [7:0].
With INCDEC_PIN=0, this register sets the phase delay for CKOUT_n in units of
N1_HS/Fosc. Note: This can take as long as 20 seconds.
01111111: +127 x 1/fOSC (2s compliment)
00000000: 0
1000000: –128 x 1/fOSC (2s compliment)
If N2–HS[2:0] = 000, CLAT does not work.
Rev. 1.0
39
Si5368
Register 17.
Bit
D7
D6
D5
D4
D3
Name FLAT_VALID
D1
D0
FLAT [14:8]
R/W
Type
D2
R/W
Reset value = 1000 0000
Bit
7
6:0
Name
Function
FLAT_VAILD FLAT_VAILD.
Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the
existing FLAT[14:0] value to be held internally for use while the new value is being written. Once the new FLAT[14:0] value is completely written, set FLAT_VALID = 1 to enable
its use.
0: Memorize existing FLAT[14:0] value and ignore intermediate register values during
write of new FLAT[14:0] value.
1: Use FLAT[14:0] value directly from registers.
FLAT [14:0]
FLAT [14:0].
Fine resolution control for overall device latency from input clocks to output clocks.
Positive values increase the skew. See DSPLLsim for details.
Register 18.
Bit
D7
D6
D5
D4
D3
Name
FLAT [7:0]
Type
R/W
Reset value = 0000 0000
40
Bit
Name
7:0
FLAT [7:0]
Function
FLAT [7:0].
See Register 17.
Rev. 1.0
D2
D1
D0
Si5368
Register 19.
Bit
D7
D6
D5
D4
D3
D2
D1
Name
FOS_EN
FOS_THR [1:0]
VALTIME [1:0]
LOCKT [2:0]
Type
R/W
R/W
R/W
R/W
D0
Reset value = 0010 1100
Bit
Name
Function
7
FOS_EN
FOS_EN.
Frequency offset enable globally disables FOS. See the individual FOS enables (FOSx_EN, register 139).
00: FOS disable
01: FOS enabled by FOSx_EN
6:5
FOS_THR [1:0] FOS_THR [1:0].
Frequency Offset at which FOS is declared:
00: ± 11 to 12 ppm Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK.
01: ± 48 to 49 ppm (SMC).
10: ± 30 ppm SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
4:3
VALTIME [1:0]
VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 seconds
2:0
LOCKT [2:0]
LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is triggered by phase slip in DSPLL. Refer to the Family Reference Manual for more details.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: 833 us
Rev. 1.0
41
Si5368
Register 20.
Bit
D7
D6
D4
D3
D2
ALRCK3_BAD_ CK2_BAD_ CK1_BAD_
MOUT_PIN
PIN
PIN
PIN
Name
Type
D5
R
R
R/W
R/W
R/W
D1
D0
LOL_PIN
INT_PIN
R/W
R/W
R/W
Reset value = 0011 1100
42
Bit
Name
Function
7:6
Reserved
5
ALRMOUT_PIN
ALRMOUT_PIN.
The ALRMOUT status can be reflected on the ALRMOUT output pin. The request to
reflect the interrupt status on this pin (INT_PIN=1) overrides the ALRMOUT_PIN
request.
0: ALRMOUT not reflected on output pin. Output pin disabled if INT_PIN=0.
1: ALRMOUT reflected to output pin if INT_PIN=0. If INT_PIN=1, interrupt status
appears on the output pin and ALRMOUT is not available on an output pin.
4
CK3_BAD_PIN
CK3_BAD_PIN.
The CK3_BAD status can be reflected on the C3B output pin.
0: C3B output pin tristated
1: C3B status reflected to output pin
3
CK2_BAD_PIN
CK2_BAD_PIN.
The CK2_BAD status can be reflected on the C2B output pin.
0: C2B output pin tristated
1: C2B status reflected to output pin
2
CK1_BAD_PIN
CK1_BAD_PIN.
The CK1_BAD status can be reflected on the C1B output pin.
0: C1B output pin tristated
1: C1B status reflected to output pin
1
LOL_PIN
LOL_PIN.
The LOL_INT status bit can be reflected on the LOL output pin.
0: LOL output pin tristated
1: LOL_INT status reflected to output pin
0
INT_PIN
INT_PIN.
Reflects the interrupt status on the INT output pin.
0: Interrupt status not displayed on INT output pin. If ALRMOUT_PIN = 0, output pin is
tristated.
1: Interrupt status reflected to output pin. ALRMOUT_PIN ignored.
Rev. 1.0
Si5368
Register 21.
Bit
D7
D6
Name
INCDEC_
PIN
Type
R/W
D5
D4
FSYNC_ CK4_ACTALIGN_PIN
V_PIN
Force 1
R/W
R/W
D3
D2
D1
D0
CK3_ACTV_PIN
CK2_ACTV_PIN
CK1_ACTV_PIN
CKSEL_
PIN
R/W
R/W
R/W
R/W
Reset value = 1111 1111
Bit
7
6
5
Name
INCDEC_PIN
Function
INCDEC_PIN.
Determines how coarse skew adjustments can be made. The adjustments can be
made via hardware using the INC/DEC pins or with software via the CLAT register.
0: INC and DEC inputs ignored; use CLAT register to adjust skew.
1: INC and DEC inputs control output phase increment/decrement.
Reserved
FSYNC_ALIGN_PIN FSYNC_ALIGN_PIN.
Realignment of FSYNCOUT can be controlled by the FSYNC_ALIGN input pin
instead of the FSYNC_ALIGN_REG register bit.
0: FSYNC_ALIGN pin ignored. FSYNC_ALIGN_REG register bit controls
FSYNCOUT realignment.
1: FSYNC_ALIGN pin controls FSYNCOUT realignment.
4
CK4_ACTV_PIN
CK4_ACTV_PIN.
If the CKSEL[1]/CK4_ACTV pin is functioning as the CK4_ACTV output (see
CKSEL[1]/CK4_ACTV pin description on CK4_ACTV), the CK4_ACTV_REG status bit can be reflected to the CK4_ACTV output pin using the CK4_ACTV_PIN
enable function.
0: CK4_ACTV output pin tristated
1: CK4_ACTV status reflected to output pin.
3
CK3_ACTV_PIN
CK3_ACTV_PIN.
If the CKSEL[0]/CK3_ACTV pin is functioning as the CK3_ACTV output (see
CKSEL[0]/CK3_ACTV pin description on CK3_ACTV), the CK3_ACTV_REG status bit can be reflected to the CK3_ACTV output pin using the CK3_ACTV_PIN
enable function.
0: CK3_ACTV output pin tristated.
1: CK3_ACTV status reflected to output pin.
2
CK2_ACTV_PIN
CK2_ACTV_PIN.
The CK2_ACTV_REG status bit can be reflected to the CK2_ACTV output pin
using the
CK2_ACTV_PIN enable function.
0: CK2_ACTV output pin tristated.
1: CK2_ACTV status reflected to output pin.
Rev. 1.0
43
Si5368
Bit
Name
Function
1
CK1_ACTV_PIN
0
CKSEL_PIN
CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CK1_ACTV output pin
using the CK1_ACTV_PIN enable function.
0: CK1_ACTV output pin tristated.
1: CK1_ACTV status reflected to output pin.
CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CKSEL[1:0] input pins.
0: CKSEL pins ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CKSEL[1:0] input pins controls clock selection.
Note: The CKx_ACTV_PIN bits in this register are of consequence only when CKSEL_PIN is 0.
Register 22.
Bit
D7
D6
Name
FSYNC_
ALIGN_
POL
FSYNC_
POL
Type
R/W
R/W
D5
R
D4
D3
D2
D1
D0
FSYNCOUT_POL
CK_ACTV_POL
CK_BAD_
POL
LOL_POL
INT_POL
R/W
R/W
R/W
R/W
R/W
Reset value = 1101 1111
44
Bit
Name
7
FSYNC_ALIGN_POL
6
FSYNC_POL
5
Reserved
4
FSYNCOUT_POL
Function
FSYNC_ALIGN_POL.
Sets the active polarity or edge for the FSYNC_ALIGN input pin.
0: Active low (falling edge).
1: Active high (rising edge).
FSYNC_POL.
Sets the active polarity and edge for the CKIN_3 and CKIN_4 inputs when used
as frame
sync inputs.
0: Active low (falling edge).
1: Active high (rising edge).
FSYNCOUT_POL.
Controls active polarity of FSYNCOUT.
0: Active low
1: Active high
Rev. 1.0
Si5368
Bit
Name
Function
3
CK_ACTV_ POL
2
CK_BAD_ POL
1
LOL_POL
LOL_POL.
Sets the active polarity for the LOL status when reflected on an output pin.
0: Active low
1: Active high
0
INT_POL
INT_POL.
Sets the active polarity for the interrupt status when reflected on the INT_ALM
output pin.
0: Active low
1: Active high
CK_ACTV_POL.
Sets the active polarity for the CK1_ACTV, CK2_ACTV, CK3_ACTV, and
CK4_ACTV
signals when reflected on an output pin.
0: Active low
1: Active high
CK_BAD_POL.
Sets the active polarity for the C1B, C2B, C3B, and ALRMOUT signals when
reflected
on output pins.
0: Active low
1: Active high
Register 23.
Bit
D7
D6
D5
Name
Type
R
R
R
D4
D3
D2
D1
D0
LOS4_
MSK
LOS3_
MSK
LOS2_
MSK
LOS1_
MSK
LOSX_
MSK
R/W
R/W
R/W
R/W
R/W
Reset value = 0001 1111
Bit
7:5
4
Name
Reserved
LOS4_MSK
3
LOS3_MSK
Function
LOS4_MSK.
Determines if a LOS on CKIN4 (LOS4_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS4_FLG register.
0: LOS4 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS4_FLG ignored in generating interrupt output.
LOS3_MSK.
Determines if a LOS on CKIN3 (LOS3_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS3_FLG register.
0: LOS3 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS3_FLG ignored in generating interrupt output.
Rev. 1.0
45
Si5368
2
LOS2_MSK
1
LOS1_MSK
0
LOSX_MSK
LOS2_MSK.
Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS2_FLG register.
0: LOS2 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS2_FLG ignored in generating interrupt output.
LOS1_MSK.
Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS1_FLG register.
0: LOS1 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS1_FLG ignored in generating interrupt output.
LOSX_MSK.
Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOSX_FLG register.
0: LOSX alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOSX_FLG ignored in generating interrupt output.
Register 24.
Bit
D7
D6
Name
Type
R
R
D5
D4
D3
D2
D1
D0
ALIGN_
MSK
FOS4_
MSK
FOS3_
MSK
FOS2_
MSK
FOS1_
MSK
LOL_MSK
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0011 1111
46
Bit
Name
7:6
Reserved
Function
5
ALIGN_MSK ALIGN_MSK.
Determines if an alignment alarm (ALIGN_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the ALIGN_FLG register.
0: FSYNC alignment alarm triggers active interrupt on INT output (if INT_PIN=1).
1: ALIGN_FLG ignored in generating interrupt output.
4
FOS4_MSK
FOS4_MSK.
Determines if the FOS4_FLG is used to in the generation of an interrupt. Writes to this
register do not change the value held in the FOS4_FLG register.
0: FOS4 alarm triggers active interrupt on INToutput (if INT_PIN=1).
1: FOS4_FLG ignored in generating interrupt output.
3
FOS3_MSK
FOS3_MSK.
Determines if the FOS3_FLG is used in the generation of an interrupt. Writes to this
register do not change the value held in the FOS3_FLG register.
0: FOS3 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: FOS3_FLG ignored in generating interrupt output.
Rev. 1.0
Si5368
2
FOS2_MSK
FOS2_MSK.
Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this register do not change the value held in the FOS2_FLG register.
0: FOS2 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: FOS2_FLG ignored in generating interrupt output.
1
FOS1_MSK
FOS1_MSK.
Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this register do not change the value held in the FOS1_FLG register.
0: FOS1 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: FOS1_FLG ignored in generating interrupt output.
0
LOL_MSK
LOL_MSK.
Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this register do not change the value held in the LOL_FLG register.
0: LOL alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOL_FLG ignored in generating interrupt output.
Register 25.
Bit
D7
D6
Name
N1_HS [2:0]
Type
R/W
D5
D4
D3
D2
D1
D0
NC1_LS [19:16]
R
R/W
Reset value = 0010 0000
Bit
Name
Function
7:5
N1_HS [2:0]
N1_HS [2:0].
Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 4) low-speed divider.
000: N1 = 4 Note: Changing the coarse skew via the INC pin is disabled for this value.
001: N1 = 5
010: N1 = 6
011: N1 = 7
100: N1 = 8
101: N1 = 9
110: N1 = 10
111: N1 = 11
4
Reserved
3:0
NC1_LS
[19:16]
NC1_LS [19:0].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220].
Rev. 1.0
47
Si5368
Register 26.
Bit
D7
D6
D5
D4
D3
Name
NC1_LS [15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
NC1_LS [15:8]
Function
NC1_LS [15:8].
See Register 25.
Register 27.
Bit
D7
D6
D5
D4
D3
Name
NC1_LS [7:0]
Type
R/W
Reset value = 0011 0001
Bit
7:0
48
Name
Function
NC1_LS [7:0] NC1_LS [7:0].
See Register 25.
Rev. 1.0
Si5368
Register 28.
Bit
D7
D6
D5
D4
D3
D1
D0
NC2_LS [19:16]
Name
Type
D2
R
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:4
Reserved
3:0
NC1_LS [19:0]
Function
NC2_LS [19:16].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or
odd.
00000000000000000000=1
00000000000000000001=2
00000000000000000011=4
00000000000000000101=6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220]
Rev. 1.0
49
Si5368
Register 29.
Bit
D7
D6
D5
D4
D3
Name
NC2_LS [15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
NC2_LS [15:8]
Function
NC2_LS [15:8].
See Register 28.
Register 30.
Bit
D7
D6
D5
D4
D3
Name
NC2_LS [7:0]
Type
R/W
Reset value = 0011 0001
50
Bit
Name
7:0
NC2_LS [7:0]
Function
NC2_LS [7:0].
See Register 28.
Rev. 1.0
Si5368
Register 31.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
NC3_LS [19:16]
Name
R
Type
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:4
Reserved
3:0
NC3_LS [19:0]
Function
NC3_LS [19:0.
Sets value for NC3 low-speed divider, which drives CKOUT3 output. Must be 0 or odd.
00000000000000000000=1
00000000000000000001=2
000000000000000000011=4
000000000000000000101=6
...
11111111111111111111=220
Valid divider values=[1, 2, 4, 6, ..., 220].
Register 32.
Bit
D7
D6
D5
D4
D3
Name
NC3_LS [15:8]
Type
R/W
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
NC3_LS [15:8]
Function
NC3_LS [15:8].
See Register 31.
Rev. 1.0
51
Si5368
Register 33.
Bit
D7
D6
D5
D4
D3
Name
NC3_LS [7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0011 0001
Bit
7:0
Name
Function
NC3_LS [7:0] NC3_LS [7:0].
See Register 31.
Register 34.
Bit
D7
D6
D5
D4
D3
NC4_LS [19:16]
Name
Type
R
R
R
R
R/W
Reset value = 0000 0000
52
Bit
Name
7:4
Reserved
3:0
NC4_LS [19:0]
Function
NC4_LS [19:0].
Sets value for NC4 low-speed divider, which drives CKOUT4 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220].
Rev. 1.0
Si5368
Register 35.
Bit
D7
D6
D5
D4
D3
Name
NC4_LS [15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
NC4_LS [15:8]
Function
NC4_LS [15:8].
See Register 34.
Register 36.
Bit
D7
D6
D5
D4
D3
Name
NC4_LS [7:0]
Type
R/W
Reset value = 0011 0001
Bit
Name
7:0
NC4_LS [7:0]
Function
NC4_LS [7:0].
See Register 34.
Rev. 1.0
53
Si5368
Register 37.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
NC5_LS [19:16]
Name
R
Type
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:4
Reserved
3:0
NC5_LS [19:0]
Function
NC5_LS [19:0].
Sets value for NC5 low-speed divider, which drives CKOUT5 output. Must be 0 or
odd.
When CK_CONFIG = 0:
00000000000000000000 = 1
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values=[1, 2, 4, 6, ..., 220].
When CK_CONFIG=1, maximum value limited to 219.:
00000000000000000000 = 1
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
01111111111111111111 = 219
Valid divider values = [1, 2, 4, 6, ..., 219].
Register 38.
Bit
D7
D6
D5
D4
D3
Name
NC5_LS [15:8]
Type
R/W
Reset value = 0000 0000
54
Bit
Name
7:0
NC5_LS [15:8]
Function
NC5_LS [15:8].
See Register 37.
Rev. 1.0
D2
D1
D0
Si5368
Register 39.
Bit
D7
D6
D5
D4
D3
Name
NC5_LS [7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0011 0001
Bit
7:0
Name
Function
NC5_LS [7:0] NC5_LS [7:0].
See Register 37.
Register 40.
Bit
D7
D6
Name
N2_HS [2:0]
Type
R/W
D5
D4
D3
N2_LS [19:16]
R
R/W
Reset value = 1100 0000
Bit
Name
Function
7:5
N2_HS [2:0]
N2_HS [2:0].
Sets value for N2 high speed divider which drives NCn_LS (n = 1 to 4) low-speed divider.
000:4
001:5
010:6
011:7
100:8
101:9
110:10
111:11.
4
Reserved
3:0
N2_LS [19:16] NC2_LS [19:0].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [2, 4, 6, ..., 220].
Rev. 1.0
55
Si5368
Register 41.
Bit
D7
D6
D5
D4
D3
Name
N2_LS [15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
7:0
Name
Function
N2_LS [15:8] N2_LS [15:8].
See Register 40.
Register 42.
Bit
D7
D6
D5
D4
D3
Name
N2_LS [7:0]
Type
R/W
Reset value = 1111 1001
56
Bit
Name
7:0
N2_LS [7:0]
Function
N2_LS [7:0].
See Register 40.
Rev. 1.0
Si5368
Register 43.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
N31 [18:16]
Name
R
Type
R
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:3
Reserved
2:0
N31 [18:0]
Function
N31 [18:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values = [1, 2, 3, ..., 219].
Register 44.
Bit
D7
D6
D5
D4
D3
Name
N31 [15:8]
Type
R/W
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
N31 [15:8]
Function
N31 [15:8].
See Register 43.
Rev. 1.0
57
Si5368
Register 45.
Bit
D7
D6
D5
D4
D3
Name
N31 [7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 1001
Bit
Name
7:0
N31 [7:0]
Function
N31 [7:0].
See Register 43.
Register 46.
Bit
D7
D6
D5
D4
D3
N32_[18:16]
Name
Type
R
R
R
R
R
Reset value = 0000 0000
58
Bit
Name
7:3
Reserved
2:0
N32_[18:0]
Function
N32_[18:0].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219].
Rev. 1.0
R/W
Si5368
Register 47.
Bit
D7
D6
D5
D4
D3
Name
N32_[15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
N32_[15:8]
Function
N32_[15:8].
See Register 46.
Register 48.
Bit
D7
D6
D5
D4
D3
Name
N32_[7:0]
Type
R/W
Reset value = 0000 1001
Bit
Name
7:0
N32_[7:0]
Function
N32_[7:0].
See Register 46.
Rev. 1.0
59
Si5368
Register 49.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
N33_[18:0]
Name
R
Type
R
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
18:0
N33_[18:0]
Function
N33_[18:0].
Sets value for input divider for CKIN3.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values = [1, 2, 3, ..., 219].
Register 50.
Bit
D7
D6
D5
D4
D3
Name
N33_[15:8]
Type
R/W
Reset value = 0000 0000
60
Bit
Name
7:0
N33_[15:8]
Function
N33_[15:8].
See Register 49.
Rev. 1.0
D2
D1
D0
Si5368
Register 51.
Bit
D7
D6
D5
D4
D3
Name
N33_[7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 1001
Bit
Name
7:0
N33_[7:0]
Function
N33_[7:0].
See Register 49.
Register 52.
Bit
D7
D6
D5
D4
D3
N34_[18:16]
Name
Type
R
R
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:0
N34_[18:0]
Function
N34_[18:0].
Sets value for input divider for CKIN4.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values = [1, 2, 3, ..., 219].
Rev. 1.0
61
Si5368
Register 53.
Bit
D7
D6
D5
D4
D3
Name
N34_[15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
N34_[15:8]
Function
N34_[15:8].
See Register 52.
Register 54.
Bit
D7
D6
D5
D4
D3
Name
N34_[7:0]
Type
R/W
Reset value = 0000 1001
62
Bit
Name
7:0
N34_[15:8]
Function
N34_[7:0].
See Register 52.
Rev. 1.0
Si5368
Register 55.
Bit
D7
D6
Name
Type
R
R
D5
D4
D3
D2
D1
CLKIN2RATE_[2:0]
CLKIN1RATE[2:0]
R/W
R/W
D0
Reset value = 0000 0000
Bit
Name
Function
7:6
Reserved
5:3
CLKIN2RATE[2:0]
CLKIN2RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
2:0
CLKIN1RATE [2:0]
CLKIN1RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
Rev. 1.0
63
Si5368
Register 56.
Bit
D7
D6
Name
Type
R
R
D5
D4
D3
D2
CLKIN4RATE_[2:0]
CLKIN3RATE[2:0]
R/W
R/W
Reset value = 0000 0000
64
D1
Bit
Name
Function
7:6
Reserved
5:3
CLKIN4RATE[2:0]
CLKIN4RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
2:0
CLKIN3RATE [2:0]
CLKIN3RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
Rev. 1.0
D0
Si5368
Register 128.
Bit
D7
D6
D5
D4
Name
Type
R
R
R
R
D3
D2
D1
D0
CK4_ACTV_REG
CK3_ACTV_REG
CK2_ACTV_REG
CK1_ACTV_REG
R
R
R
R
Reset value = 0010 0000
Bit
Name
Function
7:4
Reserved
3
CK4_ACTV_REG
CK4_ACTV_REG.
Indicates if CKIN4 is currently the active clock for the PLL input.
0: CKIN4 is not the active input clock. Either it is not selected or LOS4_INT is 1.
1: CKIN_4 is the active input clock.
2
CK3_ACTV_REG
CK3_ACTV_REG.
Indicates if CKIN3 is currently the active clock for the PLL input.
0: CKIN3 is not the active input clock - either it is not selected or LOS3_INT is 1.
1: CKIN3 is the active input clock.
1
CK2_ACTV_REG
CK2_ACTV_REG.
Indicates if CKIN2 is currently the active clock for the PLL input.
0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
1: CKIN2 is the active input clock.
0
CK1_ACTV_REG
CK1_ACTV_REG.
Indicates if CKIN1 is currently the active clock for the PLL input.
0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.
1: CKIN1 is the active input clock.
Rev. 1.0
65
Si5368
Register 129.
Bit
D7
D6
D5
Name
Type
R
R
R
D4
D3
D2
D1
D0
LOS4_INT
LOS3_INT
LOS2_INT
LOS1_INT
LOSX_INT
R
R
R
R
R
Reset value = 0001 1110
66
Bit
Name
Function
7:5
Reserved
4
LOS4_INT
LOS4_INT.
Indicates the LOS status on CKIN4.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN4 input.
3
LOS3_INT
LOS3_INT.
Indicates the LOS status on CKIN3.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN3 input.
2
LOS2_INT
LOS2_INT.
Indicates the LOS status on CKIN2.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN2 input.
1
LOS1_INT
LOS1_INT.
Indicates the LOS status on CKIN1.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN1 input.
0
LOSX_INT
LOSX_INT.
Indicates the LOS status of the external reference on the XA/XB pins.
0: Normal operation.
1: Internal loss-of-signal alarm on XA/XB reference clock input.
Rev. 1.0
Si5368
Register 130.
Bit
D7
D6
D5
Name CLATPROG- DIGHOLDRESS
VALID
Type
R
R
ALIGN_
INT
R
D4
D3
D2
FOS4_INT FOS3_INT FOS2_INT
R
R
R
D1
D0
FOS1_INT
LOL_INT
R
R
Reset value = 0000 0001
Bit
Name
Function
7
CLATPROGRESS
6
DIGHOLDVALID
5
ALIGN_INT
ALIGN_INT.
Alignment Alarm Status.
0: Normal operation.
1: Alignment alarm between input and output frame sync signals.
4
FOS4_INT
FOS4_INT.
CKIN4 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN4 input.
3
FOS3_INT
FOS3_INT.
CKIN3 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN3 input.
2
FOS2_INT
FOS2_INT.
CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
1
FOS1_INT
FOS1_INT.
CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
0
LOL_INT
CLAT Progress.
Indicates if the last change in the CLAT register has been processed.
0: Coarse skew adjustment not in progress.
1: Coarse skew adjustment in progress.
Digital Hold Valid.
Indicates if the digital hold circuit has enough samples of a valid clock to meet digital hold specifications.
0: Indicates digital filter has not been filled. The digital hold output frequency (from
the filter) is not valid.
1: Indicates digital hold filter has been filled. The digital hold output frequency is
valid.
LOL_INT.
PLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.
Rev. 1.0
67
Si5368
Register 131.
Bit
D7
D6
D5
Name
Type
R
R
R
D4
D3
D2
D1
D0
LOS4_
FLG
LOS3_
FLG
LOS2_
FLG
LOS1_
FLG
LOSX_
FLG
R/W
R/W
R/W
R/W
R/W
Reset value = 0001 1111
68
Bit
Name
Function
7:5
Reserved
4
LOS4_FLG
LOS4_FLG.
CKIN4 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS4_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS4_MSK bit. Flag cleared by writing
location to 0.
3
LOS3_FLG
LOS3_FLG.
CKIN3 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS3_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS3_MSK bit. Flag cleared by writing
location to 0.
2
LOS2_FLG
LOS2_FLG.
CKIN2 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS2_MSK bit. Flag cleared by writing
location to 0.
1
LOS1_FLG
LOS1_FLG.
CKIN1 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS1_MSK bit. Flag cleared by writing
location to 0.
0
LOSX_FLG
LOSX_FLG.
External reference (signal on pins XA/XB) Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOSX_MSK bit. Flag cleared by writing
location to 0.
Rev. 1.0
Si5368
Register 132.
Bit
D7
D5
ALIGN_
FLG
Name
Type
D6
R
R/W
D4
D3
D2
FOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLG
R/W
R/W
R/W
R/W
D1
D0
LOL_FLG
ALIGN_
ERR [8,8]
R/W
R
Reset value = 0000 0010
Bit
Name
Function
7
Reserved
6
ALIGN_FLG
ALIGN_FLG.
Alignment Alarm Flag.
0: Normal operation.
1: Held version of ALIGN_INT. Generates active output interrupt if output interrupt
pin is enabled (INT_PIN=1) and if not masked by ALIGN_MSK bit. Flag cleared by
writing
location to 0.
5
FOS4_FLG
FOS4_FLG.
CLKIN_4 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS4_INT. Generates active output interrupt if output interrupt pin
is enabled (INT_PIN=1) and if not masked by FOS4_MSK bit. Flag cleared by writing
location to 0.
4
FOS3_FLG
FOS3_FLG.
CLKIN_3 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS3_INT. Generates active output interrupt if output interrupt pin
is enabled (INT_PIN=1) and if not masked by FOS3_MSK bit. Flag cleared by writing
location to 0.
3
FOS2_FLG
FOS2_FLG.
CLKIN_2 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin
is enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing
location to 0.
Rev. 1.0
69
Si5368
Bit
Name
Function
2
FOS1_FLG
FOS1_FLG.
CLKIN_1 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin
is enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing
location to 0.
1
LOL_FLG
LOL_FLG.
PLL Loss of Lock Flag.
0: PLL locked
1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin
is enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing
location to 0.
0
ALIGN_ERR [8,8]
ALIGN_ERR [8:0].
Indicates the magnitude of the deviation of the input to output frame sync phase
alignment from the ideal value set in the FSYNC_SKEW[16:0] registers. The alignment error is given in units of tCKOUT_2.
If the alignment error exceeds 255 fCKOUT_2 clock cycles, ALIGN_ERR[7:0] limits
to its maximum value (11111111). The polarity of the phase deviation (leading or lagging) is given by the ALIGN_ERR[8] bit.
00000000=0
11111111=255
Register 133.
Bit
D7
D6
D5
D4
D3
Name
ALIGN_ERR [7:0]
Type
R
Reset value = 0000 0000
Bit
7:0
70
Name
Function
ALIGN_ERR [7:0] ALIGN_ERR [7:0].
See Register 132.
Rev. 1.0
D2
D1
D0
Si5368
Register 134.
Bit
D7
D6
D5
D4
D3
Name
PARTNUM_RO [11:4]
Type
R
D2
D1
D0
D2
D1
D0
Reset value = 0000 0100
Bit
Name
Function
7:0
PARTNUM_RO [11:4]
PARTNUM_RO [11:4].
Device ID:
0000 0100 0100'b=Si5368
Register 135.
Bit
D7
D6
D5
D4
D3
Name
PARTNUM_RO [3:0]
REVID_RO [3:0]
Type
R
R
Reset value = 0100 0010
Bit
7:4
3:0
Name
Function
PARTNUM_RO [3:0] PARTNUM_RO [3:0].
See Register 134.
REVID_RO [3:0]
REVID_RO [3:0].
Indicates revision number of device.
0000: Revision A
0001: Revision B
0010: Revision C
Other codes: Reserved
Rev. 1.0
71
Si5368
Register 136.
Bit
D7
D6
Name
RST_REG
ICAL
Type
R/W
R/W
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
Reset value = 0000 0000
Bit
Name
7
RST_REG
6
ICAL
Function
RST_REG.
Internal Reset.
0: Normal operation.
1: Reset of all internal logic. Outputs tristated or disabled during reset.
ICAL.
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is
complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be
present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take effect.
Changes in SFOUTn_REG, PD_CKn, or DSBLn_REG will cause a random change in skew
until an ICAL is completed.
0: Normal operation.
1: Writing a “1” initiates internal self-calibration. Upon completion of internal selfcalibration, ICAL is internally reset to zero.
5:0
72
Reserved
Rev. 1.0
Si5368
Register 138.
Bit
D7
D6
D5
D4
Name
Type
R
R
R
R
D3
D2
D1
D0
LOS4_EN
[1:1]
LOS3_EN
[1:1]
LOS2_EN
[1:1]
LOS1_EN
[1:1]
R/W
R/W
R/W
R/W
Reset value = 0000 1111
Bit
Name
7:4
Reserved
3
LOS4_EN [1:0]
Function
LOS4_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference
Manual for details.
2
LOS3_EN [1:0]
LOS3_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference
Manual for details.
1
LOS2_EN [1:0]
LOS2_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference
Manual for details.
0
LOS1_EN [1:0]
LOS1_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference
Manual for details.
Rev. 1.0
73
Si5368
Register 139.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
LOS4_EN
[0:0]
LOS3_EN
[0:0]
LOS2_EN
[0:0]
LOS1_EN
[0:0]
FOS4_EN
FOS3_EN
FOS2_EN
FOS1_EN
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 1111 1111
Bit
Name
7
LOS4_EN [0:0]
Function
LOS4_EN [0:0].
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual for details.
6
LOS3_EN [0:0]
LOS3_EN [0:0].
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual for details.
5
LOS2_EN [0:0]
LOS2_EN.
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual for details.
4
LOS1_EN [0:0]
LOS1_EN [0:0].
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual for details.
74
Rev. 1.0
Si5368
Bit
Name
Function
3
FOS4_EN
FOS4_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
2
FOS3_EN
FOS3_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
1
FOS2_EN
FOS2_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
0
FOS1_EN
FOS1_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
Register 140.
Bit
D7
D6
D5
D4
D3
D2
Name
INDEPENDENTSKEW1 [7:0]
Type
R/W
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
INDEPEND-ENTSKEW1 [7:0]
Function
INDEPENDENTSKEW1 [7:0].
8 bit field that represents a twos complement of the phase offset in
terms of clocks from the high speed output divider.
Rev. 1.0
75
Si5368
Register 141.
Bit
D7
D6
D5
D4
D3
D2
Name
INDEPENDENTSKEW2 [7:0]
Type
R/W
D1
D0
Reset value = 0000 0001
Bit
Name
7:0
INDEPEND-ENTSKEW2 [7:0]
Function
INDEPENDENTSKEW2 [7:0].
8 bit field that represents a twos complement of the phase offset in
terms of clocks from the high speed output divider.
Register 142.
Bit
D7
D6
D5
D4
D3
D2
Name
INDEPENDENTSKEW3 [7:0]
Type
R/W
D1
D0
Reset value = 0000 0000
Bit
7:0
Name
Function
INDEPEND-ENTSKEW3 [7:0] INDEPENDENTSKEW3 [7:0].
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider.
Register 143.
Bit
D7
D6
D5
D4
D3
D2
Name
INDEPENDENTSKEW4 [7:0]
Type
R/W
D1
D0
Reset value = 0000 0000
Bit
7:0
76
Name
Function
INDEPEND-ENTSKEW4 [7:0] INDEPENDENTSKEW4 [7:0].
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider.
Rev. 1.0
Si5368
Register 144.
Bit
D7
D6
D5
D4
D3
D2
Name
INDEPENDENTSKEW5 [7:0]
Type
R/W
D1
D0
Reset value = 0000 0000
Bit
Name
Function
7:0
INDEPEND-ENTSKEW5 [7:0]
INDEPENDENTSKEW5 [7:0].
8 bit field that represents a twos complement of the phase offset in
terms of clocks from the high speed output divider when
CK_CONFIG = 0.
Table 9. CKOUT_ALWAYS_ON and SQICAL Truth Table
CKOUT_ALWAYS_ON
SQICAL
Results
Output to Output Skew
Preserved?
0
0
CKOUT OFF until after the first ICAL
N
0
1
CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
Y
1
0
CKOUT always ON, including during an ICAL
N
1
1
CKOUT always ON, including during an ICAL
Y
Table 10 lists all of the register locations that should be followed by an ICAL after their contents are changed.
Rev. 1.0
77
Si5368
Table 10. Register Locations Requiring ICAL
Address
78
Register
0
BYPASS_REG
0
CKOUT_ALWAYS_ON
1
CK_PRIOR4
1
CK_PRIOR3
1
CK_PRIOR2
1
CK_PRIOR1
2
BWSEL_REG
4
HIST_DEL
5
ICMOS
7
FOSREFSEL
9
HIST_AVG
10
DSBL5_REG
10
DSBL4_REG
10
DSBL3_REG
10
DSBL2_REG
10
DSBL1_REG
11
PD_CK2
11
PD_CK1
19
FOS_EN
19
FOS_THR
19
VALTIME
19
LOCKT
21
INCDEC_PIN
25
N1_HS
26
NC1_LS
28
NC2_LS
31
NC3_LS
34
NC4_LS
37
NC5_LS
40
N2_HS
40
N2_LS
43
N31
46
N32
49
N33
51
N34
55
CLKIN2RATE
55
CLKIN1RATE
56
CLKIN4RATE
56
CLKIN3RATE
Rev. 1.0
Si5368
VDD
CKOUT3+
CKOUT3–
VDD
NC
VDD
CKOUT1–
CKOUT1+
VDD
NC
FS_OUT–
VDD
FS_OUT+
VDD
CMODE
VDD
CKOUT2+
CKOUT2–
NC
VDD
VDD
CKOUT4–
VDD
CKOUT4+
VDD
7. Pin Descriptions: Si5368
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
NC
NC
2
74
NC
RST
3
73
NC
NC
4
72
NC
VDD
5
71
SDI
VDD
6
70
A2_SS
GND
GND
7
69
A1
8
68
A0
C1B
9
67
NC
C2B
10
66
NC
C3B
11
65
INT_ALM
12
64
GND
GND
CS0_C3A
13
63
VDD
GND
14
62
VDD
VDD
15
61
SDA_SDO
XA
60
SCL
XB
16
17
59
C2A
GND
18
58
C1A
GND
19
57
CS1_C4A
NC
20
56
NC
FS_ALIGN
21
55
INC
NC
22
DEC
NC
23
54
53
NC
24
25
GND PAD
NC
Rev. 1.0
NC
LOL
NC
NC
CKIN1–
GND
CKIN1+
GND
GND
RATE1
CKIN3–
CKIN3+
GND
NC
GND
CKIN2–
GND
CKIN2+
RATE0
GND
CKIN4–
CKIN4+
NC
GND
NC
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDD
52
GND
NC
Si5368
79
Si5368
Table 11. Si5368 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1, 2, 4, 20,
22, 23, 24,
25, 37, 47,
48, 50, 51,
52, 53, 56,
66, 67, 72,
73, 74, 75,
80, 85, 95
NC
3
RST
I
LVCMOS
5, 6, 15, 27,
62, 63, 76,
79, 81, 84,
86, 89, 91,
94, 96, 99,
100
VDD
Vdd
Supply
VDD.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following VDD pins:
Pins
Bypass Cap
5, 6
0.1 µF
15
0.1 µF
27
0.1 µF
62, 63
0.1 µF
76, 79
1.0 µF
81, 84
0.1 µF
86, 89
0.1 µF
91, 94
0.1 µF
96, 99, 100
0.1 µF
7, 8, 14, 18,
19, 26, 28,
31, 33, 36,
38, 41, 43,
46, 64, 65
GND
GND
Supply
Ground.
This pin must be connected to system ground. Minimize the
ground path impedance for optimal performance.
9
C1B
O
LVCMOS
CKIN1 Invalid Indicator.
This pin performs the CK1_BAD function if CK1_BAD_PIN = 1
and is tristated if CK1_BAD_PIN = 0. Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
C2B
O
LVCMOS
CKIN2 Invalid Indicator.
This pin performs the CK2_BAD function if CK2_BAD_PIN = 1
and is tristated if CK2_BAD_PIN = 0. Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
No Connect.
These pins must be left unconnected for normal operation.
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are disabled during reset. The part must be programmed after a reset
or power-on to get a clock output. See Family Reference Manual for details.
This pin has a weak pull-up.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
80
Rev. 1.0
Si5368
Table 11. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
11
C3B
O
LVCMOS
CKIN3 Invalid Indicator.
This pin performs the CK3_BAD function if CK3_BAD_PIN = 1
and is tristated if CK3_BAD_PIN = 0. Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
12
INT_ALM
O
LVCMOS
Interrupt/Alarm Output Indicator.
This pin functions as a maskable interrupt output with active
polarity controlled by the INT_POL register bit. The INT output
function can be turned off by setting INT_PIN = 0. If the ALRMOUT function is desired instead on this pin, set
ALRMOUT_PIN = 1 and INT_PIN = 0.
0 = ALRMOUT not active.
1 = ALRMOUT active.
The active polarity is controlled by CK_BAD_POL. If no function
is selected, the pin tristates.
13
57
CS0_C3A
CS1_C4A
I/O
LVCMOS
Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator.
Input: If manual clock selection is chosen, and if
CKSEL_PIN = 1, the CKSEL pins control clock selection and
the CKSEL_REG bits are ignored.
CS[1:0]
Active Input Clock
00
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
If CKSEL_PIN = 0, the CKSEL_REG register bits control this
function and these inputs tristate. If configured as inputs, these
pins must not float.
Output: If auto clock selection is enabled, then they serve as
the CKIN_n active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input to the PLL
The CKn_ACTV_REG bit always reflects the active clock status
for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be
reflected on the CnA pin with active polarity controlled by the
CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates.
16
17
XA
XB
I
ANALOG
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal oscillator based reference. Refer to Family Reference Manual for interfacing to an external reference. External reference
must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pins.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Rev. 1.0
81
Si5368
Table 11. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
21
FS_ALIGN
I
LVCMOS
FSYNC Alignment Control.
If FSYNC_ALIGN_PIN = 1 and CK_CONFIG = 1, a logic high
on this pin causes the FS_OUT phase to be realigned to the rising edge of the currently active input sync (CKIN_3 or CKIN_4).
If FSYNC_ALIGN_PIN = 0, this pin is ignored and the FSYNC_ALIGN_REG bit performs this function.
0 = No realignment.
1 = Realign.
This pin has a weak pull-down.
29
30
CKIN4+
CKIN4–
I
MULTI
Clock Input 4.
Differential clock input. This input can also be driven with a single-ended signal. CKIN4 serves as the frame sync input associated with the CKIN2 clock when CK_CONFIG_REG = 1.
32
42
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or reference clock to be applied to the XA/XB port. Refer to
the Family Reference Manual for settings. These pins have both
a weak pull-up and a weak pull-down; they default to M.
34
35
CKIN2+
CKIN2–
I
MULTI
Clock Input 2.
Differential input clock. This input can also be driven with a single-ended signal.
39
40
CKIN3+
CKIN3–
I
MULTI
Clock Input 3.
Differential clock input. This input can also be driven with a single-ended signal. CKIN3 serves as the frame sync input associated with the CKIN1 clock when CK_CONFIG_REG = 1.
44
45
CKIN1+
CKIN1–
I
MULTI
Clock Input 1.
Differential clock input. This input can also be driven with a single-ended signal.
49
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if
the LOL_PIN register bit is set to one.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate.
Active polarity is controlled by the LOL_POL bit. The PLL lock
status will always be reflected in the LOL_INT read only register
bit.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
82
Rev. 1.0
Si5368
Table 11. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
54
DEC
I
LVCMOS
Coarse Latency Decrement.
A pulse on this pin decreases the input to output device latency
by 1/fOSC (approximately 200 ps). Detailed operations and timing characteristics for this pin may be found in the Any-Frequency Precision Clock Family Reference Manual. There is no
limit on the range of latency adjustment by this method. Pin control is enabled by setting INCDEC_PIN = 1 (default).
If INCDEC_PIN = 0, this pin is ignored and coarse output
latency is controlled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled
and the device maintains a fixed-phase relationship between
the selected input clock and the output clock during an input
clock switch. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
55
INC
I
LVCMOS
Coarse Latency Increment.
A pulse on this pin increases the input to output device latency
by 1/fOSC (approximately 200 ps). Detailed operations, restrictions, and timing characteristics for this pin may be found in the
Any-Frequency Precision Clock Family Reference Manual.
There is no limit on the range of latency adjustment by this
method. Pin control is enabled by setting INCDEC_PIN = 1
(default).
Note: INC does not increase latency if NI_HS = 4.
If INCDEC_PIN = 0, this pin is ignored and coarse output
latency is controlled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled
and the device maintains a fixed-phase relationship between
the selected input clock and the output clock during an input
clock switch. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
58
C1A
O
LVCMOS
CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator. The
CK1_ACTV_REG bit always reflects the active clock status for
CKIN1. If CK1_ACTV_PIN = 1, this status will also be reflected
on the C1A pin with active polarity controlled by the CK_ACTV_POL bit. If CK1_ACTV_PIN = 0, this output tristates.
59
C2A
O
LVCMOS
CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator. The
CK2_ACTV_REG bit always reflects the active clock status for
CKIN_2. If CK2_ACTV_PIN = 1, this status will also be reflected
on the C2A pin with active polarity controlled by the CK_ACTV_POL bit. If CK2_ACTV_PIN = 0, this output tristates.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Rev. 1.0
83
Si5368
Table 11. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
60
SCL
I
LVCMOS
Serial Clock.
This pin functions as the serial port clock input for both SPI and
I2C modes.
This pin has a weak pull-down.
61
SDA_SDO
I/O
LVCMOS
Serial Data.
In I2C microprocessor control mode (CMODE = 0), this pin functions as the bidirectional serial data port. In SPI microprocessor
control mode (CMODE = 1), this pin functions as the serial data
output.
68
69
A0
A1
I
LVCMOS
Serial Port Address.
In I2C microprocessor control mode (CMODE = 0), these pins
function as hardware controlled address bits. The I2C address
is 1101 [A2] [A1] [A0]. In SPI microprocessor control mode
(CMODE = 1), these pins are ignored.
This pin has a weak pull-down.
70
A2_SS
I
LVCMOS
Serial Port Address/Slave Select.
In I2C microprocessor control mode (CMODE = 0), this pin functions as a hardware controlled address bit [A2].
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the slave select input.
This pin has a weak pull-down.
71
SDI
I
LVCMOS
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the serial data input.
In I2C microprocessor control mode (CMODE = 0), this pin is
ignored.
This pin has a weak pull-down.
77
78
CKOUT3+
CKOUT3–
O
MULTI
Clock Output 3.
Differential clock output. Output signal format is selected by
SFOUT3_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
82
83
CKOUT1–
CKOUT1+
O
MULTI
Clock Output 1.
Differential clock output. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
87
88
FS_OUT–
FS_OUT+
O
MULTI
Frame Sync Output.
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision Clock
Family Reference Manual.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
84
Rev. 1.0
Si5368
Table 11. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
90
CMODE
I
LVCMOS
92
93
CKOUT2+
CKOUT2–
O
MULTI
Clock Output 2.
Differential clock output. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
97
98
CKOUT4–
CKOUT4+
O
MULTI
Clock Output 4.
Differential clock output. Output signal format is selected by
SFOUT4_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
GND PAD
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Control Mode.
Selects I2C or SPI control mode for the device.
0 = I2C Control Mode.
1 = SPI Control Mode.
This pin must be tied high or low.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Rev. 1.0
85
Si5368
8. Ordering Guide
Ordering Part
Number
Output Clock
Frequency Range
Package
ROHS6,
Pb-Free
Temperature Range
Si5368A-C-GQ
2 kHz–945 MHz
970–1134 MHz
1.213–1.417 GHz
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Si5368B-C-GQ
2 kHz–808 MHz
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Si5368C-C-GQ
2 kHz–346 MHz
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Note: Add an R at the end of the device to denote tape and reel options (for example, Si5368-C-GMR).
86
Rev. 1.0
Si5368
9. Package Outline: 100-Pin TQFP
Figure 6 illustrates the package details for the Si5368. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 6. 100-Pin Thin Quad Flat Package (TQFP)
Table 12. 100-Pin Package Diagram Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
—
—
1.20
E
16.00 BSC.
A1
0.05
—
0.15
E1
14.00 BSC.
A2
0.95
1.00
1.05
E2
3.85
4.00
4.15
b
0.17
0.22
0.27
L
0.45
0.60
0.75
c
0.09
—
0.20
aaa
—
—
0.20
D
16.00 BSC.
bbb
—
—
0.20
D1
14.00 BSC.
ccc
—
—
0.08
ddd
—
—
0.08

0º
3.5º
7º
D2
e
3.85
4.00
4.15
0.50 BSC.
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant AED-HD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Rev. 1.0
87
Si5368
10. Recommended PCB Layout
Figure 7. PCB Land Pattern Diagram
88
Rev. 1.0
Si5368
Table 13. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
E
15.40 REF.
D
15.40 REF.
E2
3.90
4.10
D2
3.90
4.10
GE
13.90
—
GD
13.90
—
X
—
0.30
Y
1.50 REF.
ZE
—
16.90
ZD
—
16.90
R1
R2
0.15 REF
—
1.00
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask
and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.0
89
Si5368
11. Top Marking: 100-Pin TQFP
11.1. Si5368 Top Marking

11.2. Top Marking Explanation
Mark Method:
Laser
Logo Size:
9.2 x 3.1 mm
Center-Justified
Font Size:
3.0 Point (1.07 mm)
Right-Justified
Line 1 Marking:
Device Part Number
X = Speed Grade
See "7. Pin Descriptions: Si5368" on
page 79.
Line 2 Marking:
YY = Year
WW = Workweek
R=Die Revision
Assigned by the Assembly Supplier.
Corresponds to the year and workweek of the mold date.
TTTTT = Mfg Code
Manufacturing Code
Circle = 1.8 mm Diameter
Center-Justified
“e3” Pb-Free Symbol
Line 3 Marking:
Country of Origin
ISO Code Abbreviation
90
Rev. 1.0
Si5368
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed LVTTL to LVCMOS in Table 9, “Absolute
Maximum Ratings,” on page 18.
 Updated Figure 4 and Figure 5 on page 19.
 Updated “5. Register Map”.

Added
RATE0 to pin description. By changing
RATE[1:0] the part can emulate a Si5367.
Changed XA/XB pin description to support both
differential and single ended external REFCLK.
Revision 0.2 to Revision 0.3
Added Figure on p..8.
Updated Figure 4, “Si5368 Typical Application
Circuit (I2C Control Mode),” and Figure 5, “Si5368
Typical Application Circuit (SPI Control Mode),” on
page 19 to show INC and DEC.
 Updated “5. Register Map”.


Changed
font of register names to underlined italics.
Updated "7. Pin Descriptions: Si5368" on page 79.
 Added “10. Recommended PCB Layout”.

Revision 0.3 to Revision 0.4

Changed VDD specification for 1.8 V.

Updated Table 8 on page 16.
Updated Table 9 on page 18.
Added table under Figure on page 8.
Updated "4. Functional Description" on page 20.
Clarified "5. Register Map" on page 22 including
correcting pin assignments for RATE0 and RATE1.




Revision 0.4 to Revision 0.41
Added register map.
 Added 3.3 V operation.
 Removed some TBDs from the AC specifications.

Revision 0.41 to Revision 1.0









Expanded spec tables.
Added device top mark drawing.
Changed “any-rate” to “any-frequency” throughout.
Added No Bypass mode with CMOS outputs.
Minor updates to Table 2 on page 4 and Table 6 on
page 14.
Removed “2. Typical Phase Noise Performance”.
Updated "4. Functional Description" on page 20.
Revised "5. Register Map" on page 22.
Revised "11. Top Marking: 100-Pin TQFP" on page
90.
Rev. 1.0
91
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