UPD78081,78082 Data Sheet
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78081, 78082
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78081, 78082 are members of the µ PD78083 subseries of the 78K/0 series microcontrollers.
Besides a high-speed, high-performance CPU, these microcontrollers have on-chip ROM, RAM, I/O ports, 8-bit
resolution A/D converter, timer, serial interface interrupt control, and other peripheral hardware.
The µ PD78P083 devices including a one-time PROM version and an EPROM version, both of which can operate
in the same power supply voltage range as a mask ROM version, and various development tools are available.
The details of the functions are described in the following user’s manuals. Be sure to read it before starting design.
µPD78083 Subseries User’s Manual
: IEU-1407
78K/0 Series User’s Manual – Instructions : IEU-1417
FEATURES
• Internal ROM and RAM
Item
Program Memory
Data Memory
(ROM)
(Internal High-speed RAM)
Part Number
•
•
•
•
Package
µPD78081
8K bytes
256 bytes
42-pin plastidc shrink DIP (600 mil)
µPD78082
16K bytes
384 bytes
44-pin plastic QFP (10 × 10 mm)
Instruction execution time can be changed from high-speed (0.4 µs) to low-speed (12.8 µs)
I/O ports: 33
8-bit resolution A/D converter : 8 channels
Serial interface : 1 channel
3-wire serial I/O / UART mode : 1 channel
• Timer : 3 channels
• Supply voltage : VDD = 1.8 to 5.5 V
APPLICATION FIELDS
Air bags, CRT displays, keyboards, air conditioners, water heaters, boilers, fan heater, dash boards, etc.
The information in this document is subject to change without notice.
Document No. U11415EJ1V0DS00 (1st edition)
(Previous No. IP-3476)
Date Published July 1996 P
Printed in Japan
The mark
shows major revised points.
©
1995
µPD78081, 78082
ORDERING INFORMATION
Part Number
Package
µPD78081CU-XXX
42-pin plastic shrink DIP (600 mil)
µPD78081GB-XXX-3B4
44-pin plastic QFP (10 × 10 mm)
µPD78081GB-XXX-3BS-MTX
44-pin plastic QFP (10 × 10 mm)
µPD78082CU-XXX
42-pin plastic shrink DIP (600 mil)
µPD78082GB-XXX-3B4
44-pin plastic QFP (10 × 10 mm)
µPD78082GB-XXX-3BS-MTX
44-pin plastic QFP (10 × 10 mm)
Caution µPD78081GB, 78082GB have two kinds of package. (Refer to 11. PACKAGE DRAWINGS). Please refer
an NEC’s sales representative for the available package.
Remark
XXX indicates ROM code suffix.
78K/0 SERIES DEVELOPMENT
The following shows the 78K/0 series products development. Subseries names are shown inside frames.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
A timer was added to the µPD78054 and external interface function was enhanced
µ PD78078
µ PD78078Y
100-pin
µPD78070A
µ PD78070AY
ROM-less versions of the µ PD78078
80-pin
µ PD78058F
µPD78058FY
EMI noise reduced product of the µ PD78054
80-pin
µ PD78054
µ PD78054Y
UART and D/A converter were added to the µ PD78014 and I/O was enhanced
64-pin
µPD78018F
µPD78018FY
Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM
capacities are available.
64-pin
µ PD78014
µPD78014Y
An A/D converter and 16-bit timer were added to the µ PD78002
64-pin
µPD780001
64-pin
µ PD78002
42/44-pin
µ PD78083
100-pin
An A/D converter was added to the µ PD78002
µPD78002Y
Basic subseries for control
On-chip UART, capable of operating at a low voltage (1.8 V)
FIP ® drive
78K/0
Series
100-pin
µPD780208
The I/O and FIP C/D of the µ PD78044A were enhanced. Display output total: 53
80-pin
µPD78044A
A 6-bit U/D counter was added to the µPD78024. Display output total: 34
64-pin
µPD78024
Basic subseries for driving FIP. Display output total: 26
LCD drive
100-pin
µPD780308
100-pin
µPD78064B
100-pin
µPD78064
µPD780308Y
The enhanced SIO to the µPD78064 and increased ROM and RAM capacities
µPD78064Y
Subseries for driving LCDs, On-chip UART
EMI noise reduced product of the µPD78064
IEBusTM supported
80-pin
µ PD78098
64-pin
µ PD78P0914
The IEBus controller was added to the µPD78054
LV control
2
On-chip PWM output, LV digital code decoder, and Hsync counter
µPD78081, 78082
The major functional differences among the subseries are shown below.
Function
Subseries Name
For Control
For FIP
drive
LCD drive
For IEBus
LV control
µPD78078
µPD78070A
µPD78058F
µPD78054
µPD78018F
µPD78014
µPD780001
µPD78002
µPD78083
µPD780208
µPD78044A
µPD78024
µPD780308
µPD78064B
µPD78064
µPD78098
µPD78P0914
ROM
Capacity
Timer
8-bit
32 K-60 K
—
4ch
48 K-60 K
16 K-60 K
8 K-60 K
8 K-32 K
8K
8 K-16 K
2ch
32
16
24
48
32
16
32
32
2ch
K-60
K-40
K-32
K-60
K
K-32
K-60
K
K
K
K
K
K
K
16-bit Watch WDT
1ch
1ch
1ch
8-bit
A/D
8-bit
D/A
8ch
2ch
—
—
—
1ch
1ch
8ch
8ch
I/O
3ch (UART: 1ch)
88
61
69
2ch
53
1ch
39
53
33
74
68
54
57
—
1ch
—
1ch
Serial
Interface
1ch (UART: 1ch)
2ch
—
2ch
1ch
1ch
1ch
8ch
—
3ch (UART: 1ch)
2ch (UART: 1ch)
2ch
6ch
1ch
—
1ch
—
1ch
1ch
8ch
8ch
2ch
—
3ch (UART: 1ch)
2ch
69
54
VDD
MIN.
Value
External
Eexpansion
1.8 V
2.7 V
2.0 V
1.8 V
2.7 V
—
1.8 V
2.7 V
—
1.8 V
2.0 V
—
—
2.7 V
4.5 V
3
µPD78081, 78082
OVERVIEW OF FUNCTION
Part Number
µPD78081
µPD78082
ROM
8K bytes
16K bytes
Internal high-speed RAM
256 bytes
384 bytes
Item
Internal
memory
Memory space
General registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Instruction cycle
On-chip instruction execution time selective function
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at main system clock of 5.0 MHz)
Instruction set
•
•
•
•
I/O ports
Total
• CMOS input
• CMOS I/O
A/D converter
8-bit resolution × 8 channels
Serial interface
3-wire serial I/O / UART mode selectable : 1 channel
Timer
• 8-bit timer/event counter : 2 channels
• Watchdog timer
: 1 channel
Timer output
2 (8-bit PWM output)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz
(at main system clock of 5.0 MHz)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock of 5.0 MHz)
Vectored
interrupts
4
64K bytes
16-bit operation
Multiplcation/division (8 bits × 8 bits,16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, boolean operation)
BCD adjustment, etc.
Maskable interrupts
Internal : 8
external : 3
Non-maskable
interrupts
Internal : 1
Software interrupts
Internal : 1
: 33
: 01
: 32
Supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to + 85 °C
Package
• 42-pin plastic shrink DIP (600 mil)
• 44-pin plastic QFP (10 × 10 mm)
µPD78081, 78082
TABLE OF CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) .......................................................................................................... 6
2.
BLOCK DIAGRAM ....................................................................................................................................... 9
3.
PIN FUNCTIONS ........................................................................................................................................ 10
3.1
Port Pins ............................................................................................................................................................. 10
3.2
Non-port Pins .................................................................................................................................................... 11
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................. 12
4.
MEMORY SPACE ...................................................................................................................................... 14
5.
PERIPHERAL HARDWARE FUNCTIONS ...............................................................................................15
5.1
Ports .................................................................................................................................................................... 15
5.2
Clock Generator ................................................................................................................................................ 16
5.3
Timer/Event Counter ......................................................................................................................................... 16
5.4
Clock Output Control Circuit ........................................................................................................................... 18
5.5
Buzzer Output Control Circuit ........................................................................................................................ 18
5.6
A/D Converter .................................................................................................................................................... 19
5.7
Serial Interface .................................................................................................................................................. 20
6.
INTERRUPT FUNCTIONS ......................................................................................................................... 21
7.
STANDBY FUNCTION ............................................................................................................................... 24
8.
RESET FUNCTION .................................................................................................................................... 24
9.
INSTRUCTION SET ................................................................................................................................... 25
10. ELECTRICAL SPECIFICATIONS ............................................................................................................. 28
11. PACKAGE DRAWINGS ............................................................................................................................. 39
12. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 42
APPENDIX A.
DEVELOPMENT TOOLS .....................................................................................................43
APPENDIX B.
RELATED DOCUMENTS ....................................................................................................45
5
µPD78081, 78082
1. PIN CONFIGURATIONS (TOP VIEW)
• 42-pin plastic shrink DIP (600 mil)
µPD78081CU-×××
µPD78082CU-×××
P55
1
42
VSS
P56
2
41
P54
P57
3
40
P53
P30
4
39
P52
P31
5
38
P51
P32
6
37
P50
P33
7
36
P100/TI5/TO5
P34
8
35
P101/TI6/TO6
P35/PCL
9
34
P70/RXD/SI2
P36/BUZ
10
33
P71/TXD/SO2
P37
11
32
P72/ASCK/SCK2
P00
12
31
P17/ANI7
P01/INTP1
13
30
P16/ANI6
P02/INTP2
14
29
P15/ANI5
P03/INTP3
15
28
P14/ANI4
RESET
16
27
P13/ANI3
IC
17
26
P12/ANI2
X2
18
25
P11/ANI1
X1
19
24
P10/ANI0
VDD
20
23
AVSS
AVDD
21
22
AVREF
Cautions 1. Connect IC (Internally Connected) pin directly to VSS.
2. Connect AVDD pin to VDD.
3. Connect AVSS pin to VSS.
6
µPD78081, 78082
• 44-pin plastic QFP (10 × 10 mm)
µPD78081GB-×××-3B4
µPD78081GB-×××-3BS-MTX
µPD78082GB-×××-3B4
NC
RESET
X2
IC
X1
VDD
AVDD
AVREF
AVSS
P10/ANI0
P11/ANI1
µPD78082GB-×××-3BS-MTX
P12/ANI2
1
44 43 42 41 40 39 38 37 36 35 34
33
P03/INTP3
P13/ANI3
2
32
P02/INTP2
P14/ANI4
3
31
P01/INTP1
P15/ANI5
4
30
P00
P16/ANI6
5
29
P37
P101/TI6/TO6
10
24
P32
P100/TI5/TO5
11
23
12 13 14 15 16 17 18 19 20 21 22
NC
P31
P30
P33
P57
P34
25
P56
26
9
VSS
8
P70/RXD/SI2
P55
P71/TXD/SO2
P54
P35/PCL
P53
P36/BUZ
27
P52
28
7
P51
6
P50
P17/ANI7
P72/ASCK/SCK2
Cautions 1. Connect IC (Internally Connected) pin directly to VSS.
2. Connect AVDD pin to VDD.
3. Connect AVSS pin to VSS.
4. Connect NC (Non-connection) pin to VSS for noise protection (It can be left open).
7
µPD78081, 78082
P00 to P03
: Port 0
PCL
P10 to P17
: Port 1
BUZ
: Buzzer Clock
P30 to P37
: Port 3
X1, X2
: Crystal (Main System Clock)
P50 to P57
: Port 5
RESET
: Reset
P70 to P72
: Port 7
ANI0-ANI7
: Analog Input
P100, P101
: Port 10
AVDD
: Analog Power Supply
INTP1 to INTP3
: Interrupt from Peripherals
AVSS
: Analog Ground
TI5, TI6
: Timer Input
AVREF
: Analog Reference Voltage
TO5, TO6
: Timer Output
VDD
: Power Supply
SI2
: Serial Input
VSS
: Ground
SO2
: Serial Output
IC
: Internally Connected
SCK2
: Serial Clock
NC
: Non-connection
RxD
: Receive Data
TxD
: Transmit Data
ASCK
: Asynchronous Serial Clock
8
: Programmable Clock
µPD78081, 78082
2. BLOCK DIAGRAM
P00
P100/TI5/TO5
8-bit TIMER/
EVENT COUNTER 5
PORT 0
P01-P03
P101/TI6/TO6
8-bit TIMER/
EVENT COUNTER 6
PORT 1
P10-P17
PORT 3
P30-P37
SERIAL
INTERFACE 2
PORT 5
P50-P57
A/D
CONVERTER
PORT 7
P70-P72
PORT 10
P100, P101
WATCHDOG
TIMER
SI2/RXD/P70
SO2/TXD/P71
SCK2/ASCK/P72
ANI0/P10ANI7/P17
AVDD
AVSS
AVREF
78K/0
CPU
CORE
ROM
RAM
INTP1/P01INTP3/P03
BUZ/P36
INTERRUPT
CONTROL
BUZZER OUTPUT
RESET
SYSTEM
CONTROL
PCL/P35
CLOCK OUTPUT
CONTROL
VDD
VSS
IC
X1
X2
Remark The internal ROM and internal high-speed RAM capacities depend on the product.
9
µPD78081, 78082
3. PIN FUNCTIONS
3.1 Port pins
Pin Name
Input/Output
Function
After Reset
P00
Input
Port 0
Input only
Input
P01
Input/output
4-bit input/output port
Input/output is specifiable
Input
Shared by:
—
INTP1
P02
bit-wise. When used as the
INTP2
P03
input port, it is possible to
INTP3
connect a pull-up resistor by
software.
P10-P17
Input/output
Port 1
Input
ANI0-ANI7
8-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
a pull-up resistor by software.
P30-P34
Input/output
Note
Port 3
Input
—
P35
8-bit input/output port
PCL
P36
Input/output is specifiable bit-wise.
BUZ
P37
When used as the input port, it is possible to connect
—
a pull-up resistor by software.
P50-P57
Input/output
Port 5
Input
—
8-bit input/output port
Can drive up to seven LEDs directly.
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
a pull-up resistor by software.
P70
Input/output
Port 7
Input
SI2/RxD
P71
3-bit input/output port
SO2/TxD
P72
Input/output is specifiable bit-wise.
SCK2/ASCK
When used as the input port, it is possible to connect
a pull-up resistor by software.
P100
P101
Input/output
Port 10
2-bit input/output port
Input
TI5/TO5
TI6/TO6
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
a pull-up resistor by software.
Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode.
The on-chip pull-up resistor is automatically disabled.
10
µPD78081, 78082
3.2 Non-port pins
Pin Name
INTP1
Input/Output
Input
Function
External interrupt input by which the active edge (rising edge,
INTP2
After Reset
Input
falling edge, or both rising and falling edges) can be specified.
Shared by:
P01
P02
INTP3
P03
SI2
Input
Serial interface serial data input.
Input
P70/RxD
SO2
Output
Serial interface serial data output.
Input
P71/TxD
SCK2
Input/Output
Serial interface serial clock input/output.
Input
P72/ASCK
RxD
Input
Asynchronous serial interface serial data input.
Input
P70/SI2
TxD
Output
Asynchronous serial interface serial data output.
Input
P71/SO2
ASCK
Input
Asynchronous serial interface serial clock input.
Input
P72/SCK2
TI5
Input
External count clock input to 8-bit timer (TM5).
Input
P100/TO5
Input
P100/TI5
TI6
TO5
External count clock input to 8-bit timer (TM6).
Output
8-bit timer output.
P101/TO6
TO6
P101/TI6
PCL
Output
Clock output. (for main system clock trimming)
Input
P35
BUZ
Output
Buzzer output.
Input
P36
ANI0-ANI7
Input
A/D converter analog input.
Input
P10-P17
AVREF
Input
A/D converter reference voltage input.
–
–
–
A/D converter analog power supply. Connected to VDD.
–
–
–
–
AVDD
AVSS
A/D converter ground potential. Connected to VSS.
–
RESET
Input
System reset input.
–
–
X1
Input
Main system clock oscillation crystal connection.
–
–
–
–
–
–
X2
–
VDD
–
Positive power supply.
VSS
–
Ground potential.
–
–
IC
–
Internal connection. Connect directly to VSS.
–
–
NC
–
Does not internally connected. Connect to VSS.
–
–
(It can be left open)
11
µPD78081, 78082
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin Input/Output Circuits
Pin Name
P00
Input/Output
Circuit Type
I/O
Recommended Connection for Unused Pins
2
Input
8-A
Input/output
Connect to VSS via a resistor individually.
P10/ANI0-P17/ANI7
11
Input/output
Connect to VDD or VSS via a resistor individually.
P30-P32
5-A
P33, P34
8-A
P35/PCL
5-A
P01/INTP1
Connect to VSS.
P02/INTP2
P03/INTP3
P36/BUZ
P37
P50-P57
5-A
P70/SI2/RxD
8-A
P71/SO2/TxD
5-A
P72/SCK2/ASCK
8-A
P100/TI5/TO5
8-A
P101/TI6/TO6
RESET
2
Input
AVREF
–
–
–
Connect to VSS.
AVDD
Connect to VDD.
AVSS
Connect to VSS.
IC
Connect to VSS.
NC
Connect to VSS (It can be left open).
12
µPD78081, 78082
Figure 3-1. Pin Input/Output Circuits
Type 2
Type 8-A
V DD
pullup
enable
P-ch
IN
V DD
data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristic
pullup
enable
P-ch
VDD
data
P-ch
IN/OUT
P-ch
IN/OUT
output
disable
VDD
pullup
enable
P-ch
V DD
data
N-ch
Type 11
V DD
Type 5-A
output
disable
N-ch
output
disable
N-ch
P-ch
Comparator
+
–
N-ch
VREF(threshold voltage)
input
enable
input
enable
13
µPD78081, 78082
4. MEMORY SPACE
The memory map of the µPD78081, 78082 is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH
Special function registers
(SFR) 256 × 8 bits
FF00H
FEFFH
FEE0H
General-purpose registers
32 × 8 bits
nnnnH
FEDFH
Program area
Internal high-speed
Data
memory
space
RAMNote
1000H
0FFFH
CALLF entry area
mmmmH
mmmmH–1
0800H
07FFH
Program area
Use prohibited
0080H
007FH
nnnnH+1
nnnnH
Program
memory
space
CALLT table area
Internal ROMNote
0040H
003FH
Vector table area
0000H
0000H
Note The internal ROM and internal high-speed RAM capacities depend on the product. (See the following table.)
Internal ROM Last Address
nnnnH
Internal High-speed RAM Starting Address
mmmmH
µPD78081
1FFFH
FE00H
µPD78082
3FFFH
FD80H
Part Number
14
µPD78081, 78082
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 Ports
Input/output ports are classified into two types.
• CMOS input (P00)
:
1
• CMOS input/output (P01 to P03, Port 1, Port 3, Port 5, Port 7, Port 10) : 32
Total
: 33
Table 5-1. Functions of Ports
Port Name
Pin Name
Port 0
P00
Function
Input only.
P01 to P03
Input/output port. Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
Port 1
P10 to P17
Input/output port. Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
Port 3
P30 to P37
Input/output port. Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
Port 5
P50 to P57
Input/output port. Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
LED can be driven directly up to 7 pins.
Port 7
P70 to P72
Input/output port. Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
Port 10
P100, P101
Input/output port. Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
15
µPD78081, 78082
5.2 Clock Generator
Main system clock generator is incorporated.
It is possible to change the instruction execution time.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at main system clock frequency of 5.0 MHz)
Figure 5-1. Clock Generator Block Diagram
X1
X2
Main system fX
clock
oscillator
Division
circuit
Selector
Prescaler
Prescaler
Clock to peripheral
hardware
fXX
fXX
2
fX
2
fXX
22
fXX
23
fXX
24
Selector
STOP
Standby
control
circuit
CPU clock
(fCPU)
5.3 Timer/Event Counter
There are the following three timer/event counter channels:
• 8-bit timer/event counter
: 2 channels
• Watchdog timer
: 1 channel
Table 5-2. Types and Functions of Timer/Event Counters
8-bit Timer/Event Counter 5, 6
Type
Function
16
Watchdog Timer
Interval timer
2 channels
1 channel
External event counter
2 channels
–
Timer output
2 output
–
PWM output
2 output
–
Square wave output
2 output
–
Interrupt request
2
1
µPD78081, 78082
Figure 5-2. 8-Bit Timer/Event Counter 5, 6 Block Diagram
Internal bus
8-bit compare register
(CRn0)
Match
Selector
2fXX - fXX/29
11
fXX/2
TI5/P100/TO5,
TI6/P101/TO6
INTTMn
OVF
8-bit timer register n
(TMn)
TO5/P100/TI5,
TO6/P101/TI6
Output control
circuit
Clear
Internal bus
n = 5, 6
Figure 5-3. Watchdog Timer Block Diagram
f XX
23
Prescaler
f XX
26
f XX
27
f XX
28
f XX
29
f XX
2 11
INTWDT
maskable
interrupt request
8-bit counter
Control
circuit
f XX
25
Selector
f XX
24
RESET
INTWDT
non-maskable
interrupt request
17
µPD78081, 78082
5.4 Clock Output Control Circuit
This circuit can output clocks of the following frequencies:
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (at main system clock
frequency of 5.0 MHz)
Figure 5-4. Clock Output Control Circuit Block Diagram
fXX
fXX/2
Selector
fXX/22
fXX/23
fXX/24
Synchronization
circuit
Output control
circuit
PCL/P35
fXX/25
fXX/26
fXX/27
5.5 Buzzer Output Control Circuit
This circuit can output clocks of the following frequencies that can be used for driving buzzers:
• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (at main system clock frequency of 5.0 MHz)
fXX/29
fXX/210
11
fXX/2
18
Selector
Figure 5-5. Buzzer Output Control Circuit Block Diagram
Output control
circuit
BUZ/P36
µPD78081, 78082
5.6 A/D Converter
The A/D converter consists of eight 8-bit resolution channels.
A/D conversion can be started by the following two methods:
• Hardware starting
• Software starting
Figure 5-6. A/D Converter Block Diagram
Series resistor string
AV DD
ANI0/P10
AV REF
ANI1/P11
ANI2/P12
ANI4/P14
Voltage comparator
Selector
ANI3/P13
ANI5/P15
Tap selector
Sample & hold circuit
ANI6/P16
AV SS
ANI7/P17
INTP3/P03
Successive approximation
register (SAR)
Edge
detector
Control
circuit
INTAD
INTP3
A/D conversion result
register (ADCR)
Internal bus
19
µPD78081, 78082
5.7 Serial Interface
There is one on-chip serial interface channel synchronous with the clock.
The serial interface channel 2 operates in the following two modes:
• 3-wire serial I/O mode
: Starting bit MSB/LSB switching possible
• Asynchronous serial interface (UART) mode : On-chip dedicated baud rate generator
Figure 5-7. Serial Interface Channel 2 Block Diagram
Internal bus
RXD/SI2/P70
Receive buffer
register (RXB/SIO2)
Direction control
circuit
Direction control
circuit
Transmit shift
register (TXS/SIO2)
Receive shift
register (RXS)
Transmit control
circuit
TXD/SO2/P71
Receive control
circuit
INTSER
INTSR/INTCSI2
SCK output
control circuit
ASCK/SCK2/P72
Baud rate
generator
20
fXX–fXX/210
INTST
µPD78081, 78082
6. INTERRUPT FUNCTIONS
A total of 13 interrupt functions are provided, divided into the following three types.
• Non-maskable interrupt
: 1
• Maskable interrupt
: 11
• Software interrupt
: 1
Table 6-1. List of Interrupt Factors
Note 1
Interrupt
Type
Interrupt Factor
Note 2
Internal/
External
Vector
Basic
Table Structure
Address
Type
Internal
0004H
Default
Priority
Name
Nonmaskable
–
INTWDT
Overflow of watchdog timer (When the watchdog timer
mode 1 is selected)
Maskable
0
INTWDT
Overflow of watchdog timer (When the interval timer mode
is selected)
1
INTP1
2
INTP2
000AH
3
INTP3
000CH
4
INTSER
Occurrence of serial interface channel 2 UART reception
error
5
INTSR
Completion of serial interface channel 2 UART reception
INTCSI2
Software
Trigger
Pin input edge detection
(A)
(B)
External
Internal
0008H
0018H
(C)
(B)
001AH
Completion of serial interface channel 2 3-wire transfer
6
INTST
Completion of serial interface channel 2 UART transmission
001CH
7
INTAD
Completion of A/D covnersion
0028H
8
INTTM5
Generation of matching signal of 8-bit timer/event counter 5
002AH
9
INTTM6
Generation of matching signal of 8-bit timer/event counter 6
002CH
–
BRK
Execution of BRK instruction
Internal
003EH
(D)
Notes 1. Default priority is the priority order when several maskable interruptions are generated at the same
time. 0 is the highest order and 9 is the lowest order.
2. Basic structure types (A) to (D) correspond to (A) to (D) in Figure 6-1.
21
µPD78081, 78082
Figure 6-1. Interrupt Function Basic Configuration (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
address
generator
Priority
control
circuit
Interrupt
request
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Priority
control
circuit
IF
Vector table
address
generator
Standby release
signal
(C) External maskable interrupt
Internal bus
External interrupt
mode register
(INTM0, INTM1)
Interrupt
request
Edge
detector
MK
IF
IE
PR
Priority control
circuit
ISP
Vector table
address
generator
Standby
release
signal
22
µPD78081, 78082
Figure 6-1. Interrupt Function Basic Configuration (2/2)
(D) Software interrupt
Internal bus
Interrupt
request
IF
:
Interrupt request flag
E
:
Interrupt enable flag
ISP :
In-service priority flag
MK :
Interrupt mask flag
PR :
Priority specification flag
Priority
control
circuit
Vector table
address
generator
23
µPD78081, 78082
7. STANDBY FUNCTION
The standby function intends to reduce current consumption. It has the following two modes:
• HALT mode : In this mode, the CPU operation clock is stopped. The average current consumption can be
reduced by intermittent operation by combining this mode with the normal operation mode.
• STOP mode : In this mode, oscillation of the main system clock is stopped. All the operations performed on the
main system clock are suspended, and power consumption becomes extremely small.
Figure 7-1. Standby Function
Main system clock operation
STOP
instruction
Interrupt
request
HALT instruction
Interrupt
request
STOP mode
(Oscillation of the main system
clock is stopped.)
8. RESET FUNCTION
There are the following two reset methods.
• External reset input by RESET pin
• Internal reset by watchdog timer runaway time detection
24
HALT mode
(Supply of clock to CPU is
stopped although clock
is generated.)
µPD78081, 78082
9. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC,
ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand
#byte
A
rNote
sfr
saddr
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
[DE]
[HL]
1st Operand
A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r
MOV
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
1
None
ROR
ROL
RORC
ROLC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C
INC
DEC
DBNZ
sfr
MOV
saddrMOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
[HL + byte]
[HL + B] $addr16
[HL + C]
MOV
DBNZ
INC
DEC
MOV
MOV
[DE]
MOV
PUSH
POP
MOV
Note Except r = A
25
µPD78081, 78082
2nd Operand
#byte
A
r
sfr
saddr
!addr16
PSW
[DE]
[HL]
1st Operand
[HL]
MOV
[HL + byte]
[HL + B]
[HL + C]
MOV
[HL + byte]
[HL + B] $addr16
[HL + C]
1
None
ROR4
ROL4
X
MULU
C
DIVUW
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
AX
rpNote
sfrp
MOVW
XCHW
MOVW
saddrp
!addr16
SP
None
1st Operand
AX
ADDW
SUBW
CMPW
rp
MOVW
MOVWNote
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
MOVW
MOVW
Note Only when rp = BC, DE, HL
26
MOVW
MOVW
MOVW
MOVW
INCW
DECW
PUSH
POP
µPD78081, 78082
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
1st Operand
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
SET1
CLR1
NOT1
(4) Call instructions/Branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
AX
!addr16
!addr11
[addr5]
$addr16
1st Operand
Basic instruction
Compound instruction
BR
CALL
BR
CALLF
CALLT
BR
BC
BNC
BZ
BNZ
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
27
µPD78081, 78082
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Test Conditions
Ratings
Unit
VDD
–0.3 to +7.0
V
AVDD
–0.3 to VDD + 0.3
V
AVREF
–0.3 to VDD + 0.3
V
AVSS
–0.3 to +0.3
V
Input voltage
VI
–0.3 to VDD + 0.3
V
Output voltage
VO
Analog input voltage
VAN
P10-P17
Output current, high
IOH
Supply voltage
–0.3 to VDD + 0.3
V
AVSS – 0.3 to AVREF + 0.3
V
Per pin
–10
mA
Total of P10-P17, P50-P54, P70-P72,
–15
mA
Analog input pins
P100, P101
Total of P01-P03, P30-P37, P55-P57 –15
IOL Note
Output current, low
Per pin
mA
15
mA
r.m.s. value
Total of P50-P54
Peak value 100
r.m.s. value
Total of P55-P57
mA
Peak value 30
mA
70
mA
Peak value 100
mA
70
mA
Total of P10-P17, P70-P72, P100,
Peak value 50
mA
P101
r.m.s. value
20
mA
Total of P01-P03, P30-P37
Peak value 50
mA
20
mA
r.m.s. value
r.m.s. value
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] × Duty
Caution If the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product
may be degraded. The absolute maximum ratings are therefore the rated values that may, if exceeded,
physically damage the product. Be sure to use the product with all the absolute maximum ratings
observed.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz, Unmeasured pins returned to 0 V.
15
pF
I/O capacitance
CIO
f = 1 MHz,
P01-P03, P10-P17, P30-P37,
15
pF
Unmeasured pins
P50-P57, P70-P72, P100,
returned to 0 V.
P101
Remark Unless otherwise specified, shared pin characteristics are the same as port pin characteristics.
28
µPD78081, 78082
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
Ceramic
IC X2
X1
resonator
Oscillation frequency
(fX)
C2
C1
Note 1
Oscillation stabilization
time
Crystal
IC X2
X1
resonator
C1
Note 2
VDD = Oscillation voltage
MIN.
TYP.
1.0
After VDD came to MIN.
X2
1.0
VDD = 4.5 to 5.5 V
X1 input frequency
(fX)
µ PD74HCU04
MHz
4
ms
5.0
MHz
10
ms
Note 1
Oscillation stabilization
X1
5.0
of oscillation voltage range
time Note 2
External clock
Unit
MAX.
range
Oscillation frequency
(fX)
C2
Test Conditions
Parameter
Circuit
30
1.0
5.0
MHz
85
500
ns
Note 1
X1 input high- and
low-level widths (tXH, tXL)
Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics.
2. Time required for oscillation to stabilize after a reset or the STOP mode has been released.
Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in
the figures as follows to avoid adverse influences on the wiring capacitance:
• Keep the wiring length as short as possible.
• Do not cross the wiring over other signal lines.
• Do not route the wiring in the vicinity of lines through which a high fluctuating current flows.
• Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS.
• Do not connect the power source pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
29
µPD78081, 78082
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input voltage, high
Symbol
VIH1
Test Conditions
P10-P17, P30-P32,
VDD = 2.7 to 5.5 V
MAX.
Unit
0.7V DD
MIN.
TYP.
VDD
V
0.8VDD
VDD
V
0.8V DD
VDD
V
0.85VDD
VDD
V
VDD
V
P35-P37, P50-P57,
P71
VIH2
P00-P03, P33, P34,
VDD = 2.7 to 5.5 V
P70, P72, P100, P101,
RESET
VIH3
X1, X2
VDD = 2.7 to 5.5 V
VDD–0.5
VDD
V
VIL1
P10-P17, P30-P32,
VDD = 2.7 to 5.5 V
0
0.3VDD
V
0
0.2VDD
V
0
0.2VDD
V
0
0.15VDD
V
0
0.4
V
0
0.2
V
VDD–0.2
Input voltage, low
P35-P37, P50-P57,
P71
VIL2
P00-P03, P33, P34,
VDD = 2.7 to 5.5 V
P70, P72, P100,
P101, RESET
VIL3
X1, X2
Output voltage, high
VOH
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD–1.0
IOH = –100 µA
VDD–0.5
Output voltage, low
VOL
P50-P57
VDD = 2.7 to 5.5 V
V
V
VDD = 2.0 to 4.5 V,
0.8
V
2.0
V
0.4
V
0.5
V
3
µA
X1, X2
20
µA
P00-P03, P10-P17,
–3
µA
–20
µA
3
µA
IOL = 10 mA
VDD = 4.5 to 5.5 V,
0.4
IOL = 15 mA
Input leak current, high
ILIH1
P01-P03, P10-P17,
VDD = 4.5 to 5.5 V,
P30-P37, P70-P72,
IOL = 1.6 mA
P100, P101
IOL = 400 µA
VIN = VDD
P00-P03, P10-P17,
P30-P37, P50-P57,
P70-P72, P100,
P101, RESET
ILIH2
Input leak current, low
ILIL1
VIN = 0 V
P30-P37, P50-P57,
P70-P72, P100,
P101, RESET
ILIL2
Output leak current, high
X1, X2
ILOH
VOUT = VDD
Output leak current, low
ILOL
VOUT = 0 V
Software pull-up resistor
R
VIN = 0 V
P01-P03, P10-P17,
15
40
P30-P37, P50-P57,
P70-P72, P100,
P101
Remark Unless otherwise specified, shared pin characteristics are the same as port pin characteristics.
30
–3
µA
90
kΩ
µPD78081, 78082
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Supply current
Note 1
Symbol
IDD1
TYP.
MAX.
Unit
5.0-MHz crystal
Test Conditions
VDD = 5.0 V ± 10%
Note 4
4.5
13.5
mA
oscillation operating
VDD = 3.0 V ± 10%
Note 5
0.7
2.1
mA
Note 2
VDD = 2.0 V ± 10%
Note 5
0.4
1.2
mA
5.0-MHz crystal oscil-
VDD = 5.0 V ± 10%
Note 4
8.0
24.0
mA
lation operating mode
VDD = 3.0 V ± 10%
Note 5
0.9
2.7
mA
1.4
4.2
mA
mA
mode (fXX = 2.5 MHz)
(fXX = 5.0 MHz)
IDD2
Note 3
5.0-MHz crystal oscil-
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
0.5
1.5
VDD = 2.0 V ± 10%
280
840
µA
5.0-MHz crystal oscil-
VDD = 5.0 V ± 10%
1.6
4.8
mA
lation HALT mode
VDD = 3.0 V ± 10%
0.65
1.95
mA
lation HALT mode
(fXX = 2.5 MHz)
(fXX = 5.0 MHz)
IDD3
MIN.
Note 2
Note 3
STOP mode
VDD = 5.0 V ± 10%
0.1
30
µA
VDD = 3.0 V ± 10%
0.05
10
µA
VDD = 2.0 V ± 10%
0.05
10
µA
Notes 1. Not including AVREF, AVDD currents or port currents (including current flowing into internal pull-up resistors).
2. fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H).
3. fXX = fX operation (when oscillation mode selection register (OSMS) is set to 01H).
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when processor clock control regisrer (PCC) is set to 04H).
Remark fXX : Main system clock frequency (fX or fX/2)
fX : Main system clock oscillation frequency
31
µPD78081, 78082
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Cycle time
Test Conditions
TCY
fXX = f X/2
Note1
MAX.
Unit
VDD = 2.7 to 5.5 V
MIN.
0.8
64
µs
2.0
64
µs
3.5 V ≤ VDD ≤ 5.5 V
0.4
32
µs
2.7 V ≤ VDD < 3.5 V
0.8
32
µs
0
4
MHz
0
275
kHz
(minimum instruction execution
fXX = f X Note2
time)
TI5, TI6
fTI
VDD = 4.5 to 5.5 V
input frequency
TI5, TI6 input high-/
tTIH,
low-level widths
tTIL
Interrupt input high-/
tINTH,
low-level widths
tINTL
RESET low-level width
tRSL
VDD = 4.5 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
TYP.
100
ns
1.8
µs
10
µs
20
µs
10
µs
20
µs
Notes 1. When oscillation mode selection register (OSMS) is set to 00H.
2. When OSMS is set to 01H.
Remark fXX : Main system clock frequency (fX or fX/2)
fX : Main system clock oscillation frequency
TCY vs VDD
(Main System Clock fXX = fX/2 Operation)
TCY vs VDD
(Main System Clock fXX = fX Operation)
60
10
Cycle Time TCY [µ s]
Cycle Time TCY [µ s]
60
Operation
Guaranteed Range
2.0
1.0
0.5
0.4
0
Operation
Guaranteed
Range
2.0
1.0
0.5
0.4
1
2
3
4
5
6
Power Supply Voltage VDD [V]
32
10
0
1
2
3
4
5
6
Power Supply Voltage VDD [V]
µPD78081, 78082
(2) Serial Interface (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK2... Internal clock output)
Parameter
SCK2 cycle time
SCK2 high/low-level
Symbol
tKCY1
tKH1, tKL1
Conditions
tSIK1
(to SCK2↑)
SI2 hold time
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
VDD = 4.5 to 5.5 V
tKCY1/2–50
ns
tKCY1/2–100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
width
SI2 setup time
MIN.
tKSI1
(from SCK2↑)
SO2 output delay time
tKSO1
C = 100 pF Note
300
ns
MAX.
Unit
from SCK2↓
Note C is the load capacitance of SCK2, SO2 output line.
(b) 3-wire serial I/O mode (SCK2... External clock input)
Parameter
SCK2 cycle time
SCK2 high/low-level
Symbol
tKCY2
tKH2, tKL2
width
Conditions
tSIK2
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
VDD = 2.0 to 5.5 V
(to SCK2↑)
SI2 hold time
TYP.
4.5 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
SI2 setup time
MIN.
tKSI2
1600
ns
2400
ns
100
ns
150
ns
400
ns
(from SCK2↑)
SO2 output delay time
tKSO2
C = 100 pF Note VDD = 2.0 to 5.5 V
from SCK2↓
SCK2 rise/fall time
tR2, tF2
300
ns
500
ns
1000
ns
Note C is the load capacitance of SO2 output line.
33
µPD78081, 78082
(c) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Transfer rate
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
78125
bps
2.7 V ≤ VDD < 4.5 V
39063
bps
2.0 V ≤ VDD < 2.7 V
19531
bps
9766
bps
MAX.
Unit
(d) UART mode (External clock input)
Parameter
ASCK cycle time
Symbol
tKCY3
Conditions
tKH3, tKL3
width
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
4800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
Transfer rate
ASCK rise/fall time
34
tR3, tF3
TYP.
4.5 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
ASCK high/low-level
MIN.
1600
ns
2400
ns
4.5 V ≤ VDD ≤ 5.5 V
39063
2.7 V ≤ VDD < 4.5 V
19531
bps
2.0 V ≤ VDD < 2.7 V
9766
bps
6510
bps
1000
ns
bps
µPD78081, 78082
AC Timing Test Points (excluding X1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test points
Clock Timing
1/fX
tXL
tXH
VDD – 0.5 V
0.4 V
X1 Input
TI Timing
1/fTI
tTIL
tTIH
TI5, TI6
35
µPD78081, 78082
Serial Transfer Timing
3-wire serial I/O mode :
tKCY1, 2
tKL1, 2
tKH1, 2
tF2
tR2
SCK2
tSIK1, 2
SI2
tKSI1, 2
Input data
tKSO1, 2
SO2
Output data
UART mode (external clock input) :
t KCY3
t KL3
t KH3
tR3
tF3
ASCK
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Resolution
Overall error Note
Conversion time
tCONV
Sampling time
Analog input voltage
Reference voltage
Resistance between AVREF and AVSS
tSAMP
VIAN
AVREF
RAIREF
Conditions
2.7
1.8
2.0
1.8
V
V
V
V
≤
≤
≤
≤
AVREF ≤ AVDD
AVREF < 2.7 V
AVDD ≤ 5.5 V
AVDD < 2.0 V
MIN.
8
19.1
38.2
12/fxx
AVSS
1.8
4
TYP.
8
MAX.
8
0.6
1.4
200
200
AVREF
AVDD
14
Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
Remarks 1. fXX : Main system clock frequency (fX or fX/2)
2. fX : Main system clock oscillation frequency
36
Unit
bit
%
%
µs
µs
µs
V
V
kΩ
µPD78081, 78082
Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to + 85°C)
Parameter
Symbol
Data retention power
supply voltage
VDDDR
Data retention power
supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
wait time
tWAIT
Conditions
MIN.
TYP.
1.8
VDDDR = 1.8 V
0.1
MAX.
Unit
5.5
V
10
µA
µs
0
Release by RESET
217/fx
ms
Release by interrupt
Note
ms
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection
of 212/fXX and 214/fXX to 217/fXX is possible.
Remark fXX : Main system clock frequency (fX or fX/2)
fX : Main system clock oscillation frequency
Data Retention Timing (STOP mode release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retension mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT mode
Operating mode
STOP mode
Data retension mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
37
µPD78081, 78082
Interrupt Input Timing
tINTL
tINTH
INTP1 - INTP3
RESET Input Timing
tRSL
RESET
38
µPD78081, 78082
11. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42
22
1
21
A
K
H
G
J
I
L
F
B
D
N
R
M
C
M
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
Remark The shape and material of the ES product is the same as
the mass produced product.
ITEM MILLIMETERS
INCHES
A
39.13 MAX.
1.541 MAX.
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
L
15.24 (T.P.)
13.2
0.600 (T.P.)
0.520
M
0.25 +0.10
–0.05
N
0.17
0.007
R
0~15°
0~15°
0.010 +0.004
–0.003
P42C-70-600A-1
39
µPD78081, 78082
µPD78081GB-×××-3B4, 78082GB-×××-3B4
44 PIN PLASTIC QFP (
10)
A
B
23
22
33
34
detail of lead end
C
D
S
R
Q
12
11
44
1
F
G
J
H
I
M
K
M
P
N
L
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
Remark The shape and material of the ES product is the same as
the mass produced product.
40
ITEM
MILLIMETERS
INCHES
A
13.6±0.4
0.535 +0.017
–0.016
B
10.0±0.2
0.394 +0.008
–0.009
C
10.0±0.2
0.394 +0.008
–0.009
D
13.6±0.4
0.535 +0.017
–0.016
F
1.0
0.039
G
1.0
0.039
H
0.35±0.10
0.014 +0.004
–0.005
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
P
Q
R
S
0.10
2.7
0.1±0.1
5°±5°
3.0 MAX.
0.004
0.106
0.004±0.004
5°±5°
0.119 MAX.
P44GB-80-3B4-3
µPD78081, 78082
µPD78081GB-×××-3BS-MTX, 78082GB-×××-3BS-MTX
44 PIN PLASTIC QFP ( 10)
A
B
23
22
33
34
detail of lead end
C
D
S
R
Q
12
11
44
1
F
J
G
H
I
M
K
M
P
N
L
NOTE
Each lead centerline is located within 0.16 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
Remark The shape and material of the ES product is the same as
the mass produced product.
ITEM MILLIMETERS
INCHES
A
13.2±0.2
0.520 +0.008
–0.009
B
10.0±0.2
0.394 +0.008
–0.009
C
10.0±0.2
0.394 +0.008
–0.009
D
13.2±0.2
0.520 +0.008
–0.009
F
1.0
0.039
G
1.0
0.039
H
0.37 +0.08
–0.07
0.015 +0.003
–0.004
I
0.16
0.007
J
0.8 (T.P.)
0.031 (T.P.)
K
1.6±0.2
0.063±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.17 +0.06
–0.05
N
0.10
0.004
P
2.7
0.106
Q
0.125±0.075
R
3 ° +7°
–3°
0.005±0.003
3° +7°
–3°
S
3.0 MAX.
0.007 +0.002
–0.003
0.119 MAX.
S44GB-80-3BS
41
µPD78081, 78082
12. RECOMMENDED SOLDERING CONDITIONS
µPD78081 and 78082 should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, consult our sales personnel.
Table 12-1. Surface Mounting Type Soldering Conditions
µPD78081GB-XXX-3B4
: 44-pin plastic QFP (10 × 10 mm)
µPD78081GB-XXX-3BS-MTX : 44-pin plastic QFP (10 × 10 mm)
µPD78082GB-XXX-3B4
: 44-pin plastic QFP (10 × 10 mm)
µPD78082GB-XXX-3BS-MTX : 44-pin plastic QFP (10 × 10 mm)
Soldering
Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
Number of times: 3 times max.
IR35-00-3
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above),
Number of times: 3 times max.
VP15-00-3
Wave soldering
Soldering bath temperature: 260°C max., Duration: 10 sec. max., Number of times:
once, Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max. Duration: 3 sec. max. (per device side)
—
Caution Use of more than one soldering methods should be avoided (except in the case of partial heating).
Table 12-2. Hole-Through Type Soldering Conditions
µPD78081CU-XXX : 42-pin plastic shrink DIP (600 mil)
µPD78082CU-XXX : 42-pin plastic shrink DIP (600 mil)
Soldering Method
Soldering Conditions
Wave soldering
(only pins)
Solder temperature: 260°C max., Duration: 10 sec. max.
Partial heating
Pin temperature: 300°C max., Duration: 3 sec. max. (per pin)
Caution Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with
the package.
42
µPD78081, 78082
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available to support development of systems using the µPD78081, 78082.
Language Processing Software
RA78K/0Notes 1, 2, 3, 4
Assembler package common to the 78K/0 series
CC78K/0Notes 1, 2, 3, 4
C compiler package common to the 78K/0 series
DF78083Notes 1, 2, 3, 4
Device file used for the µPD78083 subseries
CC78K/0–LNotes 1, 2, 3, 4
C compiler library source file common to the 78K/0 series
PROM Writing Tools
PG-1500
PROM programmer
PA-78P083CU
Programmer adapter connected to the PG-1500
PA-78P083GB
PG-1500 ControllerNotes 1, 2
Control program for the PG-1500
Debugging Tools
IE-78000-R
In-circuit emulator common to the 78K/0 series
IE-78000-R-ANote 8
In-circuit emulator common to the 78K/0 series (for integrated debugger)
IE-78000-R-BK
Break board common to the 78K/0 series
IE-78078-R-EM
Emulation board common to the µPD78078 subseries
EP-78083CU-R
Emulation probe for the µPD78083 subseries
EP-78083GB-R
EV-9200G-44
Socket mounted on the target system board prepared for 44-pin plastic QFP
SM78K0Notes 5, 6, 7
System simulator common to the 78K/0 series
ID78K0Notes 4, 5, 6, 7, 8
Integrated debugger for IE-78000-R-A
SD78K/0Notes 1, 2
Screen debugger for the IE-78000-R
DF78083Notes 1, 2, 5, 6, 7
Device file used for the µPD78083 subseries
Notes 1. Based on PC-9800 series (MS-DOSTM)
2. Based on IBM PC/ATTM and its compatibles (PC DOSTM/IBM DOSTM/MS-DOS)
3. Based on HP9000 series 300TM (HP-UXTM)
4. Based on HP9000 series 700TM (HP-UX), SPARCstationTM (SunOSTM), and EWS4800 series (EWS-UX/V)
5. Based on PC-9800 series (MS-DOS + WindowsTM)
6. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows)
7. Based on NEWSTM (NEWS-OSTM)
8. Under development
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development
tools.
2. Use the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 in combination with the DF78083.
43
µPD78081, 78082
Real-Time OS
MX78K0Notes 1, 2, 3, 4
OS used for the 78K/0 series
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note 5
Fuzzy knowledge data creating tool
FT9080Note 1/FT9085Note 2
Translator
FI78K0Notes 1, 2
Fuzzy inference module
FD78K0Notes 1, 2
Fuzzy inference debugger
Notes 1. Based on PC-9800 series (MS-DOS)
2. Based on IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS)
3. Based on HP9000 series 300 (HP-UX)
4. Based on HP9000 series 700 (HP-UX), SPARCstation (SunOS), and EWS4800 series (EWS-UX/V)
5. Based on IBM PC/AT (PC DOS/IBM DOS/MS-DOS + Windows)
Remark Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development tools.
44
µPD78081, 78082
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document No.
Document
Japanese
English
µPD78083 Subseries User’s Manual
IEU-886
IEU-1407
78K/0 Series User’s Manual-Instruction
IEU-849
IEU-1372
78K/0 Series Instruction Table
U10903J
—
78K/0 Series Instruction Set
U10904J
—
µPD78083 Subseries Special-Function Register Table
IEM-5599
—
IEA-767
10182E
78K/0 Series Application Note-Fundamental (III)
Documents on Development Tools (User's Manuals)
Document No.
Document
Japanese
English
Operation
EEU-809
EEU-1399
Language
EEU-815
EEU-1404
EEU-817
EEU-1402
Operation
EEU-656
EEU-1280
Language
EEU-655
EEU-1284
Programing Know-how
EEA-618
EEA-1208
CC78K Series Library Source File
EEU-777
—
PG-1500 PROM Programmer
EEU-651
EEU-1335
PG-1500 Controller PC-9800 Series (MS-DOS) Base
EEU-704
EEU-1291
PG-1500 Controller IBM PC Series (PC-DOS) Base
EEU-5008
U10540E
IE-78000-R
EEU-810
U11376E
IE-78000-R-A
U10057J
U10057E
IE-78000-R-BK
EEU-867
EEU-1427
IE-78078-R-EM
U10775J
EEU-1504
EEU-5003
EEU-1529
EEU-5002
U10181E
U10092J
U10092E
RA78K Series Assembler Package
RA78K Series Structured Assembler Preprocessor
CC78K Series C Compiler
CC78K/0 C Compiler Application Note
EP-78083
SM78K0 System Simulator
Reference
SM78K Series System Simulator
Third party’s user
open interface
specifications
ID78K/0 Integrated Debugger
Reference
U11151J
—
SD78K/0 Screen Debugger
Introduction
EEU-852
—
PC-9800 Series (MS-DOS) Base
Reference
U10952J
—
SD78 K/0 Screen Debugger
Introduction
EEU-5024
EEU-1414
IBM PC/AT (PC DOS) Base
Reference
U11279J
EEU-1413
Caution The above documents are subject to change without notice. Be sure to use the latest documents for
design or for any other similar purpose.
45
µPD78081, 78082
Documents on Embeded Software (User’s Manuals)
Document No.
Document
Japanese
English
EEU-5010
—
Fuzzy Knowledge Data Creation Tool
EEU-829
EEU-1438
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator
EEU-862
EEU-1444
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module
EEU-858
EEU-1441
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger
EEU-921
EEU-1458
78K/0 Series OS MX78K0
Fundamental
Other Documents
Document
Document No.
Japanese
IC Package Manual
Semiconductor Device Mounting Technology Manual
English
C10943X
C10535J
C10535E
IEI-620
IEI-1209
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Electrostatic Discharge (ESD) Test
MEM-539
—
Semiconductor Device Quality Assurance Guide
MEI-603
MEI-1202
Microcontroller-Related Product Guide – Third Party Products –
MEI-604
—
Quality Grade on NEC Semiconductor Devices
Caution The above documents are subject to change without notice. Be sure to use the latest documents for
design or for any other similar purpose.
46
µPD78081, 78082
[MEMO]
47
µPD78081, 78082
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
48
µPD78081, 78082
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Mountain View, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby Sweden
Tel: 8-63 80 820
Fax: 8-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 3
49
µPD78081, 78082
FIP is a registered trademark of NEC Corp.
IEBus is a trademark of NEC Corp.
MS-DOS and Windows are trademarks of Microsoft Corp.
IBM DOS, PC/AT and PC DOS are trademarks of IBM Corp.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett Packard Co.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corp.
The related documents in this publication may include preliminary versions. However, preliminary versions are not marked
as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
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