PCM1732 24-Bit, 96kHz, Stereo Audio DIGITAL-TO-ANALOG CONVERTER With HDCD

PCM1732 24-Bit, 96kHz, Stereo Audio DIGITAL-TO-ANALOG CONVERTER With HDCD
®
PCM1732
49%
FPO
®
®
For most current data sheet and other product
information, visit www.burr-brown.com
24-Bit, 96kHz, Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
With HDCD® Decoder
TM
●
●
●
The PCM1732 is designed for mid- to high-grade
digital audio applications which achieve 96kHz sampling rates with 24-bit audio data, such as High Definition Compatible Digital (HDCD) CD players, DVD
players, mini-disc players and AV receivers.
PCM1732 uses a newly-developed “enhanced, multilevel delta-sigma modulator” architecture that improves audio dynamic performance and reduces jitter
sensitivity.
The internal digital filter operates at 8x oversampling
at a 96kHz sampling rate, with –120dB stopband
attenuation.
PCM1732
HDCD
Amplitude
Decoding
HDCD
Hidden
Code
Recovery
HDCD
8x
Oversampling
Digital Filter
ML/I2S
MD/FSS
CS/IWO
MODE
MUTE
Low-Pass
Filter
DAC
Enhanced
Multi-Level
∆Σ
Modulator
MC/DEM
NOTE: An HDCD license from Pacific Microsonics, Inc. is
required to purchase the PCM1732.
VCC2R
AGND2R
●
●
ENHANCED MULTI-LEVEL ∆Σ DAC
INPUT AUDIO DATA WORD: 16-, 20-, 24-Bit
SAMPLING FREQUENCY (fs): 16kHz - 96kHz
SYSTEM CLOCK: 256, 384, 512, 768fS
HIGH PERFORMANCE:
THD+N: –96dB
Dynamic Range: 104dB
SNR: 104dB
AUDIO OUTPUT LEVEL: 0.57 x VCC (Vp-p)
8x OVERSAMPLING DIGITAL FILTER WITH
HDCD DECODER:
Stopband Attenuation: –120dB
Passband Ripple: ±0.00001dB
HDCD Filter Optimized for 44.1kHz to 48kHz
and 88.2kHz to 96kHz
MULTI-FUNCTIONS:
Digital De-emphasis
Soft Mute
BCKIN
Serial
Digital Attenuation
Input
LRCIN
I/F
Zero Detect
DIN
Digital Gain Scaling
Reversible Output Phase
+5V SINGLE-SUPPLY OPERATION
SMALL SO-28 PACKAGE
VCC2L
●
●
●
●
●
DESCRIPTION
AGND2L
FEATURES
Low-Pass
Filter
DAC
Mode
Control
I/F
EXTL
VOUTR
EXTR
ZERO
BPZ Control
SCK
Power-On Reset
Open
Drain
RST
HDCD® is a registered trademark of Pacific Microsonics, Inc.
Crystal/OSC
HDCD® technology is provided under license from Pacific Microsonics
Inc. The PCM1732’s design is covered by the following patents:
In the USA: 45,479,168, 5,638,074, 5,640,161, 5,808,574, 5,838,274
5,854,600, 5,864,311, 5,872,531.
In Australia: 669,114.
Other patents pending.
XTI
XTO
Power Supply
CLKO
VCC1 AGND1
VDD
DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
VOUTL
PDS-1522B
Printed in U.S.A. August, 1999
SPECIFICATIONS
24-Bit Data Performance
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted.
PCM1732
PARAMETER
CONDITIONS
MIN
TYP
MAX
RESOLUTION
24
DATA FORMAT
Audio Data Interface Format
Data Bit Length
Audio Data Format
Sampling Frequency (fS)
System Clock Frequency(1)
System Clock Duty Cycle
Standard/I2S
16/20/24 Selectable
MSB-First, Binary Two’s Complement
16
96
256/384/512/768fS
40
60
DIGITAL INPUT/OUTPUT LOGIC LEVEL
Input Logic Level (except XTI): VIH
VIL
Output Logic Level (CLKO):
VOH
VOL
CLKO PERFORMANCE(2)
Output Rise Time
Output Fall Time
Output Duty Cycle
DYNAMIC PERFORMANCE(3, 4)
THD+N
VO = 0dB
VO = –60dB
Dynamic Range
Signal-to-Noise Ratio(5)
Channel Separation
DC ACCURACY
Gain Error
Gain Mismatch Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage(6)
Center Voltage
Load Impedance
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1
(fS = 44.1kHz/48kHz optimal)
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
Filter Characteristics 2
(fS = 88.2kHz/96kHz optimal)
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
De-Emphasis Error
INTERNAL ANALOG FILTER
–3dB Bandwidth
Passband Response
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current: ICC + IDD
Power Dissipation
2.0
0.8
IOH = 2mA
IOL = 4mA
4.5
0.5
20 ~ 80% VDD, 10pF
80 ~ 20% VDD, 10pF
10pF Load
5.5
4
30
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
–96
–94
–42
fS = 44.1kHz, EIAJ A-weighted
fS = 96kHz, A-weighted
fS = 44.1kHz, EIAJ A-weighted
fS = 96kHz, A-weighted
fS = 44.1kHz
fS = 96kHz
98
98
96
Full Scale (0dB)
–90
±3.0
±3.0
±60
V
V
V
V
dB
dB
dB
% of FSR
% of FSR
mV
Vp-p
V
kΩ
5
±0.002dB
–3dB
%
dB
dB
dB
dB
dB
dB
0.57 VCC
0.5 VCC
AC Load
kHz
ns
ns
%
104
103
104
103
104
101
±1.0
±1.0
±30
VO = 0.5VCC at Bipolar Zero
UNITS
Bits
0.471fS
0.487fS
0.515fS
< 0.453fS
Stopband = 0.515fS
Stopband = 0.520fS
±0.0001
–109
–123
81/fS
±0.005dB
–3dB
dB
dB
dB
sec
0.395fS
0.441fS
0.538fS
< 0.341fS
Stopband = 0.538fS
±0.0001
–132
31/fS
±0.1
100
–0.16
f = 20kHz
VDD, VCC
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
4.5
TEMPERATURE RANGE
Operating
Storage
Thermal Resistance, θJA
5
85
93
425
465
–25
–55
kHz
dB
5.5
105
525
+70
+100
67
dB
dB
sec
dB
VDC
mA
mA
mW
mW
°C
°C
°C/W
NOTES: (1) Refer to the System Clock section of this data sheet. (2) An external buffer is recommended. (3) Dynamic performance specifications are tested with 20kHz low-pass
filter and THD+N specifications are tested with 30kHz LPF, 400Hz HPF, Average Mode. (4) Dynamic performance specifications are tested with HDCD gain scaling set to analog
gain scaling. (5) SNR is tested with infinite zero detection off. (6) Output level is for sine wave. DAC outputs 0.64 VCC (peak-to-peak) due to filter response as transient.
®
PCM1732
2
SPECIFICATIONS
16-Bit Data Performance
All specifications at +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. For discussion of HDCD scaling options, see the
Applications Considerations section of this data sheet.
PCM1732U
PARAMETER
DYNAMIC ANALOG PERFORMANCE,
STANDARD CD, ANALOG HDCD SCALING(1)
Total Harmonic Distortion + Noise
VO = 0dB
VO = –60dB
Dynamic Range
Output Voltage, Sine Wave
DYNAMIC ANALOG PERFORMANCE,
HDCD CD, ANALOG HDCD SCALING(3)
Total Harmonic Distortion + Noise
VO = 0dB
VO = –60dB
Dynamic Range
Output Voltage, Sine Wave
DYNAMIC ANALOG PERFORMANCE,
Standard CD, Digital HDCD SCALING(1)
Total Harmonic Distortion + Noise
VO = 0dB
VO = –60dB
Dynamic Range
Output Voltage, Sine Wave
DYNAMIC ANALOG PERFORMANCE
HDCD CD, Digital HDCD SCALING(2)
Total Harmonic Distortion + Noise
VO = 0dB
VO = –60dB
Dynamic Range
Output Voltage, Sine Wave
CONDITIONS
0dBFS
EIAJ A-Weighted
0dBFS(2)
0dBFS
EIAJ A-Weighted(4)
0dBFS, Without Peak Extend(2)
0dBFS, With Peak Extend(5)
+6dBFS(5, 6)
0dBFS
EIAJ A-Weighted
0dBFS
0dBFS
EIAJ A-Weighted(4)
0dBFS
+6dBFS(5)
MIN
TYP
MAX
UNITS
–95
–37
99
0.57VCC
dB
dB
dB
Vp-p
–94
–38
104
0.57VCC
0.285VCC
0.57VCC
dB
dB
dB
Vp-p
Vp-p
Vp-p
–92
–33
96
0.285VCC
dB
dB
dB
Vp-p
–91
–34
104
0.285VCC
0.57VCC
dB
dB
dB
Vp-p
Vp-p
NOTES: (1) Without dither. (2) Gain pin is LOW. (3) With the rectangular PDF dither. (4) Including Peak Extend to +6dBFS. (5) Gain pin is HIGH. (6) +6dBFS is
the full Peak Extend, while dynamic range numbers are with Peak Extend.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
PCM1732
PIN CONFIGURATION
PIN ASSIGNMENTS
Top View
SO-28
LRCIN
1
28
ML/I2S
DIN
2
27
MC/DEM
BCKIN
3
26
MD/FSS
CLKO
4
25
MUTE
XTI
5
24
MODE
XTO
6
23
CS/IWO
DGND
7
22
RST
VDD
8
21
ZERO
HDCD
9
20
GAIN
VCC2R 10
19
VCC2L
AGND2R 11
18
AGND2L
EXTR 12
17
EXTL
VOUTR 13
16
VOUTL
AGND1 14
15
VCC1
PCM1732U
PIN
NAME
I/O
DESCRIPTION
1
LRCIN
IN
Left and Right Clock Input. This clock is equal to
the sampling rate, fS.(1)
2
DIN
IN
Serial Audio Data Input(1)
3
BCKIN
IN
4
CLKO
OUT
5
XTI
IN
6
XTO
OUT
7
DGND
—
8
VDD
—
9
HDCD
OUT
Oscillator Input/External Clock Input(2)
Oscillator Output
Digital Ground
Digital Power +5V
HDCD Encoded Data Detect
10
VCC2R
—
Analog Power +5V, Rch
11
AGND2R
—
Analog Ground, Rch
12
EXTR
—
Common Mode Voltage for Analog Output Amp,
Rch
13
VOUTR
OUT
14
AGND1
—
15
VCC1
—
16
VOUTL
OUT
17
EXTL
—
18
AGND2L
OUT
19
VCC2L
—
20
GAIN
OUT
21
ZERO
OUT
22
RST
IN
Reset. When this pin is LOW, the digital filter
and modulators are held in reset.(3)
23
CS/IW0
IN
Chip Select/Input Format Selection. When this
pin is LOW, the Mode Control interface is enabled.(4)
24
MODE
IN
Mode Control Select: H = Software; L =
Hardware(3)
25
MUTE
IN
Mute Control(3)
26
MD/FSS
IN
Mode Data/Sampling Rate Range Select(3)
27
MC/DEM
IN
Mode Clock/De-Emphasis Select(3)
28
ML/I2S
IN
Mode Latch/Input Format Select(3)
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ...................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Input Current (except power supply) ............................................... ±10mA
Power Dissipation .......................................................................... 750mW
Operating Temperature Range ......................................... –25°C to +70°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) ................................................. +260°C
(reflow, 10s) .................................................... +235°C
Bit Clock Input for Serial Audio Data(1)
Buffered System Clock Output.
Analog Voltage Output, Rch
Analog Ground
Analog Power +5V
Analog Voltage Output, Lch
Common Mode Voltage for Analog Output Amp,
Lch
Analog Ground, Lch
Analog Power +5V, Lch
External (analog) Gain Scaling
Zero Data Flag
NOTES: (1) Schmitt Trigger input. (2) CMOS logic level input. (3) Schmitt
Trigger input with pull-up resister. (4) Schmitt Trigger input with pull-down
resistor.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
PCM1732U
SO-28
217
–25°C to +70°C
PCM1732U
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
PCM1732U
PCM1732U/1K
Rails
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “PCM1732U/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
PCM1732
4
TYPICAL PERFORMANCE CURVES
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted.
–60dB AMPLITUDE vs FREQUENCY
16-Bit Data
–60
–60
–70
–70
–80
–80
Amplitude (dB)
Amplitude (dB)
–60dB AMPLITUDE vs FREQUENCY
24-Bit Data
–90
–100
–110
–100
–110
–120
–120
–130
–130
–140
–140
0
2
4
6
8
10
12
14
16
18
20
0
2
4
12
14
16
–60dB AMPLITUDE vs FREQUENCY
HDCD With Peak Extend
–70
–70
–80
–80
–90
–100
–110
18
20
18
20
–90
–100
–110
–120
–120
–130
–130
–140
–140
0
2
4
6
8
10
12
14
16
18
20
0
2
4
Frequency (kHz)
6
8
10
12
14
16
Frequency (kHz)
THD+N vs SUPPLY VOLTAGE
DYNAMIC RANGE vs SUPPLY VOLTAGE
108
–86
–88
fS = 44.1kHz, 24-Bit
HDCD With Peak Extend
THD+N at 0dB (dB)
Dynamic Range (dB)
10
–60dB AMPLITUDE vs FREQUENCY
HDCD Without Peak Extend
–60
106
8
Frequency (kHz)
–60
107
6
Frequency (kHz)
Amplitude (dB)
Amplitude (dB)
–90
105
104
HDCD with Peak Extend
103
102
101
100
fS = 44.1kHz, 16-Bit
99
98
4.25
4.50
4.75
5.00
–90
–92
–94
fS = 44.1kHz, 16-Bit
–96
98
fS = 44.1kHz, 24-Bit
100
5.25
5.50
–102
4.25
5.75
Power Supply Voltage (V)
4.50
4.75
5.00
5.25
5.50
5.75
Power Supply Voltage (V)
®
5
PCM1732
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
DE-EMPHASIS ERROR (32kHz)
0.04
Level (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (32kHz)
0
–2
–4
–6
–8
–10
0.02
0
–0.02
–0.04
0
6
4
2
8
10
12
0
14
4
2
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
8
10
12
14
DE-EMPHASIS ERROR (44.1kHz)
0
–2
–4
–6
–8
–10
0.02
Level (dB)
Level (dB)
6
Frequency (kHz)
0.01
0
–0.01
–0.02
0
2
4
6
8
10
12
14
16
18
0
20
2
4
6
8
10
12
14
16
18
20
20
22
Frequency (kHz)
DE-EMPHASIS ERROR (48kHz)
0.02
Level (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
0
–2
–4
–6
–8
–10
0.01
0
–0.01
–0.02
0
2
4
6
8
10
12
14
16
18
20
22
0
2
4
6
8
Frequency (kHz)
12
14
16
18
FREQUENCY RESPONSE
(FSS High, 96kHz Filter)
FREQUENCY RESPONSE
(De-Emphasis Off, fS = 44.1kHz)
0
–20
–40
–40
–60
–60
Amplitude (dB)
0
–20
–80
–100
–120
–140
–80
–100
–120
–140
–160
–160
–180
–180
–200
–200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
4.0
0.5
1.0
PASSBAND RIPPLE CHARACTERISTICS
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (x fS Hz)
®
PCM1732
1.5
2.0
2.5
Frequency (x fS Hz)
Frequency (x fS Hz)
Amplitude (dB)
Amplitude (dB)
10
Frequency (kHz)
6
0.35
0.4
0.45
0.5
3.0
3.5
4.0
SYSTEM CLOCK
Typical input system clock frequencies to the PCM1732 are
shown in Table I and external input clock timing requirements are shown in Figure 2.
The system clock for PCM1732 must be either 256fS, 384fS,
512fS or 768fS, where fS is the audio sampling frequency
(typically 32kHz, 44.1kHz, 48kHz, 88kHz, or 96kHz). A
768fS system clock is not supported for 88.2kHz and 96kHz
sampling frequencies.
tSCKH
The system clock can be either a crystal oscillator placed
between XTI (pin 5) and XTO (pin 6), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
H
70% of VDD
L
30% of VDD
XTI
tSCKL
System Clock Pulse Width HIGH: tSCKIH : 8ns (min)
System Clock Pulse Width LOW: tSCKIL : 8ns (min)
System Clock Duty: 40% to 60%
PCM1732 has a system clock detection circuit which automatically senses if the system clock is operating at 256fS ~
768fS. The system clock should be synchronized with the
left/right clock (LRCIN, pin 1). LRCIN operates at the sampling frequency (fS). In the event these clocks are not
synchronized, the PCM1732 can compensate for the phase
difference internally. If the phase difference between leftright and system clocks is greater than 6-bit clocks (BCKIN),
the synchronization is performed internally. While the synchronization is processing, the analog output is forced to a
DC level at bipolar zero. The synchronization typically
occurs in less than 1 cycle of LRCIN.
FIGURE 2. XTI Clock Timing.
DATA INTERFACE FORMATS
Digital audio data is interfaced to the PCM1732 on pin 1
(LRCIN), pin 2 (DIN), and pin 3 (BCKIN). The PCM1732
can accept standard, I2S, and left-justified data formats.
Figure 3 illustrates acceptable input data formats. Figure 4
shows required timing specifications for digital audio data.
Reset
External Clock Input
System Clock
(256/384/512/768fS)
4
CLKO
5
XTI
6
XTO
PCM1732 has both an internal power-on reset circuit and a
RST pin (pin 22), which accepts an external reset when RST
= LOW. For internal power-on reset, initialization (reset) is
done automatically at power-on when VDD > 2.2V (typical).
During internal reset = LOW, the output of the DAC is
invalid and the analog outputs are forced to VCC /2. Figure
5 illustrates the timing of the internal power-on reset.
PCM1732
PCM1732 accepts an external forced reset when RST =
LOW. When RST = LOW, the output of the DAC is invalid
and the analog outputs are forced to VCC /2 after internal
initialization (1024 system clocks count after RST = HIGH.)
Figure 6 illustrates the timing of the RST pin.
Crystal Resonator Oscillation
System Clock
Buffer Out
4
CLKO
5
XTI
6
XTO
Buffer
C1
C2
XTAL
Zero Out (pin 21)
Zero is an open drain output. If the input data is continuously
zero for 65,536 cycles of BCKIN, an internal FET is switched
to “ON” and the drain of the internal FET is switched to
ground. The zero detect function is available in both software
mode and hardware mode.
PCM1732
C1 C2 : 10pF ~ 30pF
FIGURE 1. System Clock Connection.
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE FREQUENCY (fS)
256fS
384fS
512fS
768fS
32kHz
8.1920
12.2880
16.3840
24.5760
44.1kHz
11.2896
16.9340
22.5792
33.8688(1)
48kHz
12.2880
18.4320
24.5760
36.8640(1)
88.2kHz
22.5792
33.8688(1)
45.1584(1)
—
96kHz
24.5760
36.8640(1)
49.1520(1)
—
NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz.
TABLE I. Typical System Clock Frequencies.
®
7
PCM1732
1/fS
L_ch
R_ch
LRCIN (pin 1)
BCKIN (pin 3)
(1) 16-Bit Right Justified
DIN (pin 2)
14 15 16
1
2
MSB
(2) 20-Bit Right Justified
DIN (pin 2)
18 19 20
1
2
23 24
1
18
3
1
2
1
22
3
19 20
1
22
MSB
14
3
2
23 24
1
18
3
2
1
2
22
3
LSB
MSB
23 24
LSB
22
3
19 20
LSB
MSB
23 24
15 16
LSB
MSB
LSB
3
2
MSB
LSB
MSB
(4) 24-Bit Left Justified
DIN (pin 2)
2
15 16
LSB
MSB
(3) 24-Bit Right Justified
DIN (pin 2)
14
3
23 24
LSB
1/fS
L_ch
LRCIN (pin 1)
R_ch
BCKIN (pin 3)
(5) 16-Bit I2S
DIN (pin 2)
1
2
14
3
MSB
(6) 24-Bit I2S
DIN (pin 2)
1
2
15 16
1
2
3
MSB
LSB
22
3
MSB
23 24
1
LSB
2
14
15 16
3
MSB
LRCIN
22
23 24
LSB
1.4V
tBCL
tLB
BCKIN
1.4V
tBL
tBCY
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
: tBCY
: 100ns (min)
BCKIN Pulse Width HIGH
: tBCH
: 50ns (min)
BCKIN Pulse Width LOW
: tBCL
: 50ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
: 30ns (min)
LRCIN Edge to BCKIN Rising Edge : tLB
: 30ns (min)
DIN Set-up Time
: tDS
: 30ns (min)
DIN Hold Time
: tDH
: 30ns (min)
FIGURE 4. Audio Data Input Timing Specification.
®
PCM1732
8
2
1
2
LSB
FIGURE 3. Audio Data Input Formats.
tBCH
1
VCC = VDD
Reset
Reset Removal
Internal Reset
1024 system (= XTI) clocks
XTI
FIGURE 5. Internal Power-On Reset Timing.
RST
tRST(1)
Reset
Reset Removal
Internal Reset
1024 system (XTI) clocks
XTI
NOTE: (1) tRST = 20ns min.
FIGURE 6. External Reset Timing.
FUNCTIONAL DESCRIPTION
Table III indicates which functions are selectable within the
chosen mode. All of the functions shown are selectable within
the Software mode, but only de-emphasis control, soft mute
and input data format may be selected when using PCM1732
in the Hardware mode.
The PCM1732 can be operated in two different modes:
software or hardware mode. Software mode is a three-wire
interface using pin 28 (ML), pin 27 (MC), and pin 26 (MD).
PCM1732 can also be operated in hardware mode, where
static control signals are used on pin 28 (ML), pin 27 (DEM),
pin 26 (FSS) and pin 23 (IWO).
SOFTWARE
(Mode = H)
HARDWARE
(Mode = L)
Input Data Format Selection
O
P
Input Data Bit Selection
O
P
Input LRCIN Polarity Selection
O
X
Sampling Frequency Range
O
O
FUNCTION
The mode of operation (software or hardware) is selected by
pin 24 (MODE), as shown in Table II.
CONTROL MODE (Pin 24)
SELECTION
De-Emphasis Control
O
P
H
Software
Mute
O
O
L
Hardware
Attenuation
O
X
Infinity Zero Mute Control
O
X
TABLE II. Mode Control.
DAC Operation Control
O
X
Output Phase Selection
O
X
CLKO Output Selection
O
X
NOTE: O = selectable, X = not selectable, P = partially selectable.
TABLE III. Mode Control, Selectable Functions.
®
9
PCM1732
SOFTWARE MODE (MODE = H)
The PCM1732’s special functions in the Software mode are
shown in Table VIII. These functions are controlled using a
ML, MC, MD serial control signal.
HARDWARE MODE (MODE = L)
In Hardware mode, the following functions can be selected:
De-Emphasis Control
De-emphasis control can be selected by DEM (pin 26).
DEM (Pin 26)
FUNCTION
Input Audio Data Format Selection
Standard Format
Left-Justified
I2S Format
DE-EMPHASIS
L
OFF
H
Mute OFF (Normal Operation)
TABLE IV. De-Emphasis Control.
DEFAULT MODE
Standard Format
Input Audio Data Bit Selection
16-Bit
20-Bit
24-Bit
Sampling Rate Range Selection
The sampling rate range must be selected by FSS (pin 26)
as fS ≤ 52kHz or fS > 52kHz.
16-Bit
Sampling Rate Range
fS ≤ 52kHz
fS > 52kHz
fS ≤ 52kHz
FSS (Pin 26)
SAMPLE RATE
L
fS ≤ 52kHz
Input LRCIN Polarity Selection
Lch/Rch = HIGH/LOW
Lch/Rch = LOW/HIGH
H
fS > 52kHz
De-Emphasis Control
OFF
Soft Mute Control
OFF
TABLE V. Sampling Rate Range Select.
Input Audio Data Format
Input Data format can be selected by I2S (pin 28) and IW0
(pin 23).
I2S (Pin 28) IWO (Pin 23)
L
L
H
H
DATA FORMAT
L
H
L
H
16-Bit Data Word, Normal, Right-Justified
20-Bit Data Word, Normal, Right-Justified
16-Bit Data Word, I2S Format
24-Bit Data Word, I2S Format
Mute ON
Mute OFF (normal operation)
Infinite Zero Mute Control
Not Operated
DAC Operation Control
Operated
Sampling Rate Selection for De-Emphasis
Standard Frequency
44.1kHz
48kHz
32kHz
44.1kHz
Bit 16
Output Phase Selection
Not Inverted
CLKO Output Selection
Input Frequency
PROGRAM REGISTER BIT MAPPING
PCM1732’s special functions are controlled using four program registers which are 16 bits long. These registers are all
loaded using MD. After the 16 data bits are clocked in, ML
is used to latch in the data to the appropriate register. Figure
7 shows the complete mapping of the four registers and
Figure 8 illustrates the serial interface timing.
SOFT MUTE
L
0dB, Individual
TABLE VIII. Selectable Functions and Default.
SOFT MUTE
The Soft Mute function can be controlled by MUTE (pin 25).
H
Attenuation Control
Lch, Rch Individually
Lch, Rch Common
HDCD Hidden Code Bit Location
Bits 16, 20, 22, 24
TABLE VI. Data Format Control.
MUTE (Pin 25)
Lch/Rch = HIGH/LOW
TABLE VII. Soft Mute Control.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MODE0
res
res
res
res
res
A1
A0
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
MODE1
res
res
res
res
res
A1
A0
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
MODE2
res
res
res
res
res
A1
A0
CB1
CB0
SCA
FSS
IW1
IW0
OPE
DEM
MUT
MODE3
res
res
res
res
res
A1
A0
IZD
SF1
SF0
CK0
REV
res
ATC
LRP
I2S
FIGURE 7. Mode Register Mapping.
ML (pin 28)
MC (pin 27)
MD (pin 26)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 8. Three-Wire Serial Interface.
®
PCM1732
10
tMLL
tMHH
1.4V
ML
tMCH
tMCL
tMLS
tMLH
1.4V
MC
tMCY
LSB
MD
tMDS
tMDH
1.4V
tCSML
tMLCS
1.4V
CS
MC Pulse Cycle Time
: tMCY
: 100ns (min)
MC Pulse Width LOW
: tMCL
: 40ns (min)
MC Pulse Width HIGH
: tMCH
: 40ns (min)
MD Hold Time
: tMDH
: 40ns (min)
MD Set-up Time
: tMDS
: 40ns (min)
ML Low Level Time
: tMLL
: 40ns (min) + 1SYSCLK(1) (min)
ML High Level Time
: tMHH
: 40ns (min) + 1SYSCLK(1) (min)
ML Hold Time
: tMLH
: 40ns (min)
ML Set-up Time
: tMLS
: 40ns (min)
CS LOW to ML LOW Time(2)
: tCSML
: 10ns (min)
ML HIGH to CS HIGH Time(2)
: tMLCS
: 10ns (min)
NOTES: (1) System Clock Cycle. (2) CS should be changed during ML = HIGH.
FIGURE 9. Program Register Input Timing.
REGISTER 0 (A1 = 0, A0 = 0)
REGISTER
NAME
BIT
NAME
Register 0
AL (7:0)
LDL
A (1:0)
res
DAC Attenuation Data for Lch
Attenuation Data Load Control for Lch
Register Address
Reserved, set to LOW
Register 1
AR (7:0)
LDR
A (1:0)
res
DAC Attenuation Data for Rch
Attenuation Data Load Control for Rch
Register Address
Reserved, set to LOW
MUT
DEM
OPE
IW (1:0)
FSS
SCA
C3 (1:0)
A (1:0)
res
Left and Right DACs Soft Mute Control
De-Emphasis Control
Left and Right DACs Operation Control
Input Audio Data Bit and Format Select
Sampling Rate Range Select
HDCD Grain Scaling Select
HDCD Hidden Code Location
Register Address
Reserved, set to LOW
I2S
LRP
ATC
REV
CKO
SF (1:0)
IZD
A (1:0)
res
Audio Data Format Select
Polarity of LRCIN Select
Attenuator Control
Output Phase Select
CLKO Output Select
Sampling Rate Select
Internal Zero Detection Circuit Control
Register Address
Reserved, set to LOW
Register 2
Register 3
DESCRIPTION
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to set the attenuation data for the left
output channel.
When ATC = 1 (Bit B2 of Register MODE3 = 1), the left
channel attenuation data AL[7:0] is used for both the left and
right channel attenuators.
When ATC = 0, (Bit B2 of Register MODE3 = 0), left
channel attenuation data is taken from AL[7:0] of register
MODE0, and right channel attenuation data is taken from
AR[7:0] of register MODE1.
AL[7:0]
Left Channel Attenuator Data, where AL7 is the
MSB and AL0 is the LSB.
Attenuation Level is given by:
ATTEN = 0.5 • (DATA – 255)dB
For
For
For
For
TABLE IX. Register Functions.
DATA
DATA
DATA
DATA
=
=
=
=
FFH, ATTEN = –0dB
FEH, ATTEN = –0.5dB
01H, ATTEN = –127.5dB
00H, ATTEN = infinity = Mute
®
11
PCM1732
LDL
Left Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenuation
levels of both the Left and Right channels.
MUT (B0)
MUT = L
MUT = H
When LDL = 1, the Left channel output level is
set by the data in AL[7:0]. The Right channel
output level is set by the data in AL[7:0], or the
most recently programmed data in bits AR[7:0]
of register MODE1.
Soft Mute OFF
Soft Mute ON
TABLE X. Soft Mute Control.
DEM (B1)
DEM = L
DEM = H
When LDL = 0, the Left channel output data
remains at its previously programmed level.
De-Emphasis OFF
De-Emphasis ON
TABLE XI. De-Emphasis Control.
OPE (B2)
REGISTER 1 (A1 = 0, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8
OPE = L
OPE = H
B7 B6 B5 B4 B3 B2 B1 B0
TABLE XII. DAC Operation Control.
res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
Register 1 is used to set the attenuation data for the Right
output channel.
When OPE (B2) is HIGH, the output of the DAC will be
forced to bipolar zero, irrespective of any input data.
When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left
channel attenuation data AL[7:0] of register MODE0 is used
for both the Left and Right channel attenuators.
IW0(B3), IW1 (B4) and I2S (B0) of Register 3
Resisters IW0, IW1, and I2S determine the input data word
and input data format as shown in Table XIII.
When ATC = 0, (Bit B2 of Register MODE3 = 0), Left
channel attenuation data is taken from AL[7:0] of register
MODE0, and Right channel attenuation data is taken from
AR[7:0] of register MODE1.
AR[7:0]
Right Channel Attenuator Data, where AR7 is
the MSB and AR0 is the LSB. Attenuation
Level is given by:
ATTEN = 0.5 • (DATA – 255) dB
For
For
For
For
LDR
DATA
DATA
DATA
DATA
=
=
=
=
FFH, ATTEN = –0dB
FEH, ATTEN = –0.5dB
01H, ATTEN = –127.5dB
00H, ATTEN = infinity = Mute
IW0
I2S
AUDIO INTERFACE
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
L
L
H
H
H
H
16-Bit Standard (Right-Justified)
20-Bit Standard (Right-Justified)
24-Bit Standard (Right-Justified)
24-Bit Left-Justified (MSB First)
16-Bit I2S
24-Bit I2S
Reserved
Reserved
Sampling Rate Range is selected by the FSS (B5) register.
When LDR = 1, the Right channel output level
is set by the data in AR[7:0], or by the data in
bits AL[7:0] of register MODE0. The Left channel output level is set to the most recently
programmed data in bits AL[7:0] of register
MODE0.
FSS (B5)
SAMPLING RATE RANGE
FSS = L
FSS = H
Sampling Rate, fS ≤52kHz
Sampling Rate, fS >52kHz
TABLE XIV. Sampling Rate Range Select.
HDCD gain scaling can be implemented internally with digital
gain scaling (for normal CD and HDCD without peak extend),
or externally with analog gain scaling (for HDCD with and
without peak extend).
When LDR = 0, the Right channel output data
remains at its previously programmed level.
Digital gain scaling is implemented by 6dB attenuation for
normal CD and HDCD without peak extend, and also operated
as 0dB attenuation for HDCD with peak extend. Detection for
normal CD, HDCD without peak extend, and HDCD with
peak extend is done automatically.
REGISTER 2 (A1 = 1, A0 = 0)
B7 B6 B5 B4 B3 B2 B1
IW1
TABLE XIII. Data Format Control.
Right Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenuation
levels of both the Left and Right channels.
B15 B14 B13 B12 B11 B10 B9 B8
Normal Operation
DAC Operation OFF
B0
res res res res res A1 A0 CB1 CB0 SCA FSS IW1 IWO OPE DEM MUTE
Register 2 is used to control soft mute, de-emphasis, operation enable, input resolution, and input audio data bit and
format.
SCA (B6)
GAIN SCALING
SCA = L
SCA = H
Digital Gain Scaling
Analog Gain Scaling
TABLE XV. Gain Scaling Select.
®
PCM1732
12
These bits define the location of the bit in which the PCM1732
looks for HDCD hidden code, which is inserted into the Least
Significant Bit (LSB) of the audio data.
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency for de-emphasis.
In the case of HDCD encoded data, the HDCD hidden code
is located in the Least Significant Bit (LSB) of 16-bit audio
data. It is not necessary to change the location of this hidden
code as default.
In the case of 20-bit or 24-bit data word with HDCD
encoded input signal, this HDCD hidden code bit location
must be changed to LSB of the 20- or 24-bit word to detect
HDCD encoded signal. The word length is selected by the
CB0 and CB1 bits.
CB1 (B8)
CB0 (B7)
HDCD HIDDEN CODE BIT LOCATION
L
L
H
H
L
H
L
H
16th Data (default for CD)
20th Data
Reserved
24th Data
SF1
SF0
DE-EMPHASIS SAMPLING RATE
L
L
H
H
L
H
L
H
Reserved
48kHz
44.1kHz
32kHz
TABLE XVIII. De-Emphasis Sampling Rate Selection.
CKO (B5) is output frequency control at CLKO pin, can be
selected as buffer (1/1) or half rate of input frequency (1/2).
CKO (B5)
CLOCK OUTPUT RATE
CKO = L
Buffer Out of XTI Clock
CKO = H
Half (1/2) Frequency Out of XTI Clock
TABLE XIX. Clock Output Rate Selection.
REV (B4) is output analog signal phase control.
TABLE XVI. Word Length Selection for Hidden Code Bit.
REV (B4)
REGISTER 3 (A1 = 1, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1
res res res res res A1 A0 IZD
SF1 SF0 CKO REV res ATC LRP I2S
When IZD is LOW, the zero detect circuit is off. Under
this condition, no automatic muting will occur if the input
is continuously zero. When IZD is HIGH, the zero detect
feature is enabled. If the input data is continuously zero for
65,536 cycles of BCKIN, the output will be immediately
forced to a bipolar zero state (VCC / 2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero,
there may be an audible click. PCM1732 allows the zero
detect feature to be disabled so the user can implement an
external muting circuit.
IZD = L
IZD = H
Zero Detect Mute OFF
Zero Detect Mute ON
Inverted Output
ATC (B2) is used as an attenuation control. When bit 3 is
set HIGH, the attenuation data on Register 0 is used for
both channels, and the data in Register 1 is ignored. When
bit 3 is LOW, each channel has separate attenuation data.
Bit 8 is used to control the Infinite Zero Detection (IZD)
function.
ZERO MUTE
Normal Output
REV = H
TABLE XX. Output Phase Inversion Control.
B0
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sampling frequency, infinite zero detection, output phase,
CLKO output, and slow roll-off.
IZD (B8)
DAC OUTPUT PHASE
REV = L
ATC (B2)
ATTENUATION CONTROL
ATC = L
Individual Channel ATT Control
ATC = H
Common ATT Control
TABLE XXI. Attenuation Control Bit.
Bit 0 (I2S)is used to control the input data format. A LOW
on bit 0 sets the format to MSB-first, right-justified standard format) and a HIGH sets the format to I 2S (Philips
serial data protocol). Bit 1 (LRP) is used to select the
polarity of LRCIN (left/right clock). When bit 1 is LOW,
left channel data is assumed when LRCIN is in a HIGH
phase, and right channel data is assumed when LRCIN is
in a LOW phase. When bit 1 is HIGH, the polarity
assumption is reversed. LRP applies only to standard and
left-justified data formats.
LRP (B1)
TABLE XVII. Zero Mute Control.
LRCIN POLARITY
LRP = L
L
R
H/Lch
LRP = H
L
R
L/Lch
TABLE XXII. LRCIN Polarity.
®
13
PCM1732
THEORY OF OPERATION
The delta-sigma DAC portion of the PCM1732 is based on
an 8-level amplitude quantizer and a 4th-order noise shaper,
which converts the oversampled input data to an 8-level
delta-sigma format.
several advantages over the typical one-bit (2 level) deltasigma modulator. These advantages include improved quantization noise performance, low out-of-band noise, low idle
channel tones, and improved jitter performance.
This newly developed “enhanced multi-level delta-sigma”
architecture achieves high-grade audio dynamic performance
and sound quality.
The theoretical quantization noise performance of an 8-level
delta-sigma modulator is shown in Figure 11 and a simulated
clock jitter sensitivity plot is shown in Figure 12.
A block diagram of the 8-level delta-sigma modulator is
shown in Figure 10. This 8-level delta-sigma modulator has
–
+
+
Z–1
Z–1
+
Z–1
+
+
Z–1
+
8-Level Quantizer
0
125
–20
120
–40
115
Dynamic Range (dB)
Amplitude (dB)
FIGURE 10. 8-Level Delta-Sigma Modulator.
–60
–80
–100
–120
110
105
100
95
–140
90
–160
85
80
–180
0
1
2
3
4
5
6
7
0
8
200
FIGURE 12. Jitter Sensitivity.
FIGURE 11. Quantization Noise Spectrum.
®
PCM1732
100
300
400
Input Clock Jitter (ps)
Frequency (fS)
14
500
600
APPLICATION
CONSIDERATIONS
OUTPUT FILTERING
For testing purposes, all dynamic tests are performed on the
PCM1732 using a 20kHz low-pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and dynamic range readings than listed in the Specifications Table. The low-pass filter removes out-of-band noise.
Although it is not audible, it may affect dynamic performance specifications.
TYPES OF CD SOURCE MATERIAL
There are two types of HDCD recordings: HDCD encoded
data “with peak extend” and “without peak extend.” Most
HDCD recordings are encoded using peak extension which
gives them more “headroom” than standard CD and HDCD
disks without peak extend.
The performance of the internal low pass filter from DC to
40kHz is shown in Figure 13. The higher frequency roll-off
of the filter is shown in Figure 14. If the user’s application
has the PCM1732 driving a wideband amplifier, it is recommended to use an external low-pass filter.
PCM1732 automatically detects these various types of source
materials, indicates HDCD encoded source material by the
HDCD encoded data detect (pin 9), and indicates a peak
extended source by the GAIN (pin 20). Table XXII shows
the relationship between various types of CD source material and their corresponding reference levels.
CD SOURCE MATERIAL
HDCD
PIN
GAIN
PIN
REFERENCE
LEVEL
L
H
H
L
L
H
0dB
0dB
–6dB
Standard CD
HDCD Without Peak Extend
HDCD With Peak Extend
1
0.5
Level (dB)
TABLE XXIII. CD Source Material and Reference Levels.
In order to ensure that the average system output level of
HDCD recordings (with peak extend) match that of standard
CD and HDCD (without peak extend), analog or digital gain
scaling is implemented.
0
–0.5
–1
DIGITAL GAIN SCALING
1
10
100
1k
10k
100k
Frequency (Hz)
Digital gain scaling is automatically performed in the digital
attenuation section by detecting HDCD material encoded
with peak extend and reducing the gain of standard CD and
HDCD encoded without peak extend by 6dB.
FIGURE 13. Low-Pass Filter Response.
Digital gain scaling produces a 6dB reduciton in dynamic
range, but does not require additional analog gain scaling
circutry.
20
Gain scaling is controlled by the SCA bit in Register 2.
Setting SCA = 0 enables digital gain scaling. Setting SCA
= 1 enables analog gain scaling. The reset default is SCA =
0, digital gain scaling.
Level (dB)
0
ANALOG GAIN SCALING
–20
–40
–60
Analog gain scaling (SCA = 1) is implemented by an
external switched analog gain circuit which is controlled by
the GAIN pin (pin 20). This switched analog gain circuit
provides +6dB of gain for HDCD disks with peak extend
0dB of gain for standard CD and HDCD disks without peak
extend. Since HDCD recording with peak extend may have
peaks similiar to standard CD recordings, the analog gain
circuits must provide enough headroom for these higher
signal levels when operating with +6dB of gain.
–80
–100
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 14. Low-Pass Filter Response.
®
15
PCM1732
POWER SUPPLY CONNECTIONS
POWER SUPPLY BYPASSING
The power supplies should be bypassed as close as possible
to the device. Refer to Figure 15 for optimal values of
bypass capacitors.
PCM1732 has four power supply pins for digital (VDD), and
analog (VCC). Each connection also has a separate ground.
If the power supplies turn on at different times, there is a
possibility of a latch-up condition. To avoid this condition,
it is recommended to have a common connection between
the digital and analog power supplies. If separate supplies
are used without a common connection, the delta between
the two supplies during ramp-up time must be less than
0.1V.
PCM1732U
PCM
Audio
Interface
C1
15pF
XTAL
+VDD
DGND
C2
15pF
C2
+
HDCD
Indicator
C4
Rch Audio Out
Post
LPF
+
+
C7
10µF
1
LRCIN
ML/I2S
28
2
DIN
MC/DEM
27
3
BCKIN
MD/FSS
26
4
CLKO
MUTE
25
5
XTI
6
XTO
7
DGND
8
VDD
9
MODE
24
CS/IWO
23
RST
22
ZERO
21
HDCD
GAIN
20
10
VCC2R
VCC2L
19
11
AGND2R
AGND2L
18
12
EXTR
EXTL
17
13
VOUTR
VOUTL
16
VCC1
15
14 AGND1
Mode Control
Gain Control
(Analog Scaling)
+
+
C6
C8
10µF
Post
LPF
+
C5
+5V
C4, C5, C6 : 10µF Alum Elec or Tant || 0.1µF ceramic capacitors.
FIGURE 15. Typical Circuit Connection Diagram.
®
PCM1732
16
Lch Audio Out
17
PCM1732
®
+
C302
10µF/16V
Q301
DTC143ESA
+
R302
5.6kΩ
VCC
R301
5.6kΩ
C304
2700pF
R306
3.9kΩ
C303
2700pF
R305
3.9kΩ
FIGURE 16. Low-Pass Filter and Amplifier (relay switched).
VOUTRRY
GAIN
VOUTLRY
C301
10µF/16V
3
2
3
2
1
4
1/2
OPA2134
C306
330pF
R304
12kΩ
U302
1
(optional)
D301
1SS133
U301
1/2
OPA2134
8
C305
330pF
R303
12kΩ
2
9
(optional)
+
+
1
10
–
3
8
4
7
R310
2kΩ
R309
2kΩ
5
6
RY301
G6H-2
R308
2kΩ
R307
2kΩ
5
6
R312
2kΩ
C308
100pF
7
7
U301
U302
4
1/2
OPA2134
1/2
OPA2134
5
6
R311
2kΩ
C307
100pF
C312 +
10µF/16V
C311 +
10µF/16V
C310 +
10µF/16V
C309 +
10µF/16V
CN302
RCA pj
–AVCC
(optional)
(optional)
+AVCC
CN301
RCA pj
AVCC–
(optional)
(optional)
AVCC+
®
PCM1732
18
Q205
DTC144ESA
AVCC+
Q202
2SC2878
Q204
DTA144ESA
Q203
DTA144ESA
Q201
2SC2878
FIGURE 17. Low-Pass Filter and Amplifier (transistor swtiched).
VOUTR-TR
GAIN
VOUTL-TR
R210
10kΩ
R203
6.8kΩ
R210
10kΩ
R212
10kΩ
R211
10kΩ
R209
10kΩ
R202
6.8kΩ
R201
6.8kΩ
+
C202
47µF/6.3V
+
C201
47µF/6.3V
C204
3900pF
R208
1kΩ
C203
3900pF
R207
1kΩ
5
6
3
2
7
U201
1/2
OPA2134
8
1
U201
C206
330pF
R206
13kΩ
4
1/2
OPA2134
C205
330pF
R205
13kΩ
R214
100Ω
AVCC–
C208 +
10µF/16V
C207 +
10µF/16V
AVCC+
R213100Ω
CN202
RCA pj
CN201
RCA pj
This datasheet has been downloaded from:
www.DatasheetCatalog.com
Datasheets for electronic components.
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