USER GUIDE EDBG Description

USER GUIDE EDBG Description
USER GUIDE
EDBG
Description
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The Atmel Embedded Debugger (EDBG) is an onboard debugger for
integration into development kits with Atmel MCUs. In addition to programming
and debugging support through Atmel Studio, the EDBG offers data streaming
capabilities between the host computer and the target MCU.
42096B-MCU-02/2014
Table of Contents
Description .................................................................................... 1
1. Overview .................................................................................. 3
1.1.
Features .............................................................................. 3
2. Programming and Debugging ................................................. 4
3. Virtual COM Port ..................................................................... 5
4. Data Gateway Interface .......................................................... 6
4.1.
4.2.
4.3.
4.4.
4.5.
SPI Interface ........................................................................
USART Interface ...................................................................
TWI Interface .......................................................................
4.3.1.
Information Interface ..................................................
GPIO Interface .....................................................................
Timestamp module ................................................................
6
6
6
6
7
8
5. Technical Overview ................................................................. 9
5.1.
5.2.
5.3.
Pin Usage ............................................................................ 9
Power Consumption ............................................................... 9
LED Control ......................................................................... 9
6. Document Revision History ................................................... 10
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1.
Overview
The Atmel Embedded Debugger (EDBG) is an onboard debugger for kits with Atmel devices.
EDBG enables the user to debug the target device without an external debugger. EDBG also brings additional
features with a Data Gateway Interface (DGI) and a Virtual COM Port for streaming of data to a host PC. The
Atmel EDBG will enumerate as a composite USB device with separate interfaces for each function.
The Atmel EDBG is embedded on all Xplained Pro evaluation kits. All functionality of the Atmel EDBG is not
necessarily available on all kits - the EDBG is factory configured depending on the specific kit capabilities.
The configuration is read by Atmel Studio to present the correct capabilities and simplify the user interface.
Supported extension boards connected to the kit will be detected by the EDBG and their features are reported
to Atmel Studio.
1.1
Features
●
On-board programming and debugging through SWD, JTAG and PDI
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Virtual COM Port interface to target via UART
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Data Gateway Interface (DGI) for data streaming between target MCU and PC
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SPI, USART and TWI interfaces available
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GPIOs for accurate status indication
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Extension board identification
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Indication of power and status through LEDs
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Sleep mode to minimize power consumption
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2.
Programming and Debugging
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The Atmel EDBG has the ability to program and debug Atmel AVR and Atmel ARM Cortex -M core based
microcontrollers. The following interfaces are supported:
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Atmel ARM Cortex-M programming and debug interfaces
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Atmel megaAVR programming and debug interfaces
●
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Serial Wire Debug (SWD)
JTAG
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Atmel AVR XMEGA programming and debug interfaces
●
Program and Debug Interface (PDI)
Refer to the specific kit's user guide for details on connecting the interface.
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3.
Virtual COM Port
The EDBG features a CDC class USB interface that implements a Virtual COM Port. A UART connected to a
target device is used to enable easy communication between a computer and the target.
The following configuration options are implemented
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Baud Rate: Flexible and accurate settings up to 2Mbps
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Parity: None, Even, Odd, Mark, Space
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Stop Bits: 1 bit, 1.5 bits, 2 bits
The configuration options must be specified in the terminal application, which will propagate the configuration
to the EDBG Virtual COM Port on connection. The target MCU UART must be configured to match the Virtual
COM Port.
Note that the UART pins of the EDBG are tri-stated when no terminal program is connected to the Virtual COM
Port on the computer. This mechanism relies on the terminal program sending a DTR signal.
The Virtual COM Port is supported by the terminal extension in Atmel Studio. Most other terminal applications
will work as well.
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4.
Data Gateway Interface
The Atmel EDBG features an interface for streaming data from the target device to a computer, called the Data
Gateway Interface (DGI). This is meant as an aid in debugging and demonstration of features in the application
running on the target device.
DGI consists of multiple channels for data streaming. The available channels are listed in the sections below.
Note that not all interfaces need to be implemented on all kits, and that different kits can implement a different
subset of these interfaces. Refer to the specific kit's user guide for details.
4.1
SPI Interface
The Serial Peripheral Interface (SPI) is connected to the EDBG DGI through four digital signals; MOSI, MISO,
SCK and CS. The EDBG SPI is set to operate in slave mode, meaning that the target device must be set to
master mode. The active low CS (Chip Select) line indicates to the EDBG SPI that it should expect data to be
received and/or sent. If the master expects to receive data from the slave EDBG DGI, it must poll for them by
initiating a transfer. All pins are tri-stated until the interface is activated from the PC and the CS line is driven
low.
It is possible to configure the mode (clock phase and data setup) of the SPI module. Valid settings are 0-3. The
bit count for each transfer can also be set between 5 and 8 bits per transfer.
In normal operation, DMA will automatically buffer incoming data transfers. It is also possible to enable
timestamping to get a more accurate timing of incoming data. Note that the timestamping will add an overhead
to each data transfer, and a lower maximal throughput and a longer required inter-byte delay is expected. For
sending data to the target device DMA is always used.
4.2
USART Interface
The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) interface is connected to the EDBG
DGI through three digital signals; RX, TX and XCK. All pins are tri-stated until the interface is activated from the
PC.
Both synchronous and asynchronous modes are supported. If operated in asynchronous mode, the correct
baud rate setting must be supplied. The baud rate is flexible and is accurate up to 2Mbps. Supported parity
settings are none, even, odd, mark and space. Stop bit can be set to 1, 1.5 and 2 stop bits. It is possible to use
a transfer size of 5-8 bits. If used in synchronous mode, a clock signal must be supplied by the target device.
In normal operation, DMA will automatically buffer incoming data transfers. It is also possible to enable
timestamping to get a more accurate timing of incoming data. Note that the timestamping will add an overhead
to each data transfer, and a lower maximal throughput and a longer requred inter-byte delay is expected. For
sending data to the target device DMA is always used.
4.3
TWI Interface
The Two-Wire Interface (TWI) is connected to the EDBG DGI through two signals; SDA and SCL. The two-wire
interface of the EDBG is set to slave mode, meaning that communication must be initiated by a target device in
master mode. The interface must be enabled from the PC before communication can begin.
The slave address of the TWI interface can be configured, but is default set to 0x28.
Communication from the target device to the EDBG DGI is done by sending the slave address with the write
bit, followed by the data bytes. The master must poll the EDBG DGI for data by sending the slave address with
the read bit. Then the EDBG DGI will send a 1 byte length, directly followed by the data.
4.3.1
Information Interface
The TWI-bus can be used to request information from the EDBG. This is done by sending a special sequence
as described below.
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START Condition
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Address + W
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Request token
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START Condition (repeated start)
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Address + R
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●
Response
●
...
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STOP Condition
The sequence starts by sending a normal start condition followed by an address byte (default address is
0x28) with the RW bit cleared. Then a request token identifying the requested information is sent. Normally, a
received byte would be put into the DGI buffer, but a repeated start will trigger the EDBG to parse the received
token. Then an address with the RW bit set. The EDBG will then start to push the requested data onto the TWIbus. All response bytes must be ACKed by the master, and the final byte must be NAKed.
4.3.1.1
Extension Boards
Token: 0xE1
The EDBG has 10 pins designated for extension board identification. These pins are sampled on power-up
and the extension board identification information is stored. This information can be retrieved by using the
Extension Boards token.
The first part of the response from this request is a 2 byte BE (1st byte is MSB) extension map containing
information of which extension slots are populated. A '1' in bit 0 of the extension map means that EXT1 is
populated, a '0' means not populated. If there are extension modules present the 64 byte content of each of the
ID chips are sent. It will start with EXT1, if the extension is present it will send the content, otherwise no data is
sent.
Example: Extension boards are available in EXT2 and EXT5. The response will be
4.3.1.2
●
0x00 (Extension map MSB)
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0x12 (Extension map MSB)
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0x41 'A' (First byte in EXT2 ID content)
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0x74 't' (Second byte)
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0x6D 'm' (Third byte)
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0x65 'e' (Fourth byte)
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0x6C 'l' (Fifth byte)
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0x53 'S' (Sixth byte)
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... Remaining 58 bytes
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0x41 'A' (First byte in EXT5 ID content)
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0x74 't' (Second byte)
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0x6D 'm' (Third byte)
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... Remaining 61 bytes
●
0x00 (End of data)
Kit Data
Token: 0xD2
The EDBG has 256 bytes for storing kit-specific data such as MAC address, calibration values etc. See the kit
documentation for details on how the data is organized. The information can be retrieved by using the Kit Data
token. Note that not all kits have kit-specific data, and the entire section will read as 0.
After sending the token, the stored kit-specific data will be sent byte by byte starting with location 0, until a stop
condition is detected.
4.4
GPIO Interface
Up to four General Purpose Input/Output (GPIO) signals are connected to the EDBG DGI. In input mode, they
can be used as a status indication from the target device. In output mode, they can be used as virtual control
signals to simulate buttons.
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The GPIO interface is always timestamped. It is only useful for signals with a relatively slow toggle rate
(<250kHz).
4.5
Timestamp module
Data received on DGI Interfaces can be routed through the timestamp module to embed timing references into
the data stream. The timestamp is implemented as a counter which increments in steps of (32/60) µs, giving a
timestamp accuracy of about half a microsecond.
The timestamp module does not use DMA since it requires CPU intervention on each data unit received. This
implies a lower maximum data throughput and demands a larger delay between each data unit.
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5.
Technical Overview
5.1
Pin Usage
All pins that are not in use on the EDBG, will be tri-stated. This is done to avoid signal contention. Note that the
tri-stating of serial communication lines and external interference could lead to unintended data to be received
by the target MCU.
5.2
Power Consumption
During enumeration, the EDBG reports a current consumption of 500mA, and must therefore be connected to
a USB host that is capable of supplying this. It is impossible to predict the amount of current required by the
setup, since the EDBG is a part of a flexible evaluation kit.
The EDBG alone consumes approximately 100mA during usage. When the EDBG does not detect a VBUS
voltage, but is otherwise powered (for example through the Xplained Pro PWR header), the EDBG will go into
sleep to minimize power consumption. The power consumption during sleep mode will vary with the design, but
should be well below 1mA.
5.3
LED Control
The EDBG controls two LEDs, the power LED and the status LED. The power LED is on by default when the
kit is powered, but can be disabled by the EDBG to lower the power consumption of the kit. The status LED is
turned on when a host computer opens a connection the the USB interface. During communication activity the
status LED will flash.
If the EDBG enters bootloader mode, both the status LED and the power LED will flash simultaneously. When a
firmware upgrade is in progress the LEDs will blink alternately.
The behavior of the EDBG LEDs is summarized in Table 5-1, “EDBG LED control” on page 9.
Table 5-1. EDBG LED control
Operation mode
Power LED
Status LED
Normal operation
Power LED is lit when power is
applied to the board.
Activity indicator, LED flashes
every time something happens on
the EDBG.
Bootloader mode (idle)
The power LED and the status LED blinks simultaneously.
Bootloader mode (firmware
upgrade)
The power LED and the status LED blinks in an alternating pattern.
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6.
Document Revision History
Document
revision
Date
Comment
42096B
02/2014
Added details about TWI info interface
42096A
02/2013
First release
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Atmel Corporation
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© 2014 Atmel Corporation. All rights reserved. / Rev.: 42096B-MCU-02/2014
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