MSC_CXE_CD945_UserManual.
User’s Manual
MSC CXE-CD945
MSC COM Express™ Extended Module
Rev. 0.5
Februar 8th , 2010
MSC CXE-CD945 User's Manual
Technical Description
Preface
Copyright Notice
Copyright © 2008 MSC Vertriebs GmbH. All rights reserved.
Copying of this document, and giving it to others and the use or communication of the
contents thereof, are forbidden without express authority. Offenders are liable to the payment
of damages.
All rights are reserved in the event of the grant of a patent or the registration of a utility model
or design.
Important Information
This documentation is intended for qualified audience only. The product described herein is
not an end user product. It was developed and manufactured for further processing by
trained personnel.
Disclaimer
Although this document has been generated with the utmost care no warranty or liability for
correctness or suitability for any particular purpose is implied. The information in this
document is provided “as is” and is subject to change without notice.
EMC Rules
This unit has to be installed in a shielded housing. If not installed in a properly shielded
enclosure, and used in accordance with the instruction manual, this product may cause radio
interference in which case the user may be required to take adequate measures at his or her
own expense.
Trademarks
All used product names, logos or trademarks are property of their respective owners.
Certification
MSC Vertriebs GmbH is certified according to DIN EN ISO 9001:2000 standards.
Life-Cycle-Management
MSC products are developed and manufactured according to high quality standards. Our lifecycle-management assures long term availability through permanent product maintenance.
Technically necessary changes and improvements are introduced if applicable. A productchange-notification and end-of-life management process assures early information of our
customers.
Product Support
MSC engineers and technicians are committed to provide support to our customers
whenever needed.
Before contacting Technical Support of MSC Vertriebs GmbH, please consult the respective
pages on our web site at www.msc-ge.com/support-boards for the latest documentation,
drivers and software downloads.
If the information provided there does not solve your problem, please contact our Technical
Support:
Email: [email protected]
Phone: +49 8165 906-200
2
MSC CXE-CD945 User's Manual
Technical Description
Contents
1
2
3
4
5
General Information ........................................................................................................................................ 5
1.1
Revision History...................................................................................................................................... 5
1.2
Reference Documents ............................................................................................................................. 5
1.3
Introduction ............................................................................................................................................. 6
Technical Description ..................................................................................................................................... 7
2.1
Key features ............................................................................................................................................ 7
2.2
Block diagram ......................................................................................................................................... 8
2.3
COM Express implementation ................................................................................................................ 9
2.4
Functional units ..................................................................................................................................... 10
2.5
Power Supply ........................................................................................................................................ 12
2.6
Power dissipation .................................................................................................................................. 12
2.7
Mechanical Dimensions ........................................................................................................................ 13
2.8
Cooling solution .................................................................................................................................... 15
2.9
Signal description .................................................................................................................................. 16
2.9.1
AC97 Audio / High Definition Audio ..................................... Fehler! Textmarke nicht definiert.
2.9.2
Ethernet ................................................................................... Fehler! Textmarke nicht definiert.
2.9.3
IDE ................................................................................................................................................ 17
2.9.4
Serial ATA .................................................................................................................................... 18
2.9.5
PCI Express Lanes x1 ................................................................................................................... 19
2.9.6
PCI Express Lanes x16 ................................................................................................................. 19
2.9.7
Express Card Support .................................................................................................................... 20
2.9.8
PCI Bus ......................................................................................................................................... 20
2.9.9
USB ............................................................................................................................................... 22
2.9.10
LVDS Flat Panel ........................................................................................................................... 22
2.9.11
LPC Bus ....................................................................................................................................... 23
2.9.12
Analogue VGA.............................................................................................................................. 23
2.9.13
TV Out .......................................................................................................................................... 24
2.9.14
SVDO ............................................................................................................................................ 24
2.9.15
Miscellaneous ................................................................................................................................ 25
2.9.16
Power and System Management ................................................................................................... 26
2.9.17
General Purpose I/O ...................................................................................................................... 27
2.9.18
Module Type Definition ................................................................................................................ 27
2.9.19
Power and GND ............................................................................................................................ 28
2.10 Pin List for MSC 945GM module (Type 2) .......................................................................................... 29
Watchdog ...................................................................................................................................................... 31
System resources ........................................................................................................................................... 32
4.1
PCI Devices CXE-945 .......................................................................................................................... 32
4.2
Carrier Board PCI Resource Allocation ................................................................................................ 33
4.3
SMB Address Map ................................................................................................................................ 34
BIOS ............................................................................................................................................................. 35
5.1
Introduction ........................................................................................................................................... 35
5.1.1
Startup Screen Overview ............................................................................................................... 35
5.1.2
Activity Detection Background ..................................................................................................... 35
5.2
TrustedCore Setup Utility ..................................................................................................................... 36
5.2.1
Configuring the System BIOS ....................................................................................................... 36
5.2.2
The Main Menu ............................................................................................................................. 39
5.2.2.1
Board Information ............................................................................................................... 39
5.2.2.2
Masters & Slaves ................................................................................................................ 40
5.2.2.3
Boot Options ........................................................................................................................ 41
5.2.2.4
Keyboard Features ............................................................................................................. 41
5.2.3
The Advanced Menu ..................................................................................................................... 42
5.2.3.1 Cache Memory Control Menu ................................................................................................... 43
5.2.3.2 Yonah / Merom CPU Control Sub-Menu .................................................................................. 43
5.2.3.3 MCH Control Sub-Menu ........................................................................................................... 45
5.2.3.4 Video (Intel IGD) Control Sub-Menu ....................................................................................... 46
5.2.3.5 ICH Control Sub Menu ............................................................................................................. 47
5.2.3.5.1 PCI Express Control Sub-Menu .......................................................................................... 49
5.2.3.5.2 PCI Control Sub-Menu ....................................................................................................... 50
5.2.3.5.3 ICH USB Control Sub-Menu .............................................................................................. 51
3
MSC CXE-CD945 User's Manual
Technical Description
5.2.3.6 ACPI Control Sub-Menu ........................................................................................................... 52
5.2.3.7 I/O Device Configuration Menu ................................................................................................ 53
5.2.3.8 Watchdog Options ..................................................................................................................... 54
5.2.4
The Security Menu ........................................................................................................................ 55
5.2.5
The Power Menu ........................................................................................................................... 56
5.2.5.1
Hardware Monitoring Menu ............................................................................................... 56
5.2.6
The Boot Menu ............................................................................................................................. 57
5.2.7
The Exit Menu............................................................................................................................... 58
5.3
Bios Update ........................................................................................................................................... 59
5.4
Bios Crisis Recovery ............................................................................................................................. 60
5.5
Diagnostics Postcodes ........................................................................................................................... 62
5.5.1
Bootblock Bios Postcodes ............................................................................................................. 62
5.5.2
System Bios Postcodes .................................................................................................................. 63
5.5.3
Memory Detection Postcodes ........................................................................................................ 66
5.5.4
ACPI Postcodes ............................................................................................................................. 66
4
MSC CXE-CD945 User's Manual
Technical Description
1 General Information
1.1 Revision History
Rev.
0.1, 0.2
0.3
0.4
0.5
Date
2007-08-23
2008-03-20
2010-02-02
2010-02-08
Description
Initial version (wst)
Preface added
Bios chapter updated
Updated PCI Resource Table
1.2 Reference Documents
[1] COM Express Module Base Specification
COM Express Revision 1.0
Last update: July 10th, 2005
[2] PCI Local Bus Specification Rev. 2.1
PCI21.PDF
Last update: June 1st, 1995
http://www.pcisig.com
[3] ATA/ATAPI-6 Specification
d1410r3b.pdf
http://www.t13.org/
[4] Serial ATA Specification
Serial ATA 1.0 gold.pdf
Last update: August 29th, 2002 Rev.1.0
http://www.sata-io.org/
[5] IEEE Std. 802.3-2002
802.3-2002.pdf
http://www.ieee.org
[6] Universal Bus Specification
usb_20.pdf
Last update: April 27th, 2000
http://www.usb.org
5
MSC CXE-CD945 User's Manual
Technical Description
1.3 Introduction
COM Express™, an open specification of the PICMG (PCI Industrial Computer
Manufacturer Group), is a module concept to bring PCI Express and other latest
technologies like SATA, USB 2.0 and LVDS on a COM (Computer On Module).
A COM Express™ module is plugged onto an application-specific base board similar to
the ETX concept, but offers more options and a growth path to future CPU technologies.
Utilizing different sizes, COM Express™ can be used for highly embedded solutions up
to high performance platforms.
The design of the MSC CXE-CD945 module supports the dual core CPU technology
enabling you to boost your embedded application to highest performance levels. For low
power requirements we also support the LV-version in a single core configuration.
For evaluation and design-in of the COM Express™ modules we provide evaluation
baseboards and develop motherboards providing the interface infrastructure for the
COM Express™ module offering PC type connectors for external access.
Two module sizes are defined: the Basic Module and the Extended Module. The primary
difference between the Basic Module and the Extended Module is the over-all physical
size and the performance envelope supported by each. The Extended Module is larger
and can support larger processor and memory solutions. The Basic Module and
Extended Module use the same connectors and pin-outs and utilize several common
mounting hole positions. This level of compatibility allows that a carrier board designed
to accommodate an Extended Module can also support a Basic Module.
The MSC CXE-CD945 is a COM Express Extended Module.
Up to 440 pins of connectivity are available between COM Express™ modules and the
Carrier Board. Legacy buses such as PCI, parallel ATA, LPC, AC'97 are supported as
well as new high speed serial interconnects such as PCI Express, Serial ATA and
Gigabit Ethernet.
To enhance interoperability between COM Express™ modules and Carrier Boards, five
common signalling configurations (Pin-out Types) have been defined to ease system
integration.
6
MSC CXE-CD945 User's Manual
Technical Description
2 Technical Description
2.1 Key features
The MSC 945GM COM Express Extended module is designed as a type 2 module.
Key features include

Module size: 155 mm x 110 mm

40 mm „z‟ height with fanless cooling solution (see 2.8 , 5 mm stack option)

52 mm „z‟ height with cooling solution with fan (see 2.8 , 5 mm stack option)

Dual 220 pin connector (440 pins)

2 DDR2 SO-DIMM modules (dual channel memory)

8 USB 2.0 ports; 4 shared over-current lines

2 Serial ATA or SAS ports

4 PCI Express x1 lanes

Support pins for up to 2 ExpressCards

One dual 24-bit LVDS channel

Analog VGA

AC '97 / High definition digital audio interface (external CODEC)

Single Ethernet interface with integrated PHY (Gigabit Ethernet option available)

LPC interface

8 GPIO pins

+12V primary power supply input

+5V standby and 3.3V RTC power supply inputs

32 bit PCI interface

IDE port (to support legacy ATA devices such as CD-ROM drives and Compact
Flash storage cards)

20 PCI Express lanes (4 on A-B and 16 on C-D)

16 of 20 PCI Express lanes used for PCI Express Graphics

SDVO option (pins shared with PCI Express Graphics)

TPM module (option, TPM 1.2, SLB9635)
7
+3.3V +5V_SBY +12V
BAT
8
2.5V
A
B
C
CTRL
PCIeG
x16
LVDS
MUX
PCI
COMExpressModuleConnectorsA/B, C/D
8x
USB2.0
1.8V
RTC
SMB
W
83L786R
TPM
GigaBitLAN
i82573L
FW
H
BIOS
VCC5V_A
AT24C04AN
CMOSBackup
VREF 0.9V
ExpressCard
Support
i82256EZ
PHY
+
SYS_RESET_MB#, PLT_RST#, KBD_RST#, KBD_A20GATE, SPKR, WAKE[0:1]#,
I2C-BUS
SMBUS
WDSTS
DDR2
CH.A
I2C
HW-Mon.
CY284112XC
EXCD[0:1]_PPE#, EXCD[0:1]_PERST#
MISC
VCC5V_A
PCIE_RX[0:2]+/-, PCIE_TX[0:2]+/-
Intel®82801GBM
I/OController Hub
ICH7-M
4 x PCIe x1
VCC3V3_SUS
VCC5V_SUS
VBAT
CLK-Gen.
PCIE_RX3+/-, PCIE_TX3+/-
GPIO
LPC
PM
SDVO
PSW
LCI
B
Debug
VID[6:0]
BIOS_DISABLE#
VGA
FCBGA479
SUS_STAT#, PM_S[3:5]#, PM_BATLOW#, THRMTRP_EXT#
GPI[0:3], GPO[0:3], EXT_THRM#
LPC BUS
3.3V
HDA/AC97
VCC5V_SBY
AC'97 LINK
1.05V
2x
SATA
PATA
1.50V
SATA_RX[0:1]+/-, SATA_TX[0:1]+/1 x EIDE
DDR2
CH.B
MobileIntel®945GM
ExpressChipset
DMI
VCC3V3_SUS
USB[0:7]+/4 x USB_OC#
667MHz
Intel®
Celeron®M
CoreDuo®
Core2Duo®
32-Bit PCI BUS
VCC2V5
667MHz
1.50V
DMI
VCCA
PEG_LANE_RV#
3.3V
DDR2
SO-DIMM
1.05V
PEG_RX[0:15]+/-
VCC3V3
0.9V
VCCP
PEG_TX[0:15]+/-
1.8V
VTT
VCore
SDVO_I2C
1.8V
VCC
LVDS_B[0:2]+/-, LVDS_B_CLK+/BLKT_CTRL, VDD_EN
LVDS_I2C
VCCSM
DDR2
SO-DIMM
Termination
VCC12V
LVDS_A[0:2]+/-, LVDS_A_CLK+/-
1.8V
Termination
VCC3V3_SUS
R, G, B, HSYNC, VSYNC
DDC_CLK, DDC_DATA
PWRBTN#, EXTPWR_OK
VCC12V
VCC12V
VCC12V
VCC5V_SBY
VBAT
MSC CXE-CD945 User's Manual
Technical Description
2.2 Block diagram
1.05V
VCC5V_A
VCC5V_SBY
VCC12V
PIC12F509A-04
Watchdog
FSB
SMBUS
SMBUS
MSC CXE-CD945 User's Manual
Technical Description
2.3 COM Express implementation
COM Express™ required and optional features of pin-out type 2 are summarized in the
following table. The features identified as Minimum (Min.) shall be implemented by all
modules. Features identified up to Maximum (Max) may be additionally implemented by
a module.
The column MSC 945GM shows the implemented features of the MSC module:
Type 2
MSC 945GM
Note
Min / Max
System I/O
PCI Express Graphics (PEG)
0/1
1
signals are multiplexed with
SDVO signals
PCI Express Lanes 0 - 5
2/6
4 x1
one lane optionally reserved
for GBit LAN
PCI Express Lanes 16-31
0 / 16
1 x16
off-module x16 PCI Express
Graphics
SDVO Channels
0/2
2
signals are multiplexed with
PEG signals
LVDS Channels
0/2
2
1x dual channel, 2x24 Bit
VGA Port
0/1
1
TV-Out
0/1
0
PATA Port
1/1
1
SATA Ports
2/4
4
AC‟97 Digital Interface
0/1
1
USB 2.0 Ports
4/8
8
LAN 0 (10/100Base-T min)
1/1
1
PCI Bus - 32 Bit
1/1
1
Express Card Support
1/2
1
LPC Bus
1/1
1
General Purpose Inputs
4/4
4
General Purpose Outputs
4/4
4
(same as PEG pins)
System Management
9
not implemented
AC97 or High Definition Audio
GBit option available
SMBus
1/1
1
I2C
1/1
1
Watch Dog Timer
0/1
1
Speaker Out
1/1
1
External BIOS ROM support
0/1
1
Reset Functions
1/1
1
Thermal Protection
0/1
1
Battery Low Alarm
0/1
1
Suspend
0/1
1
Wake
0/2
2
Power Button Support
1/1
1
Power Good
1/1
1
TPM
0/0
1
Power Management
optional TPM 1.2 module
2.4 Functional units
CPUs
Intel® Celeron® M 440 (Yonah,1.86 GHz, FSB 533MHz, 479µFCBGA)
Intel® Core™ Duo L2400 (Yonah, Low Voltage, 1.66 GHz, FSB
667MHz, 479µFCBGA)
Intel® Core™ 2 Duo L7400 (Merom, 1.5 GHz, FSB 667MHz,
479µFCBGA)
Chipset
Intel® 82945GM GMCH (Graphics Memory Controller Hub)
Intel® ICH7-M I/O Controller Hub
Memory
Dual channel architecture for best performance
2 200-pin SO-DIMM sockets for up to a total of 4GB DDR2 SDRAM
PC2-4200 (DDR533, Celeron M) or PC2-5300 (DDR667, Core™
Duo )
DDR2 SO-DIMM modules (max. height 1250mil = 31.75mm)
SATA
2 SATA-2 channels up to 300MB/s each
EIDE
1 Enhanced IDE port ATA/UDMA100
USB
8 x USB 2.0
COM Express™
Type 2 interface, fully compliant
PCI Express™
Four channels, PCIe x1, one channel shared with GBit Ethernet option
10
PCI
32 Bit standard interface
LPC
Low Pincount Bus for heritage interfaces
Graphics
Controller
Intel® Graphics Media Accelerator 950 (integrated in Intel® 945GM
chipset)
Video Memory
UMA, up to 224 MB
LCD Interface
LVDS 2x24Bit, dual channel, max. resolution 1.600 x 1.200
SDVO Interface
2 independent SDVO interfaces (SDVOB, SDVOC) or
external PCIe x16 graphics (multiplexed by Intel® Graphics Media
Accelerator 950)
CRT Interface
max. resolution 2.048 x 1.536
Ethernet
10/100Base-TX (Intel® 82562EZ) controller or
10/100/1000Base-TX (Intel® 82573E)
Sound Interface
AC97 / High Definition Audio Interface
Watchdog Timer
PIC12C509A
Creates system reset (programmable, 1s … 255h)
TPM (option)
Optional TPM module, TPM 1.2, SLB9635
Fan Supply
3-pin header (12V)
Real Time Clock
(RTC)
integrated in ICH7-M
Battery
External
System
Monitoring
Voltage , Temperature , Fan

Core voltage

3.3V

1.5V

0.9V

2.5V

CPU thermal diode
11
2.5 Power Supply
+12V primary power supply input
+5V standby
Option, is not required for module operation.
If not present, there is no support for power management states and ATX power supply
functionality.
3.3V RTC power supply
Option, is not required for module operation.
BIOS SETUP data is stored in a non volatile backup memory device (EEPROM),
therefore configuration data will not get lost during power off (except for time and date
information)
Voltage
Input range
Current
+12V
+11.4V - 12.6 V
See next table
+5V Standby
+4.75V - 5.25 V
tbd
+2.0V - 3.3V
max. 6µA
+3V RTC power supply
2.6 Power dissipation
DOS Prompt, 2x 512MB DDR2 SO-DIMM
Module (CPU)
Voltage (V)
Watt (typ.)
Intel® Celeron® M 440 (Yonah,1,86 GHz)
+12V
16 W
Intel® Core™ Duo L2400
(Yonah, Low Voltage, 1.66 GHz)
+12V
18 W
Intel® Core™ 2 Duo L7400
(Merom, Low Voltage 1,5 GHz)
+12V
19 W
INTEL Thermal Analysis Tool (TAT 2.05) , 80% workload, all cores active
Module (CPU)
Voltage (V)
Watt (typ.)
Intel® Celeron® M 440 (Yonah,1,86 GHz)
+12V
20.4 W
Intel® Core™ Duo L2400
(Yonah, Low Voltage, 1.66 GHz)
+12V
26.2 W
Intel® Core™ 2 Duo L7400
(Merom, Low Voltage 1,5 GHz)
+12V
26.5 W
12
2.7 Mechanical Dimensions
Extended Module
MSC CXE CD945 Top view
13
MSC CXE CD945 Bottom view
14
2.8 Cooling solution
A special cooling solution is available for the CXE CD945 module.
optional with fan :
15
2.9 Signal description
Pins are marked in the following tables with the power rail associated with the pin, and
for input and I/O pins, with the input voltage tolerance. The pin power rail and the pin
input voltage tolerance may be different. For example, the PCI group is defined as
having a 3.3V power rail, meaning that the output signals will only be driven to 3.3V, but
the pins are tolerant of 5V signals.
An additional label, “Suspend” indicates that the pin is active during suspend states
(S3,S4,S5). If suspend modes are used, then care must be taken to avoid loading
signals that are active during suspend to avoid excessive suspend mode current draw.
Signals with a # symbol at the end indicate that their active state is a low voltage level .
Signals names without # are asserted active when their voltage level is high.
2.9.1 AC97 Audio / High Definition Audio
AC97 Audio / High Pin Type
Definition Audio
AC_RST#
O
Pwr Rail /
Tolerance
MSC
945GM
device
3.3V
/3.3V Reset output to AC97 CODEC,
active low.
Suspend
CMOS
AC_SYNC
O
CMOS
3.3V
AC_BITCLK
I/O
CMOS
3.3V/
AC_SDOUT
O
CMOS
I
3.3V/
AC_SDIN[0:2]
Description
3.3V/
CMOS
/3.3V 48kHz fixed-rate, samplesynchronization signal to the
CODEC(s).
3.3V 12.228 MHz serial data clock
generated by the external
CODEC(s).
3.3V Serial TDM data output to the
CODEC.
3.3V
ICH7-M
ICH7-M
ICH7-M
ICH7-M
Serial TDM data inputs from up to ICH7-M
3 CODECs.
Suspend
2.9.2 Ethernet
(Gigabit)
Ethernet
Pin
Type
GBE0_MDI[0
I/O
:3]+
Analog
GBE0_MDI[0
:3]-
Pwr Rail /
Tolerance
3.3V max
Suspend
Description
MSC
945GM
device
Gigabit Ethernet Controller 0: Media
Depends
Dependent Interface Differential Pairs 0,1,2,3. on LAN
The MDI can operate in 1000, 100 and 10
option,
Mbit / sec modes. Some pairs are unused in
82573 or
some modes, per the following:
82562
82573
82562
1000BASE-T 100BASE- 10BASETX
T
MDI[0]+/MDI[1]+/MDI[2]+/MDI[3]+/-
16
B1_DA+/B1_DB+/B1_DC+/B1_DD+/-
TX+/RX+/-
TX+/RX+/-
GBE0_ACT#
GBE0_LINK#
GBE0_LINK1
00#
GBE0_LINK1
000#
GBE0_CTRE
F
2.9.3
OD
CMOS
OD
CMOS
OD
CMOS
OD
CMOS
REF
3.3V /3.3V
Suspend
Gigabit Ethernet Controller 0 activity indicator,
active low.
82573 /
82562
3.3V / 3.3V
Suspend
Gigabit Ethernet Controller 0 link indicator,
active low.
82573 /
82562
3.3V / 3.3V
Suspend
Gigabit Ethernet Controller 0 100 Mbit / sec
link indicator, active low.
82573 /
82562
3.3V / 3.3V
Suspend
Gigabit Ethernet Controller 0 1000 Mbit / sec
link indicator, active low.
82573 /
82562
82562 ( 100MBit) : floating
82573 (1000MBit) : 2,5V
82573 /
82562
GND min
3.3V max
IDE
IDE
Pin
Type
Pwr Rail /
Tolerance
Description
IDE_D[0:15]
I/O
CMOS
3.3V / 5V
IDE_A[0:2]
O
CMOS
3.3V / 3.3V Address lines to IDE device.
ICH7-M
IDE_IOW#
O
CMOS
3.3V / 3.3V I/O write line to IDE device.
Data latched on trailing (rising) edge.
ICH7-M
IDE_IOR#
O
CMOS
3.3V / 3.3V I/O read line to IDE device.
ICH7-M
IDE_REQ
I
CMOS
IDE_ACK#
O
CMOS
IDE_CS1#
O
Bidirectional data to / from IDE device.
3.3V / 5V
MSC
945GM
device
ICH7-M
IDE Device DMA Request.
It is asserted by the IDE device to request a
data transfer.
3.3V / 3.3V IDE Device DMA Acknowledge.
ICH7-M
3.3V / 3.3V IDE Device Chip Select for 1F0h to 1FFh
range.
ICH7-M
3.3V / 3.3V IDE Device Chip Select for 3F0h to 3FFh
range.
ICH7-M
ICH7-M
CMOS
IDE_CS3#
O
CMOS
IDE_IORDY
I
CMOS
3.3V / 5V
IDE device I/O ready input.
Pulled low by the IDE device to extend the
cycle.
3.3V / 3.3V Reset output to IDE device, active low.
IDE_RESET#
O
CMOS
IDE_IRQ
I
CMOS
3.3V / 5V
Interrupt request from IDE device.
IDE_CBLID#
I
CMOS
3.3V / 5V
Input from off-module hardware indicating the ICH7-M
type of IDE cable being used. High indicates
a 40-pin cable used for legacy IDE modes.
Low indicates that an 80-pin cable with
interleaved grounds is used. Such a cable is
required for Ultra-DMA 66, 100 and 133
modes.
17
ICH7-M
ICH7-M
ICH7-M
2.9.4 Serial ATA
Serial ATA
Pin
Type
SATA0_TX+
O
SATA0_TX-
SATA
SATA0_RX+
I
SATA0_RX-
SATA
SATA1_TX+
O
SATA1_TX-
SATA
SATA1_RX+
I
SATA1_RX-
SATA
SATA2_TX+
O
SATA2_TX-
SATA
SATA2_RX+
I
SATA2_RX-
SATA
SATA3_TX+
O
SATA3_TX-
SATA
SATA3_RX+
I
SATA3_RX-
SATA
ATA_ACT#
O
Pwr Rail /
Tolerance
Description
MSC 945GM
device
AC coupled Serial ATA or SAS Channel 0 transmit
differential pair.
on module
ICH7-M
AC coupled Serial ATA or SAS Channel 0 receive
differential pair.
on module
ICH7-M
AC coupled Serial ATA or SAS Channel 1 transmit
differential pair.
on module
ICH7-M
AC coupled Serial ATA or SAS Channel 1 receive
differential pair.
on module
ICH7-M
AC coupled Serial ATA or SAS Channel 2 transmit
differential pair.
on module
not
supported
AC coupled Serial ATA or SAS Channel 2 receive
differential pair.
on module
not
supported
not
supported
not
supported
not
supported
not
supported
not
supported
ICH7-M
AC coupled Serial ATA or SAS Channel 3 transmit
differential pair.
on module
AC coupled Serial ATA or SAS Channel 3 receive
differential pair.
on module
3.3V / 3.3V ATA (parallel and serial) or SAS activity
indicator, active low.
CMOS
(SATALED#)
18
2.9.5 PCI Express Lanes x1
PCI Express
Lanes
Pin
Type
Pwr Rail /
Tolerance
Description
MSC 945GM
device
(Gen. Purpose)
PCIE_TX[0:3]+
O
PCIE_TX[0:3]-
PCIE
PCIE_RX[0:3]+
I
PCIE_RX[0:3]-
PCIE
PCIE_TX[4:5]+
O
PCIE_TX[4:5]-
PCIE
PCIE_RX[4:5]+
I
PCIE_RX[4:5]-
PCIE
PCIE_TX[16:31]+
O
PCIE_TX[16:31]-
PCIE
PCIE_RX[16:31]
+
PCIE_RX[16:31]-
I
PCIE
PCIE_CLK_REF
O
+
CMOS
PCIE_CLK_REF-
AC coupled PCI Express Differential Transmit Pairs 0
through 3
on module (0 through 2 with GigaBit Option)
ICH7-M
AC coupled PCI Express Differential Receive Pairs 0
through 3
off module (0 through 2 with GigaBit Option)
ICH7-M
AC coupled PCI Express Differential Transmit Pairs 4
through 5
on module
not
supported
not
supported
not
supported
not
supported
945GM
AC coupled PCI Express Differential Receive Pairs 4
through 5
off module
AC coupled PCI Express Differential Transmit Pairs 16
through 31
on module These are same lines as PEG_TX[0:15]+
and AC coupled PCI Express Differential Receive Pairs 16
through 31
off module These are the same lines as
PEG_RX[0:15]+ and 3.3V / 3.3V Reference clock output for all PCI Express
and
PCI Express Graphics lanes.
GMCH
945GM
GMCH
CY28411
2.9.6 PCI Express Lanes x16
PCI Express
Pin
Type
Pwr Rail /
Tolerance
PEG_TX[0:15]+
PEG_TX[0:15]-
O
PCIE
PEG_RX[0:15]+
PEG_RX[0:15]-
I
PCIE
AC coupled PCI Express Graphics transmit differential
on module pairs.
Some of these are multiplexed with SDVO
lines (see SDVO section).
These are the same lines as
PCIE_TX[16:31]+ and - in module pin-out
types 4 and 5.
AC coupled PCI Express Graphics receive differential
off module pairs.
Some of these are multiplexed with SDVO
lines (see SDVO section).
These are the same lines as
PCIE_RX[16:31]+ and - in module pin-out
types 4 and 5.
Lanes
Description
MSC 945GM
device
x16 Graphics
19
945GM
GMCH
945GM
GMCH
PEG_LANE_RV#
I
CMOS
PEG_ENABLE#
I
CMOS
3.3V / 3.3V PCI Express Graphics lane reversal input
strap. Pull low on the carrier board to
reverse lane order. Be aware that the
SDVO lines that share this interface do not
necessarily reverse order if this strap is
low.
3.3V / 3.3V Strap to enable PCI Express x16 external
graphics interface. Pull low to disable
internal graphics and enable the x16
interface.
945GM
GMCH
(CFG9)
ICH7-M
(GPI3)
2.9.7 Express Card Support
ExpressCard
Support
Pin
Type
EXCD[0]_CPPE#
I
I
CMOS
EXCD[1]_CPPE#
I
I
CMOS
EXCD[0]_RST#
O
CMOS
EXCD[1]_RST#
O
CMOS
Pwr Rail /
Tolerance
Description
MSC 945GM
device
3.3V / 3.3V PCI ExpressCard: PCI Express capable
card request, active low, one per card
ICH7-M
3.3V / 3.3V PCI ExpressCard: PCI Express capable
card request, active low, one per card
not
supported
3.3V / 3.3V PCI ExpressCard: reset, active low, one
per card
ICH7-M
3.3V / 3.3V PCI ExpressCard: reset, active low, one
per card
not
supported
2.9.8 PCI Bus
PCI Bus
Pin
Type
PCI_AD[0:31]
Pwr Rail /
Tolerance
Description
MSC 945GM
device
I/O
CMOS
PCI_C/BE[0:3]#
I/O
CMOS
PCI_DEVSEL#
I/O
CMOS
PCI_FRAME#
I/O
CMOS
PCI_IRDY#
I/O
CMOS
PCI_TRDY#
I/O
CMOS
PCI_STOP#
I/O
CMOS
PCI_PAR
I/O
CMOS
PCI_PERR#
I/O
CMOS
3.3V / 5V
PCI bus multiplexed address and data
lines
ICH7-M
3.3V / 5V
PCI bus byte enable lines, active low
ICH7-M
3.3V / 5V
PCI bus Device Select, active low.
ICH7-M
3.3V / 5V
PCI bus Frame control line, active low.
ICH7-M
3.3V / 5V
PCI bus Initiator Ready control line, active
low.
ICH7-M
3.3V / 5V
PCI bus Target Ready control line, active
low.
ICH7-M
3.3V / 5V
PCI bus STOP control line, active low,
driven by cycle initiator.
ICH7-M
3.3V / 5V
PCI bus parity
ICH7-M
3.3V / 5V
ICH7-M
PCI_REQ[0:3]#
3.3V / 5V
Parity Error: An external PCI device drives
PERR# when it receives data that has a
parity error.
PCI bus master request input lines, active
low.
3.3V / 5V
PCI bus master grant output lines, active
low.
ICH7-M
3.3V / 5V
Suspend
PCI Reset output, active low.
ICH7-M
PCI_GNT[0:3]#
PCI_RESET#
I
CMOS
O
CMOS
O
CMOS
20
ICH7-M
PCI Bus
Pin
Type
Pwr Rail /
Tolerance
PCI_LOCK#
I/O
CMOS
I/O OD
CMOS
3.3V / 5V
PCI Lock control line, active low.
ICH7-M
3.3V / 5V
ICH7-M
PCI_PME#
I
CMOS
3.3V / 5V
Suspend
PCI_CLKRUN#
I/O
CMOS
I
CMOS
O
CMOS
I
CMOS
3.3V / 5V
System Error: SERR# may be pulsed
active by any PCI device that detects a
system error condition.
PCI Power Management Event: PCI
peripherals drive PME# to wake system
from low-power states S1–S5.
Bidirectional pin used to support PCI clock
run protocol for mobile systems.
PCI interrupt request lines.
ICH7-M
PCI_SERR#
PCI_IRQ[A:D]#
PCI_CLK
PCI_M66EN
3.3V / 5V
Description
3.3V / 3.3V PCI 33MHz clock output.
3.3V / 5V
Module input signal indicates whether an
off-module PCI device is capable of
66MHz operation. Pulled to GND by
Carrier Board device or by Slot Card if the
devices are NOT capable of 66 MHz
operation.
If the module is not capable of supporting
66 MHz PCI operation, this input may be a
no-connect on the module.
If the module is capable of supporting 66
MHz PCI operation, and if this input is held
low by the Carrier Board, the module PCI
interface shall operate at 33 MHz.
21
MSC 945GM
device
ICH7-M
ICH7-M
ICH7-M
not
supported
2.9.9 USB
USB
Pin
Type
Pwr Rail /
Tolerance
USB[0:7]+
USB[0:7]USB_0_1_OC#
I/O
USB
I
CMOS
3.3V / 3.3V
Suspend
3.3V / 3.3V
Suspend
USB_2_3_OC#
I
CMOS
USB_4_5_OC#
I
CMOS
USB_6_7_OC#
I
CMOS
Description
MSC
945GM
device
USB differential pairs, channels 0 through
7
ICH7-M
USB over-current sense, USB channels 0
and 1. A pull-up for this line is present on
the module. An open drain driver from a
USB current monitor on the Carrier Board
may drive this line low.
Do not pull this line high on the Carrier
Board.
3.3V / 3.3V USB over-current sense, USB channels 2
Suspend and 3. A pull-up for this line is present on
the module. An open drain driver from a
USB current monitor on the Carrier Board
may drive this line low.
Do not pull this line high on the Carrier
Board.
3.3V / 3.3V USB over-current sense, USB channels 4
Suspend and 5. A pull-up for this line is present on
the module. An open drain driver from a
USB current monitor on the Carrier Board
may drive this line low.
Do not pull this line high on the Carrier
Board.
3.3V / 3.3V USB over-current sense, USB channels 6
Suspend and 7. A pull-up for this line is present on
the module. An open drain driver from a
USB current monitor on the Carrier Board
may drive this line low.
Do not pull this line high on the Carrier
Board.
ICH7-M
ICH7-M
ICH7-M
ICH7-M
2.9.10 LVDS Flat Panel
LVDS Flat Panel
Pin
Type
Pwr Rail /
Tolerance
Description
LVDS_A[0:3]+
LVDS_A[0:3]-
O
LVDS
LVDS Channel A differential pairs
945GM
GMCH
LVDS_A_CK+
LVDS_A_CK-
O
LVDS
LVDS Channel A differential clock
945GM
GMCH
LVDS_B[0:3]+
LVDS_B[0:3]-
O
LVDS
LVDS Channel B differential pairs
945GM
GMCH
LVDS_B_CK+
LVDS_B_CK-
O
LVDS
LVDS Channel B differential clock
945GM
GMCH
LVDS_VDD_EN
O
CMOS
3.3V / 3.3V LVDS panel power enable
945GM
GMCH
LVDS_BKLT_EN
O
CMOS
3.3V / 3.3V LVDS panel backlight enable
945GM
GMCH
22
MSC 945GM
device
LVDS_BKLT_CT
RL
O
3.3V / 3.3V LVDS panel backlight brightness control
945GM
3.3V / 3.3V I2C clock output for LVDS display use
945GM
GMCH
3.3V / 3.3V I2C data line for LVDS display use
945GM
GMCH
CMOS
LVDS_I2C_CK
O
CMOS
LVDS_I2C_DAT I/O OD
CMOS
GMCH
2.9.11 LPC Bus
LPC Interface
Pin
Type
LPC_AD[0:3]
I/O
Pwr Rail /
Tolerance
Description
MSC 945GM
device
3.3V / 3.3V LPC multiplexed address, command and
data bus
ICH7-M
3.3V / 3.3V LPC frame indicates the start of an LPC
cycle
ICH7-M
CMOS
LPC_FRAME#
O
CMOS
LPC_DRQ[0:1]#
I
CMOS
3.3V / 3.3V LPC serial DMA request
ICH7-M
LPC_SERIRQ
I/O
CMOS
3.3V / 3.3V LPC serial interrupt
ICH7-M
LPC_CLK
O
CMOS
3.3V / 3.3V LPC clock output - 33MHz nominal
ICH7-M
2.9.12 Analogue VGA
Analog VGA
Pin
Type
VGA_RED
O
Analog
VGA_GRN
O
Analog
VGA_BLU
O
Analog
VGA_HSYNC
O
CMOS
O
CMOS
O
CMOS
VGA_VSYNC
VGA_I2C_CK
VGA_I2C_DAT
I/O OD
CMOS
Pwr Rail /
Tolerance
Description
Red for monitor. Analog DAC output,
designed to drive a 37.5-Ohm equivalent
load.
Green for monitor. Analog DAC output,
designed to drive a 37.5-Ohm equivalent
load.
Blue for monitor. Analog DAC output,
designed to drive a 37.5-Ohm equivalent
load.
3.3V / 3.3V Horizontal sync output to VGA monitor
3.3V / 3.3V Vertical sync output to VGA monitor
3.3V / 3.3V DDC clock line (I2C port dedicated to
identify
VGA monitor capabilities)
3.3V / 3.3V DDC data line.
23
MSC 945GM
device
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
2.9.13 TV Out
TV Out
Pin
Type
TV_DAC_A
O
Analog
TV_DAC_B
O
Analog
TV_DAC_C
O
Analog
Pwr Rail /
Tolerance
Description
MSC
945GM
device
TVDAC Channel A Output supports the
following
not
Composite video: CVBS Component video: supported
Chrominance (Pb) analog signal
S-Video: not used
TVDAC Channel B Output supports the
following:
not
Composite video: not used
supported
Component video: Luminance (Y) analog
signal
S-Video: Luminance analog signal.
TVDAC Channel C Output supports the
following:
not
Composite video: not used
supported
Component: Chrominance (Pr) analog
signal.
S-Video: Chrominance analog signal.
2.9.14 SVDO
SDVO
Pin
Type
SDVOB_RED+
O
SDVOB_RED-
PCIE
SDVOB_GRN+
O
SDVOB_GRN-
PCIE
SDVOB_BLU+
O
SDVOB_BLU-
PCIE
SDVOB_CK+
O
SDVOB_CK-
PCIE
SDVOB_INT+
I
SDVOB_INT-
PCIE
SDVOC_RED+
O
SDVOC_RED-
PCIE
SDVOC_GRN+
O
SDVOC_GRN-
PCIE
SDVOC_BLU+
O
Pwr Rail /
Tolerance
Description
AC coupled Serial Digital Video B red output differential
pair
on module Multiplexed with PEG_TX[0]+ and
PEG_TX[0]- pair
AC coupled Serial Digital Video B green output
differential pair
on module Multiplexed with PEG_TX[1]+ and
PEG_TX[1]AC coupled Serial Digital Video B blue output
differential pair
on module Multiplexed with PEG_TX[2]+ and
PEG_TX[2]AC coupled Serial Digital Video B clock output
differential pair.
on module Multiplexed with PEG_TX[3]+ and
PEG_TX[3]AC coupled Serial Digital Video B interrupt input
differential pair.
off module Multiplexed with PEG_RX[1]+ and
PEG_RX[1]AC coupled Serial Digital Video C red output differential
pair.
on module Multiplexed with PEG_TX[4]+ and
PEG_TX[4]AC coupled Serial Digital Video C green output
differential pair.
on module Multiplexed with PEG_TX[5]+ and
PEG_TX[5]AC coupled Serial Digital Video C blue output
24
MSC 945GM
device
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
GMCH
945GM
SDVO
Pin
Type
SDVOC_BLU-
PCIE
SDVOC_CK+
O
SDVOC_CK-
PCIE
SDVOC_INT+
I
SDVOC_INT-
PCIE
SDVO_TVCLKIN
+
SDVO_TVCLKIN
-
I
PCIE
SDVO_FLDSTAL
I
L+
PCIE
SDVO_FLDSTAL
LSDVO_I2C_CK
O
CMOS
SDVO_I2C_DAT I/O OD
CMOS
Pwr Rail /
Tolerance
Description
differential pair.
on module Multiplexed with PEG_TX[6]+ and
PEG_TX[6]AC coupled Serial Digital Video C clock output
differential pair.
on module Multiplexed with PEG_TX[7]+ and
PEG_TX[7]AC coupled Serial Digital Video C interrupt input
differential pair.
off module Multiplexed with PEG_RX[5]+ and
PEG_RX[5]AC coupled Serial Digital Video TVOUT
off module synchronization clock
input differential pair.
Multiplexed with PEG_RX[0]+ and
PEG_RX[0]AC coupled Serial Digital Video Field Stall input
off module differential pair.
Multiplexed with PEG_RX[2]+ and
PEG_RX[2]2.5V / 2.5V SDVO I2C clock line - to set up SDVO
peripherals.
2.5V / 2.5V SDVO I2C data line - to set up SDVO
peripherals.
MSC 945GM
device
GMCH
945GM
GMCH
945GM
GMCH
not
supported
945GM
GMCH
945GM
GMCH
945GM
GMCH
2.9.15 Miscellaneous
Miscellaneous
I2C_CK
I2C_DAT
SPKR
BIOS_DISABLE#
WDT
KBD_RST#
KBD_A20GATE
Pin
Type
O
CMOS
I/O OD
CMOS
CMOS
I
CMOS
O
CMOS
I
CMOS
I
CMOS
Pwr Rail /
Description
Tolerance
MSC 945GM
device
3.3V / 3.3V General purpose I2C port clock output
ICH7-M/
GPIO2
3.3V / 3.3V General purpose I2C port data I/O line
ICH7-M/
GPIO1
3.3V / 3.3V Output for audio enunciator - the "speaker" ICH7-M
in PC-AT systems
3.3V / 3.3V Module BIOS disable input.
Disables
Pull low to disable module BIOS.
firmware hub
3.3V / 3.3V Output indicating that a watchdog time-out PIC12C509
event has occurred.
3.3V / 3.3V Input to module from (optional) external
keyboard controller that can force a reset.
Pulled high on the module. This is a legacy
artifact of the PC-AT.
3.3V / 3.3V Input to module from (optional) external
keyboard controller that can be used to
control the CPU A20 gate line. The
A20GATE restricts the memory access to
the bottom megabyte and is a legacy
artifact of the PC- AT. Pulled high on the
module.
25
ICH7-M
ICH7-M
2.9.16 Power and System Management
Power and
System
Management
Pin
Type
PWRBTN#
I
CMOS
I
CMOS
SYS_RESET#
CB_RESET#
O
CMOS
PWR_OK
I
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
SUS_STAT#
SUS_S3#
SUS_S4#
SUS_S5#
WAKE0#
WAKE1#
I
CMOS
I
CMOS
BATLOW#
I
CMOS
THRM#
I
CMOS
O
CMOS
THERMTRIP#
SMB_CK
SMB_DAT
SMB_ALERT#
Pwr Rail /
Tolerance
Description
3.3V / 3.3V Power button to bring system out of S5
Suspend (soft off), active on rising edge.
MSC 945GM
device
ICH7-M
3.3V / 3.3V Reset button input. Active low input.
ICH7-M
Suspend System is held in hardware reset while this
input is low, and comes out of reset upon
release.
3.3V / 3.3V Reset output from module to Carrier
945GM
Suspend Board. Active low. Issued by module
ICH7-M
chipset and may result from a low
FWH
SYS_RESET# input, a low PWR_OK input,
LAN
a VCC_12V power input that falls below
TPM
the minimum specification, a watchdog
timeout, or may be initiated by the module
software.
3.3V / 3.3V Power OK from main power supply. A high LTC1727
value indicates that the power is good.
3.3V / 3.3V
Suspend
3.3V / 3.3V
Suspend
3.3V / 3.3V
Suspend
3.3V / 3.3V
Suspend
Indicates imminent suspend operation;
used to notify LPC devices.
ICH7-M
Indicates system is in Suspend to RAM
state. Active low output.
ICH7-M
Indicates system is in Suspend to Disk
state. Active low output.
ICH7-M
Indicates system is in Soft Off state. Also
known as "PS_ON" and can be used to
control an ATX power supply.
3.3V / 3.3V PCI Express wake up signal.
Suspend
3.3V / 3.3V General purpose wake up signal. May be
Suspend used to implement wake-up on PS2
keyboard or mouse activity.
3.3V / 3.3V Indicates that external battery is low.
Suspend
ICH7-M
3.3V / 3.3V Input from off-module temp sensor
indicating an over-temp situation.
ICH7-M
(GPI12)
CPU
945GM
ICH7-M
ICH7-M
3.3V / 3.3V Active low output indicating that the CPU
has entered thermal shutdown.
I/O OD 3.3V / 3.3V System Management Bus bidirectional
CMOS Suspend Rail clock line. Power sourced through 5V
standby rail and main power rails.
I/O OD 3.3V / 3.3V System Management Bus bidirectional
CMOS Suspend Rail data line. Power sourced through 5V
standby rail and main power rails.
I
3.3V / 3.3V System Management Bus Alert – active
CMOS Suspend Rail low input can be used to generate an SMI#
(System Management Interrupt) or to wake
the system. Power sourced through 5V
standby rail and main power rails.
26
ICH7-M
(82573)
ICH7-M
ICH7-M
ICH7-M
ICH7-M
2.9.17 General Purpose I/O
General
Purpose I/O
Pin
Type
GPO[0:3]
O
CMOS
GPI[0:3]
I
CMOS
Pwr Rail /
Description
Tolerance
MSC 945GM
device
3.3V / 3.3V General purpose output pins.
ICH7-M
Upon a hardware reset, these outputs are
GPIOs
low.
[33,34,38,39]
3.3V / 3.3V General purpose input pins.
ICH7-M
Pulled high internally on the module.
GPIOs
[21,19,36,37]
2.9.18 Module Type Definition
Module Type
Definition
Pin
Type
TYPE[0:2]#
PDS
Pwr Rail /
Tolerance
Description
MSC
945GM
device
The TYPE pins indicate to the Carrier Board
the Pin-out Type that is implemented on the
module. The pins are tied on the module to
either ground (GND) 27 rare no-connects
(NC). For Pin-out Type 1, these pins are
don‟t care (X).
TYPE2 TYPE1 TYPE0
#
#
#
X
NC
X
NC
X
NC
Pin-out Type 1
Pin-out Type 2
NC
NC
GND
NC
GND
NC
NC
GND
GND
Pin-out Type 3 (no
DIE)
Pin-out Type 4 (no
PCI)
Pin-out Type 5 (no
DIE, no PCI)
The Carrier Board should implement
combinatorial logic that monitors the module
TYPE pins and keeps power off (e.g
deactivates the ATX_ON signal for an ATX
power supply) if an incompatible module
pin- out type is detected. The Carrier Board
logic may also implement a fault indicator
such as an LED.
27
MSC
945GM
2.9.19 Power and GND
Power and GND
Pin
Type
VCC_12V
Power
Primary power input: +12V (+/- 5%)
VCC_5V_SBY
Power
Standby power input: +5.0V (+/- 5%)
If VCC5_SBY is used, all available
VCC_5V_SBY pins on the connector(s)
shall be used.
Only used for standby and suspend
functions.
May be left unconnected if these functions
are not used in the system design.
Real-time clock circuit-power input : +3.0V
(+2.0V – 3.3V)
Ground - DC power and signal and AC
signal return path. All available GND
connector pins shall be used and tied to
Carrier Board GND plane.
VCC_RTC
Power
GND
Power
Pwr Rail /
Tolerance
Description
28
MSC 945GM
device
Voltage
regulators
VCC3.3V
SUS
regulator
ICH7-M
2.10 Pin List for MSC 945GM module (Type 2)
Row
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
GND (FIXED)
GBE0_MDI3GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1GBE0_MDI1+
GND (FIXED)
GBE0_MDI0GBE0_MDI0+
GBE0_CTREF
SUS_S3#
SATA0_TX+
SATA0_TXSUS_S4#
SATA0_RX+
SATA0_RXGND (FIXED)
SATA2_TX+
SATA2_TXSUS_S5#
SATA2_RX+
SATA2_RXBATLOW#
ATA_ACT#
AC_SYNC
AC_RST#
GND (FIXED)
AC_BITCLK
AC_SDOUT
BIOS_DISABLE#
THRMTRIP#
USB6USB6+
USB_6_7_OC#
USB4USB4+
GND (FIXED)
USB2USB2+
USB_2_3_OC#
USB0USB0+
VCC_RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC_SERIRQ
Row
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
Row
C
GND (FIXED)
C1
GBE0_ACT#
C2
LPC_FRAME#
C3
LPC_AD0
C4
LPC_AD1
C5
LPC_AD2
C6
LPC_AD3
C7
LPC_DRQ0#
C8
LPC_DRQ1#
C9
LPC_CLK
C10
GND (FIXED)
C11
PWRBTN#
C12
SMB_CK
C13
SMB_DAT
C14
SMB_ALERT#
C15
SATA1_TX+
C16
SATA1_TXC17
SUS_STAT#
C18
SATA1_RX+
C19
SATA1_RXC20
GND (FIXED)
C21
SATA3_TX+
C22
SATA3_TXC23
PWR_OK
C24
SATA3_RX+
C25
SATA3_RXC26
WDT
C27
AC_SDIN2
C28
AC_SDIN1
C29
AC_SDIN0
C30
GND (FIXED)
C31
SPKR
C32
I2C_CK
C33
I2C_DAT
C34
THRM#
C35
USB7C36
USB7+
C37
USB_4_5_OC#
C38
USB5C39
USB5+
C40
GND (FIXED)
C41
USB3C42
USB3+
C43
USB_0_1_OC#
C44
USB1C45
USB1+
C46
EXCD1_PERST# C47
EXCD1_CPPE#
C48
SYS_RESET#
C49
CB_RESET#
C50
= not supported on MSC 945GM module
29
GND (FIXED)
IDE_D7
IDE_D6
IDE_D3
IDE_D15
IDE_D8
IDE_D9
IDE_D2
IDE_D13
IDE_D1
GND (FIXED)
IDE_D14
IDE_IORDY
IDE_IOR#
PCI_PME#
PCI_GNT2#
PCI_REQ2#
PCI_GNT1#
PCI_REQ1#
PCI_GNT0#
GND (FIXED)
PCI_REQ0#
PCI_RESET#
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD6
PCI_AD8
PCI_AD10
PCI_AD12
GND (FIXED)
PCI_AD14
PCI_C/BE1#
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY#
PCI_C/BE2#
PCI_AD17
PCI_AD19
GND (FIXED)
PCI_AD21
PCI_AD23
PCI_C/BE3#
PCI_AD25
PCI_AD27
PCI_AD29
PCI_AD31
PCI_IRQA#
PCI_IRQB#
Row
D
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
GND (FIXED)
IDE_D5
IDE_D10
IDE_D11
IDE_D12
IDE_D4
IDE_D0
IDE_REQ
IDE_IOW#
IDE_ACK#
GND (FIXED)
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_CS1#
IDE_CS3#
IDE_RESET#
PCI_GNT3#
PCI_REQ3#
GND (FIXED)
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_C/BE0#
PCI_AD9
PCI_AD11
PCI_AD13
PCI_AD15
GND (FIXED)
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_AD16
PCI_AD18
PCI_AD20
PCI_AD22
GND (FIXED)
PCI_AD24
PCI_AD26
PCI_AD28
PCI_AD30
PCI_IRQC#
PCI_IRQD#
PCI_CLKRUN#
PCI_M66EN
PCI_CLK
Row
A
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
Row
B
GND (FIXED)
B51
PCIE_TX5+
B52
PCIE_TX5B53
GPI0
B54
PCIE_TX4+
B55
PCIE_TX4B56
GND
B57
PCIE_TX3+
B58
PCIE_TX3B59
GND (FIXED)
B60
PCIE_TX2+
B61
PCIE_TX2B62
GPI1
B63
PCIE_TX1+
B64
PCIE_TX1B65
GND
B66
GPI2
B67
PCIE_TX0+
B68
PCIE_TX0B69
GND (FIXED)
B70
LVDS_A0+
B71
LVDS_A0B72
LVDS_A1+
B73
LVDS_A1B74
LVDS_A2+
B75
LVDS_A2B76
LVDS_VDD_EN B77
LVDS_A3+
B78
LVDS_A3B79
GND (FIXED)
B80
LVDS_A_CK+
B81
LVDS_A_CKB82
LVDS_I2C_CK
B83
LVDS_I2C_DAT B84
GPI3
B85
KBD_RST#
B86
KBD_A20GATE
B87
PCIE0_CK_REF+ B88
PCIE0_CK_REF- B89
GND (FIXED)
B90
RSVD
B91
RSVD
B92
GPO0
B93
RSVD
B94
RSVD
B95
GND
B96
B97
VCC_12V
B98
VCC_12V
B99
VCC_12V
GND (FIXED)
B100
VCC_12V
B101
VCC_12V
B102
VCC_12V
B103
VCC_12V
B104
VCC_12V
B105
VCC_12V
B106
VCC_12V
B107
VCC_12V
B108
VCC_12V
B109
GND (FIXED)
B110
Row
C
GND (FIXED)
C51
PCIE_RX5+
C52
PCIE_RX5C53
GPO1
C54
PCIE_RX4+
C55
PCIE_RX4C56
GPO2
C57
PCIE_RX3+
C58
PCIE_RX3C59
GND (FIXED)
C60
PCIE_RX2+
C61
PCIE_RX2C62
GPO3
C63
PCIE_RX1+
C64
PCIE_RX1C65
WAKE0#
C66
WAKE1#
C67
PCIE_RX0+
C68
PCIE_RX0C69
GND (FIXED)
C70
LVDS_B0+
C71
LVDS_B0C72
LVDS_B1+
C73
LVDS_B1C74
LVDS_B2+
C75
LVDS_B2C76
LVDS_B3+
C77
LVDS_B3C78
LVDS_BKLT_EN
C79
GND (FIXED)
C80
LVDS_B_CK+
C81
LVDS_B_CKC82
LVDS_BKLT_CTRL C83
VCC_5V_SBY
C84
VCC_5V_SBY
C85
VCC_5V_SBY
C86
VCC_5V_SBY
C87
RSVD
C88
VGA_RED
C89
GND (FIXED)
C90
VGA_GRN
C91
VGA_BLU
C92
VGA_HSYNC
C93
VGA_VSYNC
C94
VGA_I2C_CK
C95
VGA_I2C_DAT
C96
TV_DAC_A
C97
TV_DAC_B
C98
TV_DAC_C
C99
GND (FIXED)
C100
VCC_12V
C101
VCC_12V
C102
VCC_12V
C103
VCC_12V
C104
VCC_12V
C105
VCC_12V
C106
VCC_12V
C107
VCC_12V
C108
VCC_12V
C109
GND (FIXED)
C110
= not supported on MSC 945GM module
30
GND (FIXED)
PEG_RX0+
PEG_RX0TYPE0#
PEG_RX1+
PEG_RX1TYPE1#
PEG_RX2+
PEG_RX2GND (FIXED)
PEG_RX3+
PEG_RX3RSVD
RSVD
PEG_RX4+
PEG_RX4RSVD
PEG_RX5+
PEG_RX5GND (FIXED)
PEG_RX6+
PEG_RX6SDVO_DATA
PEG_RX7+
PEG_RX7GND
RSVD
PEG_RX8+
PEG_RX8GND (FIXED)
PEG_RX9+
PEG_RX9RSVD
GND
PEG_RX10+
PEG_RX10GND
PEG_RX11+
PEG_RX11GND (FIXED)
PEG_RX12+
PEG_RX12GND
PEG_RX13+
PEG_RX13GND
RSVD
PEG_RX14+
PEG_RX14GND (FIXED)
PEG_RX15+
PEG_RX15GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
Row
D
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
GND (FIXED)
PEG_TX0+
PEG_TX0PEG_LANE_RV#
PEG_TX1+
PEG_TX1TYPE2#
PEG_TX2+
PEG_TX2GND (FIXED)
PEG_TX3+
PEG_TX3RSVD
RSVD
PEG_TX4+
PEG_TX4GND
PEG_TX5+
PEG_TX5GND (FIXED)
PEG_TX6+
PEG_TX6SDVO_CLK
PEG_TX7+
PEG_TX7GND
IDE_CBLID#
PEG_TX8+
PEG_TX8GND (FIXED)
PEG_TX9+
PEG_TX9RSVD
GND
PEG_TX10+
PEG_TX10GND
PEG_TX11+
PEG_TX11GND (FIXED)
PEG_TX12+
PEG_TX12GND
PEG_TX13+
PEG_TX13GND
PEG_ENABLE#
PEG_TX14+
PEG_TX14GND (FIXED)
PEG_TX15+
PEG_TX15GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
3 Watchdog
The module has a watchdog function implemented using a PIC microcontroller with an
SMBus interface. Via SETUP the watchdog can be enabled and configured.
If the watchdog is enabled a counter is started which creates a reset if it is not
retriggered within a programmable time window.
The watchdog menu in the BIOS provides the following parameters:
Watchdog:
Enabled / Disabled (default)
Initial Delay:
1s, 5s, 10s, 30s (default), 1min, 5min, 10min, 30min
Timeout: 0,4s, 1s, 5s, 10s, 30s (default), 1min, 5 min, 10min
Start on Boot:
If yes, watchdog starts at the end of POST (power on selftest)
before the OS is loaded
ICH7M Pin
GPIO6
GPIO9
Label
WDEN
WDTRIG
GPIO7
WDSTS
Description
Watchdog Enable. 1 = watchdog counter counts
Watchdog Trigger. If watchdog is enabled (WDEN=1), the signal
level on this line has to be inverted within the timeout delay to
trigger this chip (which means to avoid to get a reset)
Watchdog Status. 0 = no Timeout , Default after Power-Up or
after setting of Bit0.
1 = Timeout event has occurred; a reset has been triggered. In
this case, the watchdog counter will be stopped.
Please find programming information, register layout etc. in the datasheet of the ICH7-M.
The timeout and the delay time can be written into the watchdog controller via the SMB.
The register layout is as follows:
Address
Data Byte
0
TimeOut low Byte
Default
value
100d
Read/
Write
W
Bit
1
TimeOut high Byte
0
W
Byte
Byte
2
Delay low Byte
100d
W
Byte
3
Delay high Byte
0
W
Byte
Remark
The SMB-Address of the watchdog controller is B0h/B1h. The data structure to access
the byte registers is:
Device Address B0 - Register Address - Data Byte
Reading these registers is not supported. While writing into these registers, the
watchdog timer has to be stopped.
For information about accessing the SMB please consult the Intel® ICH7-M datasheet.
31
4 System resources
4.1 PCI Devices CXE-945
AD20 /
Dev 04h
B
C
D
PIRQ 7
(INT H)
A
PIRQ 6
(INT G)
-
PIRQ 5
(INT F)
PIRQ 3
(INT D)
1
PIRQ 2
(INT C)
DEV. #
PIRQ 1
(INT B)
or
PIRQ 0
(INT A)
IDSEL #
Bus #
Slot Number
(or Onboard
Device)
PIRQ 4
(INT E)
Interrupts of Controller (ICH-7M)
2
AD21 /
Dev 05h
-
D
A
B
C
3
AD22 /
Dev 06h
-
C
D
A
B
4
AD23 /
Dev 07h
-
B
C
D
A
Internal
Graphic
Device
Dev 02h
0
A
--
PCI Express
Root Port
Dev 28 Fkt
0/1/2/3
0
USB UHCI
Host Controller
Dev 29 Fkt 0
0
USB UHCI
Host Controller
Dev 29 Fkt 1
0
USB UHCI
Host Controller
Dev 29 Fkt 2
0
USB UHCI
Host Controller
Dev 29 Fkt 3
0
D
USB EHCI
Controller
Dev 29 Fkt 7
0
D
AC ‟97 Audio
Dev 30 Fkt 2
0
SATA
Dev 31 Fkt 2
0
B
PATA
Dev 31 Fkt 1
0
B
SMBus
Dev 31 Fkt 3
0
B
100MB Lan
Controller
Dev 8 Fkt 0
-
PCIe Slot 1
Dev 0 Fkt 0
-
PCIe Slot 2
Dev 0 Fkt 0
-
PCIe Slot 3
Dev 0 Fkt 0
-
PCIe Slot 4
Dev 0 Fkt 0
-
-
--
A
B
C
D
A
B
C
A
A
A
A
A
A
Or
GB Lan
Controller
32
4.2 Carrier Board PCI Resource Allocation
The external PCI resource allocation on the carrier board should be as follows:
The signals PCI_IRQx, PCI_REQx or PCI_GNTx are are routed exclusively to the COM
Express connector. They are not shared on the CPU board.
33
4.3 SMB Address Map
Device
A6
A5
A4
A3
A2
A1
A0
R/W
address *)
SMBus host
(ICH7-M slave)
0
0
0
1
0
0
0
x
10h / 08h
Winbond
W83L786R
0
1
0
1
1
1
0
x
5Ch / 2Eh
Watchdog
(PIC12C509)
1
0
1
1
0
0
0
x
B0h / 58h
CY28411 Clock
Synthesizer
1
1
0
1
0
0
1
x
D2h / 69h
CY25823 Clock
Synthesizer
1
1
0
1
0
1
0
x
D4h / 6Ah
CMOS backup
EEPROM
1
0
1
0
1
0
0
x
A8h / 54h
SPD EEPROM
(SO-DIMM 1)
1
0
1
0
0
0
0
x
A0h / 50h
SPD EEPROM
(SO-DIMM 2)
1
0
1
0
0
1
0
x
A2h / 52h
GigaBit LAN
*) 8 bit address (with R/W) / 7 bit address (without R/W)
34
5 BIOS
5.1 Introduction
This guide describes the Phoenix TrustedCore Startup screen and contains information
on how to access Phoenix TrustedCore setup to modify the settings which control
Phoenix pre-OS (operating system) functions.
5.1.1 Startup Screen Overview
The Phoenix TrustedCore Startup screen is a graphical user interface (GUI) that is
included in Phoenix TrustedCore products. The default bios behavior is to show an
informational text screen during bios POST phase, but the graphical boot screen can be
enabled in the bios setup. The standard boot screen is a black screen, including a
progress bar at the bottom of the screen. This bar indicates the progress of the Startup
Screen functions and provides user prompting and POST status. The following figure
shows the various parts of a generic Startup Screen at 1024x768 resolution:
5.1.2 Activity Detection Background
While the TrustedCore Startup screen is displayed, press the Setup Entry key (F2 –
TrustedCore default). The TrustedCore Startup Status Bar acknowledges the input, and
at the end of POST, the screen clears and setup launches.
An example of the Startup Status Bar displaying changing state is shown in the following
figure. The “Please Wait…” text is displayed after the F2 key is pressed to acknowledge
user input.
Active status bar:
35
5.2 TrustedCore Setup Utility
With the Phoenix TrustedCore Setup program, you can modify TrustedCore settings and
control the special features of your computer. The Setup program uses a number of
menus for making changes and turning the special features on or off. This chapter
provides an overview of the Setup utility and describes at a high-level how to use it.
5.2.1 Configuring the System BIOS
To start the Phoenix TrustedCore Setup utility, press [F2] to launch Setup. The Setup
main menu appears.
The BIOS Menu Structure
The BIOS Menu is structured in the following way:
Main
Board Information
IDE Channel 0 Master
IDE Channel 0 Slave
SATA Port 0
SATA Port 1
Boot Options
Keyboard Features
Advanced
Cache Memory
CPU Control Sub-Menu
MCH Control Sub-menu
Video (Intel IGD) Control Sub-menu
ICH Control Sub-menu
PCI Express Control Sub-menu
PCI Control Sub-menu
ICH USB Control Sub-menu
ACPI Control Sub-menu
I/O Device Configuration
Watchdog Options
Security
Power
Hardware Monitor
Boot
Exit
36
The Menu Bar
The Menu Bar at the top of the window lists these selections:
Menu Items
Description
Main
Use this menu for basic system configuration.
Advanced
Use this menu to set the Advanced Features available on your
system‟s chipset.
Security
Use this menu to set User and Supervisor Passwords and the
Backup and Virus-Check reminders.
Power
Use this menu to configure Power-Management features.
Boot
Use this menu to set the boot order in which the BIOS attempts to
boot to OS.
Exit
Exits the current menu.
Use the left and right arrow keys on your keyboard to make a menu selection.
The Legend Bar
Use the keys listed in the legend bar on the bottom of the screen to make your
selections, or to exit the current menu. The following table describes the legend keys and
their alternates:
Key
Function
F1 or Alt-H
General Help window.
Esc
Exit this menu.
Arrow keys
Select a different menu.
Up and down arrow keys
Move cursor up and down.
Tab or Shift-Tab
Move cursor left and right (i.e. at System Time / System Date).
Home or End
Move cursor to top or bottom of window.
PgUp or PgDn
Move cursor to next or previous page.
F5 or -
Select the previous value for the field.
F6 or + or Space
Select the next value for the field.
F9
Load the Default Configuration values (for all menus).
F10
Save and exit.
Enter
Execute command or select submenu.
37
Select an item
To select an item, use the arrow keys to move the cursor to the field you want. Then use
the plus-and-minus value keys to select a value for that field. The Save Values
commands in the Exit Menu save the values currently displayed in all the menus.
Display a submenu
To display a submenu, use the arrow keys to move the cursor to the sub menu you want.
Then press Enter. A pointer marks all submenus.
38
5.2.2 The Main Menu
You can make the following selections on the Main Menu itself. Use the sub menus for
other selections.
Feature
Options
Description
Board Information
Submenu
Displays BIOS Version
System Time
Enter Time (HH:MM:SS)
Set the System Time.
System Date
Enter Date (DD/MM/YYYY)
Set the System Date.
IDE Channel 0 Master
Submenu “Master & Slaves”
Configure IDE Channel 0 Master
IDE Channel 0 Slave
Submenu “Master & Slaves”
Configure IDE Channel 0 Slave
SATA Port 0
Submenu “Master & Slaves”
Configure SATA Port 0
SATA Port 1
Submenu “Master & Slaves”
Configure SATA Port 1
Boot Options
Submenu
Configure Boot Options
5.2.2.1 Board Information
Feature
Options
Description
Bios Version
Informative
Shows current bios version.
HW Platform
Informative
Name of the hardware platform
HW Revision
Informative
Hardware revision number
Serial #
Informative
Hardware Serial Number
Boot Counter
Informative
The number of times this board has
booted up.
CPU String
Informative
CPU Identification string
CPU Speed
Informative
CPU Speed
CPU Class
Informative
CPU ID Class code
CPU Model
Informative
CPU ID Model code
CPU Stepping
Informative
CPU ID Stepping
CPU Cores
Informative
Number of CPU cores
Northbridge
Informative
Identification of the northbridge
Southbridge
Informative
Identification of the southbridge
System Memory
Informative
Amount of memory below 1MB
Extended Memory
Informative
Total amount of memory
39
5.2.2.2 Masters & Slaves
The Master and Slave settings on the Main Menu control these types of devices:
• Hard-disk drives (IDE and SATA)
• Removable-disk drives
• CD-ROM drives
There is one IDE connector on your motherboard, usually labeled "Primary IDE". There
are usually two connectors on each ribbon cable attached to IDE connector. When you
have connected two drives to this connector, the one on the end of the cable is the
Master.
When you enter Setup, the Main Menu displays the results of Autotyping information
each drive provides about its own size and other characteristics–and how they are
arranged as Masters or Slaves on your machine.
Note: Do not attempt to change these settings unless you have an installed drive that
does not autotype properly (such as an older hard-disk drive that does not support
autotyping).
If you need to change your drive settings, select one of the Master or Slave drives on the
Main Menu. This will display a menu like this:
Note: The capacity is displayed in „real‟ Mbytes (1MB=1024*1024 Bytes) Drives with a
total capacity greater than 8Gbyte operate in LBA format only.
Feature
Options
Description
Type
None,
Auto,
User,
IDE Removable,
ATAPI Removable,
Other ATAPI,
CD-ROM
None = Autotyping is not able to
supply the drive type or end user has
selected None, disabling any drive that
may be installed.
Auto = Autotyping, the drive itself
supplies the information.
User = You supply the hard-disk drive
information in the following fields.
IDE Removable = Removable Disk
Drive
ATAPI Removable = Removable Disk
Drive
Other ATAPI = non-specific ATAPI
Device
CD-ROM = CD-ROM drive.
Cylinders
1 to 65536
Number of Cylinders
Heads
1 to 16
Number of read/write heads
Sectors
1 to 63
Number of sectors per track
Multi-Sector Transfers
Disabled, 2 sectors,
4 sectors, 8 sectors,
16 sectors
Any selection except Disabled
determines the number of sectors
transferred per block.
LBA Mode Control
Disabled, Enabled
Enabling LBA causes Logical Block
Addressing to be used in place of
Cylinders, Heads, & Sectors.
40
Feature
Options
Description
32 Bit I/O
Disabled, Enabled
Enables 32-bit communication
between CPU and IDE card. Requires
PCI or local bus.
Transfer Mode
Standard
Fast PIO 1
Fast PIO 2
Fast PIO 3
Fast PIO 4
FPIO 3 / DMA 1
FPIO 4 / DMA 2
Selects the method for transferring the
data between the hard disk and
system memory.
The Setup menu only lists those
options supported by the drive and
platform.
Ultra DMA Mode
Disabled
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Ultra DMA Mode supports 33/66/100
MB/sec transfer rate for fixed disk
drives.
SMART Monitoring
Disabled, Enabled
Displays the status of SMART
Monitoring if supported by the used
drive.
WARNING: Incorrect settings can cause your system to malfunction.
5.2.2.3 Boot Options
Feature
Options
Description
Summary screen
Disabled, Enabled
Enabled displays system configuration
on boot.
Boot-time Diagnostic
Screen
Disabled, Enabled
Enabled displays the diagnostic
screen during boot.
Disabled displays the Boot Logo.
Post Errors
Disabled, Enabled
Pauses and displays Setup entry or
resume boot prompt if error occurs on
boot. If disabled, system always
attempts to boot.
Extended Memory Testing Normal, Just zero it, None
Determines which type of test will be
performed on extended memory during
POST (above 1 MB).
5.2.2.4 Keyboard Features
Feature
Options
Description
NumLock
On, Off
Selects Power-on state for NumLock
Key Click
Disabled, Enabled
Enables key Click
41
Feature
Options
Description
Keyboard auto-repeat rate 30/s, 26.7/s, 21.8/s, 18.5/s,
13.3/s, 10/s, 6/s, 2/s
Selects key repeat rate
Keyboard auto-repeat
delay
Selects delay before key repeat
1/4s, 1/2s, 3/4s, 1s
5.2.3 The Advanced Menu
Feature
Installed O/S
Options
Description
Other,
Win95,
Win98,
WinMe,
Win2000,
WinXP
Select the operating system installed
on your system which you will use
most commonly.
Reset configuration Data
No, Yes
Select „Yes‟ if you want to clear the
Extended System Configuration Data
(ESCD) area.
Large Disk Access Mode
Other, DOS
Select Other for UNIX, Novell
NetWare. Select DOS for all other
operating systems.
Small Disk Access Mode
No, Yes
Select if CHS translation should be
made for a LBA-capable harddisk with
less than 1024 cylinders, e.g.
CompactFlash(R).
If you have
problems with booting from a
CompactFlash(R), try to change this
setting.
NOTE: An incorrect setting can cause
some operating systems to display
unexpected behavior.
No = translate CHS only if HDD has
>1024 cyls.
Yes = translate CHS for all LBAcapable disks.
Port 80 Cycles
LPC Bus, PCI Bus
Control where the Port 80h cycles are
sent.
Local Bus IDE adapter
Disabled, Enabled
Enable the integrated local bus IDE
adapter.
Cache Memory
Submenu
Configure Cache Memory
Yonah / Merom CPU
Control Sub-Menu
Submenu
Configure Yonah / Merom CPU
Control
MCH Control Sub-Menu
Submenu
Configure MCH Control
Video (Intel IGD) Control
Sub-Menu
Submenu
Configure Video (Intel IGD) Control
42
Feature
Options
Description
ICH Control Sub-Menu
Submenu
Configure ICH Control
ACPI Control Sub-Menu
Submenu
Configure ACPI Control
I/O Device Configuration
Submenu
Configure I/O Device
Watchdog Options
Submenu
Configure Watchdog Options
5.2.3.1 Cache Memory Control Menu
Feature
Options
Description
Cache System BIOS area
Uncached,
Write Protect
Enables caching of system BIOS area.
Cache Video BIOS area
Uncached,
Write Protect
Enables caching of video BIOS area.
Cache D000 – D3FF
Cache D400 – D7FF
Cache D800 – DBFF
Disabled,
Write Through,
Write Protect,
Write Back
Disabled = This block is not cached.
Write through = Writes are cached
and sent to main memory at once.
Write Protect = Writes are ignored.
Write Back = Writes are cached but
not sent to main memory until
necessary.
5.2.3.2 Yonah / Merom CPU Control Sub-Menu
Note: Depending on the CPU type you are using some options of the Control Sub-Menu can be hidden
in consequence of different CPU type features that exist.
Feature
Core Multi Processing
Options
Disabled, Enabled
Description
Determines whether the 2
enabled.
nd
core is
Disabled = 2nd core is disabled
Enabled = 2nd core is enabled
43
Feature
Processor Power
Management
Options
Disabled,
GV3 only,
C-States Only,
Enabled
Description
Selects the Processor Power
Management desired:
Disabled = C-States and GV3 are
disabled.
GV3 Only = C-States are disabled.
C-States Only = GV3 is disabled.
Enabled = C-States und GV3 are
enabled.
Note: GV3 refers to the speed step
capability of the CPU.
Note: If GV3 is disabled, OS will not
run with maximum frequency. To use
maximum frequency, GV3 has to be
enabled and OS must Control the CPU
frequency via Power managment.
Note: For optimal response times the
GV3 (Speed step) must be enabled
and C-States disabled.
Enhanced C-States
Enable
Disabled, Enabled
Enables Enhanced C-State support.
Disabled = Enhanced C-States
disabled.
Enabled = Enhanced C-State enable.
Timestamp Counter
Updates
Disabled, Enabled
Control TSC updates after C3/C4
through this Setup Option.
Thermal Control Circuit
Disabled,
TM1,
TM2,
TM1 and TM2
Setting this bit enables the thermal
control circuit (TCC) portion of the
Thermal Monitor feature of the CPU.
TM1 = 50% duty Cycle
TM2 = Geyserville III
PROCHOT# Enable
Disabled, Enabled
Enables the processors‟s PROCHOT#
signal.
If asserted, the TMx circuit will be
engaged.
PROCHOT# is in addition to the TCC
and Enhanced TCC circuitry inside the
processor, and either may engage
TMx.
44
Feature
Options
DTS Enable
Disabled, Enabled
No Execute Mode Mem
Protection
Enabled, Disabled
Intel (R) Virtualization
Technology
Disabled, Enabled
Set Max Ext CPUID = 3
Disabled, Enabled
Description
Enabled the Yonah DTS to be used for
platform Thermal Management.
Sets Max CPUID extended function
value to 3.
5.2.3.3 MCH Control Sub-Menu
Feature
PCI Express Graphics
Port
Options
Disabled, Auto
Description
Disabled = Port always disabled.
Auto = Only enable if card found.
Port ASPM Support
Disabled, Auto
Control ASPM support for the PEG
Device.
Auto = will set APMC to the highest
common supported ASPM between
the Port and Endpoint.
GPLL Power-Down
Enable:
Disabled, Enabled
Controls the ability of the PEG port to
power down the GPLL.
Disabled = The GPLL will always
remain actice.
Enabled = The GPLL may be powered
down.
MDA Support
Disabled, Enabled
45
Control MDA support for the PEG
Device.
5.2.3.4 Video (Intel IGD) Control Sub-Menu
Feature
Default Primary Video
Adapter
Options
Description
Select „IGD‟ to have Internal Graphics,
if supported and enabled, be used for
the boot display device.
IGD, PEG
Select „PEG‟ to have PCI Express
Graphics, if supported and enabled, be
used for the boot display device.
To use PCI Video, select IGD.
IGD – Device 2
Disabled, Auto
Enables or Disable the Internal
Graphics Device by setting item to the
desired value.
IGD – Device 2, Function1 Disabled, Auto
Enables or Disable Function 1 of the
Internal Graphics Device by setting
item to the desired value.
IGD – Boot Type
VBIOS default,
CRT,
LFP,
EFP,
EFP2,
CRT+LFP,
CRT+EFP,
CRT+EFP2
Select the Video Device that will be
activated during POST.
640x480
1 PPC, 18b
800x600
1 PPC, 18b
1024x768 1 PPC, 18b
1280x1024 2 PPC, 18b
1400x900 2 PPC, 24b
1400x1050 2 PPC, 24b
1600x1200 2 PPC, 24b
1280x1024 2 PPC, 24b
1024x768 1 PPC, 24b
10: Reserved
11: Reserved
12: Reserved
13: Reserved
14: Reserved
15: Reserved
16: Reserved
Select the LCD panel used by the
Internal Graphics Device by selecting
the appropriate setup item.
The first item is Panel 1, the last item
is Panel 16.
Some Panels are not numbered due to
size constraints.
IGD – Panel Scaling
Auto, Force Scaling, Off
Selects the LCD panel scaling option
used by the Internal Graphics Device.
1. Auto
2. Force Scaling
3. Off
IGD – Backlight
Brightness
0%, 10%, 20%, 30%, 40%,
50%, 60%, 70%, 80%, 90%,
100%
Select the starting brightness for the
LVDS backlight signal.
IGD – LCD Panel Type
Note: Due to size constrains not all
Panels are exactly numbered. The first
item is Panel 1, the last one Panel 16.
Note: some backlight inverters use an
inverted level for brightness control –
please check the inverter spec. for the
display panel
46
Feature
Spread Spectrum Clock
Chip
Options
Off, Hardware, Software
Description
Control programming of the Spread
Spectrum Clock Chip.
Hardware = Spread is Chip Controlled.
Software = Spread is BIOS Controlled
with the following supported ranges:
Down Spread: 0.8% - 3.0%.
Center Spread: 0.3% - 1.5%.
DVMT 3.0 Mode
Fixed, DVMT, Combo
Select the configuration of DVMT 3.0
Graphics Memory that Driver will
allocate for use by the Internal
Graphics Device. 1. Fixed
2. DVMT
3. Combo
Pre-Allocated Memory
Size
1 MB, 8 MB
Select the amount of Pre-Allocated
Graphics Memory for use by the
Internal Graphics Device.
Total graphics Memory
64MB, 128 MB, MaxDVMT
Select the amount of Total Graphics
Memory
Pre-Allocated + Fixed + DVMT for use
by the Internal for use by the Internal
Graphics Device.
DVMT Graphics Memory
N/A
Displays the Memory size of the Video
device.
5.2.3.5 ICH Control Sub Menu
Feature
Options
Description
PCI Express Control
Submenu
Submenu.
Configure PCI Express Control
PCI Control Submenu
Submenu
Configure PCI Control
ICH USB Contol Submenu Submenu
Configure ICH USB Control
Azalia – Device 27,
Function 0
Control Detection of the Azalia Device.
Disabled, Auto
Disabled = Azalia will be
unconditionally disabled, regardless of
presence.
Auto = Azalia will be enabled if
present, disabled otherwise.
47
Feature
AC97A – Device 30,
Function 2
Options
Disabled, Auto
Description
Control Detection of the AC97 Audio
Device.
Disabled = AC97 Audio will be
unconditionally disabled, regardless of
presence.
Auto = AC97 Audio will be enabled if
present, disabled otherwise.
AC97M – Device 30,
Function 3
Disabled, Auto
Control Detection of the AC97 Modem
Device.
Disabled = AC97 Modem will be
unconditionally disabled, regardless of
presence.
Auto = AC97 Modem will be enabled if
present, disabled otherwise.
AC97 Modem PNE Enable Disabled, Enabled
Control the ability to wake the System
from an AC97 Modem Device
SATA – Device 31,
Function 2
Compatible:
SATA Drive = Primary on SATA
Controller, in Legacy Mode.
PATA Drive = Secondary on SATA
Controller, in Legacy Mode
Compatible, Enhanced
Enhanced:
SATA Drive = Primary on SATA
Controller, in Native Mode.
PATA Drive = Primary on PATA
Controller, in Legacy Mode
AHCI Configuration
Disabled, Enabled
Enhanced AHCI:
WinXP-SP1+IAA driver supports AHCI
mode.
Disable Vacant Ports
Disabled, Enabled
Controls automatic disabling if vacant
SATA ports.
On–board LAN
Disabled, Enabled
Setting item to “Disabled” will remove
the LAN from PCI Config Space.
Setting item to “Enabled” will allow the
LAN to operate correctly.
PXE OPROM
Disabled, Enabled
48
Enable PXE Option ROM.
Feature
Pop Up Mode Enable
Options
Disabled, Enabled
Description
Select the proper mode:
If disabled, bus master traffic is a
break event and it will return from
C3/C4 to C0 based on break events.
If enabled, ICH will observe a bus
master request and it will take the
system from a C3/C4 state to a C2
state and auto enable bus masters.
Pop Down Mode Enable
Disabled, Enabled
Should be enabled only if Pop up is
enabled:
If disabled, ICH will NOT attempt to
automatically return.
If enabled, ICH will observe a NO bus
master request and it can return to a
previous C3 or C4 state.
DMI Link ASPM Support
5.2.3.5.1
Enabled, Disabled
Control ASPM support for DMI link
between GMCH and ICH.
PCI Express Control Sub-Menu
Feature
PCI Express – Root Port
1-4
Options
Disabled,
Enabled,
Auto
Description
Control PCI Express Port via this setup
option.
Disabled = Port always Disabled.
Auto = Only enable if card found.
Note that if Root Port 1 is disabled
Root Ports 2-4 will be disabled as well.
Root Port ASPM Support
Disabled, Auto
Control ASPM support for all the
enabled Root Ports.
Auto = will set APMC to the highest
common supported ASPM between
the Port and Endpoint.
ASPM Latency Checking
Disabled, Enabled
Disabled:
ASPM latencies are ignored when
enabling ASPM.
Enabled:
Enables ASPM latency checking when
enabling ASPM.
Note: Does not check below switches.
49
5.2.3.5.2
PCI Control Sub-Menu
Feature
PCI IRQ line 1
Options
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Description
Select which Interrupt should be
assigned to this PCI Irq.
Devices:IGD, PEG Port, PCI Slot 1,
PCIe Port1, PCIe Port5
PCI IRQ line 2
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Select which Interrupt should be
assigned to this PCI Irq.
Devices: PCI Slot 2, PCIe Slot2,
PCIe Port 6
PCI IRQ line 3
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Select which Interrupt should be
assigned to this PCI Irq.
Devices: PCI Slot 3, PCIe Port 3
PCI IRQ line 4
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Select which Interrupt should be
assigned to this PCI Irq.
Devices: PCI Slot 4, PCIe Port 4
PCI IRQ line 5
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Select which Interrupt should be
assigned to this PCI Irq.
Devices: UHCI Controller 1,
Internal Lan Controller
PCI IRQ line 6
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Select which Interrupt should be
assigned to this PCI Irq.
Devices: UHCI Controller 2,
PATA/SATA Controller, SMBus
PCI IRQ line 7
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Select which Interrupt should be
assigned to this PCI Irq.
Devices: UHCI Controller 3,
HD Audio or AC97 Audio
PCI IRQ line 8
Disabled, Auto Select, 3, 4, 5,
6, 7, 10, 11, 12
Select which Interrupt should be
assigned to this PCI Irq.
Devices: UHCI Controller 4, EHCI
Controller, AC97 Modem
PCI-Bridge SERR
propagation
Disabled, Enabled
50
Select if the PCI bridge should
forward the SERR signal from the
secondary bus to the primary bus.
5.2.3.5.3
ICH USB Control Sub-Menu
Feature
Options
Description
USB 1.1 Controllers
Enable 1, Enable 2, Enable 3,
Enable 4
Select the number of UHCI controllers
that should be enabled.
USB 2.0 Controller
Enable, Disable
Control USB 2.0 functionality through
this Setup Item.
Boot from USB Port 1
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
Boot from USB Port 2
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
Boot from USB Port 3
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
Boot from USB Port 4
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
Boot from USB Port 5
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
Boot from USB Port 6
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
Boot from USB Port 7
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
Boot from USB Port 8
Enable, Disable
Set the boot capability for this usb port
When set to disabled, mass storage
devices will not be able to boot from
this port.
51
5.2.3.6 ACPI Control Sub-Menu
Feature
Options
Description
Enable ACPI
No, Yes
En/Disable ACPI BIOS (Advanced
Configuration and Power Interface)
Disable ACPI _Sx
None, S1, S2, S3
Select one of the ACPI power states:
S1, S2, or S3. If selected, the
corresponding power state will be
disabled.
FACP – RTC S4 Flag
Value
Disabled, Enabled
Valid only for ACPI
Control the value for the RTC S4 flag
in the FACP Table
FACP – PM Timer Flag
Value
Disabled, Enabled
Valid only for ACPI
Controls the timer used by the OS
through the FACP Tables Flags.
This is now possible with WINXP
SP2 and beyond.
HPET Support
Disabled, Enabled
This field is valid only in the
WindowsXP OS.
Control the High Performance Event
Timer through this setup option
when enabled. The HPET Table will
then be pointed to by the RSDT and
the proper enable bits will be set.
HPET Base Address
0xFED00000,
0xFED01000,
0xFED02000,
0xFED03000
Select the Base Address for the High
Performance Event Timer.
Passive Cooling Trip Point Disabled,
15 C, 23 C, 31 C, 39 C, 47 C,
55 C, 63 C, 71 C, 79 C, 87 C,
95 C, 103 C, 111 C, 119 C
This value controls the temperature
of the ACPI Passive Trip Point – the
point in which the OS will begin
throttling the CPU.
Note: If the DTS is enabled, only
values below 97C are valid.
Passive TC1 Value,
0 - 15
This value sets the TC1-2 value for
the ACPI Passive Cooling Formula.
1 - 15
This item sets the TSP value for the
ACPI Passive Cooling Formula.
It represents in tenths of a second
how often the OS will read the
temperature when Passive Cooling
is Enabled.
Passive TC2 Value,
Passive TSP Value
52
Feature
Critical Trip Point
Options
POR,
15 C, 23 C, 31 C, 39 C, 47 C,
55 C, 63 C, 71 C, 79 C, 87 C,
95 C, 103 C, 111 C, 119 C,
127 C
Description
This value controls the temperature
of the ACPI Critical Trip Point – the
point in which the OS will shut the
system off.
Notes: (1)100C is POR for all Intels
CPUs. (2) If value is > 100C and
DTS is enabled, the Out-of-Spec Bit
will be used.
(3) The EC value will be set to 127
after ACPI initialation.
5.2.3.7 I/O Device Configuration Menu
Feature
Options
Description
Serial Port A
Disabled, Enabled, Auto
Disabled = Disabled the device
Enabled = User configuration
Auto = BIOS or OS chooses
configuration
Base I/O address
3F8, 2F8, 3E8, 2E8
Set the base I/O address for Serial
Port A.
Interrupt
3, 4
Set the interrupt for Serial Port A.
Serial Port B
Disabled, Enabled, Auto
Disabled = Disabled the device
Enabled = User configuration
Auto = BIOS or OS chooses
configuration
Mode
Normal, IR, ASK-IR
Set the mode for Serial Port B (wired
/ infrared).
Base I/O address
3F8, 2F8, 3E8, 2E8
Set the base I/O address for Serial
Port B.
Interrupt
3, 4
Set the interrupt for Serial Port B.
Parallel Port
Disabled, Enabled, Auto
Disabled = Disabled the device
Enabled = User configuration
Auto = BIOS or OS chooses
configuration
Mode
Output only,
Bi-directional,
ECP
Set the mode for Parallel Port.
Base I/O address
378, 278, 3BC
Set the base I/O address for Parallel
Port.
Interrupt
5, 7
Set the interrupt for Parallel Port.
DMA channel
1, 3
Set the DMA channel for Parallel
Port (only available if mode was set
to ECP).
53
Warning: If you choose the same I/O address or Interrupt for more than one port, the
menu displays an asterisk (*) at the conflicting settings.
5.2.3.8 Watchdog Options
Feature
Options
Description
Watchdog delay
1 second,
5 seconds,
10 seconds,
30 seconds
1 minute ,
5 minutes,
10 minutes,
30 minutes
After watchdog is activated, it waits
selected delay time before it starts
counting the timeout period.
Watchdog timeout
0.4 second,
1 second,
5 seconds,
10 seconds,
30 seconds,
1 minute ,
5 minutes,
10 minutes
Select the maximum watchdog
trigger period.
If the watchdog will not be triggered
during selected period, system reset
will be generated.
Watchdog start on boot
No, Yes
Select if the watchdog should be
started at the end of POST.
54
5.2.4 The Security Menu
Feature
Options
Description
Supervisor Password Is Displays Supervisor
Password Is
Displays the current status of the
Supervisor password (“Clear” or “Set”)
User Password Is
Displays User Password Is Displays the current status of the User
password (“Clear” or “Set”)
Set Supervisor
Password
Press return to enter
supervisor password
Supervisor Password controls access to
the setup utility.
Set User Password
Press return to enter user
password
User Password controls access to the
system at boot.
Password on boot
Disabled,
Enabled
Enables password entry on boot
TPM Support
Disabled,
Enabled
Enable Trusted Platform Module support.
Current TPM State
Displays Current TPM
State
Displays the current TPM status.
Change TPM State
No Change,
Enable & Activate,
Deactivate & Disable,
Clear
Changes TPM state.
55
5.2.5 The Power Menu
Feature
After Power Failure
Options
Stay Off,
Last State,
Power On
Description
Sets the mode of operation if an AC power loss
occurs.
Power On will turn the power on as soon as the
power supply is back on.
Last State will only turn the power on, if the system
was active when the power loss occurred.
Stay Off will keep the power off until the power
button is pressed.
CK-410 Clock Chip
Default,
Program
Control Programming of the CK-410 Clock Chip.
Default = Power On Default Values.
Program = Fine tune the clock setup according to
hardware capabilities.
Spread Spectrum Mode
Off, On
Control programming of the Spread Spectrum Mode
bit in CK-410 chip.
Hardware Monitor
Submenu
Configure Hardware Monitor
5.2.5.1 Hardware Monitoring Menu
Feature
Description
CPU Vcore
Displays the current CPU voltage.
VRam (V+2.5)
Displays the current voltage.
Vcc (V+3.3)
Displays the current voltage.
VIN1 (V+1.5)
Displays the current voltage.
VIN2 (V+0.9)
Displays the current voltage.
Temperature Sensor 0
Displays the current CPU temperature.
Temperature Sensor 1
Displays the current memory temperature.
Temperature Sensor 3
Displays the current system temperature.
FAN 1 speed
Displays the current fan speed.
56
5.2.6
The Boot Menu
After you turn on your computer, it will attempt to load the operating system (such
as DOS, Windows XP or Linux) from a device listed in the boot priority order. If it cannot
find the operating system on that device, it will attempt to load it from the next device in
that list.
Boot devices (i.e., with access to an operating system) can include: hard drives, floppy
drives, CD ROMs, removable devices (e.g. USB sticks), and network cards.
Note: Specifying any device as a boot device on the Boot Menu requires the availability
of an operating system on that device.
Selecting "Boot" from the Menu Bar displays the Boot menu, which looks like this:
Feature
Boot priority order:
1: USB KEY:
2: USB FDC:
3: IDE 4:
4: IDE 5:
5: IDE 0:
6: IDE 2:
7: PCI LAN:
8:
Exclude from boot order:
Description
Boot priority order for next boot. System tries to boot the
first bootable device in this list.
Use <+> and <-> to change order.
Use <x> to exclude or include device to boot priority list.
System does not try to boot a device from this list.
: IDE 1:
: IDE 3:
: USB HDD:
: USB CDROM:
: USB ZIP:
: USB LS120:
: PCI SCSI:
Pressing the “F10” key during the bios boot phase will bring up the bios boot menu, which
will allow you to select a different boot device for the current boot process only. In this
boot menu, only devices in the “Boot priority list” will selectable. Devices excluded from
boot order will not be shown.
57
5.2.7 The Exit Menu
The following sections describe each of the options on this menu. Note that <Esc> does
not exit this menu. You must select one of the items from the menu or menu bar to exit.
Exit Saving Changes
After making your selections on the Setup menus, always select "Exit Saving Changes".
This procedures stores the selections displayed in the menus in CMOS (short for
"battery-backed CMOS RAM") a special section of memory that stays on after you turn
your system off. The next time you boot your computer, the BIOS configures your system
according to the Setup selections stored in CMOS.
If you attempt to exit without saving, the program asks if you want to save before exiting.
During boot-up, PhoenixBIOS attempts to load the values saved in CMOS. If those
values cause the system boot to fail, reboot and press <F2> to enter Setup. In Setup, you
can get the Default Values (as described below) or try to change the selections that
caused the boot to fail.
Exit Discarding Changes
Use this option to exit Setup without storing in CMOS any new selections you may have
made. The selections previously in effect remain in effect.
Load Setup Defaults
To display the default values for all the Setup menus, select "Load Setup Defaults" from
the Main Menu.
If, during boot-up, the BIOS program detects a problem in the integrity of values stored in
CMOS, it displays these messages:
System CMOS checksum bad - run SETUP Press <F1> to resume, <F2> to Setup
The CMOS values have been corrupted or modified incorrectly, perhaps by an
application program that changes data stored in CMOS.
Press <F1> to resume the boot or <F2> to run Setup with the ROM default values
already loaded into the menus. You can make other changes before saving the values to
CMOS.
Discard Changes
If, during a Setup Session, you change your mind about changes you have made and
have not yet saved the values to CMOS, you can restore the values you previously saved
to CMOS.
Selecting “Discard Changes” on the Exit menu updates all the selections with their
previous values.
Save Changes
Selecting “Save Changes” saves all the selections without exiting Setup. You can return
to the other menus if you want to review and change your selections.
58
5.3 Bios Update
If a System-BIOS update is required please follow these instructions:
1.) Create a bootable DOS disk/usb-stick/hdd.
2.) Copy PHLASH16.EXE, BIOS.WPH and UPDATE.BAT to this device.
3.) Boot the system from this device.
4.) Type "update.bat" to update the System BIOS.
5.) When the BIOS update has finished, reboot the system.
Note: After the system has been updated, the CMOS has been changed to defaults and
therefore it is necessary to enter Setup (press F2 at boot time) to configure the system
settings.
59
5.4 Bios Crisis Recovery
Note: Contact your sales for information how to get the CRISDISK.ZIP and an USB
recovery dongle.
Please follow these simple steps to create a bootable crisis recovery medium:
1. Unzip CRISDISK.ZIP and start the windows-based program WINCRIS.EXE on the
host system. A window will pop up as shown below:
2. In the drop-down box, either select “Floppy Drive A” to create a recovery disk, or
select “Removable Disk 0 (xxxMb)” to create a recovery usb stick. Disk options
should be left at “Create MINIDOS Crisis Disk”.
3. Press the start button to generate the selected crisis recovery medium.
There are two possibilities to force the target system into crisis recovery mode: either by USB
crisis recovery dongle or by crisis recovery jumper.
1. With the dongle, you just have to plug it into a free USB port before switching the
system on. Please make sure that you use different USB controllers for USB dongle
and USB crisis recovery medium. After powerup, crisis recovery mode should
automatically start.
60
2. The crisis recovery jumper is located between CPU and northbridge, near the edge of
the board (see picture below). You have to shorten the two pins before applying
power to the board. As soon as crisis recovery is started, you can remove the jumper.
The programming process is signalled by short beeps and terminated after successfull
programming with one long beep. After that, the system is automatically rebooted.
Important Notes:
USB recovery dongle and USB crisis recovery device must not be plugged to
the same USB controller.
Crisis recovery may take up to 5 minutes
A long beep indicated successful recovery
Crisis recovery does not include the bootblock.
61
5.5 Diagnostics Postcodes
Postcodes can be seen on a special Postcode display, either on the MSC mainboard or on
an external Postcode PCI card. There is an item in the bios setup to select the bus that
should get the postcode data: either PCI (for external cards) or LPC (for onboard displays).
If a postcode display has only 2 digits, only the lower byte of word-value postcodes will be
shown.
5.5.1 Bootblock Bios Postcodes
Code
BBH
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
95h
96h
97h
99h
Bootblock Task Description
Bootblock Early Init after Reset
Chipset Init
Bridge Init
CPU Init
System Timer Init
System I/O Init
Check forced Recovery Boot, CMOS & CMOS Backup Clear
Check BIOS Checksum
Goto BIOS, start early BIOS initialzations
Init Multi Processor
Set Huge Segment
OEM Initializations
Init Interrupt and DMA Controller
Init Memory Type
Init Memory Size
Shadow Boot Block
Init SMM
System Memory Test
Init Interrupt Vectors
Init Realtime Clock
Init Standard Video
Init Beeper
Initialize USB Controller
Init Boot
Clear Huge Segment
Boot OS
Init Security
62
5.5.2 System Bios Postcodes
Code
04h
03h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Eh
0Fh
10h
11h
12h
13h
14h
16h
17h
18h
1Ah
1Ch
20h
22h
24h
28h
29h
2Ah
2Ch
2Eh
2Fh
32h
33h
36h
38h
3Ah
3Ch
3Dh
41h
42h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Eh
4Fh
50h
51h
52h
Beeps
1-2-2-3
1-3-1-1
1-3-1-3
1-3-4-1
1-3-4-3
2-1-2-3
POST Task Description
Get CPU type
Disable Non-Maskable Interrupt (NMI)
Initialize system hardware
Disable shadow and execute code from the ROM.
Initialize chipset with initial POST values
Set IN POST flag
Initialize CPU registers
Enable CPU cache
Initialize caches to initial POST values
Initialize I/O component
Initialize fixed disk drives
Initialize Power Management
Load alternate registers with initial POST values
Restore CPU control word during warm boot
Initialize PCI Bus Mastering devices
Initialize keyboard controller
BIOS ROM checksum
Initialize cache before memory Autosize
8254 timer initialization
8237 DMA controller initialization
Reset Programmable Interrupt Controller
Test DRAM refresh
Test 8742 Keyboard Controller
Set ES segment register to 4 GB
Autosize DRAM
Initialize POST Memory Manager
Clear 512 kB Base RAM
RAM Address test
Base RAM Test
Enable cache before system BIOS shadow
Compute CPU clock speed in MHz
Initialize Phoenix Dispatch Manager
Warm start shut down
Shadow system BIOS ROM
Autosize cache
Advanced configuration of chipset registers
Load alternate registers with CMOS values
Initialize RomPilot
Initialize interrupt vectors
POST device initialization
Check ROM copyright notice
Initialize I20 support
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow video BIOS ROM
Display BIOS copyright notice
Initialize MultiBoot
Display CPU type and speed
Initialize EISA board
Test keyboard
63
Code
54h
55h
58h
59h
5Ah
5Bh
5Ch
60h
62h
64h
66h
67h
68h
69h
6Ah
6Bh
6Ch
70h
72h
76h
7Ch
7Dh
7Eh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Fh
90h
91h
92h
93h
95h
96h
97h
98h
99h
9Ah
9Ch
9Dh
9Eh
9Fh
A0h
A2h
A4h
Beeps
2-2-3-1
1-2
POST Task Description
Set key click if enabled
Configure USB devices
Test for unexpected interrupts
Initialize POST display service
Display prompt "Press F2 to enter SETUP"
Disable CPU cache
Conventional memory test
Extended memory test
Address Test on Extended Memory
Jump to UserPatch1
Configure advanced cache registers
CPU feature, MP, and APIC initialization
Enable external and CPU caches
Setup System Management Mode (SMM) area
Display external L2 cache size
Load custom defaults (optional)
Display BIOS shadow status
Display error messages
Check for configuration errors
Check for keyboard errors
Set up hardware interrupt vectors
Initialilze Intelligent System Monitoring
Initialize coprocessor if present
Disable onboard Super I/O ports and IRQs
Late POST device initialisation
Detect and install external RS232 ports
Configure non-MCD IDE controllers
Detect and install external parallel ports
Initialize PC-compatible PnP ISA devices
Re-initialize onboard I/O ports.
Configure Motheboard Configurable Devices (optional)
Initialize BIOS Data Area
Enable Non-Maskable Interrupts (NMIs)
Initialize Extended BIOS Data Area
Test and initialize PS/2 mouse
Initialize floppy controller
Determine number of ATA drives (optional)
Initialize hard-disk controllers
Program timing registers according to PIO modes
Jump to UserPatch2
Build MPTABLE for multi-processor boards
Install CD ROM for boot
Clear huge ES segment register
Fixup Multi Processor table
Enable PCI devices and ROM Scan One long, two short
beeps on checksum failure
Check for SMART Drive
Shadow option ROMs
Set up Power Management
Initialize security engine (optional)
Enable hardware interrupts
Determine number of ATA and SCSI drives
Set time of day
Check key lock
Initialize typematic rate
64
Code
A8h
AAh
ACh
AEh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B9h
BAh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
D2h
Beeps
POST Task Description
Erase F2 prompt
Scan for F2 key stroke
Enter SETUP
Clear Boot flag
Check for errors
Inform RomPilot about the end of POST.
POST done - prepare to boot operating system
store enhanced CMOS values in non-volatile area
1 One short beep before boot
Terminate QuietBoot (optional)
Check password (optional)
Initialize ACPI BIOS
Prepare Boot
Initialize DMI parameters
Clear parity checkers
Display MultiBoot menu
Clear screen (optional)
Check virus and backup reminders
Try to boot with INT 19
Initialize POST PEM Error Manager
Initialize PEM error logging
Initialize error PEM display function
Initialize PEM system error handler
PnPnd dual CMOS (optional)
Initialize note dock (optional)
Initialize note dock late
Force check (optional)
Extended checksum (optional)
Redirect Int 15h to enable remote keyboard
Redirect Int 13h to Memory Technologies
Redirect Int 10h to enable remote serial video
Remap I/O and memory for PCMCIA
Initialize digitizer and display message
Unknown interrupt or exception
65
5.5.3 Memory Detection Postcodes
Code
Calistoga Memory Detection
FFA0h
Start memory detection
FF01h
Enable MCHBAR
FF02h
Check for DRAM initialisation interrupt and reset fail
FF03h
Verify all DIMMs are DDR2 and unbuffered
FF04h
Detect an improper warm reset and handle
FF05h
Detect if ECC SO-DIMMs are present in the system
FF06h Verify all DIMMs are single or double sided and not asymmetric
FF07h
Verify all DIMMs are x8 or x16 width
FF08h Find a common CAS latency between the DIMMS and the MCH
FF09h Determine the memory frequency and CAS latency to program
FF10h
Determine the smallest common TRAS for all DIMMs
FF11h
Determine the smallest common TRP for all DIMMs
FF12h
Determine the smallest common TRCD for all DIMMs
FF13h
Determine the smallest refresh period for all DIMMs
FF14h
Verify burst length of 8 is supported by all DIMMs
FF15h
Determine the smallest tWR supported by all DIMMs
FF16h
Determine DIMM size parameters
FF17h
Program Graphics frequency and PLL settings
FF18h
Program system memory frequency
FF19h
Determine and set the mode of operation for the memory
channels
FF20h
Program clock crossing registers
FF21h
Disable Fast Dispatch
FF22h Program the DRAM Row Attributes and DRAM Row Boundary
registers
FF23h
Program the DRAM Bank Architecture register
FF24h
Program the DRAM Timing & and DRAM Control registers
FF25h
Program ODT
FF26h
Perform steps required before memory init
FF27h
Program the receive enable reference timing control register
Program the DLL Timing Control Registers , RCOMP settings
FF28h
FF29h
FF30h
FF31h
FF32h
FF33h
FF34h
FF35h
FF36h
FF37h
Enable DRAM Channel I/O Buffers
Enable all clocks on populated rows
Perform JEDEC memory initialization for all memory rows
Program PM Settings
Perform additional steps required after memory init
Program DRAM throttling and throttling event registers
Setup DRAM control register for normal operation and enable
Setup DRAM control register for normal operation and enable
Enable RCOMP
Clear DRAM initialization bit in the ICH
5.5.4 ACPI Postcodes
Code
03h
04h
05h
ABh
CDh
ACPI Codes
Enter Suspend State S3
Enter Hibernate State S4
Enter Softoff State S5
Enter Wakeup from Powerstate
End Wakeup from Powerstate
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