Epson specification for S1D15000series

MF424-21
S1D15000 Series
Technical Manual
IEEE1394
LCD
driverController
with RAM
S1R75801F00A
S1D15000
Series
Technical Manual
S1D15000 Series Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
This manual was made with recycle paper,
and printed using soy-based inks.
First issue December,1992 U
Printed May,2001 in Japan H B
4.5mm
In pursuit of “Saving” Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
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NOTICE
No parts of this material may be reproduced or duplicated in any form or by any means without the written
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Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this
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© Seiko Epson corporation 2001, All rights reserved.
i8088 and i8086 are registered trademarks of Intel Corporation.
Z80 is registered trademark of Zilog Corporation.
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4.5mm
The information of the product number change
Starting April 1, 2001 the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
●DEVICES (Example : S1D15605D00B100)
S1
D
15605
D
00B1
00
Packing specification
Specifications
Shape (D:Chip, T:TCP, F:QFP)
Model number
Model name (D:LCD Driver)
Product classification (S1:Semiconductors)
Comparison table between new and previous number
Previous number
SED1510D0C
SED1510F0C
SED1520DAA
SED1520DAB
SED1520F0A
SED1520FAA
SED1521F0A
SED1521FAA
SED1522F0A
SED1522FAA
SED1526F0A
SED1526FAA
SED1526FBA
SED1526FEA
SED1526FEY
SED1526T0A
SED1528DBB
SED1528F0A
SED1530D0A
SED1530D0B
SED1540D0A
SED1540D0B
SED1540F0A
SED1560D0B
New number
S1D15100D00C*
S1D15100F00C*
S1D15200D10A*
S1D15200D10B*
S1D15200F00A *
S1D15200F10A *
S1D15201F00A *
S1D15201F10A *
S1D15202F00A *
S1D15202F10A *
S1D15206F00A *
S1D15206F10A *
S1D15206F11A *
S1D15206F14A *
S1D15206F14Y *
S1D15206T00A *
S1D15208D11B*
S1D15208F00A *
S1D15300D00A*
S1D15300D00B*
S1D15400D00A*
S1D15400D00B*
S1D15400F00A *
S1D15600D00B*
Previous number
SED1560DAB
SED1561D0B
SED1561DAB
SED1562D0B
SED1565D0B
SED1565D1B
SED1565D2B
SED1565DBB
SED1565DBE
SED1565T0*
SED1565T0B
SED1566D0B
SED1566D1B
SED1566D2B
SED1566DBB
SED1566T0*
SED1567D0B
SED1567D1B
SED1567D2B
SED1567DBB
SED1567T0*
SED1568D0B
SED1568DBB
SED1569D0B
New number
S1D15600D10B*
S1D15601D00B*
S1D15601D10B*
S1D15602D00B*
S1D15605D00B*
S1D15605D01B*
S1D15605D02B*
S1D15605D11B*
S1D15605D11E*
S1D15605T00**
S1D15605T00B *
S1D15606D00B*
S1D15606D01B*
S1D15606D02B*
S1D15606D11B*
S1D15606T00**
S1D15607D00B*
S1D15607D01B*
S1D15607D02B*
S1D15607D11B*
S1D15607T00**
S1D15608D00B*
S1D15608D11B*
S1D15609D00B*
Previous number
SED1569DBB
SED1570D0A
SED1570D0B
SED1575D0B
SED1575D3B
SED1575DAB
SED1575T0*
SED1575T0A
SED1575T3*
SED1577D0B
SED1577D3B
SED1577T0*
SED1577T3*
SED1578D0B
SED157AD0B
SED157ADAB
SED157ADBB
SED157AT0A
SED15A6D0B
SED15A6D1B
SED15A6D2B
SED15A6T0*
SED15B1D0B
SED15B1D1B
SED15B1D2B
SED15B1T0*
New number
S1D15609D11B*
S1D15700D00A*
S1D15700D00B*
S1D15705D00B*
S1D15705D03B*
S1D15705D10B*
S1D15705T00**
S1D15705T00A*
S1D15705T03**
S1D15707D00B*
S1D15707D03B*
S1D15707T00**
S1D15707T03**
S1D15708D00B*
S1D15710D00B*
S1D15710D10B*
S1D15710D11B*
S1D15710T00A*
S1D15A06D00B*
S1D15A06D01B*
S1D15A06D02B*
S1D15A06T00**
S1D15B01D00B*
S1D15B01D01B*
S1D15B01D02B*
S1D15B01T00**
S1D15100 Series
S1D15200 Series
S1D15210 Series
S1D15206 Series
S1D15300 Series
S1D15400 Series
S1D15600/601/602
Series
S1D15605 Series
S1D15700 Series
S1D15705 Series
S1D15710 Series
S1D15A06 Series
S1D15B01 Series
CONTENTS
Selection Guide
1. S1D15100 Series
2. S1D15200 Series
3. S1D15210 Series
4. S1D15206 Series
5. S1D15300 Series
6. S1D15400 Series
7. S1D15600/601/602 Series
8. S1D15605 Series
9. S1D15700 Series
10. S1D15705 Series
11. S1D15710 Series
12. S1D15A06 Series
13. S1D15B01 Series
S1D15000 Series
Selection Guide
■ LCD drivers with RAM for smalland medium-sized displays
Ultra-low power consumption and on-chip RAM make this series ideal for compact LCDbased equipment.
S1D15000 (SED1500) series
Part number
Supply voltage LCD voltage
range (V)
range (V)
Duty
Display Microprocessor Frequency
Segment Common RAM (bits)
interface
(KHz)
S1D15100D00C *
(SED1510D 0C)
S1D15100F00C* 0.9 to 6.0
(SED1510F0C)
1.8 to 6.0
1/4
32
4
128 bit
Serial
S1D15200***** 2.4 to 7.0
(SED1520* **)
3.5 to 13
1/8 to 1/32
61
16
2,560 bit
8 bit
S1D15201***** 2.4 to 7.0
(SED1521* **)
3.5 to 13
1/8 to 1/32
80
–
2,560 bit
8 bit
S1D15202***** 2.4 to 7.0
(SED1521* **)
3.5 to 13
1/8 to 1/32
69
8
2,560 bit
8 bit
S1D15206D **A*
(SED1526D *A)
S1D15206D **B*
(SED1526D *B)
S1D15206F**A*
(SED1526F*A)
S1D15206T**A*
(SED1526T*A)
S1D15208D **A*
(SED1528D *A)
S1D15208D **B*
(SED1528D *B)
S1D15208F**A*
(SED1528F*A)
S1D15208T**A*
(SED1528T*A)
S1D15300D00A*
(SED1530D 0A)
S1D15300D10A*
(SED1530D AA)
S1D15300D00B*
(SED1530D 0B)
S1D15300D10B*
(SED1530D AB)
S1D15300T10A *
(SED1530TAA)
S1D15301D00A*
(SED1531D 0A)
S1D15301D00B*
(SED1531D 0B)
S1D15301T00A *
(SED1531T0A )
S1D15302D00A*
(SED1532D 0A)
S1D15302D11A*
(SED1532D BA)
S1D15302D00B*
(SED1532D 0B)
S1D15302D11B*
(SED1532D BB)
S1D15302T00A *
(SED1532T0A )
S1D15302T11A *
(SED1532TBA)
Package
Application/additional
features
Small segment-type
LCD display. Common
QFP12-48pin and data interface.
Al pad chip
18(internal)
18(internal,
external) or Chip, TCP
2(external)
18(internal,
external) or Chip, TCP
2(external)
18(internal,
external) or Chip, TCP
2(external)
After service parts
After service parts
After service parts
Al pad chip
2.4 to 6.0
3.5 to
Supply
voltage
×3
1/8,1/9,
1/16,1/17
80
17
80×33 bit
8-bit
parallel
or Serial
20
Au bump chip DC/DC×3
(S1D15206*00**•VREG)
QFP5-128pin (S1D15206 14 •no VREG)
* **
TCP
Al pad chip
2.4 to 6.0
3.5 to
Supply
voltage
×3
1/32,1/33
64
33
80×33 bit
8-bit
parallel
or Serial
20
Au bump chip DC/DC×3
(S1D15208*00**•VREG)
QFP5-128pin (S1D15208*14**•no VREG)
TCP
Al pad chip
2.4 to 6.0
4.5 to 16
1/32,1/33
100
33
132×65 bit
8-bit
parallel
or Serial
–
Built-in power circuit for LCD
Al pad chip (DC/DC×4)
S1D15300D00**(SED1530 0 )
**
Au bump chip Common : Right
side
S1D15300 10**(SED1530 A )
**
Au bump chip Common :*Both
side
TCP
Al pad chip
2.4 to 6.0
4.5 to 16
1/64,1/65
132
–
132×65 bit
8-bit
parallel
or Serial
–
Built-in power circuit for LCD (DC/DC×4)
Au bump chip S1D15301*00 **(SED1531*0*)
Common : Right side
TCP
Al pad chip
Al pad chip
2.4 to 6.0
4.5 to 16
1/64,1/65
100
33
132×65 bit
8-bit
parallel
or Serial
–
Built-in power circuit for LCD
(DC/DC×4)
Au bump chip S1D15302 00 (SED1532 0 )
* **
**
Common : Right side
Au bump chip S1D15302 11 (SED1532 B )
* **
**
Common : Left side
TCP
TCP
TCP : Tape Carrier Package
Part number
Supply voltage LCD voltage
range (V)
range (V)
S1D15303D15B*
2.4 to 6.0
(SED1533D FB)
S1D15400D00A*
(SED1540D 0A)
S1D15400D00B*
(SED1540D 0B)
S1D15400F00A *
(SED1540F0A )
S1D15600D00A*
(SED1560D 0A)
S1D15600D10A*
(SED1560D AA)
S1D15600D00B*
(SED1560D 0B)
S1D15600D10B*
(SED1560D AB)
S1D15600T00B *
(SED1560T0B )
S1D15600T26A *
(SED1560TQA)
S1D15601D00A*
(SED1561D 0A)
S1D15601D00B*
(SED1561D 0B)
S1D15601D10B*
(SED1561D AB)
S1D15601T00B *
(SED1561T0B )
S1D15601T10B *
(SED1561TAB)
S1D15601T26A *
(SED1561TQA)
S1D15602D00A*
(SED1562D 0A)
S1D15602D00B*
(SED1562D 0B)
S1D15602T00B *
(SED1562T0B )
S1D15602T26A *
(SED1562TQA)
S1D15605D11B*
(SED1565D BB)
S1D15605D00B*
(SED1565D 0B)
S1D15605D01B*
(SED1565D 1B)
S1D15605D02B*
(SED1565D 2B)
S1D15605T00A *
(SED1565T0A )
S1D15605T00B *
(SED1565T0B )
S1D15605T00C*
(SED1565T0C)
4.5 to 16
Duty
1/17
Display Microprocessor Frequency
Segment Common RAM (bits)
interface
(KHz)
116
17
132×65 bit
8-bit
parallel
or Serial
2,560 bit
8-bit
parallel
–
Package
Application/additional
features
Built-in power circuit for LCD
Au bump chip (DC/DC×4)
Common : Left side no VREF
Al pad chip
2.4 to 7.0
3.5 to 11
1/3, 1/4
73
3, 4
18(internal),
4(external) Au bump chip
QFP5-100pin
Al pad chip
Built-in power circuit
for LCD (DC/DC×3)
S1D15600 00B
Au bump chip (SED1560 *0B) *
*
: 1/9 bias
Au bump chip S1D15600 10B
* *
(SED1560*AB)
TCP
: 1/7 bias
Al pad chip
2.4 to 6.0
6.0 to 16
1/48,1/49,
1/64,1/65
102
65
166×65 bit
8-bit
parallel
or Serial
18
QTCP
Al pad chip
2.4 to 6.0
6.0 to 16
1/24,1/25,
1/32,1/33
134
33
166×65 bit
8-bit
parallel
or Serial
18
Built-in power circuit
Au bump chip for LCD (DC/DC×3)
S1D15601 00B
Au bump chip (SED1561 *0B) *
*
: 1/7 bias
TCP
S1D15601*10B *
(SED1561*AB)
TCP
: 1/5 bias
QTCP
Al pad chip
2.4 to 6.0
6.0 to 16
1/16,1/17
(1/5 bias)
150
17
166×65 bit
8-bit
parallel
or Serial
Au bump chip
18
TCP
Built-in power circuit for
LCD (DC/DC×3)
QTCP
Au bump chip
Au bump chip
Au bump chip
1.8 to 5.5
1/65
4.5 to 16 (1/7,1/9 bias)
132
65
132×65 bit
8-bit
parallel
or Serial
33
Built-in power circuit
Au bump chip for LCD (DC/DC×4)
TCP
TCP
TCP
Part number
S1D15606D11B*
(SED1566D BB)
S1D15606D00B*
(SED1566D 0B)
S1D15606D01B*
(SED1566D 1B)
S1D15606D02B*
(SED1566D 2B)
S1D15606T00A *
(SED1566T0A )
S1D15607D11B*
(SED1567D BB)
S1D15607D00B*
(SED1567D 0B)
S1D15607D01B*
(SED1567D 1B)
S1D15607D02B*
(SED1567D 2B)
S1D15607T00B *
(SED1567T0B )
S1D15607T00C*
(SED1567T0C)
S1D15608D11B*
(SED1568D BB)
S1D15608D00B*
(SED1568D 0B)
S1D15609D11B*
(SED1569D BB)
S1D15609D00B*
(SED1569D 0B)
S1D15609T****
(SED1569Txx *)
S1D15A06D00B*
(SED15A6D0B )
S1D15A06T00A*
(SED15A6T 0A*)
S1D15B01D00B*
(SED15B1D0B )
S1D15B01T00A*
(SED15B1T 0A)
S1D15E00D00B*
(SED15E0D0B )
S1D15E00T00A*
(SED15E0T 0A)
S1D15705D00B*
(SED1575D 0B)
S1D15705D03B*
(SED1575D 3B)
S1D15705T00A *
(SED1575T0A )
S1D15705T03A *
(SED1575T3A )
S1D15707D00B*
(SED1577D 0B)
S1D15707D03B*
(SED1577D 3B)
S1D15707T00A *
(SED1577T0A )
S1D15707T03A *
(SED1577T3A )
S1D15710D00B*
(SED157AD0B )
S1D15710T00A *
(SED157AT 0A*)
Supply voltage LCD voltage
range (V)
range (V)
Duty
Display Microprocessor Frequency
Segment Common RAM (bits)
interface
(KHz)
Package
Application/additional
features
Au bump chip
Au bump chip
1.8 to 5.5
1/49
4.5 to 16 (1/6,1/8 bias)
132
49
132×65 bit
8-bit
parallel
or Serial
33
Built-in power circuit
Au bump chip for LCD (DC/DC×4)
Au bump chip
TCP
Au bump chip
Au bump chip
1.8 to 5.5
1/33
4.5 to 16 (1/5,1/6 bias)
132
33
132×65 bit
8-bit
parallel
or Serial
33
Au bump chip Built-in power circuit
for LCD (DC/DC×4)
Au bump chip
TCP
TCP
1.8 to 5.5
1/55
4.5 to 16 (1/6,1/8 bias)
1.8 to 5.5
1/53
4.5 to 16 (1/6,1/8 bias)
132
55
132×65 bit
8-bit
parallel
or Serial
132×65 bit
8-bit
parallel
or Serial
33
Au bump chip Built-in power circuit
for LCD (DC/DC×4)
Au bump chip
Au bump chip
132
53
33
Built-in power circuit
Au bump chip for LCD (DC/DC×4)
TCP
1.8 to 5.5
4.5 to 16
1/55
102
55
102×65 bit
8-bit
parallel
or Serial
33
Au bump chip Reduced ext. parts
Built-in power circuit.
TCP
1.8 to 5.5
4.5 to 16
1/65
132
65
132×65 bit
8-bit
parallel
or Serial
33
Au bump chip Built-in self-refreshing
function.
TCP
1.8 to 3.6
3.2 to 10
1/100
132
100
132×100 bit
Serial
Can be select
Au bump chip
4-line MLS driving
TCP
3.6 to 5.5
4.5 to 16
1/65
168
65
200×65 bit
8-bit
parallel
or Serial
22
4.5 to 16
1/65
168
65
200×65 bit
8-bit
parallel
or Serial
22
4.5 to 16
1/33
200
33
200×65 bit
8-bit
parallel
or Serial
22
4.5 to 16
1/33
200
33
200×65 bit
8-bit
parallel
or Serial
22
4.5 to 18
1/65
224
65
224×65 bit
8-bit
parallel
or Serial
22
2.4 to 3.6
3.6 to 5.5
2.4 to 3.6
3.6 to 5.5
2.4 to 3.6
3.6 to 5.5
2.4 to 3.6
1.8 to 5.5
Built-in power circuit
Au bump chip for LCD (DC/DC×4)
TCP
Built-in power circuit
for LCD (DC/DC×4)
Built-in power circuit
Au bump chip for LCD (DC/DC×4)
TCP
Built-in power circuit
for LCD (DC/DC×4)
Au bump chip Built-in power circuit
for LCD
TCP
TCP : Tape Carrier Package
1. S1D15100 Series
Rev. 1.0
Contents
1. DESCRIPTION ................................................................................................................................................ 1-1
2. FEATURES ...................................................................................................................................................... 1-1
3. BLOCK DIAGRAM .......................................................................................................................................... 1-1
4. PAD LAYOUT AND COORDINATES .............................................................................................................. 1-2
5. PIN LAYOUT (S1D1500F00C ) ..................................................................................................................... 1-3
*
6. PIN DESCRIPTION ......................................................................................................................................... 1-3
7. FUNCTIONAL DESCRIPTION ........................................................................................................................ 1-4
8. COMMANDS ................................................................................................................................................... 1-7
9. THE SUPPLY VOLTAGES .............................................................................................................................. 1-8
10. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 1-9
11. DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 1-9
12. AC ELECTRICAL CHARACTERISTICS ........................................................................................................ 1-10
–i–
Rev. 1.0
S1D15100 Series
1. DESCRIPTION
2. FEATURES
The S1D15100Series is a segment driver IC for
1/4-duty LCD panels. It features 150 µW maximum
power dissipation and a wide operating supply voltage
range, making it ideal for use in battery-powered devices.
The S1D15100 series incorporates an LCD driving power
circuit and allows simple configuration of the interface
with a microcomputer, achieving a handy type unit at low
cost.
•
•
•
•
•
•
•
•
•
•
•
3. BLOCK DIAGRAM
SEG0
to
SEG31
1/4-duty LCD segment driver
150 µW maximum power dissipation
Serial data interface
128 bits of display data RAM
On-chip oscillator
LCD drive voltage generator
Four common driver outputs
32 segment driver outputs
0.9 to 6.0 V supply for logic circuitry operation
1.8 to 6.0 V supply for LCD driver operation
Series specification
S1D15100D00C* : chip (Al pad)
S1D15100F00C* : QFP12-48pin
COM0 COM1 COM2 COM3
VDD
V1
V2
LCD drive
voltage
generator
Segment drivers
Common drivers
V3
VSS
OSC1
Address
counter
Address
decoder
Display data memory
Common
counter
Timing
generator
circuit
OSC2
Command decoder
SI
CK
Command/data register
C/D
CS
Rev. 1.0
EPSON
1–1
S1D15100 Series
4. PAD LAYOUT AND COORDINATES
(S1D15100D00C*)
Sectional dimensions
2500
µm
30
35
Pad
25
300 ± 30µm
MAX30
40
D1510D0B
MAX50µm
20
2500
µm
Size of pad opening
45
15
100µm
1
5
Chip size:
Chip pitch:
100µm
10
2500µm × 2500µm
525µm
Pad center coordinates
Unit: µm
No.
Pin name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OSC1
OSC2
V1
V2
V3
VSS
VDD
CK
SI
CS
C/D
COM0
COM1
COM2
COM3
VREG
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
X coordinate Y coordinate
-898
-738
-578
-418
-258
-98
63
223
383
543
703
863
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-898
-738
-578
-418
-258
-98
63
224
383
543
703
863
No.
Pin name
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
SEG 24
SEG 25
SEG 26
SEG 27
SEG 28
SEG 29
SEG 30
SEG 31
X coordinate Y coordinate
898
738
578
418
258
98
-63
-223
-383
-543
-703
-863
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
898
738
578
418
258
98
-63
-223
-383
-543
-703
-863
Origin: Center of the chip
Chip size: 2,500 × 2,500
1–2
EPSON
Rev. 1.0
S1D15100 Series
5. PINOUT (S1D15100F00C*)
36
25
37
24
Index
48
13
1
12
No.
Name
No.
Name
No.
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OSC1
OSC2
V1
V2
V3
VSS
V DD
CK
SI
CS
C/D
COM0
COM1
COM2
COM3
V REG
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
6. PIN DESCRIPTION
Pin Name
I/O
Description
Q’ty
VDD
Power supply
Plus power terminal.
Common to the microcomputer power terminal VCC.
1
V SS
Power supply
Minus power supply.
A 0V terminal to be connected to the system GND.
1
V1
V2
O
Power level monitor terminal for liquid crystal drive.
The levels V 1 = 1/3 × V3 and V2 = 2/3 × V3 are generated from
the inside of S1D15100F00C*.
2
V3
Power supply
Power terminal for liquid crystal drive.
Potential relations: VDD > V3.
1
SI
I
Serial data input.
Input of display data and of commands to control operation of
S1D15100F00C*. When display data is input, the relations
between display data input and segment ON/OFF are as follows:
SI input “0” → OFF, SI input “1” → ON
1
CK
I
Shift clock input of serial data (SI input).
SI input data is read bit by bit in the serial register at the CK
input leading edge.
1
C/D
I
Identification of SI input as data or command (in case of
S1D15100F00C* only). The LOW level indicates data, and the
HIGH level does commands.
1
CS
I
Chip select signal input (in case of S1D15100F00C * only).
When CS input is changed from the HIGH level to the LOW
level, S1D15100F00C* can accept SI inputs.
The CK counter is set to the initial state when the CS input is
changed from the HIGH level to the LOW level.
1
OSC1
OSC2
I
O
Oscillation resistance connection terminal
2
SEG0 to SEG31
O
Segment signal for liquid crystal drive
32
COM0 to COM3
O
Common signal for liquid crystal drive
4
VREG
O
Test terminal. Keep it open.
1
Total 48
Rev. 1.0
EPSON
1–3
S1D15100 Series
7. FUNCTIONAL DESCRIPTION
Command/Data Register
◊ When the CK counter counts 8 of shift clock input (CK
input) (reads the input 8-bit serial data), the serial data
taken in the command/data register is output to the
display data memory (RAM) if the input serial data is
a display data, or is output to the command decoder if
it is a command data.
◊ S1D15100 Serise identifies input serial data (SI input)
as display data or command data judging from C/D
input. It displays display data when C/D input is LOW
level or command data when the input is HIGH level.
◊ S1D15100 Serise reads and identifies C/D input at the
timing on the rising edge of 8xn of shift clock input
(CK input) from the CS = LOW level. (n=1, 2, 3, ...)
◊ The command/data register consists of an 8-bit serial
register and a 3-bit CK counter.
◊ When CS input changes from the HIGH level to the
LOW level, S1D15100 Serise comes to accept SI
inputs. Also, the CK counter is initialized when CS
input changes from the HIGH level to the LOW level.
S1D15100 Serise always accepts SI inputs. When the
built-in timing generator (CR oscillator) starts
oscillating, the CK counter is initialized.
◊ The serial register takes in serial data D7, D6, ... D0 in
this order from the SI terminal on the rising edge of the
CK. At the same time, the CK counter starts counting
the serial clock. The CK counter, when counting 8 on
the serial clock, returns to the initial state.
◊ So, serial data is taken in to the serial register in 8 bits
and is processed.
CS
SI
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
Address
6
7
8
CK
C/D
Command Decoder
◊ When the command/data register data specifies any
command (when C/D input is HIGH level when serial
data is input), the command decoder takes in and
decode the data of the command/data register to control
S1D15100F00C*.
Display Data Memory
The format of the 32 × 4-bit memory is shown in the
following figure.
0
1
2
3
4
5
29
30
31
0
1
Bit
2
3
Each 8-bit display data byte loaded from the command/
data register is stored in two consecutive addresses as
shown in the following figure. The upper four bits are
stored at the location specified by the address counter,
and the lower four bits, at the next location. The address
counter is automatically incremented by two.
1–4
EPSON
Bit 3
D7
D6
Bit 0
Bit 3
D4
D3
D5
Current address
Bit 0
D2
D1
D0
Current address + 1
Rev. 1.0
S1D15100 Series
A single 4-bit word can be written to memory using the
Data Memory Write command as shown in the following
figure. The lower four bits are stored at the location
specified by the address counter. The address counter is
automatically incremented by one.
1
0
0
∗
D3
D2
D1
Bit 3
D2
D1
Note
∗ = don’t care
◊ The display data memory address is automatically
incremented by 2 when a 8-bit display data (C/D =
LOW level) is stored, or incremented by 1 when a 4bit data is stored by the display data re-write command.
◊ After the display data is written in the RAM, the RAM
address is held as shown below unless the address is
reset:
After writing a 8-bit display data ...
the final write address is incremented by 2.
After rewriting a 4-bit display data ...
the final rewrite address is incremented by 1.
◊ Data in the display data memory synchronizes with the
COM0 to COM3 signals and is output in 32 bits to the
segment driver.
The relations of the display data memory, the segment
terminal and common signal selection timing are as
follows:
D0
Bit 0
D3
D0
Address = n
SEG SEG SEG SEG SEG SEG SEG SEG
0
1
2
3
4
5
6
7
SEG SEG SEG
29 30 31
COM0
0
COM1
1
COM2
2
COM3
3
Bit
0
1
2
3
4
5
6
7
29
30
31
Address
Address Counter
Timing Generator
◊ The address counter is a presettable type to give 5-bit
addresses to the display data memory.
◊ In case of S1D15100 Serise, any address can be set
when the address set command is used.
◊ In case of S1D15100 Serise, set addresses are
automatically incremented by 2 when an 8-bit display
data is stored (C/D = LOW level), or incremented by
1 when a 4-bit data is stored by the display data
memory rewrite command.
◊ The address decoder, after counting Address 31, counts
0 at the next counting and repeats as follows:
A low-power oscillator can be constructed using an
external feedback resistor as shown in the following
figure.
Address 0
OSC1
Alternatively, an 18 kHz external clock can be input on
OSC1, and OSC2 left open, as shown in the following
figure.
OSC1
Address 31
External clock
The address decoder sets addresses 0 to 31 of the display
data memory where the display data of address counter
is written.
OSC2
Rf
Address Decoder
Rev. 1.0
680 kΩ
OSC2
Open
Common Counter
The timing generator clock signal is frequency-divided
by the common counter to generate both the common
drive timing and the alternating frame timing.
EPSON
1–5
S1D15100 Series
Segment and Common Drivers
The 32 segment drivers and the four common drivers are
4-level outputs that switch between VDD and the V1, V2
and V3 LCD driver voltage levels.
The output states are determined by the display data
values and the common counter as shown in the following figure. The outputs are used to drive a 1/3-bias, 1/4duty LCD panel.
Frame period
COM0
VDD
V1
V2
V3
COM1
COM2
COM3
VDD
V1
V2
V3
1–6
COM1
COM2
COM3
0
0
0
0
0
0
All segments are OFF.
VDD
V1
V2
V3
Seg 0
to
Seg 31
COM0
1
0
Segments connected to COM0 are ON.
VDD
V1
V2
V3
0
1
0
0
Segments connected to COM1 are ON.
VDD
V1
V2
V3
Segments connected to COM1 or COM3 are ON.
VDD
V1
V2
V3
All segments are ON.
0
1
EPSON
1
1
0
1
1
1
Rev. 1.0
S1D15100 Series
8. COMMANDS
The S1D15100F00C * samples C/D on every eighth
rising edge of CK. If C/D is HIGH, the command/data
register contents are latched into the command decoder.
The command decoder executes the following six commands.
Address Set
Set the address counter to the value specified by D0 to
D4.
0
0
0
D4
D3
D2
D1
D0
Addresses are incremented by 2 each time a display data
(8-bit) is input. The relations between D4 to D0 and
addresses are as follows:
Display Start
Return to normal display mode. The display memory
data is output to the display.
0
D3
0
0
0
0
D2
0
0
0
0
D1
0
0
1
1
D0
0
1
0
1
Address
0
1
2
3
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
∗
∗
0
0
∗
∗
D3
Bit 3
28
29
30
31
∗
∗
∗
∗
D2
D1
D0
Data are allocated to each bit of the display data memory
as follows:
Bit 0
D2
D1
D0
Address = n
Note: ∗ = don’t care
Display ON
Turn all LCD segments ON. The display memory data
is not affected.
0
∗
Memory Write
Store the data D0 to D3 at the location specified by the
address counter. The address counter is automatically
incremented by one. The other display memory locations are not affected.
D3
1
1
1
1
∗
Note: ∗ = don’t care
1
D4
0
0
0
0
1
Reset
Reset the S1D15100F00C* . The S1D15100F00C *
then enters normal operating mode, and the display turns
OFF.
1
1
0
∗
∗
∗
∗
∗
∗
Note: ∗ = don’t care
Note: ∗ = don’t care
Display OFF
Turn all LCD segments OFF. The display memory data
is not affected.
0
1
0
∗
∗
∗
∗
∗
Note: ∗ = don’t care
Rev. 1.0
EPSON
1–7
S1D15100 Series
9. SUPPLY VOLTAGES
In addition to VDD, there are three LCD supply voltages:
V1 , V2 and V3. V3 is supplied externally, whereas V1 and
V2 are generated internally. V 1, V2 and V3 are given by
the following equations.
V1 = VDD – 1/3V LCD
V2 = VDD – 2/3V LCD
V3 = VDD – VLCD
where VLCD is the LCD drive voltage. The voltages must
be such that
VDD ≥ V1 ≥ V2 ≥ V3
LCD supply voltage connections when the LCD drive
supply is connected to VSS are shown in figure 1, and the
connections when the drive supply is independent of
VSS, in Figure 2.
When there is a lot of distortion in the LCD drive
waveforms, connect bleeder resistors as shown in the
following figure.
VDD
R1
V1
R2
V2
R3
V3
VSS
VDD
V1
V2
V3
VSS
Figure 1. LCD drive supply connected to V SS
VDD
V1
V2
V3
VSS
Figure 2. LCD drive supply not connected to VSS
1–8
EPSON
Rev. 1.0
S1D15100 Series
10. ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage range
250
Unit
V
V
V
V
mW
Topg
–20 to 75
°C
T stg
–65 to 150
°C
Tsol
260
°C
400 • 10
°C•Min
Symbol
LCD supply voltage range
Input voltage range
Output voltage range
Power dissipation
Operating temperature
range
Storage temperature range
Soldering temperature
(10 sec at leads)
Heat resistance
VSS
V3
Vl
VO
PD
Rating
–7.0 to 0.3
–7.0 to 0.3
VSS –0.3 to 0.3
VSS –0.3 to 0.3
Note: All voltages shown are specified on a
VDD = 0 V basis.
11. DC ELECTRICAL CHARACTERISTICS
VDD = 0V, VSS = –5.0 ±0.5 V, Ta = –20 to 75 °C unless otherwise noted
Parameter
Supply voltage
LCD supply voltages
Quiescent supply current
Symbol
V SS
V1
V2
V3
IDDQ
IDD1
Supply current
IDD2
LOW-level input voltage
HIGH-level input voltage
Input leakage current
SEG0 to SEG31 and COM0 to
COM3 LOW-level output voltage
SEG0 to SEG31 and COM0 to
COM3 HIGH-level output voltage
Output leakage current
Condition
VSS = –6.0 V, VIN = VDD
Display mode, Rf = 680 KΩ,
VSS = –5.0 V
Input mode, VSS = –5.0 V,
fck = 200 kHz
Rating
Typ.
—
1/3 × V3
2/3 × V3
—
0.05
Max.
–0.9
—
—
–1.8
1.0
—
20.0
30.0
—
100
250
VSS
0.2 VSS
—
—
—
0.05
0.8 VSS
VDD
2.0
V
V
µA
Unit
V
V
µA
µA
VIL
V IH
ILI
VSS ≤ VIN ≤ VDD
V OL
IOL = 0.1 mA
—
—
V SS+ 0.4
V
V OH
IOH = –0.1 mA
–0.4
—
—
V
—
—
—
—
0.05
18
16
5.0
5.0
—
—
8.0
µA
—
5.0
7.5
—
10.0
50.
VSS ≤ VOUT ≤ VDD
VSS = –5.0 V, Rf = 680 ±2% kΩ
Oscillator frequency
fOSC
VSS = –3.0 V, Rf =680 ±2% kΩ
Input terminal capacity
CI
Ta = 25°C, f = 1 MHz
V3 = –5.0 V, I ∆VON I = 0.1 V,
SEG0 to SEG31 and COM0 to
Ta = 25 °C
RON
COM3 ON resistance
V3 = –0.3 V, I ∆VON I = 0.1 V,
*1
Ta = 25 °C
*1 The internal power impedance is not included in the LCD driver on resistance (RON).
Rev. 1.0
Min.
–6.0
—
—
–6.0
—
ILO
EPSON
kHz
pF
kΩ
1–9
S1D15100 Series
12. AC ELECTRICAL CHARACTERISTICS
VDD = 0 V, VSS = –5.0 ±0.5 V, Ta = –20 to 75 °C
Parameter
Symbol
CK period
CK LOW-level pulsewidth
CK HIGH-level pulsewidth
SI to CK setup time
CK to SI hold time
CS LOW-level puisewidth
CS HIGH-level pulsewidth
tCYC
tPWL1
tPWH1
tDW1
tDH1
tPWL2
tPWH2
CS to CK setup time
tDW2
CK to CS hold time
tDH2
C/D to CK setup time
tDW3
CK to C/D hold time
tDH3
Rise time
Fall time
Condition
tPWL2 ≥ 8tCYC
Referenced to the rising edge of the
first CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
tr
tf
Min.
900
400
400
100
200
7200*1
400
Rating
Typ.
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
100
—
—
ns
200
—
—
ns
9
—
—
µs
1
—
—
µs
—
—
—
—
50
50
ns
ns
Min.
10
4.5
4.5
1.2
2.3
80*1
4.5
Rating
Typ.
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
1.2
—
—
µs
2.3
—
—
µs
100
—
—
µs
11
—
—
µs
—
—
—
—
50
50
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
*1 tCYC × 8
VDD = 0 V, VSS = –6.0 to –1.5 V, Ta = –20 to 75 °C
Parameter
Symbol
CK period
CK LOW-level puisewidth
CK HIGH-level pulsewidth
SI to CK setup time
CK to SI hold time
CS LOW-level pulsewidth
CS HIGH-level pulsewidth
tCYC
tPWL1
tPWH1
tDW1
tDH1
tPWL2
tPWH2
CS to CK setup time
tDW2
CK to CS hold time
tDH2
C/D to CK setup time
tDW3
CK to C/D hold time
tDH3
Rise time
Fall time
Condition
tPWL2 ≥ 8tCYC
Referenced to the rising edge of the
first CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
tr
tf
Unit
µs
µs
µs
µs
µs
µs
µs
*1 tCYC × 8
1–10
EPSON
Rev. 1.0
S1D15100 Series
Timing Chart
t PWH2
t PWL2
CS
t DH2
t DW2
tCYC
tPWH1
CK
t PWL1
t DW1
tf
tr
t DH1
SI
t DW3
t DH3
C/D
Timing measurement
Rev. 1.0
0.2VSS
0.2VSS
0.8VSS
0.8VSS
EPSON
1–11
2. S1D15200 Series
Rev. 1.1
Contents
1. DESCRIPTION ................................................................................................................................................2-1
2. FEATURES ......................................................................................................................................................2-1
3. BLOCK DIAGRAM ........................................................................................................................................... 2-2
4. PIN LAYOUT ................................................................................................................................................... 2-3
5. PAD .................................................................................................................................................................2-4
6. PIN DESCRIPTION ......................................................................................................................................... 2-6
7. FUNCTION DESCRIPTION .............................................................................................................................2-8
8. COMMANDS ................................................................................................................................................. 2-14
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 2-20
10. ELECTRICAL CHARCTERISTICS ................................................................................................................ 2-20
11. MPU INTERFACE CONFIGURATION ..........................................................................................................2-26
12. LCD DRIVE IINTERFACE CONFIGURATION .............................................................................................. 2-27
13. LCD PANEL WIRING EXAMPLE .................................................................................................................. 2-29
–i–
Rev. 1.1
S1D15200 Series
1. DESCRIPTION
2. FEATURES
The S1D15200 series of dot matrix LCD drivers are
designed for the display of characters and graphics. The
drivers generate LCD drive signals derived from bit
mapped data stored in an internal RAM.
The drivers are available in two configurations
The S1D15200 series drivers incorporate innovative
circuit design strategies to achieve very low power
dissipation at a wide range of operating voltages.
These features give the designer a flexible means of
implementing small to medium size LCD displays for
compact, low power systems.
• The S1D15200 which is able to drive two lines of
twelve characters each.
• The S1D15201 which is able to drive 80 segments for
extention.
• The S1D15202 which is able to drive one line of
thirteen characters each.
• Fast 8-bit MPU interface compatible with 80- and 68family microcomputers
• Many command set
• Total 80 (segment + common) drive sets
• Low power — 30 µW at 2 kHz external clock
• Wide range of supply voltages
VDD – VSS: –2.4 to –7.0 V
VDD – V5: –3.5 to –13.0 V
• Low-power CMOS
Line-up
Product
Name
S1D15200*00**
S1D15201*00**
S1D15202*00**
S1D15200*10**
S1D15201*10**
S1D15202*10**
Clock Frequency
Applicable Driver
On-Chip External
18 kHz
—
18 kHz
—
—
—
18 kHz
18 kHz
18 kHz
2 kHz
2 kHz
2 kHz
S1D15200*00**, S1D15201*00**
S1D15200*00**, S1D15202*00**
S1D15202*00**, S1D15201*00**
S1D15200*10**, S1D15201*10**
S1D15200*10**, S1D15200*10**
S1D15200*10**, S1D15201*10**
Number Number
of SEG of CMOS
Duty
Drivers Drivers
61
16
1/16, 1/32
80
0
1/8 to 1/32
69
8
1/8, 1/16
61
16
1/16, 1/32
80
0
1/8 to 1/32
69
8
1/8, 1/16
• Package code (For example S1D15200)
S1D15200T : TCP
S1D15200F**A* (QFP5-100pin)
S1D15200F**** : PKG
S1D15200F**C* (QFP15-100pin)
S1D15200D**** : Chip
S1D15200D**A* (Al-pad)
S1D15200D**B* (Au-bump)
S1D15200D**E* (Au-bump)
Rev. 1.1
EPSON
2–1
S1D15200 Series
3. BLOCK DIAGRAM
VSS
VDD
SEG0 to SEG60
V1,V2,V3,V4,V5
COM0 to COM15
An example of S1D15200*10A*:
LCD drive circuit
Display data RAM
(2560-bit)
I/O buffer
Display data latch circuit
Line address decoder
Line counter
Display start line register
Common counter
FR
Display
timing
generator
circuit
Column address counter
Column address register
Command
decoder
Status
Bus
holder
CL
Low-address
register
Column address decoder
2–2
EPSON
RES
(E,R/W)
M/S
RD,WR
A0,CS
D0~D7
MPU interface
Rev. 1.1
S1D15200 Series
4. PIN LAYOUT
1
5
10
15
20
100 COM 4
COM 3
COM 2
COM 1
COM 0
95 V1
V4
M/S
V2
V3
90 V5
FR
RES
V DD
DB 7
85 DB 6
DB 5
DB 4
DB 3
DB 2
35
40
45
80
75
70
SEG 21
SEG 20
SEG 19
SEG 18
SEG 17
SEG 16
SEG 15
SEG 14
SEG 13
SEG 12
SEG 11
SEG 10
SEG 9
SEG 8
SEG 7
SEG 6
SEG 5
SEG 4
SEG 3
SEG 2
SEG 1
SEG 0
A0
CS(OSC1)
CL(OSC2)
E (RD)
R/W (WR)
V SS
DB0
DB1
65
60
50
55
SEG 41
SEG 40
SEG 39
SEG 38
SEG 37
SEG 36
SEG 35
SEG 34
SEG 33
SEG 32
SEG 31
SEG 30
SEG 29
SEG 28
SEG 27
SEG 26
SEG 25
SEG 24
SEG 23
SEG 22
25
30
SEG 42
SEG 43
SEG 44
SEG 45
SEG 46
SEG 47
SEG 48
SEG 49
SEG 50
SEG 51
SEG 52
SEG 53
SEG 54
SEG 55
SEG 56
SEG 57
SEG 58
SEG 59
SEG 60
COM 15
COM 14
COM 13
COM 12
COM 11
COM 10
COM 9
COM 8
COM 7
COM 6
COM 5
QFP5
R/W (WR)
E (RD)
CL (OSC1)
CS (OSC2)
A0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
QFP15
75
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
RES
FR
V5
V3
V2
M/S
V4
V1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
65
70
60
55
50
80
45
85
40
90
35
Index
95
30
5
10
15
20
25
CON7
CON8
CON9
CON10
CON11
CON12
CON13
CON14
CON15
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
1
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG29
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
Note: This is an example of S1D15200F pin assignment. The modified pin names are given below.
Product
Name
S1D15200F00A*
S1D15201F00A*
S1D15202F00A*
S1D15200F10A*
S1D15201F10A*
S1D15202F10A*
74
OSC1
CS
OSC1
CS
CS
CS
75
OSC2
CL
OSC2
CL
CL
CL
Pin/Pad Number
96 to 100, 1 to 11
93
COM0 to COM15*
M/S
SEG76 to SEG61
SEG79
COM0 to 7, SEG68 to 61
M/S
COM0 to COM15*
M/S
SEG76 to SEG61
SEG79
COM0 to 7, SEG68 to 61
M/S
94
V4
SEG78
V4
V4
SEG78
V4
95
V1
SEG77
V1
V1
SEG77
V1
S1D15200: Common outputs COM0 to COM15 of the master LSI correspond to COM31 to COM16 of the
slave LSI.
S1D15202: Common outputs COM0 to COM15 of the master LSI correspond to COM15 to COM8 of the
slave LSI.
Rev. 1.1
EPSON
2–3
S1D15200 Series
5. PAD
Pad Layout
Chip specifications of AL pad package
Chip size: 4.80×7.04×0.400 mm
Pad pitch: 100×100 µm
100
Chip specifications of gold bump package
Chip size:
4.80×7.04×0.525 mm
Bump pitch: 199 µm (Min.)
Bump height: 22.5 µm (Typ.)
Bump size: 132×111 µm (±20 µm) for mushroom
model
116×92 µm (±4 µm) for vertical model
95
90
85
80
1
5
75
Y
15
70
7.04 mm
10
X
(0, 0)
65
20
25
30
D1520D AA *
60
55
35
40
45
50
4.80 mm
Note: An example of S1D15200D10A* die numbers is given. These numbers are the same as the bump
package.
2–4
EPSON
Rev. 1.1
S1D15200 Series
Pad Center Coordinates
An example of S1D15200D10** pin names is given.
The asterisk (*) can be A for AL pad package or B for
gold bump package.
S1D15200D10B* Pad Center Coordinates
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pin
X
Name
COM5
159
COM6
159
COM7
159
COM8
159
COM9
159
COM10 159
COM11 159
COM12 159
COM13 159
COM14 159
COM15 159
SEG60 159
SEG59 159
SEG58 159
SEG57 159
SEG56 159
SEG55 159
SEG54 159
SEG53 159
SEG52 159
SEG51 159
SEG50 159
SEG49 159
SEG48 159
SEG47 159
SEG46 159
SEG45 159
SEG44 159
SEG43 159
SEG42 159
SEG41 504
SEG40 704
SEG39 903
SEG38 1103
Y
6507
6308
6108
5909
5709
5510
5310
5111
4911
4712
4512
4169
3969
3770
3570
3371
3075
2876
2676
2477
2277
2078
1878
1679
1479
1280
1080
881
681
482
159
159
159
159
Pad
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Pin
Name
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
X
Y
1302
1502
1701
1901
2100
2300
2499
2699
2898
3098
3297
3497
3696
3896
4095
4295
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
482
681
881
1080
1280
1479
1679
1878
2078
2277
2477
2676
2876
3075
3275
3474
3674
3948
Pad
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
Name
SEG3
SEG2
SEG1
SEG0
A0
CS
CL
E (RD)
R/W (WR)
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
RES
FR
V5
V3
V2
M/S
V4
V1
COM0
COM1
COM2
COM3
COM4
X
Y
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4295
4095
3896
3696
3497
3297
3098
2898
2699
2499
2300
2100
1901
1701
1502
1302
1103
903
704
504
4148
4347
4547
4789
5048
5247
5447
5646
5846
6107
6307
6506
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
The other S1D15200 series packages have the different pin names as shown.
Package/Pad No.
S1D15200D00**
S1D15202D00**
S1D15202D10**
S1D15201D00**
S1D15201D10**
Rev. 1.1
74
OSC1
OSC1
OSC1
CS
CS
75
OSC2
OSC2
OSC2
CL
CL
96 to 100, 1 to 11
COM0 to COM15 *
COM0 to 7, SEG68 to 61
COM0 to 7, SEG68 to 61
SEG76 to SEG61
SEG76 to SEG61
EPSON
93
M/S
M/S
M/S
SEG79
SEG79
94
V4
V4
V4
SEG78
SEG78
95
V1
V1
V1
SEG77
SEG77
2–5
S1D15200 Series
6. PIN DESCRIPTION
(1) Power Supply Pins
Name
Description
VDD
Connected to the +5Vdc power. Common to the V CC MPU power pin.
VSS
0 Vdc pin connected to the system ground.
V1, V2, V3, V 4, V 5
Multi-level power supplies for LCD driving. The voltage determined for each liquid
crystal cell is divided by resistance or it is converted in impedance by the op amp,
and supplied. These voltages must satisfy the following:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
(2) System Bus Connection Pins
D7 to D0
Three-state I/O.
The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU
data buses.
A0
Input.
Usually connected to the low-order bit of the MPU address bus and used to identify
the data or a command.
A0=0: D0 to D7 are display control data.
A0=1: D0 to D7 are display data.
RES
CS
E (RD)
R/W (WR)
2–6
Input.
When the RES signal goes
the 68-series MPU is initialized, and when it
goes
, the 80-series MPU is initialized. The system is reset during edge
sense of the RES signal. The interface type to the 68-series or 80-series MPU is
selected by the level input as follows:
High level: 68-series MPU interface
Low level: 80-series MPU interface
Input. Active low. Effective for an external clock operation model only.
An address bus signal is usually decoded by use of chip select signal, and it is
entered. If the system has a built-in oscillator, this is used as an input pin to the
oscillator amp and an Rf oscillator resistor is connected to it. In such case, the RD,
WR and E signals must be ORed with the CS signals and entered.
• If the 68-series MPU is connected:
Input. Active HIGH.
Used as an enable clock input of the 68-series MPU.
• If the 80-series MPU is connected:
Input. Active LOW.
The RD signal of the 80-series MPU is entered in this pin. When this signal is
kept low, the SED1520 data bus is in the output status.
• If the 68-series MPU is connected:
Input.
Used as an input pin of read control signals (if R/W is HIGH) or write control
signals (if LOW).
• If the 80-series MPU is connected:
Input. Active LOW.
The WR signal of the 80-series MPU is entered in this pin. A signal on the data
bus is fetched at the rising edge of WR signal.
EPSON
Rev. 1.1
S1D15200 Series
(3) LCD Drive Circuit Signals
Name
Description
CL
Input. Effective for an external clock operation model only.
This is a display data latch signal to count up the line counter and common counter
at each signal falling and rising edges. If the system has a built-in oscillator, this is
used as an output pin of the oscillator amp and an Rf oscillator resistor is connected to it.
FR
Input/output.
This is an I/P pin of LCD AC signals, and connected to the M terminal of common
driver.
I/O selection
• Common oscillator built-in model: Output if M/S is 1;
Input if M/S is 0.
• Dedicate segment model:
Input
SEGn
Output.
The output pin for LCD column (segment) driving. A single level of VDD , V2, V3 and
V5 is selected by the combination of display RAM contents and RF signal.
1
0
FR signal
1
0
1
0
V DD
V2
V5
V3
Data
Output level
COMn
Output.
The output pin for LCD common (low) driving. A single level of VDD, V1, V4 and V5
is selected by the combination of common counter output and RF signal. The
slave LSI has the reverse common output scan sequence than the master LSI.
1
0
FR signal
1
0
1
0
V5
V1
V DD
V4
Counter output
Output level
M/S
Input.
The master or slave LSI operation select pin for the S1D15200 or S1D15202.
Connected to VDD (to select the master LSI operation mode) or VSS (to select the
slave LSI operation mode).
When this M/S pin is set, the functions of FR, COM0 to COM15, OSC1 (CS), and
OSC2 (CL) pins are changed.
M/S
FR
COM output
OSC1
OSC2
S1D15200F00A* VDD Output
COM0 to COM15
Input
Output
VSS
Input
COM31 to COM16
NC
Input
S1D15202F00A* VDD Output
COM0 to COM7
Input
Output
Input
COM15 to COM8
NC
Input
VSS
* The slave driver has the reverse common output scan sequence than the master
driver.
Rev. 1.1
EPSON
2–7
S1D15200 Series
7. FUNCTION DESCRIPTION
System Bus
MPU interface
signal level after reset (see Table 1).
When the CS signal is high, the S1D15200 series is
disconnected from the MPU bus and set to stand by.
However, the reset signal is entered regardless of the
internal setup status.
1. Selecting an interface type
The S1D15200 series transfers data via 8-bit bidirectional data buses (D0 to D7). As its Reset pin has the
MPU interface select function, the 80-series MPU or
the 68-series MPU can directly be connected to the
MPU bus by the selection of HIGH or LOW RES
Table 1
RES signal input level
Active
Active
MPU type
68-series
80-series
A0
↑
↑
(1) Data transfer
The S1D15200 and S1D15201 drivers use the A0, E (or
RD) and R/W (or WR) signals to transfer data between
the system MPU and internal registers. The combinations used Access to Display Date RAM and Internal
Registers are given in the table blow.
E
↑
RD
R/W
↑
WR
CS
↑
↑
D0 to D7
↑
↑
This means that a dummy read cycle has to be executed
at the start of every series of reads. See Figure 1.
No dummy cycle is required at the start of a series of
writes as data is transferred automatically from the input
latch to its destination.
Table 2
Common
A0
1
1
0
0
68 MPU
R/W
1
0
1
0
80 MPU
RD
0
1
0
1
WR
1
0
1
0
Function
Read display data
Write display data
Read status
Write to internal register (command)
In order to match the timing requirements of the MPU
with those of the display data RAM and control registers
all data is latched into and out of the driver. This
introduces a one cycle delay between a read request for
data and the data arriving. For example when the MPU
executes a read cycle to access display RAM the current
contents of the latch are placed on the system data bus
while the desired contents of the display RAM are
moved into the latch.
2–8
EPSON
Rev. 1.1
S1D15200 Series
WRITE
WR
MPU
DATA
Internal
timing
N
N+1
N+2
N+3
Bus
N+1
N
hold
N+2
N+3
WR
READ
WR
RD
MPU
DATA
N
N
Address set
at N
n
Dummy read
Data read
at N
n+1
Data read
at N + 1
WR
RD
Internal
timing
Column
N
address
Bus
hold
N+1
N
n
N+2
n+1
n+2
Figure 1 Bus Buffer Delay
(2) Busy flag
When the Busy flag is logical 1, the S1D15200 series is
executing its internal operations. Any command other
than Status Read is rejected during this time. The Busy
flag is output at pin D7 by the Status Read command. If
an appropriate cycle time (tcyc) is given, this flag needs
not be checked at the beginning of each command and,
therefore, the MPU processing capacity can greatly be
enhanced.
(4) Column Address Counter
The column address counter is a 7-bit presettable counter
that supplies the column address for MPU access to the
display data RAM. See Figure 2. The counter is
incremented by one every time the driver receives a Read
or Write Display Data command. Addresses above 50H
are invalid, and the counter will not increment past this
value. The contents of the column address counter are set
with the Set Column Address command.
(3) Display Start Line and Line Count
Registers
The contents of this register form a pointer to a line of
data in display data RAM corresponding to the first line
of the display (COM0), and are set by the Display Start
Line command. See section 3.
The contents of the display start line register are copied
into the line count register at the start of every frame, that
is on each edge of FR. The line count register is
incremented by the CL clock once for every display line,
thus generating a pointer to the current line of data, in
display data RAM, being transferred to the segment
driver circuits.
(5) Page Register
The page resiter is a 2-bit register that supplies the page
address for MPU access to the display data RAM. See
Figure 2. The contents of the page register are set by the
Set Page Register command.
Rev. 1.1
(6) Display Data RAM
The display data RAM stores the LCD display data, on a
1-bit per pixel basis. The relation-ship between display
data, display address and the display is shown in Figure
2.
EPSON
2–9
S1D15200 Series
(7) Common Timing Generator Circuit
Generates common timing signals and FR frame signals
from the CL basic clock. The 1/16 or 1/32 duty (for
S1D15200) or 1/8 or 1/16 duty (for S1D15202) can be
selected by the Duty Select command. If the 1/32 duty is
selected for the S1D15200 and 1/16 duty is selected for
the S1D15202, the 1/32 and 1/16 duties are provided by
two chips consisting of the master and slave chips in the
common multi-chip mode.
S1D15200
FR signal
(Master output)
Master Common
0
1
2
14 15
Slave Common
0
16 17
1
15
30 31
16 17
31
8
15
S1D15220
FR signal
(Master output)
Master Common
Slave Common
0
1
2
6
7
0
8
(8) Display Data Latch Circuit
This latch stores one line of display data for use by the
LCD driver interface circuitry. The output of this latch
is controlled by the Display ON/OFF and Static Drive
ON/OFF commands.
(9) LCD Driver Circuit
The LCD driver circuitry generates the 80 4-level signals
used to drive the LCD panel, using output from the
display data latch and the common timing generator
circuitry.
2–10
9
14 15
1
7
9
(10) Display Timing Generator
This circuit generates the internal display timing signal
using the basic clock, CL, and the frame signals, FR.
FR is used to generate the dual frame AC-drive waveform (type B drive) and to lock the line counter and
common timing generator to the system frame rate.
CL is used to lock the line counter to the system line scan
rate. If a system uses both S1D15200 or S1D15202 and
S1D15201 they must have the same CL frequency rating.
EPSON
Rev. 1.1
S1D15200 Series
(11) Oscillator Circuit (S1D15200*0A Only)
A low power-consumption CR oscillator for adjusting
the oscillation frequency using Rf oscillation resistor
only. This circuit generates a display timing signal.
Some of S1D15200 and S1D15202 series models have a
built-in oscillator and others use an external clock. This
difference must be checked before use.
Connect the Rf oscillation resistor as follows. To suppress the built-in oscillator circuit and drive the MPU
using an external clock, enter the clock having the same
phase as the OSC2 of mater chip into OSC2 of the slave
chip.
• MPU having a built-in oscillator
V DD
Master chip
Slave chip
M/S
M/S
(CS)
OSC1
(CL)
OSC2
VSS
(CS)
OSC1
(CL)
OSC2
Rf
*2
Open
*1
*1 If the parasitic capacitance of this section increases, the oscillation frequency may shift to the lower
frequency. Therefore, the Rf oscillation frequency must be reduced below the specified level.
*2 A CMOS buffer is required if the oscillation circuit is connected to two or more slave MPU chips.
• MPU driven with an external clock
Y driver
S1D15201F10A*
CL2
CL
(12) Reset Circuit
Detects a rising or falling edge of an RES input and
initializes the MPU during power-on.
• Initialization status
1. Display is off.
2. Display start line register is set to line 1.
3. Static drive is turned off.
4. Column address counter is set to address 0.
5. Page address register is set to page 3.
6. 1/32 duty (S1D15200) or 1/16 duty (S1D15202)
is selected.
7. Forward ADC is selected (ADC command D0 is
1 and ADC status flag is 1).
8. Read-modify-write is turned off.
Rev. 1.1
EPSON
The input signal level at RES pin is sensed, and an
MPU interface mode is selected as shown on Table 1.
For the 80-series MPU, the RES input is passed
through the inverter and the active high reset signal
must be entered. For the 68-series MPU, the active
low reset signal must be entered.
As shown for the MPU interface (reference example),
the RES pin must be connected to the Reset pin and
reset at the same time as the MPU initialization.
If the MPU is not initialized by the use of RES pin
during power-on, an unrecoverable MPU failure may
occur.
When the Reset command is issued, initialization
2–11
S1D15200 Series
Page address
D1,D2 = 0,0
Page 0
Page 1
Page 2
Page 3
Line
address
00 H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Start line
(Example)
Start
1/16
Response
Common
output
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM 10
COM 11
COM 12
COM 13
COM 14
COM 15
COM 16
COM 17
COM 18
COM 19
COM 20
COM 21
COM 22
COM 23
COM 24
COM 25
COM 26
COM 27
COM 28
COM 29
COM 30
COM 31
Rev. 1.1
EPSON
2–12
4D
4E
4F
02
01
00
77
78
79
0,1
SEG 0
1
2
3
4
5
6
7
1,0
1,1
SEG pin
ADC
D0 = "1" D0 = "0"
4F H
00 H
01
4E
02
4D
4C
03
4B
04
05
4A
49
06
07
48
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Column address
Display area
Figure 2 Display Data RAM Addressing
S1D15200 Series
1/5 bias, 1/16 duty
1/6 bias, 1/32 duty
0 1 2 3
0 1 2 3
15 0 1 2 3
31 0 1 2 3
FR
COM0
COM0
COM1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM2
COM8
COM9
COM10
COM11
COM12
SEG0
COM13
COM14
SEG4
SEG3
SEG2
SEG1
SEG0
COM15
SEG1
COM0—SEG0
COM0—SEG1
15
31
V DD
V SS
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
V DD
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
V DD
-V1
-V2
-V3
-V4
-V5
Figure 4 LCD drive waveforms example
Rev. 1.1
EPSON
2–13
S1D15200 Series
8. COMMANDS
Table 3
Command
Code
A0
RD WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0/1
Function
Turns display on or off.
(1) Display On/OFF
0
1
0
1
0
1
(2) Display start line
0
1
0
1
1
0Display start address (0 to 31)
Specifies RAM line corresponding to
top line of display.
(3) Set page address
0
1
0
1
0
1
Sets display RAM page in page
address register.
0
1
0
0
(4) Set column
(segment) address
(5) Read status
0
0
1
Busy
1
1
0
Page (0 to 3)
Sets display RAM column address in
Column address (0 to 79)
ADC ON/OFF Reset
0
0
1: ON, 0: OFF
column address register.
Reads the following status:
0
BUSY
1: Busy
0: Ready
ADC
1: CW output
ON/OFF
0: CCW output
1: Display off
RESET
0: Display on
1: Being reset
0
0: Normal
(6) Write display data
1
1
0
Write data
Writes data from data bus into display
RAM.
(7) Read display data
1
0
1
Read data
Reads data from display RAM onto
data bus.
(8) Select ADC
0
1
0
1
0
1
0
0
0
0
0/1
0: CW output, 1: CCW output
(9) Static drive
ON/OFF
0
1
0
1
0
1
0
0
1
0
0/1
Selects static driving operation.
1: Static drive, 0: Normal driving
(10) Select duty
0
1
0
1
0
1
0
1
0
0
0/1
Selets LCD duty cycle
1: 1/32, 0: 1/16
(11) Read-Modify-Write
(12) End
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
0
(13) Reset
0
1
0
1
1
1
0
0
0
1
0
2–14
EPSON
Read-modify-write ON
Read-modify-write OFF
Software reset
Rev. 1.1
S1D15200 Series
Command Description
Table 3 is the command table. The S1D15200 series identifies a data bus using a combination of A0 and R/W (RD or WR)
signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed
is very high. The busy check is usually not required.
(1) Display ON/OFF
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
D
AEH, AFH
This command turns the display on and off.
• D=1: Display ON
• D=0: Display OFF
(2) Display Start Line
This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COM0. The
display area begins at the specified line address and continues in the line address increment direction. This area having
the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command,
the vertical smooth scrolling and paging can be used.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
A4
A3
A2
A1
A0
C0H to DFH
This command loads the display start line register.
A4 A3 A2 A1 A0 Line Address
0
0
0
0
1
1
0
0
:
:
1
0
0
0
1
1
1
0
1
:
:
31
See Figure 2.
(3) Set Page Address
This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed
by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified.
The display status is not changed even when the page address is changed.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
1
1
0
A1
A0
B8H to BBH
This command loads the page address register.
A1 A0 Page
0
0
1
1
0
1
0
1
0
1
2
3
See Figure 2.
Rev. 1.1
EPSON
2–15
S1D15200 Series
(4) Set Column Address
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU
continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU
can access to data continuously. The column address stops to be incremented at address 80, and the page address is not
changed continuously.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
A6
A5
A4
A3
A2
A1
A0
00H to 4FH
This command loads the column address register.
A6 A5 A4 A3 A2 A1 A0 Column Address
0
0
0
0
0
0
1
0
0
0
0
:
:
1
0
0
0
0
0
1
1
1
1
0
1
:
:
79
(5) Read Status
A0
RD
R/W
WR
0
0
1
D7
D6
D5
D4
BUSY ADC ON/OFF RESET
D3
D2
D1
D0
0
0
0
0
Reading the command I/O register (A0=0) yields system status information.
• The busy bit indicates whether the driver will accept a command or not.
Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.
Busy=0: The driver will accept a new command.
• The ADC bit indicates the way column addresses are assigned to segment drivers.
ADC=1: Normal. Column address n → segment driver n.
ADC=0: Inverted. Column address 79-u → segment driver u.
• The ON/OFF bit indicates the current status of the display.
It is the inverse of the polarity of the display ON/OFF command.
ON/OFF=1: Display OFF
ON/OFF=0: Display ON
• The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode.
RESET=1: Currently executing reset command.
RESET=0: Normal operation
(6) Write Display Data
A0
RD
R/W
WR
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data
Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page
address registers and then increments the column address register by one.
2–16
EPSON
Rev. 1.1
S1D15200 Series
(7) Read Display Data
A0
RD
R/W
WR
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data
Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data
RAM location specified by the contents of the column address and page address registers and then increments the column
address register.
After loading a new address into the column address register one dummy read is required before valid data is obtained.
(8) Select ADC
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
0
0
D
A0H, A1H
This command selects the relationship between display data RAM column addresses and segment drivers.
D=1: SEG0 ← column address 4FH, … (inverted)
D=0: SEG0 ← column address 00H, … (normal)
This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit
board design. See Figure 2 for a table of segments and column addresses for the two values of D.
(9) Static Drive ON/OFF
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
0
D
A4H, A5H
Forces display on and all common outputs to be selected.
D=1: Static drive on
D=0: Static drive off
(10) Select Duty
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
0
0
D
A8H, A9H
This command sets the duty cycle of the LCD drive and is only valid for the S1D15200F and S1D15202F. It is invalid
for the S1D15201F which performs passive operation. The duty cycle of the S1D15201F is determined by the externally
generated FR signal.
S1D15200
S1D15202
D=1: 1/32 duty cycle
1/16 duty cycle
D=0: 1/16 duty cycle
1/8 duty cycle
When using the S1D15200F00A*, S1D15202F00A* (having a built-in oscillator) and the S1D15201F00A* continuously, set the duty as follows:
S1D15200F00A *
S1D15202F00A *
Rev. 1.1
1/32
1/16
1/16
1/8
EPSON
S1D15201F00A*
1/32
1/16
1/32
1/16
2–17
S1D15200 Series
(11) Read-Modify-Write
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
E0H
This command defeats column address register auto-increment after data reads. The current conetents of the column
address register are saved. This mode remains active until an End command is received.
• Operation sequence during cursor display
When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write
command. This function can reduce the load of MPU when data change is repeated at a specific display area (such as cursor
blinking).
* Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column
Address Set command cannot be used.
Set Page Address
Set Column Address
Read-Modify-Write
Dummy Read
Read Data
Write Data
No
Completed?
Yes
End
(12) End
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
EEH
This command cancels read-modify-write mode and restores the contents of the column address register to their value prior
to the receipt of the Read-Modify-Write command.
Return
Column address
N
N+1
N+2
N+3
Read-Modify-Write mode is selected.
2–18
EPSON
N+m
N
End
Rev. 1.1
S1D15200 Series
(13) Reset
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
0
E2H
This command clears
• the display start line register.
• and set page address register to 3 page.
It does not affect the contents of the display data RAM.
When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead
of this Reset signal.
(14) Power Save (Combination command)
The Power Save mode is selected if the static drive is turned ON when the display is OFF. The current consumption can
be reduced to almost the static current level. In the Power Save mode:
(a) The LCD drive is stopped, and the segment and common driver outputs are set to the VDD level.
(b) The external oscillation clock input is inhibited, and the OSC2 is set to the floating mode.
(c) The display and operation modes are kept.
The Power Save mode is released when the display is turned ON or when the static drive is turned OFF. If the LCD drive
voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the
Power Save signal.
VDD
VDD
V1
V2
V3
S1D15200
V4
V5
Power Save signal
VSSH
If the LCD drive power is generated by resistance division, the resistance and capacitance are determined by the LCD panel
size. After the panel size has been determined, reduce the resistance to the level where the display quality is not affected
and reduce the power consumption using the divider resistor.
Rev. 1.1
EPSON
2–19
S1D15200 Series
9. ABSOLUTE MAXIMUS RATINGS
Parameter
Symbol
Rating
Unit
Supply voltage (1)
VSS
–8.0 to +0.3
V
Supply voltage (2)
V5
–16.5 to +0.3
V
Supply voltage (3)
V1, V4, V 2, V3
V5 to +0.3
V
Input voltage
VIN
VSS–0.3 to +0.3
V
Output voltage
VO
VSS–0.3 to +0.3
V
Power dissipation
PD
250
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Soldering temperature time at lead
Tsol
260, 10
°C, sec
Notes: 1. All voltages are specified relative to VDD = 0 V.
2. The following relation must be always hold
VDD ≥ V 1 ≥ V2 ≥ V3 ≥ V4 ≥ V 5
3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional
operation under these conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to
avoid thermally stressing the package during board assembly.
10. ELECTRICAL CHARCTERISTICS
DC Characteristics
Ta = –20 to 75 °C, VDD = 0 V unless stated otherwise
Parameter
Symbol
Operating Recommended
voltage (1)
See note 1. Allowable
VSS
Recommended
Operating Allowable
voltage (2) Allowable
Allowable
High-level input voltage
Low-level input voltage
High-level output voltage
Condition
Min.
Rating
Typ.
Max.
–5.5
–5.0
–4.5
V
–7.0
V5
V 1, V2
V 3, V4
V IHT
VIHC
V IHT
VIHC
V ILT
VILC
V ILT
VILC
VOHT
VOHC1
VOHC2
VOHT
VOHC1
VOHC2
Unit
–13.0
–13.0
0.6×V 5
V5
VSS+2.0
0.2×VSS
V SS = –3 V
0.2×VSS
V SS = –3 V
0.2×VSS
VSS
VSS
V SS = –3 V
VSS
V SS = –3 V
VSS
IOH = –3.0 mA
VSS+2.4
IOH = –2.0 mA
VSS+2.4
IOH = –120 µA
0.2×VSS
V SS = –3 V
IOH = –2 mA 0.2×VSS
V SS = –3 V
IOH = –2 mA 0.2×VSS
V SS = –3 V
IOH = –50 µA 0.2×VSS
—
–2.4
—
—
—
—
—
—
—
—
–3.5
—
V DD
0.4×V5
V DD
V DD
V DD
V DD
V SS+0.8
0.8×VSS
0.85×V SS
0.8×VSS
—
—
—
—
—
—
V
V
V
Applicable Pin
V SS
V5
See note 10.
V 1, V2
V 3, V4
See note 2 & 3.
See note 2 & 3.
V
See note 2 & 3.
See note 2 & 3.
V
OSC2
See note 4 & 5.
V
See note 4 & 5.
OSC2
(continued)
2–20
EPSON
Rev. 1.1
S1D15200 Series
Parameter
Symbol
Condition
IOL = 3.0 mA
IOL = 2.0 mA
IOL = 120 µA
V SS = –3 V
V SS = –3 V
V SS = –3 V
Input leakage current
Output leakage current
VOLT
VOLC1
VOLC2
VOLT
VOLC1
VOLC2
ILI
ILO
LCD driver ON resistance
R ON
Ta = 25 °C
Low-level output voltage
IOL = 2 mA
IOL = 2 mA
IOL = 50 µA
–1.0
–3.0
V5 = –5.0 V
V5 = –3.5 V
Static current dissipation
IDDQ
CS = CL = VDD
fCL = 2 kHz
During display
Rf = 1 MΩ
V 5 = –5.0 V
fCL = 18 kHz
IDD (1)
Dynamic current dissipation
Input pin capacitance
Oscillation frequency
Reset time
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Rev. 1.1
Min.
—
—
—
—
5.0
10.0
50.0
—
—
—
—
0.05
2.0
9.5
5.0
1.0
5.0
15.0
10.0
1.5
4.5
6.0
12.0
300
500
150
300
—
5.0
8.0
15
18
21
—
11
16
Unit
Applicable Pin
V
OSC2
See note 4 & 5.
V
See note 4 & 5.
OSC2
µA
µA
See note 6.
See note 7.
kΩ
SEG0 to 79,
COM0 to 15,
See note 11
7.5
—
During display fCL = 2 kHz
V 5 = –5 V
V SS = –3 V
Rf = 1 MΩ
During access tcyc = 200 kHz
IDD (2) V SS = –3V,
During access tcyc = 200 kHz
Ta = 25 °C, f = 1 MHz
CIN
R f = 1.0 MΩ ±2%,
V SS = –5.0 V
fOSC
R f = 1.0 MΩ ±2%,
V SS = –3.0 V
Rating
Typ.
Max.
—
V SS+0.4
—
V SS+0.4
—
0.8×VSS
0.8×VSS
0.8×VSS
0.8×VSS
—
1.0
—
3.0
µA
µA
V DD
V DD
See note 12,
13 & 14.
µA
V DD
See note 12 & 13.
µA
See note 8.
pF
All input pins
kHz
See note 9.
21
RES
See note 15.
Operation over the specified voltage range is guaranteed, except where the supply voltage changes
suddenly during CPU access.
A0, D0 to D7, E (or RD), R/W (or WR) and CS
CL, FR, M/S and RES
D0 to D7
FR
A0, E (or RD), R/W (or WR), CS, CL, M/S and RES
When D0 to D7 and FR are high impedance.
During continual write acess at a frequency of tcyc. Current consumption during access is effectively
proportional to the access frequency.
See figure below for details
See figure below for details
For a voltage differential of 0.1 V between input (V1, …, V4) and output (COM, SEG) pins. All voltages
within specified operating voltage range.
S1D15200* 10** and S1D15201*10** and S1D15202*10** only. Does not include transient
currents due to stray and panel capacitances.
S1D15200*00** and S1D15202*00** only. Does not include transient currents due to stray and
panel capacitances.
S1D15201*00** only. Does not include transient currents due to stray and panel capacitances.
tR (Reset time) represents the time from the RES signal edge to the completion of reset of the internal
circuit. Therefore, the S1D15200 series enters the normal operation status after this tR.
tR
1.0
EPSON
—
µS
2–21
S1D15200 Series
Relationship between fOSC, fFR and Rf , and operating bounds on VSS and V5
*9
• Relationship between oscillation frequency, frames and Rf
(S1D15200F00A*), (S1D15202F00A*)
OSC1
Rf
OSC2
Ta=25°C V SS =-5V
Ta=25°C VSS =-5V
[Hz]
200
30
VSS =-5V
SED1522
20
100
Frame
fosc
[kHz]
40
Same for 1/16 and 1/32 duties
VSS =-3V
SED1520
10
0
0.5
1.0
1.5
2.0
0
2.5
0.5
1.0
[M Ω]
Rf
1.5
Rf
Figure 5 (a)
2.0
2.5
[M Ω]
Figure 5 (b)
• Relationship between external clocks (fCL) and frames
(S1D15200F10A*) , (S1D15202F10A*)
duty1/32
duty1/16
200
[Hz]
duty1/8
Frame
100
0
1
2
f CL
[kHz]
3
Figure 5 (c)
*10 • Operating voltage range of VSS and V5 systems
(V)
–15
–10
V5
Operating voltage
range
–5
0
–2
–4
VSS
–6
(V)
–8
Figure 6
2–22
EPSON
Rev. 1.1
S1D15200 Series
AC Characteristics
• MPU Bus Read/Write I (80-family MPU)
A0,CS
t AW8
t CC
t AH8
WR,RD
tr
t CYC8
tf
t DH8
t DS8
D0 to D7
(WRITE)
t OH8
t ACC8
D0 to D7
(READ)
Ta = –20 to 75 ˚C, VSS = –5.0 V ±10% unless stated otherwise
Parameter
Address hold time
Address setup time
System cycle time
Control pulsewidth
Data setup time
Data hold time
RD access time
Output disable time
Rise and fall time
Symbol
tAH8
tAW8
tCYC8
tCC
tDS8
tDH8
tACC8
tCH8
tr, t f
Condition
CL = 100 pF
—
Rating
Min.
Max.
10
—
20
—
1000
—
200
—
80
—
10
—
—
90
10
60
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS
WR, RD
D0 to D7
—
(VSS = –2.7 to –4.5 V, Ta = –20 to +75°C)
Parameter
Address hold time
Address setup time
System cycle time
Control pulse width
Data setup time
Data hold time
RD access time
Output disable time
Rise and fall time
Rev. 1.1
Symbol
tAH8
tAW8
tCYC8
tCC
tDS8
tDH8
tACC8
tCH8
tr, t f
Condition
—
—
—
CL = 100 pF
—
EPSON
Rating
Min.
Max.
20
—
40
—
2000
—
400
—
160
—
20
—
—
180
20
120
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS
WR, RD
D0 to D7
—
2–23
S1D15200 Series
• MPU Bus Read/Write II (68-family MPU)
t CYC6
E
t EW
tr
tf
t AW6
t DS6
R/W
t AH6
A0,CS
t DH6
D0 to D7
(WRITE)
t ACC6
t OH6
D0 to D7
(READ)
Ta = –20 to 75 ˚C, VSS = –5 V ±10 unless stated otherwise
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Enable
Read
pulsewidth
Write
Rise and fall time
Symbol
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
Condition
CL = 100 pF
tEW
tr, tf
—
Rating
Min.
Max.
1000
—
20
—
10
—
80
—
10
—
10
60
—
90
100
—
80
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS, R/W
D0 to D7
E
—
(VSS = –2.7 to – 4.5 V, Ta = –20 to +75°C)
Parameter
System cycle time*1
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Enable
Read
pulse width
Write
Rise and fall time
Symbol
Condition
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
—
—
—
CL = 100 pF
tEW
—
tr, tf
—
Rating
Min.
Max.
2000
—
40
—
20
—
160
—
20
—
20
120
—
180
200
—
160
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS, R/W
D0 to D7
E
—
Notes: 1. tCYC6 is the cycle time of CS. E = H, not the cycle time of E.
2–24
EPSON
Rev. 1.1
S1D15200 Series
• Display Control Signal Timing
tf
tr
CL
t WLCL
t WHCL
t DFR
FR
Input
Ta = –20 to 75 °C, VSS = –5.0 V ±10% unless stated otherwise
Parameter
Symbol
Low-level pulsewidth
High-level pulsewidth
Rise time
Fall time
FR delay time
tWLCL
tWHCL
tr
tf
tDFR
Condition
Min.
35
35
—
—
–2.0
Rating
Typ.
—
—
30
30
0.2
Max.
—
—
150
150
2.0
Min.
70
70
—
—
–4.0
Rating
Typ.
—
—
60
60
0.4
Max.
—
—
300
300
4.0
Unit
Signal
µs
µs
ns
ns
µs
FR
Unit
Signal
CL
VSS = –2.7 to –4.5 V, Ta = –20 to +75°C
Parameter
Symbol
Condition
Low-level pulse width
High-level pulse width
Rise time
Fall time
FR delay time
tWLCL
tWHCL
tr
tf
tDFR
—
—
—
—
—
µs
µs
ns
ns
µs
CL
FR
Note: The listed input tDFR applies to the S1D15200 and S1D15201 and S1D15202 in slave mode.
Output
Ta = –20 to 75 °C, VSS = –5.0 V ±10% unless stated otherwise
Parameter
FR delay time
Symbol
Condition
tDFR
CL = 100 pF
Min.
—
Rating
Typ.
0.2
Max.
0.4
Min.
—
Rating
Typ.
0.4
Max.
0.8
Unit
Signal
µs
FR
Unit
Signal
µs
FR
VSS = –2.7 to –4.5 V, Ta = –20 to +75°C
Parameter
FR delay time
Symbol
Condition
tDFR
CL = 100 pF
Notes: 1. The listed output tDFR applies to the S1D15200 and S1D15202 in master mode.
Rev. 1.1
EPSON
2–25
S1D15200 Series
11. MPU INTERFACE CONFIGURATION
80 Family MPU
VCC
A1 to A7
Decoder
IOQR
MPU
CS
S1D15200F10A
*
D0 to D7
D0 to D7
GND
VDD
A0
A0
RD
RD
WR
WR
RES
VSS
RES
V5
RESET
68 Family MPU (Reference)
V DD
V CC
A0
A0
A1 to A15
CS
Decoder
VMA
D0 to D7
D0 to D7
MPU
E
E
R/W
R/W
RES
RES
GND
S1D15200F10A*
V SS
RESET
V5
* Refer to the figure above as to S1D15201.
* S1D15200*00 **(internal osillating) does not have CS terminal. Input OR output with CS signal to AD. RD(E)
WR(R/W)terminals as the figure belew.
A0
Decoder
CS
S1D15200F00A
D0 to D7
RD
WR
RES
When in use of 80 Family MPU
2–26
EPSON
Rev. 1.1
S1D15200 Series
12. LCD DRIVE INTERGFACE CONFIGURATION
S1D15200F00A*–S1D15200F00A*
S1D15202F00A*–S1D15202F00A*
To LCD COM
To LCD SEG
To LCD SEG
S1D15200F00A
S1D15200F00A
VDD
*
Master
To LCD COM
*
Slave
M/S
M/S
OSC1
OSC2
FR
OSC1
OSC2
FR
VSS
Rf
S1D15200F10A*–S1D15200F10A*
S1D15202F10A*–S1D15202F10A*
To LCD SEG
To LCD COM
To LCD SEG
*
VDD
To LCD COM
S1D15200F10A
S1D15200F10A
*
Master
Slave
M/S
M/S
CL
FR
CL
FR
VSS
External clock
S1D15200F00A*
)–S1D15201F00A* (See note 1)
S1D15202F00A*
To LCD SEG
To LCD SEG
To LCD COM
S1D15200F00A
VDD
S1D15201F00A
*
Master
*
Slave
M/S
OSC1
OSC2
FR
OSC1
OSC2
FR
Rf
*2
Rev. 1.1
EPSON
2–27
S1D15200 Series
S1D15200F10A*–S1D15201F10A*
To LCD SEG
To LCD COM
To LCD SEG
S1D15201F10A
S1D15200F10A
*
*
VDD
M/S
CL
FR
CL
FR
External clock
Notes: 1. The duty cycle of the slave must be the same as that for the master.
2. If a system has two or more slave drivers a CMOS buffer will be required.
2–28
EPSON
Rev. 1.1
S1D15200 Series
13. LCD PANEL WIRING EXAMPLE
(THE FULL-DOT LCD PANEL DISPLAYS A CHARACTER IN 6×8 DOTS.)
1/16 duty:
• 10 characters × 2 lines
1
LCD 16×61
16
1
61
SEG
S1D15200F
COM
1/16 duty:
• 23 characters × 2 lines
1
LCD 16×141
16
1
COM
61
62
141
SEG
SEG
S1D15200F
S1D15201F
1/32 duty:
• 33 characters × 4 lines
1
LCD 32×202
16
1
COM
61
62
141
17
142
202 32
SEG
SEG
SEG
S1D15200F
S1D15201F
*
S1D15200F
COM
* The S1D15201F can be omitted (the 32×122-dot display mode is selected).
Note: A combination of 10B* or 10A* type chip (that uses internal clocks) and 00B* or 00A* type chip (that uses
external clocks) is NOT allowed.
Rev. 1.1
EPSON
2–29
S1D15200 Series
Package Dimensions
• Plastic QFP5–100 pin
Dimensions: inches (mm)
1.008 ± 0.016
(25.6 ± 0.4)
0.787 ± 0.004 (20 ± 0.1)
80
51
81
Index
31
0.106 ± 0.004
(2.7 ± 0.1)
0.006 ± 0.002
(0.15 ± 0.05)
100
0.772 ± 0.016 (19.6 ± 0.4)
0.551 ± 0.004
(14 ± 0.1)
50
0.026 ± 0.004
(0.65 ± 0.1)
1
30
0.012 ± 0.004
(0.30 ± 0.1)
0~12°
0.110
(2.8)
0.059 ± 0
.012
(1.5 ± 0.3
)
• Plastic QFP15–100 pin
0.630 ± 0.016 (16.0 ± 0.4)
0.551 ± 0.004 (14.0 ± 0.1)
75
51
Index
0.005 ± 0.002
(0.127 ± 0.05)
0.055 ± 0.004
(1.4 ± 0.1)
100
0.630 ± 0.016 (16.0 ± 0.4)
50
0.551 ± 0.004 (14.0 ± 0.1)
76
26
1
25
0.020 ± 0.004
(0.5 ± 0.1)
0.007 ± 0.004
(0.18 ± 0.1)
0~12°
0.020 ± 0.004 (0.5 ± 0.2)
0.039(1.0)
2–30
EPSON
Rev. 1.1
Punching
hole for
good
product
(Mold, marking area)
Rev. 1.1
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 35µm
• Sn plating
• Product pitch: 81P (28.5mm)
• Solder resist positional tolerance: ±0.3
Output terminal pattern shape
S1D15200 Series
TCP Dimensions
EPSON
2–31
(Mold, marking area)
3. S1D15210 Series
Rev. 1.1
Contents
1. DESCRIPTION ................................................................................................................................................ 3-1
2. FEATURES ...................................................................................................................................................... 3-1
3. BLOCK DIAGRAM ........................................................................................................................................... 3-2
4. PAD LAYOUT .................................................................................................................................................. 3-3
5. PAD CENTER COORDINATES ...................................................................................................................... 3-4
6. PIN DISCRIPTION........................................................................................................................................... 3-5
7. FUNCTION DESCRIPTION ............................................................................................................................. 3-7
8. COMMANDS .................................................................................................................................................3-12
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 3-18
10. ELECTRICAL CHARCTERISTICS ................................................................................................................ 3-18
11. EXAMPLE OF CONNECTION .......................................................................................................................3-24
–i–
Rev. 1.1
S1D15210 Series
1. DESCRIPTION
2. FEATURES
The S1D15210 Series of dot matrix LCD drivers are
designed for the display of characters and graphics. The
drivers generate LCD drive signals derived from bit
mapped data stored in an internal RAM.
The S1D15210 Series drivers incorporate innovative
circuit design strategies to achieve very low power
dissipation at a wide range of operating voltages.
• Fast 8-bit MPU interface compatible with 80- and 68family microcomputers
• 32 × 80 bit RAM
• Many command set
• Total 80 (segment + common) drive sets
• Low power — 30 µW at 2 kHz external clock
• Wide range of supply voltages
VDD – VSS: 2.4V to 6.0 V
VC5 – VSS: 3.5V to 6.0 V
• Low-power CMOS
• Al-pad chip:S1D15210D**A*
• Au-bump chip:S1D15210D**B*
Rev. 1.1
EPSON
3–1
S1D15210 Series
SEG0 to SEG79
3. BLOCK DIAGRAM
VDD
VSS
LCD drive circuit
VC5
VC3
VC2
Display data RAM
(2560-bit)
I/O buffer
Line address decoder
Line counter
Display start line register
Display data latch circuit
FR
Display
timing
generator
circuit
Column address counter
Column address register
Command
decoder
Status
Bus
holder
CL
Low-address
register
Column address decoder
3–2
RES
RD,WR
EPSON
(E,R/W)
M/S
A0,CS
D0~D7
MPU interface
Rev. 1.1
S1D15210 Series
4. PAD LAYOUT
(2)Au-bump chip
Bump size : 92×92 µm
Bump height : 22.5 µm
(1) Al-pad chip
Chip size
: 4.80×7.04×0.400 mm
Pad pitch (Typ.)
: 100×100 µm
100
95
90
85
80
1
5
75
Y
15
70
7.04 mm
10
X
(0, 0)
65
20
25
30
D1520D AA *
60
55
35
40
45
50
4.80 mm
Rev. 1.1
EPSON
3–3
S1D15210 Series
5. PAD CENTER COORDINATES
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
3–4
Pin
Name
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
X
Y
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
504
704
903
1103
6507
6308
6108
5909
5709
5510
5310
5111
4911
4712
4512
4169
3969
3770
3570
3371
3075
2876
2676
2477
2277
2078
1878
1679
1479
1280
1080
881
681
482
159
159
159
159
Pad
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Pin
Name
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
X
Y
1302
1502
1701
1901
2100
2300
2499
2699
2898
3098
3297
3497
3696
3896
4095
4295
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
482
681
881
1080
1280
1479
1679
1878
2078
2277
2477
2676
2876
3075
3275
3474
3674
3948
EPSON
Pad
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
Name
SEG3
SEG2
SEG1
SEG0
A0
CS
CL
E (RD)
R/W (WR)
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
RES
FR
VC2
VC3
VC5
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
X
Y
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4295
4095
3896
3696
3497
3297
3098
2898
2699
2499
2300
2100
1901
1701
1502
1302
1103
903
704
504
4148
4347
4547
4789
5048
5247
5447
5646
5846
6107
6307
6506
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
Rev. 1.1
S1D15210 Series
6. PIN DESCRIPTION
(1) Power Supply Pins
Name
Description
VDD
Connected to the +5Vdc power. Common to the VCC MPU power pin.
VSS
0 Vdc pin connected to the system ground.
VC5, V C3, V C2
Multi-level power supplies for LCD driving. The voltage determined for each liquid
crystal cell is divided by resistance or it is converted in impedance by the op amp,
and supplied. These voltages must satisfy the following:
VC5 ≥ VC3 ≥ VC2 ≥ VSS
(2) System Bus Connection Pins
D7 to D0
*1
Three-state I/O.
The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU
data buses.
A0
Input.
Usually connected to the low-order bit of the MPU address bus and used to identify
the data or a command.
Low level (0): D0 to D7 are display control data.
High level (1): D0 to D7 are display data.
RES
CS
E (RD)
R/W (WR)
WR (R/W)
Rev. 1.1
Input.
When the RES signal goes
the 68-series MPU is initialized, and when it
goes
, the 80-series MPU is initialized. The system is reset during edge
sense of the RES signal. The interface type to the 68-series or 80-series MPU is
selected by the level input as follows:
High level: 68-series MPU interface
Low level: 80-series MPU interface
Input. Active low.
An address bus signal is usually decoded by use of chip select signal.
• If the 68-series MPU is connected:
Input. Active high.
Used as an enable clock input of the 68-series MPU.
• If the 80-series MPU is connected:
Input. Active low.
The RD signal of the 80-series MPU is entered in this pin. When this signal is
kept low, the S1D15210 data bus is in the output status.
• If the 68-series MPU is connected:
Input.
Used as an input pin of read control signals (if R/W is high) or write control
signals (if low).
• If the 80-series MPU is connected:
Input. Active low.
The WR signal of the 80-series MPU is entered in this pin. A signal on the data
bus is fetched at the rising edge of WR signal.
EPSON
3–5
S1D15210 Series
(3) LCD Drive Circuit Signals
Name
Description
CL
Input. Effective for an external clock operation model only.
This is a display data latch signal to count up the line counter and common counter
at each signal falling and rising edges.
FR
Input.
This is an input pin of LCD AC signals, and connected to the FR pin of common
driver.
SEGn
Output.
The output pin for LCD column (segment) driving. A single level of V C5, V C3, V C2,
VSS is selected by the combination of display RAM contents and FR signal.
1
0
FR signal
1
0
VC5
VC3
1
0
Data
VSS
VC2
Output level
3–6
EPSON
Rev. 1.1
S1D15210 Series
7. FUNCTION DESCRIPTION
System Bus
(1) MPU interface
Selecting an interface type
The S1D15210 series transfers data via 8-bit bidirectional data buses (D0 to D7). As its Reset pin has the
MPU interface select function, the 80-series MPU or
the 68-series MPU can directly be connected to the
MPU bus by the selection of high or low RES signal
level after reset (see Table 1).
When the CS signal is high, the S1D15210 series is
disconnected from the MPU bus and set to stand by.
(However, the reset signal is entered regardless of the
internal setup status.)
Table 1
RES signal input level
Active
Active
MPU type
80-series
68-series
A0
A0
A0
RD
RD
E
WR
WR
R/W
CS
CS
CS
D0 to D7
D0 to D7
D0 to D7
Data transfer
The S1D15210 drivers use the A0, E (or RD) and R/W (or
WR) signals to transfer data between the system MPU
and internal registers. The combinations used are given
in the table blow.
Table 2
Common
A0
1
1
0
0
80 MPU
RD
0
1
0
1
WR
1
0
1
0
68 MPU
R/W
1
0
1
0
Access to Display Date Ram and Internal
Registers
In order to match the timing requirements of the MPU
with those of the display data RAM and control registers
all data is latched into and out of the driver.
This introduces a one cycle delay between a read request
for data and the data arriving. For example when the
MPU executes a read cycle to access display RAM the
Rev. 1.1
Function
Read display data
Write display data
Read status
Write to internal register (command)
current contents of the latch are placed on the system data
bus while the desired contents of the display RAM are
moved into the latch.
This means that a dummy read cycle has to be executed
at the start of every series of reads. See Figure 1.
No dummy cycle is required at the start of a series of
writes as data is transferred automatically from the input
latch to its destination.
EPSON
3–7
S1D15210 Series
WRITE
WR
MPU
DATA
Intermal
timing
N
N+1
N+2
N+3
Bus
N
hold
N+1
N+2
N+3
WR
READ
WR
RD
MPU
DATA
N
N
Address set
at N
n
Dummy read
Data read
at N
n+1
Data read
at N + 1
WR
RD
Internal
timing
Column
N
address
Bus
hold
N+1
N
n
N+2
n+1
n+2
Figure 1 Bus Buffer Delay
(2) Busy flag
When the Busy flag is logical 1, the S1D15200 series is
executing its internal operations. Any command other
than Status Read is rejected during this time. The Busy
flag is output at pin D7 by the Status Read command. If
an appropriate cycle time (tcyc) is given, this flag needs
not be checked at the beginning of each command and,
therefore, the MPU processing capacity can greatly be
enhanced.
(4) Column Address Counter
The column address counter is a 7-bit presettable counter
that supplies the column address for MPU access to the
display data RAM. See Figure 2. The counter is
incremented by one every time the driver receives a Read
or Write Display Data command. Addresses above 50H
are invalid, and the counter will not increment past this
value. The contents of the column address counter are set
with the Set Column Address command.
(3) Display Start Line and Line Count
Registers
The contents of this register form a pointer to a line of
data in display data RAM corresponding to the first line
of the display (COM0), and are set by the Display Start
Line command. See section 3.
The contents of the display start line register are copied
into the line count register at the start of every frame, that
is on each edge of FR. The line count register is
incremented by the CL clock once for every display line,
thus generating a pointer to the current line of data, in
display data RAM, being transferred to the segment
driver circuits.
(5) Page Register
The page resiter is a 2-bit register that supplies the page
address for MPU access to the display data RAM. See
Figure 3. The contents of the page register are set by the
Set Page Register command.
3–8
(6) Display Data RAM
The display data RAM stores the LCD display data, on a
1-bit per pixel basis. The relation-ship between display
data, display address and the display is shown in Figure
3.
EPSON
Rev. 1.1
S1D15210 Series
Page address
D1,D2 = 0,0
Page 0
Page 1
Page 2
Page 3
Line
address
00 H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1/16
Start
Start line
(Example)
Display area
3–9
EPSON
Rev. 1.1
4D
4E
4F
02
01
00
77
78
79
0,1
SEG 0
1
2
3
4
5
6
7
1,0
1,1
SEG pin
ADC
D0 = "1" D0 = "0"
4F H
00 H
01
4E
02
4D
4C
03
4B
04
05
4A
49
06
07
48
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Column address
Figure 2 Display Data RAM Addressing
S1D15210 Series
(7) Display Timing Generation Circuit
The master clock CL and the frame signal FR generate
internal timing. The master clock CL causes the line
counter to operate, which synchronizes with the line
counter. Therefore, the master clock CL and the frame
signal FR input signals of the same phases as those of the
CR and FR signals of the common driver, respectively.
Common driver
CL
S1D15210
FR
CL
(8) Display Data Latch Circuit
The display data latch circuit is a latch that temporarily
memorizes the display data to be output to the liquid
crystal drive circuit from the display data RAM for each
common period. Display ON/OFF and Display All
Lamps ON/OFF commands control the data in this latch.
Therefore, data in the display data RAM are never to be
modified.
(9) Liquid Crystal Drive Circuit
This circuit comprises 80 sets of multiplexers to generate
four-value level for the liquid crystal drive. Various
combinations of display data in the display data latch and
the FR signals output the liquid crystal waveforms as
shown in Fig. 3.
(10) Reset Circuit
This circuit detects the RES input rise or fall edge and
performs initialization.
RES input is level-sensed, then, as shown in Table 1, the
MPU interface mode is selected.
3–10
FR
When connecting to MPU, the output port of MPU is
used and the reset signal is input through software.
Otherwise, the circuit is connected to the reset terminal
of MPU and the
reset signal via the inverter is
input for 80-system MPU, and the
reset signal for
the 68-system MPU.
RES input causes initialization of S1D15210, and
initialization of the MPU is performed at the same time.
Failure of initialization by the RES terminal upon applying
power may lead to a status that cannot be released.
If the reset command is used, items 2 and 5 of the
following initial settings are to be executed:
(11) Status in Initial Setting
1. Display OFF
2. To set the display start line register on the first line.
3. Display All Lamps OFF
4. To set the column address counter to address 0.
5. To set the page address counter to the third page.
6. ADC select: normal rotation (ADC command = "0",
ADC status flag "1")
7. Read/Modify/Write OFF
EPSON
Rev. 1.1
S1D15210 Series
0 1 2 3
0 1 2 3
15 0 1 2 3
31 0 1 2 3
FR
COM0
COM0
COM1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM2
COM8
COM9
COM10
COM11
COM12
SEG0
COM13
COM14
SEG4
SEG3
SEG2
SEG1
SEG0
COM15
SEG1
* The S1D15210 doesn't
have V C4, V CI pins.
COM0—SEG0
COM0—SEG1
15
31
V DD
V SS
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
V DD
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
V DD
-V1
-V2
-V3
-V4
-V5
Figure 4 LCD drive waveforms example
Rev. 1.1
EPSON
3–11
S1D15210 Series
8. COMMANDS
Table 3
Command
Code
Function
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
(1)Display On/OFF
0
1
0
1
0
1
0
1
1
1
0/1
(2)Display start line
0
1
0
1
1
0
Display start address (0 to 31)
Specifies RAM line corresponding to top
line of display.
(3)Set page address
0
1
0
1
0
1
1
Sets display RAM page in page address
register.
0
1
0
0
(4) Set column
(segment) address
(5) Read status
0
0
1
Busy
1
0
Page (0 to 3)
0
0
1: ON, 0: OFF
Sets display RAM column address in
Column address (0 to 79)
ADC ON/OFF Reset
Turns display on or off.
column address register.
Reads the following status:
0
BUSY
1: Busy
0: Ready
ADC
1: CW output
ON/OFF
0: CCW output
1: Display off
RESET
0: Display on
1: Being reset
0
0: Normal
(6) Write display data
1
1
0
Write data
(7) Read display data
1
0
1
Read data
(8) Select ADC
(9) All-display
0
1
0
1
0
1
0
0
0
0
0/1
0
ON/OFF
(10) Read-Modify-Write 0
1
0
1
0
1
0
0
1
0
0/1
1
0
1
1
1
0
0
0
0
0
(11) End
0
1
0
1
1
1
0
1
1
1
0
(12) Reset
0
1
0
1
1
1
0
0
0
1
0
3–12
Writes data from data bus into display RAM.
Reads data from display RAM onto data
EPSON
bus.
0: CW output, 1: CCW output
Selects static driving operation.
1: Static drive, 0: Normal driving
Read-modify-write ON
Read-modify-write OFF
Software reset
Rev. 1.1
S1D15210 Series
Table 3 is the command table. The S1D15210 identifies a data bus using a combination of A0 and R/W (RD or WR)
signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed
is very high. The busy check is usually not required.
(1) Display ON/OFF
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
D
AEH, AFH
This command turns the display on and off.
• D=1: Display ON
• D=0: Display OFF
(2) Display Start Line
This command specifies the line address shown in Figure 2 and indicates the display line that corresponds to COM0. The
display area begins at the specified line address and continues in the line address increment direction. This area having
the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command,
the vertical smooth scrolling and paging can be used.
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
A4
A3
A2
A1
A0
C0H to DFH
This command loads the display start line register.
A4 A3 A2 A1 A0 Line Address
0
0
0
0
1
1
0
0
:
:
1
0
0
0
1
1
1
0
1
:
:
31
See Figure 2.
(3) Set Page Address
This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed
by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified.
The display status is not changed even when the page address is changed.
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
1
1
0
A1
A0
B8H to BBH
This command loads the page address register.
A1 A0 Page Address
0
0
1
1
0
1
0
1
0
1
2
3
See Figure 2.
Rev. 1.1
EPSON
3–13
S1D15210 Series
(4) Set Column Address
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU
continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU
can access to data continuously. The column address stops to be incremented at address 80, and the page address is not
changed continuously.
A0
(E)
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
A6
A5
A4
A3
A2
A1
A0
00H to 4FH
This command loads the column address register.
A6 A5 A4 A3 A2 A1 A0 Column Address
0
0
0
0
0
0
1
0
0
0
0
:
:
1
0
0
0
0
0
1
1
1
1
0
1
:
:
79
(5) Read Status
A0
(E)
RD
(R/W)
WR
0
0
1
D7
D6
D5
D4
BUSY ADC ON/OFF RESET
D3
D2
D1
D0
0
0
0
0
Reading the command I/O register (A0=0) yields system status information.
• The busy bit indicates whether the driver will accept a command or not.
Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.
Busy=0: The driver will accept a new command.
• The ADC bit indicates the way column addresses are assigned to segment drivers.
ADC=1: Normal. Column address n → segment driver n.
ADC=0: Inverted. Column address 79-n → segment driver u.
• The ON/OFF bit indicates the current status of the display.
It is the inverse of the polarity of the display ON/OFF command.
ON/OFF=1: Display OFF
ON/OFF=0: Display ON
• The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode.
RESET=1: Currently executing reset command.
RESET=0: Normal operation
(6) Write Display Data
A0
(E)
RD
(R/W)
WR
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data
Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page
address registers and then increments the column address register by one.
3–14
EPSON
Rev. 1.1
S1D15210 Series
(7) Read Display Data
A0
(E)
RD
(R/W)
WR
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data
Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data
RAM location specified by the contents of the column address and page address registers and then increments the column
address register.
After loading a new address into the column address register one dummy read is required before valid data is obtained.
(8) Select ADC
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
0
0
D
A0H, A1H
This command selects the relationship between display data RAM column addresses and segment drivers.
D=1: SEG0 ← column address 4FH, … (inverted)
D=0: SEG0 ← column address 00H, … (normal)
This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit
board design. See Figure 2 for a table of segments and column addresses for the two values of D.
(9) All Display ON/OFF
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
0
D
A4H, A5H
Forces display on and all common outputs to be selected.
D=1: All display on
D=0: All display off
Rev. 1.1
EPSON
3–15
S1D15210 Series
(10) Read-Modify-Write
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
E0H
This command defeats column address register auto-increment after data reads. The current conetents of the column
address register are saved. This mode remains active until an End command is received.
• Operation sequence during cursor display
When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write
command. This function can reduce the load of MPU when data change is repeated at a specific display area (such as cursor
blinking).
* Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column
Address Set command cannot be used.
Set Page Address
Set Column Address
Read-Modify-Write
Dummy Read
Read Data
Write Data
No
Completed?
Yes
End
(11) End
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
EEH
This command cancels read-modify-write mode and restores the contents of the column address register to their value prior
to the receipt of the Read-Modify-Write command.
Return
Column address
N
N+1
N+2
N+3
Read-Modify-Write mode is selected.
3–16
EPSON
N+m
N
End
Rev. 1.1
S1D15210 Series
(12) Reset
A0
(E)
RD
(R/W)
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
0
E2H
This command clears
• the display start line register.
• and set page address register to 3 page.
It does not affect the contents of the display data RAM.
When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead
of this Reset signal.
(13) Power Save (Combination command)
The Power Save mode is selected if the static drive is turned ON when the display is OFF. The current consumption can
be reduced to almost the static current level. In the Power Save mode:
(a) The LCD drive is stopped, and the segment and common driver outputs are set to the VDD level.
(b) The external oscillation clock input is inhibited, and the OSC2 is set to the floating mode.
(c) The display and operation modes are kept.
The Power Save mode is released when the display is turned ON or when the static drive is turned OFF. If the LCD drive
voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the
Power Save signal.
VC5
Power save
signal
VC5
VC3
VC2
VSS
Rev. 1.1
S1D15210
VSS
EPSON
3–17
S1D15210 Series
9. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Supply voltage (1)
VDD
–0.3 to +7.0
V
Supply voltage (2)
VC5
–0.3 to +7.0
V
Supply voltage (3)
VC3, V C2
–0.3 to VC5+3
V
Input voltage
VIN
–0.3 to VDD +0.3
V
Output voltage
VO
–0.3 to VDD +0.3
V
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. All voltages are specified relative to VSS = 0 V.
2. The following relation must be always hold
VC5 ≥ VC3 ≥ V C2 ≥ VSS
3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional
operation under these conditions is not implied.
Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to
avoid thermally stressing the package during board assembly.
10. ELECTRICAL CHARCTERISTICS
DC Characteristics
Ta = –20 to 75 °C, VDD = 0 V unless stated otherwise
Parameter
Symbol
Operating Recommended
voltage (1)
See note 1. Allowable
VDD
Condition
Min.
Rating
Typ.
Max.
4.5
5.0
5.5
2.4
Input leakage current
Output leakage current
VC5
VC3
VC2
VIH
VIL
VOH1
VOH2
VOL1
VOL2
IL1
IL2
3.5
0.5×VC5
VSS
0.8×VDD
VSS
IOH = –1 mA
0.8×VDD
VDD = –2.7 V IOH = –0.5mA 0.8×VDD
IOL = 1 mA
VSS
VDD = 2.7 V IOL = 0.5 mA
VSS
–1.0
–3.0
LCD driver ON resistance
RON
Ta = 25 °C
Allowable
Operating
Allowable
voltage (2)
Allowable
High-level input voltage
Low-level input voltage
V5 = 6.0 V
V5 = 3.5 V
—
—
—
6.0
—
—
—
—
—
—
—
—
—
6.0
VC5
0.5×V C5
VDD
0.2×V DD
VDD
VDD
0.2×V DD
0.2×V DD
1.0
3.0
1.3
3.0
2.5
6.0
Unit
Applicable Pin
V
VDD
*1
V
V
V
V
V
V
V
V
V
µA
µA
VC5 *2
VC3
VC2
*3
*3
*4
*4
*4
*4
*5
*6
kΩ
SEG0 to 79,
*7
(continued)
3–18
EPSON
Rev. 1.1
S1D15210 Series
Parameter
Static current dissipation
During
Dynamic current display
dissipation
Symbol
Condition
ISSQ
CS = CL = FR = VDD
V DD = 5 V
V C5 = 5 V
Ta = 25°C
fCL = 2 KHz
V DD = 3.0 V
V C5 = 5 V
Ta = 25°C
fCL = 2 KHz
V DD = 5 V tcyc = 200 KHz
V DD = 3.0 V tcyc = 200 KHz
Ta = 25 °C, f = 1 MHz
ISS (1)
During
access
Input pin capacitance
ISS (2)
CIN
Min.
—
Rating
Typ.
0.01
Max.
1.0
—
2.0
—
—
—
—
Unit
Applicable Pin
µA
V SS
5.0
µA
V SS
*8
1.5
4.5
µA
V SS
*8
300
150
5.0
500
300
8.0
µA
V SS
*9
All input pins
pF
Notes: 1. Although this equipment is capable of withstanding a wide range of operating voltage, it is not designed
for withstanding a sudden voltage change while accessing the MPU.
2. Ranges of Operating Voltage for VDD and VC5 Systems
8
6
VC5[V]
4
Range of
Operation
3.5
2
2.4
0
2
4
6
8
VDD[V]
3.
4.
5.
6.
7.
D0 to D7, A0, RES, CS, RD, (E), WR, (R/W), CL, and FR terminals.
D0 to D7 terminals.
A0, RES, CS, RD (E), WR (R/W), and CL terminals.
FR, D0 to D7 (in high impedance status) terminals.
These are resistance values obtained when voltage of 0.1 V is applied between the output terminals
(SEG) and the respective power terminals (VC3, VC2). These are defined within the range of the
operating voltage.
8. This is current consumed by a single IC, not including current required by the LCD panel capacity or by
the wiring capacity.
9. This indicates current consumption at the time the pattern of vertical stripes is always wrapped in by the
tcyc. Current consumption while accessing roughly proportionate to the tcyc for access. If not accessed,
only ISS1 is relevant.
Rev. 1.1
EPSON
3–19
S1D15210 Series
Timing Characteristics
• System Bus Read/Write Characteristic 1 (80-system MPU)
tAH8
A0 CS
tCYC8
tAW8
tCC
WR RD
tDH8
tDS8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
(VDD = 5.0 V ± 10%, Ta = –40 to 85°C)
Parameter
Signal
Address hold time
Address set-up time
System cycle time
Control pulse
Write
width
Read
Data set-up time
Data hold time
RD access time
Output disable time
A0
CS
WR
RD
D0 to D7
Symbol
Condition
Min.
tAH8
tAW8
—
10
20
—
—
ns
ns
tCYC8
—
1000
—
ns
tCC
—
100
—
ns
200
—
ns
tDS8
tDH8
—
80
10
—
—
ns
ns
—
10
180
90
ns
ns
tACC8
tOH8
CL = 100 pF
Max.
Unit
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Parameter
Signal
Address hold time
Address set-up time
System cycle time
Control pulse
Write
width
Read
Data set-up time
Data hold time
RD access time
Output disable time
A0
CS
WR
RD
D0 to D7
Symbol
Condition
Min.
tAH8
tAW8
—
20
40
—
—
ns
ns
tCYC8
—
2000
—
ns
tCC
—
200
—
ns
400
—
ns
tDS8
tDH8
—
160
20
—
—
ns
ns
—
20
360
180
ns
ns
tACC8
tOH8
CL = 100 pF
Max.
Unit
Note: * The rise time (tr) and fall time (tf) of the input signal are defined within 15 ns. Tr and tf are to define the
AC timing of the input waveform, and operates without any problem even when a signal beyond the
specification (15 ns) is input. However, it should be noted that the bigger tr and and tf are, the lower the
margin for noise becomes.
* All timings are defined based on the standards of 20% and 80% of VDD.
3–20
EPSON
Rev. 1.1
S1D15210 Series
• System Bus Read/Write Characteristic 2 (68-system MPU)
tCYC6
E
tAW6
tEW
tAH6
R/W
A0 CS
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
(VDD = 5.0 V ± 10%, Ta = –40 to 85°C)
Parameter
Signal
System cycle time *1
Address set-up time
Address hold time
Data set-up time
Data hold time
Output disable time
Access time
Enable pulse
Write
width
Read
A0
CS
R/W
D0 to D7
E
Symbol
Condition
Min.
Max.
Unit
tCYC6
—
1000
—
ns
tAW6
tAH6
—
20
10
—
—
ns
ns
tDS6
tDH6
—
80
10
—
—
ns
ns
tOH6
tACC6
CL = 100 pF
10
90
180
ns
ns
100
—
ns
200
—
ns
—
tEW
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Parameter
Signal
System cycle time *1
Address set-up time
Address hold time
Data set-up time
Data hold time
Output disable time
Access time
Enable pulse
Write
width
Read
A0
CS
R/W
D0 to D7
E
Symbol
Condition
Min.
Max.
Unit
tCYC6
—
2000
—
ns
tAW6
tAH6
—
40
20
—
—
ns
ns
tDS6
tDH6
—
160
20
—
—
ns
ns
tOH6
tACC6
CL = 100 pF
20
180
360
ns
ns
200
—
ns
400
—
ns
tEW
—
1 "tCYC6" represents the cycle of signal E when CS = LOW. If CS = HIGH → LOW, it is necessary to
secure tCYC6 after CS = LOW is attained.
Note: * The rise time (tr) and fall time (tf) of the input signal are defined within 15 ns. Tr and tf are to define the
AC timing of the input waveform, and operates without any problem even when a signal beyond the
specification (15 ns) is input. However, it should be noted that the bigger tr and and tf are, the lower the
margin for noise becomes.
* All timings are defined based on the standards of 20% and 80% of VDD.
Notes:
Rev. 1.1
EPSON
3–21
S1D15210 Series
• Display Control Input Timing
CL
tWLCL
tWHCL
tDFR
tf
tr
FR
Parameter
Signal
Low-level pulse width
High-level pulse width
Rise time
CL
Fall time
FR delay time
Parameter
FR
Signal
Low-level pulse width
Highlevel pulse width
Rise time
CL
Fall time
FR delay time
FR
Symbol
Condition
(VDD = 5.0 V ± 10%, Ta = –40 to 85°C)
Min.
Typ.
Max.
Unit
tWLCL
—
35
—
—
µs
tWHCL
—
35
—
—
µs
tr
—
—
30
150
ns
tf
—
—
30
150
ns
tDFR
—
–2.0
0.2
2.0
µs
Symbol
Condition
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Min.
Typ.
Max.
Unit
tWLCL
—
70
—
—
µs
tWHCL
—
70
—
—
µs
tr
—
—
60
300
ns
tf
—
—
60
300
ns
tDFR
—
–4.0
0.4
4.0
µs
Note: All timings are defined based on the standards of 20% and 80% of VDD.
3–22
EPSON
Rev. 1.1
S1D15210 Series
• Reset Input Timing (80-system MPU)
RES
tRW8
tR8
Internal
status
Parameter
Under resetting
Signal
Symbol
Reset time
Reset HIGH pulse width
RES
Condition
Reset completed
(VDD = 5.0 V ± 10%, Ta = –40 to 85°C)
Min.
Typ.
Max.
Unit
tR8
2.0
—
—
µs
tRW8
1.0
—
—
µs
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Parameter
Signal
Symbol
Reset time
Reset HIGH pulse width
RES
Condition
Min.
Typ.
Max.
Unit
tR8
4.0
—
—
µs
tRW8
2.0
—
—
µs
Note: * The rise time (tr) and fall time (tf) of the input signal are defined within 15 ns. Tr and tf are to define the AC
timing of the input waveform, and operates without any problem even when a signal beyond the specification
(15 ns) is input. However, it should be noted that the bigger tr and and tf are, the lower the margin for noise
becomes.
* All timings are defined based on the standards of 10% and 90% of VDD.
• Reset Input Timing (68-system MPU)
tRW6
RES
tR6
Internal
status
Parameter
Under resetting
Signal
Reset time
Reset LOW pulse width
RES
Symbol
Condition
Reset completed
(VDD = 5.0 V ± 10%, Ta = –40 to 85°C)
Min.
Typ.
Max.
Unit
tR6
2.0
—
—
µs
tRW6
1.0
—
—
µs
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Parameter
Signal
Reset time
Reset LOW pulse width
RES
Symbol
Condition
Min.
Typ.
Max.
Unit
tR6
4.0
—
—
µs
tRW6
2.0
—
—
µs
Note: * The rise time (tr) and fall time (tf) of the input signal are defined within 15 ns. Tr and tf are to define the
AC timing of the input waveform, and operates without any problem even when a signal beyond the
specification (15 ns) is input. However, it should be noted that the bigger tr and and tf are, the lower the
margin for noise becomes.
* All timings are defined based on the standards of 10% and 90% of VDD.
Rev. 1.1
EPSON
3–23
S1D15210 Series
11. EXAMPLE OF CONNECTION
MPU Interface (MPU example: S1C88316)
A0(R00)
A0
CE0 to CE3(R30 to R33) ✽1
CS
CL(R25)
CL
RD(R23)
RD
WR(R24)
WR
S1C88316
D0 to D7(P00 to P07)
✽3
Notes:
S1D15210
D0 to D7
RES ✽2
FR(R26)
FR
VC2
VC2
VC3
VC3
VC5
VC5
1 See S1C88316 technical Manual for the signals of S1C88316.
2 The reset input for 80-system MPU interface of S1D15210 is the opposite phase of that for the reset
input of S1C88316.
3 For the reset input of S1D15210, we recommend that you use the output port of S1C88316 and send the
reset signals through software.
EXAMPLE OF CONNECTIONS TO LIQUID CRYSTAL PANEL
Liquid crystal panel (32×131)
COM
3–24
SEG
SEG
S1C88316
(master)
S1D15210
(slave)
EPSON
Rev. 1.1
4. S1D15206 Series
Rev. 3.5
Contents
1. DESCRIPTION ................................................................................................................................................ 4-1
2. FEATURES ...................................................................................................................................................... 4-1
3. BLOCK DIAGRAM (S1D15206*00**) ............................................................................................................ 4-2
4. PIN LAYOUT ................................................................................................................................................... 4-3
5. PIN DESCRIPTION ......................................................................................................................................... 4-6
6. FUNCTION DESCRIPTION ............................................................................................................................. 4-8
7. COMMANDS .................................................................................................................................................4-18
8. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 4-22
9. ELECTRICAL CHARACTERISTICS ..............................................................................................................4-23
10. EXTERNAL WIRINGS ................................................................................................................................... 4-32
11. DIMENSIONS ................................................................................................................................................4-37
–i–
Rev. 3.5
S1D15206 Series
1. DESCRIPTION
• High-speed, 8-bit microprocessor interface allowing direct
connection to both the 8080 and 6800
• Supported serial interface
• Rich command functions (upward compatible to S1D15200
Series); they are Read/Write Display Data, Display On/Off
Switching, Set Page Address, Set Initial Display Line, Set
Column Address, Read Status, Static Drive On/Off Switching, Select Duty, Duty+1, Read-Modify-Write, Select
Segment Driver Direction, Power Save, Reset, Set Power
Control, Set Electronic Controls, Clock Stop.
• On-chip CR oscillator circuit
• On-chip LCD power circuit (The on-chip and external LCD
power supplies are software selectable.)
• Very low power consumption
• Flexible power voltages; 2.4 to 6.0 V (VDD-VSS) and -13.0
to -4.0 V (VDD -V5)
• -40 to +85°C wide operating temperature range
• CMOS process
• 128-pin QFP5 package with aluminum pad or Au bump
The S1D15206 series is a single-chip LCD driver for dot-matrix
liquid crystal displays (LCD’s). It accepts serial or 8-bit parallel
display data directly from a microprocessor and stores data in an onchip display RAM. It can generate an LCD drive signal independent
from microprocessor clock.
As the S1D15206 series features the very low power dissipation and
wide operating voltage range, it can easily realize a powerful but
compact display unit having a small battery.
A single chip of S1D15206 series can drive a 17×80-pixel or 33×64pixel LCD panel.
(Note: The S1D15206 series are not designed to have EMI resistance.)
2. FEATURES
• Direct data display using the display RAM. When RAM
data bit is 0, it is not displayed; when 1, it is displayed.
• Large 80×33-bit RAM capacity
• On-chip LCD driver circuit (97 segment and common
drivers)
Series Specifications (for 128-pin flat package)
Model
Operating clock
fCL
(Internal OSC) (Typ.)
S1D15206F00A*
2.9
S1D15206F11A*
5.8
S1D15206F10A*
2.9
S1D15206F14A*
20 kHz
2.9
S1D15208F00A*
2.9
S1D15208D11B*
5.8
COMS pin positions
Common
driver
VREG
type
COM
pin positions
Type 1
1/8, 1/9, 1/16, 1/17
80
17
QFP
Type A
5
Type B
2.9
S1D15206F14Y*
VREG type
Segment
driver
Duty
Type 2
26
Type A
1/32, 1/33
64
33
Type 1
5
—
Type 1 VREG (Built-in power supply regulating voltage)
Temperature gradient: -0.17% /°C
Type 2 VREG (Built-in power supply regulating voltage)
Temperature gradient: 0.00% /°C
Refer to No. P3 (Package pin layout), No. P4 (PAD layout) and No. P5 (PAD coordinates).
An S1D15206 series package has one of following subcodes according to its package type (an example of S1D15206):
S1D15206F****:
128-pin QFP5 flat package
S1D15206F**Y*:
128-pin QFP26 flat package
S1D15206D****:
Bear chip
S1D15206D**A* :Al-pad chip
S1D15206D**B* :Au-bump chip
S1D15206T****:
TCP
Rev.3.5
EPSON
4–1
S1D15206 Series
3. BLOCK DIAGRAM (S1D15206*00**)
CMOS
SEG0 ····························· SEG79 COM0 ···· COM15
···············································
·····················
VDD
V1
V2
V3
V4
V5
Voltage
select
circuit
Segment driver
COMS
VSS
Common driver
Shift register
CAP1+
Display data latch
CAP1–
CAP2+
I/O buffer circuit
80x33-dot display data RAM
Initial display line register
Power circuit
VOUT
Line counter
VR
Line address decoder
CAP2–
Column address decoder
Page address
register
7-bit column address counter
FR
Display timing
generator circuit
M/S
7-bit column address register
Bus holder
Status
register
Command decoder
Microprocessor interface
Oscillator
I/O buffer
D0
SR2 SR1 WR RD CS2 CS1 A0
4–2
CL
EPSON
D1
D2
D3
D4
D5
D6
D7
Rev.3.5
S1D15206 Series
4. PIN LAYOUT
65
70
80
90
64
103
110
50
Index
38
39
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COMS
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
[COM15]
(COM31) [COM14]
(COM30) [COM13]
(COM29) [COM12]
(COM28) [COM11]
(COM27) [COM10]
(COM26) [COM 9]
(COM25) [COM 8]
(COM24) [COM 7]
(COM23) [COM 6]
[COMS ]
[COM 0]
[COM 1]
[COM 2]
[COM 3]
[COM 4]
[COM 5]
V1
V2
V3
V4
V5
VR
VDD
VOUT
CAP2CAP2+
CAP1CAP1+
VSS
M/S
SR2
SR1
WR
RD
CS2
CS1
A0
FR
CL
D0
D1
D2
D3
D4
D5
D6
D7
COM0
COM1
COM2
COM3
COM4
COM5
COM6
(COM16)
(COM17)
(COM18)
(COM19)
(COM20)
(COM21)
(COM22)
30
128
20
120
10
(COM15)
(COM14)
(COM13)
(COM12)
(COM11)
(COM10)
(COM 9)
(COM 8)
(COM 7)
(COM 6)
(COM 5)
(COM 4)
(COM 3)
(COM 2)
(COM 1)
(COM 0)
1
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
102
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
Package Pin Assignment
* Pin name in ( ) apply to S1D15208.
* Pin name in [ ] apply to S1D15206D10**(CMOS Pin=Type B).
Rev.3.5
EPSON
4–3
S1D15206 Series
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
Pad Layout
102
90
80
70
65
Y
103
64
110
50
X
120
128
10
20
30
37 38
[COM15]
[COM14]
[COM13]
[COM12]
[COM11]
[COM10]
[COM 9]
[COM 8]
[COM 7]
[COM 6]
[COM 5]
[COMS ]
[COM 0]
[COM 1]
[COM 2]
[COM 3]
[COM 4]
V1
V2
V3
V4
V5
VR
VDD
VOUT
CAP2CAP2+
CAP1CAP1+
1
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COMS
COM15 (COM31)
COM14 (COM30)
COM13 (COM29)
COM12 (COM28)
COM11 (COM27)
COM10 (COM26)
COM9 (COM25)
COM8 (COM24)
COM7 (COM23)
COM6 (COM22)
VSS
M/S
SR2
SR1
WR
RD
CS2
CS1
A0
FR
CL
D0
D1
D2
D3
D4
D5
D6
D7
COM0 (COM16)
COM1 (COM17)
COM2 (COM18)
COM3 (COM19)
COM4 (COM20)
COM5 (COM21)
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64 (COM15)
SEG65 (COM14)
SEG66 (COM13)
SEG67 (COM12)
SEG68 (COM11)
SEG69 (COM10)
SEG70 (COM9)
SEG71 (COM8)
SEG72 (COM7)
SEG73 (COM6)
SEG74 (COM5)
SEG75 (COM4)
SEG76 (COM3)
SEG77 (COM2)
SEG78 (COM1)
SEG79 (COM0)
* Pin names in (
* Pin names in [
) apply to S1D15208.
] apply to S1D15206D10** (CMOS pin = Type B).
Al- pad chip
• Chip size
5.92 mm × 4.68 mm
• Chip thickness0.4 mm
• Pad opening 90.2 µm × 90.2 µm
• Pad pitch
130 µm (Min)
Au- bump chip (reference)
• Chip size
5.92 mm × 4.68 mm
• Chip thickness0.4 mm
• Bump size
81.7 µm × 81.7 µm
• Bump height 22.5 µm
4–4
EPSON
Rev.3.5
S1D15206 Series
Pad Center Coordinates
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN Name
V1
V2
V3
V4
V5
VR
VDD
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
M/S
SR2
SR1
WR
RD
CS2
CS1
A0
FR
CL
D0
D1
D2
D3
D4
D5
D6
D7
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COMS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
* Pin names in (
* Pin names in [
Rev.3.5
(COM16)
(COM17)
(COM18)
(COM19)
(COM20)
(COM21)
(COM22)
(COM23)
(COM24)
(COM25)
(COM26)
(COM27)
(COM28)
(COM29)
(COM30)
(COM31)
[CMOS ]
[COM0 ]
[COM1 ]
[COM2 ]
[COM3 ]
[COM4 ]
[COM5 ]
[COM6 ]
[COM7 ]
[COM8 ]
[COM9 ]
[COM10]
[COM11]
[COM12]
[COM13]
[COM14]
[COM15]
X
Y
PAD No.
–2767
–2637
–2507
–2377
–2246
–2116
–1985
–1857
–1727
–1522
–1318
–1113
–553
–356
–226
–95
35
165
295
425
555
719
849
979
1109
1239
1369
1500
1630
1760
1890
2069
2199
2329
2459
2589
2719
2802
–2106
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
–2149
–2176
–2166
–2185
–1654
–1524
–1393
–1263
–1133
–1003
–873
–743
–612
–482
–352
–193
–63
67
197
327
457
588
718
848
978
1108
1238
1368
1499
1629
1759
PIN Name
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
X
2516
2367
2218
2088
1957
1827
1697
1567
1437
1307
1177
1046
916
786
656
526
396
266
135
5
–125
–255
–385
–515
–646
–776
–906
–1036
–1166
–1296
–1426
–1557
–1687
–1817
–1947
–2077
–2226
–2375
–2802
(COM15)
(COM14)
(COM13)
(COM12)
(COM11)
(COM10)
(COM9)
(COM8)
(COM7)
(COM6)
(COM5)
(COM4)
(COM3)
(COM2)
(COM1)
(COM0)
Y
2185
1932
1802
1672
1541
1411
1281
1151
1021
891
760
599
469
339
209
78
–52
–182
–312
–442
–572
–703
–833
–963
–1093
–1223
–1353
) apply to S1D15208.
] apply to S1D15206D10* (CMOS pin = Type B).
EPSON
4–5
S1D15206 Series
5. PIN DESCRIPTION
Power Supply
I/O
Description
Number of pins
VDD
Name
Supply
+5VDC power supply. Common to microprocessor power supply pin VCC.
1
VSS
Supply
Ground
1
V1, V2
V3, V4
V5
Supply
LCD driver supply voltages. The Set Power Control command can switch
the on-chip and external power supply modes of these pins.
When external mode selects, the voltage determined by LCD cell is
impedance-converted by a resistive divider or an operational amplifier for
application. Voltages should be the following relationship:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
When master mode selects, these voltages are generated on the chip:
5
S1D15206
V1
V2
V3
V4
1/5
2/5
3/5
4/5
V5
V5
V5
V5
S1D15208
1/7
2/7
5/7
6/7
V5
V5
V5
V5
LCD Driver Supplies
Name
I/O
Description
Number of pins
CAP1+
O
DC/DC voltage converter capacitor 1 positive connection
1
CAP1–
O
DC/DC voltage converter capacitor 1 negative connection
1
CAP2+
O
DC/DC voltage converter capacitor 2 positive connection
1
CAP2–
O
DC/DC voltage converter capacitor 2 negative connection
1
VOUT
O
DC/DC voltage converter output
1
VR
I
Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
1
Microprocessor Interface
Name
I/O
D0 to D7
(SI)
(SCL)
I/O
A0
Number of pins
8
I
Control/display data flag input. It is connected to the LSB of microprocessor address bus. When LOW, the data on D0 to D7 is control data.
When HIGH, the data on D0 to D7 is display data.
1
CS1
CS2
I
Chip select input. Data input/output is enabled when -CS1 is LOW and
CS2 is HIGH.
2
RD
(E)
I
• Read enable input. When interfacing to an 8080-series microprocessor
and when its RD is LOW, the S1D15206 series data bus output is enabled.
• When interfacing to an 6800-series microprocessor and when its R/W
Enable (E) is HIGH, the S1D15206 series R/W input is enabled.
1
• Write enable input. When interfacing to an 8080-series microprocessor,
WR is active LOW.
• When interfacing to an 6800-series microprocessor,
it will be read mode when R/W is HIGH and it will be write mode when
R/W is LOW.
R/W = “1” : Read
R/W = “0” : Write
1
WR
(R/W)
4–6
Description
Data input/outputs. The 8-bit bidirectional data buses to be connected
to the standard 8-bit microprocessor data buses. When the serial
interface selects, D7 is serial data input (SI) and D6 is serial clock input
(SCL).
EPSON
Rev.3.5
S1D15206 Series
Name
I/O
SR1,
SR2
I
Description
Number of pins
Microprocessor interface select, and parallel/serial data input select.
SR1
0
2
SR2
1
Type
8080 microprocessor bus (parallel
input)
1
1
6800 microprocessor bus (parallel
input)
1
0
Serial input
0
0
Reset
* In serial mode, no data can be read from RAM and D0 to
D5 are HZ. RD and WR must be HIGH or LOW.
When set for the 68 family MPU, the SR1 and SR2 timing must match or
SR1 must rise first.
LCD Driver Outputs
Name
I/O
M/S
I
Description
Number of pins
Normally “1”.
1
CL
I/O
Normally “1”.
1
FR
I/O
Normally “1”.
1
SEGn
O
LCD segment driver output. VDD, V2, V3, or V5 can select according
to the display RAM and FR signal.
80 (S1D15206)
or 64 (S1D15208)
RAM data
FR signal Output voltage
of SEGn
1
VDD
1
0
V5
1
V2
0
0
V3
Power save
–
VDD
COMn
O
LCD common driver output. VDD, V1, V4, or V5 can select according
to IC internal scan signal and FR signal. The common scan sequence
is reversed in slave mode.
Internal scan
signal
1
0
Power save
COMS
O
FR
signal
1
0
1
0
–
16 (S1D15206)
or 32 (S1D15208)
Output voltage
of COMn
V5
VDD
V1
V4
VDD
Indicator COM output. COMS pin is equivalent to following COM output
pin when Duty+1 command is running:
1
S1D15206
S1D15208
1/9 duty 1/17 duty 1/33 duty
Indicator
COMS
output
Rev.3.5
COM8
EPSON
COM16
COM32
4–7
S1D15206 Series
6. FUNCTION DESCRIPTION
MPU Interface
Parallel/Serial Interface
The S1D15206 series can transfer data via 8-bit bidirectional data buses D0 to D7 or via serial data input D7 (SI). The 8-bit parallel data input
or serial data input, 8080/6800-series microprocessor, and reset status can select according to SR1 and SR2.
No data can be read from RAM and no status can be read during serial data input. Also, RD and WR are high or low, and D0 to D5 are open.
Table 1
SR1
SR2
0
1
1
Type
CS1
CS2
A0
RD
WR
Data (D0 to D7)
8080 microprocessor
bus (parallel)
CS1
CS2
A0
RD
WR
D0 to D7
1
6800 microprocessor
bus (parallel)
CS1
CS2
A0
E
R/W
D0 to D7
1
0
Serial input
CS1
CS2
A0
0/1
0/1
D6 (SCL) and D7 (SI)
0
0
Reset
CS1
CS2
A0
RD
WR
———————
* When set for the 68 family interface, the SR1 and SR2 timing must match or SR1 must rise first.
SR1
SR2
The 68 family interface
RESET
Data Bus Signals
The S1D15206 series identifies the data bus signal according to A0, RD, and WR (E, R/W) signals.
Table 2
Common
6800 processor
8080 processor
A0
WR (R/W)
RD
WR
1
1
0
1
Reads display data.
1
0
1
0
Writes display data.
0
1
0
1
Reads status.
0
0
1
0
Writes control data in internal register. (commands)
Function
Serial Interface (SR1 is high and SR2 is low)
The serial interface consists of an 8-bit shift register and a 3-bit
counter. The serial data input and serial clock input are enabled
when CS1 is low and CS2 is high (in chip select status). When chip
is not selected, the shift register and counter are reset.
When serial data input is enabled by SR1 and SR2, D7 (SI) receives
serial data and D6 (SCL) receives serial clock. Serial data of D7, D6,
..., D0 is read at D7 in this sequence when serial clock goes high.
They are converted into 8-bit parallel data and processed on rising
4–8
edge of every eighth serial clock signal.
The serial data input is determined to be the display data when A0
is high, and it is control data when A0 is low. A0 is read on rising
edge of every eighth clock signal.
Figure 1 shows a timing chart of serial interface signals. The serial
clock signal must be terminated correctly against termination reflection and ambient noise. Operation checkout on the actual machine
is recommended.
EPSON
Rev.3.5
S1D15206 Series
CS1
CS2
D7(S1)
D6(SCL)
D7
D6
2
1
D4
D5
3
4
D3
D2
5
6
D1
7
D0
8
D7
9
D6
10
D5
11
12
A0
Figure 1
from display RAM in the first read (dummy) cycle, stores it in bus
holder, and outputs it onto system bus in the next data read cycle.
Also, the microprocessor temporarily stores display data in bus
holder, and stores it in display RAM until the next data write cycle
starts.
When viewed from the microprocessor, the S1D15206 series access
speed greatly depends on the cycle time rather than access time to the
display RAM (tACC and tDS). It shows the data transfer speed to/
from the microprocessor can increase. If the cycle time is inappropriate, the microprocessor can insert the NOP instruction that is
equivalent to the wait cycle setup. However, there is a restriction in
the display RAM read sequence. When an address is set, the
specified address data is NOT output at the immediately following
read instruction. The address data is output during second data read.
A single dummy read must be inserted after address setup and after
write cycle (refer to Figure 2).
Chip Select Inputs
The S1D15206 series can interface to microprocessor when CS1 is
LOW and CS2 is HIGH.
When these pins are set to any other combination, D0 to D7 are high
impedance. A0, RD, and WR input are disabled. However, the reset
signal is entered regardless of CS1 and CS2 setup. The internal IC
status including LCD driver circuit is held until a reset signal is
entered.
Access to Display Data RAM and Internal Registers
The S1D15206 series can perform a series of pipeline processing
between LSI’s using bus holder of internal data bus in order to match
the operating frequency of display RAM and internal registers with
the microprocessor. For example, the microprocessor reads data
•Write
WR
MPU
DATA
Internal
timing
n
n+1
Latched
n
Bus holder
n+2
n+1
n+3
n+2
n+3
Write signal
•Read
WR
MPU
RD
DATA
N
N
n
n+1
Address
preset
Read signal
Internal
timing
Preset
Column
address
Incremented
N+1
N
N
Bus holder
Set address n
n
Dummy read
N+2
n+1
Read address n
n+2
Read address n+1
n: Current data
N: Dummy data
Figure 2
Rev.3.5
EPSON
4–9
S1D15206 Series
Busy Flag
The Busy flag is set when the S1D15206 series starts to operate.
During operating, it accepts Read Status instruction only. The busy
flag signal is output at pin D7 when Read Status is issued. If the cycle
time (tcyc ) is correct, the microprocessor needs not to check the flag
before issuing a command. This can greatly improve the microprocessor performance.
Initial Display Line Register
When the display RAM data is read, the display line according to
COM0 (usually, the top line of screen) is determined using register
data. The register is also used for screen scrolling and page
switching.
The Set Display Start Line command sets the 5-bit display start
address in this register. The register data is preset on the line counter
each time FR signal status changes. The line counter is incremented
by oscillator circuit output (in master mode) or CL input (in slave
mode), and it generates a line address to allow 80-bit sequential data
output from display RAM to LCD driver circuit.
Column Address Counter
This is a 7-bit presettable counter that provides column address to the
display RAM (refer to Figure 4). It is incremented by 1 when a Read/
Write command is entered. However, the counter is not incremented
but locked if a non-existing address above 50H is specified. It is
D0
D1
D2
D3
D4
unlocked when a column address is set again. The Column Address
counter is independent of Page Address register.
When ADC Select command is issued to display inverse display, the
column address decoder inverts the relationship between RAM
column address and display segment output.
Page Address Register
This is a 4-bit page address register that provides page address to the
display RAM (refer to Figure 4). The microprocessor issues Set
Page Address command to change the page and access to another
page. Page address 4 (D2 is high, but D0 and D1 are low) is RAM
area dedicate to the indicator, and display data D0 is only valid.
Display Data RAM
The display data RAM stores pixel data for LCD. It is a 33-column
by 80-row (4-page by 8+1 bit) addressable array. Each pixel can be
selected when page and column addresses are specified.
The time required to transfer data is very short because the microprocessor enters D0 to D7 corresponding to LCD common lines as
shown in Figure 3. Therefore, multiple S1D15206’s can easily
configure a large display having the high flexibility with very few
data transmission restriction.
The microprocessor writes and reads data to/from the RAM through
I/O buffer. As LCD controller operates independently, data can be
written into RAM at the same time as data is being displayed,
without causing the LCD to flicker.
1
0
1
0
0
COM0
COM1
COM2
COM3
COM4
Display data RAM
Display on LCD
Figure 3
4–10
EPSON
Rev.3.5
S1D15206 Series
Relationship between display data RAM and addresses (if initial display line is 08):
Page
address
Line
address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Data
D0
D1
D2
D2,D1,D0
D3
=0,0,0
D4
D5
D6
D7
D0
D1
D2
D3
0,0,1
D4
D5
D6
D7
D0
D1
D2
D3
0,1,0
D4
D5
D6
D7
D0
D1
D2
D3
0,1,1
D4
D5
D6
D7
1,0,0
D0
Column A D0=0 00 01020304 0506 07
D
address C D0=1 4F 4E 4D 4C 4B 4A 49 48
SEGOUT 0 1 2 3 4 5 6 7
Page 0
Page 1
Page 2
Page 3
Page 4
Start
1/8
1/16
COM
output
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM S
4D 4E 4F
02 0100
77 7879
Figure 4
Display Timing Generator Circuit
This section explains how the display timing generator circuit
operates.
Signal generation to line counter and display data latch
circuit
The line address counter, RAM, and latch circuit of the S1D15206
series operate synchronous to the display clock (the oscillator circuit
outp).mm The LCD drive signal is sent to LCD panel driver output
pin SEGn.
Rev.3.5
The timing of LCD panel driver outputs is independent of the timing
of RAM data input from microprocessor.
LCD AC Signal (FR)
The LCD AC signal, FR, is generated from the display clock. The
FR controller generates dual-frame AC driver waveforms for LCD
panel driver circuit.
EPSON
4–11
S1D15206 Series
• Dual-frame AC driver waveforms
(If S1D15206 is used in 1/16 duty)
15
16
1
2
3
4
5
6
11
12
13
14
15
16
1
2
Display clock
FR
COM0
COM1
V DD
V1
V4
V5
V DD
V1
V4
V5
RAM data
SEGn
V DD
V2
V3
V5
Common timing Signals
The common timing generator circuit uses the display clock to
generate common timing signal and FR frame signal. The Duty
Select command can select 1/8 or 1/16 duty (S1D15206). A
combination of Select Duty and Duty+1 commands can select 1/9 or
1/17 duty (S1D15206).
Display Data Latch Circuit
Power Supply Circuit
This circuit temporarily stores (or latches) display data (during a
single common signal period) when it is output from display RAM
to LCD panel driver circuit. This latch is controlled by Display ON/
OFF and Static Drive ON/OFF commands. These commands do not
alter the data.
The power supply circuit produces voltage to drive LCD panel at low
power consumption. The power circuit consists of three subcircuits:
voltage tripler, voltage regulator, and voltage follower. The voltage
tripler outputs VDD -(VSS×2) or -(VSS×3) voltage at V OUT. The
regulator circuit generates V5 voltage using external resistor. The
voltage follower circuit changes the impedance of V1 to V4 that are
generated from V5 through division with internal resistors. (Details
are explained later.)
S1D15206 series can drive LCD panel using on-chip power circuit.
However, the on-chip power circuit is intended to use for a small
LCD panel and it is inappropriate to a large panel requiring multiple
driver chips. As the large LCD panel has the dropped display quality
due to large load capacity, it must use an external power source.
The power circuit is controlled by Set Power Control command.
This command sets a three-bit data in Power Control register to
select one of eight power circuit functions. The external power
supply and part of on-chip power circuit functions can be used
simultaneously. The following explains how the Set Power Control
command works.
LCD Driver
This is a multiplexer circuit consisting of 96 segment outputs to
generate four-level LCD panel drive signals. The circuit also has a
pair of COM outputs for indicator display.
The COMn output has a shift register to sequentially output COM
scan signals. The LCD panel drive voltage is generated by a specific
combination of display data, COM scan signal, and FR signal.
Figure 6 gives an example of SEG and COM output waveforms.
Oscillation Circuit
This is a low power consumption CR oscillator having an oscillator
resistor, and its output is used as the display timing signal source or
as the clock for voltage boost circuit of LCD power supply.
The display clock output can be stopped by Clock Stop command to
minimize the current consumption of LCD panel.
4–12
EPSON
Rev.3.5
S1D15206 Series
[Control by Set Power Control command]
D2 turns on when triple booster control bit goes HIGH, and D2 turns off when this bit goes LOW.
D1 turns on when voltage regulator control bit goes HIGH, and D1 turns off when this bit goes LOW.
D0 turns on when voltage follower control bit goes HIGH, and D0 turns off when this bit goes LOW.
[Practical combination examples]
D2 D1 D0
Voltage
booster
Voltage
regulator
Voltage
follower
External voltage Voltage booster Voltage regulator
input
terminal
terminal
1
1
1
ON
ON
ON
—
Used
Used
1
0
0
ON
OFF
OFF
—
Used
OPEN
0
1
1
OFF
ON
ON
To VOUT
OPEN
Used
0
0
0
OFF
OFF
OFF
To V1 to V5
OPEN
OPEN
Voltage tripler
To use the on-chip (internal) power supply only, set
(D2,D1,D0)=(1,1,1).
If capacitors C1 are inserted between CAP1+ and CAP1-, between
CAP2+ and CAP2–, and between VSS and VOUT , the potential
between VDD and VSS is boosted to triple toward negative side and
it is output at VOUT. For double boosting, remove only capacitor C1
between CAP2+ and CAP2-, open CAP2+, and jumper between
CAP2- and VOUT. The double boosted voltage appears at V OUT
(CAP2-).
To use the voltage booster circuit only, set (D2,D1,D0)=(1,0,0).
To use the voltage regulator and voltage follower, set
(D2,D1,D0)=(0,1,1).
To use an external power supply only, set (D2,D1,D0)=(0,0,0).
Notes: 1. The voltage booster terminals are CAP1+, CAP1-, CAP2+,
and CAP2-.
2. The above listed examples are the most practical use to
control each circuit using control bits. Any other setup is
unpractical and omitted in this manual.
3. The V/F circuit alone cannot be used. When this circuit
is used, the V adjustment circuit must be set simultaneously.
The booster receives signals from oscillator circuit and, therefore,
the oscillator must be active. The following shows the boosted
potential.
(VCC =+5V) VDD =0V
VDD =0V
(GND) VSS =-5V
VSS =-5V
VOUT =2VSS =-10V
VOUT =3VSS =-15V
Potential during double boosting
Rev.3.5
Potential during triple boosting
EPSON
4–13
S1D15206 Series
Voltage regulator
The boosting voltage occurring at VOUT is sent to the voltage regulator and the V5 liquid crystal display (LCD) drive voltage is output. This
V5 voltage can be determined by the following equation when resistors Ra and Rb (R1, R2 and R3) are adjusted within the range of |V5|<|VOUT|.
V DD
R1
Ra
V5=(1+ Rb) · VREG+IREF · Rb
Ra
=(1+ R3+R2–∆R2 ) · VREG
R1+∆R2
V REG
∆R2
R2
UR
Rb
Setup example of resistors R1, R2 and R3:
When the Electronic Volume Control Function is OFF (electronic
volume control register values are (D4,D3,D2,D1,D0)
=(0,0,0,0,0)):
R3 + R2 – ∆R2
V5 = (1 +
) · VREG ................. 1
R1 + ∆R2
(As IREF = 0A)
• R1 + R2 + R3 = 6.0 MΩ ............................ 2
(Determined by the current passing between VDD and V5)
• Variable voltage range by R2: –6.2 to –9.3 V
(Determined by the LCD characteristics)
∆R2 = 0Ω, VREG = –3.1 V
To obtain V5 = –9.3 V, from equation (1):
R2 + R3 = 2 · R1 ......................... 3
∆R2 = R2, VREG = –3.1 V
To obtain V5 = –6.2 V, from equation (1):
R1 + R2 = 1 · R1 ......................... 4
To use the Electronic Volume Control Function, issue the Set Power
Control command to simultaneously operate both the voltage
regulator circuit and voltage follower circuit.
Also, when the voltage tripler off, the voltage must be supplied from
VOUT terminal.
When the Electronic Volume Control Function is used, the V5
voltage can be expressed as follows:
V5 = (1 +
3
and
4
:
R1 = 2.0 MΩ
R2 = 1.0 MΩ
R3 = 3.0 MΩ
The voltage regulator circuit has a temperature gradient of
approximately –0.17%/°C as the VREG voltage. To obtain another
temperature gradient, use the Electronic Volume Control Function
for software processing using the MPU.
As the VR pin has a high input impedance, the shielded and short
lines must be protected from a noise interference.
When the VREG = Type 2, similarly preset R1, R2 and R3 on the basis
of VREG = VSS.
Voltage regulator circuit using the Electronic Volume
Control Function
The Electronic Volume Control Function can adjust the intensity
(brightness level) of liquid crystal display (LCD) screen by command
control of V5 LCD driver voltage.
This function sets five-bit data in the electronic volume control
register, and the V 5 LCD driver voltage can be one of 32-state
voltages.
4–14
Rb
) · V REG + IREF · Rb .................. 5
Ra
(Variable voltage range)
The increased V5 voltage is controlled by use of IREF current source
of the IC. (For 32 voltage levels, ∆IREF=IREF/31)
The minimum setup voltage of the V5 absolute value is determined
by the ratio of external Ra and Rb, and the increased voltage by the
Electronic Volume Control Function is determined by resistor Rb.
Therefore, the resistors must be set as follows:
(1) Determine Rb resistor depending on the V5 variable voltage
range by use of the Electronic Volume Control.
Rb =
V5 variable voltage range
IREF
(2) To obtain the minimum voltage of the V5 absolute value,
determine Ra using the Rb of Step (1) above.
Ra =
,
IREF
Voltage regulation
current
R3
where, V REG is the constant voltage source of the IC, and it is
constant (VREG .=. –3.1 V). (VREG =Type1) VREG=VSS(VDD basis)
(VREG=Type2)
IREF is the voltage regulation current of the Electronic Volume
Control Function, and IREF .=. 2.4 µA if the electronic volume control
register (32-state) has (D4,D3,D2,D1,D0)=(1,1,1,1,1).
To adjust the V5 output voltage, insert a variable resistor between
VR, VDD and V5 as shown. A combination of R1 and R3 constant
resistors and R2 variable resistor is recommended for fine-adjustment
of V5 voltage.
2
V5
-
+IREF · (R3+R2–∆R2)
From equations
+
Rb
V5
–1
VREG
[V5 = (1 + Rb/Ra) · VREG]
The S1D15206 series have the built-in VREG reference voltage and
IREF current source which are constant during voltage variation.
However, they may change due to the variation occurring in IC
manufacturing and due to the temperature change as shown below.
Consider such variation and temperature change, and set the Ra and
Rb appropriate to the LCD used.
VREG =–3.1V±0.4V (Type1)
VREG =–0.17%/˚C
VREG =VSS (VDD basis) (Type2)
VREG =–0.00%/˚C
IREF = –1.2 µA ± 40% (For 16 levels)
IREF = 0.011 µA/°C
IREF = –2.4 µA ± 40% (For 32 levels)
IREF = 0.022 µA/°C
Ra is a variable resistor that is used to correct the V5 voltage change
due to VREG and IREF variation. Also, the contrast adjustment is
recommended for each IC chip.
Before adjusting the LCD screen contrast, set the electronic volume
control register values to (D4,D3,D2,D1,D0)=(1,0,0,0,0) or
(0,1,1,1,1) first.
When not using the Electronic Volume Control Function, set the
register values to (D4,D3,D2,D1,D0)=(0,0,0,0,0) by sending the
RES signal or by issuing the Set Electronic Volume Control Register
command.
EPSON
Rev.3.5
S1D15206 Series
If Ta = 50°C:
V5 max = (1 + Rb/Ra) · VREG
= (1 + 1 MΩ/1 MΩ) × (–3.1 V) × {1 + (–0.17%/°C)
× (50°C – 25°C)}
= –5.94 V
V5 min = V5 max + Rb · IREF
= –5.94 V + 1MΩ × {–2.4 µA + (0.022 µA/°C) ×
(–50°C – 25°C)}
= –8.89 V
Setup example of constants when Electronic Volume Control
Function is used:
V5 maximum voltage: V5 = –6.2 V (Electronic volume control
register values (D4,D3,D2,D1,D0)=(0,0,0,0,0))
V5 minimum voltages: V5 = –8.6 V (Electronic volume control
register values (D4,D3,D2,D1,D0)=(1,1,1,1,1))
V5 variable voltage range: 2.4 V
Variable voltage levels: 32 levels
(1) Determining the Rb:
Rb =
V5 variable voltage range
2.4 V
=
2.4 µA
|IREF|
Rb = 1.0 MΩ
(2) Determining the Ra:
Ra =
Rb
1.0 MΩ
=
–6.2 V
V5 max
–1
–1
VREG
–3.1 V
Ra = 1.0 MΩ
According to the V5 voltage and temperature change, equation 5 can
be as follows (if VDD = 0 V reference):
If Ta = 25°C:
V5 max = (1 + Rb/Ra) · VREG
= (1 + 1 MΩ/1 MΩ) × (–3.1 V)
= –6.2 V
V5 min = V5 max + Rb · IREF
= –6.2 V + 1 MΩ × (–2.4 µA)
= –8.6 V
If Ta = –10°C:
V5 max = (1 + Rb/Ra) · VREG
= (1 + 1 MΩ/1MΩ) × (–3.1 V) × {1 + (–0.17%/°C)
× (–10°C – 25°C)}
= –6.57 V
V5 min = V5 max + Rb · IREF
= –6.57 V + 1MΩ × {–2.4 µA + (0.022 µA/°C) ×
(–10°C – 25°C)}
= –8.20 V
The margin must also be determined in the same procedure given
above by considering the VREG and IREF variation. This margin
calculation results show that the V5 center value is affected by the
VREG and IREF variation. The voltage setup width of the Electronic
Volume Control depends on the IREF variation. When the typical
value of 0.2 V/step is set, for example, the maximum variation range
of 0.12 to 0.28 V must be considered.
When the VREG = Type 2, it so becomes that VREG = VSS and there
is no temperature gradient. However, IREF carries the same
temperature characteristics as with VREG = Type 1.
Voltage generator for LCD (Voltage fullower)
The V5 potential is divided using resistance within IC and V1, V2, V3
and V4 potentials are generated for LCD panel drive. These
potentials are then converted in impedance by voltage follower, and
sent to LCD driver circuit.
Because the LCD drive voltage has been fixed to each model, the
display quality may drop in specific duty selected by Select Duty
command. If it occurs, use an external power supply.
Model
LCD drive voltage
S1D15206
S1D15208
1/5 of bias voltage
1/7 of bias voltage
Subsection gives wiring examples and reference parts list when onchip power supply is used and when not used.
Command sequence for built-in power circuit startup
The built-in power circuit must follow the command sequence given below.
• To start the built-in power
circuit after release of Power
Save mode:
• To start the built-in power
circuit when logic units are
being powered:
Hardware reset
(SR1=SR2='0')
Release the Power Save
mode. (Static drive is
OFF or display is ON.)
Setup of power
control
Setup of power
control
*After approx. 200 msec
*After approx. 200 msec
Display turns ON.
Display turns ON.
* When the Set Power Control command is issued, the V DD level signal is output at both COM and SEG terminals for approximately 200 msec.
Any other command can be entered during this period.
Rev.3.5
EPSON
4–15
S1D15206 Series
When turning off the built-in power circuit, observe the following command sequence to mainyain power save status.
When turning off the built-in
power supply:
Display “OFF”
Command AEh
Power save
command
Static drive “ON”
Command A5h
Built-in power supply “OFF”
* Precautions when installing the COG
When installing the COG, it is necessary to duly consider the fact that
there exists a resistance of the ITO wiring occurring between the
driver chip and the externally connected parts (such as capacitors and
resistors). By the influence of this resistance, non-conformity may
occur with the indications on the liquid crystal display.
Therefore, when installing the COG design the module paying
sufficient considerations to the following three points.
1. Suppress the resistance occurring between the driver chip pin to
the externally connected parts as much as possible.
2. Suppress the resistance connecting to the power supply pin of
the driver chip.
3. Make various COG module samples with different ITO sheet
resistance to select the module with the sheet resistance with
sufficient operation margin.
Also, as for this driver IC, pay sufficient attention to the following
points when connecting to external parts for the characteristics of the
circuit.
1. Connection to the boosting capacitors The boosting capacitors
(the capacitors connecting to respective CAP pins and capacitor
being inserted between VOUT and VSS2) of this IC are being
switched over by use of the transistor with very low ONresistance of about 10Ω. However, when installing the COG,
Exemplary connection diagram 1.
2.
the resistance of ITO wiring is being inserted in series with the
switching transistor, thus dominating the boosting ability.
Consequently, the boosting ability will be hindered as a result
and pay sufficient attention to the wiring to respective boosting
capacitors.
Connection of the smoothing capacitors for the liquid crystal
drive
The smoothing capacitors for the liquid crystal driving potentials
(V1. V2, V3 and V4) are indispensable for liquid crystal drives
not only for the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs pursuant to
installation of the COG is supplemented to these smoothing
capacitors, the liquid crystal driving potentials become unstable
to cause non-conformity with the indications of the liquid
crystal display. Therefore, when using the COG module, we
definitely recommend to connect reinforcing resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these reinforcing
resistors, current consumption will increase.
Indicated below is an exemplary connection diagram of external
resistors.
Please make sufficient evaluation work for the display statuses with
any connection tests.
Exemplary connection diagram 2.
VDD
VDD
VDD
R4
V1
V2
C2
V3
C2
V1
C2
R4
S1D15206 Series
C2
V2
C2
V3
C2
S1D15206 Series
R4
VDD
R4
V4
C2
C2
V4
R4 R4
C2
4–16
V5
C2
EPSON
V5
Rev.3.5
S1D15206 Series
Reset Circuit
11. Static drive
12. Clock
The S1D15206 series chip parameters are initialized when both
SR1 and SR2 are set to low.
As explained in Section 4-32, the microprocessor should also be
reset when SR1 and SR2 are reset. The SR1 and SR2 go low only
when logical low pulses are entered at least 10 microseconds (refer
to Section for AC characteristics). The normal reset signal appears
1 microsecond after the rising edge of this signal.
If the on-board LCD power circuit of the S1D15206 series is not
used, both SR1 and SR2 must be low when an external LCD power
is supplied. If not low, the IC chip may be destroyed by surge
current. When reset, each register is cleared but the present setup of
oscillator circuit and output terminals (FR, CL, D0 to D7) is not
cleared.
As the S1D15206 series does not have a Power-On Clear circuit,
both SR1 and SR2 must go low when logic power applies. If not, any
recovery may fail.
The Reset command can reset parameters 6 to 10 listed above.
● Initial parameter setup
1. Display
2. Duty cycle
3. ADC select
4.
5.
6.
7.
8.
9.
10.
: Off
: Output
: Off
: 1/16 (S1D15206)
: Normal (D0 ADC com
mand is high and
ADC status flag is set)
Read-modify-write
: Off
Power Control register
: 0
Initial Display Line register
: Line 1
Column Address counter
: Address 0
Page Address register
: Page 0
Register data of serial interface : Cleared
Electronic control register
: 0
0 1 2 3
16 0 1 2 3
16
0 1 2 3
32 0 1 2 3
32
COM 0
COM 1
FR
VDD
VSS
COM 0
VDD
V1
V2
V3
V4
V5
COM 1
VDD
V1
V2
V3
V4
V5
COM 2
VDD
V1
V2
V3
V4
V5
SEG 0
VDD
V1
V2
V3
V4
V5
SEG 1
VDD
V1
V2
V3
V4
V5
COM -SEG 0
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
COM -SEG 1
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM 10
COM 11
COM 12
COM 13
COM 14
COM 15
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
Figure 6
Rev.3.5
EPSON
4–17
S1D15206 Series
7. COMMANDS
A0
Page 4–21 lists available commands. The S1D15206 series uses a
combination of A0, RD and WR (or R/W) signals to identify data bus
signals. As the chip analyzes and executes each command using
internal timing clock only (any external clock is required), its
processing speed is very HIGH and its busy check is usually not
required.
(1) Display ON/OFF
Alternatively turns the display on and off.
A0
0
R/W
RD WR D7
1
0
1
D6
D5
F4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
D
D6
D5
F4
D3
D2
D1
D0
1
0
A4
A3
A2
A1
A0
←
A4
0
0
0
A3
0
0
0
1
1
1
1
A2
0
0
0
:
1
1
A1
0
0
1
A0
0
1
0
1
1
0
1
HIGH-order bit
Line address
0
1
2
:
30
31
0
A2
0
0
0
0
1
R/W
RD WR D7
1
0
A1
0
0
1
1
0
1
A0
0
1
0
1
0
D3
D2
D1
D0
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
A6
0
0
A5
0
0
A4
0
0
A3
0
0
A2
0
0
A1
0
0
A0
0
1
1
0
0
1
1
1
1
R/W
RD WR D7
D6
A0
0
Column address
0
1
:
79
0
1
D5
F4
D3
D2
D1
D0
BUSY ADC ON/OFF RESET
PS
0
0
0
BUSY:
When high, the S1D15206 series is busy due to internal
operation or reset. Any command is rejected until BUSY
goes LOW. The busy check is not required if enough time
is provided for each cycle.
ADC:
Indicates the relationship between RAM column address
and segment drivers. When LOW, the display is normal
and column address “79-n” corresponds to segment driver
n. When HIGH, the display is reversed and column
address n corresponds to segment driver n.
ON/OFF: Indicates whether the display is on or off. When goes low,
the display turns on. When goes HIGH, the display turns
off. This is the opposite of Display ON/OFF command.
PS:
A0
1
D6
D5
F4
D3
D2
D1
D0
0
1
1
1
A2
A1
A0
When LOW, LCD panel is in Power Save mode.
(6) Write Display Data
Writes 8-bit data in display RAM. As the column address is
incremented by 1 automatically after each write, the microprocessor can continue to write data of multiple words.
R/W
RD WR D7
1
D6
0
D5
F4
D3
D2
D1
D0
Write data
(7) Read Display Data
Reads 8-bit data from display RAM area specified by column
address and page address. As the column address is incremented
by 1 automatically after each write, the microprocessor can
continue to read data of multiple words. A single dummy read
is required immediately after column address setup. Refer to
the display RAM section of FUNCTIONAL DESCRIPTION
for details.
Page Address
0
1
2
3
4
A0
(4) Set Column Address
Specifies column address of display RAM. When the microprocessor repeats to access to the display RAM, the column
address counter is incremented by 1 during each access until
address 80 is accessed. The page address is not changed during
this time.
4–18
F4
RESET: Indicates the initialization is in progress by SR1 and
SR2 to go LOW or by Reset command. When LOW,
the display is on. When HIGH, the chip is being reset.
(3) Set Page Address
Specifies page address to load display RAM data to page
address register. Any RAM data bit can be accessed when its
page address and column address are specified. The display
remains unchanged even when the page address is changed.
Page address 4 is the display RAM area dedicate to the indicator, and only D0 is valid for data change.
A0
D5
(5) Read Status
(2) Initial Display Line
Specifies line address (refer to Figure 4) to determine the initial
display line, or COM0. The RAM display data becomes the top
line of LCD screen. It is followed by the higher number of lines
in ascending order, corresponding to the duty cycle. When this
command changes the line address, the smooth scrolling or
page change takes place.
R/W
RD WR D7
D6
:
The display turns off when D goes low, and it turns on when D
goes HIGH.
A0
R/W
RD WR D7
1
R/W
RD WR D7
0
1
D6
D5
F4
D3
D2
D1
D0
Read data
(8) ADC Select
Changes the relationship between RAM column address and
segment driver. The order of segment driver output pins can be
reversed by software. This allows flexible IC layout during
LCD module assembly. For details, refer to the column address
section of Figure 4. When display data is written or read, the
column address is incremented by 1 as shown in Figure 4.
EPSON
Rev.3.5
S1D15206 Series
A0
0
R/W
RD WR D7
1
0
1
D6
D5
F4
D3
D2
D1
D0
A0
0
1
0
0
0
0
D
0
R/W
RD WR D7
1
When D is low, the right rotation (normal direction). When
D is HIGH, the left rotation (reverse direction).
(9) Static Drive ON/OFF
Forcibly turns the entire display ON and makes all common
outputs selectable regardless of RAM data contents. The RAM
data is held.
A0
0
R/W
RD WR D7
1
0
1
D6
D5
F4
D3
D2
D1
D0
0
1
0
0
0
0
D
When D goes LOW, the static drive turns off. When D goes
HIGH, the static drive turns on.
The LCD panel enters Power Save mode if Static Drive ON
command is issued when the display is off. Refer to the Power
Save section for details.
(10) Select Duty
Selects the LCD driver duty. However, the bias of LCD driver
voltage is fixed when on-chip power circuit is used (refer to
Subsection).
A0
0
R/W
RD WR D7
1
0
1
0
1
D6
D5
F4
D3
D2
D1
D0
0
1
0
1
0
1
D
Model
D
Duty
S1D15206
0
1
0
1
1/8 or 1/16
1/9 or 1/17
1/32
1/33
S1D15208
(12) Read-Modify-Write
A pair of Read-Modify-Write and End commands must always
be used. Once Read-Modify-Write is issued, column address is
not incremented by Read Display Data command but
incremented by Write Display Data command only. It continues until End command is issued. When the End is issued,
column address returns to the address when Read-ModifyWrite was issued. This can reduce the microprocessor load
when data of a specific display area is repeatedly changed
during cursor blinking or others.
A0
0
R/W
RD WR D7
1
0
1
D6
D5
F4
D3
D2
D1
D0
1
1
0
0
0
0
0
D6
D5
F4
D3
D2
D1
D0
Note: Any command except Read/Write Display Data and Set
Column Address can be issued during Read-Modify-Write
mode.
0
1
0
1
0
0
D
• Cursor display sequence
Model
D
Duty
Set Page Address
S1D15206
0
1
0
1
1/8
1/16
1/32
1/32
Set Column Address
S1D15208
(11) Duty+1
Increments the duty by 1. If 1/8 duty is set for the S1D15206,
for example, it is incremented to 1/9 duty. If 1/16 duty is set, it
is incremented to 1/17 duty. The COMS terminal functions as
COM8 or COM16. The display line of RAM area corresponding to page address 4, or D0, is always accessed.
Read-Modify-Write
Dummy Read
Read Data
Write Data
No
Completed?
Yes
End
Rev.3.5
EPSON
4–19
S1D15206 Series
(13) End
Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write was issued).
A0
0
R/W
RD WR D7
1
0
1
D6
D5
F4
D3
D2
D1
D0
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
N+m
N
Read-Modify-Write mode is selected.
(14) Reset
Resets the Initial Display Line register, Column Address counter, Page Address register, register data of serial interface, and
Electronic Control register to their initial status. The Reset
command does not affect on the contents of display RAM.
Refer to the Reset circuit section of FUNCTIONAL DESCRIPTION.
A0
0
R/W
RD WR D7
1
0
1
D6
D5
F4
D3
D2
D1
D0
1
1
0
0
0
1
0
0
1
0
1
D6
D5
F4
D3
D2
D1
D0
0
1
1
0
D2
D1
D0
(16) Set Electronic Control
Adjusts the contrast of LCD panel display by changing V5 LCD
drive voltage that is output by voltage regulator of on-chip
power supply.
This command selects one of 32 V 5 LCD drive voltages by
storing data in 5-bit register. The V5 voltage adjusting range
should be determined depending on the external resistance.
Refer to the Voltage Regulator Circuit section of FUNCTIONAL DESCRIPTION for details.
This command is valid only when voltage regulator circuit is
turned on by Set Power Control command.
0
4–20
R/W
RD WR D7
1
0
1
1
1
1
D1
0
0
1
D0
0
1
0
0
1
1
1
0
1
| V5 |
Low
↓
High
A0
0
R/W
RD WR D7
1
0
1
D6
D5
F4
D3
D2
D1
D0
1
1
0
0
1
1
D
Clock outputs when D is low, but clock stops when D is high.
When D0 goes LOW, voltage follower turns off. When D0 goes
HIGH, it turns on.
When D1 goes LOW, voltage regulator turns off. When D1 goes
HIGH, it turns on.
When D2 goes LOW, voltage booster turns off. When D2 goes
HIGH, it turns on.
A0
1
1
1
D2
0
0
0
↓
1
1
1
(17) Clock Stop
Stops clock output at CL to reduce current consumption.
(15) Set Power Control
Selects one of eight power circuit functions using 3-bit register.
An external power supply and part of on-chip power supply
functions can be used simultaneously. Refer to Power Circuit
section of FUNCTIONAL DESCRIPTION for details.
A0
D3
0
0
0
Set register to (D4,D3,D2,D1,D0)=(0,0,0,0,0) to suppress electronic control function.
The Reset command cannot initialize LCD power supply. Only
RES (that sets SR1 and SR2 to low) can initialize the supplies.
R/W
RD WR D7
D4
0
0
0
End
D6
D5
F4
D3
D2
D1
D0
0
0
D4
D3
D2
D1
D0
(18) Power Save (a combination with Static Drive command)
Sets LCD panel in power save mode if Static Drive ON is issued
when the display is off. Power consumption drops power
consumption level.
When LCD panel enters Power Save mode:
(a) Both oscillator and power supply stop.
(b) LCD driver stops, and segment and common driver have
VDD level output.
(c) External clock input is disabled, and clock output is set
to low (at CL).
(d) Both display data and operation mode before issue of
Power Save are held.
(As the power control register is cleared, the Set Power
Control command must be issued again after the Power
Save mode has been released.)
(e) All LCD driver voltages are fixed to V DD.
The Power Save is released when the display is turned on or
when Static Drive OFF is issued. If external voltage driver
resistors are used to supply voltage to LCD panel, current
passing through resistors must be cut off. An external power
supply must be turned off if used; its voltage must be fixed to
floating or VDD level.
* When the S1D15206 series is operating, the internal status
data set by commands is held. However, the internal status
may change due to an excessive ambient noise. The package
and system noise generation must be suppressed or a noise
protection design must be considered.
We recommend to periodically refresh the internal status
data to prevent a spike noise and other interference.
EPSON
Rev.3.5
S1D15206 Series
S1D15206 Series Command Table
Command
A0
RD WR
D7
D6
Code
D5 D4
0
D3
D2
D1
D0
1
1
1
0
1
Function
(1) Display ON/OFF
0
1
0
1
0
1
(2) Initial Display Line
0
1
0
1
1
0
(3) Set Page Address
0
1
0
1
0
1
(4) Set Column Address
0
1
0
0
(5) Read Status
0
0
1
Status
(6) Write Display Data
1
1
0
Write data
Writes data in display RAM.
(7) Read Display Data
1
0
1
Read data
Reads data from display RAM.
(8) ADC Select
0
1
0
1
0
1
0
0
0
0
0
1
Sets normal relationship between
RAM column address and segment driver when low, but reverses the relationship when HIGH.
(9) Static Drive ON/OFF
0
1
0
1
0
1
0
0
1
0
0
1
Normal indication when LOW, but
full indication when HIGH.
(10) Duty Select
0
1
0
1
0
1
0
1
0
0
0
1
Selects LCD driver duty of 1/8 (1/
16) when LOW and 1/16 (1/32)
when HIGH.
(11) Duty+1
0
1
0
1
0
1
0
1
0
1
0
1
Selects normal LCD driver duty
when LOW, and selects the duty
added by 1 when HIGH.
(12) Read-Modify-Write
0
1
0
1
1
1
0
0
0
0
0
Increments Column Address
counter during each write when
HIGH and during each read when
LOW.
(13) End
0
1
0
1
1
1
0
1
1
1
0
Releases the Read-Modify-Write.
(14) Reset
0
1
0
1
1
1
0
0
0
1
0
Resets internal functions.
(15) Set Power Control
0
1
0
1
0
1
1
0
(16) Set Electronic Control
0
1
0
1
0
0
(17) Clock Stop
0
1
0
1
1
1
0
0
1
1
0
1
Stops clock output at CL when
LOW, and stops clock when HIGH.
(18) Power Save
–
–
–
–
–
–
–
–
–
–
–
A combination of Display OFF and
Static Drive ON commands.
Initial display address
1
1
Turns on LCD panel when goes
HIGH, and turns off when goes LOW.
Specifies RAM display line for
COM0.
Page address
Column address
Sets the display RAM page in
Page Address register.
Sets RAM column address in
Column register.
0
0
0
Power control
Electronic control value
Reads the status information.
Selects various power circuit
functions.
Sets V5 output voltage to Electronic Control register.
Note: Do not use any other command, or the system malfunction may result.
Rev.3.5
EPSON
4–21
S1D15206 Series
8. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Supply voltage range
VDD
–0.3 to +7.0
V
Triple voltage
conversion
Driver supply voltage range (1)
VDD
–0.3 to +6.0
V5
–18.0 to +0.3
V
V1, V2, V3, V4
V5 to +0.3
V
Input voltage range
VIN
–0.3 to VDD+0.3
V
Output voltage range
VO
–0.3 to VDD+0.3
V
Allowable loss
PD
250
mW
Operating temperature range
TOPR
–40 to +85
°C
Storage temperature range QFP • TCP
TSTG
–65 to +150
°C
Driver supply voltage range (2)
Bear chip
–55 to +125
Soldering temperature and time
TSOLDER
260-10 (at leads)
VCC
°C•sec
VDD
GND
V SS
V1 to V5, VOUT, VREG
(Microprocessor side)
(S1D15206 series side)
Notes: 1. V1 to V5, VOUT, and VREG voltages are based on VDD=0 V.
2. Voltages VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 VSS ≥ VOUT must always be satisfied.
3. If an LSI exceeds its absolute maximum rating, it may be damaged permanently. It is desirable to use it under electrical characteristics
conditions during general operation. Otherwise, an LSI malfunction or reduced LSI reliability may result.
4. The moisture resistance of the flat package may drop during soldering. Take care not to excessively heat the package resin during
chip mounting.
4–22
EPSON
Rev.3.5
S1D15206 Series
9. ELECTRICAL CHARACTERISTICS
DC Characteristics
VDD = 5 V ±10%, VSS = 0 V, Ta = –40 to +85°C unless otherwise noted.
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Pin used
Power voltage (1)
Operational
VDD
2.4
6.0
V
Operating voltage
Operational
V5
–13.0
–4.0
V
V5
(2)
Operational
V1, V2
0.6 × V5
VDD
V
V1, V2
Operational
V3, V4
V5
0.4 × V5
V
V3, V4
VIHC
0.7 × VDD
VDD
V
*3
0.8 × VDD
VDD
VSS
0.3 × VDD
V
*3
VDD = 2.7 V
VSS
0.2 × VDD
IOH = –1 mA
0.8 × VDD
VDD
V
*4
VDD = 2.7 V, IOH = –0.5 mA
0.8 × VDD
VDD
IOH = 1 mA
VSS
0.2 × VDD
V
*4
VDD = 2.7 V, IOL = 0.5 mA
VSS
0.2 × VDD
0.4 × VDD
0.8 × VDD
V
*5
0.4 × VDD
0.8 × VDD
0.2 × VDD
0.6 × VDD
V
*5
0.2 × VDD
0.6 × VDD
*6
HIGH-level input voltage
VDD = 2.7 V
CMOS
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Schmitt
HIGH-level input voltage
VILC
VOHC
VOLC
VIHS
VDD = 2.7 V
LOW-level input voltage
VILS
VDD = 2.7 V
VDD *1
*2
Input leakage current
ILI
–1.0
1.0
µA
Output leakage current
ILO
–3.0
3.0
µA
*7
15.0
30.0
KΩ
SEG0 to 79
COS0 to 15
COMS *9
CS = CL = VDD
0.05
3.0
µA
VDD
CIN
Ta = 25°C, f = 1 MHz
5.0
8.0
pF
Input pins
fCL
Ta = 25°C, VDD = 2.7 to 5 V
2.4
2.9
3.7
kHz
4.8
5.8
7.4
*8
Applies to the
S1D15206*10**,
S1D15208*10**
Dynamic current consumption (1) when the built-in power supply is OFF
1.7 times of normal products apply to fCL = 5.8 kHz products of S1D15206F11** and S1D15208F11** .
Ta = 25°C
LCD driver ON resistance
RON
Ta = 25°C
Static current consumption
IDDQ
Input pin capacity
CL output frequency
V5 = –0.5 V
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Remarks
S1D15206
IDD (1)
VDD = 5.0V, V5–VDD = –6.0V
–
9.1
18
µA
*12
VDD = 3.0V, V5–VDD = –6.0V
–
12.0
24
VDD = 5.0V, V5–VDD = –8.0V
–
7.5
15
VDD = 3.0V, V5–VDD = –8.0V
–
9.5
19
S1D15208
Rev.3.5
EPSON
4–23
S1D15206 Series
Dynamic current consumption (2) when the built-in power supply is ON (Display all white)
1.7 times of normal products apply to fCL = 5.8 kHz products of S1D15206F11** and S1D15208F11**.
Ta = 25°C
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Remarks
S1D15206
IDD (2)
VDD = 5.0V, V5–VDD = –6.0V, dual boosting
–
31
62
µA
*13
VDD = 3.0V, V5–VDD = –6.0V, triple boosting
–
44
88
VDD = 5.0V, V5–VDD = –8.0V, dual boosting
–
37
74
VDD = 3.0V, V5–VDD = –8.0V, triple boosting
–
55
110
S1D15208
Dynamic current consumption (2) when the built-in power supply is ON (Display checker pattern)
1.7 times of normal products apply to fCL = 5.8 kHz products of S1D15206F11** and S1D15208F11**.
Item
Symbol
S1D15206
IDD (2)
S1D15208
Conditions
Min.
Typ.
Ta = 25°C
Max.
Unit
Remarks
µA
*13
VDD = 5.0V, V5–VDD = –6.0V, dual boosting
–
34
68
VDD = 3.0V, V5–VDD = –6.0V, triple boosting
–
46
92
VDD = 5.0V, V5–VDD = –8.0V, dual boosting
–
42
84
VDD = 3.0V, V5–VDD = –8.0V, triple boosting
–
60
120
Current consumption during Power Save mode VSS = 0 V, VDD = 2.7 to 5.5 V
Item
Symbol
Power save
mode
IDDS1
Conditions
Ta = 25°C
Min.
Typ.
Max.
Unit
Remarks
—
3
6
µA
—
S1D15206, S1D15208
Typical current consumption characteristics (reference data)
• Dynamic current consumption (1) when LCD external power mode lamp is ON
20
Conditions: The built-in power supply is
(µA)
15
S1D15208
I DD (1)
10
Remarks:
S1D15206
5
0
1
2
3
VDD
4
5
6
7
OFF and an external power
supply is used.
S1D15206 V5-VDD=–6.0V
S1D15208 V5-VDD=–8.0V
Ta=25°C
*12
1.7 times of normal products apply
to fCL = 5.8 kHz products of
S1D15206F11** and S1D15208F11**.
(V)
• Dynamic current consumption (2) when the LCD built-in power supply lamp is ON
80
Conditions: The built-in power supply is ON.
(µA)
S1D15206 V5-VDD=–6.0V dual boosting
S1D15208 V5-VDD=–8.0V triple boosting
Ta=25°C
60
S1D15208
IDD (2)
Remarks:
40
S1D15206
*13
1.7 times of normal products apply
to fCL = 5.8 kHz products of
S1D15206F11** and S1D15208F11**.
20
0
4–24
1
2
3
VDD
4
5
6
7
EPSON
(V)
Rev.3.5
S1D15206 Series
• Current consumption I
DD
during access (2) during MPU access cycle
It shows the current consumption when a checker
pattern is always written in fSYNC timing.
When not accessed, only the current consumption
of IDD (2) occurs.
10
(mA)
S1D15206
1
IDD(2)
Conditions: S1D15206 V5 – VDD = –6.0 V, dual boosting
S1D15208 V5 – VDD = –8.0 V, triple boosting
Ta = 25°C
S1D15208
0.1
0.01
0
0.01
f CYC
Item
0.1
1
(MHz)
10
Built-in power circuit
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input voltage
VDD
—
2.4
—
6.0
V
Booster output voltage
VOUT
VDD reference (during triple boosting)
–16.5
—
—
V
VOUT
Voltage regulator circuit
operating voltage
VOUT
VDD reference
–16.5
—
–4.0
V
VOUT
V5
VDD reference
–13.0
—
–4.0
V
VDD reference Ta = 25°C
–3.5
–3.1
–2.7
V
Voltage follower operating
voltage
Reference voltage
VREG
Pins used
*10
*11
VR
* See notes below.
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
*11
*12
*13
Although the wide range of operating voltage is guaranteed, a spike voltage change during access to the MPU is not guaranteed.
The operating voltage range of the VDD and V5 systems (See Figure 9.)
The operating voltage range is applied if an external power supply is used.
Pins D0 to D5, A0, CS1, CS2, RD (E), WR (R/W), M/S, CL, and FR
Pins D0 to D7, FR, and CL
Pins SI (D7), SCL (D6), SR1, and SR2
Pins A0, RD (E), WR (R/W), CS1, CS2, M/S, SR1, and SR2
Applied if pins D0 to D7, FR, and CL are high impedance.
For the relationship between CL output frequency and frames, see Figure 7.
For the relationship between CL output frequency and power voltage, see Figure 8.
For the relationship between CL output frequency and temperature, see Figure 11.
The resistance when the 0.1-volt voltage is applied between the SEG and COM output terminals and each power terminal (V 1, V2, V3 or
V4). It must be within operating voltage (2).
RON = 0.1 V/∆I
where, ∆I is the current that flows between power supply and SEG or COM terminal when the 0.1-volt voltage is applied.
If the triple voltage by the built-in power circuit are used the VDD primary power must be used within the input voltage range.
The V5 voltage can be adjusted within the voltage follower operating range by use of voltage regulator.
Applied if the built-in oscillation circuit is used and if not accessed by the MPU.
Applied if the built-in oscillation circuit and the built-in power circuit are used, and if not accessed by the MPU.
The current flowing through the voltage regulator resistors (R1, R2 and R3) is not included.
When the built-in voltage booster is used, the current consumption for the V DD power supply is shown.
• Relationship between CL output frequency and frames
(S1D15206 series)
The relationship between CL output frequency (fCL) and frame
frequency (f F) can be determined as follows:
• Relationship between CL output frequency and power
voltage
6
Duty
fF
5
S1D15206
1/9
1/17
8 • F OSC/288
8 • fOSC/272
4
S1D15208
1/33
8
fCL
[KHz]
• fOSC/264
Ta=25°C
fCL=5.80
Applies to the
S1D15206 11 ,
* **
S1D15208 11
* **
3
fCL=2.90
2
Figure 7
1
("f F" indicates the LCD current alternating cycle, but not the
cycle of f F signals.)
0
2
4
6
8
VDD [V]
Figure 8
Rev.3.5
EPSON
4–25
S1D15206 Series
• Operating voltage range on VDD and V5
-20
-15
-13
[V]
V5
-10
-7.2
-5
-4
2 2.4
VDD
0
6
4
8
[V]
• IDD measuring circuits
A
A
VDD
VDD
V1
V1
0V
-5V
V2
0V
-5V
V2
S1D152∗∗∗∗∗∗∗
S1D152∗∗∗∗∗∗∗
V3
V3
0V
V4
V4
-2.7V
V5
V5
VSS
VSS
• Relationship between CL output frequency and temperature
7
6
Applies to the
S1D15206*11**,
S1D15208 11
* **
5
4
fCL
[KHz]
3
2
1
-40
4–26
0
40
Ta [˚C]
80
120
EPSON
Rev.3.5
S1D15206 Series
AC Characteristics
(1) System buses
Read/write characteristics I (8080-series microprocessor)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
tCCLW
tCCLR
WR,RD
tDS8
tDH8
tCCHW
tCCHR
D0~D7
(WRITE)
tACC8
tCH8
D0~D7
(READ)
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Address hold time
Address setup time
Signal
Symbol
A0
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tCH8
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
Data setup time
Data hold time
RD access time
Output disable time
D0 to D7
Condition
Min.
Max.
Unit
5
5
ns
ns
400
ns
100
75
145
145
80
10
CL=100pF
10
ns
ns
80
60
ns
ns
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Address hold time
Address setup time
Signal
Symbol
A0
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tCH8
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
Data setup time
Data hold time
RD access time
Output disable time
D0 to D7
Condition
Min.
Max.
Unit
10
10
ns
ns
800
ns
185
185
285
285
ns
ns
160
20
ns
ns
CL=100pF
20
180
120
ns
ns
Notes: 1. tCCLW and tCCLR are limited depending on the overlap time of CS1 LOW (CS2 HIGH) and WR or RD LOW.
2. The input signal rise and fall times must be within 15 nanoseconds.
3. All signal timings are limited based on 20% and 80% of VDD voltage.
Rev.3.5
EPSON
4–27
S1D15206 Series
(2) System buses
Read/write characteristics II (6800-series microprocessor)
A0
tAH6
tAW6
CS1
(CS2="1")
tCYC6
tEWLW
tEWLR
RD (E)
tEWHW
tEWHR
WR (R/W)
tDH6
tDS6
D0~D7
(WR1TE)
tACC6
tOH6
D0~D7
(READ)
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
WR (R/W)
A0
D0 to D7
Output disable time
Access time
Enable
READ
RD (E)
LOW pulse width WRITE
Enable
READ
RD (E)
HIGH pulse width WRITE
Symbol
Condition
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
tEWLR
tEWLW
tEWHR
tEWHW
CL=100pF
Symbol
Condition
Min.
Max.
Unit
400
ns
20
10
ns
ns
80
10
ns
ns
10
60
90
ns
ns
85
ns
75
ns
135
ns
145
ns
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Signal
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
WR (R/W)
A0
D0 to D7
Output disable time
Access time
Enable
READ
RD (E)
LOW pulse width WRITE
Enable
READ
HIGH pulse width WRITE
RD (E)
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
tEWLR
tEWLW
tEWHR
tEWHW
CL=100pF
Min.
Max.
Unit
800
ns
40
20
ns
ns
160
20
ns
ns
20
120
180
ns
ns
185
ns
145
ns
285
ns
325
ns
Notes: 1. t EWHR and tEWHW are limited depending on the overlap time of CS1 LOW (CS2 high) and RD (E) HIGH.
2. The input signal rise and fall times must be within 15 nanoseconds.
3. All signal timings are limited based on 20% and 80% of VDD voltage.
4–28
EPSON
Rev.3.5
S1D15206 Series
(3) Serial interface
tCSS
CS1
(CS2="1")
tCSH
tSAS
tSAH
A0
tSCYC
tSLW
Serial clock (D6)
tSHW
tSDS
Serial data (D7)
D1 data
tSDH
D0 data
D7 data
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Address setup time
Address hold time
Signal
Symbol
Serial clock
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
A0
Data setup time
Data hold time
Serial data
CS serial clock time
CS1
(CS2="1")
Condition
Min.
Max.
Unit
500
150
150
ns
ns
ns
120
200
ns
ns
120
120
ns
ns
80
400
ns
ns
VSS = 0 V, VDD = 2.7 to 4.5V, Ta = –40 to +85°C
Parameter
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Address setup time
Address hold time
Signal
Symbol
Serial clock
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
A0
Data setup time
Data hold time
Serial data
CS serial clock time
CS1
(CS2="1")
Condition
Min.
Max.
Unit
1000
300
300
ns
ns
ns
250
400
ns
ns
250
250
ns
ns
160
800
ns
ns
Notes: 1. The input signal rise and fall times must be within 15 nanoseconds.
2. All signal timings are limited based on 20% and 80% of VDD voltage.
Rev.3.5
EPSON
4–29
S1D15206 Series
(4) Display control timing
t WHCL
CL
tf
t WLCL
tDFR
tr
FR
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
LOW level pulse width
Signal
Symbol
CL
tWLCL
35
µs
tWHCL
35
µs
HIGH level pulse width
Condition
Min.
Typ.
Max.
Unit
Rise time
tr
30
120
ns
Fall time
tf
30
120
ns
0.2
1.0
µs
FR delay time
FR
tDFR
–1.0
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
LOW level pulse width
Signal
Symbol
CL
tWLCL
70
µs
tWHCL
70
µs
HIGH level pulse width
Condition
Min.
Typ.
Max.
Unit
Rise time
tr
60
240
ns
Fall time
tf
60
240
ns
0.4
2.0
µs
FR delay time
FR
tDFR
–2.0
VSS = 0 V, VDD = 5.0 V ±10%,Ta = –40 to +85°C
Output timing
Parameter
FR delay time
Signal
Symbol
Condition
FR
tDFR
CL=100pF
Min.
Typ.
Max.
Unit
0.2
0.4
µs
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
FR delay time
Signal
Symbol
Condition
FR
tDFR
CL=100pF
Min.
Typ.
Max.
Unit
0.4
0.8
µs
Notes: 1. All signal timings are limited based on 20% and 80% of V DD voltage.
4–30
EPSON
Rev.3.5
S1D15206 Series
(5) Reset timing
t RW
Reset input
(SR1 and SR2
are LOW.)
tR
Internal circuit
status
During reset
End of reset
VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
Reset time
Reset LOW pulse width
Reset input
Symbol
Condition
Min.
Typ.
Max.
Unit
tR
1.0
µs
tRW
10
µs
VDD = 2.7 V ±10%, Ta = –40 to +85°C
Parameter
Signal
Reset time
Reset LOW pulse width
Reset input
Symbol
Condition
Min.
Typ.
Max.
Unit
tR
3.0
µs
tRW
30
µs
tR (reset time) represents the period from rising edge of reset input to end of internal circuit reset. The S1D15206 series can
operate normally after t R.
2. tRW specifies the minimum pulse width of reset input. The low pulse exceeding tRW is required for reset.
3. The input signal rise and fall times must be within 15 nanoseconds.
4. All signal timings are limited based on 20% and 80% of VDD voltage.
Notes: 1.
Rev.3.5
EPSON
4–31
S1D15206 Series
10. EXTERNAL WIRINGS
Power Supply and LCD Power Circuit
If a single S1D15206 series chip is used and if on-board power supply is used and not used
If on-chip power supply is used
If on-chip power supply is NOT used
VDD
VDD
M/S
M/S
VOUT
CAP1+
CAP1 CAP2+
CAP2 VSS
C1
C1
C1
VOUT
CAP1+
CAP1 CAP2+
CAP2 VSS
S1D152*******
S1D152*******
VDD
V1
V2
V3
V4
V5
VR
C2
R1
R2
External
power
supply
VDD
V1
V2
V3
V4
V5
VR
R3
Parts list (Reference)
Variable V5 .=. –9.3 to –6.2 V
C1
0.1 to 1 µF
C2
0.1 to 1 µF
R1
2.0 MΩ
R1
1.0 MΩ
R1
3.0 MΩ
S1D1520 D
VDD, V0 * ****
R4
R4
V1
V2
V3
V4
R4
V5
4–32
Setting value for your reference: 100 kΩ to 1 MΩ.
In order to select an optimum value for resistor R4, you should
reference the LCD and the drive waveform.
C2
R4
Note: Use jumper and shielded wires
as the input impedance of VR
terminal is high.
Notes: 1. Because of high input impedance on VR terminal,
wiring should made as short as possible and shielded
wire should be used for the wiring.
2. C1 and C2 depend on size of the liquid crystal panel
to be driven. The value to be selected for C1 and C2
must be able to stabilize the liquid crystal drive
voltage.
[A setting example]
Turn on the voltage regulator circuit and the voltage
follower circuit to apply voltage to VOUT externally.
Display the LCD heavy load patterns (horizontal
stripe-shaped), then select the C2 value that can
stabilize the liquid crystal drive voltages (V 1 to V5).
All C2 capacity values selected, however, must be
the same. Then, turn on every built-in power
supplies and select an appropriate C1 value.
3. In order to regulate the voltage, a capacitor must be
connected between VDD and VSS (near to the IC).
EPSON
Rev.3.5
S1D15206 Series
Microprocessor Interface
The S1D15206 series chips can directly connect to 8080 and 6800-series microprocessors. Also, serial interfacing requires less signal lines
between them.
8080-series microprocessors
Wiring example 1:
VCC
A0
A1 to A7
IORQ
A0
VDD
SR2
CS2
Decoder
CS1
MPU
D0 to D7
RD
WR
RES
GND
S1D15206
D0 to D7
RD
WR
SR1
VSS
RESET
Wiring example 2:
VCC
A0
A1 to A7
IORQ
A0
VDD
SR2
CS2
Decoder
CS1
MPU
D0 to D7
RD
WR
RES
GND
S1D15206
D0 to D7
RD
WR
SR1
VSS
RESET
Rev.3.5
EPSON
4–33
S1D15206 Series
6800-series microprocessors
Wiring example 1:
VCC
A0
A1 to A15
VMA
VDD
A0
SR2
CS2
Decoder
CS1
MPU
D0 to D7
E
R/W
RES
GND
S1D15206
D0 to D7
RD (E)
WR (R/W)
SR1
VSS
RESET
Wiring example 2:
VCC
A0
A1 to A15
VMA
A0
VDD
SR2
CS2
Decoder
CS1
MPU
D0 to D7
E
R/W
RES
GND
S1D15206
D0 to D7
RD (E)
WR (R/W)
SR1
VSS
RESET
4–34
EPSON
Rev.3.5
S1D15206 Series
Serial interface
Wiring example 1:
VCC
SR2
CS1
CS2
RD
S1D15206
WR
SI (D7)
SCL (D6)
SR1
Port 2
MPU
Port 3
Port 4
GND
VDD
A0
Port 1
RES
VSS
RESET
Wiring example 2:
VCC
A0
Port 1
SR2
CS1
CS2
RD
S1D15206
WR
SI (D7)
SCL (D6)
SR1
Port 2
MPU
Port 3
Port 4
GND
VDD
RES
VSS
RESET
Rev.3.5
EPSON
4–35
S1D15206 Series
LCD Panel and Wiring Examples
Single-chip configuration
S1D15206 : 80×17dot
S1D15208 : 64×33dot
SEG
SEG
80
64
S1D15206
4–36
S1D15208
COM
COM
COM
17
17
16
EPSON
Rev.3.5
S1D15206 Series
11. DIMENSIONS
Plastic 128-Pin QFP5 Package
23.6 ± 0.4
20.0 ± 0.1
102
65
103
Index
128
39
38
2.7 ± 0.1
1
0.15 ± 0.05
17.6 ± 0.4
14.0 ± 0.01
64
0.2 ± 0.1
0.5
1.8
0.8 ± 0.2
The package dimensions are subject to change without notice.
Rev.3.5
EPSON
4–37
4–38
EPSON
(Mold area)
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 35µm
• Sn plating
• Product pitch: 91P (42.75mm)
• Solder resist positional tolerance: ±0.3
(Mold area)
(Marking area)
IC center
Output terminal pattern shape
S1D15206 Series
TPC shape S1D15206T00A* (Reference drawing)
This dimensional outline drawing is subject to change for improvements without prior notice
Rev.3.5
(Marking area)
5. S1D15300 Series
Rev. 1.4
Contents
1. DESCRIPTION ................................................................................................................................................ 5-1
2. FEATURES ...................................................................................................................................................... 5-1
3. BLOCK DIAGRAM (S1D15300D00B*) ........................................................................................................... 5-2
4. PAD LAYOUT .................................................................................................................................................. 5-3
5. PIN DESCRIPTION ......................................................................................................................................... 5-5
6. FUNCTIONAL DESCRIPTION ........................................................................................................................ 5-8
7. COMMANDS .................................................................................................................................................5-19
8. COMMAND SETTING (For Refrence) ...........................................................................................................5-24
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 5-27
10. ELECTRICAL CHARACTERISTICS ..............................................................................................................5-28
11. MPU INTERFACE (For Reference) ............................................................................................................... 5-36
12. CONNECTION BETWEEN LCD DRIVERS ...................................................................................................5-37
–i–
Rev. 1.4
S1D15300 Series
1. DESCRIPTION
The S1D15300 series is a single-chip LCD driver for dot-matrix
liquid crystal displays (LCD’s) which is directly connectable to a
microcomputer bus. It accepts 8-bit serial or parallel display data
directly sent from a microcomputer and stores it in an on-chip
display RAM. It generates an LCD drive signal independent of
microprocessor clock.
The use of the on-chip display RAM of 65 × 132 bits and a one-toone correspondence between LCD panel pixel dots and on-chip
RAM bits permits implementation of displays with a high degree of
freedom.
As a total of 133 circuits of common and segment outputs are
incorporated, a single chip of S1D15300 can make 33 × 100-dot (16
× 16-dot kanji font: 6 columns × 2 lines) displays, and a single chip
of S1D15301 can make 65 × 132-dot (kanji font: 8 columns x 4 lines)
displays when the S1D15301 is combined with the common driver
S1D16700.
The S1D15302 can display the 65 × 200-dot (or 12-column by 4-line
Kanji font) area using two ICs in master and slave modes. As an
independent static indicator display is provided for time-division
driving, the low-power display is realized during system standby
and others.
No external operation clock is required for RAM read/write opera-
tions. Accordingly, this driver can be operated with a minimum
current consumption and its on-board low-current-consumption
liquid crystal power supply can implement a high-performance
handy display system with a minimum current consumption and a
smallest LSI configuration.
Two types of S1D15300 series are available: one in which common
outputs are arranged on a single side and the other in which common
outputs are arranged on both sides.
2. FEATURES
• Direct RAM data display using the display RAM. When
RAM data bit is 0, it is not displayed. When RAM data bit
is 1, it is displayed. (At normal display)
• RAM capacity: 65 × 132 = 8580 bits
• High-speed 8-bit microprocessor interface allowing direct
connection to both the 8080 and 6800.
• Serial interface
• Many command functions: Read/Write Display Data, Display ON/OFF, Normal/Reverse Display, Page Address Set,
Set Display Start Line, Set Column Address, Read Status,
All Display ON/OFF, Set LCD Bias, Electronic contrast
Controls, Read Modify Write, Select Segment Driver Direction, Power Save
• Series specifications (in cases of chip shipments)
Type 1 [VREG (Built-in power supply regulating voltage)
Temperature gradient: -0.2% / °C]
Name
Duty
LCD bias
Segment driver
COM driver
Display area
Remarks
S1D15300D00✽✽
1/33
1/5, 1/6
100
33
33 × 100
COM single-side layout
S1D15300D10✽✽
1/33
1/5, 1/6
100
33
33 × 100
COM dual-side layout
S1D15301D00✽✽
1/65
1/6, 1/8
132
0
65 × 132
S1D16700 is used as the COM.
S1D15302D00✽✽
1/65
1/6, 1/8
100
33
65 × 200
COM single-side, right-hand layout
S1D15302D11✽✽
1/65
1/6, 1/8
100
33
65 × 200
COM single-side, left-hand layout
S1D15305D10✽✽
1/35
1/5, 1/6
98
35
35 × 98
COM both-side layout
Type 2 [VREG Temperature gradient: 0.00% / °C]
Name
Duty
LCD bias
Segment driver
COM driver
Display area
Remarks
S1D15300D15✽✽
1/33
1/5, 1/6
100
33
33 × 100
COM both-side layout
S1D15302D14✽✽
1/65
1/6, 1/8
100
33
65 × 200
COM single-side, right-hand layout
S1D15303D15✽✽
1/17
1/5
116
17
17 × 116
COM both-side layout
S1D15304D14✽✽
1/9
1/5
124
9
9 × 124
COM single-side layout
Note: The S1D15300 series has the following subcodes depending on their shapes. (The S1D15300 examples are given.)
S1D15300T**** : TCP (The TCP subcode differs from the inherent chip subcode.)
S1D15300D**** : Bear chips
S1D15300D**A* : Al-pad chip
S1D15300D**B* : Au-bump chip
• On-chip LCD power circuit: Voltage booster, voltage
regulator, voltage follower × 4.
• On-chip electronic contrast control functions
• Ultra low power consumption
• Power supply voltages: VDD - VSS -2.4 V to -6.0 V
VDD - V5 -4.5 V to -16.0 V
Rev.1.4
EPSON
• Wide operating temperature range:
Ta = -40 to 85°C
• CMOS process
• Package: TCP and bare chip
• Non-radiation-resistant design
5–1
S1D15300 Series
3. BLOCK DIAGRAM (S1D15300D00B*)
O0
O99 O100
O15 COMS
···············································
·····················
VSS
V3
V5
VDD
COM S
V1
V2
Segment driver
V4
Common driver
Shift register
CAP1+
CAP1–
CAP2+
Display data latch
Power supply
circuit
CAP2–
132 x 65-dot
display data RAM
Initial display line register
Output
status
selector
circuit
Line counter
VR
Line address decoder
VOUT
I/O buffer circuit
CAP3–
Column address decoder
Page address
register
8-bit column address counter
Display timing
generator circuit
8-bit column address register
Bus holder
Command decoder
Status
register
Microprocessor interface
CS1 CS2
5–2
A0
Oscillator
FRS
FR
CL
DYO
DOF
M//S
VS1
I/O buffer
RD WR C86 P/S RES
(E) (R/W)
EPSON
D7 D6
D5
(SI) (SCL)
D4
D3
D2
D1
D0
Rev.1.4
S1D15300 Series
4. PAD LAYOUT
S1D15300 series chips
51
1
52
172
Die No.
86
138
87
Rev.1.4
137
Chip Size:
Pad Pitch:
6.65x4.57 mm
118 µm (Min.)
S1D1530*D**A*
Pad Center Size:
Chip Thickness:
(Al-pad chip)
90x90 µm
300 µm
S1D1530*D**B*
Bump Size:
Bump Height:
Chip Thickness:
(Al-bump chip)
76x76 µm
23µm (Typ.)
625 µm
EPSON
5–3
S1D15300 Series
Pad Center Coordinates
Unit: µm
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
5–4
PIN
Name
O127
O128
O129
O130
O131
COMS
FRS
FR
DYO
CL
DOF
VS1
M/S
RES
P/S
CS1
CS2
C86
A0
WR(W/R)
RD(E)
VDD
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
VSS
VOUT
CAP3CAP1+
CAP1CAP2+
CAP2V5
VR
VDD
V1
V2
V3
V4
V5
O0
O1
O2
O3
O4
X
2986
2862
2738
2614
2490
2366
2242
2124
2006
1888
1770
1652
1534
1416
1298
1180
1062
944
826
708
590
472
354
236
118
0
-118
-236
-354
-472
-590
-708
-826
-944
-1062
-1180
-1298
-1416
-1534
-1652
-1770
-1888
-2006
-2124
-2242
-2366
-2490
-2614
-2738
-2862
Y
2142
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN
Name
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
O21
O22
O23
O24
O25
O26
O27
O28
O29
O30
O31
O32
O33
O34
O35
O36
O37
O38
O39
O40
O41
O42
O43
O44
O45
O46
O47
O48
O49
O50
O51
O52
O53
O54
X
-2986
-3178
Y
2142
2006
1888
1770
1652
1534
1416
1298
1180
1062
944
826
708
590
472
354
236
118
0
-118
-236
-354
-472
-590
-708
-826
-944
-1062
-1180
-1298
-1416
-1534
-1652
-1770
-1888
-2006
-2986 -2142
-2862
-2738
-2614
-2490
-2366
-2242
-2124
-2006
-1888
-1770
-1652
-1534
-1416
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
EPSON
PIN
Name
O55
O56
O57
O58
O59
O60
O61
O62
O63
O64
O65
O66
O67
O68
O69
O70
O71
O72
O73
O74
O75
O76
O77
O78
O79
O80
O81
O82
O83
O84
O85
O86
O87
O88
O89
O90
O91
O92
O93
O94
O95
O96
O97
O98
O99
O100
O101
O102
O103
O104
X
Y
-1298 -2142
-1180
-1062
-944
-826
-708
-590
-472
-354
-236
-118
0
118
236
354
472
590
708
826
944
1062
1180
1298
1416
1534
1652
1770
1888
2006
2124
2242
2366
2490
2614
2738
2862
2986
3178 -2006
-1888
-1770
-1652
-1534
-1416
-1298
-1180
-1062
-944
-826
-708
-590
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
PIN
Name
O105
O106
O107
O108
O109
O110
O111
O112
O113
O114
O115
O116
O117
O118
O119
O120
O121
O122
O123
O124
O125
O126
X
3178
Y
-472
-354
-236
-118
0
118
236
354
472
590
708
826
944
1062
1180
1298
1416
1534
1652
1770
1888
2006
Rev.1.4
S1D15300 Series
5. PIN DESCRIPTION
Power Supply
Name
I/O
Description
Number of pins
VDD
Supply
+5V power supply. Connect to microprocessor power supply pin VCC.
2
VSS
Supply
Ground
1
V1, V2
V3, V4
V5
Supply
LCD driver supply voltages. The voltage determined by LCD cell is
impedance-converted by a resistive driver or an operational amplifier
for application. Voltages should be the following relationship:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
When the on-chip operating power circuit is on, the following voltages
are given to V1 to V4 by the on-chip power circuit. Voltage selection is
performed by the Set LCD Bias command. (The S1D15303 and S1D15304
are fixed to 1/5 bias.)
S1D15300/S1D15305
V1
V2
V3
V4
V1
V2
V3
V4
1/5•V5
2/5•V5
3/5•V5
4/5•V5
1/6•V5
2/6•V5
4/6•V5
5/6•V5
S1D15301
1/6•V5
2/6•V5
4/6•V5
5/6•V5
1/8•V5
2/8•V5
6/8•V5
7/8•V5
S1D15303
S1D15304
1/5•V 5
2/5•V 5
3/5•V 5
4/5•V 5
1/5•V 5
2/5•V 5
3/5•V 5
4/5•V 5
6
S1D15302
1/6•V5
2/6•V5
4/6•V5
5/6•V5
1/8•V 5
2/8•V 5
6/8•V 5
7/8•V 5
LCD Driver Supplies
Name
I/O
CAP1+
O
DC/DC voltage converter capacitor 1 positive connection
1
CAP1–
O
DC/DC voltage converter capacitor 1 negative connection
1
CAP2+
O
DC/DC voltage converter capacitor 2 positive connection
1
CAP2–
O
DC/DC voltage converter capacitor 2 negative connection
1
CAP3–
O
DC/DC voltage converter capacitor 1 negative connection
1
VOUT
I/O
DC/DC voltage converter output
1
Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
1
VR
I
Description
Number of pins
Microprocessor Interface
Name
I/O
Description
Number of pins
D0 to D7
I/O
8-bit bi-directional data bus to be connected to the standard 8-bit or 16-bit
microprocessor data bus.
When the serial interface selects;
D7: Serial data input (SI)
D6: Serial clock input (SCL)
8
I
Control/display data flag input. It is connected to the LSB of microprocessor address bus. When LOW, the data on D0 to D7 is control data.
When HIGH, the data on D0 to D7 is display data.
1
When RES is caused to go LOW, initialization is executed.
A reset operation is performed at the RES signal level.
1
(SI)
(SCL)
A0
RES
CS1
CS2
I
Chip select input. Data input/output is enabled when -CS1 is LOW and
CS2 is HIGH. When chip select is non-active, D0 to D7 will be "HZ".
2
RD
(E)
I
• When interfacing to an 8080 series microprocessor:
Active LOW. This input connects the RD signal of the 8080 series
microprocessor. While this signal is LOW, the S1D15300 series data
bus output is enabled.
• When interfacing to a 6800 series microprocessor:
Active HIGH. This is used as an enable clock input pin of the 6800 series
microprocessor.
1
Rev.1.4
EPSON
5–5
S1D15300 Series
Name
I/O
Description
Number of pins
WR
(R/W)
I
• Write enable input. When interfacing to an 8080-series microprocessor,
WR is active LOW.
• When interfacing to an 6800-series microprocessor,
it will be read mode when R/W is HIGH and it will be write mode when
R/W is LOW.
R/W = “1”:Read
R/W = “0”:Write
1
C86
I
Microprocessor interface select terminal.
C86 = HIGH: 6800 series microprocessor interface
C86 = LOW: 8080 series microprocessor interface
1
P/S
I
Serial data input/parallel data input select pin.
1
P/S
Chip select Data/command
Data
Read/write Serial clock
HIGH CS1, CS2
A0
D0-D7
RD, WR
—
LOW
A0
SI(D7)
Write only
SCL(D6)
CS1, CS2
* In serial mode, no data can be read from RAM.
When P/S = LOW, D0 to D5 are HZ and RD and WR must be fixed HIGH
or LOW.
LCD Driver Outputs
Name
I/O
M/S
I
Description
S1D15300 series master/slave mode select input. When a necessary
signal is output to the LCD, the master operation is synchronized with
the LCD system, while when a necessary signal is input to the LCD,
the slave operation is synchronized with the LCD system.
M/S = HIGH: Master operation
M/S = LOW : Slave operation
The folLOWing is provided depending on the M/S status.
Model
S1D1530 D
* ****
5–6
Status
Master
Slave
Number of pins
1
Power
supply
CL
FR
DYO FRS DOF
circuit
Enabled Enabled Output Output Output Output Output
Disabled Disabled Input Input
HZ
HZ Input
OSC
circuit
CL
I/O
Display clock input/output. When the S1D15300 series selects master/
slave mode, each CL pin is connected. When it is used in
combination with the common driver, this input/output is connected to
common driver YSCL pin.
M/S = HIGH: Output
M/S = LOW: Input
1
FR
I/O
LCD AC signal input/output. When the S1D15300 series selects master/
slave mode, each FR pin is connected.
When the S1D15300 series selects master mode this input/output is
connected to the common driver FR pin.
M/S = HIGH: Output
M/S = LOW: Input
1
DYO
I/O
Common drive signal output. This output is enabled for only at master
operation and connects to the common driver DIO pin. It becomes HZ
at slave operation.
1
VS1
O
Test pin. Don’t connect.
1
DOF
I/O
LCD blanking control input/output. When the S1D15300 series selects
master/slave mode, the respective DOF pin is connected. When it
is used in combination with the common driver (S1D16305), this output/
input is connected to the common driver DOFF pin.
M/S = HIGH: Output
M/S = LOW: Input
1
FRS
O
Static drive output.
This is enabled only at master operation and used together with the FR
pin. This output becomes HZ at slave operation.
1
EPSON
Rev.1.4
S1D15300 Series
Name
I/O
On
(SEG n)
(Com n)
O
Description
Number of pins
LCD drive output. The following assignment is made depending on
the model.
S1D15300D00**
S1D15300D10**
S1D15300D15**
S1D15301D00**
S1D15302D00**
S1D15302D14**
S1D15302D11**
S1D15303D15**
S1D15304D14**
S1D15305D10**
SEG
O0~O99
COM
O100~O131
O16~O115
O0~O15, O116~O131
132
O0~O131
O0~O99
O100~O131
O32~O131
O8~O123
O0~O123
O18~O115
O0~O31
O0~O7, O124~O131
O124~O131
O0~O17, O116~O131
SEG output. LCD segment drive output. One of VDD, V2, V3 and
V5 levels is selected by combination of the contents of display RAM
and FR signal.
RAM data
HIGH
0
Power save
FR
HIGH
LOW
HIGH
LOW
–
On output voltage
Normal display Reverse display
VDD
V2
V5
V3
V2
VDD
V3
V5
VDD
COM output. LCD common drive output. One of VDD, V1, V4 and V5
levels is selected by combination of scan data and FR signal.
Scan data
HIGH
LOW
Power save
COMS
O
FR
HIGH
LOW
HIGH
LOW
–
On output voltage
V5
VDD
V1
V4
VDD
Indicator COM output. When it is not used, it is made open.
Effective only with the S1D15300, S1D15302, S1D15303 and S1D15304,
S1D15305 and “HZ” with the S1D15301.
When multiple numbers of the S1D15300, S1D15302, S1D15303 and
S1D15304, S1D15305 are used, the same COMS signal is output to both
master and slave units.
Total
Rev.1.4
EPSON
1
172
5–7
S1D15300 Series
6. FUNCTIONAL DESCRIPTION
Microprocessor Interface
Interface type selection
The S1D15300 series can transfer data via 8-bit bi-directional data buses (D7 to D0) or via serial data input (SI). When HIGH or LOW is selected
for the polarity of P/S pin, either 8-bit parallel data input or serial data input can be selected as shown in Table 1. When serial data input is selected,
RAM data cannot be read out.
Table 1
P/S
Type
CS1
CS2
A0
RD
WR
C86
D7
D6
D0 to D5
HIGH
LOW
Parallel input
Serial input
CS1
CS1
CS2
CS2
A0
A0
RD
–
WR
–
C86
–
D7
SI
D6
SCL
D0 to D5
(HZ)
“–” must always be HIGH or LOW.
Parallel input
When the S1D15300 series selects parallel input (P/S = HIGH), the 8080 series microprocessor or 6800 series microprocessor can be selected
by causing the C86 pin to go HIGH or LOW as shown in Table 2.
Table 2
C86
Type
HIGH
6800 microprocessor bus
8080 microprocessor bus
LOW
CS1
CS2
A0
RD
WR
D0 to D7
CS1
CS2
A0
E
R/W
D0 to D7
CS1
CS2
A0
RD
RW
D0 to D7
Data Bus Signals
The S1D15300 series identifies the data bus signal according to A0, E, R/W, (RD, WR) signals.
Table 3
Common
6800 processor
8080 processor
A0
(R/W)
RD
WR
1
1
0
1
Reads display data.
1
0
1
0
Writes display data.
0
1
0
1
Reads status.
0
0
1
0
Writes control data in internal register. (Command)
Function
Serial Interface (P/S is low)
The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data input and serial clock input are enabled when CS1 is
low and CS2 is high (in chip select status). When chip is not selected, the shift register and counter are reset.
Serial data of D7, D6, ..., D0 is read at D7 in this sequence when serial clock (SCL) goes high. They are converted into 8-bit parallel data and
processed on rising edge of every eighth serial clock signal.
The serial data input (S1) is determined to be the display data when A0 is high, and it is control data when A0 is low. A0 is read on rising edge
of every eighth clock signal.
Figure 1 shows a timing chart of serial interface signals. The serial clock signal must be terminated correctly against termination reflection and
ambient noise. Operation checkout on the actual machine is recommended.
CS1
CS2
D7
SI
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A0
Figure 1
5–8
EPSON
Rev.1.4
S1D15300 Series
Also, the microprocessor temporarily stores display data in bus
holder, and stores it in display RAM until the next data write cycle
starts.
When viewed from the microprocessor, the S1D15300 series access
speed greatly depends on the cycle time rather than access time to the
display RAM (tACC). It shows the data transfer speed to/from the
microprocessor can increase. If the cycle time is inappropriate, the
microprocessor can insert the NOP instruction that is equivalent to
the wait cycle setup. However, there is a restriction in the display
RAM read sequence. When an address is set, the specified address
data is NOT output at the immediately following read instruction.
The address data is output during second data read. A single dummy
read must be inserted after address setup and after write cycle (refer
to Figure 2).
Chip Select Inputs
The S1D15300 series has two chip select pins, CS1 and CS2 and can
interface to a microprocessor when CS1 is low and CS2 is high.
When these pins are set to any other combination, D0 to D7 are high
impedance and A0, RD and WR inputs are disabled.
When serial input interface is selected, the shift register and counter
are reset.
Access to Display Data RAM and Internal Registers
The S1D15300 series can perform a series of pipeline processing
between LSI’s using bus holder of internal data bus in order to match
the operating frequency of display RAM and internal registers with
the microprocessor. For example, the microprocessor reads data
from display RAM in the first read (dummy) cycle, stores it in bus
holder, and outputs it onto system bus in the next data read cycle.
•Write
WR
MPU
DATA
Internal
timing
n
n+1
n+2
Latched
n
Bus holder
n+1
n+3
n+2
n+3
Write signal
•Read
WR
MPU
RD
DATA
N
N
n
n+1
Address
preset
Read signal
Internal
timing
Preset
Column
address
Incremented
N+1
N
N
Bus holder
Set address n
n
Dummy read
Data Read address n
N+2
n+1
n+2
Data Read address n+1
Figure 2
Busy Flag
The Busy flag is set when the S1D15300 series starts to operate.
During operating, it accepts Read Status instruction only. The busy
flag signal is output at pin D7 when Read Status is issued. If the cycle
time (tcyc) is correct, the microprocessor needs not to check the flag
before issuing a command. This can greatly improve the microprocessor performance.
COM0 (usually, the top line of screen) is determined using register
data. The register is also used for screen scrolling and page
switching.
The Set Display Start Line command sets the 6-bit display start
address in this register. The register data is preset on the line counter
each time FR signal status changes. The line counter is incremented
by CL signal and it generates a line address to allow 132-bit
Initial Display Line Register
When the display RAM data is read, the display line according to
Rev.1.4
EPSON
5–9
S1D15300 Series
Column Address Counter
This is a 8 bit presettable counter that provides column address to the
display RAM (refer to Figure 4). It is incremented by 1 when a Read/
Write command is entered. However, the counter is not incremented
but locked if a non-existing address above 84H is specified. It is
unlocked when a column address is set again. The Column Address
counter is independent of Page Address register.
When ADC Select command is issued to display inverse display, the
column address decoder inverts the relationship between RAM
column address and display segment output.
Page Address Register
This is a 4-bit page address register that provides page address to the
display RAM (refer to Figure 4). The microprocessor issues Set
Page Address command to change the page and access to another
page. Page address 8 (D3 is high, but D2, D1 and D0 are low) is
D0
D1
D2
D3
D4
RAM area dedicate to the indicator, and display data D0 is only
valid.
Display Data RAM
The display data RAM stores pixel data for LCD. It is a 65-column
by 132-row (8-page by 8 bit+1) addressable array. Each pixel can
be selected when page and column addresses are specified.
The time required to transfer data is very short because the microprocessor enters D0 to D7 corresponding to LCD common lines as
shown in Figure 3. Therefore, multiple S1D15300 can easily
configure a large display having the high flexibility with very few
data transmission restriction.
The microprocessor writes and reads data to/from the RAM through
I/O buffer. As LCD controller operates independently, data can be
written into RAM at the same time as data is being displayed,
without causing the LCD to flicker.
1
0
1
0
0
COM0
COM1
COM2
COM3
COM4
Display data RAM
Display on LCD
Figure 3
5–10
EPSON
Rev.1.4
S1D15300 Series
Relationship between display data RAM and addresses (if initial display line is 1CH):
0,0,1,1
0,1,0,0
0,1,0,1
0,1,1,0
0,1,1,1
Column
address
1,0,0,0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
1/64
Start
1/32
COM
output
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
80
81
82
83
0,0,1,0
Page 0
03
02
01
00
0,0,0,1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
O128
O129
O130
O131
D3, D2,
D1,D0
0,0,0,0
Line
address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Data
ADC
LCD
D0= D0=
OUT
"1" "0"
O0 83 00
O1 82 01
O2 81 02
O3 80 03
O4 7F 04
O5 7E 05
O6 7D 06
O7 7C 07
Page
address
Page 8 is accessed during
1/65 or 1/33 duty.
Figure 4
Rev.1.4
EPSON
5–11
S1D15300 Series
Output Status Selector
The S1D15300 series except S1D15301 can set a COM output scan direction to reduce restrictions at LCD module assembly. This scan direction
is set by setting “1” or “0” in the output status register D3. Fig.5 shows the status.
Fig. 5 shows the status.
LCD output
ADC
(D0)
"0"
O0
O131
0 (H)
"1"
83 (H)
Column address
83 (H)
0 (H)
Display data RAM
D3
S1D15300D00 ✽✽
SEG100
0
COM0
SEG100
1
COM31
COM31
COM0
S1D15300D10 ✽✽ 0
COM15
0
SEG100
COM16
31
S1D15300D15 ✽✽ 1
COM16
31
SEG100
COM15
0
SEG132
S1D15301D00 ✽✽ –
S1D15302D00 ✽✽ 0
SEG100
S1D15302D14 ✽✽
SEG100
S1D15302D11✽✽
S1D15303D15 ✽✽
S1D15304D14 ✽✽
S1D15305D10 ✽✽
1
COM0
COM31
COM31
COM0
0
COM31
0
SEG100
1
COM0
31
SEG100
0
COM7
0
SEG116
COM8
15
1
COM8
15
SEG116
COM7
0
0
SEG124
COM0
7
1
SEG124
COM7
0
0
COM17 0
SEG98
COM18 33
1
COM16 33
SEG98
COM17 0
The COMS pin is assigned to COM32 on S1D15300 and it is assigned to COM64 on S1D15302 independent from their output status.
The COMS pin of the S1D15303 is assigned to COM16 the COMS pin of the S1D15304 is assigned to COM8 and the COMS pin of the S1D15305
is assigned to COM34.
Figure 5 shows the COM output pin numbers of S1D15302D00** and S1D15302D11** in the master mode. In the slave mode, COM0 to
COM31 must be replaced by COM32 to COM63.
FR (master output)
Master Common
Slave Common
64 0
63 64
1
2
30 31
64 0
32 33 34
Display Timing Generator
This section explains how the display timing generator circuit
operates.
Signal generation to line counter and display data latch
circuit
The display clock (CL) generates a clock to the line counter and a
latch signal to the display data latch circuit.
The line address of the display RAM is generated in synchronization
with the display clock. 132-bit display data is latched by the display
data latch circuit in synchronization with the display clock and
output to the segment LCD drive output pin.
The display data is read to the LCD drive circuit completely
independent of access to the display data RAM from the microprocessor.
5–12
2
30 31
32
62 63 64
When the S1D15300 is operated in slave mode on the assumption of
multi-chip, the FR pin and CL pin become input pins.
Common timing signal generation
The display clock generates an internal common timing signal and
a start signal (DYO) to the common driver. A display clock resulting
from frequency division of an oscillation clock is output from the CL
pin.
When an AC signal (FR) is switched, a high pulse is output as a DYO
output at the training edge of the previous display clock.
Refer to Fig. 6. The DYO output is output only in master mode.
When the S1D15300 series is used for multi-chip, the slave requires
to receive the FR, CL, DOF signals from the master.
Table 4 shows the FR, CL, DYO and DOF status.
Table 4
Model
LCD AC signal (FR) generation
The display clock generates an LCD AC signal (FR). The FR causes
the LCD drive circuit to generate a AC drive waveform.
It generates a 2-frame AC drive waveform.
1
S1D1530*D****
EPSON
Operation
FR
CL
DYO
DOF
mode
Master
Output Output Output Output
Slave
Input
Input
Hz
Input
HZ denotes a high-impedance status.
Rev.1.4
S1D15300 Series
Example of S1D15300D00B* 1/33 duty
•
Dual-frame AC driver waveforms
32
33
1
2
3
4
5
6
28
29
30
31
32
33
1
2
3
4
5
CL
FR
DYO
VDD
V1
V4
V5
VDD
V1
COM0
COM1
V4
V5
RAM data
VDD
V2
SEGn
V3
V5
Fig. 6
The power circuit is controlled by Set Power Control command.
This command sets a three-bit data in Power Control register to
select one of eight power circuit functions. The external power
supply and part of internal power circuit functions can be used
simultaneously. The following explains how the Set Power
Control command works.
Display Data Latch Circuit.
This circuit temporarily stores (or latches) display data (during a
single common signal period) when it is output from display RAM
to LCD panel driver circuit. This latch is controlled by Display in
normal/in reverse Display ON/OFF and Static All-display on commands. These commands do not alter the data.
LCD Driver
[Control by Set Power Control command]
This is a multiplexer circuit consisting of 133 segment outputs to
generate four-level LCD panel drive signals. The LCD panel drive
voltage is generated by a specific combination of display data, COM
scan signal, and FR signal. Figure 8 gives an example of SEG and
COM output waveforms.
D2 turns on when triple booster control bit goes high, and D2 turns
off when this bit goes low.
Oscillator Circuit
D0 turns on when voltage follower control bit goes high, and D0
turns off when this bit goes low.
D1 turns on when voltage regulator control bit goes high, and D1
turns off when this bit goes low.
This is an oscillator having a complete built-in type CR, and its
output is used as the display timing signal source or as the clock for
voltage booster circuit of the LCD power supply.
The oscillator circuit is available in master mode only.
The oscillator signal is divided and output as display clock at CL pin.
[Practical combination examples]
Status 1: To use only the internal power supply.
Status 2: To use only the voltage regulator and voltage follower.
Status 3: To use only the voltage follower. input the external
voltage as V5=Vout.
Status 4: To use only an external power supply because the internal
power supply does not operate.
Power Supply Circuit
The power supply circuit generates voltage to drive the LCD panel
at low power consumption, and is available in S1D15300 master
mode only. The power supply circuit consists of a voltage booster
voltage regulator, and LCD drive voltage follower.
The power supply circuit built in the S1D15300 series is set for a
small-scale LCD panel and is inappropriate to a large-pixel panel
and a large-display-capacity LCD panel using multiple chips. As the
large LCD panel has the dropped display quality due to a large load
capacity, it must use an external power source.
D2 D1 D0
* The voltage booster terminals are CAP1+, CAP1-, CAP2+, CAP2and CAP3-.
* Combinations other than those shown in the above table are
possible but impractical.
Voltage
booster
Voltage
regulator
Voltage
follower
External voltage Voltage booster Voltage regulator
input
terminal
terminal
1
1
1
1
ON
ON
ON
—
Used
Used
2
0
1
1
OFF
ON
ON
VOUT
OPEN
Used
3
0
0
1
OFF
OFF
ON
V5
OPEN
OPEN
4
0
0
0
OFF
OFF
OFF
V1 to V5
OPEN
OPEN
Rev.1.4
EPSON
5–13
S1D15300 Series
Booster circuit
If capacitors C1 are inserted between CAP1+ and CAP1-, between
CAP2+ and CAP2-, CAP1+ and CAP3- and VSS and VOUT, the
potential between VDD and VSS is boosted to quadruple toward the
negative side and it is output at VOUT.
For triple boosting, remove only capacitor C1 between CAP+1 and
CAP3- from the connection of quadruple boosting operation and
jumper between CAP3- and VOUT. The triple boosted voltage
appears at VOUT (CAP3-).
For double boosting, remove only capacitor C1 between CAP2+ and
CAP2- from the connection of triple boosting operation, open
CAP+2 and jumper between CAP2- and VOUT (CAP3-). The
double boosted voltage appears at VOUT (CAP3-, CAP2-).
For quadruple boosting, set a VSS voltage range so that the voltage
at VOUT may not exceed the absolute maximum rating.
As the booster circuit uses signals from the oscillator circuit, the
oscillator circuit must operate.
Subsection 10.1.1 gives an external wiring example to use master
and slave chips when on-board power supply is active.
(VCC =+5V) VDD =0V
VDD =0V
VDD =0V
(GND) VSS =-5V
VSS =-5V
VSS =-3V
VOUT =2VSS =-10V
VOUT =3VSS =-15V
Potential during double boosting
VOUT =3VSS =-12V
Potential during triple boosting
Potential during quadruple boosting
Voltage regulator circuit
The boosting voltage occurring at VOUT is sent to the voltage regulator and the V5 liquid crystal display (LCD) driver voltage is output. This
V5 voltage can be determined by the following equation when resistors Ra and Rb (R1, R2 and R3) are adjusted within the range of |V5| < |VOUT|.
V5=(1+ Rb ) VREG+IREF · Rb
Ra
R3+R2-∆R2
=(1+
) VREG
R1+∆R2
+IREF · (R3+R2-∆R2)
To obtain V5 = -10 V, from equation 1 :
R2 + R3 = 2.92 × R1 ..................... 3
∆R2 = R2, VREG = –2.55V
To obtain V5 = -6 V, from equation 1 :
1.35 × (R1 + R2) = R3 .................. 4
From equations 2 ,
R1=1.27MΩ
R2=0.85MΩ
R3=2.88MΩ
VDD
R1
3
and
4
:
V REG
Ra
∆R2
R2
The voltage regulator circuit has a temperature gradient of
approximately -0.2%/°C as the VREG voltage. To obtain another
temperature gradient, use the Electronic Volume Control Function
for software processing using the MPU.
+
V5
VR IREF
As the VR pin has a high input impedance, the shielded and short
lines must be protected from a noise interference.
Rb
R3
Voltage regulator using the Electronic Volume Control
Function
VREG is the constant voltage source of the IC, and in case of Type 1,
it is constant and VREG .=. –2.55 V (if VDD is 0 V), In case of Type 2,
VREG=V SS (V DD basis). To adjust the V5 output voltage, insert a
variable resistor between VR, VDD and V5 as shown. A combination
of R1 and R3 constant resistors and R2 variable resistor is
recommended for fine-adjustment of V5 voltage.
Setup example of resistors R1, R2 and R3:
When the Electronic Volume Control Function is OFF (electronic
volume control register values are (D4,D3,D2,D1,D0)=(0,0,0,0,0)):
( 1 + R3 + R2 – ∆R2)
VREG .......................
R1 + ∆R2
V5 =
1
V5 = (1 +
(As IREF = 0 A)
• R1 + R2 + R3 = 5MΩ ................................ 2
(Determined by the current passing between VDD and V5)
• Variable voltage range by R2 V5 = –6 to –10 V
(Determined by the LCD characteristics)
∆R2 = OΩ, VREG = –2.55V
5–14
The Electronic Volume Control Function can adjust the intensity
(brightness level) of liquid crystal display (LCD) screen by command
control of V5 LCD driver voltage.
This function sets five-bit data in the electronic volume control
register, and the V 5 LCD driver voltage can be one of 32-state
voltages.
To use the Electronic Volume Control Function, issue the Set Power
Control command to simultaneously operate both the voltage
regulator circuit and voltage follower circuit.
Also, when the boosting circuit is off, the voltage must be supplied
from VOUT terminal.
When the Electronic Volume Control Function is used, the V5
voltage can be expressed as follows:
Rb
) VREG + Rb × ∆IREF ........................
Ra
5
Variable voltage range
The increased V5 voltage is controlled by use of IREF current source
of the IC. (For 32 voltage levels, ∆IREF = IREF/31)
EPSON
Rev.1.4
S1D15300 Series
The minimum setup voltage of the V5 absolute value is determined
by the ratio of external Ra and Rb, and the increased voltage by the
Electronic Volume Control Function is determined by resistor Rb.
Therefore, the resistors must be set as follows:
S1D15300 Series V5
[V]
-10V
V5
1) Determine Rb resistor depending on the V 5 variable voltage
range by use of the Electronic Volume Control.
Rb =
V5 variable voltage range
IREF
-5V
2) To obtain the minimum voltage of the V5 absolute value, determine
Ra using the Rb of Step 1) above.
Rb
Ra =
V5
–1
VREG
V5 variable voltage range
(32 levels)
(VDD) 0V
-20
20
40
Ta
{V5 = (1 + Rb/Ra) × VREG}
The S1D15300 series have the built-in VREG reference voltage and
IREF current source which are constant during voltage variation.
However, they may change due to the variation occurring in IC
manufacturing and due to the temperature change as shown below.
Consider such variation and temperature change, and set the Ra and
Rb appropriate to the LCD used.
VREG = –2.55V±0.20V (Type1)
V REG = VSS (VDD basis) (Type2)
IREF = –3.2µA±40% (For 16 levels)
–6.5µA±40% (For 32 levels)
0
VREG = –0.2%/˚C
VREG = –0.00%/˚C
IREF = 0.023µA/°C
0.052µA/°C
60
[¡C]
According to the V5 voltage and temperature change, equation
be as follows (if VDD = 0 V reference):
5
can
Ta=–10°C
V5max = (1+Rb/Ra) × VREG
(Ta=–10°C)
= (1+625k/462k) × (–2.55V)
× {1+(–0.2%/°C) × (–10°C–25°C)}
= –6.42V
V5min = V5max + Rb × IREF
(Ta=–10°C)
= –6.42V + 625k
× {–6.5µA+(0.052µA/°C) × (–10°C–25°C)}
= –11.63V
Ra is a variable resistor that is used to correct the V5 voltage change
due to VREG and IREF variation. Also, the contrast adjustment is
recommended for each IC chip.
Before adjusting the LCD screen contrast, set the electronic volume
control register values to (D4,D3,D2,D1,D0)=(1,0,0,0,0) or
(0,1,1,1,1) first.
When not using the Electronic Volume Control Function, set the
register values to (D4,D3,D2,D1,D0)=(0,0,0,0,0) by sending the
RES signal or the Set Electronic Volume Control Register command.
Ta=–50°C
V5max = (1+Rb/Ra) × VREG
(Ta=50°C)
= (1+625k/462k) × (–2.55V)
× {1+(–0.2%/°C) × (50°C–25°C)}
= –5.7V
V5min = V5max + Rb × IREF
(Ta=50°C)
= –5.7V + 625k
× {–6.5µA+(0.052µA/°C) × (50°C–25°C)}
= –8.95V
Setup example of constants when Electronic Volume Control
Function is used:
The margin must also be determined in the same procedure given
above by considering the VREG and IREF variation. This margin
calculation results show that the V5 center value is affected by the
VREG and IREF variation. The voltage setup width of the Electronic
Volume Control depends on the IREF variation. When the typical
value of 0.2 V/step is set, for example, the maximum variation range
of 0.12 to 0.28 V must be considered.
V5 maximum voltage:
V5 = –6 V (Electronic volume control
register values (D4,D3,D2,D1,D0) =
(0,0,0,0,0))
V5 minimum voltages:
V5 = –10 V (Electronic volume control
register values (D4,D3,D2,D1,D0) =
(1,1,1,1,1))
V5 variable voltage range: 4 V
Variable voltage levels:
32 levels
1) Determining the Rb:
R3 =
4V
V5 variable voltage range
=
6.5µA Rb = 625KΩ
| IREF |
In case of Type 2, it so becomes that VREG = VSS (VDD basis) and
there is no temperature gradient. However, IREF carries the same
temperature characteristics as with Type 1.
Command Sequence when Built-in Power Supply is Turned
OFF
To turn off the built-in power supply, follow the command sequence
as shown below to turn it off after making the system into the standby
mode.
2) Determining the Ra:
Ra =
Rb
=
V5max
–1
VREG
625kΩ
–6V
–1
–2.55V
Static Indicator ON
Command ADh
Display OFF
Command AEh
Power Save
Command
Ra = 462KΩ
Entire Displays ON
Ta=25°C
V5max = (1+Rb/Ra) × VREG
= (1+625k/442k) × (–2.55V)
= –6.0V
V5min = V5 max + Rb × IREF
= –6V + 625k × (–6.5µA)
= –10.0V
Rev.1.4
Command A5h
Built-in Power OFF
EPSON
5–15
S1D15300 Series
Voltage generator circuit
1–1 Power set command
when the built-in power supply
is used (triple boosting)
(D2, D1, D0) = (1, 1, 1)
1–2 when the on-chip power circuit is used 2 when VOUT is input from the outside
(D2, D1, D0) = (0, 1, 1)
VDD
M/S
CL
CAP3C1
C1
C1
VSS
CAP1+
C1
VSS
C1
CAP1CAP2+
C1
C1
CAP2VOUT
CAP3-
CAP3VSS
CAP1+
CAP2+
R2
CAP2-
VOUT
V5
S1D15300 series
V1
V1
V1
V2
V2
V3
C2
V2
V3
C2
V3
V4
V4
V4
V5
V5
V5
4 when the on-chip power circuit is used
VDD
M/S
M/S
VSS
CL
CAP3CAP1+
CAP3VSS
VSS
CAP1+
CAP1-
CAP1-
CAP2+
CAP2+
CAP2-
CAP2-
VOUT
VOUT
V5
VR
VDD
S1D15300 series
R1
VDD
VSS
V5
S1D15300 series
VR
S1D15300 series
VDD
VDD
VDD
V1
V2
C2
V3
V4
V5
5–16
VR
VDD
VDD
External
power
supply
R2
VDD
3 when V5 is input from the outside
(D2, D1, D0) = (0, 0, 1)
VSS
CAP2+
CAP2-
R1
VDD
VSS
CAP1-
R3
VR
VDD
R1
CL
CAP1+
External
power
supply
CAP1-
V5
S1D15300 series
VR
C2
VSS
R3
V5
VDD
VSS
VOUT
R3
R2
M/S
M/S
VSS
VSS
VDD
VDD
V1
External
power
supply
V2
V3
V4
V5
EPSON
Rev.1.4
S1D15300 Series
Reference setup value: S1D15300 V5 = -7 to -9 V
S1D15301 V5 = -11 to -13 V (variable)
S1D15302 V5 = -11 to -13 V (variable)
SED1530
SED1531
SED1532
C1
1.0~4.7 uF
1.0~4.7 uF
1.0~4.7 uF
C2
0.22~0.47 uF
0.47~1.0 uF
0.47~1.0 uF
R1
700 KΩ
1 MΩ
1 MΩ
R2
200 KΩ
200 KΩ
200 KΩ
R3
1.6 MΩ
4 MΩ
4 MΩ
LCD
SIZE
16 × 50 mm
32 × 64 mm
32 × 100 mm
DOT
CONFIGURATION
32 × 100
64 × 128
64 × 200
1:
*2: C1 and C2 depend on the capacity of the LCD panel to be
driven. Set a value so that the LCD drive voltage may be stable.
[Setup example]
Turn on the voltage regulator and voltage follower and give an
external voltage to VOUT. Display a horizontal-stripe LCD
heavy load pattern and determine C2 so that the LCD drive
voltage (V1 to V5) may be stable. However, the capacity value
of C2 must be all equal. Next, turn on all the on-board power
supplies and determine C1.
*3: LCD SIZE means the length and breadth of the display portion
of the LCD panel.
LCD drive voltage
S1D15300
S1D15301
S1D15302
1/5 or 1/6 bias
1/6 or 1/8 bias
When the RES input goes low, this LSI is initialized.
Initialized status
As the input impedance of VR is high, a noise protection using
short wire and cable shield is required.
Model
Reset Circuit
1. Display OFF
2. Normal display
3. ADC select: Normal display (ADC command D0 =
low)
4. Read modify write OFF
5. Power control register (D2, D1, D0) = (0, 0, 0)
6. Register data clear in serial interface
7. LCD power supply bias ratio 1/6 (S1D15300), 1/8
(S1D15301, SE1D15302)
8. Static indicator: OFF
9. Display start line register set at line 1
10. Column address counter set at address 0
11. Page address register set at page 0
12. Output status register (D3) = (0)
13. Electronic control register set at 0
14. Test command OFF
As seen in 11. Microprocessor Interface (Reference Example),
connect the RES pin to the reset pin of the microprocessor and
initialize the microprocessor at the same time.
In case the S1D15300 series does not use the internal LCD power
supply circuit, the RES must be low when the external LCD power
supply is turned on.
When RES goes low, each register is cleared and set to the above
initialized status. However, it has no effect on the oscillator circuit
and output pins (FR, CL, DYO, D0 to D7).
The initialization by RES pin signal is always required during
power-on. If the control signal from the MPU is HZ, an overcurrent
may flow through the IC. A protection is required to prevent the HZ
signal at the input pin during power-on.
Be sure to initialize it by RES pin when turning on the power supply.
When the reset command is used, only parameters 8 to 14 in the
above initialization are executed.
* Precautions when installing the COG
When installing the COG, it is necessary to duly consider the fact
that there exists a resistance of the ITO wiring occurring between the
driver chip and the externally connected parts (such as capacitors
and resistors). By the influence of this resistance, non-conformity
may occur with the indications on the liquid crystal display.
Therefore, when installing the COG design the module paying
sufficient considerations to the following three points.
1. Suppress the resistance occurring between the driver chip pin to
the externally connected parts as much as possible.
2. Suppress the resistance connecting to the power supply pin of
the driver chip.
3. Make various COG module samples with different ITO sheet
resistance to select the module with the sheet resistance with
sufficient operation margin.
Also, as for this driver IC, pay sufficient attention to the following
points when connecting to external parts for the characteristics of the
circuit.
1. Connection to the boosting capacitors The boosting capacitors
(the capacitors connecting to respective CAP pins and capacitor
being inserted between VOUT and VSS2) of this IC are being
switched over by use of the transistor with very low ONresistance of about 10Ω. However, when installing the COG,
Rev.1.4
2.
the resistance of ITO wiring is being inserted in series with the
switching transistor, thus dominating the boosting ability.
Consequently, the boosting ability will be hindered as a result
and pay sufficient attention to the wiring to respective boosting
capacitors.
Connection of the smoothing capacitors for the liquid crystal
drive
The smoothing capacitors for the liquid crystal driving potentials
(V1. V2, V3 and V4) are indispensable for liquid crystal drives
not only for the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs pursuant to
installation of the COG is supplemented to these smoothing
capacitors, the liquid crystal driving potentials become unstable
to cause non-conformity with the indications of the liquid
crystal display. Therefore, when using the COG module, we
definitely recommend to connect reinforcing resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these reinforcing
resistors, current consumption will increase.
Indicated below is an exemplary connection diagram of external
resistors.
Please make sufficient evaluation work for the display statuses with
any connection tests.
EPSON
5–17
S1D15300 Series
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
VDD
VDD
R4
V1
V2
C2
V3
C2
V1
C2
R4
S1D15300 Series
C2
S1D15300 Series
R4
VDD
V2
C2
V3
C2
R4
V4
C2
C2
V4
R4 R4
V5
C2
C2
COM 0
VDD
VSS
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
FR
COM 1
COM 2
COM 0
COM 3
COM 4
COM 5
COM 1
COM 6
COM 7
COM 8
COM 2
COM 9
COM 10
COM 11
COM 12
SEG 0
COM 13
COM 14
COM 15
SEG 1
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
V5
S
E
G
4
COM -SEG 0
COM -SEG 1
Figure 8
5–18
EPSON
Rev.1.4
S1D15300 Series
7. COMMANDS
A0
The S1D15300 series uses a combination of A0, RD (E) and WR (R/
W) signals to identify data bus signals. As the chip analyzes and
executes each command using internal timing clock only regardless
of external clock, its processing speed is very high and its busy check
is usually not required. The 8080 series microprocessor interface
enters a read status when a low pulse is input to the RD pin and a write
status when a low pulse is input to the WR pin. The 6800 series
microprocessor interface enters a read status when a high pulse is
input to the R/W pin and a write status when a low pulse is input to
this pin. When a high pulse is input to the E pin, the command is
activated. (For timing, see Timing Characteristics.) Accordingly, in
the command explanation and command table, RD (E) becomes 1
(high) when the 6800 series microprocessor interface reads status or
display data. This is an only different point from the 8080 series
microprocessor interface.
Taking the 8080 series microprocessor interface as an example,
commands will be explained below.
When the serial interface is selected, input data starting from D7 in
sequence.
E R/W
RD WR D7
0
1
A3
0
0
0
0
0
0
0
0
1
0
A2
0
0
0
0
1
1
1
1
0
0
E R/W
RD WR D7
1
0
1
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
D
(2) Start Display Line
Specifies line address (refer to Figure 4) to determine the initial
display line, or COM0. The RAM display data becomes the top
line of LCD screen. It is followed by the higher number of lines
in ascending order, corresponding to the duty cycle. When this
command changes the line address, the smooth scrolling or
page change takes place.
A0
0
1
0
D6
D5
D4
D3
D2
D1
D0
1
A5
A4
A3
A2
A1
A0
←
A5
0
0
0
A4
0
0
0
A3
0
0
0
1
1
1
1
1
1
A2
0
0
0
A1
0
0
1
A0
0
1
0
1
1
1
1
0
1
:
D3
D2
D1
D0
0
1
1
A3
A2
A1
A0
1
A0
0
1
0
1
0
1
0
1
0
Page Address
0
1
2
3
4
5
6
7
8
(4) Set Column Address
Specifies column address of display RAM. Divide the column
address into 4 higher bits and 4 lower bits. Set each of them
succession. When the microprocessor repeats to access to the
display RAM, the column address counter is incremented by 1
during each access until address 132 is accessed. The page
address is not changed during this time.
Higher bits
0
1
0
0
0
0
1 A7 A6 A5 A4
Lower bits
0
1
0
0
0
0
0 A3 A2 A1 A0
A1
0
0
A0
0
1
1
1
Column address
0
1
:
131
A7
0
0
A6 A5
0
0
0
0
0
Line address
0
1
2
:
62
63
(3) Set Page Address
Specifies page address to load display RAM data to page
address register. Any RAM data bit can be accessed when its
page address and column address are specified. The display
remains unchanged even when the page address is changed.
Page address 8 is the display RAM area dedicate to the indicator, and only D0 is valid for data change.
A3 A2
0
0
0
0
0
0
0
0
(5) Read Status
E R/W
RD WR D7
0
High-order bit
A4
0
0
:
1
A0
0
D4
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
The display turns off when D goes low, and it turns on when D
goes high.
E R/W
RD WR D7
D5
A1
0
0
1
1
0
0
1
1
0
(1) Display ON/OFF
Alternatively turns the display on and off.
A0
D6
0
1
D6
D5
D4 D3
BUSY ADC ON/OFF RESET 0
D2
D1
D0
0
0
0
BUSY:
When high, the S1D15206 series is busy due to internal
operation or reset. Any command is rejected until BUSY
goes low. The busy check is not required if enough time
is provided for each cycle.
ADC:
Indicates the relationship between RAM column address
and segment drivers. When low, the display is normal and
column address “131-n” corresponds to segment driver n.
When high, the display is reversed and column address n
corresponds to segment driver n.
ON/OFF: Indicates whether the display is on or off. When goes low,
the display turns on. When goes high, the display turns
off. This is the opposite of Display ON/OFF command.
RESET: Indicates the initialization is in progress by RES signal
or by Reset command. When low, the display is on.
When high, the chip is being reset.
(6) Write Display Data
Writes 8-bit data in display RAM. As the column address is
incremented by 1 automatically after each write, the microprocessor can continue to write data of multiple words.
A0
1
Rev.1.4
EPSON
E R/W
RD WR D7
1
0
D6
D5
D4
D3
D2
D1
D0
Write data
5–19
S1D15300 Series
(7) Read Display Data
Reads 8-bit data from display RAM area specified by column
address and page address. As the column address is incremented
by 1 automatically after each write, the microprocessor can
continue to read data of multiple words. A single dummy read
is required immediately after column address setup. Refer to
the display RAM section of FUNCTIONAL DESCRIPTION
for details. Note that no display data can be read via the serial
interface.
A0
1
RD WR D7
0
D6
1
D5
D4
D3
D2
D1
D0
A0
0
0
1
0
1
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
D
When D is low, the right rotation (normal direction). When D
is high, the left rotation (reverse direction).
(9) Normal/Reverse Display
Reverses the Display ON/OFF status without rewriting the
contents of the display data RAM.
E R/W
RD WR D7
A0
0
1
0
1
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
D
0
When D is low, the RAM data is high, being LCD ON potential
(normal display).
When D is high, the RAM data is low, being LCD ON potential
(reverse display).
1
D4
D3
D2
D1
D0
0
1
0
0
0
1
D
Bias ratio of LCD power supply
1/5 bias or 1/6 bias
1/6 bias or 1/8 bias
1/5 bias
(12) Read-Modify-Write
A pair of Read-Modify-Write and End commands must always
be used. Once Read-Modify-Write is issued, column address is
not incremented by Read Display Data command but
incremented by Write Display Data command only. It continues until End command is issued. When the End is issued,
column address returns to the address when Read-ModifyWrite was issued. This can reduce the microprocessor load
when data of a specific display area is repeatedly changed
during cursor blinking or others.
A0
D6
0
D5
Model
S1D15300
S1D15301
S1D15302
S1D15303
S1D15304
(8) ADC Select
Changes the relationship between RAM column address and
segment driver. The order of segment driver output pins can be
reversed by software. This allows flexible IC layout during
LCD module assembly. For details, refer to the column address
section of Figure 4. When display data is written or read, the
column address is incremented by 1 as shown in Figure 4.
D6
1
D6
The potential V5 is resistively divided inside the IC to produce
potentials V1, V2, V3 and V4 which are necessary to drive the LCD.
The bias ratio can be selected using the LCD bias setting command.
(The S1D15303 and S1D15304 are fixed to 1/5 bias.)
Moreover, the potentials V1, V2, V3 and V4 are converted in the
impedance and supplied to the LCD drive circuit.
Read data
E R/W
A0 RD WR D7
E R/W
RD WR D7
E R/W
RD WR D7
1
0
1
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
0
0
0
Note: Any command except Read/Write Display Data and Set
Column Address can be issued during Read-Modify-Write
mode.
• Cursor display sequence
(10) Entire Display ON
Forcibly turns the entire display on regardless of the contents of
the display data RAM. At this time, the contents of the display
data RAM are held.
This command has priority over the Normal/Reverse Display
command. When D is low, the normal display status is provided.
Set Page Address
Set Column Address
Read-Modify-Write
E R/W
A0 RD WR D7
0
1
0
1
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
D
Dummy Read
When D is high, the entire display ON status is provided.
If the Entire Display ON command is executed in the display
OFF status, the LCD panel enters Power Save mode. Refer to
the Power Save section for details.
(11) Set LCD Bias
Selects a bias ratio of the voltage required for driving the LCD.
This command is enabled when the voltage follower in the
power supply circuit operates.
(The LCD bias setting command is invalid for the S1D15303
and S1D15304. They are being fixed to the 1/5 bias.)
5–20
EPSON
Read Data
Write Data
No
Completed?
Yes
End
Rev.1.4
S1D15300 Series
(13) End
Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write was issued).
A0
E R/W
RD WR D7
0
1
0
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
1
1
0
1
Return
Column address
N
N+1
N+2
N+3
N+m
N
Read-Modify-Write mode is selected.
(14) Reset
Resets the Initial Display Line register, Column Address counter, Page Address register, and output status selector circuit to
their initial status. The Reset command does not affect on the
contents of display RAM. Refer to the Reset circuit section of
FUNCTIONAL DESCRIPTION.
E R/W
RD WR D7
A0
0
1
0
1
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
0
1
0
The Reset command cannot initialize LCD power supply. Only
the Reset siganl to the RES pin can initialize the supplies.
(15) Output Status Select Register
Applicable to the S1D15300 and S1D15302. When D is high
or low, the scan direction of the COM output pin is selectable.
Refer to Output Status Selector Circuit in Functional Description for details.
A0
0
E R/W
RD WR D7
1
0
1
D6
D5
D4
D3
D2
D1
D0
1
0
0
D
∗
∗
∗
0
1
0
0
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
A2
A1
A0
0
0
1
0
1
D6
D5
D4
D3
D2
D1
D0
0
0
A4
A3
A2
A1
A0
D1
0
0
1
D0
0
1
0
0
1
1
1
0
1
E R/W
RD WR D7
↓
HIGH
1
0
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
D
1
(19) Power Save (Compound Command)
When all displays are turned on during indicator off, the Power
Save command is issued to greatly reduce the current consumption.
If the static indicators are off, the Power Save command sleeps
the system. If on, this command stands by the system.
Release the Sleep mode using the both Power Save OFF
command (Indicator ON command or All Indicator Displays
OFF command) and Static Indictor ON command.
Release the Standby mode using the Power Save OFF command
(Indicator ON command or All Indicator Displays OFF
command).
Static OFF
Indicator ON
Power Save (compound command)
(Sleep mode)
(Standby mode)
Power Save OFF (Display ON command or
Entire Displays OFF command)
Static Indicator ON
(Sleeve mode released)
Rev.1.4
| V5 |
LOW
D 0: Static indicator OFF
1: Static indicator ON
(17) Set Electronic Control
Adjusts the contrast of LCD panel display by changing V5 LCD
drive voltage that is output by voltage regulator of on-board
power supply.
This command selects one of 32 V5 LCD drive voltages by
storing data in 5-bit register. The V5 voltage adjusting range
should be determined depending on the external resistance.
Refer to the Voltage Regulator section of FUNCTIONAL
DESCRIPTION for details.
A0
1
1
1
A0
When A0 goes low, voltage follower turns off. When A0 goes
high, it turns on.
When A1 goes low, voltage regulator turns off. When A1 goes
high, it turns on.
When A2 goes low, voltage booster turns off. When A2 goes
high, it turns on.
R/W
RD WR D7
1
1
1
D2
0
0
0
:
1
1
1
(18) Static Indicator
This command turns on or off static drive indicators. The
indicator display is controlled by this command only, and it is
not affected by the other display control commands.
Either FR or FRS terminal is connected to either of static
indicator LCD drive electrodes, and the remaining terminal is
connected to another electrode. When the indicator is turned
on, the static drive operates and the indicator blinks at an
interval of approximately one second. The pattern separation
between indicator electrodes are dynamic drive electrodes is
recommended. A closer pattern may cause an LCD and
electrode deterioration.
(16) Set Power Control
Selects one of eight power circuit functions using 3-bit register.
An external power supply and part of on-chip power circuit can
be used simultaneously. Refer to Power Supply Circuit section
of FUNCTIONAL DESCRIPTION for details.
E R/W
RD WR D7
D3
0
0
0
Set register to (D4,D3,D2,D1,D0)=(0,0,0,0,0) to suppress electronic control function.
D: Selects the scan direction of COM output pin
* : Invalid bit
A0
D4
0
0
0
End
EPSON
(Standby mode released)
5–21
S1D15300 Series
Sleep mode
This mode stops every operation of the LCD display system,
and can reduce current consumption nearly to a static current
value if no access is made from the microprocessor. The
internal status in the sleep mode is as follows:
When an external power supply is used, likewise, the function
of this external power supply must be stopped so that it may be
fixed to floating or VDD level, prior to or concurrently with
causing the S1D15300 series to go to the sleep mode or standby
mode.
(1) Stops the oscillator circuit and LCD power supply circuit.
(2) Stops the LCD drive and outputs the VDD level as the
segment/common driver output.
(3) Holds the display data and operation mode provided before
the start of the sleep mode.
(4) The MPU can access to the built-in display RAM.
When the common driver S1D16305 or S1D16501 is combined
with the S1D15301 in the configuration, the DOF pin of the
S1D15301 must be connected to the DOFF pin of the S1D16305
or S1D16501.
Standby mode
Stops the operation of the duty LCD display system and turns
on only the static drive system to reduce current consumption
to the minimum level required for static drive.
The ON operation of the static drive system indicates that the
S1D15300 series is in the standby mode. The internal status in
the standby mode is as follows:
(20) Test Command
This is the dedicate IC chip test command. It must not be used
for normal operation. If the Test command is issued erroneously, set the -RES input to low or issue the Reset command to
release the test mode.
(1) Stops the LCD power supply circuit.
(2) Stops the LCD drive and outputs the VDD level as the
segment/common driver output. However, the static drive
system operates.
(3) Holds the display data and operation mode provided before
the start of the standby mode.
(4) The MPU can access to the built-in display RAM.
When the RESET command is issued in the standby mode,
the sleep mode is set.
When the LCD drive voltage level is given by an external
resistive driver, the current of this resistor must be cut so that it
may be fixed to floating or V DD level, prior to or concurrently
with causing the S1D15300 series to go to the sleep mode or
standby mode.
5–22
EPSON
A0
0
E R/W
RD WR D7
1
0
1
D6
D5
D4
D3
D2
D1
D0
1
1
1
∗
∗
∗
∗
* : Invalid bit
Cautions: The S1D15300 Series holds an operation status
specified by each command. However, the internal
operation status may be changed by a high level of
ambient noise. It must be considered to suppress the
noise on the its package and system or to prevent an
ambient noise insertion. To prevent a spike noise, a
built-in software for periodical status refreshment is
recommended to use.
The test command can be inserted in an unexpected
place. Therefore, it is recommended to enter the test
mode reset command F0h during the refresh
sequence.
Rev.1.4
S1D15300 Series
Command
A0
RD WR
D7
D6
Code
D5 D4
1
0
D3
D2
D1
D0
1
1
1
0
1
Function
(1) Display ON/OFF
0
1
0
1
0
(2) Initial Display Line
0
1
0
0
1
(3) Set Page Address
0
1
0
1
0
1
1
Page address
(4) Set Column Address
4 higher bits
0
1
0
0
0
0
1
Higher column
address
Sets 4 higher bits of column
address of display RAM in register
(4) Set Column Address
4 lower bits
0
1
0
0
0
0
0
Lower column
address
Sets 4 lower bits of column
address of display RAM in register
(5) Read Status
0
0
1
Status
(6) Write Display Data
1
1
0
Write data
Writes data in display RAM.
(7) Read Display Data
1
0
1
Read data
Reads data from display RAM.
(8) ADC Select
0
1
0
1
0
1
0
0
0
0
0
1
Sets normal relationship between
RAM column address and segment driver when low, but reverses the relationship when high.
(9) Normal/Reverse Display 0
1
0
1
0
1
0
0
1
1
0
1
Normal indication when low, but
full indication when high.
(10) Entire Display ON/OFF 0
1
0
1
0
1
0
0
1
0
0
1
Selects normal display (0) or
Entire Display ON (1).
(11) Set LCD Bias
0
1
0
1
0
1
0
0
0
1
0
1
Sets LCD drive voltage bias ratio.
(12) Read-Modify-Write
0
1
0
1
1
1
0
0
0
0
0
Increments Column Address
counter during each write when
high and during each read when
low.
(13) End
0
1
0
1
1
1
0
1
1
1
0
Releases the Read-Modify-Write.
(14) Reset
0
1
0
1
1
1
0
0
0
1
0
Resets internal functions.
(15) Set Output Status
Register
0
1
0
1
1
0
0
0
1
*
*
*
Selects COM output scan
direction. * Invalid data
(16) Set Power Control
0
1
0
0
0
1
0
1
(17) Set Electronic Control
Register
0
1
0
1
0
0
(18) Set Standby
0
1
0
1
0
1
0
1
1
0
0
1
Selects standby status.
0: OFF 1: ON
(19) Power Save
–
–
–
–
–
–
–
–
–
–
–
Compound command of display
OFF and entire display ON
(20) Test Command
0
1
0
1
1
1
1
*
*
*
*
IC Test command. Do not use!
(21) Test Mode Reset
0
1
0
1
1
1
1
0
0
0
0
Command of test mode reset
Start display address
0
0
Turns on LCD panel when goes
high, and turns off when goes low.
Specifies RAM display line for
COM0.
0
Sets the display RAM page in
Page Address register.
0
Operation
status
Reads the status information.
Selects the power circuit
operation mode.
Electronic control value
Sets V5 output voltage to Electronic Control register.
Note: Do not use any other command, or the system malfunction may result.
Rev.1.4
EPSON
5–23
S1D15300 Series
8. COMMAND SETTING (For Refrence)
Instruction Setup Examples
Initial setup
Note: As power is turned on, this IC outputs non-LCD-drive potentials V2 – V6 from SEG terminal (generates output for driving the LCD)
and V1 – V 4 from COM terminal (also used for generating the LCD drive output). If charge remains on the smoothing capacitor being
inserted between the above LCD driving terminals, the display screen can be blacked out momentarily. In order to avoid this trouble,
it is recommended to employ the following powering on procedure.
• When the built-in power is used immediately after the main power is turned on:
Turn on VDD and VSS power while maintaining
RES terminal at LOW.
Wait until the power supply is stabilized.
Cancel the reset mode (RES terminal = HIGH).
Turn on the initial setup mode (Default). *1
Function select through the commands (user setup).
LCD bias set *2
ADC select *3
Common output mode select *4
Operations ranging from powering on
through the power control set must be
completed within 5 ms.
Function select through the command (user setup).
Electronic volume *5
Function select through the command (user setup)
Power control set *6
Initial setup is complete
* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned.
Notes: *1:
*2:
*3:
*4:
*5:
Refer to the “Reset Circuit” in the Function Description.
Refer to the “LCD Bias Set” in the Command Description (11).
Refer to the “ADC Select” in the Command Description (8).
Refer to the “Output State Register Set” in the Command Description (15)
Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in the Command Description
(17).
*6: Refer to the “Supply Circuit” in the Function Description and the “Power Control Set” in the Command Description (16).
5–24
EPSON
Rev.1.4
S1D15300 Series
• When the built-in power supply is not used immediately after the main power is turned on:
Turn VDD and VSS power on with
RES terminal being set to LOW.
Wait until the power supply is stabilized.
Cancel the reset mode (RES terminal = HIGH)
Turn on the initial setup mode (Default) *1
The power save mode must be turned
on within 5 ms from powering on.
Turn on the power save mode (multiple commands) *7
Function select through the commands (user setup)
LCD bias set *2
ADC select *3
Common output mode select *4
Function select through the command (user setup)
Electronic volume *5
Turn off the power save mode *6
Function select through the command (user setup)
Power control set * 7
Operations ranging from turning off of
the power save mode through the
power control set must be completed
within 5 ms.
Initial setup is complete
* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned. Check them on the actual system.
Notes: *1:
*2:
*3:
*4:
*5:
Refer to the “Reset Circuit” in the Function Description.
Refer to the “LCD Bias Set” in the Command Description (11).
Refer to the “ADC Select” in the Command Description (8).
Refer to the “Output State Register Set” in the Command Description (15)
Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in the Command Description
(17).
*6: Refer to the “Supply Circuit” in the Function Description and the “Power Control Set” in the Command Description (16).
*7: You can select either the sleep mode or standby mode for the power save mode. Refer to the “Power Save (Multiple Commands)”
in the Command Description (19).
Rev.1.4
EPSON
5–25
S1D15300 Series
• Data Display
Initial setup is complete
Function select through the commands (user setup)
Display start line set *8
Page address set *9
Column address set *10
Function select through the command (user setup)
Display data write *11
Function select through the command (user setup)
Display ON/OFF *12
Data display is complete
Notes: *8: Refer to the “Display Line Set” in the Command Description (2).
*9: Refer to the “Page Address Set” in the Command Description (3).
*10: Refer to the “Column Address Set” in the Command Description (4).
*11: Refer to the “Display Data Write” in the Command Description (6).
*12: Refer to the “Display ON/OFF” in the Command Description (1). It is recommended to avoid the all-white-display of the display
start data.
• Powering Off *13
Any state
Function select through the command (user setup)
Power save *14
Turn VDD and VSS power off
The time spent for the operations ranging from power
save through powering off (VDD – VSS = 2.4V) (tH)
must be longer than the time required for V5 to V1 go
under the LCD panel threshold voltage (normally 1V).
* tH is determined by time constant of the external
resisters Ra and Rb (for adjusting voltages V5 to V1)
and the smoothing capacitor C2.
* It is recommended to cut tH shorter by connecting a
resistor between VDD and V5.
Notes: *13: This IC functions as the logic circuit of the power supplies VDD – V SS, and used for controlling the driver of LCD power supplies
VDD – V5. Thus, if power supplies V DD – VSS are turned off while voltage is still present on LCD power supplies VDD – V5, drivers
(COM and SEG) may output uncontrolled voltage. Therefore, you are required to observe the following powering off procedure:
Turn the built-in power supply off, then turn off the IC power supplies (VDD – VSS) only after making sure that potential of V5 –
V1 is below the LCD panel threshold voltage level. Refer to the “Supply Circuit” in the Function Description.
*14: When the power save command is entered, you must not implement reset from RES terminal until VDD – VSS power are turned off.
Refer to the “Power Save” in the Command Description.
• Refresh
It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise.
Refresh sequence
Cancel the test mode *15
Set every command according to the state being selected
(including setup of the default state).
Refresh the DDRAM.
Notes: *15: Refer to the “Test Mode Cancellation” in the Command Description (21).
5–26
EPSON
Rev.1.4
S1D15300 Series
9. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
–0.3 to +7.0
Supply voltage range
Triple boosting
VDD
–0.3 to +6.0
Quadruple boosting
V
–0.3 to +4.5
Supply voltage range (1) (VDD Level)
V5, VOUT
–18.0 to +0.3
V
Supply voltage range (2) (VDD Level)
V1, V2, V3, V4
V5 to +0.3
V
Input voltage range
VIN
–0.3 to VDD+0.3
V
Output voltage range
VO
–0.3 to VDD+0.3
V
TOPR
–40 to +85
°C
Operating temperature range
TCP
–55 to +100
Storage temperature range
TSTR
Bear chip
–55 to +125
VCC
VDD
GND
VSS
°C
VDD
V1 to V4
V5 , VOUT
(System)
(S1D15300 series)
Notes: 1. V1 to V5, VOUT, voltages are based on VDD=0 V.
2. Voltages VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be satisfied.
3. If an LSI exceeds its absolute maximum rating, it may be damaged permanently. It is desirable to use it under electrical characteristics
conditions during general operation. Otherwise, an LSI malfunction or reduced LSI reliability may result.
Rev.1.4
EPSON
5–27
S1D15300 Series
10. ELECTRICAL CHARACTERISTICS
DC Characteristics
VSS = 0 V, VDD = 5 V ±10%, Ta = –40 to +85°C unless otherwise noted.
Item
Power voltage (1)
Symbol
Recommended
Operation
Operational
Condition
VDD
Min.
Typ.
Max.
Unit
Pin used
4.5
5.0
5.5
V
VSS *1
2.4
–
6.0
Operating voltage
Operational
V5
VDD level (VDD = 0 V)
–16.0
–
–4.5
V
V5
(2)
Operational
V1, V2
VDD level (VDD = 0 V)
0.4 × V5
–
VDD
V
V1, V2
Operational
V3, V4
VDD level (VDD = 0 V)
V5
–
0.6 × V5
V
V3, V4
0.7 × VDD
–
VDD
V
0.8 × VDD
–
VDD
VSS
–
0.3 × VDD
VDD = 2.7 V
VSS
–
0.2 × VDD
IOH = –1 mA
0.8 × VDD
–
VDD
VDD = 2.7 V, IOH = –0.5 mA
0.8 × VDD
–
VDD
IOL = 1 mA
VSS
–
0.2 × VDD
VDD = 2.7 V, IOL = 0.5 mA
VSS
–
0.2 × VDD
*5
0.85 × VDD
–
VDD
*4
0.8 × VDD
–
VDD
*4
VSS
–
0.15 × VDD
*4
VDD = 2.7 V
VSS
–
0.2 × VDD
*4
VIN = VDD or VSS
–1.0
–
1.0
µA
–3.0
–
3.0
µA
HIGH-level input voltage
VIHC
VDD = 2.7 V
CMOS
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Schmitt
HIGH-level input voltage
VILC
VOHC
VOLC
VIHS
VDD = 2.7 V
LOW-level input voltage
VILS
Input leakage current
ILI
Output leakage current
ILO
LCD driver ON resistance
RON
Ta = 25°C
V5 = –14.0 V
–
2.0
3.0
VDD level
V5 = –8.0 V
–
3.0
4.5
*2
*3
*3
V
*3
*3
V
*5
*5
V
kΩ
*5
*6
*7
SEG n
COM n
*8
ISSQ
VIN = VDD or VSS
–
0.01
5.0
µA
VSS
I5Q
V5 = –18.0 V (VDD level)
–
0.01
15.0
µA
V5
Input pin capacity
CIN
Ta = 25°C, f = 1 MHz
–
5.0
8.0
pF
*3 *4
Oscillation frequency
fOSC
Ta = 25°C
VDD = 5 V
18
22
26
kHz
*9
VDD = 2.7 V
18
22
26
Min.
Typ.
Max.
Unit
Triple boosting
2.4
–
6.0
V
Quadruple boosting
2.4
–
4.5
Static current consumption
Item
Built-in power circuit
Input voltage
Symbol
VDD
Condition
Pin used
*10
Booster output voltage
VOUT
Triple voltage conversion (VDD level)
–18.0
–
–
V
VOUT
Voltage regulator operation
VOUT
(VDD level)
–18.0
–
–6.0
V
VOUT
V5
(VDD level)
–18.0
–
–6.0
V
–16.0
–
–4.5
V
–2.75
–2.55
–2.35
V
voltage
Voltage follower operation
voltage
Reference voltage
VREG
Ta = 25°C (VDD level)
*11
For the mark *, refer to P. 1–25
5–28
EPSON
Rev.1.4
S1D15300 Series
Dynamic current consumption (1) when the built-in power supply is OFF
Ta = 25°C
Min.
Typ.
Max.
S1D15300/
Item
Symbol
VDD = 5.0V, V5 – VDD = –8.0 V
—
24
40
S1D15305
VDD = 3.0V, V5 – VDD = –8.0 V
—
22
35
S1D15301
VDD = 5.0V, V5 – VDD = –11.0 V
—
40
65
IDD
VDD = 3.0V, V5 – VDD = –11.0 V
—
36
60
(1)
VDD = 5.0V, V5 – VDD = –11.0 V
—
39
65
VDD = 3.0V, V5 – VDD = –11.0 V
—
32
55
S1D15303
VDD = 3.0V, V5 – VDD = –5.0 V
—
20
35
S1D15304
VDD = 3.0V, V5 – VDD = –5.0 V
—
20
35
Condition
Min.
Typ.
Max.
S1D15300/
VDD = 5.0V, V5 – VDD = –8.0 V, dual boosting
—
41
70
S1D15305
VDD = 3.0V, V5 – VDD = –8.0 V, triple boosting
—
48
80
S1D15301
VDD = 5.0V, V5 – VDD = –11.0 V, triple boosting
—
96
160
IDD
VDD = 3.0V, V 5 – VDD = –11.0 V, quadruple boosting
—
118
190
(1)
VDD = 5.0V, V5 – VDD = –11.0 V, triple boosting
—
95
160
VDD = 3.0V, V 5 – VDD = –11.0 V, quadruple boosting
—
114
190
S1D15303
VDD = 3.0V, V5 – VDD = –5.0 V, dual boosting
—
30
50
S1D15304
VDD = 3.0V, V5 – VDD = –5.0 V, dual boosting
—
32
55
S1D15302
Condition
Unit
Note
µA
*12
Dynamic current consumption (2) when the built-in power supply is ON
Item
Symbol
S1D15302
Ta = 25°C
Unit
Note
µA
*13
Current consumption during Power Save mode
VSS = 0 V, VDD = 2.7 to 5.5 V Ta=25°C
Item
Symbol
Condition
Min.
Typ.
Max.
During sleep
IDDS1
S1D15300, S1D15301, S1D15302
—
0.01
1
During standby
IDDS2
S1D15300, S1D15301, S1D15302
—
10
20
Unit
Note
µA
Typical current consumption characteristics (reference
data)
• Dynamic current consumption (1) when LCD external
power mode lamp is ON
80
(uA)
Condition: The built-in power supply is
OFF and an external power
supply is used.
S1D15300/S1D15305 V5-VDD=–8.0V
S1D15301 V5-VDD=–11.0V
S1D15302 V5-VDD=–11.0V
S1D15303 V5-VDD=–6.0V
S1D15304 V5-VDD=–6.0V
Ta=25°C
60
IDD (1)
(ISS+15)
S1D15301, S1D15302
40
S1D15300/S1D15305
Remarks: ✽12
20
S1D15303, S1D15304
0
1
2
3
4
5
6
7
(V)
VDD
Rev.1.4
EPSON
5–29
S1D15300 Series
• Dynamic current consumption (2) when the LCD built-in
power circuit lamp is ON
200
(uA)
Condition: The built-in power circuit is ON.
S1D15300/S1D15305: V5-VDD=–8.0 V,
triple boosting
S1D15301: V5-VDD=–11.0 V,
quadruple boosting
S1D15302: V5-VDD=–11.0 V,
quadruple boosting
S1D15303: V5-VDD=–5.0 V,
dual boosting
S1D15304: V5-VDD=–5.0 V,
dual boosting
Ta=25°C
150
IDD (1)
S1D15301, S1D15302
100
S1D15300/S1D15305
50
S1D15303, S1D15304
Remarks: ✽13
0
1
2
3
4
5
6
7 (V)
VDD
*1
Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from
the microprocessor.
*2 VDD and V5 operating voltage range. (Refer to Fig. 10.)
The operating voltage range applies if an external power supply is used.
*3 A0, D0 - D5, D6, D7 (SI), RD (E), WR (R/W), CS1, CS2, FR, M/S, C86, P/S and DOF pins
*4 CL, SCL (D6) and RES pins
*5 D0 - D5, D6, D7 (SI), FR, FRS, DYO, DOF and CL pins
*6 A0, RD (E), WR (R/W), CS1, CS2, M/S, RES, C86 and P/S pins
*7 Applies when the D0 - D7, FR, CL, DYO and DOF pins are in high impedance,
*8 Resistance value when 0.1 V is applied between the output pin SEGn or COMn and each power supply pin (V1, V2, V3, V4).
This is specified in the operating voltage (2) range.
R ON = 0.1 V/∆I (∆I: Current flowing when 0.1 V is applied in the ON status.)
*9 For the relationship between oscillation frequency and frame frequency, refer to Fig. 9.
*10 For triple or quadruple boosting using the on-chip power useing the primary-side power supply VDD must be used within the input voltage
range.
*11 The voltage regulator adjusts V5 within the voltage follower operating voltage range.
*12, *13 Current that each IC unit consumes. It does not include the current of the LCD panel capacity, wiring capacity, etc.
This is current consumption under the conditions of display data = checker, display ON, S1D15300 = 1/33 duty (1/6 Bias), and S1D15301
and S1D15302 = 1/65 duty. (1/8 Bias)
*12 Applies to the case where the on-chip oscillator circuit is used and no access is made from the microprocessor.
*13 Applies to the case where the on-chip oscillator circuit and the on-chip power circuit are used and no access is made from the
microprocessor.
The current flowing through voltage regulation resistors (R1, R2 and R3) is not included.
The current consumption, when the on-chip voltage booster is used, is for the power supply VDD.
• Relationship between oscillation frequency and frame frequency
The relationship between oscillation frequency fOSC and LCD frame frequency, fF can be obtained by the following expression.
Duty
f CL
fF
S1D15300
1/33
f OSC/8
f OSC/(8*33)
S1D15301
f OSC/(4*65)
1/65
f OSC/4
S1D15302
S1D15303
1/17
f OSC/8
f OSC/(8*17)
S1D15304
1/9
f OSC/8
f OSC/(8*9)
S1D15305
1/35
f OSC/8
f OSC/(8*35)
(fF does not indicate the FR signal cycle but the AC cycle.)
Fig. 9
Relationship between clock (fCL) and frame frequency fF
5–30
EPSON
Rev.1.4
S1D15300 Series
• VSS and V5 operating voltage range
-20
-16
[V]
-15
V5-VDD
-11
Operating
range
-10
-5
2.4
0
3.5
2
4
VDD
6
8
[V]
Fig 10
• Current consumption at access IDD (2) - Microprocessor access cycle
This indicates current consumption when data is always
written on the checker pattern at fcyc. When no access
is made, only IDD (1) occurs.
10
[mA]
1
S1D15301,
S1D15302
IDD (2)
0.1
0.01
0
S1D15300,
S1D15303,
S1D15304,
S1D15305
0.01
0.1
1
fcyc [MHz]
Condition: S1D15300/S1D15305 V5-VDD=-8.0V,
triple boosting
S1D15301 V5-VDD=-11.0V,
quadruple boosting
S1D15302 V5-VDD=-11.0V,
quadruple boosting
10
S1D15303 V5-VDD=-6.0V,
dual boosting
S1D15304 V5-VDD=-6.0V,
dual boosting
Ta = 25¡C
Fig. 11
Rev.1.4
EPSON
5–31
S1D15300 Series
AC Characteristics
(1) System buses
Read/write characteristics I (8080-series microprocessor)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
tCCLW
tCCLR
WR,RD
tDS8
tDH8
tCCHW
tCCHR
D0~D7
(WRITE)
tACC8
tCH8
D0~D7
(READ)
VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Address hold time
Address setup time
Signal
A0
System cycle time
Control LOW pulse width(WR)
Control LOW pulse width(RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
Data setup time
Data hold time
RD access time
Output disable time
D0 to D7
Symbol
tAHIGH8
tAW8
tCYC8
tCCLOWW
tCCLOWR
tCCHIGHW
tCCHIGHR
tDS8
tDHIGH8
tACC8
tCHIGH8
Condition
CL=100pF
Min.
Max.
Unit
10
10
–
–
ns
ns
166
–
ns
30
70
100
70
–
–
–
–
ns
ns
ns
ns
20
10
–
–
ns
ns
–
10
70
50
ns
ns
VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Address hold time
Address setup time
Signal
Symbol
A0
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tCH8
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
Data setup time
Data hold time
RD access time
Output disable time
D0 to D7
Condition
CL=100pF
Min.
Max.
Unit
19
15
–
–
ns
ns
450
–
ns
60
140
200
140
–
–
–
–
ns
ns
ns
ns
40
15
–
–
ns
ns
–
10
140
100
ns
ns
Notes: 1. The input signal rise/fall time (tr, tf) is specified at 15 ns or less.
When system cycle time is used at a high speed, it is specified by t r + tf ≤ (tCYC8 - tCCLW ) or
tr + tf ≤ (tCYC8 - tCCLR - tCCHR).
2. Every timing is specified on the basis of 20% and 80% of VDD .
3. t EWHR and tEWHW are specified by the overlap period in which CS1 is “0” (CS2 = “1”) and WR and RD are “0”.
4. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to
-4.5 V by 30% before the operation.
5–32
EPSON
Rev.1.4
S1D15300 Series
(2) System buses
Read/write characteristics II (6800-series microprocessor)
A0
R/W
tAH6
tAW6
CS1
(CS2="1")
tEWHW tEWHR
tCYC6
tEWLW tEWLR
E
tDS6
tDH6
D0~D7
(WR1TE)
tACC6
D0~D7
(READ)
tOH6
VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
A0
W/R
D0 to D7
Output disable time
Access time
Enable
READ
E
LOW pulse width WRITE
Enable
READ
E
HIGH pulse width WRITE
Symbol
Condition
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
tEWHR
tEWHW
tEWLR
tEWLW
CL=100pF
Symbol
Condition
Min.
Max.
Unit
166
–
ns
10
10
–
–
ns
ns
20
10
–
–
ns
ns
10
–
50
70
ns
ns
70
–
ns
30
–
ns
70
–
ns
100
–
ns
VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Signal
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
A0
R/W
D0 to D7
Output disable time
Access time
Enable
READ
E
LOW pulse width WRITE
Enable
READ
HIGH pulse width WRITE
E
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
tEWHR
tEWHW
tEWLR
tEWLW
CL=100pF
Min.
Max.
Unit
450
–
ns
15
19
–
–
ns
ns
40
15
–
–
ns
ns
10
–
100
140
ns
ns
140
–
ns
60
–
ns
140
–
ns
200
–
ns
Notes: 1. The input rise/fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is used at a high speed, it is specified by
tr + tf ≤ (tCYC6 - tEWLW - tEWHW) or tr + tf ≤ (tCYC6 - t EWLR - tEWHR).
2. Every timing is specified on the basis of 20% and 80% of VDD.
3. tEWHR and tEWHW are specified by the overlap period in which CS1 is “0” (CS2 = “1”) and E is “1”.
4. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to
-4.5 V by 30% before the operation.
Rev.1.4
EPSON
5–33
S1D15300 Series
(3) Serial interface
tCSS
CS1
(CS2="1")
tCSH
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tf
tSHW
tr
tSDH
tSDS
SI
VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
Symbol
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
Address setup time
Address hold time
A0
Data setup time
Data hold time
SI
CS serial clock time
CS
Condition
Min.
Max.
Unit
250
100
75
–
–
–
ns
ns
ns
50
200
–
–
ns
ns
50
50
–
–
ns
ns
30
100
–
–
ns
VDD = 2.7 to 4.5V, Ta = –40 to +85°C
Parameter
Signal
Symbol
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
Address setup time
Address hold time
A0
Data setup time
Data hold time
SI
CS serial clock time
CS
Condition
Min.
Max.
Unit
500
200
150
–
–
–
ns
ns
ns
100
400
–
–
ns
ns
100
100
–
–
ns
ns
60
200
–
–
ns
Notes: 1. The input signal rise and fall times must be within 15 nanoseconds.
2. All signal timings are limited based on 20% and 80% of VDD voltage.
3. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to
-4.5 V by 30% before the operation.
5–34
EPSON
Rev.1.4
S1D15300 Series
(4) Display control timing
CL
(OUT)
tDFR
FR
tDOH
tDOL
DYO
VDD = 5.0 V ±10%, Ta = –40 to +85°C
Output timing
Parameter
FR delay time
DYO HIGH delay time
Signal
Symbol
Condition
Min.
Typ.
Max.
Unit
FR
tDFR
CL = 50 pF
–
10
40
ns
DYO
tDOH
–
40
100
ns
tDOL
–
40
100
ns
DYO LOW delay time
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Output timing
Parameter
FR delay time
DYO HIGH delay time
Signal
Symbol
Condition
Min.
Typ.
Max.
Unit
FR
tDFR
CL = 50 pF
–
15
80
ns
DYO
tDOH
–
70
200
ns
tDOL
–
70
200
ns
DYO LOW delay time
Notes: 1. The otput timing is valid in master mode.
2. Every timing is specified on the basis of 20% and 80% of VDD.
(5) Reset timing
t RW
RES
tR
Internal circuit
status
During reset
End of reset
VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
Reset time
Reset LOW pulse width
RES
Symbol
Condition
Min.
Typ.
Max.
Unit
tR
0.5
–
–
µs
tRW
0.5
–
–
µs
VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Signal
Reset time
Reset LOW pulse width
RES
Symbol
Condition
Min.
Typ.
Max.
Unit
tR
1.0
–
–
µs
tRW
1.0
–
–
µs
Note: The reset timing is specified on the basis of 20% and 80% of V DD.
Rev.1.4
EPSON
5–35
S1D15300 Series
11. MPU INTERFACE (For Reference)
The S1D15300 series chips can directly connect to 8080 and 6800-series microprocessors. Also, serial interfacing requires less signal lines
between them. When multiple chips are used in the S1D15300 series they can be connected to the microprocessor and one of them can be selected
by Chip Select.
8080-series microprocessors
VDD
VCC
A0
A0
VDD
C86
A1 to A7
IORQ
Decoder
MPU
CS1
CS2
S1D15300
D0 to D7
RD
WR
VSS
RES
D0 to D7
RD
WR
RES
GND
VSS
VDD
P/S
RESET
VSS
6800-series microprocessors
VDD
VCC
A0
A0
VDD
VDD
C86
A1 to A15
VMA
Decoder
MPU
CS1
CS2
S1D15300
VDD
D0 to D7
E
R/W
VSS
RES
D0 to D7
E
R/W
RES
GND
P/S
RESET
VSS
Serial interface
VDD
VCC
A0
A0
VDD
C86
A1 to A7
Decoder
MPU
GND
CS1
CS2
Port 1
Port 2
SI
SCL
RES
RES
S1D15300
VDD
or GND
P/S
VSS
RESET
VSS
5–36
EPSON
Rev.1.4
S1D15300 Series
12. CONNECTION BETWEEN LCD DRIVERS
The LCD panel display area can easily be expanded by use of multiple S1D15300 series chips. The S1D15300 series can also be connected to
the common driver (S1D16305).
S1D15301 to S1D16305 (S1D16305)
VDD
S11D16305
DOFF
DIO
FR
S1D15301
(master)
FR
YSCL
CL
DYO
M/S
DOF
S1D15300 to S1D15301
VDD
S1D15300
(master)
M/S
CL
DYO
FR
S1D15300
(slave)
FR
DOF
CL
DYO
M/S
VSS
DOF
S1D15302 to S1D15302
VDD
S1D15302
(master)
M/S
CL
Rev.1.4
DYO
FR
S1D15302
(slave)
FR
DOF
CL
EPSON
DYO
M/S
DOF
VSS
5–37
S1D15300 Series
S1D15300 : 100×33dot
SEG (100)
SEG (100)
S1D15300D00A*
<Master>
S1D15300D10A*
<Master>
COM (33)
COM (17)
S1D16700
COM (16)
COM(65)
132×65 dot
DOFF DIO YSCL FR
SEG(132)
FR
CL
DYO
DOF
VDD
M/S
S1D15301
S1D15302 : 200×65 dot
SEG(100)
SEG(100)
S1D15302
<Master>
COM(33)
VDD
5–38
M/S
FR
DOF
FR
DOF
CL
CL
EPSON
S1D15302
<Slave>
COM(32)
M/S
Rev.1.4
(Mold, marking area)
(Mold, marking area)
Rev.1.4
EPSON
Output terminal pattern shape
(Mold, marking area)
IC center
in the product.
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 35µm
• Sn plating
• Product pitch: 91P (42.75mm)
• Solder resist positional tolerance: ±0.3
Note 1) Regist position tolerance = 0.3
Note 2) Product pitch: 9IP (42.75mm)
Note 3) Lot No. is to be indicated in columns
(Mold, marking area)
S1D15300 Series
Dimensional outline drawing of the flexible substrate
(an example) The dimensions are subject to change without prior notice.
5–39
6. S1D15400 Series
Rev. 1.0
Contents
1. DESCRIPTION ................................................................................................................................................ 6-1
2. FEATURES ...................................................................................................................................................... 6-1
3. BLOCK DIAGRAM ........................................................................................................................................... 6-2
4. PIN LAYOUT ................................................................................................................................................... 6-3
5. PAD ................................................................................................................................................................. 6-5
6. PIN DESCRIPTION ......................................................................................................................................... 6-6
7. BLOCK DESCRIPTION ................................................................................................................................... 6-8
8. COMMANDS .................................................................................................................................................6-13
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 6-19
10. DC CHARACTERISTICS ...............................................................................................................................6-20
11. AC CHARACTERISTICS ...............................................................................................................................6-22
12. MPU INTERFACE CONFIGURATION ......................................................................................................... 6-26
13. LCD DRIVE INTERFACE CONFIGURATION ............................................................................................... 6-27
14. PANEL INTERFACE CONFIGURATION ...................................................................................................... 6-28
–i–
Rev. 1.0
S1D15400 Series
1. DESCRIPTION
2. FEATURES
The S1D15400 is a segment LCD driver intended for use
with medium size LCD panels.
The driver generates LCD drive signals from data supplied by an MPU over a high speed, 8-bit bus, 4-bit bus
and stored in its internal display RAM.
The S1D15400 incorporates innovative circuit design
strategies, to achieve very low power consumption at a
wide range of operating voltages, and a rich command
set. These features give the designer a flexible means of
implementing small to medium size LCD displays for
compact, low power systems.
• Fast 8-bit MPU interface compatible with 80- and 68family microcomputers
• Rich command set
• 73 segment drive outputs
• 4 common drive outputs
• Selectable 1/3 or 1/4 duty cycle
• Low power consumption -70 µW maximum
• Wide range of supply voltages, VSS
–2.4 V to –7.0 V
• Implemented in CMOS
• Choice of packages
— S1D15400F00A* : 100-pin QFP
— S1D15400D00A* : Al-pad chip
— S1D15400D00B* : Au-bump chip
Rev. 1.0
EPSON
Clock Source
fCL
Frame Frequency
External clock
4 kHz
85/64 Hz
Internal osc.
18 kHz
375/281 Hz
6–1
S1D15400 Series
V SS
V DD
SG0~SG72
V 1 ,V2 ,V3
CM0~CM3
M/S
3. BLOCK DIAGRAM
LCD driver circuit
Internal bus
Display data RAM
2560bit
I/O buffer
Display data latch circuit
Line address decoder
Line address counter
Display start line register
Common counter
OSC1
FR
Display
timing
generator
Column address counter
Column address register
Command
decoder
Status
Bas holder
OSC2
LOW address
register
Column address decoder
6–2
EPSON
RES
(RD)(WR)
E,R/W
A 0 ,CS
D 0 ~D 7
MPU Interface
Rev. 1.0
S1D15400 Series
4. PIN LAYOUT
For chip pad locations see section 4.3, Mechanical Specifications.
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Name
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
Number
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
Number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
A0
OSC1
OSC2
Number
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
E (RD)
R/W (WR)
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
RES
FR
V3
CS
NC
M/S
V2
V1
COM0
COM1
COM2
COM3
SEG72
Pin
Duty
Rev. 1.0
98
99
1/4
COM2
COM3
1/3
NC
COM2
EPSON
6–3
S1D15400 Series
Mechanical Specifications
S1D15400F00A* Flat Pack
Dimensions: inches (mm)
1.008 ± 0.016
(25.6 ± 0.4)
0.787 ± 0.004 (20 ± 0.1)
80
51
81
Index
31
0.106 ± 0.004
(2.7 ± 0.1)
0.006 ± 0.002
(0.15 ± 0.05)
100
0.772 ± 0.016 (19.6 ± 0.4)
0.551 ± 0.004
(14 ± 0.1)
50
1
0.026 ± 0.004
(0.65 ± 0.1)
30
0.012 ± 0.004
(0.30 ± 0.1)
0~12°
0.110
(2.8)
6–4
EPSON
0.059 ± 0
.012
(1.5 ± 0.3
)
Rev. 1.0
S1D15400 Series
5. PAD
100
1
95
90
85
80
S1D15400D Pad Layout
5
Al-pad chip
• Die size: 4.80 mm × 7.04 mm × 0.525 mm
• Pad size: 100 × 100 µm
Au-bump chip
• Minimum bump pitch: 199 µm
• Bump height: 20 µm +10/–5 µm
• Bump size: 132 × 111 µm ±20 µm
75
10
70
15
7.04 mm
65
20
60
25
55
D1540D0A
Y
30
35
40
45
50
4.80 mm
Pad Center Coordinates
Pad
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Rev. 1.0
Name
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
X
X
Y
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
504
704
903
1103
6507
6308
6108
5909
5709
5510
5310
5111
4911
4712
4512
4169
3969
3770
3570
3371
3075
2876
2676
2477
2277
2078
1878
1679
1479
1280
1080
881
681
482
159
159
159
159
Pad
Number
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Name
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
EPSON
X
Y
1302
1502
1701
1901
2100
2300
2499
2699
2898
3098
3297
3497
3696
3896
4095
4295
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
482
681
881
1080
1280
1479
1679
1878
2078
2277
2477
2676
2876
3075
3275
3474
3674
3948
Pad
Number
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
—
—
Name
SEG3
SEG2
SEG1
SEG0
A0
OSC1
OSC2
E (RD)
R/W (WR)
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
RES
FR
V3
CS
NC
M/S
V2
V1
COM0
COM1
COM2
COM3
SEG72
—
—
X
Y
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4295
4095
3896
3696
3497
3297
3098
2898
2699
2499
2300
2100
1901
1701
1502
1302
1103
903
704
504
—
—
4148
4347
4547
4789
5048
5247
5447
5646
5846
6107
6307
6506
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
—
—
6–5
S1D15400 Series
6. PIN DESCRIPTION
Power Terminals
Terminal
name
Description
VDD
Connects to a +5-V power supply. Used in common with the MPU power terminal.
VSS
A 0-V terminal connected to the system GND.
V1,V2,V3
Multi-level power supply terminals for driving the LCD panel. Through divisions by
resistors or impedance conversion with an operational amplifier, they apply a voltage
determined by the LCD cells.Electric potential is determined depending on VDD. The
following relationship must be observed.
VDD ≥ V1 ≥ V2 ≥ V3
System Bus Connection Terminals
D7-D0
A0
RES
CS
E(RD)
R/W(WR)
6–6
Three-state I/O terminals
They comprise an 8-bit bi-directional data bus, and connected to an 8- or a 16-bit
standard MPU data bus.
Input terminal
Typically, the least significant bit of an MPU address bus is connected to discriminate
between data and commands.
0: Represents that D0-D7 output display control commands.
1: Represents that D0-D7 output data to be displayed.
Input
By setting RES to “
,” series 68 and 80 MPUs are initialized respectively. MPUs
are reset when a RES signal edge is detected. After initialization, the type of an interface
to the 68/80 MPUs is selected depending on the input level.
HIGH: Interface to series 68 MPU is selected.
LOW : Interface to series 80 MPU is selected.
Input activated at the LOW level
A terminal for chip selection signals. Typically, signals that result from decoding of
address bus signals are input.
<When series 68 MPU is connected>
Input activated at the HIGH level
An enable clock input terminal for the MPU.
<When series 80 MPU is connected>
Input activated at the LOW level
A terminal for RD signal from the MPU. The data bus on the S1D15400 outputs signals
while the RD signal is at the LOW level.
<When series 68 MPU is connected>
Input
An input terminal for read/write control signals.
R/W = HIGH: Read
R/W = LOW: Write
<When series 80 MPU is connected>
Input activated at the LOW level
A terminal for WR signal from the MPU. The signals on the data bus are fetched at a
rising edge of the WR signal.
EPSON
Rev. 1.0
S1D15400 Series
LCD Panel Driving Circuit Terminals
Terminal
name
OSC1
OSC2
FR
Description
A terminal for connecting a resistor for internal oscillation.
When M/S = 0, internal oscillation is prohibited, making OCS2 serve as a clock input
terminal in the opposite phase to OCS1. During the power-saving mode, oscillation and
clock input are prohibited, making OCS2 work as a high-impedance terminal. (See the
explanation of functions.)
Input/output terminal
An input/output terminal for AC control signals for the LCD panel.
M/S = 1: Output
M/S = 0: Input
SEG0-SEG72 Output terminal
Output for driving the LCD segments. Depending on the combination of the FR signal
and the contents of the display RAM, one of the VDD, V1, V 2, and V3 levels is selected.
1
0
FR
1
0
1
0
VDD
V2
V3
V1
DATA
OUTPUT
LEVEL
COM0-COM3
Output terminals (The function of the COM2 and COM3 output terminals changes
depending on the duty select command.)
They are common (LOW) output terminals for driving the LCD panel. Depending on the
combination of the FR signal and the output from the common counter, one of the V DD,
V1, V2, and V3 levels is selected.
1
0
FR
1
0
1
0
V3
V1
VDD
V2
COUNTER
OUTPUT
LEVEL
MS
Counter output
Output level
Input
A terminal that selects whether the MPU operates as a master or slave of the S1D15400.
It connects to VDD or VSS. This terminal determines the function of the FR, OSC1, and
OSC2 terminals.
M/S = VDD : Master
= VSS: Slave
M/S
VDD
VDD
FR
output
output
OSC1
Input
Input
OSC2 COMOutput
output
Enabled
output
Enabled
* When the FR signal is used to establish synchronization between the master and slave
ICs, both of them will output the same waveforms from the COM terminal.
Rev. 1.0
EPSON
6–7
S1D15400 Series
7. BLOCK DESCRIPTION
System Bus
Data transfer
The S1D15400 driver uses the A0, E (or RD) and R/W (or
WR) signals to transfer data between the system MPU
and internal registers. The combinations used are given
in the table below.
In order to match the timing requirements of the MPU
with those of the display data RAM and control registers,
all data is latched into and out of the driver. This
introduces a one cycle delay between a read request for
data and the data arriving. For example, when the MPU
executes a read cycle to access display RAM, the current
contents of the latch are placed on the system data bus
while the desired contents of the display RAM are moved
into the latch.
By using an MPU data bus I/O latch the display data
Common
A0
1
1
0
0
6–8
68 MPU
R/W
1
0
1
0
RAM access timing is determined by the driver cycle
time, tcyc, not by the RAM access time. In general this
strategy leads to faster data transfers between the driver
and the MPU.
If the MPU access frequency is likely to exceed 1/tcyc,
then the designer has the choice of inserting NOPs into
the access loop or polling the driver, by reading the busy
flag, to see if it will accept new data or instructions.
This means that a dummy read cycle has to be executed
at the start of every series of reads.
No dummy cycle is required at the start of a series of
writes as data is transferred automatically from the input
latch to its destination.
80 MPU
RD
0
1
0
1
WR
1
0
1
0
EPSON
Function
Read display data
Write display data
Read status
Write to internal register (command)
Rev. 1.0
S1D15400 Series
WRITE
WR
MPU
DATA
N
N+1
N+2
N+3
Latch
Internal
timing
N+1
N
N+2
N+3
WR
READ
WR
RD
MPU
DATA
N
N
n
Dummy read
Address set
at N
n+1
Data read
at N
Address set
at N + 1
WR
RD
Internal
timing
Column
N
address
Latch
N+1
N
n
N+2
n+1
n+2
Figure 1 Bus Buffer Delay
Busy flag
When the Busy flag is logical 1, the S1D15400 is executing its internal operations. Any command other than
Status Read is rejected during this time. The Busy flag
is output at pin D7 by the Status Read command. If an
Rev. 1.0
appropriate cycle time (tcyc) is given, this flag needs not
be checked at the beginning of each command and,
therefore, the MPU processing capacity can greatly be
EPSON
6–9
S1D15400 Series
Display Start Line and Line Count
Registers
The contents of this register form a pointer to a line of
data in display data RAM corresponding to the first line
of the display (COM0), and are set by the “Set Display
Start Line” command (see section 3).
The contents of the display start-line register are copied
into the line count register at the start of every frame, that
is on each edge of FR. The line count register is
incremented by the CL clock once for every display line,
thus generating a pointer to the current line of data in
display data RAM being transferred to the segment
driver ciruits.
Column Address Counter
Page Register
The page register is a 2-bit register which supplies the
page address (see figure 2) for MPU accesses to the
display data RAM. The contents of the Page Register are
set by the Set Page Register Command.
Display Data RAM
The column address counter is a 7-bit presettable counter
which supplies the column address (see figure 2) for
MPU accesses to the display data RAM. The counter is
incremented by one every time the driver receives a Read
6–10
or Write Display Data Command.
Addresses above 50 H are invalid, and the counter will
not increment past this valu. The contents of the column
address conter are set with the Set Column Address
command.
The display data RAM stores the LCD display data, on a
1-bit per pixel basis. The relation-ship between display
data, display address and the display is shown in figure
2.
EPSON
Rev. 1.0
S1D15400 Series
Non-display area
Line
address
Matching relation
Finish
Start
Start Line
(example)
Display area
Page address
00 H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
(Example of duty 1/4,Display start line set to 08H.)
0 Page
4D
4E
4F
D1,D2= 0,0
02
01
00
1 Page
77
78
79
0,1
49
2 Page
3 Page
06
0
1
2
3
Common
output
COM
COM
COM
COM
6–11
EPSON
Rev. 1.0
73
1,0
1,1
SEG
SEG 0
1
2
3
4
5
6
7
ADC
D0="1" D0="0"
4F H
00 H
01
4E
02
4D
4C
03
4B
04
05
4A
49
06
07
48
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Column address
Figure 2 Display Data RAM Addressing
S1D15400 Series
Common Timing Generator
Reset Circuit
This circuit generates common timing and frame (FR)
signals from the basic clock CL. The “Select Duty
Cycle” command selects a duty cycle of 1/3 or 1/4.
This circuit senses both the edge and the level of the
signal at the RES pin and uses this information to
•
1.
2.
3.
4.
5.
6.
7.
Initialization status
Display is off.
Display start line register is set to line 1.
Static drive is turned off.
Column address counter is set to address 0.
Page address register is set to page 0.
1/4 duty is selected.
Forward ADC is selected (ADC command D0 is 0 and
ADC status flag is 1).
8. Read-modify-write is turned off.
Display Data Latch Circuit
This latch stores one line of display data for use by the
LCD driver interface circuitry. The output of this latch
is controlled by the “Display ON/OFF” and “Static
Driver ON/OFF” commands.
LCD Drive Circuit
The LCD driver circuitry generates the 77 4-level signals
used to drive the LCD panel, using output from the
display data latch and the common timing generator
circuitry.
The input signal level at RES pin is sensed, and an MPU
interface mode is selected as shown on Table 1. For the
80-series MPU, the RES input is passed through the
inverter and the active high reset signal must be entered.
For the 68-series MPU, the active low reset signal must
be entered.
Display Timing Generator
This circuit generates the internal display timing signal
using the basic clock OSC1, and the frame signal, FR.
FR is used to generate the dual frame AC-drive waveform (type B drive) and to lock the line counter and
common timing generator to the system frame rate.
OSC1 is used to lock the line counter to the system line
scan rate.
When the Reset command is issued, initialization items
2, 4 and 5 above are executed.
As shown for the MPU interface (reference example), the
RES pin must be connected to the Reset pin and reset at
the same time as the MPU initialization.
Oscillation Circuit
The oscillator is a low power RC oscillator whose frequency of oscillation is determined by the value of the
feedback resistor Rf or an externally generated 50% duty
cycle clock input via OSC1. If a slave S1D15400 is used,
its OSC2 input is connected to the OSC2 output of the
master driver.
• Oscillator mounted
V DD
If the MPU is not initialized by the use of RES pin during
power-on, an unrecoverable MPU failure may occur.
Master
Slave
M/S
M/S
OSC1
OSC2
OSC1
VSS
OSC2
Rf
*2
Open
*1
*1 Oscillating freguency shifts to low freguency side
when parasitic capacity gets larger, So Rf should be
smaller than the regular value.
*2 CMOS buffer is needed when connecting to more
than two slave LSI.
• External clock operation
V DD
S1D15400
Clock originating
(MPU)
M/S
CL
OSC1
OSC2
Slave
OSC2
6–12
EPSON
Rev. 1.0
S1D15400 Series
8. COMMANDS
Table 3
Command
Code
A0
RD WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0/1
(1)Display On/OFF
0
1
0
1
0
1
(2)Display start line
0
1
0
1
1
0Display start address (0 to 31)
(3)Set page address
0
1
0
1
0
1
0
1
0
0
(4)Set column
(segment) address
1
1
0
Function
Turns display on or off.
1: ON, 0: OFF
*
Specifies RAM line corresponding to top
line of display.
Page (0 to 3)
Sets display RAM page in page address
register.
Sets display RAM column address in
column address register.
Column address (0 to 72)
Reads the following status:
(5)Read status
0
0
1
Busy
ADC ON/OFF Reset
0
0
0
BUSY
1: busy
0: Ready
ADC
1: Forward
0: Reverse
ON/OFF
1: Display off
RESET
0: Display on
1: being reset
0
0: Normal
Writes data from data bus into display RAM.
(6)Write display data
1
1
0
Write data
(7)Read display data
1
0
1
Read data
(8)Select ADC
0
1
0
1
0
1
0
0
0
0
0/1
(9)Statis drive
ON/OFF
0
1
0
1
0
1
0
0
1
0
0/1
(10)Select duty
0
1
0
1
0
1
0
1
0
0
0/1
(11)Read Modify Write 0
1
0
1
1
1
0
0
0
0
0
1: 1/4, 0: 1/3
Increments the column address register by
(12)End
0
1
0
1
1
1
0
1
1
1
0
1 druing write only.
Read modify write OFF
(13)Reset
0
1
0
1
1
1
0
0
0
1
0
Reads data from display RAM onto data
bus.
0: Forward, 1: Reverse
Selects static driving operation.
1: Static drive, 0: Normal driving
Selets LCD duty cycle
Sets the display start line register to line 1,
and sets the column address counter and
page address register to 0.
* The Power Save mode is selected if the static drive is turned ON when the display is OFF.
Table 3 is the command table. The S1D15400 identifies a data bus using a combination of A0 and R/W (RD or WR)
signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed
is very high. The busy check is usually not required.
Rev. 1.0
EPSON
6–13
S1D15400 Series
(1) Display ON/OFF
This command turns the display on and off.
D=1: Display ON
D=0: Display OFF
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
D
AEH, AFH
(2) Display Start Line
This command specifies the line address shown in Figure 2 and indicates the display line that corresponds to COM0. The
display area begins at the specified line address and continues in the line address increment direction. This area having
the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command,
the vertical smooth scrolling and paging can be used.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
A4
A3
A2
A1
A0
C0H to DFH
A4 A3 A2 A1 A0 Line Address
0
0
0
0
1
1
0
0
:
:
1
0
0
0
1
1
1
0
1
:
:
31
See figure 2.
(3) Set Page Address
This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed
by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified.
The display status is not changed even when the page address is changed.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
1
1
0
A1
A0
B8H to BBH
A1 A0 Page
0
0
1
1
0
1
0
1
0
1
2
3
igure 2.
6–14
EPSON
Rev. 1.0
S1D15400 Series
(4) Set Column Address
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU
continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU
can access to data continuously. The column address stops to be incremented at address 80, and the page address is not
changed continuously.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
A6
A5
A4
A3
A2
A1
A0
00H to 4FH
A6 A5 A4 A3 A2 A1 A0 Column Address
0
0
0
0
0
0
1
0
0
0
0
:
:
1
0
0
0
0
0
1
1
1
1
0
1
:
:
79
(5) Read Status
A0
RD
R/W
WR
0
0
1
D7
D6
D5
D4
BUSY ADC ON/OFF RESET
D3
D2
D1
D0
0
0
0
0
Reading the command I/O register (A0=0) yields system status information.
• The BUSY bit indicates whether the driver will accept a command or not.
Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.
Busy=0: The driver will accept a new command.
• The ADC bit indicates the way column addresses are assigned to segment drivers.
ADC=1: Normal. Column address n → segment driver n.
ADC=0: Inverted. Column address 79-n → segment driver n.
• The ON/OFF bit indicates the current status of the display.
ON/OFF=1: Display OFF
RESET=0: Display ON
• The RESET bit indicates whether the driver is executing a reset or is in normal operating mode.
RESET=1: Currently executing reset command
RESET=0: Normal operation
(6) Write Display Data
A0
RD
R/W
WR
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data
Writes 8-bits of data into the display data RAM at a location specified by the contents of the column address and page
address registers, and increments the column address register by one.
Rev. 1.0
EPSON
6–15
S1D15400 Series
(7) Read Display Data
A0
RD
R/W
WR
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data
Reads 8-bits of data from the data I/O latch, updates the contents of the I/O buffer with display data from the display data
RAM location specified by the contents of the column address and page address registers and increments the column
address register.
After loading a new address into the column address register, one dummy read is required before valid data is obtained.
(8) Select ADC
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
0
0
D
A0H, A1H
Selects the relationship between display data RAM column addresses and segment drivers.
D=1: SEG0 ← column address 4FH, … (inverted)
D=0: SEG0 ← column address 00H, … (normal)
This command is provided to reduce restrictions on the placement of driver ICS and routing of traces during printed circuit
board design. See figure 2 for a table of segments and column addresses for the two values of D.
(9) Static Drive ON/OFF
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
0
D
A4H, A5H
Forces display on and all common outputs to be selected.
D=1: Static drive on
D=0: Static drive off
(10) Select Duty
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
0
0
D
A8H, A9H
Sets the duty cycle of the LCD drive.
D=1: 1/4 duty cycle
D=0: 1/3 duty cycle
6–16
EPSON
Rev. 1.0
S1D15400 Series
(11) Read-Modify-Write
This command is used in combination with the End command. Once the Read-Modify-Write command is entered, the
column address is incremented by 1 only by the display data write command but not incremented by the display data read
command. This status is kept until the End command is entered.
When the End command is entered, the column address is returned to the column address when the Read-Modify-Write
command is entered. This function can reduce the load of MPU when it repeatedly changes data of the specific display
area such as a blinking cursor.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
E0H
* Any command other than data read and write can be used during the Read-Modify-Write mode. However, the Column
Address Set command cannot be used.
Sequence when the cursor is displayed
Page address set
Column address set
Read/modify/write
Dummy read
Data read
Data write
NO
End of change
YES
End
Rev. 1.0
EPSON
6–17
S1D15400 Series
(12) End
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
EEH
Return
Column address
N
N+1
N+2
N+m
Read/modify/write mode set
N
End
Cancels read-modify-write mode and restores the contents of the column address register to their value prior to the receipt
of the read-modify-write command.
(13) Reset
This command resets the display start line register, column address counter, and page address register to their initial status.
This command does not affect on the display data RAM. For details, see the Reset circuit of the functional block
explanation.
The counter and registers are reset after the Reset command has been entered.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
0
E2H
When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead
of this Reset signal.
Power Save (compound command)
The system enters the power save state by switching the static drive on in the display off state, reducing the consumed
current almost to static current. The internal state in the power save state is as follows:
• The LCD drive is stopped, and the segment and common drivers output the VDD level.
• Oscillating external clock entry is inhibited, and OSC2 becomes floating.
• The display data and the operation mode are held.
The power save state can be canceled by switching the display on or static drive off.
When the LCD drive voltage level is supplied by an externally-equipped resistance dividing circuit, the current flowing
through the resistor must be cut by means of the power save signal.
VDD
VDD
R
V1
R
V2
R
V3
S1D15400
Power save signal
VSSH
6–18
EPSON
Rev. 1.0
S1D15400 Series
9. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Supply voltage (1)
VSS
–8.0 to +0.3
V
Supply voltage (2)
V3
–15.0 to +0.3
V
Supply voltage (3)
V1, V2, V3
V3 to +0.3
V
Input voltage
VIN
VSS–0.3 to +0.3
V
Output voltage
VO
VSS–0.3 to +0.3
V
Power dissipation
PD
250
mW
Operating temperature
Topr
–40 to +85
°C
–65 to +150
°C
Storage temperature
QFP
chip
Soldering temperature × time (at lead)
Tstg
Tsol
–55 to +125
260, 10
°C, s
Notes: 1. All voltages are specified relative to VDD = 0 V.
2. The following relation must always hold VDD ≥ V1 ≥ V2 ≥ V3.
3. Exceeding the absolute maximum ratings may cause permanent damage to the device.
Functional operation under these conditions is not implied.
4. Moisture resistance of flat packages can be reduced during the soldering process, so care should be taken
to avoid thermally stressing the package during board assembly.
Rev. 1.0
EPSON
6–19
S1D15400 Series
10. DC CHARACTERISTICS
(Ta = –20 to 75 °C, VDD = 0 V)
Parameter
Symbol
Operating Recommended
voltage (1)
See note 1. Allowable
VSS
Recommended
Operating Allowable
voltage (2) Allowable
Allowable
Input leakage current
Output leakage current
LCD driver ON resistor
RON
Static current dissipation
IDD0
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Dynamic current dissipation
Input pin capacitance
Oscillation frequency
Reset time
Min.
Rating
Typ.
Max.
–5.5
–5.0
–4.5
Unit
V
V3
V1
V2
V IHT
VIHC
VILT
VILC
VOHT
VOHC1
VOHC2
VOLT
VOLC1
VOLC2
ILI
ILO
HIGH-level input voltage
Condition
IOH = –3.0 mA
IOH = –2.0 mA
IOH = –120 µA
IOL = 3.0 mA
IOL = 2.0 mA
IOL = 120 µA
Ta = 25 °C
V3 = –5.0 V
V3 = –3.5 V
CS = CL = VDD
During display fOSC = 4 kHz
IDD (1)
V 3 = –5.0 V
R f = 1 MΩ
IDD (2) During assess fcyc = 200 kHz
CIN Ta = 25 °C, f = 1 MHz
Rf = 1.0 MΩ ±2%, Vss=-5.0V
fOSC
Rf = 1.0 MΩ ±2%, Vss=–5.0V
tR
–7.0
—
–2.4
–11.0
–11.0
0.6×V 3
V3
VSS+2.0
0.2×VSS
VSS
VSS
VSS+2.4
VSS+2.4
0.2×VSS
—
—
—
–1.0
–3.0
—
—
—
—
—
—
—
15
11
1.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
10.0
0.05
1.5
9.5
300
5.0
18
16
—
–3.5
–2.7
VDD
0.4×V3
VDD
VDD
VSS+0.8
0.8×VSS
—
—
—
VSS+0.4
VSS+0.4
0.8×VSS
1.0
3.0
7.5
50.0
1.0
4.0
15.0
500
8.0
21
21
1000
V
V
V
V
V
V
V
µA
µA
Applicable Pin
V SS
V3,
See note 10.
V1
V2
See note 2
See note 3
See note 2
See note 3
See note 4
See note 5
OSC2
See note 4
See note 5
OSC2
See note 6.
See note 7.
kΩ
SEG0 to 72,
COM0 to 3.
See note 11.
µA
V DD
µA
V DD
pF
See note 8.
All input pins
kHz
See note 9.
µS
RES
Notes: 1. Operation over the specified voltage range is guaranteed, except where the supply voltage changes
suddenly during CPU access.
2. A0, D0 to D7, E (or RD), R/W (or WR) and CS
3. CL, FR, M/S and RES
4. D0 to D7
5. FR
6. A0, E (or RD), R/W (or WR), CS, CL and M/S, RES
7. When D0 to D7 and FR are high impedance.
8. During continual write access at a frequency of tcyc . Current consumption during access is effectively
proportional to the access frequency.
9. See figure below for details
10. See figure below for details
11. For a voltage differential of 0.1 V between input (V1, …, V2) and output (COM, SEG) pins. All voltages
within specified operating voltage range.
6–20
EPSON
Rev. 1.0
S1D15400 Series
Relationship between fOSC, fFR and R f
OSC1
Rf
OSC2
fOSC vs Rf
Ta = 25 °C
FR vs Rf
Ta = 25 °C
VSS = –5V
40
VSS = –5V
800
30
f OSC
[kHz]
Frame
[kHz] 400
20
10
0
0.5
1.0
1.5
Rf
[MΩ ]
2.0
0
2.5
0.5
1.0
1.5
Rf
[MΩ ]
2.0
2.5
1/4 duty
1/3 duty
Relationship between fCL and FR
fOSC vs FR
200
Frame
100
[Hz]
0
4.0
8.0
12.0
[kHz ]
fOSC
1/4 duty
1/3 duty
Operating bounds on VSS and V3
V3 vs VSS
-15
-10
V3
[V]
Operating voltage
range
-5
0
-2
-4
-6
-8
VSS [V]
Rev. 1.0
EPSON
6–21
S1D15400 Series
11. AC CHARACTERISTICS
• MPU Bus Read/Write I (80-family MPU)
A0,CS
t AW8
t CYC8
t AH8
WR,RD
t CC
t DS8
t DH8
D0 to D7
(WRITE)
t CH8
t ACC8
D0 to D7
(READ)
(Ta = –20 to 75 °C, VSS = –5.0 V ±10%)
Signal
A0, CS
WR, RD
D0 to D7
Parameters
Address hold time
Address setup time
System cycle time
Control pulsewidth
Data setup time
Data setup time
RD access time
Output disable time
Symbol
tAH8
tAW8
tCYC8
tCC
tDS8
tDH8
tACC8
tCH8
Rating
Min.
Max.
10
—
20
—
1000
—
200
—
80
—
10
—
—
90
10
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL = 100 pF
Notes: 1. All parameter values for a VSS of –3.0 V are about 100% up of their value for a VSS of –5.0 V.
2. All inputs must have a rise and fall time of less than 15 ns.
6–22
EPSON
Rev. 1.0
S1D15400 Series
• MPU Bus Read/Write II (68-family MPU)
t CYC6
E
t EW
t AW6
t DS6
R/W
t AH6
A0,CS
t DH6
D0 to D7
(WRITE)
t ACC6
t OH6
D0 to D7
(READ)
(Ta = –20 to 75 °C, VSS = –5 V ±10%)
Signal
A0, CS,R/W
D0 to D7
E
Parameters
Symbol
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Enable
Read
pulse width
Write
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
tEW
Rating
Min.
Max.
1000
—
20
—
10
—
80
—
10
—
10
60
—
90
100
—
8
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
CL = 100 pF
Notes: 1. tcyc6 is the cycle time of CS.E, not the cycle time of E.
2. All parameter values for a VSS of –3.0 V are about 100% up of their value for a VSS of –5.0 V.
3. All inputs must have a rise and fall time of less than 15 ns.
Rev. 1.0
EPSON
6–23
S1D15400 Series
• Display Control Signal Timing
tf
tr
CL
t WLCL
t WHCL
t DFR
FR
Input
(Ta = –20 to 75 °C, VSS = –5.0 V ±10%)
Signal
CL
FR
Parameters
Symbol
LOW-level pulse width
HIGH-level pulse width
Rise time
Fall time
FR delay time
tWLCL
tWHCL
tr
tf
tDFR
Min.
35
35
—
—
-2.0
Rating
TYP.
—
—
30
30
0.2
Max.
—
—
150
150
2.0
Min.
—
Rating
TYP.
0.2
Max.
0.4
Unit
Condition
µs
µs
ns
ns
µs
Output
(Ta = –20 to 75 °C, VSS = –5.0 V ±10%)
Signal
FR
Parameters
FR delay time
Symbol
tDFR
Unit
µs
Condition
CL = 100 pF
Notes: 1. The listed input tDFR applies to the S1D15400 in slave mode. The listed output tDFR applies to the
S1D15400 in master mode.
2. All parameter values for a VSS of –3.0 V are about 100% up of their value for a VSS of –5.0 V.
6–24
EPSON
Rev. 1.0
S1D15400 Series
Example Drive Waveforms (1/3 Bias, 1/4 duty)
COM0
VDD
VSS
FR
COM1
COM2
COM3
VDD
V1
V2
V3
COM0
COM4
COM5
COM6
COM7
VDD
V1
V2
V3
COM1
COM14
COM15
0
1
2 3
SEG
4
VDD
V1
V2
V3
COM2
VDD
V1
V2
V3
COM3
VDD
V1
V2
V3
SEGn
Rev. 1.0
COM3 to SEGn
V3
V2
V1
0V
–V1
–V2
–V3
COM0 to SEGn
V1
0V
–V1
EPSON
6–25
S1D15400 Series
12. MPU INTERFACE CONFIGURATION
80 Family MPU
VCC
A0
A1 to A7
IOQR
MPU
Decoder
CS
S1D15400
D0 to D7
GND
VDD
A0
D0 to D7
RD
RD
WR
WR
RES
RES
VSS
V3
RESET
68 Family MPU
VCC
A1 to A15
VMA
MPU
A0
A0
Decoder
CS
S1D15400
D0 to D7
D0 to D7
E
E
GND
VDD
R/W
R/W
RES
RES
VSS
V3
RESET
6–26
EPSON
Rev. 1.0
S1D15400 Series
13. LCD DRIVE INTERFACE CONFIGURATION
S1D15400 - S1D15400 (Internal Oscillator)
To LCD COM
VDD
To LCD SEG
To LCD SEG
S1D15400
S1D15400
Master
Slave *1
To LCD COM
M/S
M/S
OSC1
OSC2
FR
OSC1
OSC2
FR
VSS
Rf
*2
S1D15400 - S1D15400 (External clock)
To LCD COM
To LCD SEG
To LCD SEG
S1D15400
S1D15400
Master
Slave *1
VDD
M/S
M/S
OSC1
External clock
OSC2
FR
OSC1
OSC2
FR
VSS
*2
Notes: 1. The duty cycle of the slave must be the same as that for the master.
2. If a system has two or more slave drivers a CMOS buffer will be required.
Rev. 1.0
EPSON
6–27
S1D15400 Series
14. PANEL INTERFACE CONFIGURATION
LCD
Segment type
SEG
SEG
COM
S1D15400
S1D15400
Master
6–28
Slave
EPSON
Rev. 1.0
7. S1D15600/601/602 Series
Rev. 4.6
CONTENTS
1. DESCRIPTION ................................................................................................................................................ 7-1
2. FEATURES ...................................................................................................................................................... 7-1
3. BLOCK DIAGRAM ........................................................................................................................................... 7-2
4. PAD ................................................................................................................................................................. 7-3
5. PIN DESCRIPTION ......................................................................................................................................... 7-5
6. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 7-9
7. FUNCTIONAL DESCRIPTION ......................................................................................................................7-21
8. COMMANDS .................................................................................................................................................7-40
9. COMMAND DISCRIPTION-INSTRUCTION SETUP EXAMPLES ................................................................7-49
–i–
Rev. 4.6
S1D15600/601/602 Series
1. DESCRIPTION
The S1D15600/601/602 series is a single-chip LCD
driver for dot-matrix liquid crystal displays. It accepts
serial or 8-bit parallel display data directly from a microprocessor and stores data in an on-chip 166 × 65-bit
RAM.
The S1D15600/601/602 series features 167 common and
segment outputs to drive either a 65 × 102-pixel
(S1D15600) display (4 rows × 6 columns with 16 × 16pixel characters) or a 33 × 134-pixel (S1D15601) display
(2 rows × 8 columns with 16 × 16-pixel characters) or a
17 × 150-pixel (S1D15602) display (1 row × 9 columns
with 16 × 16 characters). In addition, two S1D15600s
can be connected together to drive a 65 × 268-pixel
graphics display panel.
The S1D15600/601/602 series can read and write RAM
data with the minimum current consumption as it does
not require any external operation clock. Also, it has a
built-in LCD power supply featuring the very low current
consumption and, therefore, the display system of a highperformance but handy instrument can be realized by use
of the minimum current consumption and LSI chip
configuration.
The S1D15600/601/602 Series has the S1D15600,
S1D15601 and S1D15602 available according to the
duty.
• On-chip 166 × 65-bit display RAM
• Direct relationship between RAM bits and display
pixels.
• High speed Interfaces to 6800- and 8080-series microprocessors
• Selectable 8-bit parallel/serial interface
• Many command functions
• On-chip LCD power circuit including DC/DC
voltage converter, voltage regulator and voltage
followers.
• On-Chip Contrast control.
• Two types of VREG (Built-in power supply regulator
temperature gradient).
• Type1 (S1D1560* D00** , S1D1560*D10 **)...–
0.2%/˚C
• Type2 (S1D15600D14**)...0.00%/˚C
• On-chip oscillator
• Ultra low power consumption
• Power Supply
VDD – VSS –2.4 V to –6.0 V
VDD – V5 –3.5 V to –16.0 V
• Ta = –30 to 85°C
• CMOS process
• TCP, QTCP
• The system is not designed against the radio activity.
2. FEATURES
• Wide variety of duty and display areas
Model
S1D15600
S1D15601
S1D15602
Duty
1/65
1/64
1/49
1/48
1/33
1/32
1/25
1/24
1/17
1/16
LCD bias
1/9
1/7
1/7
1/5
1/5
Single-chip
display area
65 × 102
64 × 102
49 × 102
48 × 102
33 × 134
32 × 134
25 × 134
24 × 134
17 × 150
16 × 150
Note: The LCD bias is obtained if the built-in power
supply is used.
Rev. 4.6
EPSON
7–1
S1D15600/601/602 Series
3. BLOCK DIAGRAM
O0 to O31
O32
to
O101 O102 to O165 COMI
VSS
VDD
VDD
V1
V1
V2
Common
and
segment
driver
V3
V4
Common
and
segment
driver
Segment
driver
V2
Common
I
V3
V4
V5
V5
Frame
control
Shift
register
Shift
register
CAP1+
CAP1–
CAP2+
Supply
voltage
generator1
166–bit display data latch
CAP2–
VR
T1, T2
Output
status
select
I/O
buffer
Line
address
decoder
166 x 65–bit display
data RAM
Line
counter
Display
initial line
register
166–bit column address decoder
FR
8–bit column address counter
SYNC
Page
address
register
Display
timing
generator
8–bit column address register
CL
CLO
DYO
M/S
Bus holder
7–2
OSC1
Command
decoder
Status flag
Oscillator
OSC2
MPU interface
I/O buffer
CS1 CS2 A0 RD WR C86 SI SCL P/S RES
D7 D6 D5 D4 D3 D2 D1 D0
EPSON
Rev. 4.6
S1D15600/601/602 Series
4. PAD
V5
V4
V3
V2
V1
VDD
VR
V5
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
D4
D3
D2
D1
D0
VSS
RD
WR
A0
C86
CS2
CS1
P/S
S1
SCL
RES
M/S
VDD
V1
V2
V3
V4
V5
Pad layout
O0
1 216
49
COM1
O165
D156 D0B
*
95
8.08 × 5.28 mm
100 µm (Min.)
625 µm
300 µm (Al-pad)
Chip size
Pad pitch
Chip thickness
:
:
:
:
Bump size A
: 103 µm × 95 µm (Typ.) (Pad No. 1 ~ 6, 18, 36 ~ 42,
44 ~ 49)
: 69 µm × 95 µm (Typ.) (other then the above)
: 23 µm (Typ.)
• Au-Bump
Bump size B
Bump hight
• Al-pad
Pad size A
Bump size B
Rev. 4.6
O121
O120
170
O46
O45
: 111 µm × 102 µm (Typ.) (Pad No. 1 ~ 6, 18, 36 ~ 42,
44 ~ 49)
: 77 µm × 99 µm (Typ.) (Other then the above)
EPSON
7–3
S1D15600/601/602 Series
S1D15600/601/602 Series
Unit : µm
PAD Center Coordinates
PAD
PIN
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Name
V5
V4
V3
V2
V1
VDD
M/S
RES
SCL
SI
P/S
CS1
CS2
C86
A0
WR
RD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
DYO
CLO
SYNC
FR
CL
OSC2
OSC1
T2
T1
VSS
CAP1+
CAP1CAP2+
CAP2VOUT
V5
VR
VDD
V1
V2
V3
V4
V5
00
01
02
03
04
7–4
X
Y
3640
3489
3339
3188
3037
2889
2755
2604
2453
2302
2151
2001
1850
1699
1548
1397
1247
1077
945
794
643
493
342
191
40
-111
-261
-412
-563
-714
-865
-1015
-1166
-1317
-1468
-1638
-1789
-1939
-2090
-2241
-2392
-2543
-2674
-2844
-2995
-3146
-3297
-3447
-3598
-3887
2487
2294
2194
2094
1994
1894
PAD
PIN
No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Name
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
X
-3887
Y
1794
1694
1594
1494
1394
1294
1194
1094
994
894
794
694
594
494
394
294
194
94
-6
-106
-206
-306
-406
-506
-606
-706
-806
-906
-1006
-1106
-1206
-1306
-1406
-1506
-1606
-1706
-1806
-1906
-2006
-2106
-2206
-3711 -2487
-3611
-3511
-3411
-3311
-3211
-3111
-3011
-2911
-2811
-2711
-2611
-2511
PAD
PIN
No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Name
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
EPSON
X
Y
PAD
No.
-2411 -2487 163
-2311
164
-2211
165
-2111
166
-2011
167
-1911
168
-1811
169
-1711
170
-1611
171
-1511
172
-1411
173
-1311
174
-1211
175
-1111
176
-1011
177
-911
178
-811
179
-711
180
-611
181
-511
182
-411
183
-311
184
-211
185
-111
186
-11
187
89
188
189
189
289
190
389
191
489
192
589
193
689
194
789
195
889
196
989
197
1089
198
1189
199
1289
200
1389
201
1489
202
1589
203
1689
204
1789
205
1889
206
1989
207
2089
208
2189
209
2289
210
2389
211
2489
212
2589
213
2689
214
2789
215
2889
216
PIN
Name
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
COMI
X
Y
2989 -2487
3089
3189
3289
3389
3489
3589
3689
3887 -2206
-2106
-2006
-1906
-1806
-1706
-1606
-1506
-1406
-1306
-1206
-1106
-1006
-906
-806
-706
-606
-506
-406
-306
-206
-106
-6
94
194
294
394
494
594
694
794
894
994
1094
1194
1294
1394
1494
1594
1694
1794
1894
1994
2094
2194
2294
Rev. 4.6
S1D15600/601/602 Series
5. PIN DESCRIPTION
Power Supply
Name
I/O
VDD
Supply
VSS
V1 to V5
Supply
Description
Number of pins
5V supply. Common to MPU power supply pin VCC.
2
Ground
2
LCD driver supply voltages. The voltage determined by the
LCD cellis impedance-converted by a resistive divider or an
operational amplifier for application. Voltages should be
determined on a V DD- basis so as to satisfy the following
relationship. The voltages must satisfy the following relationship.
VDD ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5.
When master mode selects, these voltages are generated on-chip.
11
V1
V2
V3
V4
10B* S1D15601D10B *
S1D15600D00B* S1D15600D
S1D15601D00B* S1D15602D00B *
1/9 V5
1/7 V5
1/5 V5
2/9 V5
2/7 V5
2/5 V5
7/9 V5
5/7 V5
3/5 V5
8/9 V5
6/7 V5
4/5 V5
LCD Driver Supplies
Name
I/O
Description
Number of pins
CAP1+
O
DC/DC voltage converter capacitor 1 positive connection
1
CAP1–
O
DC/DC voltage converter capacitor 1 negative connection
1
CAP2+
O
DC/DC voltage converter capacitor 2 positive connection
1
CAP2–
O
DC/DC voltage converter capacitor 2 negative connection
1
VOUT
I/O
DC/DC voltage converter output1
1
VR
I
Voltage adjustment pin. Applies voltage between VDD and V5
1
using a resistive divider.
T1, T2
Rev. 4.6
I
Liquid crystal power control terminals
T1
T2
Boosting circuit
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
Valid
Valid
Invalid
Invalid
EPSON
Voltage
regulation
circuit
Valid
Valid
Valid
Invalid
2
V/F circuit
Valid
Valid
Valid
Valid
7–5
S1D15600/601/602 Series
Microprocessor Interface
Name
I/O
D0 to D7
I/O
A0
Description
Number of pins
Data inputs/outputs
8
I
Control/display data flag input. This is connected to the LSB
of the microprocessor address bus.
When LOW, the data on D0 to D7 is control data.
When HIGH, the data on D0 to D7 is display data.
1
RES
I
Reset input. System is reset and initialized when LOW.
1
CS1, CS2
I
Chip select inputs. Data input/output is enabled when
CS1 is LOW and CS2 is HIGH.
2
RD (E)
I
Read enable input. See note. 1
1
WR (R/W)
I
Write enable input. See note. 2
1
C86
I
Microprocessor interface select input. LOW when interfacing to
8080-series. HIGH when interfacing to 6800-series.
1
SI
I
Serial data input
1
SCL
I
Serial clock input. Data is read on the rising edge of SCL and
converted to 8-bit parallel data.
1
Parallel/serial data input select
1
P/S
I
P/S
Operating
mode
Chip select
Data/command
Data
input/
output
Read/write
Serial
clock
HIGH
Parallel
CS1, CS2
A0
D0 to D7
RD, WR
—
LOW
Serial
CS1, CS2
A0
SI
Write only
SCL
In serial mode, data cannot be read from the RAM, and D0 to D7,
HZ, RD and WR must be HIGH or LOW. In parallel mode, SI
and SCL must be HIGH or LOW.
Note 1
When interfacing to 8080-series microprocessors, RD is active-LOW. When interfacing to 6800-series microprocessors, they are active-HIGH.
Note 2
When interfacing to 8080-series microprocessors, WR is active-LOW. When interfacing to 6800-series microprocessors, It will be read mode when WR is high and It will be write mode when WR is LOW.
7–6
EPSON
Rev. 4.6
S1D15600/601/602 Series
Oscillator and Timing Control
Name
I/O
Description
Number of pins
OSCI
I
Connecting pins for feedback resistors of the built-in oscillator
When M/S = HIGH: Connect oscillator resistor Rf to the OSC1
and OSC2 pins. The OSC2 pin is used for output of the oscillator
amplifier.
2
OSC2
I/O
When M/S = LOW: The OSC2 pin is used for input of oscillation
signal. The OSC1 pin should be left open. Fix the CL pin to theVSS
level when using the internal oscillator circuit as the display clock.
2
CL
I
Display clock input. The line counter increments on the rising edge
of CL and the display pattern is output on the falling edge. When
use external display clock, OSC1 = HIGH, OSC2 = LOW and
reset this LSI by RES pin.
1
CLO
O
Display clock output. When using the master operation, the clock
signal is output on this pin. Connect CLO to YSCL on the
common driver.
1
M/S
I
Master/slave select input. Master makes some signals for display,
and slave gets them. This is for display syncronization.
1
Device
156XDOB
Operating
mode
Internal
oscillator
Power
supply
LOW
Slave
OFF
OFF
I
I
Open
I
O
HIGH
Master
ON
ON
O
O
I
O
O
M/S
FR
SYNC OSC1 OSC2 DYO
Note
I = input mode
O = output mode
FR
I/O
LCD AC drive signal input/output. If the S1D15600/601/602 series
MPU’s are used in master and slave configuration, this pin must
be connected to each FR pin. Also when the S1D15600/601/602
series isused as the master MPU, this pin must be connected to
the FRpin of the common driver. Output is selected when M/S is
HIGH, and input is selected when M/S is LOW.
1
SYNC
I/O
Display sync input/output. If the S1D15600/601/602 series MPU’s
are used in master and slave configuration, this pin must be
connected to each SYNC pin. Output is selected when M/S is
HIGH, and Input is selected when M/S is LOW.
1
DYO
O
Start-up output for common driver. Connect to DIO of the
common driver.
1
Rev. 4.6
EPSON
7–7
S1D15600/601/602 Series
LCD Driver Outputs
Name
I/O
Description
Number of pins
O0 to O165
O
LCD driver outputs. O0 to O31 and O102 to O165 are selectable
segment or common outputs, determined by a selection command.
O32 to O101 are segment outputs only.
166
For segment outputs, the ON voltage level is given as shown in
the following table.
RAM data
LOW
HIGH
LCD ON voltage
FR
Normal display Inverse display
V5
V3
LOW
HIGH
LOW
V2
V5
VDD
V3
HIGH
VDD
V2
For common outputs, the ON voltage is given as shown in the
following table.
Scan data
FR
LCD ON voltage
LOW
LOW
HIGH
V4
V1
LOW
VDD
HIGH
V5
HIGH
COMI
O
LCD driver common output. Common outputs when the “DUTY +1”
command is executed are as follows:
S1D15600
S1D15601
S1D15602
“DUTY + 1” ON
“DUTY + 1” OFF
COM64, COM48
COM32, COM24
COM16
V1 or V4
V1 or V4
V1 or V4
1
Common output special for the indicator.
7–8
EPSON
Rev. 4.6
S1D15600/601/602 Series
6.ABSOLUTE MAXMUM RATINGS
Parameter
Symbol
Rating
Unit
Supply voltage (1)
Supply voltage range (2)
(DC/DC When in use)
VSS
–7.0 +0.03
–6.0 to 0.3
(when triple boosting)
V
Driver supply voltage range (1)
V5
–18.0 to 0.3
V
Driver supply voltage range (2)
V1, V2, V3, V 4
V5 to 0.3
V
Input voltage range
VIN
VSS –0.3 to 0.3
V
Output voltage range
Vo
VSS –0.3 to 0.3
V
Operating temperature range
Topr
–30 to 85
°C
Storage temperature range (TCP)
Tstr
–55 to 100
°C
VCC
VDD
GND
VSS
VDD
V5
(System)
(S1D15600/601/602 series)
Notes: 1. The voltages shown are based on VDD = 0 V.
2. Always keep the condition of VDD ≥ V1 ≥ V 2 ≥ V3 ≥V4 ≥ V5 for voltages V1, V2 , V3 and V4.
3. If LSIs are used over the absolute maximum rating, the LSIs may be destroyed permanently. It is
desirable to use them under the electrical characteristic conditions for general operation. Otherwise, a
malfunction of the LSI may be caused and LSI reliability may be affected.
4. A guarantee on operating temperature below –30°C may be studied individually.
Rev. 4.6
EPSON
7–9
S1D15600/601/602 Series
DC Characteristics
VDD = 0 V, VSS = –5 V ± 10%, Ta = –30 to +85°C unless otherwise noted.
Item
Symbol
Power
Recommendvoltage (1) ed operation
Condition
Min.
Typ.
Max.
Unit
VSS
–5.5
–5.0
–4.5
V
–6.0
–2.4
V5
–16.0
–4.0
V
V5 *2
voltage (2) Operational
V1 , V2
0.4 × V 5
VDD
V
V1 , V2
Operational
V3 , V4
V5
0.6 × V5
V
V3 , V4
VIHC1
0.3 × VSS
VDD
V
VIHC2
0.15 × V SS
VDD
*4
*3
Operational
Operating
Operational
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
0.3 × VSS
VDD
VSS = –2.7 V
0.2 × VSS
VDD
VILC1
VSS
0.7 × V SS
VILC2
VSS
0.85 × VSS
*4
VSS
0.7 × V SS
*3
VILC1
VSS = –2.7 V
VILC2
VSS = –2.7 V
VOHC1
VOHC2
VSS
0.8 × V SS
0.2 × VSS
0.2 × VSS
VDD
VDD
V
V
VOHC1
VSS = –2.7 V
IOH = –0.5 mA
0.2 × VSS
VDD
VSS = –2.7 V
IOH = –50 µA
0.2 × VSS
VDD
VOLC1
IOL = 1 mA
VSS
0.8 × V SS
VOLC2
IOL = 120 µA
VSS
0.8 × V SS
*3
*4
*5
OSC2
*5
OSC2
V
*5
OSC2
VOLC1
VSS = –2.7 V
IOL = 0.5 mA
VSS
0.8 × V SS
VOLC2
VSS = –2.7 V
IOL = 50 µA
VSS
0.8 × V SS
–1.0
1.0
µA
*6
–3.0
3.0
µA
*7
kΩ
O0 to O166
LCD driver ON resistance
RON
Static power consumption
ISSQ
Input terminal capacity
CIN
Oscillation frequency
f OSC
I 5Q
VIN = VDD or VSS
Ta = 25°C
Ta = 25°C
Rf =1 MΩ
VSS
VOUT
Voltage regulator
operation
voltage
VOUT
3.0
V5 = –8.0 V
3.0
4.5
0.00
5.0
µA
VSS
0.01
15.0
µA
V5
5.0
8.0
pF
*3 *4
kHz
*9
1.0
µs
*10
1.0
µs
*11
f=1MHz
VSS = –5V
15
18
22
VSS = –2.7V
11
16
21
when triple
boosting
*8
–6.0
–18.0
–2.4
V
V
*12
VOUT
–16.0
–6.0
V
VOUT
*13
Voltage regulutor
V5
1
Supplied to S1D15600D00B
–16.0
–6.0
V
operation voltage
V5
2
Supplied to S1D15601D00B
–16.0
–5.0
V
V5
3
–16.0
–4.0
V
V5
4
–16.0
–4.5
V
–2.65
V
VREG
*5
OSC2
2.0
tR
tRW
Input voltage
Amplified output voltage
V
V5 = –14.0 V
V5 = –18.0V
±2%
Built-in power circuit
*4
V
IOH = –1 mA
IOH = –120 µA
VOHC2
ILI
Reference voltage
*3
VSS = –2.7 V
I LO
*
*
Supplied to S1D15601D10B
*
Supplied to S1D15602D00B
*
Ta = 25°C
*V SS = –2.4V is on the same basis as VSS = –2.7V.
7–10
*1
VIHC2
Input leakage current
Reset time
VSS
VIHC1
Output leakage current
Reset “L” pulse width
Pin used
EPSON
–2.35
–2.5
* See the 4-12 page for details.
Rev. 4.6
S1D15600/601/602 Series
When dynamic current consumption (I) is displaye; the built-in power circuit is on and T1 = T2 =
LOW.
VDD = 0 V, VSS = –5 V ± 10%, Ta = –30 to +85°C unless otherwise noted.
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
S1D15600
V 5 = –12.5 V; 3 times amplified
169
340
µA
S1D15601
V 5 = –8.0 V ; 3 times amplified
124
250
µA
V 5 = –6.0 V ; 2 times amplified
53
110
µA
V SS = –2.7 V; 3 times amplified
66
130
µA
S1D15602
IDD (1)
Remarks
*16
V 5 = –6.0 V
Typical current consumption characteristics
- Dynamic current consumption (I), if an external clock and an external power supply are used.
Conditions:
40
( A)
30
I DD (1)
(ISS + I5)
20
5601
S1D1
2
S1D1560
10
0
00
156
S1D
1
2
3
4
5
6
VDD
7
(V)
Remarks:
The built-in power supply is off but
the external one is used.
S1D15600 V5 – VDD = –12.5 V
S1D15601 V5 – VDD = –8.0 V
S1D15602 V5 – VDD = –6.0 V
External clock:
S1D15600 fCL = 4 kHz
S1D15601 fCL = 2 kHz
S1D15602 fCL = 1 kHz
*14
- Dynamic current consumption (I), if the built-in oscillator and the external power supply are used.
Conditions:
80
( A)
1
1D
I DD (1)
(ISS + I5)
40
D
S1
20
S1D
0
S
01
156
2
1560
1
2
3
4
VDD
Rev. 4.6
00
56
60
5
6
7
Remarks:
The built-in power supply is off but
the external one is used.
S1D15600 V5 – VDD = –12.5 V
S1D15601 V5 – VDD = –8.0 V
S1D15602 V5 – VDD = –6.0 V
Internal oscillation:
S1D15600 Rf = 1 MΩ
S1D15601 Rf = 1 MΩ
S1D15602 Rf = 1 MΩ
*15
(V)
EPSON
7–11
S1D15600/601/602 Series
- Dynamic current consumption (I), if the built-in power supply is used.
Conditions:
200
( A)
I DD
0
60
D15
S1
150
(1)
1
1560
S1D
100
602
S1D15
50
0
1
2
3
4
VDD
5
6
7
(V)
Remarks:
The built-in power supply is on and
T1 = T2 = Low.
S1D15600 V5 – VDD = –12.5 V; 3
times amplified
S1D15601 V5 – VDD = –8.0 V; 3
times amplified
S1D15602 V5 – VDD = –6.0 V; 2
times amplified
Internal oscillation:
S1D15600 Rf = 1 MΩ
S1D15601 Rf = 1 MΩ
S1D15602 Rf = 1 MΩ
*16
Notes: *1. Although the wide range of operating voltage is guaranteed, a spike voltage change during access to the
MPU is not guaranteed.
*2. The operating voltage range of the VSS and V5 systems (see Figure 11).
The operating voltage range is applied if an external power supply is used.
*3. Pins A0, D0 to D7, RD (E), WR (R/W), CS1, CS2, FR, SYNC, M/S, C86, SI, P/S, T1 and T2.
*4. Pins CL, SCL, and RES
*5. Pins D0 to D7, FR, SYNC, CL0, and DY0
*6. Pins A0, RD (E), WR (R/W), CS1, CS2, CL, M/S, RES, C86, SI, SCL, P/S, T1, and T2.
*7. Applied if pins D0 to D7, FR, and SYNC are high impedance.
*8. The resistance when the 0.1-volt voltage is applied between the “On” output terminal and each power
terminal (V1, V2, V3 or V4). It must be within the operating voltage (2).
R ON = 0.1 V/∆I
(∆I is the current that flows when 0.1 VDC is applied during power-on.)
*9. The relationship between the oscillation frequency, frame and Rf value (see Figure 10).
*10. “tr” (reset time) indicates the period between the time when the RES signal rises and when the internal
circuit has been reset. Therefore, the S1D1560 * is usually operable after “tr” time.
*11. Specifies the minimum pulse width of RES” signal. The LOW pulse greater than “ tRW” must be entered
for reset.
*12. If the voltage is amplified three times by the built-in power circuit, the primary power V SS must be used
within the input voltage range.
*13. The V 5 voltage can be adjusted within the voltage follower operating range by the voltage regulator
circuit.
*14, 15, 16 Indicates the current consumed by the separate IC. The current consumption due to the LCD panel
capacity and wiring capacity is not included.
The current consumption is shown if the checker is used, the display is turned on, the output status of
Case 6 is selected, and the S1D15600D00B* is set to 1/64 duty, the S1D15601D00B* is set to 1/32
duty, and the S1D15602D00B* is set to 1/16 duty.
*14. Applied if an external clock is used and if not accessed by the MPU.
*15. Applied if the built-in oscillation circuit is used and if not accessed by the MPU.
*16. Applied if the built-in oscillation circuit and the built-in power circuit are used (T1 = T2 = Low) and if
not accessed by the MPU. Measuring conditions: C1 = 4.7 µF, C2 = 0.47 µF, Ra + Rb = 2 MΩ
This includes the current that flows through the voltage regulator resistor (Ra + Rb = 2 MΩ). If the
built-in power circuit is used, the current consumption is equal to the current of VSS power.
7–12
EPSON
Rev. 4.6
S1D15600/601/602 Series
The relationship between oscillator frequency fOSC
and LCD frame frequency fF is obtained from the
following expression.
Oscillator frequency vs. frame vs. Rf
[S1D1560*D00B*]
Ta = 25°C
40
VSS = –5 V
S1D15600
30
[KHz]
20
f OSC
S1D15601
10
S1D15602
0
0.5
1.0
Rf
1.5
[MΩ ]
2.0
(f F indicates not
AC.)
2.5
Duty
fF
1/64
focs/256
1/48
focs/192
1/32
focs/256
1/24
focs/192
1/16
focs/256
fF signal cycle but cycle of LCD
Figure 10 (a)
External clock (fCL) vs. frame
[S1D1560*D00B*]
200
duty 1/64 S1D15600
duty 1/48
[Hz]
100
fF
duty 1/32 S1D15601
duty 1/24
duty 1/16 S1D15602
0
2
4
f CL [KHz]
6
8
Figure 10 (b)
Rev. 4.6
EPSON
7–13
S1D15600/601/602 Series
Operating voltage range for VSS and V5
–16
Power consumption during access (IDD (2)) MPU access cycle
–20
10
–15
1
5.0V
2.7V
–13
[V]
–10
V5–VDD
[mA]
I DD (2)
–5
0
0.1
0.01
2
2.4
4
3.0
VSS [V]
6
8
0
0.01
0.1
f cyc [MHz]
1
10
Figure 12
Figure 11
This graphic shows the current consumption when
the vertical patterns are written during “fcyc”. If not
accessed, IDD(1) is only shown.
Reset
Rating
Parameter
Symbol
tR
Reset LOW-level pulsewidth tRW
Reset time
Condition
See note.
Unit
Min.
Typ.
Max.
1.0
—
—
µs
1.0
—
—
µs
Note
tR is measured from the rising edge of RES. The S1D15600 enters normal operating mode after a reset.
7–14
EPSON
Rev. 4.6
S1D15600/601/602 Series
Display control timing
CL
t WLCL
t WHCL
tf
tr
t DFR
FR
t DSNC
SYNC
t DOH
t DOL
t CDH
t CDL
DYO
CLO
Input timing
VSS = –5.5 to –4.5 V, Ta = –30 to 85 °C
Rating
Parameter
CL LOW-level pulsewidth
CL HIGH-level pulsewidth
CL rise time
CL fall time
FR delay time
SYNC delay time
Symbol
Condition
tWLCL
tWHCL
tr
tf
tDFR
tDSNC
Unit
Min.
Typ.
Max.
35
—
—
µs
35
—
—
µs
—
30
—
ns
—
30
—
ns
–1.0
—
1.0
µs
–1.0
—
1.0
µs
VSS = –4.5 to –2.7 V, Ta = –30 to 85 °C
Rating
Parameter
CL LOW-level pulsewidth
CL HIGH-level pulsewidth
CL rise time
CL fall time
FR delay time
SYNC delay time
Symbol
Condition
tWLCL
tWHCL
tr
tf
tDFR
tDSNC
Unit
Min.
Typ.
Max.
35
—
—
µs
35
—
—
µs
—
40
—
ns
—
40
—
ns
–1.0
—
1.0
µs
–1.0
—
1.0
µs
Notes: 1. Effective only when the S1D15600D00B* is in the master mode.
2. The FR/SYNC delay time input timing is provided in the slave operation.
The FR/SYNC delay time output timing is provided in the master operation.
3. Each timing is based on 20% and 80% of VSS.
4. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
Rev. 4.6
EPSON
7–15
S1D15600/601/602 Series
Output timing
VSS = –5.5 to –4.5 V, Ta = –30 to 85 °C
Rating
Parameter
Symbol
Condition
Unit
tDFR
SYNC delay time
tDSNC
DYO LOW-level delay time tDOL
DYO HIGH-level delay time tDOH
CL = 50 pF
CLO to DYO LOW-level
S1D15600D0*B* operating in
FR delay time
delay time
CLO to DYO HIGH-level
delay time
tCDL
tCDH
Min.
Typ.
Max.
—
60
150
ns
—
60
150
ns
—
70
160
ns
—
70
160
ns
10
40
100
ns
10
40
100
ns
master mode only
S1D15600D0*B* operating in
master mode only
VSS = –4.5 to –2.7 V, Ta = –30 to 85 °C
Rating
Parameter
Symbol
Condition
Unit
tDFR
SYNC delay time
tDSNC
DYO LOW-level delay time tDOL
DYO HIGH-level delay time tDOH
CL = 50 pF
CLO to DYO LOW-level
S1D15600D0*B* operating in
FR delay time
delay time
CLO to DYO HIGH-level
delay time
tCDL
tCDH
Min.
Typ.
Max.
—
120
240
ns
—
120
240
ns
—
140
250
ns
—
140
250
ns
10
100
200
ns
10
100
200
ns
master mode only
S1D15600D0*B* operating in
master mode only
(1) System buses
Read/write characteristics I (80-series MPU)
t AH8
A0
t CYC8
t AW8
WR, RD
(CS)
tr
t CCLR
t CCLW
t CCHR
t CCHW
tf
t DH8
t DS8
D0 ~ D7
(WRITE)
t ACC8
tCH8
D0 ~ D7
(READ)
7–16
EPSON
Rev. 4.6
S1D15600/601/602 Series
VSS = –5.0 ±10%, Ta = –30 to 85 °C
Item
Address hold time
Signal
Symbol
A0, CS
tAH8
tAW8
tCYC8
Address setup time
System cycle time
Control LOW pulse width (WR)
WR
Control LOW pulse width (RD)
RD
Control HIGH pulse width (WR)
WR
Control HIGH pulse width (RD)
RD
Data setup time
Data hold time
RD access time
D0 to D7
Output disable time
Input signal change time
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tCH8
tr, tf
Conditions
Min.
Max.
Unit
10
ns
10
ns
200
ns
22
ns
77
ns
172
ns
117
ns
20
ns
10
ns
CL = 100pF
10
70
ns
50
ns
15
ns
VSS = –2.7 to –4.5 V, Ta = –30 to 85 °C
Item
Address hold time
Signal
Symbol
A0, CS
tAH8
tAW8
tCYC8
Address setup time
System cycle time
Control LOW pulse width (WR)
WR
Control LOW pulse width (RD)
RD
Control HIGH pulse width (WR)
WR
Control HIGH pulse width (RD)
RD
Data setup time
Data hold time
RD access time
Output disable time
Input signal change time
D0 to D7
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tCH8
tr, tf
Conditions
Min.
Max.
Unit
0
ns
0
ns
450
ns
44
ns
194
ns
394
ns
244
ns
20
ns
10
ns
CL = 100pF
10
140
ns
100
ns
15
ns
Notes: 1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC8–tCCLW–
tCCHW) or tr + tf ≤ (tCYC8–tCCLR–tCCHR)
2. All signal timings are limited based on the 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the RD or WR signal is in the
LOW level.
If read/write operation is performed by the RD or WR signal while CS is active, it is determined by the
RD or WR signal timing.
If read/write operation is performed by CS while the RD or WR signal is in the low level, it is determined by the CS active timing.
4. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
Rev. 4.6
EPSON
7–17
S1D15600/601/602 Series
(2) System buses
Read/write characteristics II (68-series MPU)
t CYC6
t EWLR
t EWLW
E
tr
t EWHR
t EWHW
t AW6
tf
t AH6
A0, R/W
t AH6
t DS6
t DH6
D0 ~ D7
(WRITE)
t OH6
t ACC6
D0 ~ D7
(READ)
VSS = –5.0 V ± 10%, Ta = –30 ~ 85 °C
Item
Signal
System cycle time
Address setup time
(A0)
Address hold time
R/W
Data setup time
Data hold time
D0~D7
Output disable time
Access time
Enable HIGH pulse
READ
width
WRITE
Enable LOW pulse
READ
width
WRITE
Input signal change time
7–18
E
E
Symbol
Conditions
Min.
Max.
Unit
tCYC6
200
ns
tAW6
tAH6
tDS6
tDH6
tOH6
tACC5
tEWHR
tEWHW
tEWLR
tEWLW
tr, tf
10
ns
10
ns
20
ns
10
n
EPSON
CL = 100pF
10
50
ns
70
ns
77
ns
22
ns
117
ns
172
ns
15
ns
Rev. 4.6
S1D15600/601/602 Series
VSS = –2.7 V ~ 4.5 V, Ta = –30 ~ 85 °C
Item
Signal
Symbol
tCYC6
System cycle time
Address setup time
A0
Address hold time
R/W
tAW6
tAH6
tDS6
tDH6
tOH6
tACC5
tEWHR
tEWHW
tEWLR
tEWLW
tr, tf
Data setup time
Data hold time
D0 to D7
Output disable time
Access time
Enable HIGH pulse
READ
width
WRITE
Enable LOW pulse
READ
width
WRITE
E
E
Input signal change time
Notes:
Conditions
CL = 100pF
Min.
Max.
Unit
450
ns
0
ns
0
ns
20
ns
10
ns
20
100
ns
140
ns
194
ns
44
ns
244
ns
394
ns
15
ns
1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC6-tEWLW-tEWHW)
or tr + tf ≤ (tCYC6 -tEWLR-tEWHR).
2. All signal timings are limited based on the 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the E signal is in the high level.
If read/write operation is performed by the E signal while CS is active, it is determined by the E signal
timing.
If read/write operation is performed by CS while the E signal is in the high level, it is determined by the
CS active timing.
4. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
(3) Serial interface
t CSS
t CSH
CS
t SAS
t SAH
A0
t SCYC
t SLW
SCL
tr
tf
t SDS
t SHW
t SDH
SI
Rev. 4.6
EPSON
7–19
S1D15600/601/602 Series
VSS = –5.0 V ±10%, Ta = –30 ~ 85 °C
Item
Serial clock cycle
Signal
Symbol
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
tr, tf
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
A0
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
cs
Input signal change time
Conditions
Min.
Max.
Unit
250
ns
75
ns
75
ns
50
ns
200
ns
50
ns
30
ns
30
ns
400
50
ns
VSS = –2.7 V ~ –4.5 V, Ta = –30 ~ 85 °C
Item
Serial clock cycle
Signal
Symbol
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
tr, tf
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
A0
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
Input signal change time
cs
Conditions
Min.
Max.
Unit
500
ns
150
ns
150
ns
100
ns
400
ns
100
ns
100
ns
60
ns
800
50
ns
*1. All signal timings are limited based on the 20% and 80% of VSS voltage.
*2. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
7–20
EPSON
Rev. 4.6
S1D15600/601/602 Series
7. FUNCTIONAL DESCRIPTION
Microprocessor Interface
Parallel/serial interface
series through the serial data input (SI), but not from the
Parallel data can be transferred in either direction beS1D15600/601/602 series to the microprocessor. The
tween the controlling microprocessor and the S1D15600/
parallel or serial interface is selected by P/S as shown in
601/602 series through the 8-bit I/O buffer (D0 to D7).
table 1.
Serial data can be sent from the microprocessor to the
S1D15600/601/602
Table 1. Parallel/serial interface selection
P/S
Input type
CS1
CS2
A0
RD
WR
C86
SI
SCL
D0 to D7
HIGH
Parallel
CS1
CS2
A0
RD
WR
C86
—
—
D0 to D7
LOW
Serial
CS1
CS2
A0
—
—
—
SI
SCL
(Hz)
Note
“—” indicates fixed to either HIGH or to LOW
For the parallel interface, the type of microprocessor is
selected by C86 as shown in table 2.
Common 6800 series
Table 2. Microprocessor selection for parallel
interface
MPU bus
type
C86
HIGH
LOW
CS1 CS2
A0
RD
WR D0 to D7
6800-series CS1 CS2
A0
E
R/W D0 to D7
8080-series CS1 CS2
A0
RD
WR D0 to D7
Parallel interface
A0, WR (or R/W) and RD (or E) identify the type of
parallel data transfer to be made as shown in table 3.
Serial interface
The serial interface comprises an 8-bit shift register and
a 3-bit counter. These are reset when CS1 is HIGH and
CS2 is LOW. When these states are reversed, serial data
and clock pulses can be received from the microprocessor on SI and SCL, respectively.
Rev. 4.6
Table 3. Parallel data transfer
8080 series
Description
A0
1
R/W
1
E
1
RD
0
WR
1
1
0
1
1
0
Display data write
0
1
1
0
1
Status read
0
0
1
1
0
Write to internal reigister
(command)
Display data read out
Serial data is read on the rising edge of SCL and must be
input at SI in the sequence D7 to D0. On every eighth
clock pulse, the data is transferred from the shift register
and processed as 8-bit parallel data.
Input data is display data when A0 is HIGH and control
data when A0 is LOW. A0 is read on the rising edge of
every eighth clock signal.
The SLC signal is affected by the termination reflection
and external noise caused by the line length. The operation check on the actual machine is recommended.
EPSON
7–21
S1D15600/601/602 Series
CS1
CS2
SI
D7
1
SCL
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
D7
9
D6
10
A0
Figure 1. Serial interface timing
(dummy read cycle). On the next read cycle, the data is
read from the bus buffer onto the microprocessor bus. At
the same time, the next block of data is transferred from
RAM to the bus buffer. Likewise, when the microprocessor writes data to display data RAM, the data is first
stored in the bus buffer before being written to RAM at
the next write cycle.
When writing data from the microprocessor to RAM,
there is no delay since data is automatically transferred
from the bus buffer to the display data RAM. If the data
rate is required to slow down, the microprocessor can
insert an NOP instruction which has the same affect as
executing a wait procedure.
When a sequence of address sets is executed, a dummy
read cycle must be inserted between each pair of address
sets. This is necessary because the addressed data from
the RAM is delayed one cycle by the bus buffer, before
it is sent to the microprocessor. A dummy read cycle is
thus necessary after an address set and after a write cycle.
Chip select inputs
The S1D15600/601/602 series has two chip select pins:
CS1 and CS2, and data exchange between the microprocessor and the S1D15600/601/602 series is enabled when
CS1 is LOW and CS2 is HIGH. When these pins are set
to any other combination, D0 to D7 are high impedance.
The A0, RD, WR, SI and SCI inputs are disabled. If the
serial input interface has been selected, the shift register
and counter are reset. The Reset signal is entered
independent from the CS1 and CS2 status.
Data Transfer
To match the timing of the display data RAM and
registers to that of the controlling microprocessor, the
S1D15600/601/602 series uses an internal data bus and
bus buffer. A kind of pipeline processing takes place.
When the microprocessor reads the contents of RAM, the
data for the initial read cycle is first stored in the busbuffer
WR
MPU
DATA
Bus
holder
N
N+1
N
N+2
N+1
N+3
N+2
N+3
Internal
timing
WR
Figure 2. Write timing
7–22
EPSON
Rev. 4.6
S1D15600/601/602 Series
WR
MPU
RD
DATA
N
n
N
Address set
Dummy read
n+1
Data read n
Data read (n+1)
WR
RD
Internal
timing
Column
address
Bus
holder
N
N+1
N
n
N+2
N+1
N+2
Figure 3. Read timing
Status Flag
The S1D15600/601/602 series has a single bit status flag,
D7. When D7 is HIGH, the device is busy and will only
accept a Status Read command. If cycle times are
Rev. 4.6
monitored ed carefully, this flag does not have to be
checked before each command, and microprocessor capabilities can be fully utilized.
EPSON
7–23
S1D15600/601/602 Series
Display Data RAM
The display data RAM stores pixel data for the LCD. It
is a 166-column × 65-row addressable array as shown in
figure 4.
(If the display start line is set to 1ch)
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
1/64
Start
1/32
Page 8
ADC
LCD
OUT DO DO
=1 =0
O0 A5 00
O1 A4 01
O2 A3 02
O3 A2 03
O4 A1 04
O5 A0 05
O6 9F 06
O7 9E 07
1 0 0 0
Page 0
A2
A3
A4
A5
0 0 0 1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Common
address
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM I
to
O3
O2
O1
O0
0 0 0 0
Line
address
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Column address
DATA
to
O162
O163
O164
O165
Page
address
to
Figure 4. Display data RAM addressing
Note
For a 1/65 and 1/33 display duty cycles, page 8 is accessed following 1BH and 3BH, respectively.
7–24
EPSON
Rev. 4.6
S1D15600/601/602 Series
The 65 rows are divided into 8 pages of 8 lines and a ninth
page with a single line (D0 only). Data is read from or
written to the 8 lines of each page directly through D0 to
D7.
D0
D1
D2
D3
D4
The time taken to transfer data is very short, because the
microprocessor inputs D0 to D7 correspond to the LCD
common lines as shown in figure 5. Large display
configurations can thus be created using multiple
S1D15600/601/602.
COM0
COM1
COM2
COM3
COM4
1
0
1
0
0
Figure 5. RAM-to-LCD data transfer
The microprocessor reads from and writes to RAM
through the I/O buffer. Since the LCD controller operates independently, data can be written to RAM at the
same time as data is being displayed, without causing the
LCD to flicker.
Column Address Counter
The column address counter is an 8-bit presettable counter that provides the column address to display data
RAM. See figure 4. It is incremented by 1 each time a
read or write command is received. The counter automatically stops at the highest address, A6H. The contents of the column address counter are changed by the
Column Address Set command. This counter is independent of the page address register.
When the Select ADC command is used to select inverse
display operation, the column address decoder inverts
the relationship between the RAM column data and the
display segment outputs.
Page Address Register
The 4-bit page address register provides the page address
to display data RAM. The contents of the register are
changed by the Page Address Set command.
Page address 8 (D3 = HIGH, D2, D1, D0 = LOW) is a
special use RAM area for the indicator.
Initial Display Line Register
The initial display line register stores the address of the
RAM line that corresponds to the first (normally the top)
Rev. 4.6
line (COM0) of the display. See figure 4. The contents
of this 6-bit register are changed by the Initial Display
Line command. At the start of each LCD frame, synchronized with SYNC, the initial line is copied to the line
counter. The line counter is then incremented on the CL
clock signal once for every display line. This generates
the line addresses for the transfer of the 166 bits of RAM
data to the LCD drivers.
If a 1/65 or 1/33 display duty cycle is selected by the Duty
+ 1 command, the line address corresponding to the 65th
or 33rd SYNC signal is changed and the indicator special-use line address is selected. If the Duty + 1 command
is not used, the indicator special-use line address is not
selected.
Output Selection Circuit
The number of common (COM) and segment (SEG)
driver outputs can be selected to fit different LCD panel
configurations by the output selection circuit.
There are 70 segment-only outputs (O32 to O101) and 96
common or segment dual outputs (O0 to O31 and O102
to O165). A command select the status of the dual
common/segment outputs. Figure 6 shows the six different LCD driver arrangements.
Necessary LCD driver voltage is automatically allocated
to the COM/SEG dual outputs when their function is
determined by the output selection circuit.
The S1D15600 selects Case 1, 2 or 6 while the S1D15601
selects Case 3, 4, 5 or 6. As to the S1D15602, COM/SEG
output status cannot be selected, being fixed.
EPSON
7–25
S1D15600/601/602 Series
ADC LOW
(D0) HIGH
0
→
165 ←
→ 165
0
←
Column address
Display data RAM
Case 1
Case 2
Case 3
Case 4
Case 5
Case 6
102 segments
16 commons
↑
O0
↑
O15
64 commons
32 commons
102 segments
134 segments
134 segments
134 segments
166 segments
↑
O101
32 commons
32 commons
↑
O31
32 commons
16 commons
↑
O133
↑
O149
↑
O165
Figure 6. Output configuration selection
When COM outputs are assigned to the output drivers,
the unused RAM area is not available. However, all
RAM column addresses can still be accessed by the
microprocessor.
Since duty setting and output selection are independent,
the appropriate duty must be selected for each case.
Cases 1 to 6 are determined according to the three lowest
bits in the output status register in the output selection
circuit. The COM output scanning direction can be
selected by setting bit D3 in the output status register to
HIGH or LOW.
Table 4
S1D15600
Duty
COM I function
S1D15601
S1D15602
1/64
1/48
1/32
1/24
1/16
COM64
COM48
COM32
COM24
COM16
When the DUTY + 1 command is executed, pin COM1
becomes as shown in Figure 4 irrelevant to output selection:
Since master/slave operation and the output selection
circuit are completely independent in the S1D15600/
601/602 series, a chip either on the master or slave side
can be allocated to the COM output function in multichip configuration.
The LCD driver outputs shown in Table 5 become
ineffective when the S1D15600 or S1D15601 is used
with 1/48 or 1/24 duty, respectively. In this case,
ineffective outputs are used in the open state.
Table 5
Case 1
S1D15600
Case 2
Case 3
S1D15601
Case 4
Case 5
7–26
D3
0
1
0
1
0
1
0
1
0
1
Output status register
D2
D1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
EPSON
D0
1
1
0
0
1
1
0
0
1
1
Ineffective output
O150
O102
O150
O16
O0
O23
O158
O134
O158
O8
to
to
to
to
to
to
to
to
to
to
O165
O117
O165
O31
O7
O31
O165
O141
O165
O15
Rev. 4.6
S1D15600/601/602 Series
S1D15600 Output Status
The S1D15600 selects any output status from Cases 1, 2
and 6.
1/64 duty
Case
1
2
6
1
2
6
64 × 102)
Status register
LCD driver output
D3 D2 D1 D0 O0
O31 O32
O101 O102
O133 O134
O165
0
1
0
1
SEG102
COM0
COM63
1
1
0
1
SEG102
COM63
COM0
0
1
0
0
COM31
COM0
SEG102
COM32
COM63
1
1
0
0
COM32
COM63
SEG102
COM31
COM0
–
0
0
0
1/48 duty
Case
(Display Area
SEG166
(Display Area
48 × 102)
Status register
LCD driver output
D3 D2 D1 D0 O0
O31 O32
0
1
0
1
1
1
0
1
0
1
0
0
COM31
1
1
0
0
COM32
–
0
0
0
O101 O102
O133 O134
O165
COM47
COM0
COM0
COM47
COM0
47
SEG102
COM32
SEG102
COM31
47
COM0
SEG166
S1D15601 Output Status
The S1D15601 selects any output status from Cases 3, 4,
5 and 6.
1/32 duty
Case
3
4
5
6
(Display Area
3
4
5
6
LCD driver output
Status register
D3 D2 D1 D0 O0
O15 O16
O31 O32
O133 O134
149 150
O165
0
0
1
1
COM31
COM0
SEG134
1
0
1
1
COM0
COM31
SEG134
0
0
1
0
SEG134
COM0
COM31
1
0
1
0
SEG134
COM31
COM0
0
0
0
1
15←COM0
SEG134
COM16→31
1
0
0
1
COM16→31
SEG134
15←COM0
–
0
0
0
SEG166
(Display Area
1/24 duty
Case
32 × 134)
24 × 134)
LCD driver output
Status register
D3 D2 D1 D0 O0
O15 O16
O31 O32
O133 O134
149 150
O165
0
0
1
1
1
0
1
1
0
0
1
0
SEG134
1
0
1
0
SEG134
0
0
0
1
15←COM0
SEG134
16→23
1
0
0
1
16→23
SEG134
15←COM0
–
0
0
0
Rev. 4.6
COM23
COM0
COM0
SEG134
SEG134
COM23
COM0
COM23
COM23
COM0
SEG166
EPSON
7–27
S1D15600/601/602 Series
S1D15602 Output Status
COM/SEG output status of the S1D15602 is fixed.
1/16 duty (16 × 150)
LCD driver output
00
0149 150
15
SEG150
0165
COM0
Display Timers
Line counter and display data latch
timing
In a multiple-chip configuration, FR and SYNC are
inputs. The SYNC signal from the master synchronizes
the line counter and common timing of the slave.
The display clock, CL, provides the timing signals for the
line counter and the display data latch. The RAM line
address is generated synchronously using the display
clock. The display data latch synchronizes the 166-bit
display data with the display clock.
The timing of the LCD panel driver outputs is independent of the timing of the input data from the microprocessor.
Common timing signals
FR and SYNC
The LCD AC signal, FR, and the synchronization signal,
SYNC, are generated from the display clock. The FR
controller generates the timing for the LCD panel driver
outputs. Normally, 2-frame wave patterns are generated,
but n-line inverse wave patterns can also be generated.
These produce a high-quality display if n is based on the
LCD panel being used.
SYNC synchronizes the timing of the line counter and
common timers. It is also needed to synchronize the
frame period and a 50% duty clock.
7–28
The internal common timing and the special-use common driver start signal, DYO, are generated from CL.
As shown in figures 7 and 8, DYO outputs a HIGH-level
pulse on the rising edge of the CL clock pulse that
precedes a change on SYNC. DYO is generated by both
the S1D15600D0B*, regardless of whether the device is
in master or slave mode. However, when operating in
slave mode, the device duty and the external SYNC
signal must be the same as that of the master. In a
multiple-chip configuration, FR and SYNC must be
supplied to the slave from the master.
Table 6. Master and slave timing signal status
Part number
SD1560 D
EPSON
Mode
FR
SYNC
CLO
DYO
Master
Output
Output
CL
output
Output
Slave
Input
Input
B
* ** *
High
Output
impedance
Rev. 4.6
S1D15600/601/602 Series
2-frame AC driver waveform
(S1D15601 1/32 duty)
31 32
1
2
3
4
5
6
27 28 29 30 31 32
1
2
3
4
5
CL
SYNC
FR
DYO
COM0
VDD
V1
V4
V5
COM1
VDD
V1
V4
V5
RAM
data
VDD
V2
V3
V5
SEG n
Figure 7. Frame driver timing
Rev. 4.6
EPSON
7–29
S1D15600/601/602 Series
n line inverse driver waveform (n = 5, line inverse register 4)
31 32
1
2
3
4
5
6
27 28 29 30 31 32
1
2
3
4
5
CL
SYNC
FR
DYO
COM0
VDD
V1
V4
V5
COM1
VDD
V1
V4
V5
RAM
data
VDD
V2
V3
V5
SEG n
Figure 8. Line inverse driver timing
Note
When n = 5, the line inversion register is set to 4.
7–30
EPSON
Rev. 4.6
S1D15600/601/602 Series
LCD Driver
The LCD driver converts RAM data into the 167 outputs
that drive the LCD panel. There are 70 segment outputs,
96 segment or common dual outputs, and a COM1 output
for the indicator display.
Two shift registers for the common/segment drivers are
used to ensure that the common outputs are output in the
correct sequence. The driver output voltages depend on
the display data, the common scanning signal and FR.
VDD
VSS
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
FR
(SYNC)
COM0
COM1
COM0
COM2
COM3
COM4
COM5
COM1
COM6
COM7
COM8
COM9
COM2
COM10
COM 1
COM12
COM13
SEG0
COM14
COM15
SEG0 SEG1 SEG2 SEG3 SEG4
SEG1
COM0
to
SEG0
COM0
to
SEG1
Figure 9. Example of segment and common timing
Rev. 4.6
EPSON
7–31
S1D15600/601/602 Series
Display Data Latch Circuit
FR Control Circuit
The display data latch circuit temporarily stores the
output display data from the display data RAM to the
LCD driver circuit in each common period. Since the
Normal/Inverse Display, Display ON/OFF and Display
All Points ON/OFF commands control the data in this
latch, the data in the display data RAM is remains
unchanged.
The LCD driver voltage supplied to the LCD driver
outputs is selected using FR signal.
Power Supply Circuit
This is a power circuit to produce voltage needed to drive
liquid crystals at a low power consumption. This circuit
is valid only when the S1D1560*D**B* master is in
opera-tion. The power circuit consists of voltage tripler,
voltage regulator and the voltage follower.
The power circuit built into S1D1560*D**B* is set for
smaller scale liquid crystal panels and it is not too
suitable when the picture element is larger or to drive a
liquid crystal panel with lager indication capacity using
multiple chips. With liquid crystal panels with a larger
load capacity, the quality of display may become very
bad. Use an external power in such cases. (If an external
amp circuit is configured, we recommend to use the
S1F76600 and S1F76610.)
The power circuit can be controlled by the built-in power
ON/OFF command. When the built-in power is turned
off, all of the boosting circuit, voltage regulation circuit
and voltage follower circuit goes open. In this case, the
liquid crystal driving voltage V 1, V2 , V3, V4 and V5
should be supplied from outside and the terminals CAP1+,
CAP1-, CAP2+, CAP2-, Vout and VR should be kept
opened.
If the built-in power supply is turned on, you must always
enter this command after the wait time of the built-in
power supply turn-on completion command.
Various functions of the power circuit may be selected by
combinations of the setting of the T1 and T2. It is also
possible to make a combined use of the external power
LCD Driver Circuit
This multiplexer generates 4-value levels for the LCD
driver, having 167 outputs of 70 SEG outputs, 96 SEG/
COM dual outputs and a COM output for the indicator
display. The SEG/COM dual outputs have a shift register
and sequentially transmits COM scanning signals. The
LCD driver voltage is output according to the combination of display data, COM scanning signal and FR signal.
Figure 9 shows a typical SEG/COM output waveform.
Oscillator Circuit
The low power consumption type CR oscillator adjusting
the oscillator frequency by use of only oscillator resistor
Rf is used as a display timing signal source or clock for
the voltage raising circuit of the LCD power supply.
The oscillator circuit is only available in the master
operation mode. When a signal from the oscillator circuit
is used for display clock, fix the CL pin to the VSS level.
When the oscillator circuit is not used, fix the OSC1 or
OSC2 pin to the VDD or VSS level, respectively.
The oscillator signal frequency is divided and output
from the CLO pin as display clock. The frequency is
divided to one-fourth, one-eighth or one-sixteenth in the
S1D15600, S1D15601 or S1D15602, respectively.
T1
T2
Voltage
tripler
Voltage
regulator
voltage
follower
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
●
●
×
×
●
●
●
×
●
●
●
●
supply and a portion of the functions of the built-in power
supply.
When (T1, T2) = (HIGH, LOW), the boosting circuit
does not work and open the boosting circuit terminals
(CAP1+, CAP1-, CAP2+ and CAP2-) and apply liquid
crystal driving voltage to the Vout terminals from outside.
7–32
External
voltage
input
–
–
VOUT
V5
Voltage
tripler
terminals
OPEN
OPEN
VR terminals
OPEN
When (T1, T2) = (HIGH, HIGH), the boosting circuit and
voltage regulation circuit do not work and open the
boosting circuit terminals and the VR terminals and
apply liquid crystal driving voltage connecting the V5
terminals.
EPSON
Rev. 4.6
S1D15600/601/602 Series
Voltage tripler
V5=(1+ Rb ) VREG+IREF · Rb
Ra
R3+R2-∆R2
=(1+
) VREG
R1+∆R2
+IREF · (R3+R2-∆R2)
By connecting capacitors C1 between CAP1+ and
CAP1-, CAP2+ and CAP2- and VSS-Vout, the electric
potential between VDD-V SS is boosted to the triple
toward negative side and outputted from the Vout terminal. When a double boosting is required, disconnect the
capacitor between CAP2+ and CAP2- and short-circuit
the CAP2- and Vout terminals to obtain output boosted
to the double out of the Vout (or CAP2-) terminal.
Signals from the oscillation circuit are used in the boosting circuit and it then is necessary that the oscillation
circuit is in operation.
Electric potentials by the boosting functions are given
below.
VDD
R1
V REG
Ra
∆R2
+
R2
-
V5
VR IREF
(VCC =+5V) VDD =0V
(GND)
Rb
R3
VSS =–5V
VOUT =2VSS =–10V
Electric potentials of double boosting
VREG is the constant voltage source of the IC, and it is
.
constant and VREG =. –2.5 ± 0.15 V (if VDD is 0 V). To
adjust the V5 output voltage, insert a variable resistor
between VR, VDD and V5 as shown. A combination of R1
and R3 constant resistors and R2 variable resistor is
recommended for fine-adjustment of V5 voltage.
VDD =0V
VSS =–5V
Setup example of resistors R1, R2 and R3: (In case of
Type 1)
VOUT =3VSS =–15V
When the Electronic Volume Control Function is OFF
(electronic volume control register values are
(D4,D3,D2,D1,D0)=(0,0,0,0,0)):
Electric potentials of triple boosting
V5 =
Voltage Regulator
The boosting voltage occurring at VOUT is sent to the
voltage regulator, and the V5 liquid crystal display (LCD)
driver voltage is output. This V5 voltage can be determined
by the following equation when resistors Ra and Rb (R1,
R2 and R3) are adjusted within the range of |V5| < |VOUT|.
( 1 + R3 + R2 – ∆R2)
VREG .......................
R1 + ∆R2
(As IREF = 0 A)
• R1 + R2 + R3 = 5MΩ ................................ 2
(Determined by the current passing between
VDD and V5 )
• Variable voltage range by R2 V5 = –6 to –10 V
(Determined by the LCD characteristics)
∆R2 = OΩ, V REG = –2.55V
To obtain V5 = -10 V, from equation 1 :
R2 + R3 = 2.92 × R1 ..................... 3
∆R2 = R2, VREG = –2.55V
To obtain V5 = -6 V, from equation 1 :
1.35 × (R1 + R2) = R3 .................. 4
From equations 2 ,
R1=1.27MΩ
R2=0.85MΩ
R3=2.88MΩ
Rev. 4.6
1
EPSON
3
and
4
:
7–33
S1D15600/601/602 Series
The voltage regulator has a temperature gradient of
approximately -0.2%/°C as the VREG voltage. To obtain
another temperature gradient, use the Electronic Volume
Control Function for software processing using the MPU.
As the VR pin has a high input impedance, the shielded
and short lines must be protected from a noise interference.
In case of Type 2, similarly preset R1, R2 and R3 on the
basis of VREG = VSS.
The S1D15206 series have the built-in VREG reference
voltage and I REF current source which are constant
during voltage variation. However, they may change due
to the variation occurring in IC manufacturing and due to
the temperature change as shown below.
Consider such variation and temperature change, and set
the Ra and Rb appropriate to the LCD used.
VREG = –2.5V±0.15V } Type1
VREG = –0.2%/˚C
VREG = VSS
}Type2
VREG = 0.00%/˚C
VREG = –0.2%/°C
IREF = –3.2µA±40% (For 16 levels)
IREF = 0.023µA/°C
–6.5µA±40% (For 32 levels)
0.052µA/°C
Voltage regulator using the Electronic Volume
Control Function
The Electronic Volume Control Function can adjust the
intensity (brightness level) of liquid crystal display (LCD)
screen by command control of V5 LCD driver voltage.
This function sets five-bit data in the electronic volume
control register, and the V5 LCD driver voltage can be
one of 32-state voltages.
To use the Electronic Volume Control Function, issue
the Set Power Control command to simultaneously operate
both the voltage regulator circuit and voltage follower
circuit.
Also, when the boosting circuit is off, the voltage must be
supplied from VOUT terminal.
When the Electronic Volume Control Function is used,
the V5 voltage can be expressed as follows:
Ra is a variable resistor that is used to correct the V 5
voltage change due to VREG and IREF variation. Also, the
contrast adjustment is recommended for each IC chip.
Before adjusting the LCD screen contrast, set the
electronic volume control register values to
(D4,D3,D2,D1,D0)=(1,0,0,0,0) or (0,1,1,1,1) first.
When not using the Electronic Volume Control Function,
set the register values to (D4,D3,D2,D1,D0)=(0,0,0,0,0)
by sending the RES signal or the Set Electronic Volume
Control Register command.
V5 = (1 + Rb ) VREG + Rb × ∆IREF ........................
Ra
Setup example of constants when Electronic Volume
Control Function is used:
5
Variable voltage range
V5 maximum voltage:
The increased V5 voltage is controlled by use of IREF
current source of the IC. (For 32 voltage levels, ∆IREF =
IREF/31)
The minimum setup voltage of the V5 absolute value is
determined by the ratio of external Ra and Rb, and the
increased voltage by the Electronic Volume Control
Function is determined by resistor Rb. Therefore, the
resistors must be set as follows:
1) Determine Rb resistor depending on the V5 variable
voltage range by use of the Electronic Volume Control.
V 5 = –6 V (Electronic
volume control register
values (D4,D3,D2,D1,D0)
= (0,0,0,0,0))
V5 minimum voltages:
V 5 = –10 V (Electronic
volume control register
values (D4,D3,D2,D1,D0)
= (1,1,1,1,1))
V5 variable voltage range: 4 V
Variable voltage levels:
32 levels
1) Determining the Rb:
R3 =
V variable voltage range
Rb = 5
IREF
Rb = 625KΩ
2) To obtain the minimum voltage of the V5 absolute
value, determine Ra using the Rb of Step 1) above.
Ra =
Rb
V5
–1
VREG
4V
V5 variable voltage range
=
| IREF |
6.5µA
2) Determining the Ra:
Ra =
{V5 = (1 + Rb/Ra) × VREG}
Rb
=
V5max
–1
VREG
625KΩ
–6V
–1
–2.55V
Ra = 462KΩ
7–34
EPSON
Rev. 4.6
S1D15600/601/602 Series
Ta=–10°C
V5max = (1+Rb/Ra) × VREG (Ta=–10°C)
= (1+625k/462k) × (–2.55V)
× {1+(–0.2%/°C) × (–10°C–25°C)}
= –6.42V
V5min = V5max + Rb × IREF (Ta=–10°C)
= –6.42V + 625k
× {–6.5µA+(0.052µA/°C) ×
(–10°C–25°C)}
= –11.63V
S1D15600 Series V5
[V]
-10V
V5
V5 variable voltage range
(32 levels)
-5V
(VDD) 0V
-20
0
20
40
Ta
60
[¡C]
According to the V5 voltage and temperature change,
equation 5 can be as follows (if VDD = 0 V reference):
Ta=25°C
V5 max = (1+Rb/Ra) × VREG
= (1+625k/442k) × (–2.55V)
= –6.0V
V5 min = V5 max + Rb × IREF
= –6V + 625k × (–6.5µA)
= –10.0V
Rev. 4.6
Ta=–50°C
V5max = (1+Rb/Ra) × VREG (Ta=50°C)
= (1+625k/462k) × (–2.55V)
× {1+(–0.2%/°C) × (50°C–25°C)}
= –5.7V
V5min = V5max + Rb × IREF (Ta=50°C)
= –5.7V + 625k
× {–6.5µA+(0.052µA/°C) ×
(50°C–25°C)}
= –8.95V
The margin must also be determined in the same procedure
given above by considering the VREG and IREF variation.
This margin calculation results show that the V5 center
value is affected by the VREG and IREF variation. The
voltage setup width of the Electronic Volume Control
depends on the IREF variation. When the typical value of
0.2 V/step is set, for example, the maximum variation
range of 0.12 to 0.28 V must be considered.
In case of Type 2, it so becomes that VREG = VSS (VDD
basis) and there is no temperature gradient. However,
IREF carries the same temperature characteristics as with
Type 1.
EPSON
7–35
S1D15600/601/602 Series
Example of V5 Voltage When Using S1D15600/601/602 Series Electronic Volume
(V)
S1D15600/601/602 Series V5
–14
–12
–10
➃
➀
➄
➇
➁
➆
–8
∗
➂
V5
∗
➅
∗
–6
V5 Min.
–4
V5 typ
∗ V5 Max.
–2
0
–20
–10
0
10
20
Ta
Liquid Crystal Voltage Generating Circuit
A V5 potential is resistively divided within the IC to
cause V1, V2, V3 and V 4 potentials needed for driving of
liquid crystals. The V1, V 2, V3 and V4 potentials are
further converted in the impedance by the voltage follower before supplied to the liquid crystal driving circuit.
The liquid crystal driving voltage is fixed with each type.
types
30
40
50
60
(°C)
As shown in Fig. 8, it needs to connect, externally voltage
stabilizing capacitors C2 to the liquid crystal power
terminals. When selecting such capacitor C2 make
actual liquid crystal displays matching to the display
capacity of the liquid crystal display panel, before determining on the capacitance as the constant value for
voltage stabilization.
Liquid crystal driving voltage
S1D15600D00B* 1/9 bias voltage
S1D15600D10B* 1/7 bias voltage
S1D15601D00B* 1/7 bias voltage
S1D15601D10B* 1/5 bias voltage
S1D15602D00B* 1/5 bias voltage
7–36
EPSON
Rev. 4.6
S1D15600/601/602 Series
When the built-in power circuit is not used
When the built-in power circuit is used
Rf *1
osc1
VSS
M/S
osc2
C1
C1
osc1
CL
VSS
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
C1
Rf
VDD
VSS
osc2
VSS
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
VSS
VDD
M/S
CL
VSS
R3
R2
*2
VDD
V5
VR
V5
VR
S1D1560 D
* **B*
VDD
S1D1560*D**B*
R1
C2
VDD
VDD
V1
V2
V3
V4
V5
V1
V2
V3
V4
V5
External
supply
voltage
Reference set values:
.
S1D15600 V5 =
. . –11~ –13 V
S1D15601 V5 =
. . –7~ –9 V
S1D15602 V5 =. –5~ –7 V (Variable)
*2 Use short wiring or shielded cables for the VR
pin due to high input impedance.
S1D15600 S1D15601 S1D15602
C1
4.7 µF
2.2 to
4.7 µF
2.2 to
4.7 µF
C2
0.1 to
0.47 µF
0.1 to
0.47 µF
0.1 µF
R1
1 MΩ
700 kΩ
500 kΩ
R2
200 kΩ
200 kΩ
200 kΩ
R3
4 MΩ
1.6 MΩ
700 kΩ
LCD
SIZE
32×51
mm
16×67
mm
8×75
mm
DOT
64×102
32×134
16×150
Rev. 4.6
*1 Connect oscillator feedback resistor Rf as short
as possible and place it close to the IC for
preventing a malfunction.
*3 Determine C1, C2 depending on the size of LCD
panel driven. You must set these values so that
the LCD driving voltage becomes stable. Set
(T1, T2)=(HIGH, LOW) and supply an external
voltage to V OUT. Display the LCD heavy load
pattern and determine C2 so that the LCD driving
voltages (V 1 to V5) become stable. Then, set
(T1, T2)=(LOW, LOW) and determine C1.
Set the same capacitance for C2.
*4 The “LCD SIZE” indicates the vertical and
horizontal length of the LCD panel display area.
EPSON
7–37
S1D15600/601/602 Series
* Precautions when installing the COG
When installing the COG, it is necessary to duly consider
the fact that there exists a resistance of the ITO wiring
occurring between the driver chip and the externally
connected parts (such as capacitors and resistors). By the
influence of this resistance, non-conformity may occur
with the indications on the liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the driver
chip pin to the externally connected parts as much as
possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
2.
the resistance of ITO wiring is being inserted in
series with the switching transistor, thus dominating
the boosting ability.
Consequently, the boosting ability will be hindered
as a result and pay sufficient attention to the wiring
to respective boosting capacitors.
Connection of the smoothing capacitors for the
liquid crystal drive
The smoothing capacitors for the liquid crystal
driving potentials (V 1 . V 2 , V 3 and V 4) are
indispensable for liquid crystal drives not only for
the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs
pursuant to installation of the COG is supplemented
to these smoothing capacitors, the liquid crystal
driving potentials become unstable to cause nonconformity with the indications of the liquid crystal
display. Therefore, when using the COG module,
we definitely recommend to connect reinforcing
resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these
reinforcing resistors, current consumption will
increase.
Also, as for this driver IC, pay sufficient attention to the
following points when connecting to external parts for
the characteristics of the circuit.
1. Connection to the boosting capacitors The boosting
capacitors (the capacitors connecting to respective
CAP pins and capacitor being inserted between
VOUT and VSS2) of this IC are being switched over
by use of the transistor with very low ON-resistance
of about 10Ω. However, when installing the COG,
Indicated below is an exemplary connection diagram of
external resistors.
Please make sufficient evaluation work for the display
statuses with any connection tests.
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
VDD
VDD
R4
V1
V2
C2
V3
C2
R4
V2
C2
V3
C2
R4
V4
C2
V1
C2
S1D15600/601/602 Series
C2
C2
S1D15600/601/602 Series
R4
VDD
V4
R4 R4
C2
7–38
V5
C2
EPSON
V5
Rev. 4.6
S1D15600/601/602 Series
Reset
When power is turned ON, the S1D15600/601/602 series
is initialized on the rising edge of RES. Initial settings are
as follows.
1. Display
: OFF
2. Display mode
: Normal
3. n-line inversion
: OFF
4. Duty cycle
: 1/64 (S1D15600)
1/32 (S1D15601)
5. ADC select
: Normal (D0 = L)
6. Read/write modify
: OFF
7. Internal power supply
: OFF
8. Serial interface register data : Cleared
9. Display initial line register : Line 1
10. Column address counter
: 0
11. Page address register
: Page 0
12. Output selection circuit
: Case 6
13. n-line inversion register
: 16
14. Set the electronic control register to zero (0).
RES should be connected to the microprocessor reset
terminal so that both devices are reset at the same time.
RES must be LOW for at least 1 µs to correctly reset the
S1D15600/601/602 series. Normal operation starts 1 µs
after the rising edge on RES.
Rev. 4.6
If the built-in LCD power circuit of the S1D1560*D**B*
is not used, the RES signal must be low when the external
LCD power supply is turned on. When the RES goes low,
each register is cleared to the above listed initial status.
However, the oscillation circuit and output pins (OSC2,
FR, SYNC, CLD, DYO, D0 to D7 pins) are not affected.
If the S1D15600 is not properly initialized when power
is turned ON, it can lock itself into a state that cannot be
cancelled.
Although S1D15600/601/602 Series devices maintain
the operation status under commands, when external
noise of excessive levels enters, their internal statys may
be changed. Consequently, it is necessary to provide
means to suppress noise occurring from package or the
system or orovide means to avoid influence of such
noise.
Also, to cope with sudden noise, we suggest you to set up
the software so the operation status can be periodically
refreshed.
When the Reset command is used, only initial settings 9
to 14 are active.
EPSON
7–39
S1D15600/601/602 Series
8. COMMANDS
and it is set to the write status when a low pulse is entered
in this pin. The command is activated when a high pulse
is entered in the E pin. (For their timings, see Section 10
“Timing Characteristics.”) Therefore, the 68-series MPU
interface differs from the 80-series MPU interface in the
point where the RD (or E) signal is 1 (or high) during
status read and during display data read explained in the
command description and on the command table. The
following command description uses an 80-series MPU
interface example.
If the serial interface is selected, data is sequentially
entered from D7.
The Command Set
A0, RD(E) and WR(R/W) identify the data bus commands. Interpretation and execution of commands are
synchronized to the internal clock. Since a busy check is
normally not needed, commands can be processed at
high speed.
For the 80-series MPU interface, the command is activated when a low pulse is entered in the RD pin during
read or when a low pulse is entered in the WR pin during
write. While the 68-series MPU interface is set to the
read status when a high pulse is entered in the R/W pin,
Table 7. S1D15600/601/602 series command table
Command
Code
Function
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
(1)Display ON/OFF
0
1
0
1
0
1
0
1
1
1
0
1
(2)Display START
Line set
0
1
0
0
1
(3)Page address set
0
1
0
1
0
1
1
Page address
(4)Column address set;
high-order 4 bits
0
1
0
0
0
0
1
High-order
column address
(4)Column address set;
low-order 4 bits
0
1
0
0
0
0
0
Low-order
column address
(5)Status read
0
0
1
(6)Display data write
1
1
0
Write Data
Writes data in the display
RAM.
(7)Display data read
1
0
1
Read Data
Reads data from the
display RAM.
(8)ADC select
0
1
0
1
0
1
0
0
0
0
0
1
(9)Normal/reverse
display
0
1
0
1
0
1
0
0
1
1
0
1
(10)Display all points
ON/OFF
0
1
0
1
0
1
0
0
1
0
0
1
Outputs the display RAM
address for SEG.
0: Normal 1: Reversed
Displays the LCD image
in normal or reverse
mode.
0: Normal 1: Reversed
Lights all segments.
0: Normal display
1: All ON
(11)Duty select
0
1
0
1
0
1
0
1
0
0
0
1
Sets LCD drive duty (1).
0:1/24, 48 1:1/32, 64
(12)Duty +1
0
1
0
1
0
1
0
1
0
1
0
1
Sets LCD drive duty (2).
0: Normal 1: Duty+1
(13)n-line reverse
register set
0
1
0
0
0
1
1
No. of reversed
n-lines
(14)n-line reverse
register release
0
1
0
0
0
1
0
0
7–40
Determines the RAM
display line for COM 0
Dispaly start address
Status
0
EPSON
0
0
0
0
Turns the LCD display ON
and OFF
0 : OFF
1 : ON
Sets the display RAM
pages in the Page
Address register.
Sets the high order 4
bits of the display RAM
column address in the
register.
Sets the low-order 4 bits
of the display RA
column address in the
register.
0
0
Reads the status
information.
Sets the line reverse
driving and No. of
reverse lines in the line
reverse register.
Releases the line reverse
driving.
Rev. 4.6
S1D15600/601/602 Series
Command
Code
Function
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
(15)Read Modify write
0
1
0
1
1
1
0
0
0
0
0
Increments by 1 during
write of column address
counter, and set to 0
during read.
(16)End
0
1
0
1
1
1
0
1
1
1
0
Releases the Read
Modify write mode.
(17)Reset
0
1
0
1
1
1
0
0
0
1
0
Internal reset
(18)Output status
register set
0
1
0
1
1
0
0
Output status
(19)LCD Power
supply ON/OFF
0
1
0
0
0
1
0
0
1
0
0
1
0: Power OFF
1: Power ON
(20)Built-in power
supply ON/OFF
0
1
0
1
1
1
0
1
1
0
1
(21)Electronic volume
control register set
0
1
0
1
0
0
Completes the turn-on
sequence of built-in
power supply.
Sets the V5 output
voltage in the electronic
control register.
Electronic control
value
A complex command to
turn off the display and
light all indictors.
(22)Power save
Rev. 4.6
Sets the COM and SEG
status in registers.
EPSON
7–41
S1D15600/601/602 Series
(1) Display ON/OFF
Alternatively turns the display ON and OFF.
A0
E R/W
D7
RD WR
0
1
0
D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
1
1
D
Note
D = 0 Display OFF
D = 1 Display ON
(2) Display Start Line Set
Loads the RAM line address of the initial display line,
COM0, into the initial display line register. The RAM
display data becomes the top line of the LCD screen. It
is followed by the higher number lines in ascending
order, corresponding to the duty cycle. The screen can be
scrolled using this command by incrementing the line
address.
E R/W
A0 RD
D7 D6 D5 D4 D3 D2 D1 D0
WR
0
1
0
0
1
A5 A4 A3 A2 A1 A0
A3
A2
A1
A0
Page
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
(4) Column Address Set
Loads the RAM column address from the microprocessor into the column address register. The column address
is divided into two parts-4 high-order bits and 4 loworder bits.
When the microprocessor reads or writes display data to
or from RAM, column addresses are automatically
incremented, starting with the address stored in the
column address register and ending with address 166.
The page address is not incremented automatically.
A5
A4
A3
A2
A1
A0
Line address
0
0
0
0
0
0
0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
↓
↓
1
1
1
1
1
0
62
1
1
1
1
1
1
63
0
E R/W
A0 RD
D7 D6 D5 D4 D3 D2 D1 D0
WR
1
0
1
0
1
1
1
0
E
R/W
1
0
0
0
0
1
A7 A6 A5 A4
0
0
0
0
A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0 Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
↓
1
0
1
0
↓
0
1
0
1
165
(5) Status read
Indicates to the microprocessor the four S1D15600 status
conditions.
A3 A2 A1 A0
E
EPSON
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
7–42
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
(3) Page Address Set
Loads the RAM page address from the microprocessor
into the page address register. A page address, along with
a column address, defines a RAM location for writing or
reading display data. When the page address is changed,
the display status is not affected.
Page address 8 is a special use RAM area for the indicator. Only D0 is available for data exchange.
0
E
0
ON/ RES- 0
1 Busy ADC OFF
ET
0
0
0
Rev. 4.6
S1D15600/601/602 Series
BUSY
ADC
ON/OFF
RESET
Indicates whether or not the S1D15600 will
accept a command. If BUSY is 1, the device
is currently executing a command or is resetting, and no new commands can be accepted.
If BUSY is 0, a new command can be accepted. It is not necessary for the microprocessor to check the status of this bit if enough
time is allowed for the last cycle to be completed.
Indicates the relationship between RAM column addresses and the segment drivers. If
ADC is 1, the relationship is normal and
column address n corresponds to segment
driver n. If ADC is 0, the relationship is
inverted and column address (165 – n) corresponds to segment driver n.
Indicates whether the display is ON or OFF.
If ON/OFF is 1, the display is OFF. If ON/
OFF is 0, the display is ON. Note that this is
the opposite of the Display ON/OFF command.
Indicates when initialization is in process as
the result of RES or the Reset command.
(6) Display Data Write
Writes bytes of display data from the microprocessor to
the RAM location specified by the column address and
page address registers. The column address is incremented
automatically so that the microprocessor can continuously write data to the addressed page.
E
R/W
1
0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
Write data
(7) Display Data Read
Sends bytes of display data to the microprocessor from
the RAM location specified by the column address and
page address registers. The column address is incremented
automatically so that the microprocessor can continously
read data from the addressed page. A dummy read is
required after loading an address into the column address
register.
Display data cannot be read through the serial interface.
E
R/W
0
1
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
Rev. 4.6
(8) ADC Select
Selects the relationship between the RAM column addresses and the segment drivers. When reading or
writing display data, the column address is incremented
as shown in figure 4.
E
R/W
1
0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0
0
0
D
Note
D = 0 Rotate right (normal direction)
D = 1 Rotate left (reverse direction)
The output pin relationship can also be changed by the
microprocessor. There are very few restrictions on pin
assignments when constructing an LCD module.
(9) Normal/Reverse Display
Determines whether the data in RAM is displayed normally or inverted.
E R/W
A0 RD
D7 D6 D5 D4 D3 D2 D1 D0
WR
0
1
0
1
0
1
0
0
1
1
D
Note
D = 0 LCD segment is ON when RAM data is 1
(normal).
D = 1 LCD segment is ON when RAM data is 0
(inverse).
(10) Display All Points ON/OFF
Turns all LCD points ON independently of the display
data in RAM. The RAM contents are not changed.
This command has priority over the normal/inverse
display command.
A0
0
E R/W
D7
RD WR
1
0
1
D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
0
D
Note
D = 0 Normal display status
D = 1 All display segments ON
If this command is received when the display status is
OFF, the Power Save command is executed.
Read data
EPSON
7–43
S1D15600/601/602 Series
(11) Duty Select
Selects the LCD driver duty.
Since this is independent from contents of the output
status register, the duty must be selected according to the
LCD output status.
In multi-chip configuration, the master and slave devices
must have the same duty.
A0
E R/W
D7
RD WR
0
1
0
1
0
1
0
1
D
Duty
S1D15600
0
1
1/48
1/64
S1D15601
0
1
1/24
1/32
0
1
1/16
1/16
0
0
0
1
0
1
0
D
E R/W
D7
RD WR
1
0
0
D6 D5 D4 D3 D2 D1 D0
0
1
1
A3 A2 A1 A0
A3
A2
A1
A0
Number of inverted
lines
0
0
0
0
–
0
0
0
1
2
0
0
1
0
3
↓
(12) Duty + 1
Increases the duty by 1. If 1/48 or 1/64 duty is selected
in the S1D15600 for example, 1/49 or 1/65 is set, respectively and COM1 functions as either the COM48 or
COM64 output. The display line always accesses the
RAM area corresponding to page address 8, D0. (Refer
to Figure 4.)
In multi-chip configuration, the Duty + 1 command must
be executed to both the master and slave sides.
E R/W
A0 RD
D7
WR
A0
D6 D5 D4 D3 D2 D1 D0
Model
S1D15602
(13) n-line Reverse Register Set
Selects the number of inverse lines for the LCD AC
controller. The value of n is set between 2 to 16 and is
stored in the n-line inversion register.
↓
1
1
1
0
15
1
1
1
1
16
Do not use this command when using the votage follower
of the built-in power supply, the characteristics of the
built-in power supply cannot then be guaranteed to stay
within the specification.
(14) n-line Reverse Register Release
Cancels n-line inversion and restores the normal 2-frame
AC control. The contents of the n-line inversion register
are not changed.
E R/W
A0 RD
D7 D6 D5 D4 D3 D2 D1 D0
WR
D6 D5 D4 D3 D2 D1 D0
0
0
1
0
1
0
Model
D
Duty
S1D15600
0
1
1/48 or 1/64
1/49 or 1/65
S1D15601
0
1
1/24 or 1/32
1/25 or 1/33
S1D15602
0
1
1/16
1/17
1
1
0
0
0
1
0
0
0
0
0
D
(15) Read Modify Write
Following this command, the column address is no
longer incremented automatically by a Read Display
Data command. The column address is still incremented
by the Write Display Data command. This mode is
cancelled by the End command. The column address is
then returned to its value prior to the Modify Read
command. This command makes it easy to manage the
duplication of data from a particular display area for
features such as cursor blinking.
A0
0
E R/W
D7
RD WR
1
0
1
D6 D5 D4 D3 D2 D1 D0
1
1
0
0
0
0
0
Note that the Column Address Set command cannot be
used in modify-read mode.
7–44
EPSON
Rev. 4.6
S1D15600/601/602 Series
(16) End
Cancels the modify read mode. The column address
prior to the Modify Read command is restored.
Page address set.
Column address set.
E
R/W
1
0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
0
1
1
1
0
Read–modify–write cycle.
(17) Reset
Resets the initial display line, column address, page
address, and n-line inversion registers to their initial
values. This command does not affect the display data in
RAM.
Dummy read.
Data read.
A0
E R/W
D7
RD WR
D6 D5 D4 D3 D2 D1 D0
Data write.
0
No
1
0
1
1
1
0
0
0
1
0
The reset command does not initialize the LCD power
supply. Only RES can be used to initialize the supplies.
Changes
finished?
Yes
END
Figure 13.
Command sequence for
cursor blinking
Return
Column
address
N
N+1
N+2
N+3
N+m
N
Read–modify–write mode set
(18) Output Status Register Set
Available only in the S1D15600 and S1D15601.
This command selects the role of the COM/SEG dual
pins and determines the LCD driver output status.
The COM output scanning direction can be selected by
setting A3 to HIGH or LOW. For details, refer to the
Output Status Circuit in each function description.
Rev. 4.6
End
A0
0
E R/W
D7
RD WR
1
0
1
D6 D5 D4 D3 D2 D1 D0
1
0
0
A3 A2 A1 A0
A3: Selection of the COM output scanning direction
EPSON
7–45
S1D15600/601/602 Series
Number of
COM/SEG
Output pins
A2 A1 A0
Output
Status
0 0 0
Case 6
SEG 166
0 0 1
Case 5
SEG 134, COM 32
0 1 0
Case 4
SEG 134, COM 32
0 1 1
Case 3
SEG 134, COM 32
1 0 0
Case 2
SEG 102, COM 64
1 0 1
Case 1
SEG 102, COM 64
1 1 0
Case 6
SEG 166
1 1 1
Case 6
SEG 166
Sequence in the Built-in Power supply
ON/OFF Status
To turn on built-in power supply, execute the above builtin power supply ON sequence. To turn off internal power
supply execute the power save sequence as shown in the
following power supply OFF status. Accordingly, to turn
on built-in power supply again after turn it off (power
save), execute the “Power Save Clear Sequence” that
will be described afterwards.
Remarks
Applies to the
SED1560/61
Applies to the
SED1561
Built-in power supply ON status
Applies to the
SED1560
Reset by RES signal
Applies to the
SED1560/61
(19) LCD Power Supply ON/OFF
Turns the S1D1560*D**B* internal LCD power supply
ON or OFF. When the power supply is ON, the voltage
converter, the voltage regulator circuit and the voltage
followers are operating. For the converter to function,
the oscillator must also be operating.
A0 E R/W D7
RD WR
0
1
0
0
*1
Output Status Select
command
A*(H)
*2
*DUTY+1
command
AB(H)
Electronic Volume Control
setup
**(H)
Internal Power Supply ON
command
25(H)
command
ED(H)
*4,5
*3
1
0
0
1
0
Power Supply Startup End
Built-in power supply OFF status
D6 D5 D4 D3 D2 D1 D0
0
(Waiting time)
D
Display OFF
command
AE(H)
Output Status case 6
command
CF(H)
*DUTY+1 Clear
command
AA(H)
Display All ON
command
A5(H)
Note
D = 0 Supply OFF
D = 1 Supply ON
*2
When an external power supply is used with the
S1D15600D**B*, the internal supply must be OFF.
If the S1D15600D** B* is used in a multiple-chip
configu-ration, an external power supply that meets the
specifications of the LCD panel must be used. An
S1D15600 operating as a slave must have its internal
power supply turned OFF.
*1: Regarding the S1D15602, it is not necessary to
execute a command to decide an output status.
*2: When the COMI pin is not used, it is not necessary
to enter the DUTY+1 and DUTY+1 Clear commands.
*3: When the built-in power supply startup end command is not executed, current is consumed
stationarily.
Built-in power supply startup end command must
always be used in a pair with built-in power supply
ON command.
*4: The waiting time depends on the externally-installed capacitance C2 (refer to 7-37). After the
waiting time shown in Graph 1, the power supply
can be started surely.
(20) Built-in Power Supply ON/OFF
This command turns on the built-in power supply.
A0
E R/W
D7
RD WR
0
1
0
1
D6 D5 D4 D3 D2 D1 D0
1
1
0
1
1
0
1
The S1D15600 series has the built-in, low-power LCD
driving voltage generator circuit which can cut almost all
currents except those required for LCD display. This is
the primary advantage of the S1D15600 series product.
However, it has the LOW power and you need perform
the following power-on sequence when turning on the
built-in power supply:
7–46
EPSON
Rev. 4.6
S1D15600/601/602 Series
120
(ms)
100
Waiting
time
80
V5 voltage conditions
1/9 bias V5 = –6.0 to –16.0 V
1/7 bias V5 = –5.0 to –12.0 V
1/5 bias V5 = –4.5 to –8.0 V
1/9 bias
60
1/7 bias
40
20
1/5 bias
0
0.5
1.0
Capacitance C2
Graph 1
(µF)
*5: Within the waiting time in built-in power supply ON status, any command other than built-in power supply control
commands such as Power Save, and display ON/OFF command, display normal rotation/reverse command, display
all ON command, output status select command and DUTY+1 clear command can accept another command without
any problem. RAM read and write operations can be freely performed.
(21) Electronic Volume Control Register Set
Through these commands, the liquid crystal driving
voltage V 5 being outputted from the voltage regulation
circuit of the built-in liquid crystal power supply, in order
to adjust the contrast of the liquid crystal display.
By setting data to the 4 bit register, one of the 16 voltage
status may be selected for the liquid crystal driving
voltage V5 . External resistors are used for setting the
voltage regulation range of the V5. For details refer to the
paragraph of the voltage regulation circuit in the Clause
for the explanation of functions.
E
R/W
1
0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
A4 A3 A2 A1 A0
A4 A3 A2 A1 A0
| V5 |
0
0
0
:
:
0
0
Small (as the absolute value)
1
1
1
1
1
Large (as the absolute value)
When not using the electronic volume control function,
set to (0, 0, 0, 0, 0).
(22) Power Save (Complex Command)
If the Display All Points ON command is specified in the
display OFF state, the system enters the power save
status, reducing the power consumption to approximate
the static power consumption value. The internal state in
the power save status is as follows:
(a) The oscillator and power supply circuits are stopped.
Rev. 4.6
(b) The LCD driver is stopped and segment and common driver outputs output the VDD level.
(c) An input of an external clock is inhibited and OSC2
enters the high-impedance state.
(d) The display data and operation mode before execution of the power save command are held.
(e) All LCD driver voltages are fixed to the VDD level.
The power save mode is cancelled by entering either the
Display ON command or the Display All Points OFF
command (display operation state). When external voltage driver resistors are used to supply the LCD driver
voltage level, the current through them must be cut off by
the power save signal.
If an external power supply is used, it must be turned OFF
using the power save signal in the same manner and
voltage levels must be fixed to the floating or VDD level.
Sequence in the Power Save Status
Power Save and Power Save Clear must be executed
according to the following sequence.
To give a liquid crystal driving voltage level by the
externally-installed resistance dividing circuit, the current flowing in this resistance must be cut before or
concurrently with putting the S1D15600/601/602 series
into the power save status so that it may be fixed to the
floating or VDD level.
When using an external power supply, likewise, its
function must be stopped before or concurrently with
putting the S1D15600/601/602 series ino the power save
status so that it may be fixed to the floating or VDD level.
In a configurationinwhich an exclusive common driver
such as S1D16700 is combined with the S1D15600/601/
602 series, it is necessary to stop the external power
supply function after putting all the common output into
non-selection level.
EPSON
7–47
S1D15600/601/602 Series
Power save sequence
Power save clear sequence
Display OFF
command
AE(H)
Reset by RES signal
*3
Output Status case 6
command
CF(H)
*3
Output Status Select
command
C*(H)
*2
*DUTY+1 Clear
command
AA(H)
*2
*DUTY+1
command
AB(H)
*1
Display All ON
command
A5(H)
Internal Power Supply ON
command
25(H)
command
ED(H)
*1: In the power save sequence, the power save status is
provided after the display all ON command. In the
power save clear sequence, the power save status is
cleared after the display all ON status OFF command.
*2 When the COMI pin is not used, it is not necessary to
eneter the DUTY+1 command and DUTY+1 clear
command.
*3 In the S1D15602, it is not necessary to execute a
command to decide an output status.
*4 The display ON command can be executed any-
7–48
*1
Display All ON Status OFF
*6
(Waiting time)
*5
Power Supply Startup End
where if it is later than the display all ON status OFF
command.
*5 When internal power supply startup end command is
not executed, current is consumed stationarily. Internal power supply startup end command must
always be used in a pair with internal power supply
ON command.
*6 The waiting time depends on the Externally-installed
capacitance C2 (refer to 7-46). After the waiting
time shown in the above Graph 1, the power supply
can be started surely.
EPSON
Rev. 4.6
S1D15600/601/602 Series
9. COMMAND DESCRIPTION – INSTRUCTION SETUP EXAMPLES
Instruction Setup Examples
Initial setup
Note: As power is turned on, this IC outputs non-LCD-drive potentials V2 – V3 from SEG terminal (generates output
for driving the LCD) and V1 –V4 from COM terminal (also used for generating the LCD drive output). If charge
remains on the smoothing capacitor being inserted between the above LCD driving terminals, the display screen
can be blacked out momentarily. In order to avoid this trouble, it is recommended to employ the following
powering on procedure.
• When the built-in power is used immediately after the main power is turned on:
Turn on VDD and VSS power while maintaining
RES terminal at LOW.
Wait until the power supply is stabilized.
Cancel the reset mode (RES terminal = HIGH).
Turn on the initial setup mode (Default). *1
Function select through the commands (user setup).
ADC select *2
Output state register set *3
Duty select *4
Duty + 1 *5
Electronic volume *6
n-line inversion register set *7
Operations ranging from powering on
through the power control set must be
completed within 5 ms.
Function select through the command (user setup).
Built-in power supply ON *8
Waiting time *9
Function select through the command (user setup)
Powering on is complete *10
Initial setup is complete
* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned.
Check them on the actual system.
Notes: *1:
*2:
*3:
*4:
*5:
*6:
Refer to the “Reset Circuit” in the Function Description.
Refer to the “ADC Select” in the Command Selection (8).
Refer to the “Output State Register Set” in the Command Description (18).
Refer to the “Duty Select” in the Command Description (11).
Refer to the “Duty + 1” in the Command Description.
Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in
the Command Description (21).
*7: Refer to the “n-line Inversion Register Set” in the Command Description (13).
*8: Refer to the “Built-in Power Supply ON/OFF” in the Command Description (21).
*9: Refer to the “Built-in Power Supply ON/OFF Sequence” in the Command Description.
*10: Refer to the “Built-in Power Supply ON Complete” in the Command Description (20).
Rev. 4.6
EPSON
7–49
S1D15600/601/602 Series
• When the built-in power supply is not used immediately after the main power is turned on:
Turn VDD and VSS power on with RES terminal being set to LOW.
Wait until the power supply is stabilized.
Cancel the reset mode (RES terminal = HIGH)
Turn on the initial setup mode (Default) *1
The power save mode
must be turned on within
5 ms from powering on.
Implement the power save sequence (multiple commands) *11
Function select through the commands (user setup)
ADC select *2
Output state register set *3
Duty select *4
Electronic volume *6
n-line inversion register set *7
Implement the power save cancel sequence *12
Initial setup is complete
* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned. Check
them on the actual system.
Notes: *1:
*2:
*3:
*4:
*6:
Refer to the “Reset Circuit” in the Function Description.
Refer to the “ADC Select” in the Command Description (8).
Refer to the “Output State Register Set” in the Command Description (18)
Refer to the “Duty Select” in the Command Description (11).
Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in
the Command Description (21).
*7: Refer to the “n-line Inversion Register Set” in the Command Description (13).
*8: Refer to the “Built-in Power Supply ON/OFF” in the Command Description (19).
*11,12: You can select either the sleep mode or standby mode for the power save mode. Refer to the “Power
Save (Multiple Commands)” in the Command Description (22).
7–50
EPSON
Rev. 4.6
S1D15600/601/602 Series
• Data Display
Initial setup is complete
Function select through the commands (user setup)
Display start line set *13
Page address set *14
Column address set *15
Function select through the command (user setup)
Display data write *16
Function select through the command (user setup)
Display ON/OFF *17
Data display is complete
Notes: *13: Refer to the “Display Line Set” in the Command Description (2).
*14: Refer to the “Page Address Set” in the Command Description (3).
*15: Refer to the “Column Address Set” in the Command Description (4).
*16: Refer to the “Display Data Write” in the Command Description (6).
*17: Refer to the “Display ON/OFF” in the Command Description (1).
It is recommended to avoid the all-white-display of the display start data.
• Powering Off *18
Any state
Function select through the command (user setup)
Power save sequence *19
Turn VDD and VSS power
The time spent for the operations ranging from power
save through powering off (VDD – VSS = 2.4V) (tL)
must be longer than the time required for V5 to V1 go
under the LCD panel threshold voltage (normally 1V).
* tH is determined by time constant of the external
resisters Ra and Rb (for adjusting voltages V5 to V1)
and the smoothing capacitor C2.
* It is recommended to cut tL shorter by connecting a
resistor between VDD and V5.
Notes: *18: This IC functions as the logic circuit of the power supplies VDD – VSS, and used for controlling the
driver of LCD power supplies VDD – V5. Thus, if power supplies VDD – VSS are turned off while
voltage is still present on LCD power supplies VDD – V5, drivers (COM and SEG) may output
uncontrolled voltage. Therefore, you are required to observe the following powering off procedure:
Turn the built-in power supply off, then turn off the IC power supplies (VDD – VSS) only after making
sure that potential of V5 – V1 is below the LCD panel threshold voltage level. Refer to the “Supply
Circuit” in the Function Description.
*19: When the power save command is entered, you must not implement reset from RES terminal until VDD –
VSS power are turned off. Refer to the “Power Save” in the Command Description.
• Refresh
It is recommended that the operating modes and display contens be refreshed periodically,to prevent the effect of
unexpected noise. This sequence, however, must not be turned on as long as the initial setup, data display or powering
off sequence is taking place.
Refresh sequence
Set every command according to the state being selected
(including setup of the default state).
Refresh the DDRAM.
Rev. 4.6
EPSON
7–51
S1D15600/601/602 Series
Connection between LCD drivers
The LCD display area can be increased by using the
S1D15600/601/602 series in a multiple-chip configuration
or with the S1D15600/601/602 series special common
driver (S1D16300).
Application with external Driver
S1D1560*D**B*–S1D16300
VDD
FR
S1D16300
DIO
FR
SYNC
YSCL
S1D1560 D B
(Master)
* ** *
OSC1 OSC2
CL
M/S
CLO DYO
Rf
VSS
S1D1560*D**B*–S1D1560*D**B*
(when oscillator circuit is used)
VDD
S1D1560 D B
(Master)
M/S
* ** *
OSC1 OSC2
FR
FR
SYNC
SYNC
CL CLO DYO
S1D1560 D
(Slave)
* **B*
OSC1 OSC2
VSS
CL CLO DYO
VSS
Rf
M/S
VSS
VDD
S1D1560 D00
(Master)
M/S
*
OSC1 OSC2
*
FR
FR
SYNC
SYNC
CL CLO DYO
VDD
VSS
Rf
S1D1560 D00
(Slave)
*
OSC1 OSC2
*
M/S
CL CLO DYO
VSS
S1D1560*D**B*–S1D1560 *D**B* (External clock)
VDD
S1D1560 D B
(Master)
M/S
* ** *
OSC1 OSC2
FR
FR
SYNC
SYNC
CL CLO DYO
VDD
VSS
S1D1560 D00
(Slave)
OSC1 OSC2
*
*
M/S
VSS
CL CLO DYO
VSS
External clock
7–52
EPSON
Rev. 4.6
S1D15600/601/602 Series
Microprocessor Interface
The S1D15600/601/602 series interfaces to either 8080or 6800-series microprocessors. The number of
connections to the microprocessor can be minimized by
using a serial interface. When used in a multiple-chip
configuration, the S1D15600 is controlled by the chip
select signals from the microprocessor.
8080-series microprocessors
VCC
A0
A0
VDD
C86
A1 to A7
MPU
Decoder
IORQ
D0 to D7
GND
CS1
CS2
S1D15600
D0 to D7
RD
WR
RES
RD
WR
RES
P/S
VSS
RESET
6800-series microprocessors
VCC
A0
A0
VDD
C86
A0 to A15
MPU
Decoder
VMA
D0 to D7
GND
CS1
CS2
S1D15600
D0 to D7
E
R/W
RES
E
R/W
RES
VSS
A0
VDD
P/S
RESET
Serial interface
VCC
A0
C86
A0 to A7
Decoder
MPU
CS1
CS2
PORT1
PORT2
SI
SCL
RES
RES
S1D15600
VDD
or
GND
P/S
GND
VSS
RESET
Rev. 4.6
EPSON
7–53
S1D15600/601/602 Series
LCD Panel Interface Examples
Single-chip configurations
65 x 102
Segments
Commons
S1D15600
(Master)
Case 1
17 x 150
33 x 134
Segments
Commons
Segments
S1D15601
(Master)
Commons
S1D15602
Case 4
Multiple-chip configurations
65 x 268
Segments
Commons
Segments
S1D15600
(Master)
S1D15600
(Slave)
Case 1
Case 6
33 x 300
Segments
Commons
7–54
Segments
S1D15601
(Master)
S1D15601
(Slave)
Case 4
Case 6
EPSON
Rev. 4.6
S1D15600/601/602 Series
Special Common Driver Configurations
S1D
16702
65 x 166
Commons
Segments
S1D15600
(Master)
Case 6
* If an external amp circuit is configured,
we recommend to use the S1F76600
and S1F76610.
Rev. 4.6
EPSON
7–55
S1D15600/601/602 Series
SED1560T TCP Pin Layout
This drawing is not for specifying the TCP outline shape.
O0
S1D15600
TOP
VIEW
V5
V4
V3
V2
V1
V DD
VR
V5
V OUT
CAP2–
CAP2+
CAP1–
CAP1+
V SS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
D4
D3
D2
D1
D0
V SS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
V DD
V1
V2
V3
V4
V5
O165
COMI
7–56
EPSON
Rev. 4.6
Output terminal pattern shape
SR batten
PI batten
(Mold, marking area)
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 35µm
• Sn plating
• Product pitch: 111P (52.25mm)
• Solder resist positional tolerance: ±0.3
(Punching hole
for good product)
S1D15600/601/602 Series
TCP DIMENSIONS (2 ways)
Rev. 4.6
EPSON
7–57
(Mold, marking area)
S1D15600/601/602 Series
TCP DIMENSIONS (4 ways)
7–58
EPSON
Rev. 4.6
8. S1D15605 Series
Rev. 2.4a
Contents
1. DESCRIPTION ................................................................................................................................................ 8-1
2. FEATURES ...................................................................................................................................................... 8-1
3. BLOCK DIAGRAM ........................................................................................................................................... 8-3
4. PAD ................................................................................................................................................................. 8-4
5. PIN DESCRIPTIONS .....................................................................................................................................8-20
6. DESCRIPTION OF FUNCTIONS .................................................................................................................. 8-24
7. COMMANDS .................................................................................................................................................8-49
8. COMMAND DESCRIPTION .......................................................................................................................... 8-58
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 8-64
10. DC CHARACTERISTICS ...............................................................................................................................8-65
11. TIMING CHARACTERISTICS .......................................................................................................................8-73
12. THE MPU INTERFACE (REFERENCE EXAMPLES) ...................................................................................8-81
13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) ..................................................... 8-82
14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) .................................................. 8-83
15. A SAMPLE TCP PIN ASSIGNMENT .............................................................................................................8-84
16. EXTERNAL VIEW OF TCP PINS .................................................................................................................. 8-85
–i–
Rev. 2.4a
S1D15605 Series
1. DESCRIPTION
The S1D15605 Series is a series of single-chip dot matrix
liquid crystal display drivers that can be connected
directly to a microprocessor bus. 8-bit parallel or serial
display data sent from the microprocessor is stored in
the internal display data RAM and the chip generates a
liquid crystal drive signal independent of the microprocessor. Because the chips in the S1D15605 *****
contain 65 × 132 bits of display data RAM and there is
a 1-to-1 correspondence between the liquid crystal
panel pixels and the internal RAM bits, these chips
enable displays with a high degree of freedom.
The S1D15606***** chips contain 49 common output
circuits and 132 segment output circuits, so that a single
chip can drive a 49 × 132 dot display (capable of
displaying 8 columns × 4 rows of a 16 × 16 dot kanji
font). The S1D15607***** chips contain 33 common
output circuits and 132 segment output circuits, so that
a single chip can drive 33 × 132 dot display (capable of
displaying 8 columns × 2 rows of 16 × 16 dot kanji
fonts). Thanks to the built-in 55 common output circuits
and 132 segment output circuits, the S1D15608*****
is capable of displaying 55 × 132 dots (11 columns × 4
lines using 11 × 12 dots Kanji font) with a single chip.
The S1D15609***** chips contain 53 common output
circuits and 132 segment output circuits, so that a single
chip can drive 53 × 132 dot display (capable of displaying
11 columns × 4 rows of 11 × 12 dot kanji fonts).
Moreover, the capacity of the display can be extended
through the use of master/slave structures between
chips.
The chips are able to minimize power consumption
because no external operating clock is necessary for the
display data RAM read/write operation. Furthermore,
because each chip is equipped internally with a lowpower liquid crystal driver power supply, resistors for
liquid crystal driver power voltage adjustment and a
display clock CR oscillator circuit, the S1D15605 Series
chips can be used to create the lowest power display
system with the fewest components for highperformance portable devices.
2. FEATURES
• Direct display of RAM data through the display data
RAM.
RAM bit data: “1” Display on
“0” Display off
(during normal display)
• RAM capacity
65 × 132 = 8580 bits
• Display driver circuits
S1D15605 ***** :65 common output and 132
segment outputs
S1D15606 ***** :49 common output and 132
segment outputs
S1D15607 *****:33 common outputs and 132
segment outputs
S1D15608 *****:55 common outputs and 132
segment outputs
S1D15609 *****:53 common outputs and 132
segment outputs
Rev. 2.4a
• High-speed 8-bit MPU interface (The chip can be
connected directly to the both the 80x86 series MPUs
and the 68000 series MPUs)
/Serial interfaces are supported.
• Abundant command functions
Display data Read/Write, display ON/OFF, Normal/
Reverse display mode, page address set, display start
line set, column address set, status read, display all
points ON/OFF, LCD bias set, electronic volume,
read/modify/write, segment driver direction select,
power saver, static indicator, common output status
select, V5 voltage regulation internal resistor ratio
set.
• Static drive circuit equipped internally for indicators.
(1 system, with variable flashing speed.)
• Low-power liquid crystal display power supply circuit
equipped internally.
Booster circuit (with Boost ratios of Double/Triple/
Quad, where the step-up voltage reference power
supply can be input externally)
High-accuracy voltage adjustment circuit (Thermal
gradient –0.05%/°C or –0.2%/°C or external input)
V5 voltage regulator resistors equipped internally,
V1 to V4 voltage divider resistors equipped internally,
electronic volume function equipped internally,
voltage follower.
• CR oscillator circuit equipped internally (external
clock can also be input)
• Extremely low power consumption
Operating power when the built-in power supply is
used (an example)
S1D15605D00B* 81 µA (VDD – VSS = VDD – VSS2=
/S1D15605D11B* 3.0 V, Quad voltage, V5 – VDD =
–11.0 V)
S1D15606D00B* 43 µA (VDD – VSS = VDD – VSS2 =
/S1D15606D11B* 3.0 V, Triple voltage, V5 – VDD =
–8.0 V)
S1D15607D00B* 29 µA (VDD – VSS = VDD – VSS2 =
/S1D15607D11B* 3.0 V, Triple voltage, V5 – VDD =
–8.0 V)
S1D15608D00B*/S1D15608D11B*
/S1D15609D00B*/S1D15609D11B*
46µA (VDD – VSS = VDD – VSS2 =
3.0 V, Triple voltage, V5 – VDD =
– 8.0 V)
Conditions: When all displays are in white and the
normal mode is selected (see page 60 *12 for details
of the conditions).
• Power supply
Operable on the low 1.8 voltage
Logic power supply VDD – VSS = 1.8 V to 5.5 V
Boost reference voltage: V DD – VSS2 = 1.8 V to
6.0 V
Liquid crystal drive power supply: V5 – VDD = –4.5
V to –16.0 V
• Wide range of operating temperatures: –40 to 85°C
• CMOS process
• Shipping forms include bare chip and TCP.
• These chips not designed for resistance to light or
resistance to radiation.
EPSON
8–1
S1D15605 Series
Series Specifications
Bare chip
Product Name
Duty
Bias
SEG Dr
COM Dr
S1D15605D00B*
S1D15605D11B*
S1D15605D11E*
S1D15605D01B*
S1D15605D02B*
S1D15606D00B*
S1D15606D01B*
S1D15606D02B*
S1D15606D11B*
S1D15607D00B*
S1D15607D01B*
S1D15607D02B*
S1D15607D11B*
S1D15608D00B*
S1D15609D00B*
1/65
1/65
1/65
1/65
1/65
1/49
1/49
1/49
1/49
1/33
1/33
1/33
1/33
1/55
1/53
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/8, 1/6
1/8, 1/6
1/8, 1/6
1/8, 1/6
1/6, 1/5
1/6, 1/5
1/6, 1/5
1/6, 1/5
1/8, 1/6
1/8, 1/6
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
65
65
65
65
65
49
49
49
49
33
33
33
33
55
53
VREG Temperature
Gradient
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.2%/°C
External Input
–0.05%/°C
–0.2%/°C
External Input
–0.05%/°C
–0.05%/°C
–0.2%/°C
External Input
–0.05%/°C
–0.05%/°C
–0.05%/°C
Chip
Thickness
625 µm
625 µm
300 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
TCP
Product Name
Duty
Bias
SEG Dr
COM Dr
1/65
1/9, 1/7
132
65
S1D15605T00**
1/49
1/8, 1/6
132
49
S1D15606T00**
1/33
1/6, 1/5
132
33
S1D15607T00**
Product name of custom TCP can be coped with specially.
8–2
EPSON
VREG Temperature Gradient
–0.05%/°C
–0.05%/°C
–0.05%/°C
Rev. 2.4a
S1D15605 Series
3. BLOCK DIAGRAM
COMS
• • • • • • • • • •
COM63
COM0
• • • • • • • • • • • • • • • • • • • • • • • • •
SEG131
SEG0
Example: S1D15605 *****
VSS
VDD
V2
V3
SEG Drivers
COMS
V1
COM Drivers
V4
V5
Shift register
CAP1+
Display data latch circuit
VSS2
VR
Display timing generation circuit
Power
supply
circuit
Line address circuit
VOUT
Page address circuit
CAP2+
CAP2–
CAP3+
I/O buffer
CAP1–
Display data RAM
132 x 65
VRS
IRS
HPM
FRS
FR
CL
DOF
M/S
Oscillator
circuit
Column address circuit
Bus holder
Command decoder
CLS
Status
Rev. 2.4a
EPSON
D0
D1
D2
D3
D4
D5
D6 (SCL)
D7 (SI)
RES
P/S
WR (R/W)
RD (E)
A0
CS2
CS1
MPU interface
8–3
S1D15605 Series
4. PAD
Pad Layout
99
1
100
309
Die No.
(0, 0)
D1565D0B
S1D15605 Series
275
134
135
8–4
274
Chip Size
10.82 mm × 2.81 mm
Chip Thickness
0.625 mm
Bump Pitch
71 µm (Min.)
Bump Size
PAD No. 1~24
PAD No. 25~82
PAD No. 83~99
PAD No. 100
PAD No. 101~133
PAD No. 134
PAD No. 135
PAD No. 136~273
PAD No. 274
PAD No. 275
PAD No. 276~308
PAD No. 309
Bump Height
17 µm (Typ.)
EPSON
85 µm ×
64 µm ×
85 µm ×
85 µm ×
85 µm ×
85 µm ×
73 µm ×
47 µm ×
73 µm ×
86 µm ×
85 µm ×
85 µm ×
85 µm
85 µm
85 µm
73 µm
47 µm
73 µm
85 µm
85 µm
85 µm
73 µm
47 µm
73 µm
Rev. 2.4a
S1D15605 Series
S1D15605***** Pad Center Coordinates
Units: µm
PAD
PIN
No.
Name
1
(NC)
2
FRS
3
FR
4
CL
5
DOF
6
TEST0
7
V SS
8
CS1
9
CS2
10
VDD
11
RES
12
A0
13
V SS
14 WR, R/W
15
RD, E
16
VDD
17
D0
18
D1
19
D2
20
D3
21
D4
22
D5
23 D6, SCL
24
D7, SI
25
(NC)
26
VDD
27
VDD
28
VDD
29
VDD
30
V SS
31
V SS
32
V SS
33
V SS2
34
V SS2
35
V SS2
36
V SS2
37
(NC)
38
VOUT
39
VOUT
40
CAP3–
Rev. 2.4a
X
Y
4973
4853
4734
4614
4494
4375
4255
4136
4016
3896
3777
3657
3538
3418
3298
3179
3059
2940
2820
2700
2581
2461
2342
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
873
784
1246
PAD
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN
Name
CAP3–
(NC)
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
CAP2+
V SS
V SS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
TEST1
TEST1
TEST2
TEST2
(NC)
TEST3
TEST3
TEST4
X
Y
695
605
516
427
338
249
160
71
–18
–107
–196
–285
–374
–463
–552
–641
–730
–819
–908
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
–2155
–2244
–2333
–2422
–2511
–2600
–2689
–2778
1246
EPSON
PAD
No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PIN
Name
TEST4
(NC)
V DD
M/S
CLS
VSS
C86
P/S
V DD
HPM
VSS
IRS
V DD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
X
Y
–2867
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
–4375
–4494
–4614
–4734
–4853
–4973
–5252
1246
1248
1163
1090
1017
945
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
8–5
S1D15605 Series
Units: µm
PAD
No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
8–6
PIN
Name
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
X
Y
–5252
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–1246
–5009
–4924
–4853
–4781
–4709
–4637
–4565
–4493
–4421
–4349
–4277
–4206
–4134
–4062
–3990
–3918
–3846
–3774
–3702
–3630
–3559
–3487
–3415
–3343
–3271
–3199
PAD
No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PIN
Name
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
X
Y
–3127
–3055
–2983
–2912
–2840
–2768
–2696
–2624
–2552
–2480
–2408
–2336
–2265
–2193
–2121
–2049
–1977
–1905
–1833
–1761
–1689
–1618
–1546
–1474
–1402
–1330
–1258
–1186
–1114
–1042
–971
–899
–827
–755
–683
–611
–539
–467
–395
–324
–1246
EPSON
PAD
PIN
No.
Name
201 SEG62
202 SEG63
203 SEG64
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
219 SEG80
220 SEG81
221 SEG82
222 SEG83
223 SEG84
224 SEG85
225 SEG86
226 SEG87
227 SEG88
228 SEG89
229 SEG90
230 SEG91
231 SEG92
232 SEG93
233 SEG94
234 SEG95
235 SEG96
236 SEG97
237 SEG98
238 SEG99
239 SEG100
240 SEG101
X
Y
–252
–180
–108
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
1042
1114
1186
1258
1330
1402
1474
1546
1618
1689
1761
1833
1905
1977
2049
2121
2193
2265
2336
2408
2480
2552
–1246
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
PIN
Name
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
(NC)
(NC)
(NC)
(NC)
(NC)
COM32
COM33
COM34
COM35
COM36
Rev. 2.4a
X
Y
2624
2696
2768
2840
2912
2983
3055
3127
3199
3271
3343
3415
3487
3558
3630
3702
3774
3846
3918
3990
4062
4134
4206
4277
4349
4421
4493
4565
4637
4709
4781
4853
4924
5009
5252
–1246
PAD
No.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
PIN
Name
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
(NC)
X
Y
5252
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
–1248
–1163
–1090
–1018
–945
–872
EPSON
8–7
S1D15605 Series
S1D15606***** Pad Center Coordinates
Units: µm
PAD
PIN
No.
Name
1
(NC)
2
FRS
3
FR
4
CL
5
DOF
6
TEST0
7
VSS
8
CS1
9
CS2
10
VDD
11
RES
12
A0
13
VSS
14 WR, R/W
15
RD, E
16
VDD
17
D0
18
D1
19
D2
20
D3
21
D4
22
D5
23 D6, SCL
24
D7, SI
25
(NC)
26
VDD
27
VDD
28
VDD
29
VDD
30
VSS
31
VSS
32
VSS
33
VSS2
34
VSS2
35
VSS2
36
VSS2
37
(NC)
38
V OUT
39
V OUT
40
CAP3–
8–8
X
Y
4973
4853
4734
4614
4494
4375
4255
4136
4016
3896
3777
3657
3538
3418
3298
3179
3059
2940
2820
2700
2581
2461
2342
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
873
784
1246
PAD
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN
Name
CAP3–
(NC)
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
CAP2+
VSS
VSS
V RS
V RS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
TEST1
TEST1
TEST2
TEST2
(NC)
TEST3
TEST3
TEST4
X
Y
695
605
516
427
338
249
160
71
–18
–107
–196
–285
–374
–463
–552
–641
–730
–819
–908
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
–2155
–2244
–2333
–2422
–2511
–2600
–2689
–2778
1246
EPSON
PAD
No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PIN
Name
TEST4
(NC)
VDD
M/S
CLS
V SS
C86
P/S
VDD
HPM
V SS
IRS
VDD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
(NC)
(NC)
COM23
(NC)
COM22
(NC)
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
X
Y
–2867
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
–4375
–4494
–4614
–4734
–4853
–4973
–5252
1246
1248
1163
1090
1017
945
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
PIN
Name
COM7
COM6
COM5
COM4
COM3
COM2
COM1
(NC)
COM0
(NC)
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
Rev. 2.4a
X
Y
–5252
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–1246
–5009
–4924
–4853
–4781
–4709
–4637
–4565
–4493
–4421
–4349
–4277
–4206
–4134
–4062
–3990
–3918
–3846
–3774
–3702
–3630
–3559
–3487
–3415
–3343
–3271
–3199
PAD
No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PIN
Name
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
X
Y
–3127
–3055
–2983
–2912
–2840
–2768
–2696
–2624
–2552
–2480
–2408
–2336
–2265
–2193
–2121
–2049
–1977
–1905
–1833
–1761
–1689
–1618
–1546
–1474
–1402
–1330
–1258
–1186
–1114
–1042
–971
–899
–827
–755
–683
–611
–539
–467
–395
–324
–1246
EPSON
PAD
PIN
No.
Name
201 SEG62
202 SEG63
203 SEG64
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
219 SEG80
220 SEG81
221 SEG82
222 SEG83
223 SEG84
224 SEG85
225 SEG86
226 SEG87
227 SEG88
228 SEG89
229 SEG90
230 SEG91
231 SEG92
232 SEG93
233 SEG94
234 SEG95
235 SEG96
236 SEG97
237 SEG98
238 SEG99
239 SEG100
240 SEG101
X
Y
–252
–180
–108
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
1042
1114
1186
1258
1330
1402
1474
1546
1618
1689
1761
1833
1905
1977
2049
2121
2193
2265
2336
2408
2480
2552
–1246
8–9
S1D15605 Series
Units: µm
PAD
No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
8–10
PIN
Name
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
COM24
(NC)
COM25
X
Y
2624
2696
2768
2840
2912
2983
3055
3127
3199
3271
3343
3415
3487
3558
3630
3702
3774
3846
3918
3990
4062
4134
4206
4277
4349
4421
4493
4565
4637
4709
4781
4853
4924
5009
5252
–1246
PAD
No.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
PIN
Name
(NC)
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
(NC)
COM47
(NC)
COMS
(NC)
(NC)
(NC)
X
Y
5252
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
–1248
–1163
–1090
–1018
–945
–872
EPSON
Rev. 2.4a
S1D15605 Series
S1D15607***** Pad Center Coordinates
Units: µm
PAD
PIN
No.
Name
1
(NC)
2
FRS
3
FR
4
CL
5
DOF
6
TEST0
7
V SS
8
CS1
9
CS2
10
VDD
11
RES
12
A0
13
V SS
14 WR, R/W
15
RD, E
16
VDD
17
D0
18
D1
19
D2
20
D3
21
D4
22
D5
23 D6, SCL
24
D7, SI
25
(NC)
26
VDD
27
VDD
28
VDD
29
VDD
30
V SS
31
V SS
32
V SS
33
V SS2
34
V SS2
35
V SS2
36
V SS2
37
(NC)
38
VOUT
39
VOUT
40
CAP3–
Rev. 2.4a
X
Y
4973
4853
4734
4614
4494
4375
4255
4136
4016
3896
3777
3657
3538
3418
3298
3179
3059
2940
2820
2700
2581
2461
2342
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
873
784
1246
PAD
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN
Name
CAP3–
(NC)
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
CAP2+
VSS
VSS
VRS
VRS
V DD
V DD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
V DD
V DD
TEST1
TEST1
TEST2
TEST2
(NC)
TEST3
TEST3
TEST4
X
Y
695
605
516
427
338
249
160
71
–18
–107
–196
–285
–374
–463
–552
–641
–730
–819
–908
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
–2155
–2244
–2333
–2422
–2511
–2600
–2689
–2778
1246
EPSON
PAD
No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PIN
Name
TEST4
(NC)
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
COM15
COM15
COM14
COM14
COM13
COM13
COM12
COM12
COM11
COM11
COM10
COM10
COM9
COM9
COM8
COM8
COM7
COM7
COM6
COM6
X
Y
–2867
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
–4375
–4494
–4614
–4734
–4853
–4973
–5252
1246
1248
1163
1090
1017
945
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
8–11
S1D15605 Series
Units: µm
PAD
No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
8–12
PIN
Name
COM5
COM5
COM4
COM4
COM3
COM3
COM2
COM2
COM1
COM1
COM0
COM0
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
X
Y
–5252
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–1246
–5009
–4924
–4853
–4781
–4709
–4637
–4565
–4493
–4421
–4349
–4277
–4206
–4134
–4062
–3990
–3918
–3846
–3774
–3702
–3630
–3559
–3487
–3415
–3343
–3271
–3199
PAD
No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PIN
Name
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
X
Y
–3127
–3055
–2983
–2912
–2840
–2768
–2696
–2624
–2552
–2480
–2408
–2336
–2265
–2193
–2121
–2049
–1977
–1905
–1833
–1761
–1689
–1618
–1546
–1474
–1402
–1330
–1258
–1186
–1114
–1042
–971
–899
–827
–755
–683
–611
–539
–467
–395
–324
–1246
EPSON
PAD
PIN
No.
Name
201 SEG62
202 SEG63
203 SEG64
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
219 SEG80
220 SEG81
221 SEG82
222 SEG83
223 SEG84
224 SEG85
225 SEG86
226 SEG87
227 SEG88
228 SEG89
229 SEG90
230 SEG91
231 SEG92
232 SEG93
233 SEG94
234 SEG95
235 SEG96
236 SEG97
237 SEG98
238 SEG99
239 SEG100
240 SEG101
X
Y
–252
–180
–108
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
1042
1114
1186
1258
1330
1402
1474
1546
1618
1689
1761
1833
1905
1977
2049
2121
2193
2265
2336
2408
2480
2552
–1246
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
PIN
Name
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
(NC)
(NC)
(NC)
(NC)
(NC)
COM16
COM16
COM17
COM17
COM18
Rev. 2.4a
X
Y
2624
2696
2768
2840
2912
2983
3055
3127
3199
3271
3343
3415
3487
3558
3630
3702
3774
3846
3918
3990
4062
4134
4206
4277
4349
4421
4493
4565
4637
4709
4781
4853
4924
5009
5252
–1246
PAD
No.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
PIN
Name
COM18
COM19
COM19
COM20
COM20
COM21
COM21
COM22
COM22
COM23
COM23
COM24
COM24
COM25
COM25
COM26
COM26
COM27
COM27
COM28
COM28
COM29
COM29
COM30
COM30
COM31
COM31
COMS
(NC)
X
Y
5252
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
–1248
–1163
–1090
–1018
–945
–872
EPSON
8–13
S1D15605 Series
S1D15608***** Pad Center Coordinates
Units: µm
PAD
PIN
No.
Name
1
(NC)
2
FRS
3
FR
4
CL
5
DOF
6
TEST0
7
VSS
8
CS1
9
CS2
10
VDD
11
RES
12
A0
13
VSS
14 WR, R/W
15
RD, E
16
VDD
17
D0
18
D1
19
D2
20
D3
21
D4
22
D5
23 D6, SCL
24
D7, SI
25
(NC)
26
VDD
27
VDD
28
VDD
29
VDD
30
VSS
31
VSS
32
VSS
33
VSS2
34
VSS2
35
VSS2
36
VSS2
37
(NC)
38
V OUT
39
V OUT
40
CAP3–
8–14
X
Y
4973
4853
4734
4614
4494
4375
4255
4136
4016
3896
3777
3657
3538
3418
3298
3179
3059
2940
2820
2700
2581
2461
2342
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
873
784
1246
PAD
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN
Name
CAP3–
(NC)
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
CAP2+
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
TEST1
TEST1
TEST2
TEST2
(NC)
TEST3
TEST3
TEST4
X
Y
695
605
516
427
338
249
160
71
–18
–107
–196
–285
–374
–463
–552
–641
–730
–819
–908
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
–2155
–2244
–2333
–2422
–2511
–2600
–2689
–2778
1246
EPSON
PAD
No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PIN
Name
TEST4
(NC)
VDD
M/S
CLS
V SS
C86
P/S
VDD
HPM
V SS
IRS
VDD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
(NC)
COM26
(NC)
COM25
COM25
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
X
Y
–2867
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
–4375
–4494
–4614
–4734
–4853
–4973
–5252
1246
1248
1163
1090
1017
945
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
PIN
Name
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
(NC)
COM0
(NC)
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
Rev. 2.4a
X
Y
–5252
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–1246
–5009
–4924
–4853
–4781
–4709
–4637
–4565
–4493
–4421
–4349
–4277
–4206
–4134
–4062
–3990
–3918
–3846
–3774
–3702
–3630
–3559
–3487
–3415
–3343
–3271
–3199
PAD
No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PIN
Name
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
X
Y
–3127
–3055
–2983
–2912
–2840
–2768
–2696
–2624
–2552
–2480
–2408
–2336
–2265
–2193
–2121
–2049
–1977
–1905
–1833
–1761
–1689
–1618
–1546
–1474
–1402
–1330
–1258
–1186
–1114
–1042
–971
–899
–827
–755
–683
–611
–539
–467
–395
–324
–1246
EPSON
PAD
PIN
No.
Name
201 SEG62
202 SEG63
203 SEG64
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
219 SEG80
220 SEG81
221 SEG82
222 SEG83
223 SEG84
224 SEG85
225 SEG86
226 SEG87
227 SEG88
228 SEG89
229 SEG90
230 SEG91
231 SEG92
232 SEG93
233 SEG94
234 SEG95
235 SEG96
236 SEG97
237 SEG98
238 SEG99
239 SEG100
240 SEG101
X
Y
–252
–180
–108
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
1042
1114
1186
1258
1330
1402
1474
1546
1618
1689
1761
1833
1905
1977
2049
2121
2193
2265
2336
2408
2480
2552
–1246
8–15
S1D15605 Series
Units: µm
PAD
No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
8–16
PIN
Name
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
COM27
(NC)
COM28
(NC)
X
Y
2624
2696
2768
2840
2912
2983
3055
3127
3199
3271
3343
3415
3487
3558
3630
3702
3774
3846
3918
3990
4062
4134
4206
4277
4349
4421
4493
4565
4637
4709
4781
4853
4924
5009
5252
–1246
PAD
No.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
PIN
Name
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM48
COM50
COM51
COM52
COM53
(NC)
COMS
(NC)
(NC)
X
Y
5252
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
–1248
–1163
–1090
–1018
–945
–872
EPSON
Rev. 2.4a
S1D15605 Series
S1D15609***** Pad Center Coordinates
Units: µm
PAD
PIN
No.
Name
1
(NC)
2
FRS
3
FR
4
CL
5
DOF
6
TEST0
7
V SS
8
CS1
9
CS2
10
VDD
11
RES
12
A0
13
V SS
14 WR, R/W
15
RD, E
16
VDD
17
D0
18
D1
19
D2
20
D3
21
D4
22
D5
23 D6, SCL
24
D7, SI
25
(NC)
26
VDD
27
VDD
28
VDD
29
VDD
30
V SS
31
V SS
32
V SS
33
V SS2
34
V SS2
35
V SS2
36
V SS2
37
(NC)
38
VOUT
39
VOUT
40
CAP3–
Rev. 2.4a
X
Y
4973
4853
4734
4614
4494
4375
4255
4136
4016
3896
3777
3657
3538
3418
3298
3179
3059
2940
2820
2700
2581
2461
2342
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
873
784
1246
PAD
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN
Name
CAP3–
(NC)
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
CAP2+
VSS
VSS
VRS
VRS
V DD
V DD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
V DD
V DD
TEST1
TEST1
TEST2
TEST2
(NC)
TEST3
TEST3
TEST4
X
Y
695
605
516
427
338
249
160
71
–18
–107
–196
–285
–374
–463
–552
–641
–730
–819
–908
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
–2155
–2244
–2333
–2422
–2511
–2600
–2689
–2778
1246
EPSON
PAD
No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PIN
Name
TEST4
(NC)
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
(NC)
COM25
(NC)
COM24
(NC)
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
X
Y
–2867
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
–4375
–4494
–4614
–4734
–4853
–4973
–5252
1246
1248
1163
1090
1017
945
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
8–17
S1D15605 Series
Units: µm
PAD
No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
8–18
PIN
Name
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
(NC)
COM0
(NC)
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
X
Y
–5252
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–1246
–5009
–4924
–4853
–4781
–4709
–4637
–4565
–4493
–4421
–4349
–4277
–4206
–4134
–4062
–3990
–3918
–3846
–3774
–3702
–3630
–3559
–3487
–3415
–3343
–3271
–3199
PAD
No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PIN
Name
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
X
Y
–3127
–3055
–2983
–2912
–2840
–2768
–2696
–2624
–2552
–2480
–2408
–2336
–2265
–2193
–2121
–2049
–1977
–1905
–1833
–1761
–1689
–1618
–1546
–1474
–1402
–1330
–1258
–1186
–1114
–1042
–971
–899
–827
–755
–683
–611
–539
–467
–395
–324
–1246
EPSON
PAD
PIN
No.
Name
201 SEG62
202 SEG63
203 SEG64
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
219 SEG80
220 SEG81
221 SEG82
222 SEG83
223 SEG84
224 SEG85
225 SEG86
226 SEG87
227 SEG88
228 SEG89
229 SEG90
230 SEG91
231 SEG92
232 SEG93
233 SEG94
234 SEG95
235 SEG96
236 SEG97
237 SEG98
238 SEG99
239 SEG100
240 SEG101
X
Y
–252
–180
–108
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
1042
1114
1186
1258
1330
1402
1474
1546
1618
1689
1761
1833
1905
1977
2049
2121
2193
2265
2336
2408
2480
2552
–1246
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
PIN
Name
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
COM26
(NC)
COM27
(NC)
Rev. 2.4a
X
Y
2624
2696
2768
2840
2912
2983
3055
3127
3199
3271
3343
3415
3487
3558
3630
3702
3774
3846
3918
3990
4062
4134
4206
4277
4349
4421
4493
4565
4637
4709
4781
4853
4924
5009
5252
–1246
PAD
No.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
PIN
Name
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
(NC)
COM51
(NC)
COMS
(NC)
(NC)
X
Y
5252
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
–1248
–1163
–1090
–1018
–945
–872
EPSON
8–19
S1D15605 Series
5. PIN DESCRIPTIONS
Power Supply Pins
Pin Name
VDD
VSS
VSS2
VRS
V1, V 2,
V3, V 4,
V5
I/O
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Power
Supply
No. of
Pins
13
Function
Shared with the MPU power supply terminal V CC.
This is a 0V terminal connected to the system GND.
9
This is the reference power supply for the step-up voltage circuit for the
liquid crystal drive.
This is the externally-input VREG power supply for the LCD power supply
voltage regulator.
These are only enabled for the models with the VREG external input option.
This is a multi-level power supply for the liquid crystal drive. The voltage
applied is determined by the liquid crystal cell, and is changed through the
use of a resistive voltage divided or through changing the impedance using
an op. amp. Voltage levels are determined based on V DD, and must
maintain the relative magnitudes shown below.
4
2
10
VDD (= V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master operation: When the power supply turns ON, the internal power
supply circuits produce the V1 to V4 voltages shown below. The voltage
settings are selected using the LCD bias set command.
V1
V2
V3
V4
S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609*****
1/9•V5 1/7•V5 1/8•V5 1/6•V5 1/6•V5 1/5•V5 1/8•V5 1/6•V5 1/8•V5 1/6•V5
2/9•V5 2/7•V5 2/8•V5 2/6•V5 2/6•V5 2/5•V5 2/8•V5 2/6•V5 2/8•V5 2/6•V5
7/9•V5 5/7•V5 6/8•V5 4/6•V5 4/6•V5 3/5•V5 6/8•V5 4/6•V5 6/8•V5 4/6•V5
8/9•V5 6/7•V5 7/8•V5 5/6•V5 5/6•V5 4/5•V5 7/8•V5 5/6•V5 7/6•V5 5/6•V5
LCD Power Supply Circuit Terminals
Pin Name
I/O
Function
CAP1+
O
CAP1–
O
CAP2+
O
CAP2–
O
CAP3–
O
VOUT
I/O
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP1- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP1+ terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP2- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP2+ terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP1+ terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
VSS2.
Output voltage regulator terminal. Provides the voltage between VDD and
V5 through a resistive voltage divider.
These are only enabled when the V5 voltage regulator internal resistors are
not used (IRS = LOW).
These cannot be used when the V5 voltage regulator internal resistors are
used (IRS = HIGH).
VR
8–20
I
EPSON
No. of
Pins
2
2
2
2
2
2
2
Rev. 2.4a
S1D15605 Series
System Bus Connection Terminals
Pin Name
I/O
Function
D7 to D0
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus.
When the serial interface is selected (P/S = LOW), then D7 serves as the
serial data input terminal (SI) and D6 serves as the serial clock input
terminal (SCL). At this time, D0 to D5 are set to high impedance.
When the chip select is inactive, D0 to D7 are set to high impedance.
This is connect to the least significant bit of the normal MPU address bus,
and it determines whether the data bits are data or a command.
A0 = HIGH: Indicates that D0 to D7 are display data.
A0 = LOW: Indicates that D0 to D7 are display control data.
When RES is set to LOW, the settings are initialized.
The reset operation is performed by the RES signal level.
This is the chip select signal. When CS1 = LOW and CS2 = HIGH, then the
chip select becomes active, and data/command I/O is enabled.
• When connected to an 8080 MPU, this is active LOW.
This pin is connected to the RD signal of the 8080 MPU, and the
S1D15605 series data bus is in an output status when this signal is LOW.
• When connected to a 6800 Series MPU, this is active HIGH.
This is the 6800 Series MPU enable clock input terminal.
• When connected to an 8080 MPU, this is active LOW.
This terminal connects to the 8080 MPU WR signal. The signals on
the data bus are latched at the rising edge of the WR signal.
• When connected to a 6800 Series MPU:
This is the read/write control signal input terminal.
When R/W = HIGH: Read.
When R/W = LOW: Write.
This is the MPU interface switch terminal.
C86 = HIGH: 6800 Series MPU interface.
C86 = LOW: 8080 MPU interface.
This is the parallel data input/serial data input switch terminal.
P/S = HIGH: Parallel data input.
P/S = LOW: Serial data input.
The following applies depending on the P/S status:
(SI)
(SCL)
A0
I
RES
I
CS1
CS2
RD
(E)
I
I
WR
(R/W)
I
C86
I
P/S
I
No. of
Pins
8
1
1
2
1
1
1
1
P/S Data/Command
Data
Read/Write Serial Clock
HIGH
A0
D0 to D7
RD, WR
LOW
A0
SI (D7)
Write only
SCL (D6)
CLS
I
When P/S = LOW, D0 to D5 are HZ. D0 to D5 may be HIGH, LOW or Open.
RD (E) and WR (P/W) are fixed to either HGIH or LOW.
With serial data input, RAM display data reading is not supported.
Terminal to select whether or enable or disable the display clock internal
oscillator circuit.
CLS = HIGH: Internal oscillator circuit is enabled
CLS = LOW: Internal oscillator circuit is disabled (requires external input)
When CLS = LOW, input the display clock through the CL terminal.
When using the S1D15605 Series as a master or slave, set respective
CLS pins at the same level.
Display clock
Built-in oscillator circuit used
External input
Rev. 2.4a
Master
HIGH
LOW
EPSON
1
Slave
HIGH
LOW
8–21
S1D15605 Series
Pin Name
M/S
I/O
Function
I
This terminal selects the master/slave operation for the S1D15605 Series
chips. Master operation outputs the timing signals that are required for the
LCD display, while slave operation inputs the timing signals required for the
liquid crystal display, synchronizing the liquid crystal display system.
M/S = HIGH: Master operation
M/S = LOW: Slave operation
The following is true depending on the M/S and CLS status:
M/S CLS Oscillator
Circuit
HIGH HIGH Enabled
LOW Disabled
LOW HIGH Disabled
LOW Disabled
CL
I/O
I/O
DOF
I/O
FRS
O
IRS
I
HPM
I
8–22
CL
FR
FRS
DOF
Output
Input
Input
Input
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Input
Input
This is the display clock input terminal
The following is true depending on the M/S and CLS status.
M/S CLS
HIGH HIGH
LOW
LOW HIGH
LOW
FR
Power
Supply
Circuit
Enabled
Enabled
Disabled
Disabled
No. of
Pins
1
1
CL
Output
Input
Input
Input
When the S1D15605 Series chips are used in master/slave mode, the
various CL terminals must be connected.
This is the liquid crystal alternating current signal I/O terminal.
M/S = HIGH: Output
M/S = LOW: Input
When the S1D15605 Series chip is used in master/slave mode, the various
FR terminals must be connected.
This is the liquid crystal display blanking control terminal.
M/S = HIGH: Output
M/S = LOW: Input
When the S1D15605 Series chip is used in master/slave mode, the various
DOF terminals must be connected.
This is the output terminal for the static drive.
This terminal is only enabled when the static indicator display is ON when
in master operation mode, and is used in conjunction with the FR terminal.
This terminal selects the resistors for the V5 voltage level adjustment.
IRS = HIGH: Use the internal resistors
IRS = LOW: Do not use the internal resistors. The V5 voltage level is
regulated by an external resistive voltage divider attached to the VR
terminal.
This pin is enabled only when the master operation mode is selected.
It is fixed to either HIGH or LOW when the slave operation mode is selected.
This is the power control terminal for the power supply circuit for liquid
crystal drive.
HPM = HIGH: Normal mode
HPM = LOW: High power mode
This pin is enabled only when the master operation mode is selected.
It is fixed to either HIGH or LOW when the slave operation mode is selected.
EPSON
1
1
1
1
1
Rev. 2.4a
S1D15605 Series
Liquid Crystal Drive Terminals
Pin Name
I/O
Function
SEG0
to
SEG131
O
These are the liquid crystal segment drive outputs. Through a combination
of the contents of the display RAM and with the FR signal, a single level is
selected from VDD, V2, V3, and V5.
COM0
to
COMn
O
RAM DATA
FR
HIGH
HIGH
LOW
LOW
Power save
HIGH
LOW
HIGH
LOW
—
No. of
Pins
132
Output Voltage
Normal Display Reverse Display
VDD
V2
V5
V3
V2
VDD
V3
V5
VDD
These are the liquid crystal common drive outputs.
Part No.
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****
S1D15609*****
COM
COM 0 ~ COM 63
COM 0 ~ COM 47
COM 0 ~ COM 31
COM 0 ~ COM 53
COM 0 ~ COM 51
Part No.
No. of pins
S1D15605*****
64
S1D15606*****
48
S1D15607*****
32
S1D15608*****
54
S1D15609*****
52
Through a combination of the contents of the scan data and with the
FR signal, a single level is selected from VDD, V1, V 4, and V5.
Scan Data
HIGH
HIGH
LOW
LOW
Power Save
COMS
O
FR
Output Voltage
HIGH
V5
LOW
VDD
HIGH
V1
LOW
V4
—
VDD
These are the COM output terminals for the indicator. Both terminals
output the same signal.
Leave these open if they are not used.
When in master/slave mode, the same signal is output by both master and
slave.
2
Test Terminals
Pin Name
I/O
TEST0 to 9
I/O
Rev. 2.4a
Function
No. of
Pins
14
These are terminals for IC chip testing.
TEST0 to 4 and 7 to 9 should be open, TEST 5 and 6 should be fixed to
HIGH.
Total: 288 pins for the S1D15605*****.
272 pins for the S1D15606*****.
256 pins for the S1D15607*****.
278 pins for the S1D15608*****.
276 pins for the S1D15609*****.
EPSON
8–23
S1D15605 Series
6. DESCRIPTION OF FUNCTIONS
The MPU Interface
Selecting the Interface Type
With the S1D15605 Series chips, data transfers are done
through an 8-bit bi-directional data bus (D7 to D0) or
through a serial data input (SI). Through selecting the P/
S terminal polarity to the HIGH or LOW it is possible to
select either parallel data input or serial data input as
shown in Table 1.
Table 1
P/S
CS1 CS2
A0
RD
HIGH: Parallel Input CS1 CS2
A0
RD
LOW: Serial Input
CS1 CS2
A0
—
“—” indicates fixed to either HIGH or to LOW.
The Parallel Interface
When the parallel interface has been selected (P/S =
HIGH), then it is possible to connect directly to either an
WR C86
D7
D6
D5~D0
WR C86
D7
D6
D5~D0
—
—
SI
SCL
(HZ)
HZ is in the state of High Impedance.
8080-system MPU or a 6800 Series MPU (as shown in
Table 2) by selecting the C86 terminal to either HIGH
or to LOW.
Table 2
P/S
CS1 CS2
HIGH: 6800 Series MPU Bus CS1 CS2
LOW: 8080 MPU Bus
CS1 CS2
A0
A0
A0
RD
E
RD
WR
R/W
WR
D7~D0
D7~D0
D7~D0
Moreover, data bus signals are recognized by a
combination of A0, RD (E), WR (R/W) signals, as
shown in Table 3.
Shared
A0
1
1
0
0
8–24
6800 Series
R/W
1
0
1
0
Table 3
8080 Series
RD
WR
0
1
1
0
0
1
1
0
EPSON
Function
Reads the display data
Writes the display data
Status read
Write control data (command)
Rev. 2.4a
S1D15605 Series
of the eighth serial clock for the processing.
The A0 input is used to determine whether or the serial
data input is display data or command data; when A0 =
HIGH, the data is display data, and when A0 = LOW
then the data is command data. The A0 input is read and
used for detection every 8th rising edge of the serial
clock after the chip becomes active.
Figure 1 is a serial interface signal chart.
The Serial Interface
When the serial interface has been selected (P/S =
LOW) then when the chip is in active state (CS1 = LOW
and CS2 = HIGH) the serial data input (SI) and the serial
clock input (SCL) can be received. The serial data is
read from the serial data input pin in the rising edge of
the serial clocks D7, D6 through D0, in this order. This
data is converted to 8 bits parallel data in the rising edge
CS1
CS2
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
D5
D4
D3
D2
13
14
SCL
11
12
A0
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their initial states.
* Reading is not possible while in serial interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that
operation be rechecked on the actual equipment.
The Chip Select
The S1D15605 Series chips have two chip select
terminals: CS1 and CS2. The MPU interface or the
serial interface is enabled only when CS1 = LOW and
CS2 = HIGH.
When the chip select is inactive, D0 to D7 enter a high
impedance state, and the A0, RD, and WR inputs are
inactive. When the serial interface is selected, the shift
register and the counter are reset.
Accessing the Display Data RAM and the
Internal Registers
Data transfer at a higher speed is ensured since the MPU
is required to satisfy the cycle time (tCYC) requirement
alone in accessing the S1D15605 Series. Wait time may
not be considered.
And, in the S1D15605 Series chips, each time data is
sent from the MPU, a type of pipeline process between
Rev. 2.4a
LSIs is performed through the bus holder attached to the
internal data bus.
For example, when the MPU writes data to the display
data RAM, once the data is stored in the bus holder, then
it is written to the display data RAM before the next data
write cycle. Moreover, when the MPU reads the display
data RAM, the first data read cycle (dummy) stores the
read data in the bus holder, and then the data is read from
the bus holder to the system bus at the next data read
cycle.
There is a certain restriction in the read sequence of the
display data RAM. Please be advised that data of the
specified address is not generated by the read instruction
issued immediately after the address setup. This data is
generated in data read of the second time. Thus, a
dummy read is required whenever the address setup or
write cycle operation is conducted.
This relationship is shown in Figure 2.
EPSON
8–25
S1D15605 Series
read instruction. If the cycle time (tCYC) is maintained,
it is not necessary to check for this flag before each
command. This makes vast improvements in MPU
processing capabilities possible.
The Busy Flag
When the busy flag is “1” it indicates that the S1D15605
Series chip is running internal processes, and at this
time no command aside from a status read will be
received. The busy flag is outputted to D7 pin with the
Internal Timing
MPU
Writing
WR
DATA
N
N+1
N+2
N+3
Latch
N+1
N
BUS Holder
N+2
N+3
Write Signal
Reading
MPU
WR
RD
Internal Timing
DATA
N
N
n
n+1
Address Preset
Read Signal
Column Address
Preset N
Bus Holder
Increment N+1
N
Address Set
#n
n
Dummy
Read
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
Figure 2
8–26
EPSON
Rev. 2.4a
S1D15605 Series
Display Data RAM
Display Data RAM
The display data RAM is a RAM that stores the dot data
for the display. It has a 65 (8 page × 8 bit +1) × 132 bit
structure. It is possible to access the desired bit by
specifying the page address and the column address.
Because, as is shown in Figure 3, the D7 to D0 display
data from the MPU corresponds to the liquid crystal
display common direction, there are few constraints at
the time of display data transfer when multiple S1D15605
series chips are used, thus and display structures can be
created easily and with a high degree of freedom.
Moreover, reading from and writing to the display
RAM from the MPU side is performed through the I/O
buffer, which is an independent operation from signal
reading for the liquid crystal driver. Consequently, even
if the display data RAM is accessed asynchronously
during liquid crystal display, it will not cause adverse
effects on the display (such as flickering).
D0
0 1 1 1
0
COM0
D1
1 0 0 0
0
COM1
D2
0 0 0 0
0
COM2
D3
0 1 1 1
0
COM3
D4
1 0 0 0
0
COM4
—
—
Display data RAM
Liquid crystal display
Figure 3
The Page Address Circuit
As shown in Figure 6-4, page address of the display data
RAM is specified through the Page Address Set
Command. The page address must be specified again
when changing pages to perform access.
Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page
for the RAM region used only by the indicators, and
only display data D0 is used.
The Column Addresses
As is shown in Figure 4, the display data RAM column
address is specified by the Column Address Set
command. The specified column address is incremented
(+1) with each display data read/write command. This
allows the MPU display data to be accessed continuously.
Moreover, the incrementation of column addresses stops
with 83H. Because the column address is independent
of the page address, when moving, for example, from
page 0 column 83H to page 1 column 00H, it is necessary
to respecify both the page address and the column
address.
Furthermore, as is shown in Table 4, the ADC command
(segment driver direction select command) can be used
to reverse the relationship between the display data
RAM column address and the segment output. Because
of this, the constraints on the IC layout when the LCD
module is assembled can be minimized.
Rev. 2.4a
Table 4
SEG
SEG 131
Output SEG0
ADC “0” 0 (H) → Column Address → 83 (H)
(D0) “1” 83 (H) ← Column Address ← 0 (H)
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies
the line address relating to the COM output when the
contents of the display data RAM are displayed. Using
the display start line address set command, what is
normally the top line of the display can be specified (this
is the COM0 output when the common output mode is
normal, and the COM63 output for S1D15605 Series,
COM47 output for S1D15606 Series, COM31 output for
the S1D15607 Series, COM53 output for S1D15608*****
and COM51 output for S1D15609*****) when the common
output mode is reversed. The display area is a 65 line area
for the S1D15605 Series, a 49 line are for the S1D15606,
a 33 line area for the S1D15607 Series , 55 line area for
the S1D15608 ***** and 53 line area for the
S1D15609***** from the display start line address.
If the line addresses are changed dynamically using the
display start line address set command, screen scrolling,
page swapping, etc. can be performed.
EPSON
8–27
S1D15605 Series
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
83
82
81
80
7F
7E
7D
7C
00
01
02
03
04
05
06
07
0
Page 2
54 lines
0
Page 1
Start
32 lines
1
48 lines
0
52 lines
0
63 lines
0
Page 0
1 0
D0 D0
ADC
Column
Address
0
LCD
Out
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
11H
12H
13H
14H
15H
16H
17H
18H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
7C
7D
7E
7F
80
81
82
83
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
07
06
05
04
03
02
01
00
0
When the
Line
common output
Address mode is normal
Data
SEG127
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
Page Address
D3
D2
D1
D0
COM
Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
Regardless of the display
start line address, the
S1D15605 Series
accesses 65th line, the
S1D15606 Series
accesses 49th line and
the S1D15607 Series
accesses 33th line and
the S1D15608 Series
accesses 55th line, the
S1D15609 Series
accesses 53 lines.
Figure 4
8–28
EPSON
Rev. 2.4a
S1D15605 Series
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily
stores the display data that is output to the liquid crystal
driver circuit from the display data RAM.
Because the display normal/reverse status, display ON/
OFF status, and display all points ON/OFF commands
control only the data within the latch, they do not change
the data within the display data RAM itself.
The Oscillator Circuit
This is a CR-type oscillator that produces the display
clock. The oscillator circuit is only enabled when M/S
= HIGH and CLS = HIGH.
When CLS = LOW the oscillation stops, and the display
clock is input through the CL terminal.
Display Timing Generator Circuit
The display timing generator circuit generates the timing
signal to the line address circuit and the display data
latch circuit using the display clock. The display data is
latched into the display data latch circuit synchronized
with the display clock, and is output to the data driver
output terminal. Reading to the display data liquid
crystal driver circuits is completely independent of
accesses to the display data RAM by the MPU.
Consequently, even if the display data RAM is accessed
asynchronously during liquid crystal display, there is
absolutely no adverse effect (such as flickering) on the
display.
Moreover, the display timing generator circuit generates
the common timing and the liquid crystal alternating
current signal (FR) from the display clock. It generates
a drive wave form using a 2 frame alternating current
drive method, as is shown in Figure 5, for the liquid
crystal drive circuit.
Two-frame alternating current drive wave form (S1D15605*****)
64 65 1
2
3
4
5
6
60 61 62 63 64 65 1
2
3
4
5
6
CL
FR
VDD
V1
COM0
V4
V5
VDD
V1
COM1
V4
V5
RAM
DATA
VDD
V2
SEGn
V3
V5
Figure 5
Rev. 2.4a
EPSON
8–29
S1D15605 Series
When multiple S1D15605 Series chips are used, the
slave chips must be supplied the display timing signals
(FR, CL, DOF) from the master chip[s].
Table 5 shows the status of the FR, CL, and DOF
signals.
Table 5
Operating Mode
Master (M/S = HIGH) The internal oscillator circuit is enabled (CLS = HIGH)
The internal oscillator circuit is disabled (CLS = LOW)
Slave (M/S = LOW) Set the CLS pin to the same level as with the master.
FR
Output
Output
Input
Input
CL
Output
Input
Input
Input
DOF
Output
Output
Input
Input
The Common Output Status Select
Circuit
In the S1D15605 Series chips, the COM output scan
direction can be selected by the common output status
select command. (See Table 6.) Consequently, the
constraints in IC layout at the time of LCD module
assembly can be minimized.
Table 6
Status
COM Scan Direction
S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609*****
Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51
Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0
The Liquid Crystal Driver Circuits
These are a 197-channel (S1D15605 Series), a 181channel (S1D15606 Series) multiplexers 165-channel
(S1D15607 Series), 187-channel (S1D15608 Series)
and a 185-channel (S1D15609 Series) that generate
four voltage levels for driving the liquid crystal. The
combination of the display data, the COM scan signal,
and the FR signal produces the liquid crystal drive
voltage output.
Figure 6 shows examples of the SEG and COM output
wave form.
8–30
EPSON
Rev. 2.4a
S1D15605 Series
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
FR
VDD
VSS
COM0
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
COM1
COM2
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
SEG0
SEG1
SEG2
COM0–SEG0
V5
V4
V3
V2
V1
V∞
–V1
–V2
–V3
–V4
–V5
COM0–SEG1
V5
V4
V3
V2
V1
V∞
–V1
–V2
–V3
–V4
–V5
Figure 6
Rev. 2.4a
EPSON
8–31
S1D15605 Series
The Power Supply Circuits
The power supply circuits are low-power consumption
power supply circuits that generate the voltage levels
required for the liquid crystal drivers. They comprise
Booster circuits, voltage regulator circuits, and voltage
follower circuits. They are only enabled in master
operation.
The power supply circuits can turn the Booster circuits,
the voltage regulator circuits, and the voltage follower
circuits ON of OFF independently through the use of the
Power Control Set command. Consequently, it is possible
to make an external power supply and the internal
power supply function somewhat in parallel. Table 7
shows the Power Control Set Command 3-bit data
control function, and Table 8 shows reference
combinations.
Table 7 The Control Details of Each Bit of the Power Control Set Command
Status
Item
“1”
“0”
D2 Booster circuit control bit
ON
OFF
D1 Voltage regulator circuit (V regulator circuit) control bit
ON
OFF
D0 Voltage follower circuit (V/F circuit) control bit
ON
OFF
Table 8 Reference Combinations
Use Settings
Step-up
D2 D1 D0 circuit
V
V/F
regulator circuit
circuit
Step-up
External voltage
voltage system
input
terminal
VSS2
Used
Only the internal power supply is 1
1
1
O
O
O
used
2 Only the V regulator circuit and
0
1
1
X
O
O
VOUT, VSS2 Open
the V/F circuit are used
3 Only the V/F circuit is used
0
0
1
X
X
O
V5, VSS2
Open
4 Only the external power supply is
0
0
0
X
X
X
V1 to V5
Open
used
* The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–.
* While other combinations, not shown above, are also possible, these combinations are not recommended
because they have no practical use.
1
The Step-up Voltage Circuits
Using the step-up voltage circuits equipped within the
S1D15605 Series chips it is possible to product a Quad
step-up, a Triple step-up, and a Double step-up of the
VDD – V SS2 voltage levels.
Quad step-up: Connect capacitor C1 between CAP1+
and CAP1–, between CAP2+ and CAP2–,
between CAP1+ and CAP3–, and between
VSS2 and VOUT, to produce a voltage level
in the negative direction at the VOUT
terminal that is 4 times the voltage level
between VDD and VSS2 .
Triple step-up: Connect capacitor C1 between CAP1+
and CAP1–, between CAP2+ and CAP2–
and between V SS2 and VOUT , and short
between CAP3– and V OUT to produce a
voltage level in the negative direction at the
VOUT terminal that is 3 times the voltage
8–32
difference between VDD and VSS2 .
Double step-up:
Connect capacitor C1 between
CAP1+ and CAP1–, and between VSS2 and
V OUT , leave CAP2+ open, and short
between CAP2–, CAP3– and VOUT to
produce a voltage in the negative direction
at the VOUT terminal that is twice the voltage
between VDD and VSS2 .
The step-up voltage relationships are shown in Figure 7.
EPSON
Rev. 2.4a
S1D15605 Series
VSS2
+
+
CAP1+
C1
CAP1–
C1
VOUT
CAP3–
CAP1+
+
C1
CAP1–
CAP2–
C1
S1D15605 Series
CAP3–
C1
S1D15605 Series
VOUT
VSS2
+
C1
VOUT
CAP3–
CAP1+
+
C1
CAP1–
CAP2–
CAP2–
CAP2+
OPEN CAP2+
S1D15605 Series
VSS2
+
C1
C1
+
CAP2+
4 x step-up voltage circuit
+
3 x step-up voltage circuit
VDD = 0V
VDD = 0V
VSS2 = –3V
VSS2 = –3V
2 x step-up voltage circuit
VDD = 0V
VSS2 = –5V
VOUT = 3 x VSS2 = –9V
VOUT = 2 x VSS2 = –10V
VOUT = 4 x VSS2 = –12V
4x step-up voltage relationships
3x step-up voltage relationships
2x step-up voltage relationships
Figure 7
* The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated
value.
The Voltage Regulator Circuit
The step-up voltage generated at V OUT outputs the
liquid crystal driver voltage V5 through the voltage
regulator circuit.
Because the S1D15605 Series chips have an internal
high-accuracy fixed voltage power supply with a 64level electronic volume function and internal resistors
for the V5 voltage regulator, systems can be constructed
without having to include high-accuracy voltage
regulator circuit components.
Moreover, in the S1D15605 Series, three types of thermal
gradients have been prepared as V REG options: (1)
approximately -0.05%/°C (2) approximately -0.2%/°C,
and (3) external input (supplied to the VRS terminal).
Rev. 2.4a
(A) When the V5 Voltage Regulator Internal
Resistors Are Used
Through the use of the V 5 voltage regulator internal
resistors and the electronic volume function the liquid
crystal power supply voltage V5 can be controlled by
commands alone (without adding any external resistors),
making it possible to adjust the liquid crystal display
brightness. The V5 voltage can be calculated using
equation A-1 over the range where | V5 | < | VOUT |.
EPSON
8–33
S1D15605 Series
Rb 

V5 = 1 +
⋅ VEV

Ra 
α 
Rb  

= 1+
⋅ 1–
⋅ VREG

Ra   162 
[Q V = (1 − α 162) ⋅ V ]
EV
(Equation A-1)
REG
∴
VDD
VEV (constant voltage supply + electronic volume)
Internal Ra
+
V5
–
Internal Rb
Figure 8
VREG is the IC-internal fixed voltage supply, and its
voltage at Ta = 25°C is as shown in Table 9.
Table 9
Equipment Type
Thermal Gradient
(1) Internal Power Supply
–0.05
(2) Internal Power Supply
–0.2
(3) External Input
—
α is set to 1 level of 64 possible levels by the electronic
volume function depending on the data set in the 6-bit
electronic volume register. Table 10 shows the value for
α depending on the electronic volume register settings.
Table 10
D5 D4 D3 D2 D1 D0
α
0
0
0
0
0
0
63
0
0
0
0
0
1
62
0
0
0
0
1
0
61
.
.
.
.
.
.
1
1
1
1
0
1
2
1
1
1
1
1
0
1
1
1
1
1
1
1
0
8–34
Units
[%/°C ]
[%/°C ]
—
VREG
–2.1
–4.9
VRS
Units
[V]
[V]
[V]
Rb/Ra is the V5 voltage regulator internal resistor ratio,
and can be set to 8 different levels through the V 5
voltage regulator internal resistor ratio set command.
The (1 + Rb/Ra) ratio assumes the values shown in
Table 11 depending on the 3-bit data settings in the V 5
voltage regulator internal resistor ratio register.
EPSON
Rev. 2.4a
S1D15605 Series
V 5 voltage regulator internal resistance ratio register
value and (1 + Rb/Ra) ratio (Reference value)
Table 11
S1D15605 *****
S1D15606*****
Register
Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ]
D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input (1) –0.05 (2) –0.2 (3) VREG External Input
0 0
0
3.0
1.3
1.5
3.0
1.3
1.5
0 0
1
3.5
1.5
2.0
3.5
1.5
2.0
0 1
0
4.0
1.8
2.5
4.0
1.8
2.5
0 1
1
4.5
2.0
3.0
4.5
2.0
3.0
1 0
0
5.0
2.3
3.5
5.0
2.3
3.5
1 0
1
5.5
2.5
4.0
5.4
2.5
4.0
1 1
0
6.0
2.8
4.5
5.9
2.8
4.5
1 1
1
6.4
3.0
5.0
6.4
3.0
5.0
S1D15607*****
S1D15608*****/S1D15609*****
Register
Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ]
D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input
–0.05
0 0
0
3.0
1.3
1.5
3
0 0
1
3.5
1.5
2.0
3.5
0 1
0
4.0
1.8
2.5
4
0 1
1
4.5
2.0
3.0
4.5
1 0
0
5.0
2.3
3.5
5
1 0
1
5.4
2.5
4.0
5.4
1 1
0
5.9
2.8
4.5
5.9
1 1
1
6.4
3.0
5.0
6.4
For the internal resistance ratio, a manufacturing
dispersion of up to ±7% should be taken into account.
When not within the tolerance, adjust the V 5 voltage by
externally mounting Ra and Rb.
Figs. 9, 10, 11 (for S1D15605 Series), 12, 13, 14 (for
S1D15606 Series), 15, 16, 17 (for S1D15607 Series), 18
(for S1D15608D00B* ) and Figs. 19 (for
S1D15609D00B*) show V5 voltage measured by values
of the internal resistance ratio resistor for V 5 voltage
adjustment and electric volume resister for each
temperature grade model, when Ta = 25 °C.
Rev. 2.4a
EPSON
8–35
S1D15605 Series
S1D15605D00B*/S1D15605D11B*
–16
–15
–14
111
V5 [v]
–13
–12
110
–11
101
–10
100
–9
011
–8
010
–7
001
–6
000
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 9: S1D15605D00B */S1D15605D11B* (1) For Models Where the Thermal Gradient = -0.05%/°C
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15605D01B*
–16
–15
111
–14
110
–13
101
–12
100
–11
011
–10
V5 [v]
–9
010
–8
001
–7
000
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 10: S1D15605D01B* (2) For Models Where the Thermal Gradient = -0.2%/°C
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
8–36
EPSON
Rev. 2.4a
S1D15605 Series
S1D15605D02B*
–16
111
–15
–14
110
–13
101
–12
–11
100
–10
011
V5 [v]
–9
–8
010
–7
001
–6
–5
000
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 11: S1D15605D02B* (3) For models with External Input
The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic
volume register.
–16
S1D15606D00B*/S1D15606D11B *
–15
–14
111
–13
110
–12
101
–11
100
–10
011
V5 [v]
–9
010
–8
001
–7
000
–6
–5
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–4
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 12: S1D15606D00B*/S1D15606D11B* (1) For Models Where the Thermal Gradient = -0.05%/°C
The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic
volume register.
Rev. 2.4a
EPSON
8–37
S1D15605 Series
S1D15606D01B*
–16
111
–15
–14
110
–13
101
–12
100
–11
011
–10
010
V5 [v]
–9
–8
001
–7
000
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 13: S1D15606D01B* (2) For Models Where the Thermal Gradient = -0.2%/°C
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15606D02B*
–16
111
–15
110
–14
–13
101
–12
100
–11
–10
011
V5 [v]
–9
–8
010
–7
001
–6
000
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 14: S1D15606D02B * (3) For models with External Input
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
8–38
EPSON
Rev. 2.4a
S1D15605 Series
S1D15607D00B*/S1D15607D11B *
–16
–15
–14
111
–13
110
–12
101
–11
100
–10
011
V5 [v]
–9
010
–8
001
–7
000
–6
–5
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–4
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 15: S1D15607D00B*/S1D15607D11B* (1) For Models Where the Thermal Gradient = -0.05%/°C
The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15607D01B*
–16
111
–15
110
–14
101
–13
–12
100
–11
011
V5 [v]
–10
–9
010
–8
001
–7
000
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 16: S1D15607D01B* (2) For Models Where the Thermal Gradient = -0.2%/°C
The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic
volume register.
Rev. 2.4a
EPSON
8–39
S1D15605 Series
S1D15607D02B*
–16
111
–15
110
–14
–13
101
–12
–11
100
–10
011
V5 [v]
–9
–8
010
–7
001
–6
–5
000
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 17: S1D15607D02B * (3) For models with External Input
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15608D00B*
–16
111
–15
110
–14
–13
101
–12
–11
100
–10
011
V5 [v]
–9
–8
010
–7
001
–6
–5
000
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 18: S1D15608D00B * (1) For Models Where the Thermal Gradient = –0.05%/°C
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
8–40
EPSON
Rev. 2.4a
S1D15605 Series
S1D15609D00B*
–16
111
–15
110
–14
–13
101
–12
–11
100
–10
011
V5 [v]
–9
–8
010
–7
001
–6
–5
000
–4
The V5 voltage
regulator internal
resistance ratio
registers
(D2, D1, D0)
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Figure 19: S1D15609D00B* Temperature Gradient = –0.05%/°C Model
The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic
volume register.
Setup example: When selecting Ta = 25°C and V5 = 7
V for an S1D15607 model on which Temperature
gradient = –0.05%/°C.
Using Figure 15 and the equation A-1, the following
setup is enabled.
At this time, the variable range and the notch width of
the V5 voltage is, as shown Table 13, as dependent on
the electronic volume.
Table 12
Contents
For V5 voltage
regulator
Electronic Volume
Register
D5 D4 D3 D2 D1 D0
— — — 0
1
0
1
V5
Variable Range
Notch width
Rev. 2.4a
0
0
1
0
Min.
–8.4 (63 levels)
1
Table 13
Typ.
Max.
–6.8 (central value) –5.1 (0 level)
51
EPSON
Units
[V]
[mV]
8–41
S1D15605 Series
(B) When an External Resistance is Used
(i.e., The V5 Voltage Regulator Internal
Resistors Are Not Used) (1)
The liquid crystal power supply voltage V5 can also be
set without using the V 5 voltage regulator internal
resistors (IRS terminal = LOW) by adding resistors Ra’
and Rb’ between VDD and VR, and between VR and V5,
respectively. When this is done, the use of the electronic
volume function makes it possible to adjust the brightness
of the liquid crystal display by controlling the liquid
crystal power supply voltage V5 through commands.
In the range where | V5 | < | VOUT |, the V5 voltage can
be calculated using equation B-1 based on the external
resistances Ra’ and Rb’.
Rb' 

V5 = 1 +
⋅ VEV

Ra' 
Rb'  
α 

= 1+
⋅ 1–
⋅ VREG

Ra'   162 
[Q V = (1 − α 162) ⋅ V ]
EV
( Equation B-1)
REG
∴
VDD
VEV (fixed voltage power supply + electronic volume)
External
resistor Ra'
+
V5
–
External
resistor Rb'
Figure 20
Setup example: When selecting Ta = 25°C and V5 = –
7 V for an S1D15607 Series model where the temperature
gradient = –0.05%/°C.
When the central value of the electron volume register
is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α
= 31 and VREG = –2.1 V so, according to equation B-1,
α 
Rb'  

V5 = 1 +
⋅ 1−
⋅ VREG

Ra'   162 
31 
Rb'  

−11V = 1 +
⋅ 1−
⋅ ( −2.1) (Equation B-2)

Ra'   162 
Consequently, by equations B-2 and B-3,
Rb'
= 3.12
Ra'
Ra' = 340 kΩ
Rb' = 1060 kΩ
At this time, the V5 voltage variable range and notch
width, based on the electron volume function, is as
given in Table 14.
Moreover, when the value of the current running through
Ra’ and Rb’ is set to 5 µA,
(Equation B-3)
Ra' + Rb' = 1.4 MΩ
V5
Variable Range
Notch width
8–42
Min.
–8.6 (63 levels)
Table 14
Typ.
Max.
–7.0 (central value) –5.3 (0 level)
52
EPSON
Units
[V]
[mV]
Rev. 2.4a
S1D15605 Series
the electronic volume function makes it possible to
control the liquid crystal power supply voltage V5 by
commands to adjust the liquid crystal display brightness.
In the range where | V5 | < | VOUT | the V5 voltage can
be calculated by equation C-1 below based on the R1
and R2 (variable resistor) and R3 settings, where R2 can
be subjected to fine adjustments (∆ R2 ).
(C) When External Resistors are Used
(i.e. The V5 Voltage Regulator Internal
Resistors Are Not Used). (2)
When the external resistor described above are used,
adding a variable resistor as well makes it possible to
perform fine adjustments on Ra’ and Rb’, to set the
liquid crystal drive voltage V 5. In this case, the use of

R + R2 − ∆R2 
V5 = 1 + 3
⋅ VEV
R1 + ∆R2 


R + R2 − ∆R2  
α 
= 1 + 3
 ⋅ 1 – 162  ⋅ VREG
R
R
+
∆


1
2
[Q V = (1 − α 162) ⋅ V ]
EV
(Equation C-1)
REG
∴
VDD
VEV (fixed voltage supply + electronic volume)
Ra'
External
resistor R1
+
V5
∆R2
External
resistor R2
–
VR
Rb'
External
resistor R3
Figure 21
Setup example: When selecting Ta = 25°C and V5 = –
5 to –9 V (using R2) for an S1D15607 model where the
temperature gradient = –0.05%/°C.
When the central value for the electronic volume register
is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0),
α = 31
VREG = −2.1V
so, according to equation C-1, when ∆ R2 = 0 Ω, in order
to make V5 = –9 V,
When ∆ R2 = R2 , in order to make V = –5 V,

R3  
31 
−5V = 1 +
 ⋅ 1 − 162  ⋅ ( −2.1)
+
R
R

1
2
(Equation C-3)
Moreover, when the current flowing VDD and V5 is set
to 5 µA,
R1 + R2 + R3 = 1.4 MΩ
(Equation C-4)
With this, according to equation C-2, C-3 and C-4,
R1 = 264 kΩ

R + R2  
31 
−9V = 1 + 3
 ⋅ 1 − 162  ⋅ ( −2.1)
R


1
R2 = 211kΩ
R3 = 925kΩ
(Equation C-2)
At this time, the V5 voltage variable range and notch
width based on the electron volume function is as shown
in Table 15.
V5
Variable Range
Notch width
Rev. 2.4a
Min.
–8.7 (63 levels)
Table 15
Typ.
Max.
–7.0 (central value) –5.3 (0 level)
53
EPSON
Units
[V]
[mV]
8–43
S1D15605 Series
* When the V5 voltage regulator internal resistors or
the electronic volume function is used, it is necessary
to at least set the voltage regulator circuit and the
voltage follower circuit to an operating mode using
the power control set commands. Moreover, it is
necessary to provide a voltage from VOUT when the
Booster circuit is OFF.
* The V R terminal is enabled only when the V5 voltage
regulator internal resistors are not uesd (i.e. the IRS
terminal = LOW). When the V 5 voltage regulator
internal resistors are uesd (i.e. when the IRS terminal
= HIGH), then the V R terminal is left open.
* Because the input impedance of the VR terminal is
high, it is necessary to take into consideration short
leads, shield cables, etc. to handle noise.
High Power Mode
The power supply circuit equipped in the S1D15605
Series chips has very low power consumption (normal
mode: HPM = HIGH). However, for LCDs or panels
with large loads, this low-power power supply may
cause display quality to degrade. When this occurs,
setting the HPM terminal to LOW (high power mode)
can improve the quality of the display. We recommend
that the display be checked on actual equipment to
determine whether or not to use this mode.
Moreover, if the improvement to the display is inadequate
even after high power mode has been set, then it is
necessary to add a liquid crystal drive power supply
externally.
The Internal Power Supply Shutdown
Command Sequence
The sequence shown in Figure 22 is recommended for
shutting down the internal power supply, first placing
the power supply in power saver mode and then turning
the power supply OFF.
The Liquid Crystal Voltage Generator Circuit
The V5 voltage is produced by a resistive voltage
divider within the IC, and can be produced at the V1, V2,
V3, and V4 voltage levels required for liquid crystal
driving. Moreover, when the voltage follower changes
the impedance, it provides V1, V 2, V3 and V4 to the
liquid crystal drive circuit. 1/9 bias or 1/7 bias for
S1D15605 Series, 1/8 bias or 1/6 bias for S1D15606
Series, 1/6 bias or 1/5 bias for the S1D15607 Series, 1/
8 bias or 1/6 bias for S1D15608 Series and 1/8 bias or
1/6 bias for S1D15609 Series can be selected.
Sequence
Details
(Command, status)
Command address
D7 D6 D5 D4 D3 D2 D1 D0
Step1
Display OFF
1
0
1
0
1
1
1
0
Step2
Display all points ON
1
0
1
0
0
1
0
1
End
Power saver
commands
(compound)
Internal power supply OFF
Figure 22
8–44
EPSON
Rev. 2.4a
S1D15605 Series
Reference Circuit Examples
Figure 22 shows reference circuit examples.
➀ When used all of the step-up circuit, voltage regulating circuit and V/F circuit
(1) When the voltage regulator internal resistor
is used.
(Example where VSS2 = VSS, with 4x step-up)
(2) When the voltage regulator internal resistor
is not used.
(Example where VSS2 = VSS, with 4x step-up)
VDD
C1
C1
C1
VDD
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VDD
C2
C2
C2
C2
C2
V1
IRS
C1
VSS
C1
C1
C1
R3
R2
VDD
VDD
C2
V2
V3
V4
C2
V4
V5
C2
V5
(2) When the V5 voltage regulator internal resistor
is used.
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
R1
VDD
C2
C2
C2
C2
C2
Rev. 2.4a
V1
VDD
M/S
IRS
VSS
External
power
supply
S1D15605 Series
VDD
V2
V3
IRS
R3
R2
V1
C2
VDD
External
power
supply
R1
C2
➁ When the voltage regulator circuit and V/F
circuit alone are used
(1) When the V5 voltage regulator internal resistor
is not used.
VSS
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
M/S
VDD
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VDD
C2
C2
V2
V1
V2
V3
C2
V3
V4
C2
V4
V5
C2
V5
EPSON
M/S
S1D15605 Series
C1
VSS
M/S
S1D15605 Series
IRS
S1D15605 Series
VDD
8–45
S1D15605 Series
➂ When the V/F circuit alone is used
➃ When the built-in power is not used
VSS
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VSS
External
power
supply
VDD
VDD
C2
V1
C2
IRS
M/S
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
S1D15605 Series
IRS
VDD
VDD
VDD
V1
V2
External
power
supply
V2
C2
V3
C2
V4
V4
C2
V5
V5
5 When the built-in power circuit is used to drive a
liquid crystal panel heavily loaded with AC or DC, it
is recommended to connect an external resistor to
stabilize potentials of V1, V2, V3 and V 4 which are
output from the built-in voltage follower.
M/S
S1D15605 Series
VDD
V3
Examples of shared reference settings
When V5 can vary between –8 and 12 V
Item
Set value
Units
C1
C2
1.0 to 4.7
0.01 to 1.0
µF
µF
VDD, V0
R4
C2
V1
V2
V3
S1D15605 Series
R4
V4
R4
Reference set value R4: 100kΩ ~ 1MΩ
It is recommended to set an optimum
resistance value R4 taking the liquid crystal
display and the drive waveform.
R4
V5
Figure 23
* 1 Because the VR terminal input impedance is high, use short leads and shielded lines.
* 2 C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal
drive voltage.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to V OUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that
stabilizes the liquid crystal drive voltages (V 1 to V5 ). Note that all C2 capacitors must have the same capacitance
value.
• Next turn all the power supplies ON and determine C1.
8–46
EPSON
Rev. 2.4a
S1D15605 Series
* Precautions when installing the COG
When installing the COG, it is necessary to duly consider
the fact that there exists a resistance of the ITO wiring
occurring between the driver chip and the externally
connected parts (such as capacitors and resistors). By the
influence of this resistance, non-conformity may occur
with the indications on the liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the driver
chip pin to the externally connected parts as much as
possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
2.
the resistance of ITO wiring is being inserted in
series with the switching transistor, thus dominating
the boosting ability.
Consequently, the boosting ability will be hindered
as a result and pay sufficient attention to the wiring
to respective boosting capacitors.
Connection of the smoothing capacitors for the
liquid crystal drive
The smoothing capacitors for the liquid crystal
driving potentials (V 1 . V 2 , V 3 and V 4 ) are
indispensable for liquid crystal drives not only for
the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs
pursuant to installation of the COG is supplemented
to these smoothing capacitors, the liquid crystal
driving potentials become unstable to cause nonconformity with the indications of the liquid crystal
display. Therefore, when using the COG module,
we definitely recommend to connect reinforcing
resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these
reinforcing resistors, current consumption will
increase.
Also, as for this driver IC, pay sufficient attention to the
following points when connecting to external parts for
the characteristics of the circuit.
1. Connection to the boosting capacitors The boosting
capacitors (the capacitors connecting to respective
CAP pins and capacitor being inserted between
VOUT and VSS2) of this IC are being switched over
by use of the transistor with very low ON-resistance
of about 10Ω. However, when installing the COG,
Indicated below is an exemplary connection diagram of
external resistors.
Please make sufficient evaluation work for the display
statuses with any connection tests.
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
VDD
VDD
R4
V1
V2
C2
V3
C2
V1
C2
R4
S1D15605 Series
C2
V2
C2
V3
C2
S1D15605 Series
R4
VDD
R4
V4
C2
C2
V4
R4 R4
C2
Rev. 2.4a
V5
C2
EPSON
V5
8–47
S1D15605 Series
The Reset Circuit
When the RES input comes to the LOW level, these
LSIs return to the default state. Their default states are
as follows:
1. Display OFF
2. Normal display
3. ADC select: Normal (ADC command D0 = LOW)
4. Power control register: (D2, D1, D0) = (0, 0, 0)
5. Serial interface internal register data clear
6. LCD power supply bias rate:
S1D15605***** ........................ 1/9 bias
S1D15606*****, 15608*****, 15609 *****
................................................................ 1/8 bias
S1D15607********* ................ 1/6 bias
7. All-indicator lamps-on OFF (All-indicator lamps
ON/OFF command D0 = LOW)
8. Power saving clear
9. V5 voltage regulator internal resistors Ra and Rb
separation
(In case of S1D15605D11B*, S1D15606D11B*,
S1D15607D11B * , S1D15608D11B * and
S1D15609D11B*, internal resistors are connected
while RES is LOW.)
10. Output conditions of SEG and COM terminals
SEG : V2/V3 , COM : V1/V4
(In case of S1D15605D11B*, S1D15606D11B*,
S1D15607D11B * , S1D15608D11B * and
S1D15609D11B*, both the SEG terminal and the
COM terminal output the VDA level while RES is
LOW. In case of other models, the SEG terminal
outputs V2 and the COM terminal outputs V1 while
RES is LOW.)
11. Read modify write OFF
12. Static indicator OFF
Static indicator register : (D1, D2) = (0, 0)
13. Display start line set to first line
14. Column address set to Address 0
15. Page address set to Page 0
16. Common output status normal
17. V5 voltage regulator internal resistor ratio set mode
clear
18. Electronic volume register set mode clear
Electronic volume register : (D5, D4, D3, D2, D1,
D0) = (1, 0. 0, 0, 0, 0)
19. Test mode clear
8–48
On the other hand, when the reset command is used, the
above default settings from 11 to 19 are only executed.
When the power is turned on, the IC internal state
becomes unstable, and it is necessary to initialize it
using the RES terminal. After the initialization, each
input terminal should be controlled normally.
Moreover, when the control signal from the MPU is in
the high impedance, an overcurrent may flow to the IC.
After applying a current, it is necessary to take proper
measures to prevent the input terminal from getting into
the high impedance state.
If the internal liquid crystal power supply circuit is not
used on S1D15605D11B * , S1D15606D11B * ,
S1D15607D11B* , S1D15608D11B* and
S1D15609D11B *, it is necessary that RES is HIGH
when the external liquid crystal power supply is turned
on. This IC has the function to discharge V5 when RES
is LOW, and the external power supply short-circuits to
VDD when RES is LOW.
While RES is LOW, the oscillator and the display
timing generator stop, and the CL, FR, FRS and DOF
terminals are fixed to HIGH. The terminals D0 to D7
are not affected. The VDD level is output from the SEG
and COM output terminals. This means that an internal
resistor is connected between V DD and V5 .
When the internal liquid crystal power supply circuit is
not used on other models of S1D15605 series, it is
necessary that RE is LOWwhen the external liquid
crystal power supply is turned on.
While RES is LOW, the oscillator works but the display
timing generator stops, and the CL, FR, FRS and DOF
terminals are fixed to HIGH. The terminals D0 to D7
are not affected.
EPSON
Rev. 2.4a
S1D15605 Series
7. COMMANDS
The S1D15605 Series chips identify the data bus signals by a combination of A0, RD (E), WR (R/W) signals. Command
interpretation and execution does not depend on the external clock, but rather is performed through internal timing only,
and thus the processing is fast enough that normally a busy check is not required.
In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and
inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read
mode when an HIGH signal is input to the R/W terminal and placed in a write mode when a LOW signal is input to the
R/W terminal and then the command is launched by inputting a high pulse to the E terminal. (See “10. Timing
Characteristics” regarding the timing.) Consequently, the 6800 Series MPU interface is different than the 80x86 Series
MPU interface in that in the explanation of commands and the display commands the status read and display data read
RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface
as the example.
When the serial interface is selected, the data is input in sequence starting with D7.
<Explanation of Commands>
(1) Display ON/OFF
This command turns the display ON and OFF.
A0
0
E R/W
RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
0
1
1
1
1
0
Setting
Display ON
Display OFF
When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See
the section on the power saver for details.
(2) Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further
details see the explanation of this function in “The Line Address Circuit”.
A0
0
E R/W
RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
↓
1
1
1
1
1
0
1
1
1
1
1
1
Line address
0
1
2
↓
62
63
(3) Page Address Set
This command specifies the page address corresponding to the low address when the MPU accesses the display data
RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data
RAM. Changing the page address does not accompany a change in the status display. See the page address circuit in
the Function Description (page 1–20) for the detail.
A0
0
E R/W
RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
↓
0
1
1
1
1
0
0
0
Rev. 2.4a
EPSON
Page address
0
1
2
↓
7
8
8–49
S1D15605 Series
(4) Column Address Set
This command specifies the column address of the display data RAM shown in Figure 4. The column address is split
into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the
display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to
continuously read from/write to the display data. The column address increment is topped at 83H. This does not change
the page address continuously. See the function explanation in “The Column Address Circuit,” for details.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6
HIGH bits → 0
1
0
0 0 0 1 A7 A6 A5 A4 0 0
LOW bits →
0 A3 A2 A1 A0 0 0
0 0
↓ ↓
1 0
1 0
A5
0
0
0
A4
0
0
0
A3
0
0
0
A2
0
0
0
A1
0
0
1
0
0
0
0
0
0
0
0
1
1
Column
A0 address
0
0
1
1
0
2
0
1
130
131
(5) Status Read
A0
0
E R/W
RD WR
0
1
BUSY
ADC
ON/OFF
RESET
D7
BUSY
D6
ADC
D5
D4
ON/OFF RESET
D3 D2 D1 D0
0
0
0
0
When BUSY = 1, it indicates that either processing is occurring internally or a reset condition
is in process. While the chip does not accept commands until BUSY = 0, if the cycle time can
be satisfied, there is no need to check for BUSY conditions.
This shows the relationship between the column address and the segment driver.
0: Reverse (column address 131-n ↔ SEG n)
1: Normal (column address n ↔ SEG n)
(The ADC command switches the polarity.)
ON/OFF: indicates the display ON/OFF state.
0: Display ON
1: Display OFF
(This display ON/OFF command switches the polarity.)
This indicates that the chip is in the process of initialization either because of a RES signal or
because of a reset command.
0: Operating state
1: Reset in progress
(6) Display Data Write
This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically
incremented by “1” after the write, the MPU can write the display data.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
Write data
(7) Display Data Read
This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically
incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required
immediately after the column address has been set. See the function explanation in “Display Data RAM” for the
explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes
unavailable.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
Read Data
8–50
EPSON
Rev. 2.4a
S1D15605 Series
(8) ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence between the display RAM data column address and the segment driver
output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address
circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the
display data is done according to the column address indicated in Figure 4.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 0 1 0 0 0 0 0
1
Setting
Normal
Reverse
(9) Display Normal/Reverse
This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When
this is done the display data RAM contents are maintained.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 0 1 0 0 1 1 0
1
Setting
RAM Data HIGH
LCD ON voltage (normal)
RAM Data LOW
LCD ON voltage (reverse)
(10) Display All Points ON/OFF
This command makes it possible to force all display points ON regardless of the content of the display data RAM. The
contents of the display data RAM are maintained when this is done. This command takes priority over the display
normal/reverse command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 0 1 0 0 1 0 0
1
Setting
Normal display mode
Display all points ON
When the display is in an OFF mode, executing the display all points ON command will place the display in power save
mode. For details, see the (20) Power Save section.
(11) LCD Bias Set
This command selects the voltage bias ratio required for the liquid crystal display. This command can be valid while
the V/F circuit of Power Supply circuit is in operation.
E R/W
Select Status
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609 *****
0
1
0
1 0 1 0 0 0 1 0
1/9 bias
1/8 bias
1/6 bias
1/8 bias
1/8 bias
1
1/7 bias
1/6 bias
1/5 bias
1/6 bias
1/6 bias
(12) Read/Modify/Write
This command is used paired with the “END” command. Once this command has been input, the display data read
command does not change the column address, but only the display data write command increments (+1) the column
address. This mode is maintained until the END command is input. When the END command is input, the column
address returns to the address it was at when the read/modify/write command was entered. This function makes it
possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when
there is a blanking cursor.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 1 1 0 0 0 0 0
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
However, the column address set command cannot be used.
Rev. 2.4a
EPSON
8–51
S1D15605 Series
• The sequence for cursor display
Page address set
Column address set
Read/modify/write
Dummy read
Data read
Data process
Data write
No
Change complete?
Yes
End
Figure 24
(13) End
This command releases the read/modify/write mode, and returns the column address to the address it was at when the
mode was entered.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 1 1 0 1 1 1 0
Return
Column address
N
N+1
N+2
N+3
Read/modify/write mode set
•••
N+m
N
End
Figure 25
(14) Reset
This command initializes the display start line, the column address, the page address, the common output mode, the V 5
voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/
write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in
“Reset” for details.
The reset operation is performed after the reset command is entered.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 1 1 0 0 0 1 0
The initialization when the power supply is applied must be done through applying a reset signal to the RES terminal.
The reset command must not be used instead.
8–52
EPSON
Rev. 2.4a
S1D15605 Series
(15) Common Output Mode Select
This command can select the scan direction of the COM output terminal. For details, see the function explanation in
“Common Output Mode Select Circuit.”
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
Selected Mode
S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609*****
1 1 0 0 0 * * * Normal COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0→COM51
1
Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0
* Disabled bit
(16) Power Controller Set
This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,”
for details
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Selected Mode
0
1
0
0 0 1 0 1 0
Booster circuit: OFF
1
Booster circuit: ON
0
Voltage regulator circuit: OFF
1
Voltage regulator circuit: ON
0 Voltage follower circuit: OFF
1 Voltage follower circuit: ON
[Translator’s Note: the abbreviations explained within these parentheses for V
and V/F have been written out in the English translation and are therefore no
longer necessary.]
(17) V 5 Voltage Regulator Internal Resistor Ratio Set
This command sets the V 5 voltage regulator internal resistor ratio. For details, see the function explanation is “The
Power Supply Circuits.”
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2
0
1
0
0 0 1 0 0 0
0
0
D1
0
0
1
↓
1 1
1 1
D0
0
1
0
Rb/Ra Ratio
Small
↓
0
1
Large
(18) The Electronic Volume (Double Byte Command)
This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal
drive voltage V 5 through the output from the voltage regulator circuits of the internal liquid crystal power supply.
This command is a two byte command used as a pair with the electronic volume mode set command and the electronic
volume register set command, and both commands must be issued one after the other.
• The Electronic Volume Mode Set
When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume
mode has been set, no other command except for the electronic volume register command can be used. Once the
electronic volume register set command has been used to set data into the register, then the electronic volume mode is
released.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 0 0 0 0 0 0 1
Rev. 2.4a
EPSON
8–53
S1D15605 Series
• Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes
one of the 64 voltage levels.
When this command is input, the electronic volume mode is released after the electronic volume register has been set.
E R/W
A0 RD WR D7 D6 D5
0
1
0
*
* 0
0
1
0
*
* 0
0
1
0
*
* 0
0
0
1
1
0
0
*
*
*
*
D4 D3
0 0
0 0
0 0
↓
1 1 1
1 1 1
D2
0
0
0
D1
0
1
1
D0
1
0
1
1
1
1
1
0
1
| V5 |
Small
↓
Large
* Inactive bit
When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)
• The Electronic Volume Register Set Sequence
Electronic volume mode set
Electronic volume register set
No
Electronic volume mode clear
Changes complete?
Yes
Figure 26
(19) Static Indicator (Double Byte Command)
This command controls the static drive system indicator display. The static indicator display is controlled by this
command only, and is independent of other display control commands.
This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other
is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the
dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the
electrodes.
The static indicator ON command is a double byte command paired with the static indicator register set command, and
thus one must execute one after the other. (The static indicator OFF command is a single byte command.)
• Static Indicator ON/OFF
When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static
indicator ON command has been entered, no other command aside from the static indicator register set command can
be used. This mode is cleared when data is set in the register by the static indicator register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 0 1 0 1 1 0 0
1
8–54
Static Indicator
OFF
ON
EPSON
Rev. 2.4a
S1D15605 Series
• Static Indicator Register Set
This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking
mode.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1
0
1
0
* * * * *
* 0
0
1
1
D0
0
1
0
1
Indicator Display State
OFF
ON (blinking at approximately one second intervals)
ON (blinking at approximately 0.5 second intervals)
ON (constantly on)
* Disabled bit
• Static Indicator Register Set Sequence
Static indicator mode set
Static indicator register set
Static indicator
mode clear
No
Changes complete?
Yes
Figure 27
(20) Power Save (Compound Command)
When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered,
thus greatly reducing power consumption.
The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF,
it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered.
In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before
the power saver mode was initiated, and the MPU is still able to access the display data RAM.
Refer to figure 28 for power save off sequence.
Static indicator OFF
Static indicator ON
Power saver (compound command)
Sleep mode
Standby mode
Power save OFF (compound command)
Display all points OFF command
Static indicator ON
(2 bytes command)
Power save OFF
(Display all points OFF command)
Sleep mode cancel
Standby mode cancel
Figure 28
Rev. 2.4a
EPSON
8–55
S1D15605 Series
• Sleep Mode
This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption
current is reduced to a value near the static current. The internal modes during sleep mode are as follows:
1 The oscillator circuit and the LCD power supply circuit are halted.
2 All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level.
• Standby Mode
The duty LCD display system operations are halted and only the static drive system for the indicator continues to
operate, providing the minimum required consumption current for the static drive. The internal modes are in the
following states during standby mode.
1 The LCD power supply circuits are halted. The oscillator circuit continues to operate.
2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output
a VDD level. The static drive system does not operate.
When a reset command is performed while in standby mode, the system enters sleep mode.
* When an external power supply is used, it is recommended that the functions of the external power supply circuit
be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage
are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the
electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The
S1D15605 series chips have a liquid crystal display blanking control terminal DOF. This terminal enters an LOW
state when the power saver mode is launched. Using the output of DOF, it is possible to stop the function of an external
power supply circuit.
* When the master is turned on, the oscillator circuit is operable immediately after the powering on.
(21) NOP
Non-OPeration Command
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 1 1 0 0 0 1 1
(22) Test
This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared
by applying a LOW signal to the RES input by the reset command or by using an NOP.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1 1 1 1 * * * *
* Inactive bit
Note: The S1D15605 Series chips maintain their operating modes until something happens to change them.
Consequently, excessive external noise, etc., can change the internal modes of the S1D15605 Series chip. Thus
in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise
from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to
prevent the effects of unanticipated noise.
8–56
EPSON
Rev. 2.4a
S1D15605 Series
Table 16 Table of S1D15605 Series Commands
(1)
(2)
Display start line set
0
1
0
0
1
(3)
Page address set
0
1
0
1
0
1
1
Page address
(4)
Column address
set upper bit
0
1
0
0
0
0
1
Most significant
column address
0
1
0
0
0
0
0
(5)
(6)
(7)
Column address
set lower bit
Status read
Display data write
Display data read
0
1
1
0
1
0
1
0
1
(8)
ADC select
0
1
0
1
0
1
0
0
0
0
0
1
(9)
Display normal/
reverse
0
1
0
1
0
1
0
0
1
1
0
1
(10) Display all points
ON/OFF
0
1
0
1
0
1
0
0
1
0
0
1
(11) LCD bias set
0
1
0
1
0
1
0
0
0
1
0
1
(12) Read/modify/write
0
1
0
1
1
1
0
0
0
0
0
(13) End
(14) Reset
(15) Common output
mode select
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
*
1
1
*
0
0
*
(16) Power control set
0
1
0
0
0
1
0
1
(17) V5 voltage
regulator internal
resistor ratio set
(18) Electronic volume
mode set
Electronic volume
register set
0
1
0
0
0
1
0
0
Operating
mode
Resistor ratio
0
1
0
1
0
0
0
0
0
0
1
0
*
*
(19) Static indicator
ON/OFF
Static indicator
register set
(20) Power saver
0
1
0
1
0
1
0
1
1
0
1
0
*
*
*
*
*
*
(21) NOP
(22) Test
0
0
Rev. 2.4a
A0
0
RD
1
WR
0
D7
1
Command Code
D6 D5 D4
0
1
0
Command
Display ON/OFF
1
1
0
0
1
1
D2
1
D1
1
D0
0
1
Display start address
Status
1
1
D3
1
Least significant
column address
0
0
0
0
Write data
Read data
0
0
1
EPSON
0
*
0
*
Sets the LCD drive voltage
bias ratio
S1D15605***** .. 0: 1/9, 1: 1/7
S1D15606*****
/S1D15608*****
/S1D15609***** . 0: 1/8, 1: 1/6
S1D15607***** .. 0: 1/6, 1: 1/5
Column address increment
At write: +1
At read: 0
Clear read/modify/write
Internal reset
Select COM output scan
direction
0: normal direction,
1: reverse direction
Select internal power
supply operating mode
Select internal resistor ratio
(Rb/Ra) mode
Set the V5 output voltage
electronic volume register
0
0
1
Mode
1
*
Sets the display RAM address
SEG output correspondence
0: normal, 1: reverse
Sets the LCD display normal/
reverse
0: normal, 1: reverse
Display all points
0: normal display
1: all points ON
1
Electronic volume value
1
1
Function
LCD display ON/OFF
0: OFF, 1: ON
Sets the display RAM display
start line address
Sets the display RAM page
address
Sets the most significant 4 bits
of the display RAM column
address.
Sets the least significant 4 bits of
the display RAM column address.
Reads the status data
Writes to the display RAM
Reads from the display RAM
1
*
0: OFF, 1: ON
Set the flashing mode
Display OFF and display all
points ON compound command
Command for non-operation
Command for IC test. Do not
use this command
(Note) *: disabled data
8–57
S1D15605 Series
8. COMMAND DESCRIPTION
Instruction Setup: Reference (reference)
(1) Initialization
Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1
and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is
remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the
VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To
avoid occurrence of such a failure, we recommend the following flow when turning on the power.
1
When the built-in power is being used immediately after turning on the power:
Turn ON the VDD-VSS power keeping the
RES pin = LOW.
When the power is stabilized
Release the reset state. (RES pin = HIGH)
Initialized state (Default) *1
Function setup by command input (User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
(In case of S1D15605D11B ,
*
S1D15606D11B*, S1D15607D11B*,
S1D15608D11B* and S1D15609D11B*)
Arrange to execute all the procedures
from releasing the reset state through
setting the power control within 5ms.
(In case of other models) execute the
procedures from turning on the power
to setting the power control in 5ms.
Function setup by command input (User setup)
(16) Power control setting *7
This concludes the initialization
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.
*1: 6. Description of functions; “Resetting circuit” (If takes not more than 2 ms from Power Supply ON to
the stability of internal oscillating circuit.)
*2: 7. Command description; “(11) LCD bias setting”
*3: 7. Command description; “(8) ADC selection”
*4: 7. Command description; “(15) Common output state selection”
*5: 6. Description of functions; “Power circuit” & Command description; “(17) Setting the built-in
resistance radio for regulation of the V5 voltage”
*6: 6. Description of functions; “Power circuit” & Command description; “(18) Electronic volume control”
*7: 6. Description of functions; “Power circuit” & Command description; “(16) Power control setting”
8–58
EPSON
Rev. 2.4a
S1D15605 Series
2
When the built-in power is not being used immediately after turning on the power:
Turn ON the VDD-VSS power keeping the
RES pin = LOW.
When the power is stabilized
Release the reset state. (RES pin = HIGH)
Initialized state (Default) *1
Power saver START (multiple commands) *8
(In case of S1D15605D11B*,
S1D15606D11B , S1D15607D11B ,
*
*
S1D15608D11B and S1D15609D11B )
*
*
Arrange to start the power saver within
5ms after releasing the reset state.
(In case of other models) execute the
procedures from turning on the power
to setting the power control in 5ms.
Function setup by command input (User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Power saver OFF *8
Function setup by command input (User setup)
(16) Power control setting *7
Arrange to start power control
setting within 5ms after turning
OFF the power saver.
This concludes the initialization
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.
*1: 6. Description of functions; “Resetting circuit” (The contents of DDRAM can be variable even in the
initial setting (Default) at the reset state.)
*2: 7. Command description; “(11) LCD bias setting”
*3: 7. Command description; “(8) ADC selection”
*4: 7. Command description; “(15) Common output state selection”
*5: 6. Description of functions; “Power circuit” & “(17) Command description; Setting the built-in
resistance radio for regulation of the V5 voltage”
*6: 6. Description of functions; “Power circuit” & “(18) Command description; Electronic volume control”
*7: 6. Description of functions; “Power circuit” & “(16) Command description; Power control setting”
*8: 7. The power saver ON state can either be in sleep state or stand-by state.
Command description; “Power saver START (multiple commands)”
Rev. 2.4a
EPSON
8–59
S1D15605 Series
(2) Data Display
End of initialization
Function setup by command input (User setup)
(2) Display start line set *9
(3) Page address set *10
(4) Column address set *11
Function setup by command input (User setup)
(6) Display data write *12
Function setup by command input (User setup)
(1) Display ON/OFF *13
End of data display
Notes: Reference items
*9: Command Description; Display start line set
*10: Command Description; Page address set
*11: Command Description; Column address set
*12: Command Description; Display data write
*13: Command Description; Display ON/OFF
Avoid displaying all the data at the data
display start (when the display is ON) in
white.
(3) Power OFF *14
• In case of S1D15605D11B*, S1D15606D11B*, S1D15607D11B*, S1D15608D11B* and S1D15609D11B*,
Optional status
Function setup by command input (User setup)
(20) Power save *15
Reset active (RES pin = LOW)
VDD – VSS power OFF
Set the time (tL) from reset active to turning off
the VDD - VSS power (VDD - VSS = 1.8 V) longer
than the time (tH) when the potential of V5 ~ V1
becomes below the threshold voltage
(approximately 1 V) of the LCD panel.
For tH, refer to the <Reference Data> of this
event. When tH is too long, insert a resistor
between V5 and VDD to reduce it.
• In case of other models,
Optional status
Function setup by command input (User setup)
(20) Power save *15
VDD – VSS power OFF
Set the time (tL) from power save to turning off
the VDD - VSS power (VDD - VSS = 1.8 V) longer
than the time (tH) when the potential of V5 ~ V1
becomes below the threshold voltage
(approximately 1V) of the LCD panel.
• tH is determined depending on the voltage
regulator external resistors Ra and Rb and the
time constant of V5 ~ V1 smoothing capacity C2.
• When an internal resistor is used, it is
recommended to insert a resistor R between
VDD and V5 to reduce tH.
Notes: Reference items
*14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply
VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has
still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning
off the power, observe the following basic procedures:
• After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below
the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS ).
6. Description of Function, 6.7 Power Circuit
*15: After inputting the power save command, be sure to reset the function using the RES terminal until the
power supply VDD - VSS is turned off. 7. Command Description (20) Power Save
*16: After inputting the power save command, do not reset the function using the RES terminal until the
power supply VDD - VSS is turned off. 7. Command Description (20) Power Save
8–60
EPSON
Rev. 2.4a
S1D15605 Series
(4) Refresh
It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of
unexpected noise.
Refresh sequence
NOP command
Set all commands to the ready state
(Including default state setting.)
Refreshing of DRAM
Precautions on Turning off the power
• In case of S1D15605D11B*, S1D15606D11B*, S1D15607D11B*, S1D15608D11B* and S1D15609D11B*,
Observe Paragraph 1) as the basic rule.
<Turning the power (VDD - VSS) off>
1) Power Save (The LCD powers (VDD - V5 ) are off.) → Reset input → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software. tH is determined according to the external capacity C 2 (smoothing
capacity of V5 ~ V1) and the driver’s discharging capacity.
Power
save Reset Power Off
tL
VDD
1.8 V
RES
VDD
SEG
Since the power (VDD-VSS) is
cut off, the output comes not
to be fixed.
VDD
COM
V1
V2
V3
V4
V5
Rev. 2.4a
About 1 V: Below Vth of the LCD panel
tH
For tH, see Figure 29.
EPSON
8–61
S1D15605 Series
<Turning the power (VDD - VSS ) off : When command control is not possible.>
2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
For t L, make the power (VDD - VSS) falling characteristics longer or consider any other method. t H is
determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging
capacity.
Reset
Power Off
tL
VDD
1.8 V
RES
VDD
SEG
Since the power (VDD-VSS) is
cut off, the output comes not
be fixed.
VDD
COM
V1
V2
V3
V4
V5
About 1 V: Below Vth of the LCD panel
tH
For tH, see Figure 29.
<Reference Data>
V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset.
V5 voltage falling (discharge) time (tH) after the process of operation → reset.
V5 voltage falling time (mSec)
100
VDD-VSS(V)
1.8
2.4
50
3.0
4.0
5.0
0
0.5
1.0
C2: V1 to V5 capacity (uF)
Figure 29
8–62
EPSON
Rev. 2.4a
S1D15605 Series
• In case of other models than the above
<Turning the power (VDD - VSS) off>
Power save (The LCD powers (VDD - VSS) are off.) -> Power (V DD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software. tH is determined according to the external capacity C (smoothing
capacity of V5 to V1) and the external resisters Ra + Rb (for V5 voltage regulation)
Power
save
Power
Off
tL
VDD
1.8 V
SEG
Since the power (VDD-VSS) is
cut off, the output comes not
be fixed.
COM
V1
V2
V3
V4
V5
About 1 V: Below Vth of the LCD panel
tH
tH is determined depending on the time
constant of (Ra + Rb) C.
Rev. 2.4a
EPSON
8–63
S1D15605 Series
9. ABSOLUTE MAXIMUM RATINGS
Unless otherwise noted, VSS = 0 V
Table 17
Parameter
Power Supply Voltage
Power supply voltage (2)
(VDD standard)
With Triple step-up
With Quad step-up
Power supply voltage (3) (VDD standard)
Power supply voltage (4) (VDD standard)
Input voltage
Output voltage
Operating temperature
Storage temperature
TCP
Bare chip
Symbol
VDD
VSS2
V5, VOUT
V1, V2 , V3 , V4
VIN
VO
TOPR
TSTR
VCC
VDD
GND
VSS
Conditions
–0.3 to +7.0
–7.0 to +0.3
–6.0 to +0.3
–4.5 to +0.3
–18.0 to +0.3
V5 to +0.3
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–40 to +85
–55 to +100
–55 to +125
Unit
V
V
V
V
V
V
°C
°C
VDD
VSS2, V1 to V4
V5, VOUT
System (MPU) side
S1D15605 Series chip side
Figure 30
Notes and Cautions
1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference.
2. Insure that the voltage levels of V1, V2, V3, and V 4 are always such that VDD ≥ V1 ≥ V 2 ≥ V3 ≥ V4 ≥ V 5.
3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover,
it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of
the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative
impact on the LSI reliability as well.
8–64
EPSON
Rev. 2.4a
S1D15605 Series
10. DC CHARACTERISTICS
Unless otherwise specified, VSS = 0 V, V DD = 3.0 V ± 10%, Ta = –40 to 85°C
Table 18
Item
V
Applicable
Pin
V DD*1
5.5
V
V DD*1
—
–2.7
V
VSS2
–6.0
—
–1.8
V
VSS2
(Relative to V DD)
–16.0
—
–4.5
V
V5 *2
(Relative to V DD)
0.4 × V5
—
VDD
V
V1, V2
(Relative to V DD)
V5
—
0.6 × V5
V
V3, V4
VIHC
0.8 × VDD
—
VDD
V
*3
VILC
V SS
—
0.2 × VDD
V
*3
0.8 × VDD
—
VDD
V
*4
Symbol
VDD
Operating RecomVoltage (1) mended
Voltage
Possible
Operating
Voltage
Operating RecomVSS2
Voltage (2) mended
Voltage
VSS2
Possible
Operating
Voltage
Operating Possible
V5
Voltage (3) Operating
Voltage
Possible V1, V2
Operating
Voltage
Possible V3, V4
Operating
Voltage
High-level Input
Voltage
Low-level Input
Voltage
High-level Output
Voltage
Low-level Output
Voltage
Input leakage
current
Output leakage
current
Max.
3.3
1.8
—
(Relative to V DD)
–3.3
(Relative to V DD)
Units
VOHC
IOH = –0.5 mA
VOLC
IOL = 0.5 mA
V SS
—
0.2 × VDD
V
*4
VIN = VDD or VSS
–1.0
—
1.0
µA
*5
–3.0
—
3.0
µA
*6
—
—
2.0
3.2
3.5
5.4
kΩ
kΩ
SEGn
COMn *7
—
0.01
5
µA
V SS, VSS2
—
0.01
15
µA
V5
C IN
V5 = –18.0 V
(Relative To VDD)
Ta = 25°C f = 1 MHz
—
5.0
8.0
pF
fOSC
Ta = 25°C
18
22
26
kHz
*8
S1D15605*****/15607*****
18
22
26
kHz
CL
Ta = 25°C
27
33
39
kHz
*8
S1D15606*****/15608*****/
15609
14
17
20
kHz
CL
ILI
ILO
Liquid Crystal Driver
ON Resistance
RON
Static Consumption
Current
Output Leakage
Current
Input Terminal
Capacitance
Oscillator Internal
Frequency Oscillator
External
Input
Internal
Oscillator
External
Input
ISSQ
Rev. 2.4a
Min.
2.7
Rating
Typ.
—
Condition
I5Q
fCL
fOSC
fCL
Ta = 25°C
V5 = –14.0 V
(Relative To VDD) V5 = –8.0 V
*****
EPSON
8–65
S1D15605 Series
Table 19
Item
Input voltage
Symbol
VSS2
Internal Power
VSS2
Supply Step-up VOUT
output voltage
Circuit
Voltage regulator VOUT
Circuit Operating
Voltage
V5
Voltage Follower
Circuit Operating
Voltage
Base Voltage VREG0
VREG1
8–66
V
Applicable
Pin
VSS2
–1.8
V
VSS2
—
—
V
VOUT
–18.0
—
–6.0
V
VOUT
(Relative to VDD)
–16.0
—
–4.5
V
V5 *9
Ta = 25°C
–0.05%/°C
(Relative to VDD) –0.2%/°C
–2.04
–4.65
–2.10
–4.9
–2.16
–5.15
V
V
*10
*10
Condition
Min.
–6.0
Rating
Typ.
—
Max.
–1.8
With Triple
(Relative To VDD)
With Quad
(Relative To VDD)
(Relative to VDD)
–4.5
—
–18.0
(Relative to VDD)
EPSON
Units
Rev. 2.4a
S1D15605 Series
• Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF
Current consumed by total ICs when an external power supply is used.
Table 20 Display Pattern OFF
Ta = 25°C
Item
S1D15605*****
Symbol
Condition
IDD (1)
VDD = 5.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
S1D15606*****
S1D15607*****
S1D15608*****/
S1D15609*****
Min.
—
—
—
—
—
—
—
—
—
Rating
Units Notes
Typ. Max.
18
30
µA
*11
16
27
13
22
11
19
9
15
8
13
7
12
12
20
10
17
Table 21 Display Pattern Checker
Ta = 25°C
Item
S1D15605*****
Symbol
Condition
IDD (1)
VDD = 5.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
S1D15606*****
S1D15607*****
S1D15608*****/
S1D15609*****
Rating
Units Notes
Min. Typ. Max.
—
23
38
µA
*11
—
21
35
—
17
29
—
14
24
—
12
20
—
11
18
—
10
17
—
15
25
—
13
22
• Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON
The values of curret consumed in all the IC including internal power supply circuit.
Table 22 Display Pattern OFF
Ta = 25°C
Item
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****/
S1D15609*****
Rev. 2.4a
Symbol
Condition
IDD (2) VDD = 5.0 V, Triple step-up voltage. Normal Mode
V5 – VDD = –11.0 V
High-Power Mode
VDD = 3.0 V, Quad step-up voltage. Normal Mode
V5 – VDD = –11.0 V
High-Power Mode
VDD = 5.0 V, Double step-up voltage. Normal Mode
V5 – VDD = –8.0 V
High-Power Mode
VDD = 3.0 V, Triple step-up voltage. Normal Mode
V5 – VDD = –8.0 V
High-Power Mode
VDD = 3.0 V, Quad step-up voltage. Normal Mode
V5 – VDD = –11.0 V
High-Power Mode
VDD = 5.0 V, Double step-up voltage. Normal Mode
V5 – VDD = –8.0 V
High-Power Mode
VDD = 3.0 V, Triple step-up voltage. Normal Mode
V5 – VDD = –8.0 V
High-Power Mode
VDD = 5.0 V, Double step-up voltage. Normal Mode
V5 – VDD = –8.0 V
High-Power Mode
VDD = 3.0 V, Triple step-up voltage. Normal Mode
V5 – VDD = –8.0 V
High-Power Mode
EPSON
Rating
Units Notes
Min. Typ. Max.
— 67 112 µA *12
— 114 190
— 81 135
— 138 230
— 35 59
— 64 107
— 43 72
— 84 140
— 72 121
— 128 214
— 26 44
— 60 100
— 29 49
— 73 122
— 37 62
— 67 112
— 46 77
— 87 145
8–67
S1D15605 Series
Table 23 Display Pattern Checker
Item
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****/
S1D15609*****
Symbol
Condition
IDD (2) V DD = 5.0 V, Triple step-up voltage. Normal Mode
V5 – V DD = –11.0 V
High-Power Mode
V DD = 3.0 V, Quad step-up voltage. Normal Mode
V5 – V DD = –11.0 V
High-Power Mode
VDD = 5.0 V, Double step-up voltage. Normal Mode
V5 – V DD = –8.0 V
High-Power Mode
V DD = 3.0 V, Triple step-up voltage. Normal Mode
V5 – V DD = –8.0 V
High-Power Mode
V DD = 3.0 V, Quad step-up voltage. Normal Mode
V5 – V DD = –11.0 V
High-Power Mode
VDD = 5.0 V, Double step-up voltage. Normal Mode
V5 – V DD = –8.0 V
High-Power Mode
V DD = 3.0 V, Triple step-up voltage. Normal Mode
V5 – V DD = –8.0 V
High-Power Mode
VDD = 5.0 V, Double step-up voltage. Normal Mode
V5 – V DD = –8.0 V
High-Power Mode
V DD = 3.0 V, Triple step-up voltage. Normal Mode
V5 – V DD = –8.0 V
High-Power Mode
Ta = 25°C
Rating
Units Notes
Min. Typ. Max.
— 81 135 µA *12
— 127 212
— 96 160
— 153 255
— 41 69
— 71 119
— 51 85
— 92 154
— 85 142
— 142 237
— 32 53
— 62 103
— 44 73
— 89 148
— 44 74
— 74 127
— 54 90
— 95 159
• Consumption Current at Time of Power Saver Mode, VSS = 0 V, V DD = 3.0 V ± 10%
Table 24
Ta = 25°C
Item
Sleep mode
Standby Mode
Sleep mode
Standby Mode
Sleep mode
Standby Mode
Sleep mode
S1D15605*****
S1D15605*****
S1D15606*****
S1D15606*****
S1D15607*****
S1D15607*****
S1D15608*****/
S1D15609*****
Standby Mode S1D15608*****/
S1D15609*****
Symbol
Condition
IDDS1
IDDS2
IDDS1
IDDS2
IDDS1
IDDS2
IDDS1
—
—
—
—
—
—
—
IDDS2
—
Rating
Units Notes
Min. Typ. Max.
0.01
5
µA
4
8
µA
0.01
5
µA
4
8
µA
0.01
5
µA
3
6
µA
0.01
5
µA
4
8
µA
TBD: To Be Determined
8–68
EPSON
Rev. 2.4a
S1D15605 Series
Reference Data 1
• Dynamic Consumption Current (1) During LCD Display Using an External Power Supply
IDD (1) (ISS + I5) [µA]
40
Conditions: Internal power supply OFF
External power supply in use
S1D15605/S1D15606 (–11.0V):
V5 – VDD = –11.0 V
S1D15606 (–8.0V)/S1D15607/
S1D15608/S1D15609:
V5 – VDD = –8.0 V
Display pattern: OFF
Ta = 25°C
S1D15605
S1D15606 (–11.0V)
S1D15608/S1D15609 (–8.0V)
S1D15606 (–8.0V)
30
20
10
S1D15607
Note: *11
0
0
2
4
VDD [V]
6
8
Figure 31
IDD (1) (ISS + I5) [µA]
40
Conditions: Internal power supply OFF
External power supply in use
S1D15605/S1D15606 (–11.0V):
V5 – VDD = –11.0 V
S1D15606 (–8.0V)/S1D15607/
S1D15608/S1D15609:
V5 – VDD = –8.0 V
S1D15605
Display pattern: Checker
S1D15606 (–11.0V)
Ta = 25°C
S1D15608/S1D15609 (–8.0V)
S1D15606 (–8.0V)
S1D15607
30
20
10
Note: *11
0
0
2
4
6
8
VDD [V]
Figure 32
Rev. 2.4a
EPSON
8–69
S1D15605 Series
Reference Data 2
• Dynamic Consumption Current (2) During LCD display using the internal power supply
Conditions: Internal power supply ON
S1D15605/S1D15606 (×4, –11.0V)/
S1D15608/S1D15609 (×4, –11.0V):
4× step-up voltage: V5 – VDD = –11.0 V
S1D15606 (×3, –8.0V)/S1D15607/
S1D15608/S1D15609 (×3, –8.0V):
3× step-up voltage: V5 – VDD = –8.0 V
S1D15605
Normal mode
S1D15608/15609 (x4, –11.0V)
Display pattern: OFF
S1D15606 (x4, –11.0V)
Ta = 25°C
S1D15608/S1D15609 (x3, –8.0V)
140
120
IDD (2) [µA]
100
80
60
S1D15606 (x3, –8.0V)
40
S1D15607
20
0
0
Note: *12
2
4
VDD [V]
6
8
Figure 33
Conditions: Internal power supply ON
S1D15605/S1D15606 (×4, –11.0V)/
S1D15608/S1D15609 (×4, –11.0V):
4× step-up voltage: V5 – VDD = –11.0 V
S1D15606 (×3, –8.0V)/S1D15607/
S1D15608/S1D15609 (×3, –8.0V):
S1D15605
3× step-up voltage: V5 – VDD = –8.0 V
S1D15608/15609 (x4, –11.0V)
Normal mode
S1D15606 (x4, –11.0V)
Display pattern: Checker
Ta = 25°C
S1D15608/S1D15609 (x3, –8.0V)
S1D15606 (x3, –8.0V)
120
IDD (2) [µA]
100
80
60
S1D15607
40
20
0
0
Note: *12
2
4
6
8
VDD [V]
Figure 34
8–70
EPSON
Rev. 2.4a
S1D15605 Series
Reference Data 3
• Dynamic Consumption Current (3) During access
10
This figure indicates the consumption
current while the checker pattern is
constantly written through fCYC.
If there is no access, then only (1) remains.
Conditions: Internal power supply OFF,
external power supply used
S1D15605:
VDD – VSS = 3.0 V, V5=–11.0 V
S1D15606/S1D15607/
S1D15608/S1D15609:
VDD – VSS = 3.0 V, V5=–8.0 V
Ta = 25°C
IDD(3)[mA]
1
0.1
S1D15605
S1D15606
S1D15607
S1D15608/S1D15609
0.01
0.001
0.01
0.1
1
10
fCYC[MHz]
Figure 35
Reference Data 4
• Operating voltage range of VSS and V5 systems
–20
S1D15605 Series
Note: *2
–16
V5-VDD[V]
–15
Operating range
–10
–7.2
–5 –4.5
1.8
0
0
3.0
2
5.5
4
6
8
VDD[V]
Figure 36
Rev. 2.4a
EPSON
8–71
S1D15605 Series
• The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame
Rate Frequency f FR
Table 25
S1D15605*****
Item
When the internal oscillator circuit is used
When the internal oscillator circuit is not used
S1D15606***** When the internal oscillator circuit is used
When the internal oscillator circuit is not used
S1D15607***** When the internal oscillator circuit is used
When the internal oscillator circuit is not used
S1D15608***** When the internal oscillator circuit is used
When the internal oscillator circuit is not used
S1D15609***** When the internal oscillator circuit is used
When the internal oscillator circuit is not used
fCL
fFR
fOSC
____
4
External input (fCL)
fOSC
_____
4 × 65
fCL
____
260
fOSC
_____
fOSC
____
8
External input (fCL)
fOSC
____
8
External input (fCL)
fOSC
____
8
External input (fCL)
fOSC
____
8
External input (fCL)
8 × 49
fCL
____
196
fOSC
_____
8 × 33
fCL
____
264
fOSC
_____
8 × 55
fCL
____
220
f
OSC
_____
8 × 53
fCL
____
212
(fFR is the liquid crystal alternating current period, and not the FR signal period.)
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are
sudden fluctuations to the voltage while the MPU is being accessed.
*2 The operating voltage range for the VDD system and the V5 system is as shown in Figure 36. This applies
when the external power supply is being used.
*3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF,
RES, IRS, and HPM terminals.
*4 The D0 to D7, FR, FRS, DOF, and CL terminals.
*5 The A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, and HPM terminals.
*6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF terminals are in a high impedance state.
*7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or
COMn and the various power supply terminals (V1, V2, V3, and V 4). These are specified for the operating
voltage (3) range.
RON = 0.1 V/∆ I (Where ∆ I is the current that flows when 0.1 V is applied while the power supply is ON.)
*8 See Table 9-7 for the relationship between the oscillator frequency and the frame rate frequency.
*9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
*10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the S1D15605/S1D15606/
S1D15607 chips, the temperature range can come in three types as VREG options: (1) approximately–0.05%/°C,
(2) –0.2%/°C, and (3) external input.
*11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned
on.
The S1D15605 is 1/9 biased, S1D15606/S1D15608/S1D15609 is 1/8 biased and S1D15607 is 1/6 biased.
Does not include the current due to the LCD panel capacity and wiring capacity.
Applicable only when there is no access from the MPU.
*12 It is the value on a model having the VREG option temperature gradient is –0.05%/°C when the V 5 voltage
regulator internal resistor is used.
8–72
EPSON
Rev. 2.4a
S1D15605 Series
11. TIMING CHARACTERISTICS
(1) System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
*1
tCCLR, tCCLW
WR, RD
tCCHR, tCCHW
CS1
(CS2="1")
*2
tf
tr
WR, RD
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 37
Table 26
Item
Signal
Address hold time
Address setup time
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
A0
Rev. 2.4a
A0
WR
RD
WR
RD
D0 to D7
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
EPSON
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
0
—
ns
0
—
ns
166
—
ns
30
—
ns
70
—
ns
30
—
ns
30
—
ns
30
—
ns
10
—
ns
CL = 100 pF
—
70
ns
5
50
ns
8–73
S1D15605 Series
Table 27
Item
Signal
Address hold time
Address setup time
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
A0
A0
WR
RD
WR
RD
D0 to D7
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
0
—
ns
0
—
ns
300
—
ns
60
—
ns
120
—
ns
60
—
ns
60
—
ns
40
—
ns
15
—
ns
CL = 100 pF
—
140
ns
10
100
ns
Table 28
Item
Signal
Address hold time
Address setup time
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
A0
*1
*2
*3
*4
*5
8–74
A0
WR
RD
WR
RD
D0 to D7
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
0
—
ns
0
—
ns
1000
—
ns
120
—
ns
240
—
ns
120
—
ns
120
—
ns
80
—
ns
30
—
ns
CL = 100 pF
—
280
ns
10
200
ns
This is in the case of making the access by WR and RD,setting the CS1=LOW.
This is the case of making the accese by CS1,setting the WR,RD=LOW.
The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns.When using the
system cycle time at high speed, they are specified for (tr + tf) ≤ (tCYC8-tCCLR-tCCHR).
All timings are specified based on the 20 and 80% of VDD.
tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and
WR,RD are at the LOW level.
EPSON
Rev. 2.4a
S1D15605 Series
(2) System Bus Read/Write Characteristics 2 (6800 Series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
*1
tEWHR, tEWHW
tCYC6
E
tEWLR, tEWLWW
CS1
(CS2="1")
*2
tr
tf
E
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 38
Table 29
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
time
Enable LOW pulse
time
Rev. 2.4a
Signal
Symbol
A0
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
A0
D0 to D7
Read
Write
Read
Write
E
E
EPSON
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
0
—
ns
0
—
ns
166
—
ns
30
—
ns
10
—
ns
CL = 100 pF
—
70
ns
10
50
ns
70
—
ns
30
—
ns
30
—
ns
30
—
ns
8–75
S1D15605 Series
Table 30
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
time
Enable LOW pulse
time
Signal
Symbol
A0
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
A0
D0 to D7
Read
Write
Read
Write
E
E
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
0
—
ns
0
—
ns
300
—
ns
40
—
ns
15
—
ns
CL = 100 pF
—
140
ns
10
100
ns
120
—
ns
60
—
ns
60
—
ns
60
—
ns
Table 31
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
time
Enable LOW pulse
time
*1
*2
*3
*4
*5
8–76
Signal
Symbol
A0
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
A0
D0 to D7
Read
Write
Read
Write
E
E
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
0
—
ns
0
—
ns
1000
—
ns
80
—
ns
30
—
ns
CL = 100 pF
—
280
ns
10
200
ns
240
—
ns
120
—
ns
120
—
ns
120
—
ns
This is in the case of making the access by E, setting the CS1=LOW.
This is the case of making the accese by CS1,setting the E=HIGH.
The rise and fall times ((tr and tf) of the input signal are specified for less than 15 ns.When using the
system cycle time at high speed, they are specified for (tr + tf) ≤ (tCYC6-tEWLW-tEWHW) or (tr + tf) ≤
(tCYC6-tEWLR-tEWHR).
All timings are specified based on the 20 and 80% of VDD.
tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and E
is at the HIGH level.
EPSON
Rev. 2.4a
S1D15605 Series
(3) The Serial Interface
tCSS
CS1
(CS2="1")
tCSH
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Figure 39
Table 32
Item
Serial Clock Period
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Rev. 2.4a
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
EPSON
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
200
—
ns
75
—
ns
75
—
ns
50
—
ns
100
—
ns
50
—
ns
50
—
ns
100
—
ns
100
—
ns
8–77
S1D15605 Series
Table 33
Item
Serial Clock Period
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
250
—
ns
100
—
ns
100
—
ns
150
—
ns
150
—
ns
100
—
ns
100
—
ns
150
—
ns
150
—
ns
Table 34
Item
Serial Clock Period
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Rating
Condition
Units
Min.
Max.
400
—
ns
150
—
ns
150
—
ns
250
—
ns
250
—
ns
150
—
ns
150
—
ns
250
—
ns
250
—
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
8–78
EPSON
Rev. 2.4a
S1D15605 Series
(4) Display Control Output Timing
CL
(OUT)
tDFR
FR
Figure 40
Table 35
Item
FR delay time
Signal
Symbol
FR
tDFR
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C)
Rating
Condition
Units
Min.
Typ.
Max.
CL = 50 pF
—
10
40
ns
Table 36
Item
FR delay time
Signal
Symbol
FR
tDFR
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Rating
Condition
Units
Min.
Typ.
Max.
CL = 50 pF
—
20
80
ns
Table 37
Item
FR delay time
Signal
Symbol
FR
tDFR
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C)
Rating
Condition
Units
Min.
Typ.
Max.
CL = 50 pF
—
50
200
ns
*1 Valid only when the master mode is selected.
*2 All timing is based on 20% and 80% of VDD.
Rev. 2.4a
EPSON
8–79
S1D15605 Series
Reset Timing
tRW
RES
tR
Internal
status
During reset
Reset complete
Figure 41
Table 38
Item
Reset time
Reset LOW pulse width
Signal
Symbol
tR
RES
tRW
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C)
Rating
Condition
Units
Min.
Typ.
Max.
—
—
0.5
µs
0.5
—
—
µs
Table 39
Item
Reset time
Reset LOW pulse width
Signal
Symbol
tR
RES
tRW
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Rating
Condition
Units
Min.
Typ.
Max.
—
—
1
µs
1
—
—
µs
Table 40
Item
Reset time
Reset LOW pulse width
Signal
Symbol
tR
RES
tRW
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C)
Rating
Condition
Units
Min.
Typ.
Max.
—
—
1.5
µs
1.5
—
—
µs
*1 All timing is specified with 20% and 80% of VDD as the standard.
8–80
EPSON
Rev. 2.4a
S1D15605 Series
12. THE MPU INTERFACE (REFERENCE EXAMPLES)
The S1D15605 Series can be connected to either 80 × 86 Series MPUs or to 6800 Series MPUs. Moreover, using the
serial interface it is possible to operate the S1D15605 series chips with fewer signal lines.
The display area can be enlarged by using multiple S1D15605 Series chips. When this is done, the chip select signal
can be used to select the individual ICs to access.
(1) 8080 Series MPUs
VDD
VDD
A0
MPU
A1 to A7
IORQ
D0 to D7
RD
WR
RES
GND
A0
Decoder
RESET
CS1
CS2
D0 to D7
RD
WR
RES
VSS
C86
S1D15605 Series
VCC
P/S
VSS
Figure 42-1
(2) 6800 Series MPUs
VDD
VDD
MPU
A0
A1 to A15
VMA
D0 to D7
E
R/W
RES
GND
A0
Decoder
RESET
CS1
CS2
D0 to D7
E
R/W
RES
VSS
C86
S1D15605 Series
VCC
P/S
VSS
Figure 42-2
(3) Using the Serial Interface
VDD or
VSS
VDD
A0
MPU
A1 to A7
A0
Decoder
Port 1
Port 2
RES
GND
RESET
CS1
CS2
SI
SCL
RES
VSS
C86
S1D15605 Series
VCC
P/S
VSS
Figure 42-3
Rev. 2.4a
EPSON
8–81
S1D15605 Series
13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE)
The liquid crystal display area can be enlarged with ease through the use of multiple S1D15605 Series chips. Use a same
equipment type.
(1) S1D15605 (master) ↔ S1D15605 (slave)
VDD
S1D15605 Series
Master
FR
FR
CL
CL
DOF
DOF
Output
Input
S1D15605 Series
Slave
M/S
M/S
VSS
Figure 43
8–82
EPSON
Rev. 2.4a
S1D15605 Series
14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES)
The liquid crystal display area can be enlarged with ease through the use of multiple S1D15605 Series chips.
Use a same equipment type, in the composition of these chips.
(1) Single-chip Structure
132 x 65 Dots
COM
SEG
COM
S1D15605 Series
Master
Figure 44-1
(2) Double-chip Structure, #1
264 x 65 Dots
COM
SEG
SEG
S1D15605 Series
Master
COM
S1D15605 Series
Slave
Figure 44-2
Rev. 2.4a
EPSON
8–83
S1D15605 Series
15. A SAMPLE TCP PIN ASSIGNMENT
S1D15605T00B* TCP Pin Layout
Note: The following does not specify dimensions of the TCP pins.
An example
FR
FR
FRS
CL
DOF
VSS
VSS2
VOUT
CAP3CAP1+
CAP1CAP2CAP2+
VRS
VDD
COM S
COM 63
•
•
•
•
•
COM 33
COM 32
CHIP TOP VIEW
CS1
CS2
RES
A0
WR,R/W
RD, E
D0
D1
D2
D3
D4
D5
D6, SCL
D7, SI
VDD
SEG 131
SEG 130
•
•
•
•
•
SEG 1
V1
SEG 0
V2
COM S
V3
COM 0
V4
V5
•
VR
VDD
•
M/S
CLS
C86
P/S
HPM
IRS
•
•
•
COM 30
COM 31
8–84
EPSON
Rev. 2.4a
Rev. 2.4a
EPSON
(Mold, marking area) (Mold, marking area)
Section A
Output terminal pattern shape
Section B
Test pat detailed view
(Mold, marking area)
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 25µm
• Sn plating
• Product pitch: 41P (19.0mm)
• Solder resist positional tolerance: ±0.3
(Mold, marking area)
Section A
Section A
S1D15605 Series
16. EXTERNAL VIEW OF TCP PINS
8–85
9. S1D15700 Series
Rev. 3.0
Contents
1. DESCRIPTION ................................................................................................................................................ 9-1
2. FEATURES ...................................................................................................................................................... 9-1
3. PAD ................................................................................................................................................................. 9-1
4. PIN DESCRIPTION ......................................................................................................................................... 9-4
5. BLOCK DIAGRAM ........................................................................................................................................... 9-5
6. FUNCTION DESCRIPTION ............................................................................................................................. 9-6
7. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 9-10
8. ELECTRICAL CHARACTERISTICS ..............................................................................................................9-11
9. LCD DRIVER POWER SUPPLY ...................................................................................................................9-14
10. EXAMPLE OF APPLICATION .......................................................................................................................9-15
–i–
Rev. 3.0
S1D15700 Series
1. DESCRIPTION
2. FEATURES
The S1D15700 is an 80 output segment (column) driver
with an internal display RAM. This drive is suitable for
driving a dot matrix LCD panel; from a mid-range
capacity dot matrix LCD panel to a CGA class dot matrix
LCD panel. This device is used with the S1D16305.
The display data is stored in the internal display RAM
and an LCD panel drive signal is generated. As a result,
this device allows configuration of an ultra low power
display system since the display data is not transferred
unless the display is changed.
In addition, the logic power is low voltage; a wide range
of applications is possible.
•
•
•
•
•
•
•
•
•
•
•
Display duty cycle: 1/64 – 1/200
LCD driver output: 80 out
Internal display RAM: 200 × 80 bits
Slim chip
Ultra low power consumption
Power
VDD – VSS
2.7 V to 5.5 V
VDD – VEE
8.0 V to 20 V
High speed and low power date transfer by the 4-bit
bus enables chain method
Non-bias display off function
Output shift direction-pin selection
Adjustable LCD power offset bias for VDD level
Package Chip
S1D15700D00A* (Al-pad chip)
S1D15700D00B* (Au-bump chip)
3. PAD
Pad Layout
31
1
32
99
Y
X
49
D1570D
82
50
Rev. 3.0
81
S1D15700D00A*
Chip Size
Pad Center Size
Pad Pitch
Chip Thickness
(Al-pad chip)
8.04 mm × 3.51 mm
100 µm × 100 µm
170 µm (Min.)
400 µm ±25 µm (Al Pad)
S1D15700D00B*
Bump Size
Pump Pitch
Chip Thickness
Bump Height
(Al-bump chip)
92 µm × 82 µm
170 µm (Min.)
525 µm
17~28 µm (reference)
EPSON
9–1
S1D15700 Series
S1D15700 Pad Center Coordinates (Al-pad)
Unit: µm
PAD
No
PIN
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
X 75
X 76
X 77
X 78
X 79
X 80
EIO2
VDD
SHL
D0
D1
D2
D3
YD
VEE
V5
V3
V2
V0
FR
XSCL
DOFF
LP
VSS
EIO1
X1
X2
X3
X4
X5
X6
X7
X8
X9
X 10
X 11
X 12
X 13
X 14
X 15
9–2
X
Y
3640
3432
3224
3016
2808
2600
2340
2080
1820
1560
1300
1040
780
520
260
0
–260
–520
–780
–1040
–1300
–1560
–1820
–2080
–2340
–2600
–2808
–3016
–3224
–3432
–3640
–3862
1595
1452
1282
1112
942
772
602
432
262
92
PAD
No
PIN
Name
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
X 16
X 17
X 18
X 19
X 20
X 21
X 22
X 23
X 24
X 25
X 26
X 27
X 28
X 29
X 30
X 31
X 32
X 33
X 34
X 35
X 36
X 37
X 38
X 39
X 40
X 41
X 42
X 43
X 44
X 45
X 46
X 47
X 48
X 49
X 50
X 51
X 52
X 53
X 54
X 55
X
Y
–3862
–78
–248
–418
–588
–758
–928
–1098
–1268
–1438
–1595
–3641
–3406
–3171
–2936
–2701
–2466
–2231
–1996
–1761
–1526
–1291
–1056
–821
–586
–351
–116
119
354
589
824
1059
1294
1530
1765
2000
2235
2470
2705
2940
3175
3410
EPSON
PAD
No
PIN
Name
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
X 56
X 57
X 58
X 59
X 60
X 61
X 62
X 63
X 64
X 65
X 66
X 67
X 68
X 69
X 70
X 71
X 72
X 73
X 74
X
Y
3645
3862
–1595
–1438
–1268
–1098
–928
–758
–588
–418
–248
–78
92
262
432
602
772
942
1112
1282
1452
Rev. 3.0
S1D15700 Series
(Au-bump) Unit: µm
Unit: µm
PAD
No
PIN
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
X 75
X 76
X 77
X 78
X 79
X 80
EIO2
V DD
SHL
D0
D1
D2
D3
YD
VEE
V5
V3
V2
V0
FR
XSCL
DOFF
LP
VSS
EIO1
X1
X2
X3
X4
X5
X6
X7
X8
X9
X 10
X 11
X 12
X 13
X 14
X 15
Rev. 3.0
X
Y
3640
3432
3224
3016
2808
2600
2340
2080
1820
1560
1300
1040
780
520
260
0
–260
–520
–780
–1040
–1300
–1560
–1820
–2080
–2340
–2600
–2808
–3016
–3224
–3432
–3640
–3868
1601
1452
1282
1112
942
772
602
432
262
92
PAD
No
PIN
Name
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
X 16
X 17
X 18
X 19
X 20
X 21
X 22
X 23
X 24
X 25
X 26
X 27
X 28
X 29
X 30
X 31
X 32
X 33
X 34
X 35
X 36
X 37
X 38
X 39
X 40
X 41
X 42
X 43
X 44
X 45
X 46
X 47
X 48
X 49
X 50
X 51
X 52
X 53
X 54
X 55
X
Y
–3868
–78
–248
–418
–588
–758
–928
–1098
–1268
–1438
–1601
–3641
–3406
–3171
–2936
–2701
–2466
–2231
–1996
–1761
–1526
–1291
–1056
–821
–586
–351
–116
119
354
589
824
1059
1294
1530
1765
2000
2235
2470
2705
2940
3175
3410
EPSON
PAD
No
PIN
Name
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
X 56
X 57
X 58
X 59
X 60
X 61
X 62
X 63
X 64
X 65
X 66
X 67
X 68
X 69
X 70
X 71
X 72
X 73
X 74
X
Y
3645
3868
–1601
–1438
–1268
–1098
–928
–758
–588
–418
–248
–78
92
262
432
602
772
942
1112
1282
1452
9–3
S1D15700 Series
4. PIN DESCRIPTION
Pin Name
I/O
X1 – X80
O
D0 – D3
XSCL
I
I
LP
I/O
EIO1
EIO2
I/O
SHL
I
Function
LCD drive segment (column) output
The output changes with the LP’s trailing edge.
Display data input
Display data shift clock input
Reads the display data (D0 – D3) into the data register with a trailing
edge.
Display data latch clock input
• The display RAM data (specified by the low address shift register) is read
into the latch with a leading edge, and the LCD display data is output.
• For a specified low address, the contents of the write register are written
in the display RAM. (At Data transfer mode)
• Resets the enable control circuit.
Enable I/O
• Configured by SHL.
• Output is reset to HIGH by LP input. When the 80 bit display data is read,
the output falls to LOW automatically.
• To connect in cascade format, connect these pins to the next level EIO.
Shift direction and input/output select input
• If the display data is entered in the input (D3, D2, D1, D0) in the order of
(a1, a2, a3, a4) (b1, b2, b3, b4) … (t1, t2, t3, t4), the relationship of the
display data and the segment output is as given in the table below.
No. of
Pins
80
4
1
1
2
1
Xn (SEG output)
EIO
80 79 78 77 76 75 … 6 5 4 3 2 1 1 2
LOW a1 a2 a3 a4 b1 b2 … s3 s4 t1 t2 t3 t4 O I
HIGH t4 t3 t2 t1 s4 s3 … b2 b1 a4 a3 a2 a1 I O
SHL
DOFF
I
FR
YD
I
I
V0, V2,
V3, V5
VEE
VDD, V SS
9–4
Power
supply
Power
supply
Power
supply
Forced blank input
In the LOW level, the segment output is forced to the V0 level.
The display RAM data is maintained.
LCD AC drive signal input
Scan start input
• Rests the low address counter decoder.
• The number of scanned lines (number of low addresses) for the
display RAM is determined by the number of LP pulses, which are
input in one YD cycle.
LCD drive power input
VDD ≥ V0 ≥ V2 ≥ V3 ≥ V5 ≥ VEE
LCD drive power input VDD – VEE
Logic power input
VDD : connect to the system VCC pin.
VSS: connect to the system GND.
EPSON
1
1
1
4
1
2
Rev. 3.0
S1D15700 Series
5. BLOCK DIAGRAM
X1
X80
--------------------
VDD
V0
V2
LCD Driver
V3
V5
80 OUT
VSS
VEE
Level Shifter
FR
Latch 80 OUT
DOFF
YD
Row
Address
Counter
Decoder
Display RAM
200 x 80
LP
Data Register 80 bit
XSCL
Control Gate
D0 to D3
Enable Shift Register
20 bit
Data Control
SHL
Enable
Control
Rev. 3.0
EPSON
E101
E102
9–5
S1D15700 Series
6. FUNCTION DESCRIPTION
Enable Shift Register
Data Register
The order of the display data latched is reversed by the
SHL input.
This 80 bit register controls the write operation into the
display RAM. The data is written in the display RAM
with the trailing edge of the LP signal. In the self-refresh
mode, the data is not written in the display RAM.
Enable Control and Data Control
If the enable signal is disabled (EIO = HIGH), the
internal clock signal and the data bus are fixed to LOW.
This is a power-save mode.
To use multiple segment drivers, connect in cascade
format the EIO pin of each driver, and connect the EIO
pin of the first driver to the “VSS” pin.
The enable control circuit automatically detects when the
80 bit data has been read and automatically transfers the
enable signal. As a result, a control signal by a control
LSI is not necessary.
Display RAM
This is a static RAM (200 × 80 bits) that stores the LCD
data.
The display RAM data (80 bit) for the low address is read
out to the latch with the trailing edge of the LP signal. In
addition, with the trailing edge of the LP signal, the
contents of the data register is moved to the write register.
The contents of the write register are then written in the
display RAM area for the low address. The low address
is then incremented.
If the XSCL signal does not come in after the trailing
edge of the LP signal, the mode is changed to the selfrefresh mode. The write register does not write data in
the display RAM and the low address is incremented.
The mode is then changed to the read out mode to read the
next line.
Control Circuit
The control circuit detects the self-refresh mode, allows
the write register to write the data into the display RAM,
and controls and low address count signal.
Latch
This reads the 80 bit data for the low address of the
display RAM with the trailing edge of the LP signal, and
sends the output signal to the level shifter.
Level Shifter
This is the level interface circuit that converts the signal
voltage level from VDD – VSS to VDD – VEE (LCD driver
power).
LCD Driver
The LCD driver outputs the LCD driver voltage.
The table below shows the relationship between the
display signals (D3 – D0 ), LCD AC-drive wave form
(FR) and the segment output voltage.
DOFF
HIGH
D0 – D3
FR
X Output Voltage
HIGH
HIGH
V0
LOW
V5
LOW
Low Address Counter Decoder
This selects a line of the display RAM in sequence. This
decoder catches the HIGH of the YD signal at the trailing
edge of the LP signal, and resets the low address counter.
It then initialize the selected address of the display RAM.
In a normal operation, the decoder is incremented after
the writing operation into the display RAM. (The writing
operation is caused by the trailing edge of the LP signal.)
In the self-refresh mode, the decoder is incremented
without the writing operation into the display RAM.
9–6
EPSON
LOW
—
HIGH
V2
LOW
V3
—
V0
Rev. 3.0
S1D15700 Series
Self-Refresh Function
Setting self-refresh mode
The self-refresh mode functions as follows: if the displayed contents do not change, there is no transfer of the
display data from the display controller to the S1D15700.
The S1D15700 automatically detects this and powerdown is displayed.
The S1D15700 is set to the self-refresh mode by maintaining the shift clock (XSCLK) in the “L” level for 1
horizontal display period (LP signal cycle) after the row
data for 1 line has been input. The S1D15700 checks the
mode (whether or not the mode is changed to the selfrefresh mode) every 1 horizontal display period. During
1 horizontal display period in which XSCL stops working, the display data is not written into the S1D15700
display RAM.
To stop XSCL, terminate display data (D0 – D3) transfer
from the display controller (because of the power down),
and set XSCL to HIGH or LOW. At this time, the display
control must periodically send the LP, YD, and FR
signals to the S1D15700 the same way as when data is
transferred. The S1D15700 inputs these signals, reads
the display data periodically from the internal display
RAM and refreshes the display.
The display-off function is available in the self-refresh
mode.
Rev. 3.0
Canceling self-refresh mode
The self-refresh mode is canceled as follows: The
display controller inputs the shift clock (XSCL) into the
S1D15700 for one horizontal display period or longer.
This should be down with the trailing edge of the LP
signal and in the data transfer timing. After the mode is
canceled, the line data, which has been sent in the
horizontal display period, is written in the display RAM
at the time of the next trailing edge of the LP signal.
If the S1D15700s are connected in cascade format, the
self-refresh modes of all S1D15700s are not canceled
unless the appropriate number of the XSCL clocks for the
cascaded S1D15700s are entered.
EPSON
9–7
S1D15700 Series
Timing Diagram
Sample of 1/200 duty
YD
200
1
2
3
4
199
200
1
2
1
2
3
199
200
1
LP
LATCH
DATA
FR
LP
XSCL
D0 ~ D3
20
1
2
3
19
20
19
20
1
2
19
20
L
H
L
H
H
H
1
2
1
DIO 1
DIO 2
DIO n
1 ~ n serial conection number of Driver IC
LP
LATCH
DATA
H
FR
H
L
H
L
H
L
L
L
H
L
L
DOFF
V0
V2
V3
V5
9–8
EPSON
Rev. 3.0
S1D15700 Series
Self-refresh mode timing
YD
LP
INPUT
DATA
(D0 ~ D3)
Flame 1 Flame 1
Line 1
Line 2
Flame 1
Line 4
Flame 2 Flame 2
Line 1
Line 2
Flame 2
Line 4
DISPLAY
DATA
Flame 1 Flame 1 Flame 0 Flame 1
Line 1
Line 2 Line 3
Line 4
Data transfer mode
Self-refresh mode
Data transfer mode
LP
XSCL
Write register
output data
RAM
address
Flame 1
Line 1
Line 1
Flame 1
Line 2
Line 2
Line 3
Line 4
READ
READ
RAM
W/R timing
READ
Latch data
Rev. 3.0
WRITE
Flame 0
READ
Line 1
WRITE
Flame 0
EPSON
Line 2
Flame 0
Line 3
9–9
S1D15700 Series
7. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
–7.0 to +0.3
Supply voltage 1
VSS
–22.0 to +0.3
Supply voltage 2
VEE
VEE –0.3 to VDD +0.3
Supply voltage 3
V0, V2, V 3, V5
VSS –0.3 to VDD +0.3
Input voltage
VI
VSS –0.3 to VDD +0.3
Output voltage
VO
EIO output current
I01
20
Operating temperature
Topr
–40 to +85
Storage temperature 1
Tstg1
–65 to +150
Storage temperature 2
Tstg2
–55 to +100
Notes: 1. All voltages are given relative to VDD = 0 V.
2. For storage temperature 1 – Plastic package
For storage temperature 2 – TAB mounted
3. V0, V 2, V3, and V5 must satisfy the condition
VDD ≥ V0 ≥ V2 ≥ V3 ≥ V5 ≥ VEE
Unit
V
V
V
V
V
mA
°C
°C
°C
VDD
VDD
–2.7 V
V0
VSS
V2
–20 V
V3
V5
VEE
VEE
4. If the logic power is being floated or if the Vss voltage exceeds -2.5 Vdc during LCD power-on,
the LSI chips may be damaged permanently. Take care not to damage the chips especially in
the system power on/off sequence.
9–10
EPSON
Rev. 3.0
S1D15700 Series
8. ELECTRICAL CHARACTERISTICS
DC Characteristics
VDD = V0 = 0 V, VSS = –5.0 V ±10%, Ta = –40 to 85°C
Item
Symbol
Supply voltage (1)
V SS
Condition
Min.
Typ.
Max.
Unit
Pin
–5.5
–5.0
–2.7
V
V SS
Recommended
operation voltage
V EE
–20.0
–8.0
V
V EE
Supply voltage (2)
V0
Supply voltage (3)
V2
Recommended value
VDD –2.5
V DD
V
V0
Recommended value
2/9 VEE
V
V2
Supply voltage (4)
V3
Recommended value
7/9 VEE
V
V3
Supply voltage (5)
V5
Recommended value
V EE +2.5
V
V5
VSS = –2.7 to –5.5V
V
V
EIO1, EIO2,
FR, D0 to D3,
YD, LP, SHL,
DOFF, XSCL
V
EIO1, EIO2
VSS = –2.7 to –5.5V
VEE
Input high voltage
VIH
Input low voltage
VIL
0.2•VSS
Output high voltage
V OH
VSS = –2.7
IOH = –0.6mA
Output low voltage
V OL
to –5.5 V
IOL = 0.6mA
0.8•VSS
VDD –0.4
V DD +0.4
V
I LI
VSS ≤ VIN ≤ VDD
2.0
µA
D0 to D3, LP,
FR, YD, XSCL,
SHL, DOFF
I/O leakage current
ILI/O
VSS ≤ VIN ≤ VDD
5.0
µA
EIO1, EIO2
Static current
ISS
V5 = –20.0 to –10.0 V
VIH = VDD, VIL = VSS
25
µA
V SS
On resistance
R SEG
∆VON = 0.5 V, V 0 = VDD,
V3 = 7/9•VEE, V2 = 2/9•VEE
VEE = V5 = –14.0 V
1.0
1.4
kΩ
X1 to X80
Average
Data
current
transfer
consump- mode
tion (1)
IDDT
VSS = –5.0 V, VIH = VDD
VIL = VSS, f XSCL = 4.0 MHz
fLP = 14 kHz, fFR = 70 Hz
Checkered pattern,
non-burden
VDD = V0 = 0V V2 = –4 V
V3 = –16 V, VEE = V5 = –20 V
0.3
0.8
mA
VDD
Selfrefresh
mode
IDDS
fXSCL = 0 Hz = VSS
Another place is same as
IDDT item
70
200
µA
Average current
consumption (2)
IEE
VSS = –5.0 V, V0 = 0.0 V
V2 = –4 V, V3 = –16 V
IEE = V 5 = –20.0 V
Another place is same as
IDDT item
25
70
µA
V EE
Input capacitance
CI
Freq. = 1 MHz, Ta = 25°C
Simple substance of CHIP
8
pF
D0 to D3, LP,
FR, YD, XSCL,
SHL, DOFF
15
pF
EIO1, EIO2
Input leakage
current
I/O capacitance
Rev. 3.0
CI/O
EPSON
9–11
S1D15700 Series
AC Timing
V IH = 0.2 V SS
V IL = 0.8 V SS
Input timing
YD
t YDS
t YDH
FR
t WLL
t WLH
t DF
LP
tC
t LD
t LH
XSCL
t DS
t DH
t WCH
t WCL
D0~D3
t SUE
EIO
(IN)
Item
XSCL cycle time
XSCL high level pulse width
XSCL low level pulse width
Data setup time
Data hold time
XSCL
→ LP
LP
→ XSCL
LP high level pulse width
LP low level pulse width
FR phase difference
EIO setup time
YD setup time
YD hold time
Rise/fall time
Symbol
t WCH
tWCL
tDS
tDH
tLD
tLH
tWLH
tWLL
tDF
tSUE
tYDS
tYDH
tr, tf
Item
Symbol
tC
XSCL cycle time
XSCL high level pulse width
tWCH
XSCL low level pulse width
tWCL
Data setup time
tDS
Data hold time
tDH
XSCL
→ LP
tLD
LP
→ XSCL
tLH
LP high level pulse width
tWLH
LP low level pulse width
tWLL
FR phase difference
tDF
EIO setup time
tSUE
YD setup time
tYDS
YD hold time
tYDH
Rise/fall time
tr, tf
*: Recommended tWLH value = tC
9–12
Condition
tC
*
*
VSS = –5.0 V ±10%, Ta = –40 to 85°C
Min.
Max.
Unit
150
ns
30
ns
30
ns
20
ns
15
ns
10
ns
70
ns
40
ns
600
ns
–300
+300
ns
35
ns
40
ns
40
ns
30
ns
VSS = –4.5 V to –2.7 V, Ta = –40 to 85°C
Condition
Min.
Max.
Unit
250
ns
70
ns
70
ns
50
ns
50
ns
80
ns
140
ns
75
ns
1200
ns
–300
+300
ns
50
ns
80
ns
80
ns
30
ns
EPSON
Rev. 3.0
S1D15700 Series
Output Timing
V IH = 0.2 V SS
V IL = 0.8 V SS
FR
t FRSD
LP
t LSD
XSCL
t ER
t DCL
EIO
(OUT)
Xn
Item
EIO reset time
EIO output delay time
LP → Xn output delay time
FR → Xn output delay time
Item
EIO reset time
EIO output delay time
LP → Xn output delay time
FR → Xn output delay time
Rev. 3.0
Symbol
tER
tDCL
tLSD
tFRSD
VDD = –5.0 ±10%, VEE = –8.0 to –20.0 V, Ta = –40 to 85°C
Condition
Min.
Max.
Unit
CL = 15 pF
90
ns
(EIO)
VSS = –2.7 V
55
ns
CL = 100 pF
400
ns
400
ns
VDD = –4.5 V to –2.7 V, V EE = –8.0 to –20.0 V, Ta = –40 to 85°C
Symbol
Condition
Min.
Max.
Unit
tER
CL = 15 pF
150
ns
tDCL
(EIO)
VSS = –2.7 V
95
ns
tLSD
CL = 100 pF
800
ns
tFRSD
800
ns
EPSON
9–13
S1D15700 Series
9. LCD DRIVER POWER SUPPLY
Generating LCD Drive Voltages
System Power-up
To obtain individual voltage levels for LCD driver,
register-split the potential between VEE – VDD and drive
the LCD with the voltage follower using the operation
amplifier. When using an operation amplifier, V 0 and
VDD, V5 and VEE are separated.
However, if the potential of V0 is lower than VDD
potential or V5 is higher than V EE and the potential
difference increases, the LCD driver capability decreases.
To avoid this, set VDD and V0 or V5 and VEE within 0 V
to 2.5 V. If an operation amplifier is not used, connect V0
and VDD, V5 and VEE.
If there are direct resistors on the VEE (VDD) power line,
voltage falls in VEE (VDD) at the LSI power pins. This is
caused by IDD (IEE) at the time of signal change. As a
result, the relationship (VDD ≥ V0 ≥ V2 ≥ V3 ≥ V5 ≥ VEE)
for intermediate potential of LCD can not be maintained
and the LSI may be damaged.
To insert a protective resistor, the voltage must be stabilized according to the capacity.
This LSI has high LCD drive voltage. As a result, if the
logic power is being floated or if the V SS voltage is kept
above –2.5Vdc and high voltage is applied in the LCD
driver, the LSI may be damaged because of the excess
current.
Until the LCD drive voltage is stabilized, use the display
off function (DOFF) to set the potential of the LCD drive
output to V0 level.
Follow the sequence given below when turning the
power on/off.
To turn on the power – Turn on the logic power
→ Turn the LCD driver on.
(On turn them on simultaneously.)
To turn off the power – Turn off the LCD driver
→ Turn off the logic power.
(Or turn them off simultaneously.)
To avoid excess current, insert the high-speed fuse in
series with the LCD power. Select the appropriate value
for a protective resistor according to the capacity of a
LCD cell.
V
t1
t2
VDD
VSS
t3
t1, t2, t3 ≥ 0s
VEE
DOFF
VDD
VSS
9–14
EPSON
Rev. 3.0
Rev. 3.0
EPSON
D0 ~ 3
EIO1
1
S1D15700
EIO2
V EE
SHL
DOFF
LP
XSCL
S1D16700
100
V SS
80
EIO1
2
S1D15700
80
EIO2
D O T
D U T Y
2 0 0
VDD
SHL = [H]
V5
1 / 2 0 0
×
V0
DIO2
r
640
r
DIO1
DIO2
V SS
FR
SHL
DIO1
V4
YSCL
V3
YD
SHL = [L]
–+
–+
r
V2
S1D16700
100
R
V1
–+
r
– +
EIO1
8
S1D15700
80
EIO2
S1D15700 Series
10. EXAMPLE OF APPLICATION
Constitution of LCD
9–15
10. S1D15705 Series
Rev. 3.1a
Contents
1. DESCRIPTION ..............................................................................................................................................10-1
2. FEATURES .................................................................................................................................................... 10-1
3. BLOCK DIAGRAM ......................................................................................................................................... 10-3
4. PAD ...............................................................................................................................................................10-4
5. PIN DESCRIPTION .....................................................................................................................................10-14
6. FUNCTION DESCRIPTION ......................................................................................................................... 10-18
7. COMMAND .................................................................................................................................................. 10-38
8. COMMAND SETTING ................................................................................................................................. 10-50
9. ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 10-54
10. DC CHARACTERISTICS .............................................................................................................................10-55
11. MICROPROCESSOR (MPU) INTERFACE: REFERENCE ......................................................................... 10-70
12. CONNECTION BETWEEN LCD DRIVERS: REFERENCE ........................................................................10-71
13. LCD PANEL WIRING: REFERENCE ..........................................................................................................10-72
14. TCP PIN LAYOUT ....................................................................................................................................... 10-73
15. TCP DIMENSIONS ......................................................................................................................................10-74
16. TEMPERATURE SENSOR CIRCUIT ..........................................................................................................10-75
–i–
Rev. 3.1a
S1D15705 Series
1. DESCRIPTION
The S1D15705 series is a 1-chip dot matrix liquid
crystal driver that can be connected to the bus of a
microcomputer. It stores the 8-bit parallel or serial
display data sent from the microcomputer in the built-in
display data RAM and generates liquid crystal drive
signals independently of the microcomputer. Since it
incorporates 65 × 200 bits of the display data RAM and
the one-dot pixel of the liquid crystal panel and one bit
of the built-in RAM have a one-to-one correspondence,
it enables display with the high degree of freedom.
The S1D15705 series incorporates 65 circuits of the
common output and 168 circuits of the segment output
and can display 65 × 168 dots (capable of displaying 10
columns × 4 rows of a 16 × 16 dot kanji font) using the
single chip. The S1D15707 Series incorporates 33
circuits of the common output and 200 circuits of the
segment output and can display 33 × 200 dots (capable
of displaying 12 columns × 2 rows of a 16 × 16 dot kanji
font). The S1D15708 series incorporates 17 circuits of
the common output and 200 circuits of the segment
output and can display 17 × 200 dots (capable of
displaying 12 columns × 1 rows of a 16 × 16 dot kanji
font). It can also expand the display capacity by using
the two chips for the master and slave configuration.
Incorporating an analog temperature sensor circuit, the
S1D15705*10** can be used to constitute a system to
provide optimum LCD contrast throughout a wide
temperature range without need for use of supplementary
parts such as the thermistor, under controls of a
microcomputer.
Since the read/write operation of the display data RAM
does not require external operation clocks, the S1D15705
series can be operated with the minimum current
consumption. Since it also incorporates a liquid crystal
drive power supply with low current consumption,
liquid crystal drive power supply voltage adjusting
resistor, and display clock CR oscillator circuit, it can
provide a display system for high performance handy
equipment with the minimum current consumption and
the minimum parts configuration.
•
•
•
•
•
•
•
•
•
2. FEATURES
• Direct display of RAM data using the display data
RAM
RAM bit data “1” .... goes on.
“0” .... goes off (at display normal
rotation).
• RAM capacity
65 × 200 = 13,000 bits
• Liquid crystal drive circuit
The S1D15705 Series
65 circuits for the common output and 168 circuits
for the segment output
Rev. 3.1a
•
•
•
•
EPSON
The S1D15707 Series
33 circuits for the common output and 200 circuits
for the segment output
The S1D15708 Series
17 circuits for the common output and 200 circuits
for the segment output
High-speed 8-bit MPU interface (Both the 80 and 68
series MUPs can directly be connected.)/serial
interface enabled
Abundant command functions
Display Data Read/Write, Display ON/OFF, Display
Normal Rotation/Reversal, Page Address Set, Display
Start Line Set, column address set, Status Read,
Power Supply Save Display All Lighting ON/OFF,
LCD Bias Set, Read Modify Write, Segment Driver
Direction Select, Electronic Control, V5 Voltage
Adjusting Built-in Resistance Ratio Set, Static
Indicator, n Line Alternating Current Reversal Drive,
Common Output State Selection, and Built-in
Oscillator Circuit ON
Built-in static drive circuit for indicators (One set,
blinking speed variable)
Built-in power supply circuit for low power supply
liquid crystal drive
Booster circuit (Boosting magnification - double,
triple, quadruple, boosting reference power supply
external input enabled)
3% high accuracy alternating current voltage adjusting
circuit (Temperature gradient: –0.05%/°C)
Built-in V5 voltage adjusting resistor, built-in V1 to
V4 voltage generation split resistors, built-in
electronic control function, and voltage follower
Built-in CR oscillator circuit (external clock input
enabled)
Ultra-low power consumption
Built-in temperature sensor circuit (S1D15705D10B*)
Power supplies
Logic power supply: VDD – VSS = 2.4 to 3.6 V
(S1D15705*03**, S1D15707*03**)
VDD – VSS = 3.6 to 5.5 V
(S1D15705*00**, S1D15707*00**, S1D15708*00**)
Boosting reference power supply: VDD – VSS = 1.8 to
6.0 V
Liquid crystal drive power supply: V5 – VDD = –4.5 to
–18.0 V (S1D15705*****) /–4.5 V to –16.0 V
(S1D15707*****) /–4.5 V to –10.0 (S1D15708*****)
Wide operating temperature range –40 to 85°C
CMOS process
Shipping form Bare chip, TCP
No light-resistant and radiation-resistant design are
provided.
10–1
S1D15705 Series
Series specification
Product
Voltage
Duty
name
[V]
S1D15705D00B* –3.6 to –5.5 1/65
S1D15705D10B* –3.6 to –5.5 1/65
S1D15705D03B* –2.4 to –3.6 1/65
S1D15705T00A* –3.6 to –5.5 1/65
S1D15705T03A* –2.4 to –3.6 1/65
S1D15707D00B* –3.6 to –5.5 1/33
S1D15707D03B* –2.4 to –3.6 1/33
S1D15707T00** –3.6 to –5.5 1/33
S1D15707T03** –2.4 to –3.6 1/33
S1D15708D00B* –3.6 to –5.5 1/17
Bias
SEG Dr
COM Dr
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/6, 1/5
1/6, 1/5
1/6, 1/5
1/6, 1/5
1/6, 1/5
168
168
168
168
168
200
200
200
200
200
65
65
65
65
65
33
33
33
33
17
VREG temperature
gradient
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
Shipping
form
Bare chip
Bare chip
Bare chip
TCP
TCP
Bare chip
Bare chip
TCP
TCP
Bare chip
∗Specifications for circuits other than the temperature sensor circuit are the same as those of the
S1D15705D00B*.
10–2
EPSON
Rev. 3.1a
S1D15705 Series
3. BLOCK DIAGRAM
COMS
• • • • • • • • • •
COM63
COM0
• • • • • • • • • • • • • • • • • • • • • • • • •
SEG167
SEG0
Example : S1D15705*****
VSS
V2
V3
SEG Drivers
COMS
VDD
V1
COM Drivers
V4
V5
Shift register
Display data latch circuit
CAP1+
Display timing generator circuit
Line address
VSS2
VR
I/O buffer
VOUT
Page address
CAP2+
CAP2–
CAP3–
Power supply circuit
CAP1–
Display data RAM
200 x 65
VRS
IRS
HPM
FRS
FR
SYNC
CL
DOF
M/S
Oscillator circuit
Column address
Bus holder
Command decoder
CLS
Status
Rev. 3.1a
EPSON
D0
D1
D2
D3
D4
D5
D6 (SCL)
D7 (SI)
RES
P/S
WR (R/W)
RD (E)
A0
CS2
CS1
MPU Interface
10–3
S1D15705 Series
4. PAD
Pad layout
93
1
94
337
D1575D0B
S1D15705 Series
Die No.
(ex. S1D15705D00B*)
(0, 0)
303
128
129
302
Item
Chip size
Chip thickness
Bump pitch
Bump size
PAD No.1 to 93
PAD No.94
PAD No.95 to 127
PAD No.128
PAD No.129
PAD No.130 to 301
PAD No.302
PAD No.303
PAD No.304 to 336
PAD No.337
Bump height
10–4
Size
X
13.30
85
85
85
85
73
47
73
86
85
85
EPSON
×
0.625
71 (Min.)
×
×
×
×
×
×
×
×
×
×
17 (Typ.)
Y
2.81
85
73
47
73
85
85
85
73
47
73
Unit
mm
mm
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
Rev. 3.1a
S1D15705 Series
S1D15705***** Pad Central Coordinates
Unit: µm
PAD
PIN
No.
Name
1
(NC)
2
(NC)
3
SYNC
4
FRS
5
FR
6
CL
7
DOF
8
SYNC
9
VSS
10
CS1
11
CS2
12
VDD
13
RES
14
A0
15
VSS
16 WR, R/W
17
RD, E
18
VDD
19
D0
20
D1
21
D2
22
D3
23
D4
24
D5
25 D6 (SCL)
26
D7 (SI)
27
VDD
28
VDD
29
VDD
30
VDD
31
VDD
32
VSS
33
VSS
34
VSS
35
VSS2
36
VSS2
37
VSS2
38
VSS2
39
VSS2
40
(NC)
41
VOUT
42
VOUT
43
CAP3–
44
CAP3–
45
(NC)
46
CAP1+
47
CAP1+
48
CAP1–
49
CAP1–
50
CAP2–
Rev. 3.1a
X
Y
6195
6059
5922
5786
5649
5513
5376
5240
5103
4967
4830
4694
4557
4421
4284
4148
4011
3875
3738
3602
3465
3329
3192
3056
2919
2783
2646
2512
2378
2245
2111
1977
1843
1709
1575
1441
1307
1173
1039
906
772
638
504
370
236
102
–32
–166
–300
–433
1246
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN
Name
CAP2–
CAP2+
CAP2+
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
TEST1
TEST2
TEST3
TEST4
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
COM31
COM30
COM29
COM28
COM27
COM26
X
Y
–567 1246
–701
–835
–969
–1103
–1237
–1371
–1505
–1639
–1772
–1906
–2040
–2174
–2308
–2442
–2576
–2710
–2844
–2978
–3111
–3245
–3379
–3513
–3647
–3781
–3915
–4049
–4185
–4322
–4458
–4595
–4731
–4868
–5004
–5141
–5277
–5414
–5550
–5687
–5836
–5956
–6076
–6195
–6474 1248
1163
1090
1017
945
872
799
EPSON
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
PIN
Name
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
X
Y
–6474
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–6232 –1246
–6147
–6075
–6002
–5930
–5859
–5787
–5715
–5643
–5571
–5499
–5427
–5355
–5283
–5212
–5140
–5068
–4996
–4924
–4852
–4780
–4708
10–5
S1D15705 Series
Unit: µm
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
10–6
PIN
Name
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
X
Y
–4636 –1246
–4564
–4493
–4421
–4349
–4277
–4205
–4133
–4061
–3989
–3917
–3846
–3774
–3702
–3630
–3558
–3486
–3414
–3342
–3270
–3199
–3127
–3055
–2983
–2911
–2839
–2767
–2695
–2623
–2552
–2480
–2408
–2336
–2264
–2192
–2120
–2048
–1976
–1905
–1833
–1761
–1689
–1617
–1545
–1473
–1401
–1329
–1258
–1186
–1114
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
PIN
Name
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
X
Y
–1042 –1246
–970
–898
–826
–754
–682
–611
–539
–467
–395
–323
–251
–179
–107
–35
36
108
180
252
324
396
468
540
612
683
755
827
899
971
1043
1115
1187
1259
1330
1402
1474
1546
1618
1690
1762
1834
1906
1977
2049
2121
2193
2265
2337
2409
2481
EPSON
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
PIN
Name
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
(NC)
X
Y
2553 –1246
2625
2696
2768
2840
2912
2984
3056
3128
3200
3272
3343
3415
3487
3559
3631
3703
3775
3847
3919
3990
4062
4134
4206
4278
4350
4422
4494
4566
4637
4709
4781
4853
4925
4997
5069
5141
5213
5284
5356
5428
5500
5572
5644
5716
5788
5860
5931
6003
6075
Rev. 3.1a
S1D15705 Series
Unit: µm
PAD
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
PIN
Name
(NC)
(NC)
(NC)
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
(NC)
Rev. 3.1a
X
Y
6147 –1246
6232
↓
6474 –1248
–1163
–1090
–1018
–945
–872
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
EPSON
10–7
S1D15705 Series
S1D15707***** Pad Central Coordinates
Unit: µm
PAD
PIN
No.
Name
1
(NC)
2
(NC)
3
SYNC
4
FRS
5
FR
6
CL
7
DOF
8
SYNC
9
VSS
10
CS1
11
CS2
12
VDD
13
RES
14
A0
15
VSS
16 WR, R/W
17
RD, E
18
VDD
19
D0
20
D1
21
D2
22
D3
23
D4
24
D5
25 D6 (SCL)
26
D7 (SI)
27
VDD
28
VDD
29
VDD
30
VDD
31
VDD
32
VSS
33
VSS
34
VSS
35
VSS2
36
VSS2
37
VSS2
38
VSS2
39
VSS2
40
(NC)
41
VOUT
42
VOUT
43
CAP3–
44
CAP3–
45
(NC)
46
CAP1+
47
CAP1+
48
CAP1–
49
CAP1–
50
CAP2–
10–8
X
Y
6195
6059
5922
5786
5649
5513
5376
5240
5103
4967
4830
4694
4557
4421
4284
4148
4011
3875
3738
3602
3465
3329
3192
3056
2919
2783
2646
2512
2378
2245
2111
1977
1843
1709
1575
1441
1307
1173
1039
906
772
638
504
370
236
102
–32
–166
–300
–433
1246
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN
Name
CAP2–
CAP2+
CAP2+
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
TEST1
TEST2
TEST3
TEST4
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
COM31
COM30
COM29
COM28
COM27
COM26
X
Y
–567 1246
–701
–835
–969
–1103
–1237
–1371
–1505
–1639
–1772
–1906
–2040
–2174
–2308
–2442
–2576
–2710
–2844
–2978
–3111
–3245
–3379
–3513
–3647
–3781
–3915
–4049
–4185
–4322
–4458
–4595
–4731
–4868
–5004
–5141
–5277
–5414
–5550
–5687
–5836
–5956
–6076
–6195
–6474 1248
1163
1090
1017
945
872
799
EPSON
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
PIN
Name
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
X
Y
–6474
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–6232 –1246
–6147
–6075
–6002
–5930
–5859
–5787
–5715
–5643
–5571
–5499
–5427
–5355
–5283
–5212
–5140
–5068
–4996
–4924
–4852
–4780
–4708
Rev. 3.1a
S1D15705 Series
Unit: µm
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PIN
Name
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
Rev. 3.1a
X
Y
–4636 –1246
–4564
–4493
–4421
–4349
–4277
–4205
–4133
–4061
–3989
–3917
–3846
–3774
–3702
–3630
–3558
–3486
–3414
–3342
–3270
–3199
–3127
–3055
–2983
–2911
–2839
–2767
–2695
–2623
–2552
–2480
–2408
–2336
–2264
–2192
–2120
–2048
–1976
–1905
–1833
–1761
–1689
–1617
–1545
–1473
–1401
–1329
–1258
–1186
–1114
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
PIN
Name
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
X
Y
–1042 –1246
–970
–898
–826
–754
–682
–611
–539
–467
–395
–323
–251
–179
–107
–35
36
108
180
252
324
396
468
540
612
683
755
827
899
971
1043
1115
1187
1259
1330
1402
1474
1546
1618
1690
1762
1834
1906
1977
2049
2121
2193
2265
2337
2409
2481
EPSON
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
PIN
Name
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
(NC)
X
Y
2553 –1246
2625
2696
2768
2840
2912
2984
3056
3128
3200
3272
3343
3415
3487
3559
3631
3703
3775
3847
3919
3990
4062
4134
4206
4278
4350
4422
4494
4566
4637
4709
4781
4853
4925
4997
5069
5141
5213
5284
5356
5428
5500
5572
5644
5716
5788
5860
5931
6003
6075
10–9
S1D15705 Series
Unit: µm
PAD
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
10–10
PIN
X
Y
Name
(NC)
6147 –1246
(NC)
6232
↓
(NC)
6474 –1248
SEG168
–1163
SEG169
–1090
SEG170
–1018
SEG171
–945
SEG172
–872
SEG173
–800
SEG174
–727
SEG175
–654
SEG176
–581
SEG177
–509
SEG178
–436
SEG179
–363
SEG180
–291
SEG181
–218
SEG182
–145
SEG183
–73
SEG184
0
SEG185
73
SEG186
145
SEG187
218
SEG188
291
SEG189
363
SEG190
436
SEG191
509
SEG192
581
SEG193
654
SEG194
727
SEG195
799
SEG196
872
SEG197
945
SEG198
1017
SEG199
1090
COMS
1163
(NC)
1248
EPSON
Rev. 3.1a
S1D15705 Series
S1D15708***** Pad Central Coordinates
PAD
PIN
No.
Name
1
(NC)
2
(NC)
3
SYNC
4
FRS
5
FR
6
CL
7
DOF
8
SYNC
9
VSS
10
CS1
11
CS2
12
VDD
13
RES
14
A0
15
VSS
16
WR,R/W
17
RD, E
18
VDD
19
D0
20
D1
21
D2
22
D3
23
D4
24
D5
25 D6 (SCL)
26
D7 (SI)
27
VDD
28
VDD
29
VDD
30
VDD
31
VDD
32
VSS
33
VSS
34
VSS
35
VSS2
36
VSS2
37
VSS2
38
VSS2
39
VSS2
40
(NC)
41
VOUT
42
VOUT
43
CAP3–
44
CAP3–
45
(NC)
46
CAP1+
47
CAP1+
48
CAP1–
49
CAP1–
50
CAP2–
Rev. 3.1a
X
Y
6159
6059
5922
5786
5649
5513
5376
5240
5103
4967
4830
4694
4557
4421
4284
4148
4011
3875
3738
3602
3465
3329
3192
3056
2919
2783
2646
2512
2378
2245
2111
1977
1843
1709
1575
1441
1307
1173
1039
906
772
638
504
370
236
102
– 32
–166
–300
–433
1246
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN
Name
CAP2–
CAP2+
CAP2+
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
TEST1
TEST2
TEST3
TEST4
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
TEST5
TEST6
TEST7
TEST8
TEST9
(NC)
(NC)
COM15
COM15
COM14
COM14
COM13
COM13
Unit: µm
X
Y
–567
–701
–835
–969
–1103
–1237
–1371
–1505
–1639
–1772
–1906
–2040
–2174
–2308
–2442
–2576
–2710
–2844
–2978
–3111
–3245
–3379
–3513
–3647
–3781
–3915
–4049
–4185
–4322
–4458
–4595
–4731
–4868
–5004
–5141
–5277
–5414
–5550
–5687
–5836
–5956
–6076
–6195
–6474
1246
EPSON
1248
1163
1090
1017
945
872
799
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
PIN
Name
COM12
COM12
COM11
COM11
COM10
COM10
COM9
COM9
COM8
COM8
COM7
COM7
COM6
COM6
COM5
COM5
COM4
COM4
COM3
COM3
COM2
COM2
COM1
COM1
COM0
COM0
COMS
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
X
Y
–6474
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
– 1018
– 1090
– 1163
– 1248
–6232 – 1246
–6147
–6075
–6002
–5930
–5859
–5787
–5715
–5643
–5571
–5499
–5427
–5355
–5283
–5212
–5140
–5068
–4996
–4924
–4852
–4780
–4708
10–11
S1D15705 Series
Unit: µm
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
10–12
PIN
Name
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
X
Y
–4636 –1246
–4564
–4493
–4421
–4349
–4277
–4205
–4133
–4061
–3989
–3917
–3846
–3774
–3702
–3630
–3558
–3486
–3414
–3342
–3270
–3199
–3127
–3055
–2983
–2911
–2839
–2767
–2695
–2623
–2552
–2480
–2408
–2336
–2264
–2192
–2120
–2048
–1976
–1905
–1833
–1761
–1689
–1617
–1545
–1473
–1401
–1329
–1258
–1186
–1114
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
PIN
Name
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
X
Y
–1042 –1246
–970
–898
–826
–754
–682
–611
–539
–467
–395
–323
–251
–179
–107
–35
36
108
180
252
324
396
468
540
612
683
755
827
899
971
1043
1115
1187
1259
1330
1402
1474
1546
1618
1690
1762
1834
1906
1977
2049
2121
2193
2265
2337
2409
2481
EPSON
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
PIN
Name
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
(NC)
X
Y
2553 –1246
2625
2696
2768
2840
2912
2984
3056
3128
3200
3272
3343
3415
3487
3559
3631
3703
3775
3847
3919
3990
4062
4134
4206
4278
4350
4422
4494
4566
4637
4709
4781
4853
4925
4997
5069
5141
5213
5284
5356
5428
5500
5572
5644
5716
5788
5860
5931
6003
6075
Rev. 3.1a
S1D15705 Series
Unit: µm
PAD
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
PIN
X
Y
Name
(NC)
6147 –1246
(NC)
6232
↓
(NC)
6474 –1248
SEG168
–1163
SEG169
–1090
SEG170
–1018
SEG171
–945
SEG172
–872
SEG173
–800
SEG174
–727
SEG175
–654
SEG176
–581
SEG177
–509
SEG178
–436
SEG179
–363
SEG180
–291
SEG181
–218
SEG182
–145
SEG183
–73
SEG184
0
SEG185
73
SEG186
145
SEG187
218
SEG188
291
SEG189
363
SEG190
436
SEG191
509
SEG192
581
SEG193
654
SEG194
727
SEG195
799
SEG196
872
SEG197
945
SEG198
1017
SEG199
1090
COMS
1163
(NC)
1248
Rev. 3.1a
EPSON
10–13
S1D15705 Series
5. PIN DESCRIPTION
Power Supply Pin
Pin name
I/O
Description
Number of
pins
VDD
Power
supply
Commonly used with the MPU power supply pin VCC.
12
VSS
Power
supply
0 V pin connected to the system ground (GND).
9
VSS2
Power
supply
Boosting circuit reference power supply for liquid crystal drive.
5
VRS
Power
supply
External input pin for liquid crystal power supply voltage
adjusting circuit.
They are set to OPEN.
2
Power
supply
Multi-level power supply for liquid crystal drive. The voltage
specified according to liquid crystal cells is impedance-converted
by a split resistor or operation amplifier (OP amp) and applied.
The potential needs to be specified based on VDD to establish the
relationship of dimensions shown below:
V 1, V 2
V 3, V 4
V5
10
VDD (=V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master operation When the power supply is ON, the following
voltages are applied to V1 to V4 from the built-in power supply
circuit. The selection of the voltages is determined using the LCD
bias set command.
V1
V2
V3
V4
S1D15705*** S1D15707***, S1D15708***
1/9•V5
1/7•V5
1/6•V5
1/5•V5
2/9•V5
2/7•V5
2/6•V5
2/5•V5
7/9•V5
5/7•V5
4/6•V5
3/5•V5
8/9•V5
6/7•V5
5/6•V5
4/5•V5
LCD Power Supply Circuit Pin
Pin name
I/O
Description
Number of
pins
CAP1+
O
Boosting capacitor positive side connecting pin. Connects
a capacitor between the pin and CAP1– pin.
2
CAP1–
O
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP1+ pin.
2
CAP2+
O
Boosting capacitor positive side connecting pin. Connects
a capacitor between the pin and CAP2– pin.
2
CAP2–
O
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP2+ pin.
2
CAP3–
O
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP1+ pin.
2
VOUT
O
Boosting output pin. Connects a capacitor between the pin and VSS2.
2
VR
I
Voltage adjusting pin. Applies voltage between VDD and V5 using
a split resistor.
Valid only when the V5 voltage adjusting built-in resistor is not used
(IRS=LOW)
Do not use VR when the V5 voltage adjusting built-in resistor is
used (IRS=HIGH)
1
10–14
EPSON
Rev. 3.1a
S1D15705 Series
System Bus Connecting Pins
Pin name
I/O
D7 to D0
(SI)
(SCL)
I/O
A0
I
RES
I
CS1
CS2
RD
(E)
I
WR
(R/W)
I
FRS
O
C86
I
P/S
I
I
Number of
pins
Description
An 8-bit bidirectional data bus is used to connect an 8-bit or 16-bit
standard MPU data bus.
When the serial interface is selected (P/S=LOW),
D7: Serial data entry pin (SI)
D6: Serial clock input pin (SCL)
In this case, D0 to D5 are set to high impedance.
When Chip Select is in the non-active state, D0 to D7 are set to
high impedance.
Normally the lowest order bit of the MPU address bus is connected
to discriminate data / commands.
A0=HIGH: Indicates that D0 to D7 are display data.
A0=LOW: Indicates that D0 to D7 are control data.
Initialized by setting RES to LOW.
Reset operation is performed at the RES signal level.
Chip Select signal. When CS1=LOW and CS2=HIGH, this signal
becomes active and the input/output of data/commands is enabled.
• When the 80 series MPU is connected, active LOW is set.
Pin that connects the RD signal of the 80 series MPU. When this
signal is LOW, the S1D15705 series data bus is set in the output state.
• When the 68 series MPU is connected, active HIGH is set.
68 series MPU enable clock input pin
• When the 80 series MPU is connected, active LOW is set.
Pin that connects the WR signal of the 80 series MPU. The data
bus signal is latched on the leading edge of the WR signal.
• When the 68 series MPU is connected,
Read/write control signal input pin
R/W=HIGH: Read operation
R/W=LOW: Write operation
Output pin for static drive
Used together with the SYNC pin
MPU interface switching pin
C86=HIGH: 68 series MPU interface
C86=LOW: 80 series MPU interface
8
Switching pin for parallel data entry/serial data entry
P/S=HIGH: Parallel data entry
P/S=LOW: Serial data entry
According to the P/S state, the following table is given.
1
P/S
Data/
command
Data
Read/write
HIGH
A0
D0 to D7
RD, WR
LOW
A0
SI (D7)
Write-only
1
1
2
1
1
1
1
Serial clock
SCL (D6)
When P/S=LOW, D0 to D5 are set to high impedance. D0 to D5 can
be HIGH, LOW, or “OPEN”.
RD(E) and WR (R/W) are fixed to HIGH or LOW.
For the serial data entry, RAM display data cannot be read.
Rev. 3.1a
EPSON
10–15
S1D15705 Series
Pin name
I/O
CLS
I
M/S
I
Description
Pin that selects the validity/invalidity of the built-in oscillator circuit
for display clocks.
CLS=HIGH: Built-in oscillator circuit valid
CLS=LOW: Built-in oscillator circuit invalid (external input)
When CLS=LOW, display clocks are input from the CL pin.
When the S1D15705 series is used for the master/slave
configuration, each of the CLS pins is set to the same level together.
Display clock
Master
Slave
Built-in oscillator circuit used
HIGH
HIGH
External input
LOW
LOW
Pin that selects the master/slave operation for the S1D15705 series.
The liquid crystal display system is synchronized by outputting the
timing signal required for the liquid crystal display for the master
operation and inputting the timing signal required for the liquid
crystal display for the slave operation.
M/S=HIGH : Master operation
M/S=LOW : Slave operation
According to the M/S and CLS states, the following table is given.
M/S
CLS Oscillator Power supply CL
circuit
circuit
HIGH HIGH Valid
Valid
Output
LOW Invalid
Valid
Input
LOW HIGH Invalid
Invalid
Input
LOW Invalid
Invalid
Input
CL
I/O
FR
Output
Output
Input
Input
SYNC FRS
Output
Output
Input
Input
Output
Output
Output
Output
Number of
pins
1
1
DOF
Output
Output
Input
Input
Display clock I/O pin
According to the M/S and CLS states, the following table is given.
1
M/S CLS
CL
HIGH HIGH Output
LOW Input
LOW HIGH Input
LOW Input
FR
I/O
SYNC
I/O
DOF
I/O
IRS
I
HPM
I
10–16
When the S1D15705 series is used for the master/slave
configuration, each CL pin is connected.
Liquid crystal alternating current signal I/O pin
M/S=HIGH : Output
M/S=LOW : Input
When the SED15705 series is used for the master/slave
configuration, each FR pin is connected.
Liquid crystal synchronizing current signal I/O pin
M/S=HIGH : Output
M/S=LOW : Input
When the S1D15705 series is used for the master/slave
configuration, each SYNC pin is connected.
Liquid crystal display blanking control pin
M/S=HIGH : Output
M/S=LOW : Input
When the S1D15705 series is used for the master/slave
configuration, each DOF pin is connected.
V5 voltage adjusting resistor selection pin
IRS=HIGH: Built-in resistor used
IRS=LOW: Built-in resistor not used. The V5 voltage is adjusted
by the VR pin and stand-alone split resistor.
Valid only at master operation. The pin is fixed to HIGH or LOW at
slave operation.
Power supply control pin of the power supply circuit for liquid
crystal drive
HPM=HIGH : Normal mode
HPM=LOW : High power supply mode
Valid only at master operation. The pin is fixed to HIGH or LOW at
slave operation.
EPSON
1
2
1
1
1
Rev. 3.1a
S1D15705 Series
Liquid Crystal Drive Pin
Pin name
SEG0
to
SEGn
I/O
O
Number of
pins
Description
Output pins for the LCD segment drive.
For the pin assignment by model, refer to the table below.
Product name
SEG
S1D15705*****
SEG0 to SEG167
S1D15707***** /S1D15708***** SEG0 to SEG199
168 or 200
Number of pins
168
200
Contents of the display RAM and FR signal are combined to select
a desired level among VDD, V2, V3 and V5.
COM0
to
COMn
RAM data
FR
HIGH
HIGH
LOW
LOW
Power save
HIGH
LOW
HIGH
LOW
—
Output voltage
Display
Display reversal
normal operation
VDD
V2
V5
V3
V2
VDD
V3
V5
VDD
Output pins for the LCD common drive.
For the pin assignment by model, refer to the table below.
Product name
S1D15705*****
S1D15707*****
S1D15708*****
SEG
COM0 to COM63
COM0 to COM31
COM0 to COM15
64 or 32
or 16
Number of pins
64
32
16
Scan data and FR signal are combined to select a desired level
among VDD, V1, V4 and V5.
Scanning data
HIGH
HIGH
LOW
LOW
Power save
COMS
O
FR
HIGH
LOW
HIGH
LOW
—
Output voltage
V5
VDD
V1
V4
VDD
Indicator dedicated COM output pin. Set to OPEN when not used.
When COMS is used for the master/slave configuration, the same
signal is output to both the master and slave.
2
Test Pin
I/O
TEST1
to 6
I/O
IC chip test pin. Fix the pin to HIGH.
When using the temperature sensor with the S1D15705 *10 **, refer
to “Section 17. Temperature Sensor Circuit”.
6
TEST7
to 9
I/O
IC chip test pin. Take into consideration so that the capacity of
lines cannot be exhausted by setting the pin to OPEN.
3
Rev. 3.1a
Description
Number of
pins
Pin name
EPSON
10–17
S1D15705 Series
6. FUNCTION DESCRIPTION
MPU Interface
Selection of interface type
The S1D15705 series transfers data through 8-bit bidirectional data buses (D7 to D0) or serial data input (SI). By setting
the polarity of the P/S pin to either HIGH or LOW, the 8-bit parallel data entry or serial data entry can be selected as
listed in Table 1.
CS1
CS2
Table 1
A0
RD
HIGH: Parallel data entry
CS1
CS2
A0
LOW: Serial data entry
CS1
CS2
A0
—
—
—
SI
SCL
(HZ)
Fix — to HIGH or LOW. HZ indicates the high impedance state.
P/S
RD
WR
C86
D7
D6
D5 to D0
WR
C86
D7
D6
D5 to D0
Parallel interface
When the parallel interface is selected (P/S=HIGH), the S1D15705 series can directly be connected to the MPU bus
of either the 80 or 68 series MPU by setting the C86 pin to HIGH or LOW as listed in Table 2.
C86
CS1
Table 2
CS2
A0
H: 68 series MPU bus
CS1
CS2
L: 80 series MPU bus
CS1
CS2
RD
WR
D7 to D0
A0
E
R/W
D7 to D0
A0
RD
WR
D7 to D0
In addition, the data bus signal can be identified according to the combinations of the A0, RD (E), WR (R/W) signals
as listed in Table 3.
10–18
Table 3
80 series
Common
68 series
A0
R/W
RD
WR
1
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
EPSON
Function
Display data read
Display data write
Status read
Control data write (command)
Rev. 3.1a
S1D15705 Series
converted into 8-bit parallel data on the leading edge of
the 8th serial clock, then processed.
Whether to identify that the serial data entry is display
data or command is judged by the A0 input, and
A0=HIGH indicates display data and A0=LOW indicates
the command. After the chip is set to the non-active
state, the A0 input is read and identified at the timing on
the 8 × n-th leading edge of the serial clock. Fig. 1 shows
the signal chart of the serial interface.
Serial interface
When the serial interface is selected (P/S=LOW), the
serial data entry (SI) and serial clock input(SCL) can be
accepted with the chip in the non-active state (CS1=LOW
or CS2=HIGH. The serial interface consists of an 8-bit
shift register and a 3-bit counter. Serial data is fetched
from the serial data entry pin in the order of D7, D6, ....,
and D0 on the leading edge of the serial clock and
CS1
CS2
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
D5
D4
D3
D2
13
14
SCL
11
12
A0
Fig. 1
• When the chip is in the non-active state, both the shift register and counter are reset to the initial state.
• Cannot be read for the serial interface.
• For the SCL signal, pay careful attention to the terminating reflection of lines and external noise. The operation
confirmation using actual equipment is recommended.
Chip select
The S1D15705 series has two chip select pins CS1 and
CS2 and enables the MPU interface or serial interface
only when CS1=LOW and CS2=HIGH.
When Chip Select is in the non-active state, D0 to D7 are
in the high impedance state and the A0, RD, and WR
inputs become invalid. When the serial interface is
selected, the shift register and counter are reset.
Display data RAM and internal register
access
Since the S1D15705 series access viewed from the
MUP side satisfies the cycle time and does not require
the wait time, high-speed data transfer is enabled.
The S1D15705 series performs a kind of inter-LSI
pipeline processing through the bus holder attached to
the internal data bus when it performs the data transfer
with the MPU.
For example, when data is written on the display data
RAM, the data is first held in the bus holder and written
Rev. 3.1a
on the display data RAM up to the next data write cycle.
Further, when the MPU reads the contents of display
data RAM, the read data at the first data read cycle
(dummy) is held in the bus holder and read on the system
bus from the bus holder up to the next data read cycle.
The read sequence of the display data RAM is restricted.
When the address is set, note that the specified address
data is not output to the subsequent read instruction and
output at the second data read. Therefore single dummy
read is required after the address set and write cycle.
Fig. 2 shows this relationship.
Busy flag
When the busy flag is “1”, it indicates that the S1D15705
series is performing an internal operation, and only the
status read instruction can be accepted. The busy flag is
output to the D7 pin using the status read command. If
the cycle time (tCYC) is ensured, the MPU throughput
can be improved greatly since this flag needs not be
checked before each command.
EPSON
10–19
S1D15705 Series
Internal timing
MPU
• Write
WR
DATA
N
N+1
N+2
N+3
Latch
N+1
N
BUS Holder
N+2
N+3
Write Signal
• Read
MPU
WR
RD
Internal timing
DATA
N
N
n
n+1
Address Preset
Read Signal
Column Address
Preset N
Bus Holder
Increment N+1
N
Address Set
#n
n
Dummy
Read
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
Fig. 2
10–20
EPSON
Rev. 3.1a
S1D15705 Series
display configuration with the high degree of freedom
can easily be obtained when the S1D15705 series is
used for the multiple chip configuration.
Besides, the read/write operation to the display data
RAM is performed through the I/O buffer from the
MPU side independently of the liquid crystal drive
signal read. Therefore even when the display data RAM
is asynchronously accessed during liquid crystal display,
the access will not have any adverse effect on the
display such as flickering.
Display Data RAM
Display data RAM
This display data RAM stores display dot data and
consists of 65 (8 pages × one 8 bit + 1) × 200 bits.
Desired bits can be accessed by specifying page and
column addresses.
Since the MPU display data D7 to D0 correspond to the
common direction of the liquid crystal display, the
restrictions at display data transfer is reduced and the
D0
0 1 1 1
0
COM0
D1
1 0 0 0
0
COM1
D2
0 0 0 0
0
COM2
D3
0 1 1 1
0
COM3
D4
1 0 0 0
0
COM4
—
—
Display data RAM
Liquid crystal display
Fig. 3
Page address circuit
As shown in Fig. 4, the page address of the display data
RAM is specified using the page address set command.
To access the data using a new page, the page address is
respecified.
The page address 8 (D3,D2,D1,D0=1,0,0,0) is an
indicator dedicated RAM area and only the display data
D0 is valid.
Column address circuit
As shown in Fig. 4, an address on the column side of the
display data RAM is specified using the column address
set command. Since the specified address is incremented
by 1 whenever the display data read/write command is
input, the MPU can successively access the display
data.
Besides, the column address stops the increment at the
column C7H. Since the column and page addresses are
independent each other, for example, the page and
column addresses need to be respecified respectively to
move from the column C7H of page 0 and column 00H.
Further, as shown in Fig. 4, the correspondence
relationship between the column address of the display
data RAM and the segment address can be reversed
using the ADC command (segment driver direction
select command). Therefore the IC assignment
restrictions at LCD module assembly are reduced.
Table 4
S1D15705*****
S1D15707***** / S1D15708*****
SEG output
SEG0
SEG167
ADC
“0”
0 (H)→ Column Address→ A7 (H)
(D0)
“1”
C7 (H)←Column Address← 20 (H)
Line address circuit
When displaying contents of the display data RAM, the
line address circuit is used for specifying the
corresponding addresses. See Figure 4. Using the
display start line address set command, the top line is
normally selected (when the common output state is
normal, COM0 is output. And, when reversed, the
S1D15705***** outputs COM63, S1D15707*****
outputs COM31 and S1D15708 ***** outputs
Rev. 3.1a
SEG0
SEG199
0 (H)→ Column Address→ C7 (H)
C7 (H)←Column Address ← 0 (H)
COM15). For the S1D15705*****, the display area
of 65 lines is secured starting from the specified display
start line address in the address incrementing direction.
And, 33 lines are provided for the S1D15707*****,
17 lines are provided for the S1D15708*****.
Dynamically changing the line address using the display
start line address set command enables screen scrolling
and page change.
EPSON
10–21
S1D15705 Series
0
0
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
27
26
25
24
23
22
21
20
C7
C6
C5
C4
C3
C2
C1
C0
00
01
02
03
04
05
06
07
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
63 lines
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Start
1 0
D0 D0
ADC
Column
Address
0
*****
Line
output state:
: When setting the display start line to one channel Address Normal rotation
LCD
Out
0
Common
Data S1D15705
A0
A1
A2
A3
A4
A5
A6
A7
Page Address
D3
D2
D1
D0
COM
Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
The 65th line
is accessed
independently
of the display
start line address.
Fig. 4
10–22
EPSON
Rev. 3.1a
S1D15705 Series
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
C7
C6
C5
C4
C3
C2
C1
C0
00
01
02
03
04
05
06
07
0
Page 1
Start Start
COM
Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COMS
16 lines
0
Page 0
32 lines
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1 0
D0 D0
ADC
Column
Address
0
Line
output state:
Address Normal rotation
LCD
Out
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
C0
C1
C2
C3
C4
C5
C6
C7
0
S1D15707*****, S1D15708*****:
When setting the display start line to one channel
07
06
05
04
03
02
01
00
0
Common
Data
SEG192
SEG193
SEG194
SEG195
SEG196
SEG197
SEG198
SEG199
Page Address
D3
D2
D1
D0
The 33rd of
S1D15707
and the 17th
S1D15708
are accessed
independ-ently of the
display start line
address.
*****
*****
Fig. 4-2
Rev. 3.1a
EPSON
10–23
S1D15705 Series
Display data latch circuit
The display data latch circuit is a latch that temporarily
stores the display data output from the display data
RAM to the liquid crystal drive circuit.
Since the Display Normal Rotation/Reversal, Display
ON/OFF, and Display All Lighting ON/OFF commands
control the data in this latch, the data within the display
data RAM is not changed.
even when the display data RAM is asynchronously
accessed during liquid crystal display, the access will
not have any adverse effect on the display such as
flickering.
The circuit also generates the internal common timing,
liquid crystal alternating current signal (FR), and
synchronous signal (SYNC) from the display clocks.
As shown in Fig. 5, the FR normally generates the drive
waveforms in the 2-frame alternating current drive
system to the liquid crystal drive circuit. It can generate
n-line reversal alternating current drive waveforms by
setting data (n-1) to the n-line reversal drive register. If
a display quality problem such as crosstalk occurs, it
can be improved by using the n-line reversal alternating
current drive waveforms. Determine the number of
lines (n) to which alternating current is applied by
actually displaying the liquid crystal.
SNYC is a signal that synchronizes the line counter and
common timing generator circuit to the SYNC signal
output side IC. Therefore the SYNC signal becomes a
waveform at a duty ratio of 50% that synchronizes to the
frame synchronization.
When the S1D15705 series is used for the multiple chip
configuration, the slave side needs to supply the display
timing signals (FR, SYNC, CL, and DOF) from the
master side.
Table 5 shows the state of FR, SYNC, CL, or DOF.
Oscillator Circuit
This oscillator circuit is a CR type oscillator and generates
display clocks. The oscillator circuit is valid only when
M/S=HIGH and CLS=HIGH and starts oscillation after
the Built-in Oscillator Circuit ON command is entered.
When CLS=LOW, the oscillation is stopped and the
display clocks are entered from the CL pin.
Display Timing Generator Circuit
This display timing generator circuit generates timing
signals from the display clocks to the line address circuit
and the display latch circuit. It latches the display data
to the display data latch circuit and outputs it to the
segment drive output pin by synchronizing to the display
clocks. The read operation of display data to the liquid
crystal drive circuit is completely independent of the
access to the display data RAM from the MPU. Therefore
Table 5
Operation mode
FR
Master (M/S=HIGH) Built-in oscillator circuit valid (CLS=HIGH) Output
Built-in oscillator circuit invalid (CLS=LOW) Output
Slave (M/S=LOW) Built-in oscillator circuit valid (CLS=HIGH) Input
Built-in oscillator circuit invalid (CLS=LOW) Input
SYNC
Output
Output
Input
Input
CL
Output
Input
Input
Input
DOF
Output
Output
Input
Input
2-frame alternating current drive waveforms
64 65 1
2
3
4
5
6
60 61 62 63 64 65 1
2
3
4
5
6
CL
FR
SYNC
VDD
V1
COM0
V4
V5
VDD
V1
COM1
V4
V5
RAM
DATA
VDD
V2
SEGn
V3
V5
Fig. 5
10–24
EPSON
Rev. 3.1a
S1D15705 Series
n-line reversal alternating current drive waveforms (Example of n=5: when the line reversal
register is set to 4)
64 65 1
2
3
4
5
6
60 61 62 63 64 65 1
2
3
4
5
6
CL
FR
SYNC
VDD
V1
COM0
V4
V5
VDD
V1
COM1
V4
V5
RAM
DATA
VDD
V2
SEGn
V3
V5
Fig. 6
Common Output State Selection Circuit
The S1D15705 series can set the scanning direction of the COM output using the common output state selection
command (see Fig. 6). Therefore the IC assignment restrictions at LCD module assembly are reduced.
Table 6
State
COM scanning direction
S1D15705*****
S1D15707*****
S1D15708*****
Normal rotation
COM 0
→
COM 63
COM 0
→
COM 31
COM 0
→
COM 15
Reversal
COM 63
→
COM 0
COM 31
→
COM 0
COM 15
→
COM 0
Liquid Crystal Drive Circuit
These are a 233-channel (S1D15705***** and S1D15707*****), a 217-channel (S1D15708*****) multiplexers
that generate four voltage levels for liquid crystal drive. It outputs the liquid crystal drive voltage that corresponds to
the combinations of the display data, COM scanning signal, and FR signal.
Fig. 7 shows examples of the SEG and COM output waveforms.
Rev. 3.1a
EPSON
10–25
S1D15705 Series
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
FR
VDD
VSS
COM0
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
COM1
COM2
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
SEG0
SEG1
SEG2
COM0–SEG0
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
COM0–SEG1
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
Fig. 7
10–26
EPSON
Rev. 3.1a
S1D15705 Series
Power Supply Circuit
This power supply circuit is a low power supply
consumption one that generates the voltage required for
the liquid crystal drive and consists of a boosting circuit,
voltage adjusting circuit, and voltage follower circuit. It
is valid only at master operation.
The power supply circuit ON/OFF controls the boosting
circuit, voltage adjusting circuit, and voltage follower
circuit using the power supply control set command,
respectively.
Therefore, it can also use the partial functions of the
external power supply and built-in power supply
together. Table 7 lists the functions that control 3-bit
data using the power control set command and Table 8
lists the reference combinations.
Table 7 Description of controlling bits using the power control set command
State
Item
“1”
“0”
D2 Boosting circuit control bit
ON
OFF
D1 Voltage adjusting circuit (V adjusting circuit) control bit
ON
OFF
D0 Voltage follower circuit (V/F circuit) control bit
ON
OFF
Table 8 Reference combinations
Boosting V adjusting V/F
External
Boosting
D1
D0
circuit
circuit
circuit voltage input system pin
Status of use
D2
1
Built-in power
supply used
1
1
1
O
O
O
VSS2
Used
2
V adjusting circuit
and V/F circuit only
0
1
1
X
O
O
VOUT, VSS2
OPEN
3
V/F circuit only
0
0
1
X
X
O
V5, VSS2
OPEN
External power
0
0
0
X
X
X
V1 to V5
OPEN
supply only
• The boosting system pin indicates the CAP1+, CAP1–, CAP2+, CAP2–, or CAP3– pin.
• Although the combinations other than those listed in the above table are also possible, they cannot be recommended
because they are not actual use methods.
4
Boosting circuit
The boosting circuit incorporated in the S1D15705
series enables the quadruple boosting, triple boosting,
and double boosting of the V DD – VSS2 potential.
For the quadruple boosting, the VDD ↔ VSS2 potential
is quadruple-boosted to the negative side and output to
the V OUT pin by connecting the capacitor C1 between
CAP1+↔and CAP1–, between CAP2+↔ and CAP2–,
between CAP1+↔ and CAP3–, and between VSS2↔
and VOUT.
For the triple boosting, the VDD ↔ V SS2 potential is
Rev. 3.1a
triple-boosted to the negative side and output to the
V OUT pin by connecting the capacitor C1 between
CAP1+↔ and CAP1–, between CAP2+↔ and CAP2–,
and between VSS2 ↔ and V OUT and strapping both
CAP3– and VOUT pins.
For the double boosting, the V DD ↔ VSS2 potential is
doubly boosted to the negative side and output to the
V OUT pin by connecting the capacitor C1 between
CAP1+↔ and CAP1–, and between VSS2↔, setting
CAP2+ to OPEN, and V OUT and strapping CAP2–,
CAP3–, and VOUT pins.
Fig. 8 shows the relationships of boosting potential.
EPSON
10–27
S1D15705 Series
VSS2
+
+
CAP1+
C1
CAP1—
C1
VOUT
CAP3—
CAP1+
+
C1
CAP1—
CAP2—
C1
VOUT
S1D15705 Series
CAP3—
C1
S1D15705 Series
VOUT
VSS2
+
C1
CAP3—
CAP1+
+
C1
CAP1—
CAP2—
S1D15705 Series
VSS2
+
C1
CAP2—
C1
+
CAP2+
Quadruple boosting circuit
+
CAP2+
OPEN CAP2+
Triple boosting circuit
VDD = 0V
VDD = 0V
VSS2 = –3V
VSS2 = –3V
Double boosting circuit
VDD = 0V
VSS2 = –5V
VOUT = 3 x VSS2 = –9V
VOUT = 2 x VSS2 = –10V
VOUT = 4 x VSS2 = –12V
Quadruple boosting
potential relationship
Triple boosting
potential relationship
Double boosting
potential relationship
Fig. 8
• Set the V SS2 ” voltage range so that the voltage of the VOUT pin cannot exceed the absolute maximum ratings.
Voltage adjusting circuit
The boosting voltage generated in VOUT outputs the
liquid crystal drive voltage V5 through the voltage
adjusting circuit.
Since the S1D15705 series incorporates a high-accuracy
constant power supply, 64-step electronic control
function, and V5 voltage adjusting resistor, a highaccuracy voltage adjusting circuit can eliminate and
save parts.
(A) When using the V5 voltage adjusting built-in resistor
The liquid crystal power supply voltage V5 can be
controlled only using the command without an
external resistor and the light and shade of liquid
crystal display be adjusted by using the V5 voltage
adjusting built-in resistor and the electronic control
function.
The V 5 voltage can be obtained according to
Expression A-1 within the range of |V5 |<|VOUT|.
Rb 

V5 = 1 +
⋅ VEV

Ra 
α 
Rb  

= 1+
⋅ 1–
⋅ VREG

Ra   162 
(Expression A-1)
[Q V = (1 − α 162) ⋅ V ]
+
10–28
EPSON
EV
REG
Rev. 3.1a
S1D15705 Series
VDD
VEV (Constant voltage source
+ electronic control)
Built-in Ra
+
V5
–
Built-in Rb
Fig. 9
VREG is a constant voltage source within an IC, and the
value at Ta=25°C is constant as listed in Table 9.
Device
Internal
power supply
Table 9
Temperature Unit
gradient
–0.05
[%/°C]
VREG
Unit
–2.1
[V]
Table 10
D2
D1
D0
α
0
0
63
0
0
1
62
0
1
0
61
··
·
D5
D4
D3
0
0
0
0
0
0
0
0
0
0
··
·
α indicates an electronic control command value. Setting
data in a 6-bit electronic control register enters one state
among 64 states. Table 10 lists the values of α based on
the setup of the electronic control register.
1
1
1
1
0
1
2
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Rb/Ra indicates the V 5 voltage adjusting built-in
resistance ratio and can be adjusted into eight steps
using the V5 voltage adjusting built-in resistance ratio
set command. The reference values of the (1+Rb/Ra)
ratio are obtained as listed in Table 11 by setting 3-bit
data in the V5 voltage adjusting built-in resistance ratio
register.
Table 11 (Reference values)
S1D15705*****
S1D15707***** / S1D15708*****
Register
Device per temperature
gradient [Unit: %/°C]
Device per temperature
gradient [Unit: %/°C]
D2
D1
D0
–0.05
–0.05
0
0
0
4.5
3.0
0
0
1
5.0
3.5
0
1
0
5.5
4.0
0
1
1
6.0
4.5
1
0
0
6.5
5.0
1
0
1
7.0
5.5
1
1
0
7.6
6.0
1
1
1
8.1
6.5
It is necessary to take a manufacturing deviation of upto ±7% of the built-in resistance ratio into consideration. When
this is not permissible, supplement external Ra and Rb to ajdust the V 5 voltage.
Figs. 10 show the V 5 voltage reference values per temperature gradient device based on the values of the V5 voltage
adjusting built-in resistance ratio register and electronic control register at Ta=25°C.
Rev. 3.1a
EPSON
10–29
S1D15705 Series
–18
–17
S1D15705*****
–16
1 1 1
–15
1 1 0
–14
1 0 1
–13
1 0 0
–12
0 1 1
–11
0 1 0
–10
0 0 1
V5 [v]
–9
0 0 0
–8
–7
–6
–5
V5 voltage adjusting
built-in resistance
ratio registers
(D2, D1, and D0)
–4
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Fig. 10-1 S1D15705***** Temperature gradient = –0.05%/°C device
V5 voltage based on the values of V5 voltage adjusting built-in resistance ratio register and electronic
control register
–18
–17
–16
S1D15707*****, S1D15708*****
V5 [v]
–15
–14
1 1 1
–13
1 1 0
–12
1 0 1
–11
1 0 0
–10
0 1 1
–9
0 1 0
–8
0 0 1
–7
0 0 0
–6
–5
V5 voltage adjusting
built-in resistance
ratio registers
(D2, D1, and D0)
–4
–3
–2
–1
Electric Volume
Resister
3FH
30H
18H
00H
0
Fig. 10-2 S1D15707*****, S1D15708***** Temperature gradient = –0.05%/°C device
V5 voltage based on the values of V5 voltage adjusting built-in resistance ratio register and electronic
control register
*S1D15708 should be used in system operating voltage ranges. (V5–VDD = –10V or V5–VDD=less than –
10V)
10–30
EPSON
Rev. 3.1a
S1D15705 Series
<Setting example: S1D15705***** When setting V5 = –9 V at Ta=25°C>
From Fig. 8 and Expression A-1.
Table 12
Register
Description
D5
D4
D3
D2
D1
D0
V5 voltage adjusting
–
–
–
0
1
0
electronic control
0
1
1
0
0
1
In this case, Table 13 lists the V5 voltage variable range and pitch width using the electronic control function.
Table 13
Typ.
Min.
V5
Variable range
–11.6
to
–9.3
Pitch width
to
Max.
Unit
–7.1
[V]
67
[mV]
The V5 voltage can be obtained from Expression B1 by setting the external resistors Ra’ and Rb’
within the range of |V5| < |VOUT|.
(B) When using the external resistor (not using the V 5
voltage adjusting built-in resistor) 1
The liquid crystal power supply voltage V 5 can
also be set by adding the resistors (Ra’ and Rb’)
between V DD and V R and between V R and V 5
without the V5 voltage adjusting built-in resistor
(IRS pin=LOW). Also in this case, the liquid crystal
power supply voltage V5 can be controlled using
the command and the light and shade of liquid
crystal display can be adjusted by using the
electronic control function.
Rb' 

V5 = 1 +
⋅ VEV

Ra' 
α 
Rb'  

= 1+
⋅ 1–
⋅ VREG

Ra'   162 
(Expression B-1)
[Q V = (1 − α 162) ⋅ V ]
EV
REG
+
VDD
VEV (Constant voltage source
+ electronic control)
Stand-alone Ra'
+
V5
–
VR
Stand-alone Rb
Fig. 11
<Setting example: S1D15705***** When setting V5=–7 V at Ta=25°C>
Set the value of the electronic control register as the
intermediate value (D5, D4, D3, D2, D1, D0) =
(1,0,0,0,0,0). From the foregoing we can establish the
expression:
Also, suppose the current applied to Ra’ and Rb’ is 5µA.
(Expression B-2)
Ra' + Rb' = 1.4 MΩ
It follows that
Therefore from Expressions B-2 and B-3, we have
α = 31
VREG = –2.1V
From Expression B-1, it follows that
Rb'  
α 
V5 = 1 +
⋅ 1−
⋅ VREG (Expression B-2)



Ra'
162 
Rb'  
31 
−7V = 1 +
⋅ 1−
⋅ ( −2.1)

Ra'   162 
Rev. 3.1a
Rb'
= 3.12
Ra'
Ra' = 340 kΩ
Rb' = 1060 kΩ
In this case, Table 14 lists the V5 voltage variable range
and pitch width using the electronic control function.
EPSON
10–31
S1D15705 Series
V5
Min.
Variable range
–8.6
Table 14
Typ.
to
–7.0
Pitch width
to
Max.
Unit
–5.3
[V]
52
[mV]
The V5 voltage can be obtained from the following
expression C-1 by setting the external resistors R1 ,
R2 (variable resistors), and R3 within the range of
|V 5| < |VOUT| and finely adjusting R2 (∆R2).
(C) When using the external resistor (not using the V5
voltage adjusting built-in resistor) 2
In the use of the above-mentioned external resistor,
the liquid crystal power supply voltage V5 can also
be set by adding the resistors to finely adjust Ra’
and Rb’. Also in this case, the liquid crystal power
supply voltage V5 can be controlled using the
command and the light and shade of liquid crystal
display can be adjusted by using the electronic
control function.

R + R2 − ∆R2 
⋅ VEV
V5 = 1 + 3
R1 + ∆R2 


R + R2 − ∆R2  
α 
⋅ 1–
⋅ VREG
= 1 + 3
R1 + ∆R2   162 

[Q V = (1 − α 162) ⋅ V ]
EV
REG
(Expression C-1)
+
VDD
VEV (Constant voltage source
+ electronic control)
Ra' Stand-alone R1
+
Stand-alone R2
V5
∆R2
–
VR
Rb' Stand-alone R3
Fig. 12
<Setting example: S1D15705***** When setting V5=–5 to –9 V at Ta=25°C>
Set the value of the electronic control register as the
intermediate value (D5, D4, D3, D2, D1, D0) =
(1,0,0,0,0,0). From the foregoing we can establish the
expression:
α = 31
VREG = −2.1V
When ∆R2=R2, to obtain V5=-5V, it follows that

R3  
31 
−5V = 1 +
⋅ 1−
⋅ ( −2.1)
R1 + R2  
162 

(Expression C-3)
When ∆R2=0Ω, to obtain V5=–9 V from Expression C1, it follows that
Also, suppose the current applied between VDD and V5
is 5µA.
R1 + R2 + R3 = 1.4 MΩ
(Expression C-4)
It follows that
Therefore from Expressions C-2, C-3, and C-4, we have

R + R2  
31 
−9V = 1 + 3
⋅ 1−
⋅ ( −2.1)
R1  
162 

(Expression C-2)
R1 = 264 kΩ
R2 = 211kΩ
R3 = 925kΩ
10–32
EPSON
Rev. 3.1a
S1D15705 Series
In this case, Table 6-15 lists the V5 voltage variable range and pitch width using the electronic control function.
V5
Min.
Variable range
–8.7
Table 15
Typ.
to
–7.0
Pitch width
to
53
Max.
Unit
–5.3
[V]
[mV]
• When using the V5 voltage adjusting built-in resistor or electronic control function, the state where at least the voltage
adjusting circuit and voltage follower circuit are operated together needs to be set using the power control set
command. Also when the boosting circuit is OFF, the voltage needs to be applied from VOUT.
• The VR pin is valid only when the V5 voltage adjusting built-in resistor (IRS pin=LOW). Set the VR pin to OPEN
when using the V5 voltage adjusting built-in resistor (IRS pin=HIGH).
• Since the VR pin has high input impedance, noise must be taken into consideration such as for short and shielded lines.
may be deteriorated in large load liquid crystal or
panels. In this case, the display quality can be improved
by setting HPM pin=LOW (high power mode). Whether
to use the power supply circuit in this mode should need
the display confirmation by actual equipment.
Besides, if the improvement is insufficient even for the
high power mode setting, the crystal liquid drive power
needs to be supplied externally.
Liquid crystal voltage generator circuit
The V5 voltage is resistor-split within an IC and generates
the V1, V2, V3, and V 4 potentials required for the liquid
crystal drive.
Further, the V1, V2, V3, and V4 potentials are impedanceconverted by the voltage follower and supplied to the
liquid crystal drive circuit.
Using the bias set command allows you to select a
d esired b ias ratio from 1/9 or 1/7 for t he
S1D15705***** and 1/6 or 1/5 for the S1D15707*****
and S1D15708***** .
Command sequence when the built-in power
supply is turned off
To turn off the built-in power supply, set it in the power
save state and then turn off the power supply according
to the command sequence shown in Fig. 13 (procedure).
High power mode
The power supply circuit incorporated in the S1D15705
series has the ultra-low power consumption (normal
mode: HPM=HIGH). Therefore the display quality
Procedure
Description
(Command, state)
Step1
Power save
Step2
Turning off the built
Command address
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
0
0
0
Power save command
1
-in power supply
(Both stand-by and
sleep can be useal)
Fig. 13
Rev. 3.1a
EPSON
10–33
S1D15705 Series
Reference circuit examples
1 Built-in power supply used
(1) When using the V5 voltage adjusting built-in resistor
(Example of VSS2=VSS, quadruple boosting)
(2) When not using the V5 voltage adjusting built-in resistor
(Example of VSS2=VSS, quadruple boosting)
VDD
C1
VSS
C1
C1
C1
VDD
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VDD
C2
C2
C2
C2
C2
V1
M/S
IRS
C1
VSS
C1
C1
S1D15705 Series
IRS
C1
R3
R2
VDD
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
R1
VDD
C2
C2
V2
V1
M/S
S1D15705 Series
VDD
V2
V3
C2
V3
V4
C2
V4
V5
C2
V5
2 Only the voltage adjusting circuit and V/F circuit used
(1) When using the V5 voltage adjusting built-in resistor
(2) When not using the V5 voltage adjusting built-in resistor
VDD
VSS
External
Power
Supply
VDD
VSS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
V5
VR
VDD
C2
C2
C2
C2
C2
10–34
V1
M/S
IRS
VSS
External
Power
Supply
S1D15705 Series
IRS
R3
R2
VDD
VSS
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
R1
VDD
C2
C2
V2
V1
V2
V3
C2
V3
V4
C2
V4
V5
C2
V5
EPSON
M/S
S1D15705 Series
VDD
Rev. 3.1a
S1D15705 Series
3 Only the V/F circuit used
4 Only the external power supply used
Depending on all external power supplies
VDD
VSS
External
Power
Supply
VDD
VDD
C2
C2
V1
VSS
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VDD
VDD
V1
V2
C2
V3
C2
V4
C2
V5
M/S
External
Power
Supply
S1D15705 Series
VSS
VSS
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
IRS
M/S
S1D15705 Series
IRS
VDD
V2
V3
V4
V5
Common reference setting example
At V5 =–8 to –12 V variable
Item
C1
C2
Setting value
1.0 to 4.7
0.01 to 1.0
Unit
µF
µF
Fig. 14
*1 Since the VR pin has high input impedance, it uses short and shielded wires.
*2 C1 and C2 are determined according to the size of the LCD panel. Set a value so that the liquid crystal drive voltage
can be stable.
[Setting example] • Turn on the V adjusting circuit and the V/F circuit and apply external voltage.
• Display LCD heavy load patterns like lateral stripes and determine C2 so that the liquid crystal
drive voltages (V1 to V5) can be stable.
• Then turn on all built-in power supplies and determine C1.
*3 Capacity is connected in order to stabilize voltage between VDD and VSS power supplies.
Rev. 3.1a
EPSON
10–35
S1D15705 Series
*4 When the built-in V/F circuit is used to drive an LCD panel with heavy alternating or direct current load, we
recommend that external resistance be connected in order to stabilize V/F outputs, or electric potentials, V1, V 2,
V3 and V4 .
VDD
C2
Adjust resistance value R 4 to the optimal level by
checking driving waveform displayed on the LCD.
V1
Reference setting: R4 = 0.1 to 1.0 [MΩ]
R4
V2
C2
V3
C2
S1D15705 Series
R4
VDD
V4
C2
R4 R4
C2
V5
Fig. 15
*5 Precautions when installing the COG
When installing the COG, it is necessary to duly consider
the fact that there exists a resistance of the ITO wiring
occurring between the driver chip and the externally
connected parts (such as capacitors and resistors). By the
influence of this resistance, non-conformity may occur
with the indications on the liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the driver
chip pin to the externally connected parts as much as
possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
Also, as for this driver IC, pay sufficient attention to the
following points when connecting to external parts for
the characteristics of the circuit.
1. Connection to the boosting capacitors The boosting
capacitors (the capacitors connecting to respective
CAP pins and capacitor being inserted between
VOUT and VSS2) of this IC are being switched over
by use of the transistor with very low ON-resistance
of about 10Ω. However, when installing the COG,
10–36
2.
the resistance of ITO wiring is being inserted in
series with the switching transistor, thus dominating
the boosting ability.
Consequently, the boosting ability will be hindered
as a result and pay sufficient attention to the wiring
to respective boosting capacitors.
Connection of the smoothing capacitors for the
liquid crystal drive
The smoothing capacitors for the liquid crystal
driving potentials (V 1 . V 2 , V 3 and V 4) are
indispensable for liquid crystal drives not only for
the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs
pursuant to installation of the COG is supplemented
to these smoothing capacitors, the liquid crystal
driving potentials become unstable to cause nonconformity with the indications of the liquid crystal
display. Therefore, when using the COG module,
we definitely recommend to connect reinforcing
resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these
reinforcing resistors, current consumption will
increase.
Indicated below is an exemplary connection diagram of
external resistors.
Please make sufficient evaluation work for the display
statuses with any connection tests.
EPSON
Rev. 3.1a
S1D15705 Series
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
VDD
VDD
R4
V1
V2
C2
V3
C2
V1
C2
R4
S1D15705 Series
C2
V2
C2
V3
C2
S1D15705 Series
R4
VDD
R4
V4
C2
C2
V4
R4 R4
C2
V5
C2
Reset Circuit
When the RES input is set to the LOW level, this LSI
enters each of the initial setting states
1. Display OFF
2. Display Normal Rotation
3. ADC Select: Normal rotation (ADC command
D0=0)
4. Power Control Register: (D2,D1,D0)=(0,0,0)
5. Register Data Clear within Serial Interface
6. LCD Power Supply Bias Ratio:
S1D15705: 1/9 bias
S1D15707/S1D15708: 1/6 bias
7. n-Line Alternating Current Reversal Drive Reset
8. Sleeve mode cancel (standby mode is not canceled)
9. Display All Lighting OFF: (Display All Lighting
ON/OFF command D0=LOW)
10. Built-in Oscillator Circuit stopped
11. Static Indicator OFF
Static Indicator Register: (D1,D2)=(0,0)
12. Read Modify Write OFF
13. Display start line set to the first line
14. Column address set to address 0
15. Page address set to page 0
16. Common Output State Normal rotation
17. V5 Voltage Adjusting Built-in Resistance Ratio
Register: (D2,D1,D0)=(0,0,0)
18. Electronic Control Register Set Mode Reset
Electronic Control Register* (D5, D4, D3, D2,
D1, D0) = (1,0,0,0,0,0)
19. n-Line Alternating Current Reversal Register: (D3,
D2, D1, D0) = (0, 0, 0, 0)
20. Test Mode Reset
Rev. 3.1a
V5
On the other hand, when using the reset command, only
the items 11 to 20 of the above-mentioned initial setting
are executed.
When the power is turned on, the initialization using the
RES pin is required. After the initialization using the
RES pin, each input pin needs to be controlled normally.
Besides, when the MPU control signal has high
impedance, overcurrent may be applied to an IC. After
turning on the power, take action so that the input pin
cannot have high impedance.
The S1D15705 Series discharge electric charges of V5
and VOUT at RES pin is set to the LOW level. If external
power supplies for driving LCD are used, do not input
external power while the RES pin is set to the LOW
level to prevent short-circuiting between the external
power supplies and VDD.
EPSON
10–37
S1D15705 Series
7. COMMAND
The S1D15705 series identifies data bus signals according to the combinations of A0, RD(E), and WR(R/W). Since the
interpretation and execution of commands are performed only by the internal timing independently of external clocks,
the S1D15705 performs high-speed processing that does not require busy check normally.
The 80 series MPU interface starts commands by inputting low pulses to the RD pin at read and to the WR pin at write
operation. The 68 series MPU interface enters the read state when HIGH is input to the R/W pin. It enters the write state
when LOW is input to the same pin. It starts commands by inputting high pulses to the E pin (for the timing, see the
Timing Characteristics of Chapter 10). Therefore the 68 series MPU interface differs from the 80 series MPU interface
in that RD(E) is set to “1 (H)” at status read and display data read in the Command Description and Command Table.
The command description is given below by taking the 80 series MPU interface as an example.
When selecting the serial interface, enter sequential data from D7.
Command description
(1) Display ON/OFF
This command specifies display ON/OFF.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
1
1
Setting
1
Display ON
0
Display OFF
For display OFF, the segment and common drivers output the VDD level.
(2) Display Start Line Set
This command specifies the display start line address of the display data RAM shown in Fig. 4. The display area is
displayed for 65 lines for the S1D15705*****, 33 lines for the S1D15707***** and 17 lines for the S1D15708*****
from the specified line address to the line address increment direction. When this command is used to dynamically
change the line address, the vertical smooth scroll and page change are enabled. For details, see the Line address circuit
of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
↓
10–38
Line address
↓
1
1
1
1
1
0
62
1
1
1
1
1
1
63
EPSON
Rev. 3.1a
S1D15705 Series
(3) Page Address Set
This command specifies the page address that corresponds to the low address when accessing the display data RAM
shown in Fig. 4 from the MPU side. The display data RAM can access desired bits when the page address and column
address are specified. Even when the page address is changed, the display state will not be changed. For details, see the
Page address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
1
Page address
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
↓
↓
0
1
1
1
7
1
0
0
0
8
(4) Column Address Set
This command specifies the column address of the display data RAM shown in Fig. 4. The column address is set
(basically successively) by dividing it into high-order four bits and low-order four bits. Since the column address is
automatically incremented by 1 whenever the display data RAM is accessed. The MPU can successively read/write the
display data. The column address stops the increment at C7H. In this case, the page address is not changed successively.
For details, see the Column address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
High-order bit →
0
1
0
0
0
0
Low-order bit →
1
A7
A6
A5 A4
0
A3
A2
A1 A0
A7 A6 A5 A4 A3 A2 A1 A0 Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
↓
↓
1
0
1
0
0
1
1
0
166
1
0
1
0
0
1
1
1
167
↓
Rev. 3.1a
↓
1
1
0
0
0
1
1
0
198
1
1
0
0
0
1
1
1
199
EPSON
10–39
S1D15705 Series
(5) Status Read
E R/W
A0 RD WR
0
0
BUSY
ADC
ON/OFF
RESET
1
D7
D6
D5
D4
D3 D2 D1 D0
BUSY ADC ON/OFF RESET
0
0
0
0
When BUSY=1, indicates an internal operation being done or reset.
The command cannot be accepted until BUSY=0 is reached. However, if the cycle time is
satisfied, the command needs not be checked.
Indicates the correspondence relationship between the column address and segment driver.
0: Reversal (column address 199–n ↔ SEG n)
1: Normal rotation (column address n ↔ SEG n)
(Reverses the polarity of ADC command.)
ON/OFF: Specifies display ON/OFF
0: Display ON
1: Display OFF
(Reverses the polarity of display ON/OFF command.)
Indicates the RES signal or that initial setting is being done using the reset command.
0: Operating state
1: Resetting
(6) Display Data Write
This command writes 8-bit data to the specified address of the display data RAM. Since the column address is
automatically incremented by 1 after the data is written, the MPU can successively write the display data.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
Write data
(7) Display Data Read
This command reads the 8-bit data in the specified address of the display data RAM. Since the column address is
automatically incremented by 1 after the data is written, the MPU can successively read the data consisting of multiple
words.
Besides, immediately after the column address is set, dummy read is required one time. For details, see the description
of the Display data RAM and internal register access of “Function Description”.
When using the serial interface, the display cannot be read.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
10–40
0
1
Read data
EPSON
Rev. 3.1a
S1D15705 Series
(8) ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence relationship between the column address of the display RAM data shown
in Fig. 4 and the segment driver output. Therefore the order of the segment driver output pin can be reversed using the
command. After the display data is written and read, the column address is incremented by 1 according to the column
address of Fig. 4. For details, see the Column address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
0
0
Setting
0
Clockwise (normal rotation)
1
Counterclockwise (reversal)
(9) Display Normal Rotation/Reversal
This command can reversal display lighting and non-lighting without overwriting the contents of display data RAM.
In this case, the contents of display data RAM are held.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
1
1
Setting
0
LCD on potential (normal rotation)
RAM data HIGH
1
LCD on potential (reversal)
RAM data LOW
(10) Display All Lighting ON/OFF
This command can forcedly make all display set in the lighting state irrespective of the contents of display data RAM.
In this case, the contents of display data RAM are held.
This command has priority over the display normal rotation/reversal command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
1
0
Setting
0
Normal display state
1
Display all lighting
(11) LCD Bias Set
This command selects the bias ratio of the voltage required for liquid crystal drive. The command is valid when the V/
F circuit of the power supply circuit is operated.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
Rev. 3.1a
0
1
0
1
0
0
0
1
S1D15705*****
Selected state
S1D15707***** / S1D15708*****
0
1/9 bias
1/6 bias
1
1/7 bias
1/5 bias
EPSON
10–41
S1D15705 Series
(12) Read Modify Write
This command is used together with the end command. Once this command is entered, the column address can be
incremented by 1 only using the display data write command instead of being changed using the display read command.
This state is held until the end command is entered. When the end command is entered, the column address returns to
the address when the read modify write command is entered. This function can reduce the load of the MPU when
repeatedly changing data for a specific display area such as a blinking cursor.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
0
* The commands other than Display Data Read/Write can be used even in Read Modify Write mode. However, the
column address set command cannot be used.
• Sequence for cursor display
Page Address Set
Column Address Set
Read Modify Write
Dummy Read
Data Read
Data processing
Data Write
No
Is the change terminated?
Yes
End
Fig. 16
10–42
EPSON
Rev. 3.1a
S1D15705 Series
(13) End
This command resets the Read Modify Write mode and returns the column address to the mode initial address.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
Read Modify Write Mode Set
•••
N+m
N
End
Fig. 17
(14) Reset
This command initializes Display Start Line, Column Address, Page Address, Common Output State, V5 Voltage
Adjusting Built-in Resistance Ratio, Electronic Control, and Static Indicator and resets the Read Modify Write mode
and Test mode. This will not have any effect on the display data RAM. For details, see the Reset of “ Function
Description”.
Reset operation is performed after the reset command is entered.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
0
The initialization when the power is applied is performed using the reset signal to the RES pin. The reset command
cannot be substituted for the signal.
(15) Common Output State Selection
This command can select the scanning direction of the COM output pin. For details, see the Common Output State
Selection Circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1 0
0 0
1
Rev. 3.1a
*
*
Selected state
S1D15705***** S1D15707***** S1D15708*****
* Normal rotation COM0 → COM63 COM0 → COM31 C OM0 → COM15
Reversal
COM63 → COM0 COM31 → COM0 COM15→ COM0
*: Invalid bit
EPSON
10–43
S1D15705 Series
(16) Power Control Set
This command sets the function of the power supply circuit. For details, see the Power Supply Circuit of “Function
Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
0
1
0
1
Selected state
Boosting circuit: OFF
Boosting circuit: ON
0
1
V adjusting circuit: OFF
V adjusting circuit: ON
0
V/F circuit: OFF
1
V/F circuit: ON
(V/F circuit: Voltage follower circuit, V adjusting circuit: voltage adjusting circuit)
(17) V5 Voltage Adjusting Built-in Resistance Ratio Set
This command sets the V5 voltage adjusting built-in resistance ratio. For details, see the Power Supply Circuit of
“Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
↓
Rb to Ra ratio
Small
↓
1
1
0
1
1
1
Large
(18) Electronic Control (2-Byte Command)
This command controls the liquid crystal drive voltage V5 output from the voltage adjusting circuit of the built-in liquid
crystal power supply and can adjust the light and shade of liquid crystal display.
Since this command is a 2-byte command that is used together with the electronic control mode set command and
electronic control register set command, always use both the commands consecutively.
• Electronic Control Mode Set
Entering this command validates the electronic control register set command. Once the electronic control mode is set,
the commands other than the electronic control register set command cannot be used. This state is reset after data is set
in the register using the electronic control register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
10–44
1
0
1
0
0
0
0
0
0
1
EPSON
Rev. 3.1a
S1D15705 Series
• Electronic Control Register Set
This command is used to set 6-bit data in the electronic volume register to allow the liquid crystal drive voltage V5 to
enter one-state voltage value among 64-state voltage values.
After this command is entered and the electronic control register is set, the electronic control mode is reset.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
*
*
0
0
0
0
0
0
0
1
0
*
*
0
0
0
0
0
1
0
1
0
*
*
0
0
0
0
1
0
| V5 |
Small
↓
0
1
0
*
*
1
1
1
↓
1
1
0
0
1
0
*
*
1
1
1
1
1
1
Large
When not using the electronic control function, set (1,0,0,0,0,0).
*: Invalid bit
• Sequence of the electronic control register set
Electronic Control Mode Set
Electronic Control Register Set
Electronic control mode reset
No
Is the change terminated?
Yes
Fig. 18
(19) Static Indicator (2-Byte Command)
This command controls the indicator display of the static drive system. The static indicator display is controlled only
using this command, and this command is independent of other display control commands.
The static indicator is used to connect the SYNC pin to one of its liquid crystal drive electrodes and the FRS pin to the
other. For the electrodes used for the static indicator, the pattern separated from the electrodes for dynamic drive are
recommended. When this pattern is too adjacent, the deterioration of liquid crystal and electrodes may be caused.
Since the static indicator ON command is a 2-byte command that is used together with the static indicator register set
command, always use both the commands consecutively. (The static indicator OFF command is a 1-byte command.)
Rev. 3.1a
EPSON
10–45
S1D15705 Series
• Static Indicator ON/OFF
Entering the static indicator ON command validates the static indicator register set command. Once the static indicator
ON command is entered, the commands other than the static indicator register set command cannot be used. This state
is reset after the data is set in the register using the static indicator register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
1
0
Static indicator
0
OFF
1
ON
• Static Indicator Register Set
This command sets data in the 2-bit static indicator register and sets the blinking state of the static indicator.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
*
*
*
*
*
*
Indicator display state
0
0
OFF
0
1
ON (blinks at an interval of approximately
0.5 second.)
1
0
ON (blinks at an interval of approximately
one second.)
1
1
ON (goes on at all times.)
*: Invalid bit
• Sequence of Static Indicator Register Set
Static Indicator ON
Static Indicator Register Set
(Static indicator
mode reset)
No
Is the change terminated?
Yes
Fig. 19
10–46
EPSON
Rev. 3.1a
S1D15705 Series
(20) Power Save
This command makes the static indicator enter the power save state and can greatly reduce the power consumption. The
power save state consists of the sleep state and stand-by state.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
0
0
0
1
Power save state
Stand-by state
Sleep state
The operating state before the display data and power save activation is held in the sleep and stand-by states, and the
display data RAM can also be accessed from the MPU.
• Sleep State
This command stops all the operations of LCD display systems, and can reduce the power consumption approximate
to the static current when they are not accessed from the MPU. The internal state in the sleep state is as follows:
(1) The oscillator circuit and the LCD power supply circuit are stopped.
(2) All liquid crystal drive circuit is stopped and the segment and common drivers output the VDD level.
• Stand-by State
This command stops the operation of the duty LCD display system and operates only the static drive system for
indicators. Consequently the minimum current consumption required for the static drive is obtained. The internal state
in the stand-by state is as follows:
(1) The LCD power supply circuit is stopped. The oscillator circuit is operated.
(2) The duty drive system liquid crystal drive circuit is stopped and the segment and common drivers output the VDD
level. The static drive system is operated.
* When using external power supplies, it is recommended that the function of the external power supply circuit
should be stopped at power save activation. For example, when providing each level of the liquid crystal drive
voltage using a stand-alone split resistor circuit, it is recommended that the circuit which cuts off the current
applied to the split resistor circuit should be added at power save activation. The S1D15705 series has the liquid
crystal display blanking control pin DOF and is set to LOW at power save activation. The function of the
external power supply circuit can be stopped using the DOF output.
(21) Power Save Reset
This command resets the power save state and returns the state before power save activation.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
1
(22) n-Line Reversal Drive Register Set
This command sets the number of reversal lines of the liquid crystal drive in the register. 2 to 16 lines can be set. For
details, see the Display Timing Generator Circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
Rev. 3.1a
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
↓
1
1
0
1
0
0
1
EPSON
Line of reversal lines
—
2
3
↓
15
16
10–47
S1D15705 Series
(23) n-Line Reversal Drive Reset
This command resets the n-line reversal alternating current drive and returns to the normal 2-frame reversal alternating
current drive system. The value of the n-line reversal alternating current drive register is not changed.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
1
0
0
(24) Built-in Oscillator Circuit ON
This command starts the operation of the built-in CR oscillator circuit. This command is valid only for the master
operation (M/S=HIGH) and built-in oscillator circuit valid (CLS=HIGH).
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
0
1
1
(25) NOP
Non-OPeration
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
1
(26) Test
IC chip test command. Do not use this command. If the test command is used incorrectly, it can be reset by setting the
RES input to LOW or by using the reset command or NOP.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
1
*
*
*
*
*: Invalid bit
(Note) Although the S1D15705 series holds the command operating state, it may change the internal state if excessive
foreign noise is entered. Such action that suppresses the generation of noise and prevents the effect of noise
needs to be taken on installation and systems. Besides, to prevent sudden noise, it is recommended that the
operating state should periodically be refreshed.
10–48
EPSON
Rev. 3.1a
S1D15705 Series
Table 16 S1D15705 Series Commands
Command
(1) Display ON/OFF
(2) Display Start Line Set
(3) Page Address Set
(4) Column Address Set
High-Order Bit
Column Address Set
Low-Order Bit
(5)
(6)
(7)
(8)
Status Read
Display Data Read
Display Data Write
ADC Select
Command code
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
0 1
0
1 0 1 0 1 1 1 0 LCD display ON/OFF
1
0: OFF, 1: ON
0 1
0
0 1
Display start address Sets the display start line
address of the display RAM.
0 1
0
1 0 1 1
Page
Sets the page address of
Address
the display RAM.
0 1
0
0 0 0 1
High order
Sets the high-order four bits of
Column
the column address of the display
address
RAM.
0 1
0
0 0 0 0
Low order
Sets the low-order four bits of
Column
the column address of the display
address
RAM.
0
1
1
0
0
1
0
1
1
0
1
0
Status
0 0
Write data
Read data
1 0 1 0 0 0
0
0
0
0
1
(9) Display Normal
Rotation/Reversal
0
1
0
1
0
1
0
0
1
1
0
1
(10) Display All Lighting
ON/OFF
(11) LCD Bias Set
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
(12) Read Modify Write
0
1
0
1
1
1
0
0
0
0
0
Reads the status information.
Writes data on the display RAM.
Reads data from the display RAM.
Supports the SEG output of
the display RAM address.
0: normal rotation, 1: Reversal
LCD display normal rotation/
reversal
0: normal rotation, 1: Reversal
Display all lighting
0: normal display, 1: All ON
Sets the LCD drive voltage bias ratio.
S1D15705 ***** 0: 1/9, 1: 1/7,
S1D15707 ***** 0: 1/6, 1: 1/5
Increments the column address.
At write operation: By 1, at read: 0
Resets Read Modify Write.
(13) End
0
1
0
1
1
1
0
1
1
1
0
(14) Reset
(15) Common Output State
Selection
0
0
1
1
0
0
1 1
1 1
1
0
0
0
0
0
0
*
1
*
0
*
(16) Power Control Set
0
1
0
0
0
1
0
1
1
(17) V5 Voltage Adjusting Internal 0
Resistance Ratio Set
(18) Electronic Control
0
Mode Set
Electronic Control
0
Register Set
(19) Static Indicator ON/OFF
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
*
*
1
0
1
0
1
Sets the V5 output voltage
in the electronic register.
0: OFF, 1: ON
Moves to the power save state.
0: Stand-by, 1: Sleep
Resets power save.
Sets the number of line
reversal drive lines.
Resets the line reversal drive.
Starts the operation of the built-in
CR oscillator circuit.
Non-Operation command
Do not use the IC chip
test command.
*: Invalid bit
Internal resetting
Selects the scanning direction of
the COM output.
0: Normal rotation, 1: Reversal
Operating Selects the state of the built-in
state
power supply
Resistance Selects the state of the built-in
ratio setting resistance ratio (Rb/Ra).
0 0 1
Static Indicator
Register Set
(20) Power Save
0
1
0
*
*
*
Electronic
control value
0 1 1 0 0
1
* * * State
0
1
0
1
0
1
0
1
(21) Power Save Reset
(22) n-Line Reversal Drive
Register Set
(23) n-Line Reversal Drive Reset
(24) Built-in Oscillator
Circuit ON
(25) NOP
(26) Test
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
1
1
0
0
0 0 0
Number of
reversal Line
0 1 0 0
1 0 1 1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
*
Rev. 3.1a
EPSON
0
0
*
0
1
*
0
1
1
1
*
Sets the blinking state.
10–49
S1D15705 Series
8. COMMAND SETTING
Instruction Setup: Reference
(1) Initial Setting
Turn on the VDD - VSS power supply in the RES pin=LOW *1
Power supply regulated
Reset the reset state (RES pin=HIGH)
Initial setting state (default) *2
Function setting by command input (set by user)
(24) Built-in Oscillator Circuit ON *3
(The built-in CR oscillator circuit is used)
Function setting by command input (set by user)
(11) LCD Bias Set *4
(8) ADC Select *5
(15) Common Output State Selection *6
(22) n-Line Reversal Register Set *7
(When the n-line alternating current
reversal drive is used)
Function setting by command input (set by user)
(17) V5 Voltage Adjusting Built-in Resistance
ratio Set *8
(18) Electronic Control *9
Function setting by command input (set by user)
(16) Power Control Set *10
End of initial setting
Notes: Reference items
*1: If external power supplies for driving LCD are used, do not supply voltage on VOUT or V5 pin during
the period when RES = LOW. Instead, input voltage after releasing the reset state.
6. Function Description “Reset Circuit”
*2: The contents of DDRAM are not defined even in the initial setting state after resetting.
6. Function Description Section “Reset Circuit”
*3: 7. Command Description Item (24) Built-in oscillator circuit ON
*4: 7. Command Description Item (11) LCD bias set
*5: 7. Command Description Item (8) ADC select
*6: 7. Command Description Item (15) Common output state selection
*7: 6. Function Description Section “Display Timing Generator Circuit”, 7. Command Description Item (22)
n-Line Reversal Register Set
*8: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (17) V5
Voltage Adjusting Built-in Resistance ratio Set
*9: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (18)
Electronic Control
*10: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (16)
Power Control Set
10–50
EPSON
Rev. 3.1a
S1D15705 Series
(2) Data Display
End of initial setting
Function setting by command input (set by user)
(2) Display Start Line Set *11
(3) Page Address Set *12
(4) Column Address Set *13
Function setting by command input (set by user)
(6) Display Data Write *14
Function setting by command input (set by user)
(1) Display ON/OFF *15
End of data display
Notes: Reference items
*11: 7. Command Description Item (2) Display Start Line Set
*12: 7. Command Description Item (3) Page Address Set
*13: 7. Command Description Item (4) Column Address Set
*14: The contents of DDRAM is not defined after completing initial setting. Enter data in each DDRAM to
be used for display.
7. Command Description Item (6) Display Data Write
*15: Avoid activating the display function with entering space characters as the data if possible.
7. Command Description Item (1) Display ON/OFF
(3) Refresh *16
A desired mode
Set all commands again.
Write in the display data RAM again.
Notes: Reference items
*16: It is recommended that the operating modes and display contents be refreshed periodically to prevent
the effect of unexpected noise.
Rev. 3.1a
EPSON
10–51
S1D15705 Series
(4) Power OFF *17
Any desired state
Function setting by command input (set by user)
(20) Power Save *18
Reset state (RES pin=LOW) *19
Set the time interval after the point when reset
state has attained and the point when VDD — VSS
power is shut off (tL) so that electric potentials, V1
through V5, attain values lower than the threshold
voltage displayed on the LCD panel. *20
VDD — VSS power OFF
Notes: Reference items
*17: This IC is a VDD – VSS power system circuit controlling the LCD driving circuit for the VDD – V5
power system. Shutting of power with voltage remaining in the VDD – V5 power system may cause
uncontrolling voltage to be output from the SEG and COM pins. Follow the Power OFF sequence.
*18: 7. Command Description Item Power Saving
*19: When external power supplies for driving LCD are used, turn all external power supplies off before
entering reset state.
6. Function Description Item Reset Circuit
*20: The reference value for the threshold voltage of the LCD panel is 1 [V].
When the built-in power circuit is used, the discharge time, tH, or the time interval between the point
when the reset state has started and the point when voltage between VDD and V 5 becomes 1 [V]
depends on the VDD – VSS power voltage and the capacity C2 connected between V1 – V5 and VDD.
V5 voltage discharge time [ms]
100
80
60
40
20
0
0
0.2
0.4
0.6
Capacity C2 [µF]
0.8
1
Fig. 20
10–52
EPSON
Rev. 3.1a
S1D15705 Series
Set up tL so that the relationship, tL > tH, is maintained. A state of tL < tH may cause faulty display.
tL
Power saving
Power OFF
VDD
2.4 [V]
RES
As power (VDD – VSS)
is shut off, it becomes
impossible to fix output.
SEG
COM
At or under Vth on LCD.
Use 1.0 [V] as a
reference.
VDD
V1
V2
V3
V4
V5
tH
Fig. 21
tL
Power OFF
Take action so that the relationship,
tL > tH, is maintained by measures
such as making the trailing
characteristic longer.
VDD
2.4 [V]
RES
As power (VDD – VSS)
is shut off, it becomes
unable to fix output.
SEG
COM
At or under Vth on LCD.
Use 1.0 [V] as a
reference.
VDD
V1
V2
V3
V4
V5
tH
If command control is disabled when power is OFF, take action so that the relationship, tL > tH, is
maintained by measures such as making the trailing characteristic of power (VDD – VSS ) longer.
Fig. 22
Rev. 3.1a
EPSON
10–53
S1D15705 Series
9. ABSOLUTE MAXIMUM RATINGS
Table 17
VSS=0 V unless specified otherwise
Item
Symbol
Power supply voltage
VDD
Power supply voltage (2)
(Based on VDD )
At triple boosting
VSS2
At quadruple boosting
Specification value
–0.3
to
+7.0
–7.0
to
+0.3
–6.0
to
+0.3
–4.5
to
+0.3
Power supply voltage (3) (Based on VDD)
V5, VOUT
–20.0
to
+0.3
Power supply voltage (4) (Based on VDD)
V1, V2, V3, V 4
V5
to
+0.3
Input voltage
VIN
–0.3
to VDD+0.3
Output voltage
VO
–0.3
to VDD+0.3
TOPR
–40
to
+85
TSTR
–55
to
+100
–55
to
+125
Operating temperature
Storage temperature
TCP
Bare chip
VCC
VDD
GND
VSS
Unit
V
°C
VDD
VSS2, V1 to V4
V5, VOUT
System (MPU) side
S1D15705 side
Fig. 23
(Notes) 1.
2.
3.
4.
10–54
The values of the VSS2 , V1 to V5 , and VOUT voltages are based on VDD=0 V.
The V1, V2, V3, and V 4 voltages must always satisfy the condition of VDD≥V1≥V2≥V3≥V4≥V5.
The VSS2 and VOUT voltages must always satisfy the condition of VDD≥VSS≥VSS2≥VOUT.
When LSI is used exceeding the absolute maximum ratings, the LSI may be damaged permanently.
Besides, it is desirable that the LSI should be used in the electrical characteristics condition for normal
operation. If this condition is exceeded, the LSI may malfunction and have an adverse effect on the
reliability of the LSI.
EPSON
Rev. 3.1a
S1D15705 Series
10. DC CHARACTERISTICS
Table 18
Unless otherwise specified, VSS=0 V, Ta=–40 to 85°C
Specification value
Min.
Typ.
Max.
2.4
—
3.6
3.6
—
5.5
Item
Operating voltage (1)
Symbol
Condition
S1D15705*03**/S1D15707*03**
V DD
V DD
S1D15705*00**/S1D15707*00**
/S1D15708*00**
Operating voltage (2)
V SS2 (Based on VDD)
–6.0
Operating voltage (3)
V5
S1D15705***** (Based on VDD)
–18.0
V5
S1D15707***** (Based on VDD)
–16.0
V5
S1D15708***** (Based on VDD)
–10.0
V 1, V2 (Based on VDD)
0.4×V5
V 3, V4 (Based on V DD)
V5
High level input voltage
VIHC
0.8×VDD
Low level input voltage
VILC
VSS
0.8×VDD
High level output voltage
VOHC IOH=–0.5mA
Low level output voltage
V OLC IOL =0.5mA
VSS
Input leak current
ILI
V IN=VDD or VSS
–1.0
Output leak current
ILO
–3.0
Liquid crystal driver
RON
Ta=25°C
V5=–14.0V
—
On resistance
(Based on V DD) V5=–8.0V
—
Static current consumption I SSQ
—
Output leak current
I5Q
V 5=–18.0V (Based on VDD)
—
Input pin capacity
CIN
Ta=25°C, f=1MHz
—
Oscillating Built-in
fOSC
Ta=25°C
18
frequency oscillation
External input
fCL
Ta=25°C, S1D15705*****
4.5
Ta=25°C, S1D15707*****
2.25
Ta=25°C, S1D15708*****
1.13
—
—
—
—
—
—
—
—
—
—
—
—
2.0
3.2
0.01
0.01
5.0
22
–1.8
–4.5
–4.5
–4.5
V DD
0.6×V 5
V DD
0.2×V DD
V DD
0.2×V DD
1.0
3.0
3.5
5.4
5
15
8.0
26
5.5
2.75
1.38
6.5
3.25
1.63
Applicable
Unit
pin
V
VDD *1
VDD *1
µA
kΩ
µA
VSS2
V5 *2
V5 *2
V5 *2
V1, V2
V3, V4
*3
*3
*4
*4
*5
*6
SEGn
COMn *7
V SS, VSS2
V5
pF
*8
kHz
CL *8
CL *8
CL *8
Table 19
Built-in power supply circuit
Item
Input voltage
Symbol
V SS2
V SS2
Boosting output voltage VOUT
Voltage adjusting circuit VOUT
operating voltage
V/F circuit operating
V5
voltage
V5
V5
Reference voltage
VREG0
Condition
At triple boosting
(Based on V DD)
At quadruple boosting
(Based on V DD)
(Based on V DD) –20.0
(Based on V DD) –20.0
S1D15705***** (Based on VDD)
S1D15707***** (Based on VDD)
S1D15708***** (Based on VDD)
Ta=25°C,
–0.05%/°C
Specification value
Min.
Typ.
Max.
–6.0
—
–1.8
–4.5
—
—
—
—
–6.0
–18.0
–16.0
–10.0
–2.04
—
—
—
–2.10
Unit
V
–1.8
Applicable
pin
VSS2
VSS2
V OUT
V OUT
–4.5
–4.5
–4.5
–2.16
V5 *9
V5 *9
V5 *9
*10
[*: see Page 61.]
Rev. 3.1a
EPSON
10–55
S1D15705 Series
Dynamic current consumption value (1) During display operation and built-in power supply OFF
Current values dissipated by the whole IC when the external power supply is used
Table 20-1 Display All White
Item
S1D15705*00**
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
Ta=25°C
Symbol
IDD
(1)
Condition
VDD=5.0V, V5–VDD =–11.0V
VDD=3.0V, V5–VDD =–11.0V
VDD=5.0V, V5–VDD =–8.0V
VDD=3.0V, V5–VDD =–8.0V
VDD=5.0V, V5–VDD =–6.0V
Specification value
Min.
Typ.
Max.
—
22
37
—
22
37
8
14
8
14
4
7
Unit Remarks
µA
Table 20-2 Display Checker Pattern
Item
S1D15705*00**
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
Symbol
IDD
(1)
*11
Ta=25°C
Condition
VDD=5.0V, V5–VDD =–11.0V
VDD=3.0V, V5–VDD =–11.0V
VDD=5.0V, V5–VDD =–8.0V
VDD=3.0V, V5–VDD =–8.0V
VDD=5.0V, V5–VDD =–6.0V
Specification value
Min.
Typ.
Max.
—
33
55
—
32
54
14
24
14
24
5
9
Unit Remarks
µA
*11
Dynamic current consumption value (2) During display operation and built-in power supply ON
Current values dissipated by the whole IC containing the built-in power supply circuit
Table 21-1 Display Checker Pattern
Item
S1D15705*00**
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
Symbol
IDD
(2)
Ta=25°C
Condition
VDD=5.0V,
Triple boosting
V5–VDD=–11.0V
VDD=3.0V,
Quadruple boosting
V5–VDD=–11.0V
VDD=5.0V,
Triple boosting
V5–VDD=–8.0V
VDD=3.0V,
Quadruple boosting
V5–VDD=–8.0V
VDD=5.0V,
Double boosting
V5–VDD=–6.0V
Normal mode
Specification value
Min.
Typ.
Max.
—
73
122
High power mode
Normal mode
—
—
216
92
360
154
High power mode
Normal mode
—
—
272
40
454
67
High power mode
Normal mode
—
—
171
51
285
85
High power mode
Normal mode
—
—
228
28
380
47
High power mode
—
137
229
Unit Remarks
µA
*12
[*: see Page 61.]
10–56
EPSON
Rev. 3.1a
S1D15705 Series
Table 21-2 Display Checker Pattern
Item
S1D15705*00**
Symbol
IDD
(2)
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
Ta=25°C
Condition
VDD=5.0V,
Triple boosting
V5–VDD=–11.0V
VDD=3.0V,
Quadruple boosting
V5–VDD=–11.0V
VDD=5.0V,
Triple boosting
V5–VDD=–8.0V
VDD=3.0V,
Quadruple boosting
V5–VDD=–8.0V
VDD=3.0V,
Double boosting
V5–VDD=–6.0V
Normal mode
Specification value
Min.
Typ.
Max.
—
97
162
High power mode
Normal mode
—
—
254
130
424
217
High power mode
Normal mode
—
—
308
54
514
90
High power mode
Normal mode
—
—
185
71
309
119
High power mode
Normal mode
—
—
248
35
414
59
High power mode
—
144
240
Unit Remarks
µA
*12
Current consumption at power save VSS =0 V and VDD= 3.0 V ±10% (S1D15705*03**, S1D15707*03**)
5.0V ± 10% (S1D15705*00**, S1D15707*00**,
S1D15708*00**)
Table 22
Item
Sleep state
Stand-by state
Ta=25°C
Symbol
Condition
IDDS1
IDDS2
Ta=25°C
Ta=25°C
Specification value
Min.
Typ.
Max.
—
0.01
5
—
4
8
Unit Remarks
µA
[*: see Page 61.]
Rev. 3.1a
EPSON
10–57
S1D15705 Series
[Reference data 1]
• Dynamic current consumption (1) External power supply used and LCD being displayed
IDD (1) (ISS + I5) [µA]
40
S1D15705/
Checker
S1D15705*03**/ S1D15705*00**/
S1D15707 03
S1D15707 00
30
* **
* **
S1D15705/
All white
20
S1D15707/
Checker
S1D15707/
All white
10
Condition: Built-in power supply OFF
External power supply used
S1D15705: V5 – VDD = –11.0 V
S1D15707: V5 – VDD = –8.0 V
S1D15708: V5 – VDD = –6.0 V
Display pattern: All white/checker
Ta = 25°C
Remarks: *11
S1D15708/Checker
S1D15708/All white
0
0
2
3.6 4
6
8
VDD [V]
Fig. 24
[Reference data 2]
• Dynamic current consumption (2) Built-in power supply used and LCD being displayed
250
IDD (2) [µA]
200
S1D15705 03 /
* **
S1D15707*03**
S1D15705 00 /
* **
S1D15707*00**
150
S1D15705/Checker
100
S1D15705/All white
50
0
0
2
3.6 4
S1D15707/Checker
S1D15707/All white
S1D15708/Checker
S1D15708/All white
6
8
Condition: Built-in power supply ON
Normal mode
Quadruple boosting
S1D15705: V5 – VDD = –11.0 V
Triple boosting
S1D15707: V5 – VDD = –8.0 V
Double boosting
S1D15708: V5 – VDD = –6.0 V
Display pattern: All white/checker
Ta = 25°C
Remarks: *12
VDD [V]
Fig. 25
[*: see page 61.]
10–58
EPSON
Rev. 3.1a
S1D15705 Series
[Reference data 3]
• Dynamic current consumption (3) During access
Indicates the current consumption when the checker
pattern is always written at fCYC.
Only IDD (1) when not accessed
Condition: Built-in power supply OFF and external
power supply used
S1D15705:
V5 – VDD = –11.0 V
S1D15707:
V5 – VDD = –11.0 V
S1D15705*03**/S1D15707*03**:
VDD – VSS = 3.0 V
S1D15705*00**/S1D15707*00**
/S1D15708*00**:
VDD – VSS = 5.0 V
Ta = 25°C
10
* **
IDD (3) [mA]
1
S1D15705 00
* **
S1D15705 03
* **
S1D15707*00**
S1D15707 03
* **
S1D15708 00
0.1
[*: see page 61.]
0.01
0.001
0.01
0.1
1
10
fCYC [MHz]
Fig. 26
Rev. 3.1a
EPSON
10–59
S1D15705 Series
[Reference data 4]
V SS and V 5 system operating voltage
ranges
Remarks: *2
–20
–20
–18
–15
–16
S1D15705 00
* **
S1D15705 03
* **
–15
S1D15707 03
S1D15707 00
–10
V5 - VDD [V]
V5 - VDD [V]
* **
Operation
Area
–9.6
–5
–10
* **
Operation
Area
–9.6
–5
–4.5
–4.5
2.4
0
0
2
3.6
4
5.5
6
2.4
8
VDD [V]
0
0
2
3.6
5.5
4
6
8
VDD [V]
–20
[*: see page 10-61.]
V5 - VDD [V]
–15
S1D15708 00
* **
–10
Operation
Area
–5
–4.5
0
0
2
3.6
5.5
4
6
8
VDD [V]
Fig. 27
10–60
EPSON
Rev. 3.1a
S1D15705 Series
Relationships between the oscillating frequency fOSC, display clock frequency f CL, and liquid
crystal frame frequency f FR
Table 23
Item
fCL
fFR
S1D15705***** When built-in oscillator
fOSC
fOSC
circuit used
4
4*65
When built-in oscillator
External input (fCL)
fCL
circuit not used
65
S1D15707***** When built-in oscillator
fOSC
fOSC
circuit used
8
8*33
When built-in oscillator
External input (fCL)
fCL
circuit not used
33
S1D15708***** When built-in oscillator
fOSC
fOSC
circuit used
16
16*17
When built-in oscillator
External input (fCL)
fCL
circuit not used
17
(fFR indicates the alternating current cycle of the liquid crystal and does not indicate that of the FR signal.)
[Reference items marked by *]
*1 The wide operating voltage range is not warranted. However, when there is a sudden voltage change
during MPU access, it cannot be warranted.
*2 For the VDD and V5 operating voltage ranges, see Fig. 27. These ranges are applied when using the
external power supply.
*3 A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF,
RES, IRS and HPM pins
*4 D0 to D7, FR, FRS, DOF and CL pins
*5 A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS and HPM pins
*6 Applied when D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF pins are in the high impedance state
*7 Resistance value when the 0.1 V voltage is applied between the output pin SEGn or COMn and power
supply pins (V1, V2, V3, and V 4). Specified within the range of operating voltage (3)
RON = 0.1 V/∆I (∆I indicates the current applied when 0.1 V is applied between the power ON.)
*8 For the relationship between the oscillating frequency and frame frequency, see Table 23. The
specification value of the external input item is a recommended value.
*9 The V5 voltage adjusting circuit is adjusted within the voltage follower operating voltage range.
*10 Built-in reference voltage source of the V5 voltage adjusting circuit.
*11 and *12 Indicate the current dissipated by a single IC at built-in oscillator circuit used, 1/9 bias
(S1D15705*****), 1/6 bias (S1D15707*****/S1D15708*****), and display ON.
Does not include the current due to the LCD panel capacity and wireing capacity.
Applicable only when there is no access from the MPU.
*12 When the V5 voltage adjusting built-in resistor is used
Rev. 3.1a
EPSON
10–61
S1D15705 Series
Timing Characteristics
System bus read/write characteristics 1 (80 series MPU)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
*1
tCCLR, tCCLW
WR, RD
tCCHR, tCCHW
CS1
(CS2="1")
*2
tf
tr
WR, RD
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
[S1D15705*00**, S1D15707*00 **, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Specification value
Item
Signal Symbol
Condition
Unit
Min.
Max.
0
—
ns
Address hold time
A0
tAH8
Address setup time
tAW8
0
—
System cycle time
tCYC8
250
—
Control LOW pulse width (Write)
WR
tCCLW
30
—
Control LOW pulse width (Read) RD
tCCLR
70
—
Control HIGH pulse width (Write)
WR
tCCHW
30
—
Control HIGH pulse width (Read) RD
tCCHR
30
—
D0 to D7
tDS8
30
—
Data setup time
Data hold time
tDH8
10
—
CL=100pF
—
70
RD access time
tACC8
Output disable time
tOH8
5
50
10–62
EPSON
Rev. 3.1a
S1D15705 Series
[S1D15705*00 **, S1D15707*00**, S1D15708*00 **: VDD=3.6V to 4.5V, Ta=–40 to 85°C]
Specification value
Item
Signal Symbol
Condition
Unit
Min.
Max.
0
—
ns
Address hold time
A0
tAH8
Address setup time
tAW8
0
—
System cycle time
tCYC8
300
—
Control LOW pulse width (Write)
WR
tCCLW
60
—
Control LOW pulse width (Read) RD
tCCLR
120
—
Control HIGH pulse width (Write)
WR
tCCHW
60
—
Control HIGH pulse width (Read) RD
tCCHR
60
—
D0 to D7
tDS8
40
—
Data setup time
Data hold time
tDH8
15
—
CL=100pF
—
280
RD access time
tACC8
Output disable time
tOH8
10
100
[S1D15705*03**, S1D15707*03 **: VDD=2.4V to3.6V, Ta=–40 to 85°C]
Specification value
Item
Signal Symbol
Condition
Unit
Min.
Max.
0
—
ns
Address hold time
A0
tAH8
Address setup time
tAW8
0
—
System cycle time
tCYC8
800
—
Control LOW pulse width (Write)
WR
tCCLW
120
—
Control LOW pulse width (Read)
RD
tCCLR
240
—
Control HIGH pulse width (Write)
WR
tCCHW
120
—
Control HIGH pulse width (Read) RD
tCCHR
120
—
D0 to D7
tDS8
80
—
Data setup time
Data hold time
tDH8
30
—
CL=100pF
—
280
RD access time
tACC8
Output disable time
tOH8
10
200
*1
*2
*3
*4
*5
This is in the case of making the access by WR and RD, setting the CS1=LOW.
This is in the case of making the access by CS1, setting the WR, RD=LOW.
The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr +tf ) ≤ (tCYC8–t CCLW–tCCHW) or (t r+tf ) ≤ (tCYC8–tCCLR–t CCHR).
All timings are specified based on the 20 and 80% of VDD.
tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2= HIGH) level and WR, RD are
at the LOW level.
Rev. 3.1a
EPSON
10–63
S1D15705 Series
System bus read/write characteristics 2 (68 series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
tCYC6
*1
tEWHR, tEWHW
E
tEWLR, tEWLW
CS1
(CS2="1")
tr
*2
tf
E
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
Max.
0
—
ns
Address hold time
A0
tAH6
Address setup time
tAW6
0
—
System cycle time
tCYC6
250
—
30
—
Data setup time
D0 to D7
tDS6
Data hold time
tDH6
10
—
CL=100pF
—
70
Access time
tACC6
Output disable time
tOH6
5
50
Enable HIGH pulse width Read
E
tEWHR
70
—
Write
tEWHW
30
—
Enable LOW pulse width Read
E
tEWLR
30
—
Write
tEWLW
30
—
10–64
EPSON
Rev. 3.1a
S1D15705 Series
[S1D15705*00 **, S1D15707*00**, S1D15708*00 **: VDD=3.6V to 4.5V, Ta=–40 to 85°C]
Specification value
Item
Signal
Symbol
Condition
Min.
Max.
Unit
Address hold time
A0
tAH6
0
—
ns
Address setup time
tAW6
0
—
System cycle time
tCYC6
300
—
Data setup time
D0 to D7
tDS6
40
—
Data hold time
tDH6
15
—
CL=100pF
—
140
Access time
tACC6
Output disable time
tOH6
10
100
Enable HIGH pulse width Read
E
tEWHR
120
—
Write
tEWHW
60
—
Enable LOW pulse width Read
E
tEWLR
60
—
Write
tEWLW
60
—
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse width Read
Write
Enable LOW pulse width Read
Write
*1
*2
*3
*4
*5
[S1D15705*03**, S1D15707*03 **: VDD=2.4V to 3.6V, Ta=–40 to 85°C]
Specification value
Signal
Symbol
Condition
Unit
Min.
Max.
0
—
ns
A0
tAH6
tAW6
0
—
tCYC6
800
—
D0 to D7
tDS6
80
—
tDH6
30
—
tACC6
CL=100pF
—
280
tOH6
10
200
E
tEWHR
240
—
tEWHW
120
—
E
tEWLR
120
—
tEWLW
120
—
This is in the case of making the access by E, setting the CS1=LOW.
This is in the case of making the access by CS1, setting the E=HIGH.
The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr +tf ) ≤ (tCYC6–t EWLW–t EWHW) or (t r+tf ) ≤ (tCYC6–tEWLR –tEWHR).
All timings are specified based on the 20 and 80% of VDD.
tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2= HIGH) level and E is at the
HIGH level.
Rev. 3.1a
EPSON
10–65
S1D15705 Series
Serial interface
tCSS
CS1
(CS2="1")
tCSH
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
Max.
Serial clock cycle
SCL
tSCYC
200
—
ns
SCL HIGH pulse width
tSHW
75
—
SCL LOW pulse width
tSLW
75
—
Address setup time
A0
tSAS
50
—
Address hold time
tSAH
100
—
Data setup time
SI
tSDS
50
—
Data hold time
tSDH
50
—
CS-SCL time
CS
tCSS
100
—
tCSH
100
—
10–66
EPSON
Rev. 3.1a
S1D15705 Series
[S1D15705*00 **, S1D15707*00**, S1D15708*00 **: VDD=3.6V to 4.5V, Ta=–40 to 85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
Max.
Serial clock cycle
SCL
tSCYC
250
—
ns
100
—
SCL HIGH pulse width
tSHW
SCL LOW pulse width
tSLW
100
—
Address setup time
A0
tSAS
150
—
Address hold time
tSAH
150
—
100
—
Data setup time
SI
tSDS
Data hold time
tSDH
100
—
CS-SCL time
CS
tCSS
150
—
tCSH
150
—
Item
Serial clock cycle
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
*1
*2
[S1D15705*03**, S1D15707*03 **: VDD=2.4V to 3.6V, Ta=–40 to 85°C]
Specification value
Signal
Symbol
Condition
Unit
Min.
Max.
SCL
tSCYC
400
—
ns
tSHW
150
—
tSLW
150
—
A0
tSAS
250
—
tSAH
250
—
SI
tSDS
150
—
tSDH
150
—
CS
tCSS
250
—
tCSH
250
—
The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns.
All timings are specified based on the 20 and 80% of VDD.
Rev. 3.1a
EPSON
10–67
S1D15705 Series
Display control output timing
CL
(OUT)
tDFR
FR
tDSNC
SYNC
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Item
Signal
Symbol
Condition
FR delay time
SYNC delay time
FR
SYNC
tDFR
CL=50pF
CL=50pF
tDSNC
Specification value
Min.
Typ.
Max.
—
10
40
—
10
40
Unit
ns
ns
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=3.6V to 4.5V, Ta=–40 to 85°C]
Item
FR delay time
SYNC delay time
Signal
FR
SYNC
Symbol
tDFR
tDSNC
Condition
CL=50pF
CL=50pF
Specification value
Min.
Typ.
Max.
—
20
80
—
20
80
Unit
ns
ns
[S1D15705*03**, S1D15707*03**: VDD=2.4V to 3.6V, Ta=–40 to 85°C]
Item
FR delay time
SYNC delay time
Signal
FR
SYNC
Symbol
tDFR
tDSNC
Condition
CL=50pF
CL=50pF
Specification value
Min.
Typ.
Max.
—
50
200
—
50
200
Unit
ns
ns
*1 Valid only when the master mode is selected.
*2 All timings are specified based on the 20 and 80% of VDD.
*3 Pay attention not to cause delays of the timing signals CL, FR and SYNC to the salve side by wiring resistance, etc.,
while master/slave operations are in progress. If these delays occur, indication failures such as flickering may occur.
10–68
EPSON
Rev. 3.1a
S1D15705 Series
Reset input timing
tRW
RES
tR
Internal state
Resetting
Completion of reset
[S1D15705*00 **, S1D15707*00**, S1D15708*00 **: VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Item
Reset time
Reset LOW pulse width
Signal
RES
Symbol
tR
tRW
Condition
Specification value
Min.
Typ.
Max.
—
—
0.5
0.5
—
—
Unit
µs
[S1D15705*00 **, S1D15707*00**, S1D15708*00 **: VDD=3.6V to 4.5V, Ta=–40 to 85°C]
Item
Reset time
Reset LOW pulse width
Signal
RES
Symbol
tR
tRW
Condition
Specification value
Min.
Typ.
Max.
—
—
1
1
—
—
Unit
µs
[S1D15705*03**, S1D15707*03 **: VDD=2.4V to 3.6V, Ta=–40 to 85°C]
Item
Reset time
Reset LOW pulse width
*1
Signal
RES
Symbol
tR
tRW
Condition
Specification value
Min.
Typ.
Max.
—
—
1.5
1.5
—
—
Unit
µs
All timings are specified based on the 20 and 80% of VDD.
Rev. 3.1a
EPSON
10–69
S1D15705 Series
11. MICROPROCESSOR (MPU) INTERFACE: REFERENCE
The S1D15705 series can directly be connected to the 80 system MPU and 68 series MUP. It can also be operated with
a fewer signal lines by using the serial interface.
The S1D15705 series is used for the multiple chip configuration to expand the display area. In this case, it can select
the ICs that are accessed individually using the Chip Select signal.
After the initialization using the RES pin, the respective input pins of the S1D15705 series need to be controlled
normally.
80 series MPU
VDD
VDD
A0
MPU
A1 to A7
IORQ
D0 to D7
RD
WR
RES
GND
A0
Decoder
RESET
CS1
CS2
D0 to D7
RD
WR
RES
VSS
C86
S1D15705
VCC
P/S
VSS
68 series MPU
VDD
VDD
MPU
A0
A1 to A15
VMA
D0 to D7
E
R/W
RES
GND
A0
Decoder
RESET
CS1
CS2
D0 to D7
E
R/W
RES
VSS
C86
S1D15705
VCC
P/S
VSS
Serial interface
VDD
A0
MPU
A1 to A7
A0
CS1
CS2
Decoder
Port 1
Port 2
RES
GND
SI
SCL
RES
VSS
RESET
C86
VDD or VSS
S1D15705
VCC
P/S
VSS
10–70
EPSON
Rev. 3.1a
S1D15705 Series
12. CONNECTION BETWEEN LCD DRIVERS: REFERENCE
The S1D15705 series is used for the multiple chip configuration to easily expand the liquid crystal display area. Use
the same device (S1D15705*****/S1D15705*****, S1D15707***** /S1D15707***** or S1D15708***** /
S1D15708*****) for the master/slave.
S1D15705 (master) ↔ S1D15705 (slave)
VDD
M/S
M/S
FR
SYNC
SYNC
CL
CL
DOF
DOF
Output
S1D15705
Slave
S1D15705
Master
FR
Input
VSS
Rev. 3.1a
EPSON
10–71
S1D15705 Series
13. LCD PANEL WIRING: REFERENCE
The S1D15705 series is used for the multiple chip configuration to easily expand the liquid crystal display area. Use
the same device (S1D15705*****/S1D15705*****, S1D15707*****/S1D15707***** or S1D15708*****/
S1D15708*****) for the multiple chip configuration.
1-chip configuration
168 x 65 Dots
COM
SEG
COM
S1D15705
Master
2-chip configuration
336 x 65 Dots
COM
SEG
SEG
S1D15705 Series
Master
10–72
COM
S1D15705 Series
Slave
EPSON
Rev. 3.1a
S1D15705 Series
14. TCP PIN LAYOUT
Reference
FRS
SYNC
COM S
COM 63
•
•
•
•
•
COM 33
COM 32
CHIP TOP VIEW
FR
CL
DOF
SYNC
CS1
CS2
RES
A0
WR,R/W
RD, E
D0
D1
D2
D3
D4
D5
D6, SCL
D7, SI
VDD
VSS
VSS2
VOUT
CAP3CAP1+
CAP1CAP2CAP2+
VRS
VDD
V1
V2
V3
V4
V5
VR
VDD
M/S
CLS
C86
P/S
HPM
IRS
SEG 167
SEG 166
•
•
•
•
•
SEG 1
SEG 0
COM S
COM 0
•
•
•
•
•
COM 30
COM 31
Note) This TCP pin layout does not specify the TCP dimensions.
Rev. 3.1a
EPSON
10–73
10–74
(Mold,Marking area)Part B
Part A Output terminal pattern shape
Part B Detail for Test pad
(Mold,Marking area)
Specifications
• Base: U-rex S 75µm
• Copper foil : Electrolytic copper foil, 25µm
• Sn plating
• Product pitch : 41p (19.0mm)
• Solder resist positional tolerance: ±0.3 (part for not specified)
S1D15705 Series
15. TCP DIMENSIONS
EPSON
Rev. 3.1a
S1D15705 Series
16. TEMPERATURE SENSOR CIRCUIT
S1D15705*10** incorporates a temperatujre sensor circuit with a 11.4mV/°C (typ.) temperature gradient carrying
analog voltage output pins. The S1D15705*10** makes it possible to provide LCD indications with optimum contrast
throughout a wide temperature range without need for use of supplementary parts by inputting electronic volume control
registration value equivalent signals corresponding to the outputs of the temperature sensor through the MPU to control
the LCD drive voltage V5.
For LCD drive voltage controls of higher precision, we recommend you to constitute a system which can absorb
deviations of the output voltage by, such as, feeding back sampled output voltages under a certain temperature
environment to the MPU to let it memorize as the reference voltages.
Regarding the specifications of other items than the temperature sensor circuit, such as of the absolute maximum ratings,
DC characteristics, AC characteristics, etc., refer to the specifications for S1D15705*00**.
Pin Definitions
Temperature sensor circuit related pins are allocated to TEST1, 2, 3 and 4 and the pin names are TEST1, SVS, VSEN,
SEN and SENSEL in the given sequence. The temperature sensor should be used under the pin statuses indicated in
the Table below. When the temperature sensor is not being used, fix respective pins to HIGH.
Number
of pins
Pin names
I/O
Pin definitions
SVS
This is the power supply pin for the temperature sensor. Apply
prescribed operating voltage between the VDD.
This is the analog voltage output pin for the temperature sensor.
Monitor the output voltage between the VDD.
1
VSEN
Power
supply
O
SEN
O
Consider to keep this pin open in order not to apply the load
capacitance of wires, etc.
1
SENSEL
I
Fix this pin to HIGH.
1
1
Electric Characteristics
Items
Operating voltage
Output voltage
Codes
Conditions
SVS
VSEN
(On the basis of VDD)
(On the basis of VDD)
Ta = 40°C
(On the basis of VDD)
Ta = 25°C
(On the basis of VDD)
Ta = 85°C
Specifications
Min.
Typ. Max.
–5.5 –5.0 –4.5
–4.35 –3.62 –2.89
Units
Applicable
pins
V
V
SVS
VSEN
–3.48 –2.88 –2.28
–2.92 –2.20 –1.47
Output voltage
temperature gradient
Output voltage linearity
VGRA
*1
9.4
11.4
13.4
mV/°C
VSEN
∆VL
*2
–1.5
—
1.5
%
VSEN
Output voltage setup time
tSEN
*3
100
—
—
mS
VSEN
Operating current
ISEN
Ta = 25°C
—
40
150
µA
SVS
Rev. 3.1a
EPSON
10–75
S1D15705 Series
[* Notes]
*1: Represents the gradient of the approximate line of the Typ. output voltages.
*2: Represents the maximum deviation between the output voltage curve and the approximate line.
Assuming that the difference of output voltages at –40°C and at 80°C as ∆VSEN , assuming that the difference
between the approximate line and the output voltage values as ∆DIFF and assuming that the maximum value
thereof as ∆DIFF (MAX), the output voltages linearity ∆VL can be calculated by use of the following equation.
∆DIFF (MAX)
∆VL = ———————— × 100
∆VSEN
Output voltage VSEN [V]
(ON the basis of VDD 0= 0 [V])
∆VDIFF
∆VSEN
= VSEN(–40°C)–VSEN(85°C)
∆VDIFF
Output voltage
Approximate line
The ∆VDIFF which becomes the
maximum point under all the
temperature levels is to be
deemed as the ∆VDIFF (MAX).
∆VDIFF
–50
–25
0
25
50
75
100
Temperature Ta [°C]
*3: Represents the queuing time after the supply voltage SVS is applied to the SVS pin until the output voltage is
stabilized and monitoring thereof becomes feasible. Be sure to sample the output voltage after the prescribed
queuing time has elapsed.
Output voltage characteristics
Output voltage VSEN [V]
(ON the basis of VDD 0= 0 [V])
0
–1
Min.
–2
Typ.
Max.
–3
–4
–5
–50
–25
0
25
50
75
100
Temperature Ta [°C]
10–76
EPSON
Rev. 3.1a
S1D15705 Series
Output Pin Load
Maintain the load capacity CL for the V SEN output pin VSEN at 100pF or less and keep the load resistance RL for the
VSEN output pin VSEN at 1MΩ or more.
In order to obtain accurate output voltage values, be careful not to insert a current flowing channel between the V SS.
VDD
VDD
S1D15705 Series
CL
Rev. 3.1a
RL
VSEN
VSEN
EPSON
10–77
11. S1D15710 Series
Rev. 1.1a
Contents
1. DESCRIPTION ..............................................................................................................................................11-1
2. FEATURES .................................................................................................................................................... 11-1
3. BLOCK DIAGRAM ......................................................................................................................................... 11-2
4. PIN LAYOUT .................................................................................................................................................11-3
5. PIN DESCRIPTION .......................................................................................................................................11-7
6. FUNCTION DESCRIPTION ......................................................................................................................... 11-11
7. COMMAND DESCRIPTION ........................................................................................................................ 11-29
8. COMMAND SETTING ................................................................................................................................. 11-40
9. ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 11-44
10. DC CHARACTERISTICS .............................................................................................................................11-45
11. MICROPROCESSOR (MPU) INTERFACE: REFERENCE ......................................................................... 11-57
12. CONNECTION BETWEEN LCD DRIVERS: REFERENCE ........................................................................11-58
13. LCD PANEL WIRING: REFERENCE ..........................................................................................................11-59
14. TCP PIN LAYOUT ....................................................................................................................................... 11-60
15. TCP DIMENSIONS ......................................................................................................................................11-61
16. TEMPERATURE SENSOR CIRCUIT ..........................................................................................................11-62
–i–
Rev. 1.1a
S1D15710 Series
1. DESCRIPTION
The S1D15710 Series is a single-chip dot matrix liquid
crystal display driver that can be connected directly to
a microprocessor bus. Eight-bit parallel or serial display
data transmitted from the microprocessor is stored in
the internal display data RAM, and the chip generates
liquid crystal drive signals, independently of the
microprocessor.
It has a on-chip 65 × 256-bit display data RAM, and
there is a one-to-one correspondence between the dot
pixel on the liquid crystal panel pixels and internal
RAM bit. This feature ensures implementation of
highly free display.
The S1D15710 Series incorporate 65 common output
circuits and 224 segment output circuits. A single chip
can drive a 65 × 224 dot display (capable of displaying
14 columns × 4 rows with 16 × 16-dot kanji font).
Further, display capacity can be extended by designing
two chips in a master/display configuration.
Since both the S1D15710*10** and S1D15710*11**
have built-in analog temperature sensor circuits, systems
can be build that can maintain appropriate liquid crystal
contrast over a wide temperature range with
microcomputer control without requiring such parts as
thermostats.
The S1D15710 Series can read and write RAM data
with the minimum current consumption because it does
not require any external operation clock. Also it
incorporates a LCD power supply featuring a very low
current consumption, a LCD drive power voltage
regulator resistor and a display clock CR oscillator
circuit. This allows the display system of a highperformance for handy equipment to be realized at the
minimum power consumption and minimum component
configuration.
2. FEATURES
• Direct display of RAM data using the display data
RAM
RAM bit data “1” .... goes on.
“0” .... goes off (at display normal
rotation).
• RAM capacity
65 × 256 = 16,640 bits
• Liquid crystal drive circuit
65 circuits for the common output and 224 circuits
for the segment output
• High-speed 8-bit MPU interface (Both the 80 and 68
series MUPs can directly be connected.)/serial
interface enabled
• Abundant command functions
Display Data Read/Write, Display ON/OFF, Display
Normal Rotation/Reversal, Page Address Set, Display
Start Line Set, column address set, Status Read,
Power Supply Save Display All Lighting ON/OFF,
LCD Bias Set, Read Modify Write, Segment Driver
Direction Select, Electronic Control, V5 Voltage
Adjusting Built-in Resistance Ratio Set, Static
Indicator, n Line Alternating Current Reversal Drive,
Common Output State Selection, and Built-in
Oscillator Circuit ON
• Built-in static drive circuit for indicators (One set,
blinking speed variable)
• Built-in power supply circuit for low power supply
liquid crystal drive
Booster circuit (Boosting magnification - double,
triple, quadruple, boosting reference power supply
external input enabled)
• 3% high accuracy alternating current voltage adjusting
circuit (Temperature gradient: –0.05%/°C)
Built-in V5 voltage adjusting resistor, built-in V1 to
V4 voltage generation split resistors, built-in
electronic control function, and voltage follower
• Built-in CR oscillator circuit (external clock input
enabled)
• Low power consumption
• Built-in temperature sensor circuit (S1D15710D10B*
and S1D15710D11B*)
• Power supplies
Logic power supply: VDD – VSS = 1.8 to 5.5 V
Boosting reference power supply: VDD – VSS = 1.8 to
6.0 V
Liquid crystal drive power supply: V5 – V DD = –4.5
to –18.0 V
• Wide operating temperature range –40 to 85°C
• CMOS process
• Shipping form Bare chip, TCP
• No light-resistant and radiation-resistant design are
provided.
Series specification
Product name
Duty
Bias
SEG Dr
COM Dr
S1D15710D00B*
S1D15710D10B *(*1)
S1D15710D11B *(*2)
S1D15710T00 **
1/65
1/65
1/65
1/65
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/9, 1/7
224
224
224
224
65
65
65
65
VREG temperature
gradient
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
Shipping form
Bare chip
Bare chip
Bare chip
TCP
*1: The built-in power circuit has been upgraded so that liquid crystal displays having big load capacities can be
driven. Check the display and select if the display quality is inadequate even in high power mode of
S1D15710D00B*. There are no methods for supplying liquid crystal drive power externally without using the
built-in power circuit. In that case, select either the S1D15710D10B* or the S1D15710D11B*.
*2: All specificationa are same as those of the S1D15710D11B* except for the temperature sensor circuit.
Rev. 1.1a
EPSON
11–1
S1D15710 Series
COMS
• • • • • • • • • •
COM63
COM0
• • • • • • • • • • • • • • • • • • • • • • • • •
SEG223
SEG0
3. BLOCK DIAGRAM
VSS
V2
V3
SEG Drivers
COMS
VDD
V1
COM Drivers
V4
V5
Shift register
Display data latch circuit
CAP1+
Display timing generator circuit
Line address
VSS2
VR
I/O buffer
VOUT
Page address
CAP2+
CAP2–
CAP3–
Power supply circuit
CAP1–
Display data RAM
256 x 65
VRS
IRS
HPM
FRS
FR
SYNC
CL
DOF
M/S
Oscillator circuit
Column address
Bus holder
Command decoder
CLS
Status
Interface
11–2
EPSON
D0
D1
D2
D3
D4
D5
D6 (SCL)
D7 (SI)
RES
P/S
WR (R/W)
RD (E)
A0
CS2
CS1
MPU
Rev. 1.1a
S1D15710 Series
4. PIN LAYOUT
Chip Specification
117
1
118
417
D157AD0B
S1D15710 Series
Y
Die No.
(As an example
X
(0, 0)
of S1D15710D00B /D11B )
*
*
383
152
153
382
Item
Chip size
Chip thickness
Bump pitch
Bump size
PAD No.1 to 117
PAD No.118
PAD No.119 to 151
PAD No.152
PAD No.153
PAD No.154 to 381
PAD No.382
PAD No.383
PAD No.384 to 416
PAD No.417
Bump height
Rev. 1.1a
Size
X
16.65
85
85
85
85
73
47
73
86
85
85
EPSON
×
0.625
69 (Min.)
×
×
×
×
×
×
×
×
×
×
17 (Typ.)
Y
2.90
85
73
47
73
85
85
85
73
47
73
Unit
mm
mm
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
11–3
S1D15710 Series
PAD Central Coordinates
Unit: µm
PAD
PIN
No.
Name
1
(NC)
2
SYNC
3
FRS
4
TEST1
5
VDD
6
TEST2
7
VSS
8
TEST3
9
VDD
10
TEST4
11
VSS
12
VSS
13
VSS
14
VDD
15
VDD
16
VDD
17
VDD
18
TEST5
19
TEST5
20
TEST6
21
TEST6
22
TEST7
23
TEST7
24
TEST8
25
TEST8
26
TEST9
27
TEST9
28
SYNC
29
FRS
30
FR
31
CL
32
DOF
33
VSS
34
CS1
35
CS2
36
VDD
37
RES
38
A0
39
VSS
40 WR, R/W
41
RD,E
42
VDD
43
D0
44
D1
45
D2
46
D3
47
D4
48
D5
49 D6 (SCL)
50
D7 (SI)
11–4
X
Y
7814
7677
7541
7404
7268
7131
6995
6855
6718
6582
6445
6309
6169
6033
5896
5760
5623
5483
5347
5210
5074
4937
4798
4661
4525
4388
4252
4112
3975
3839
3702
3566
3429
3293
3156
3020
2883
2747
2610
2474
2337
2201
2064
1928
1791
1655
1518
1382
1245
1109
1293
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN
Name
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
CAP3–
(NC)
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
CAP2+
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VDD
TEST10
VSS
TEST11
X
Y
972
1293
838
704
571
437
303
169
35
–99
–233
–367
–501
–635
–768
–902
–1036
–1170
–1304
–1438
–1572
–1706
–1840
–1974
–2107
–2241
–2375
–2509
–2643
–2777
–2911
–3045
–3179
–3313
–3446
–3580
–3714
–3848
–3982
–4116
–4250
–4384
–4518
–4652
–4785
–4919
–5053
–5187
–5321
–5455
–5589
EPSON
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
PIN
Name
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
TEST12
TEST13
TEST14
TEST15
TEST16
(NC)
(NC)
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
X
Y
–5723 1293
–5859
–5996
–6132
–6269
–6405
–6542
–6678
–6815
–6951
–7088
–7224
–7361
–7510
–7630
–7750
–7869
–8148 1295
1209
1137
1064
991
919
846
773
701
628
555
483
410
337
265
192
119
47
–26
–99
–171
–244
–317
–389
–462
–535
–607
–680
–753
–825
–898
–971
–1043
Rev. 1.1a
S1D15710 Series
Unit: µm
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PIN
Name
COMS
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
Rev. 1.1a
X
Y
–8148 –1116
–1201
–7906 –1293
–7823
–7754
–7685
–7616
–7547
–7478
–7409
–7340
–7271
–7202
–7133
–7064
–6995
–6926
–6857
–6788
–6719
–6650
–6581
–6512
–6442
–6373
–6304
–6235
–6166
–6097
–6028
–5959
–5890
–5821
–5752
–5683
–5614
–5545
–5476
–5407
–5338
–5269
–5200
–5131
–5062
–4993
–4924
–4855
–4786
–4717
–4648
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
PIN
Name
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
X
Y
–4579 –1293
–4510
–4441
–4372
–4303
–4234
–4164
–4095
–4026
–3957
–3888
–3819
–3750
–3681
–3612
–3543
–3474
–3405
–3336
–3267
–3198
–3129
–3060
–2991
–2922
–2853
–2784
–2715
–2646
–2577
–2508
–2439
–2370
–2301
–2232
–2163
–2094
–2025
–1956
–1886
–1817
–1748
–1679
–1610
–1541
–1472
–1403
–1334
–1265
–1196
EPSON
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
PIN
Name
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
X
Y
–1127 –1293
–1058
–989
–920
–851
–782
–713
–644
–575
–506
–437
–368
–299
–230
–161
–92
–23
46
115
184
253
322
391
461
530
599
668
737
806
875
944
1013
1082
1151
1220
1289
1358
1427
1496
1565
1634
1703
1772
1841
1910
1979
2048
2117
2186
2255
11–5
S1D15710 Series
Unit: µm
PAD
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
11–6
PIN
Name
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
SEG168
SEG169
SEG170
SEG171
SEG172
SEG173
SEG174
SEG175
SEG176
SEG177
SEG178
SEG179
SEG180
SEG181
SEG182
SEG183
SEG184
SEG185
SEG186
SEG187
SEG188
SEG189
SEG190
SEG191
SEG192
SEG193
SEG194
X
Y
2324 –1293
2393
2462
2531
2600
2669
2739
2808
2877
2946
3015
3084
3153
3222
3291
3360
3429
3498
3567
3636
3705
3774
3843
3912
3981
4050
4119
4188
4257
4326
4395
4464
4533
4602
4671
4740
4809
4878
4947
5017
5086
5155
5224
5293
5362
5431
5500
5569
5638
5707
PAD
No.
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
PIN
Name
SEG195
SEG196
SEG197
SEG198
SEG199
SEG200
SEG201
SEG202
SEG203
SEG204
SEG205
SEG206
SEG207
SEG208
SEG209
SEG210
SEG211
SEG212
SEG213
SEG214
SEG215
SEG216
SEG217
SEG218
SEG219
SEG220
SEG221
SEG222
SEG223
(NC)
(NC)
(NC)
(NC)
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
X
Y
5776 –1293
5845
5914
5983
6052
6121
6190
6259
6328
6397
6466
6535
6604
6673
6742
6811
6880
6949
7018
7087
7156
7225
7294
7364
7433
7502
7571
7640
7709
7778
7847
7930
8148 –1201
–1116
–1043
–971
–898
–825
–753
–680
–607
–535
–462
–389
–317
–244
–171
–99
–26
47
EPSON
PAD
No.
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
PIN
Name
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
(NC)
X
Y
8148
119
192
265
337
410
483
555
628
701
773
846
919
991
1064
1137
1209
1295
Rev. 1.1a
S1D15710 Series
5. PIN DESCRIPTION
Power Supply Pin
Pin name
I/O
Description
Number of
pins
VDD
Power
supply
Commonly used with the MPU power supply pin V CC.
12
VSS
Power
supply
0 V pin connected to the system ground (GND)
9
VSS2
Power
supply
Boosting circuit reference power supply for liquid crystal drive
5
VRS
Power
supply
External input pin for liquid crystal power supply voltage
adjusting circuit
They are set to OPEN
2
Power
supply
Multi-level power supply for liquid crystal drive. The voltage
specified according to liquid crystal cells is impedance-converted
by a split resistor or operation amplifier (OP amp) and applied.
The potential needs to be specified based on V DD to establish the
relationship of dimensions shown below:
V1, V2
V3, V4
V5
10
VDD (=V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master operation When the power supply is ON, the following
voltages are applied to V1 ~ V4 from the built-in power supply
circuit. The selection of the voltages is determined using the LCD
bias set command.
V1
V2
V3
V4
1/9•V5
2/9•V5
7/9•V5
8/9•V5
1/7•V5
2/7•V5
5/7•V5
6/7•V5
LCD Power Supply Circuit Pin
Pin name
I/O
Description
Number of
pins
CAP1+
O
Boosting capacitor positive side connecting pin. Connects
a capacitor between the pin and CAP1– pin.
2
CAP1–
O
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP1+ pin.
2
CAP2+
O
Boosting capacitor positive side connecting pin. Connects
a capacitor between the pin and CAP2– pin.
2
CAP2–
O
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP2+ pin.
2
CAP3–
O
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP1+ pin.
2
I/O
Boosting output pin. Connects a capacitor between the pin and V SS2.
2
I
Voltage adjusting pin. Applies voltage between VDD and V5 using
a split resistor.
Valid only when the V 5 voltage adjusting built-in resistor is not used
(IRS=LOW)
Do not use VR when the V5 voltage adjusting built-in resistor is
used (IRS=HIGH)
1
VOUT
VR
Rev. 1.1a
EPSON
11–7
S1D15710 Series
System Bus Connecting Pins
Pin name
I/O
D7 to D0
(SI)
(SCL)
I/O
A0
I
RES
I
CS1
CS2
RD
(E)
I
WR
(R/W)
I
FRS
O
C86
I
P/S
I
I
Number of
pins
Description
An 8-bit bidirectional data bus is used to connect an 8-bit or 16-bit
standard MPU data bus.
When the serial interface is selected (P/S=LOW),
D7: Serial data entry pin (SI)
D6: Serial clock input pin (SCL)
In this case, D0 to D5 are set to high impedance.
When Chip Select is in the non-active state, D0 to D7 are set to
high impedance.
Normally the lowest order bit of the MPU address bus is connected
to discriminate data / commands.
A0=HIGH: Indicates that D0 to D7 are display data.
A0=LOW: Indicates that D0 to D7 are control data.
Initialized by setting RES to LOW.
Reset operation is performed at the RES signal level.
Chip Select signal. When CS1=LOW and CS2=HIGH, this signal
becomes active and the input/output of data/commands is enabled.
• When the 80 series MPU is connected, active LOW is set.
Pin that connects the RD signal of the 80 series MPU. When this
signal is LOW, the S1D15710 series data bus is set in the output state.
• When the 68 series MPU is connected, active HIGH is set.
68 series MPU enable clock input pin
• When the 80 series MPU is connected, active LOW is set.
Pin that connects the WR signal of the 80 series MPU. The data
bus signal is latched on the leading edge of the WR signal.
• When the 68 series MPU is connected,
Read/write control signal input pin
R/W=HIGH: Read operation
R/W=LOW: Write operation
Output pin for static drive
Used together with the SYNC pin
MPU interface switching pin
C86=HIGH: 68 series MPU interface
C86=LOW: 80 series MPU interface
Switching pin for parallel data entry/serial data entry
P/S=HIGH: Parallel data entry
P/S=LOW: Serial data entry
According to the P/S state, the following table is given.
P/S
Data/
command
Data
Read/write
HIGH
A0
D0 to D7
RD, WR
LOW
A0
SI (D7)
Write-only
8
1
1
2
1
1
1
1
1
Serial clock
SCL (D6)
When P/S=LOW, D0 to D5 are set to high impedance. D0 to D5 can
be HIGH, LOW, or “OPEN”.
RD(E) and WR (R/W) are fixed to HIGH or LOW.
For the serial data entry, RAM display data cannot be read.
11–8
EPSON
Rev. 1.1a
S1D15710 Series
Pin name
I/O
Description
Number of
pins
1
CLS
I
Pin that selects the validity/invalidity of the built-in oscillator circuit
for display clocks.
CLS=HIGH: Built-in oscillator circuit valid
CLS=LOW: Built-in oscillator circuit invalid (external input)
When CLS=LOW, display clocks are input from the CL pin.
When the S1D15710 series is used for the master/slave
configuration, each of the CLS pins is set to the same level together.
Display clock
Master
Slave
Built-in oscillator circuit used
HIGH
HIGH
External input
LOW
LOW
M/S
I
Pin that selects the master/slave operation for the S1D15710 series.
The liquid crystal display system is synchronized by outputting the
timing signal required for the liquid crystal display for the master
operation and inputting the timing signal required for the liquid
crystal display for the slave operation.
M/S=HIGH: Master operation
M/S=LOW: Slave operation
According to the M/S and CLS states, the following table is given.
M/S CLS Oscillator Power supply CL
FR SYNC FRS DOF
circuit
circuit
HIGH HIGH Valid
Valid
Output Output Output Output Output
LOW Invalid
Valid
Input Output Output Output Output
LOW HIGH Invalid
Invalid
Input Input Input Output Input
LOW Invalid
Invalid
Input Input Input Output Input
1
CL
I/O
Display clock I/O pin
According to the M/S and CLS states, the following table is given.
M/S CLS
CL
HIGH HIGH Output
LOW Input
LOW HIGH Input
LOW Input
1
FR
I/O
SYNC
I/O
DOF
I/O
IRS
I
HPM
I
Rev. 1.1a
When the S1D15710 series is used for the master/slave
configuration, each CL pin is connected.
Liquid crystal alternating current signal I/O pin
M/S=HIGH: Output
M/S=LOW: Input
When the S1D15710 series is used for the master/slave
configuration, each FR pin is connected.
Liquid crystal synchronizing current signal I/O pin
M/S=HIGH: Output
M/S=LOW: Input
When the S1D15710 series is used for the master/slave
configuration, each SYNC pin is connected.
Liquid crystal display blanking control pin
M/S=HIGH: Output
M/S=LOW: Input
When the S1D15710 series is used for the master/slave
configuration, each DOF pin is connected.
V 5 voltage adjusting resistor selection pin
IRS=HIGH: Built-in resistor used
IRS=LOW: Built-in resistor not used. The V5 voltage is adjusted by
the V R pin and stand-alone split resistor.
Valid only at master operation. The pin is fixed to HIGH or LOW at
slave operation.
Power supply control pin of the power supply circuit for liquid
crystal drive
HPM=HIGH: Normal mode
HPM=LOW: High power supply mode
Valid only at master operation. The pin is fixed to HIGH or LOW at
slave operation.
EPSON
1
2
1
1
1
11–9
S1D15710 Series
Liquid Crystal Drive Pin
Pin name
SEG0
to
SEG223
I/O
O
COM0
to
COM63
Output pins for the LCD segment drive. Contents of the display
RAM and FR signal are combined to select a desired level among
VDD, V2, V3 and V5.
RAM data
FR
HIGH
HIGH
LOW
LOW
Power save
HIGH
LOW
HIGH
LOW
—
O
224
Output voltage
Display
Display reversal
normal operation
VDD
V2
V5
V3
V2
VDD
V3
V5
VDD
Output pins for the LCD common drive. Scan data and FR signal
are combined to select a desired level among VDD, V1, V4 and V5.
Scanning data
HIGH
HIGH
LOW
LOW
Power save
COMS
Number of
pins
Description
FR
HIGH
LOW
HIGH
LOW
—
64
Output voltage
V5
VDD
V1
V4
VDD
Indicator dedicated COM output pin
Set to OPEN when not used
When COMS is used for the master/slave configuration, the same
signal is output to both the master and slave.
2
Test Pin
Pin name
I/O
TEST1 ~ 4
I/O
TEST10
I
Description
Number of
pins
Fix the pin to HIGH.
To use a built-in temperature sensor circuit in the S1D15710*00**/
S1D15710*11**, see 16, Temperature Sensor Circuit.
4
Fix it to HIGH for the S1D15710*00**/S1D15710*11**; fix it to
LOW for S1D15710*10**.
1
TEST11~13
I/O
IC chip test pin. Fix the pin to HIGH.
3
TEST5 ~ 9,
14 ~ 16
I/O
IC chip test pin. Take into consideration so that the capacity of
lines cannot be exhausted by setting the pin to OPEN.
13
11–10
EPSON
Rev. 1.1a
S1D15710 Series
6. FUNCTION DESCRIPTION
MPU Interface
Selection of interface type
The S1D15710 series transfers data through 8-bit bidirectional data buses (D7 to D0) or serial data input (SI). By setting
the polarity of the P/S pin to either HIGH or LOW, the 8-bit parallel data entry or serial data entry can be selected as
listed in Table 1.
CS1
CS2
Table 1
A0
RD
HIGH: Parallel data entry
CS1
CS2
A0
LOW: Serial data entry
CS1
CS2
A0
—
—
—
SI
SCL
(HZ)
Fix — to HIGH or LOW . HZ indicates the high impedance state.
P/S
RD
WR
C86
D7
D6
D5 to D0
WR
C86
D7
D6
D5 to D0
Parallel interface
When the parallel interface is selected (P/S=HIGH), the S1D15705 series can directly be connected to the MPU bus
of either the 80 or 68 series MPU by setting the C86 pin to HIGH or LOW as listed in Table 2.
C86
CS1
Table 2
CS2
A0
RD
WR
D7 to D0
HIGH: 68 series MPU bus CS1
CS2
A0
E
R/W
D7 to D0
LOW: 80 series MPU bus CS1
CS2
A0
RD
WR
D7 to D0
In addition, the data bus signal can be identified according to the combinations of the A0, RD (E), WR (R/W) signals
as listed in Table 3.
Table 3
80 series
Common
68 series
A0
R/W
RD
WR
1
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
Rev. 1.1a
EPSON
Function
Display data read
Display data write
Status read
Control data write (command)
11–11
S1D15710 Series
converted into 8-bit parallel data on the leading edge of
the 8th serial clock, then processed.
Whether to identify that the serial data entry is display
data or command is judged by the A0 input, and
A0=HIGH indicates display data and A0=LOW indicates
the command. After the chip is set to the non-active
state, the A0 input is read and identified at the timing on
the 8 × n-th leading edge of the serial clock. Figure 1
shows the signal chart of the serial interface.
Serial interface
When the serial interface is selected (P/S=LOW), the
serial data entry (SI) and serial clock input(SCL) can be
accepted with the chip in the non-active state (CS1=LOW
or CS2=HIGH. The serial interface consists of an 8-bit
shift register and a 3-bit counter. Serial data is fetched
from the serial data entry pin in the order of D7, D6, ....,
and D0 on the leading edge of the serial clock and
CS1
CS2
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
D5
D4
D3
D2
13
14
SCL
11
12
A0
Figure 1
• When the chip is in the non-active state, both the shift register and counter are reset to the initial state.
• Cannot be read for the serial interface.
• For the SCL signal, pay careful attention to the terminating reflection of lines and external noise. The operation
confirmation using actual equipment is recommended.
Chip select
The S1D15710 series has two chip select pins CS1 and
CS2 and enables the MPU interface or serial interface
only when CS1=LOW and CS2=HIGH.
When Chip Select is in the non-active state, D0 to D7 are
in the high impedance state and the A0, RD, and WR
inputs become invalid. When the serial interface is
selected, the shift register and counter are reset.
Display data RAM and internal register
access
Since the S1D15710 series access viewed from the
MUP side satisfies the cycle time and does not require
the wait time, high-speed data transfer is enabled.
The S1D15710 series performs a kind of inter-LSI
pipeline processing through the bus holder attached to
the internal data bus when it performs the data transfer
with the MPU.
For example, when data is written on the display data
RAM, the data is first held in the bus holder and written
11–12
on the display data RAM up to the next data write cycle.
Further, when the MPU reads the contents of display
data RAM, the read data at the first data read cycle
(dummy) is held in the bus holder and read on the system
bus from the bus holder up to the next data read cycle.
The read sequence of the display data RAM is restricted.
When the address is set, note that the specified address
data is not output to the subsequent read instruction and
output at the second data read. Therefore single dummy
read is required after the address set and write cycle.
Figure 2 shows this relationship.
Busy flag
When the busy flag is “1”, it indicates that the S1D15710
series is performing an internal operation, and only the
status read instruction can be accepted. The busy flag is
output to the D7 pin using the status read command. If
the cycle time (tCYC) is ensured, the MPU throughput
can be improved greatly since this flag needs not be
checked before each command.
EPSON
Rev. 1.1a
S1D15710 Series
Internal timing
MPU
• Write
WR
DATA
N
N+1
N+2
N+3
Latch
N+1
N
BUS Holder
N+2
N+3
Write Signal
• Read
MPU
WR
RD
Internal timing
DATA
N
N
n
n+1
Address Preset
Read Signal
Column Address
Preset N
Bus Holder
Increment N+1
N
Address Set
#n
n
Dummy
Read
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
Figure 2
Rev. 1.1a
EPSON
11–13
S1D15710 Series
Display Data RAM
Display data RAM
This display data RAM stores display dot data and
consists of 65 (8 pages × one 8 bit + 1) × 256 bits.
Desired bits can be accessed by specifying page and
column addresses.
Since the MPU display data D7 to D0 correspond to the
common direction of the liquid crystal display, the
restrictions at display data transfer is reduced and the
display configuration with the high degree of freedom
can easily be obtained when the S1D15710 series is
used for the multiple chip configuration.
Besides, the read/write operation to the display data
RAM is performed through the I/O buffer from the
MPU side independently of the liquid crystal drive
signal read. Therefore even when the display data RAM
is asynchronously accessed during liquid crystal display,
the access will not have any adverse effect on the
display such as flickering.
D0
0 1 1 1
0
COM0
D1
1 0 0 0
0
COM1
D2
0 0 0 0
0
COM2
D3
0 1 1 1
0
COM3
D4
1 0 0 0
0
COM4
—
—
Display data RAM
Liquid crystal display
Figure 3
Page address circuit
As shown in Figure 4, the page address of the display
data RAM is specified using the page address set
command. To access the data using a new page, the page
address is respecified.
The page address 8 (D3,D2,D1,D0=1,0,0,0) is an
indicator dedicated RAM area and only the display data
D0 is valid.
Column address circuit
As shown in Figure 4, the display data RAM column
address is specified by the Column Address Set
command. The specified column address is incremented
by +1 at every input of display data read/write command.
This allows the MPU to access the display data
continuously.
Incrementation of the column address is stopped by
FFH. When display data is accessed continuously, the
column address continues to specify the FFH after
access of the FFH. It should be noted that the column
address FFH display data is accessed repeatedly. The
column address and page address are independent of
each other. Therefore, when shifting from the column
of page 0 to the column of page 1, for example, it is
necessary to specify each of the page address and
column address again.
11–14
Furthermore, as shown in Table 4, the AD command
(segment driver direction select command) can used to
reverse the correspondence between the display data
RAM column address and segment output. This allows
constraints on IC layout to be minimized at the time of
LCD module assembling.
Table 4
SEG output
SEG0
SEG223
ADC
“0”
0 (H)→ Column Address→ DF (H)
(D0)
“1”
FF (H)←Column Address← 20 (H)
Line address circuit
When displaying contents of the display data RAM, the
line address circuit is used for specifying the
corresponding addresses. See Figure 4. Using the
display start line address set command, the top line is
normally selected (when the common output state is
normal, COM0 is output. And, when reversed outputs
COM63). For the display area of 65 lines is secured
starting from the specified display start line address in
the address incrementing direction.
Dynamically changing the line address using the display
start line address set command enables screen scrolling
and page change.
EPSON
Rev. 1.1a
S1D15710 Series
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
SEG0 FF 00
SEG1 FE 01
SEG2 FD 02
SEG3 FC 03
SEG4 FB 04
SEG5 FA 05
SEG6 F9 06
SEG7 F8 07
0
Page 0
64 lines
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Start
1 0
D0 D0
ADC
Column
Address
0
Line
output state:
Address Normal rotation
LCD
Out
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D8
D9
DA
DB
DC
DD
DE
DF
0
When setting the display start line to one channel
27
26
25
24
23
22
21
20
0
Common
Data
SEG218
SEG217
SEG218
SEG219
SEG220
SEG221
SEG222
SEG223
Page Address
D3
D2
D1
D0
COM
Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
The 65th line
is accessed
independently
of the display
start line address.
Figure 4
Rev. 1.1a
EPSON
11–15
S1D15710 Series
Display data latch circuit
The display data latch circuit is a latch that temporarily
stores the display data output from the display data
RAM to the liquid crystal drive circuit.
Since the Display Normal Rotation/Reversal, Display
ON/OFF, and Display All Lighting ON/OFF commands
control the data in this latch, the data within the display
data RAM is not changed.
Oscillator Circuit
This oscillator circuit is a CR type oscillator and generates
display clocks. The oscillator circuit is valid only when
M/S=HIGH and CLS=HIGH and starts oscillation after
the Built-in Oscillator Circuit ON command is entered.
When CLS=LOW, the oscillation is stopped and the
display clocks are entered from the CL pin.
Display Timing Generator Circuit
This display timing generator circuit generates timing
signals from the display clocks to the line address circuit
and the display latch circuit. It latches the display data
to the display data latch circuit and outputs it to the
segment drive output pin by synchronizing to the display
clocks. The read operation of display data to the liquid
crystal drive circuit is completely independent of the
access to the display data RAM from the MPU. Therefore
even when the display data RAM is asynchronously
accessed during liquid crystal display, the access will
not have any adverse effect on the display such as
flickering.
The circuit also generates the internal common timing,
liquid crystal alternating current signal (FR), and
synchronous signal (SYNC) from the display clocks.
As shown in Figure 5, the FR normally generates the
drive waveforms in the 2-frame alternating current
drive system to the liquid crystal drive circuit. It can
generate n-line reversal alternating current drive
waveforms by setting data (n-1) to the n-line reversal
drive register. If a display quality problem such as
crosstalk occurs, it can be improved by using the n-line
reversal alternating current drive waveforms. Determine
the number of lines (n) to which alternating current is
applied by actually displaying the liquid crystal.
SNYC is a signal that synchronizes the line counter and
common timing generator circuit to the SYNC signal
output side IC. Therefore the SYNC signal becomes a
waveform at a duty ratio of 50% that synchronizes to the
frame synchronization.
When the S1D15710 series is used for the multiple chip
configuration, the slave side needs to supply the display
timing signals (FR, SYNC, CL, and DOF) from the
master side.
Table 5 shows the state of FR, SYNC, CL, or DOF.
Table 5
Operation mode
Built-in oscillator circuit valid (CLS=HIGH)
Built-in oscillator circuit invalid (CLS=LOW)
Built-in oscillator circuit valid (CLS=HIGH)
Built-in oscillator circuit invalid (CLS=LOW)
Master
(M/S=HIGH)
Slave
(M/S=LOW)
FR
Output
Output
Input
Input
SYNC
Output
Output
Input
Input
CL
Output
Input
Input
Input
DOF
Output
Output
Input
Input
2-frame alternating current drive waveforms
64 65 1
2
3
4
5
6
60 61 62 63 64 65 1
2
3
4
5
6
CL
SYNC
FR
VDD
V1
COM0
V4
V5
VDD
V1
COM1
V4
V5
RAM
DATA
VDD
V2
SEGn
V3
V5
Figure 5
11–16
EPSON
Rev. 1.1a
S1D15710 Series
n-line reversal alternating current drive waveforms (Example of n=5: when the line reversal
register is set to 4)
64 65 1
2
3
4
5
6
60 61 62 63 64 65 1
2
3
4
5
6
CL
SYNC
FR
VDD
V1
COM0
V4
V5
VDD
V1
COM1
V4
V5
RAM
DATA
VDD
V2
SEGn
V3
V5
Figure 6
Common Output State Selection Circuit
Liquid Crystal Drive Circuit
The S1D15710 series can set the scanning direction of
the COM output using the common output state selection
command (see Figure 6). Therefore the IC assignment
restrictions at LCD module assembly are reduced.
This liquid crystal drive circuit is 289 sets of mutiplexers
that generate quadruple levels for liquid crystal drive. It
outputs the liquid crystal drive voltage that corresponds
to the combinations of the display data, COM scanning
signal, and FR signal.
Figure 6 shows examples of the SEG and COM output
waveforms.
Table 6
State
COM scanning direction
Normal rotation
COM 0
→
COM 63
Reversal
COM 63
→
COM 0
Rev. 1.1a
EPSON
11–17
S1D15710 Series
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
FR
VDD
VSS
COM0
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
COM1
COM2
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
SEG0
SEG1
SEG2
COM0–SEG0
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
COM0–SEG1
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
Figure 7
11–18
EPSON
Rev. 1.1a
S1D15710 Series
Power Supply Circuit
This power supply circuit is a low power supply
consumption one that generates the voltage required for
the liquid crystal drive and consists of a boosting circuit,
voltage adjusting circuit, and voltage follower circuit. It
is valid only at master operation.
The power supply circuit ON/OFF controls the boosting
circuit, voltage adjusting circuit, and voltage follower
circuit using the power supply control set command,
respectively.
Therefore, it can also use the partial functions of the
external power supply and built-in power supply
together. Table 7 lists the functions that control 3-bit
data using the power control set command and Table 8
lists the reference combinations.
Table 7 Description of controlling bits using the power control set command
State
Item
“1”
“0”
D2 Boosting circuit control bit
ON
OFF
D1 Voltage adjusting circuit (V adjusting circuit) control bit
ON
OFF
D0 Voltage follower circuit (V/F circuit) control bit
ON
OFF
Table 8 Reference combinations
Boosting V adjusting V/F
External
Boosting
D1
D0
circuit
circuit
circuit voltage input system pin
Status of use
D2
1
Built-in power
supply used
1
1
1
O
O
O
VSS2
Used
2
V adjusting circuit
and V/F circuit only
0
1
1
X
O
O
VOUT, VSS2
OPEN
3
V/F circuit only
0
0
1
X
X
O
V5, VSS2
OPEN
External power
0
0
0
X
X
X
V1 to V5
OPEN
supply only
• The boosting system pin indicates the CAP1+, CAP1–, CAP2+, CAP2–, or CAP3– pin.
• Although the combinations other than those listed in the above table are also possible, they cannot be recommended
because they are not actual use methods.
4
Boosting circuit
The boosting circuit incorporated in the S1D15710
series enables the quadruple boosting, triple boosting,
and double boosting of the V DD – VSS2 potential.
For the quadruple boosting, the VDD ↔ VSS2 potential
is quadruple-boosted to the negative side and output to
the V OUT pin by connecting the capacitor C1 between
CAP1+↔and CAP1–, between CAP2+↔ and CAP2–,
between CAP1+↔ and CAP3–, and between VSS2↔
and VOUT.
For the triple boosting, the VDD ↔ V SS2 potential is
Rev. 1.1a
triple-boosted to the negative side and output to the
V OUT pin by connecting the capacitor C1 between
CAP1+↔ and CAP1–, between CAP2+↔ and CAP2–,
and between VSS2 ↔ and V OUT and strapping both
CAP3– and VOUT pins.
For the double boosting, the V DD ↔ VSS2 potential is
doubly boosted to the negative side and output to the
V OUT pin by connecting the capacitor C1 between
CAP1+↔ and CAP1–, and between VSS2↔, setting
CAP2+ to OPEN, and V OUT and strapping CAP2–,
CAP3–, and VOUT pins.
Figure 8 shows the relationships of boosting potential.
EPSON
11–19
S1D15710 Series
VSS2
+
C1
C1
C1
VOUT
CAP3–
CAP3–
CAP3–
CAP1+
C1
CAP1+
+
C1
CAP1–
CAP2–
C1
S1D15710
VOUT
S1D15710
VOUT
C1
+
VSS2
+
CAP1+
+
C1
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
OPEN CAP2+
S1D15710
VSS2
+
C1
+
CAP2+
Quadruple boosting circuit
+
Triple boosting circuit
VDD = 0V
VDD = 0V
VSS2 = –3V
VSS2 = –3V
Double boosting circuit
VDD = 0V
VSS2 = –5V
VOUT = 3 x VSS2 = –9V
VOUT = 2 x VSS2 = –10V
VOUT = 4 x VSS2 = –12V
Quadruple boosting
potential relationship
Triple boosting
potential relationship
Double boosting
potential relationship
Figure 8
• Set the V SS2 ” voltage range so that the voltage of the VOUT pin cannot exceed the absolute maximum ratings.
Voltage adjusting circuit
The boosting voltage generated in VOUT outputs the
liquid crystal drive voltage V5 through the voltage
adjusting circuit.
Since the S1D15710 series incorporates a high-accuracy
constant power supply, 64-step electronic control
function, and V5 voltage adjusting resistor, a highaccuracy voltage adjusting circuit can eliminate and
save parts.
(A) When using the V5 voltage adjusting built-in resistor
The liquid crystal power supply voltage V5 can be
controlled only using the command without an
external resistor and the light and shade of liquid
crystal display be adjusted by using the V5 voltage
adjusting built-in resistor and the electronic control
function.
The V 5 voltage can be obtained according to
Expression A-1 within the range of |V5 |<|VOUT|.
Rb 

V5 = 1 +
⋅ VEV

Ra 
α 
Rb  

= 1+
⋅ 1–
⋅ VREG

Ra   162 
(Expression A-1)
[ΘV = (1 − α 162) ⋅ V ]
EV
11–20
EPSON
REG
Rev. 1.1a
S1D15710 Series
VDD
VEV (Constant voltage source
+ electronic control)
Built-in Ra
+
V5
–
Built-in Rb
Figure 9
VREG is a constant voltage source within an IC, and the
value at Ta=25°C is constant as listed in Table 9.
Device
Table 9
Temperature Unit
gradient
Internal
power supply
–0.05
[%/°C]
VREG
Unit
–2.1
[V]
Rb/Ra indicates the V 5 voltage adjusting built-in
resistance ratio and can be adjusted into eight steps
using the V5 voltage adjusting built-in resistance ratio
set command. The reference values of the (1+Rb/Ra)
ratio are obtained as listed in Table 11 by setting 3-bit
data in the V5 voltage adjusting built-in resistance ratio
register.
Table 11 (Reference values)
Register
α indicates an electronic control command value. Setting
data in a 6-bit electronic control register enters one state
among 64 states. Table 10 lists the values of α based on
the setup of the electronic control register.
Table 10
D2
D1
D2
D1
D0
–0.05
0
0
0
4.5
0
0
1
5.0
D0
α
0
1
0
5.5
0
0
63
0
1
1
6.0
0
0
1
62
1
0
0
6.5
0
1
0
1
0
1
7.0
1
1
0
7.6
1
1
1
8.1
D5
D4
D3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
61
··
·
2
1
1
1
1
1
0
1
1
1
1
1
1
1
0
··
·
Rev. 1.1a
Device per temperature
gradient [Unit: %/ °C]
For the internal resistance ratio, a manufacturing
dispersion of up to ±7% should be taken into account.
When not within the tolerance, adjust the V5 voltage by
externally mounting Ra and Rb.
Figure 10 show the V 5 voltage reference values per
temperature gradient device based on the values of the
V5 voltage adjusting built-in resistance ratio register
and electronic control register at Ta=25°C.
EPSON
11–21
S1D15710 Series
–18
–17
S1D15710*****
–16
1 1 1
–15
1 1 0
–14
1 0 1
–13
1 0 0
–12
0 1 1
–11
0 1 0
–10
0 0 1
V5 [v]
–9
0 0 0
–8
–7
–6
–5
V5 voltage adjusting
built-in resistance
ratio registers
(D2, D1, and D0)
–4
–3
–2
–1
0
00H
30H
18H
Figure 10 S1D15710
*****
Electric Volume
Resister
3FH
Temperature gradient = –0.05%/°C
V5 voltage based on the values of V5 voltage adjusting built-in resistance ratio register and electronic
control register
<Setting example: When setting V5 = –9 V at Ta=25°C>
From Figure 8 and Expression A-1.
Table 12
Register
Description
D5
D4
D3
D2
D1
D0
V5 voltage adjusting
–
–
–
0
1
0
electronic control
1
0
0
1
0
1
In this case, Table 13 lists the V5 voltage variable range and pitch width using the electronic control function.
V5
Variable range
Pitch width
11–22
Table 13
Typ.
Min.
–11.6
to
–9.3
67
EPSON
to
Max.
Unit
–7.1
[V]
[mV]
Rev. 1.1a
S1D15710 Series
The V5 voltage can be obtained from Expression B1 by setting the external resistors Ra’ and Rb’
within the range of |V5| < |VOUT|.
(B) When using the external resistor (not using the V 5
voltage adjusting built-in resistor) 1
The liquid crystal power supply voltage V 5 can
also be set by adding the resistors (Ra’ and Rb’)
between V DD and V R and between V R and V 5
without the V 5 voltage adjusting built-in resistor
(IRS pin=LOW). Also in this case, the liquid crystal
power supply voltage V5 can be controlled using
the command and the light and shade of liquid
crystal display can be adjusted by using the
electronic control function.
Rb' 

V5 = 1 +
⋅ VEV

Ra' 
Rb'  
α 

= 1+
⋅ 1–
⋅ VREG

Ra'   162 
(Expression B-1)
[ΘV = (1 − α 162) ⋅ V ]
EV
REG
VDD
VEV (Constant voltage source
+ electronic control)
Stand-alone Ra'
+
V5
–
VR
Stand-alone Rb
Figure 11
<Setting example: When setting V5=–9 V at Ta=25°C>
Also, suppose the current applied to Ra’ and Rb’ is 5µA.
(Expression B-2)
Ra' + Rb' = 1.8 MΩ
It follows that
Therefore from Expressions B-2 and B-3, we have
Set the value of the electronic control register as the
intermediate value (D5, D4, D3, D2, D1, D0) =
(1,0,0,0,0,0). From the foregoing we can establish the
expression:
α = 31
VREG = –2.1V
Rb'
= 4.3
Ra'
Ra' = 340 kΩ
From Expression B-1, it follows that
Rb' = 1460 kΩ
α 
Rb'  

V5 = 1 +
⋅ 1−
⋅ VREG (Expression B-2)

Ra'   162 
In this case, Table 14 lists the V5 voltage variable range
and pitch width using the electronic control function.
31 
Rb'  

−9V = 1 +
⋅ 1−
⋅ ( −2.1)

Ra'   162 
V5
Variable range
Table 14
Typ.
Min.
–11.1
to
–9.0
Pitch width
to
67
(C) When using the external resistor (not using the V5
voltage adjusting built-in resistor) 2
In the use of the above-mentioned external resistor,
the liquid crystal power supply voltage V5 can also
be set by adding the resistors to finely adjust Ra’
and Rb’. Also in this case, the liquid crystal power
supply voltage V5 can be controlled using the
command and the light and shade of liquid crystal
display can be adjusted by using the electronic
control function.
EPSON
Unit
–6.8
[V]
[mV]
The V5 voltage can be obtained from the following
expression C-1 by setting the external resistors R1,
R2 (variable resistors), and R3 within the range of
|V 5| < |VOUT| and finely adjusting R2 (∆R2).

R + R2 − ∆R2 
V5 = 1 + 3
⋅ VEV
R1 + ∆R2 


R + R2 − ∆R2  
α 
= 1 + 3
⋅ 1–
⋅ VREG
R1 + ∆R2   162 

[ΘV = (1 − α 162) ⋅ V ]
EV
Rev. 1.1a
Max.
REG
(Expression C-1)
11–23
S1D15710 Series
VDD
VEV (Constant voltage source
+ electronic control)
Ra' Stand-alone R1
+
Stand-alone R2
V5
∆R2
–
VR
Rb' Stand-alone R3
Figure 12
<Setting example: When setting V5 =–7 to –11 V at Ta=25°C>
Set the value of the electronic control register as the
intermediate value (D5, D4, D3, D2, D1, D0) =
(1,0,0,0,0,0). From the foregoing we can establish the
expression:
Also, suppose the current applied between VDD and V5
is 5µA.
R1 + R2 + R3 = 1.8 MΩ
(Expression C-4)
It follows that
Therefore from Expressions C-2, C-3, and C-4, we have
α = 31
VREG = −2.1V
R1 = 162 kΩ
When ∆R2=0Ω, to obtain V5=–9 V from Expression C1, it follows that
R2 = 278kΩ
R3 = 1363kΩ

R + R2  
31 
−11V = 1 + 3
⋅ 1−
⋅ ( −2.1)
R1   162 

At this time, the V5 voltage variable range and notch
width based on electronic volume function are given in
the following Table when V5=–9 V by R2 is assumed:
(Expression C-2)
When ∆R2=R2, to obtain V5=–7V, it follows that

R3  
31 
−7V = 1 +
⋅ ( −2.1)
⋅ 1−
R1 + R2   162 

(Expression C-3)
V5
Variable range
Table 15
Typ.
Min.
–11.1
to
–9.0
Pitch width
to
67
Max.
Unit
–6.8
[V]
[mV]
• When using the V5 voltage adjusting built-in resistor or electronic control function, the state where at least the V5
voltage adjusting circuit and voltage follower circuit are operated together needs to be set using the power control
set command. Also when the boosting circuit is OFF, the voltage needs to be applied from V OUT.
• The VR pin is valid only when the V5 voltage adjusting built-in resistor (IRS pin=LOW). Set the V R pin to OPEN
when using the V 5 voltage adjusting built-in resistor (IRS pin=HIGH).
• Since the VR pin has high input impedance, noise must be taken into consideration such as for short and shielded lines.
Liquid crystal voltage generator circuit
The V5 voltage is resistor-split within an IC and generates
the V1 , V2, V3, and V4 potentials required for the liquid
crystal drive.
Further, the V1, V2, V3, and V4 potentials are impedanceconverted by the voltage follower and supplied to the
liquid crystal drive circuit.
11–24
Using the bias set command allows you to select a
desired bias ratio from 1/9 or 1/7.
High power mode
The power supply circuit incorporated in the S1D15710
series has the ultra-low power consumption (normal
mode: HPM=HIGH). Therefore the display quality
EPSON
Rev. 1.1a
S1D15710 Series
may be deteriorated in large load liquid crystal or
panels. In this case, the display quality can be improved
by setting HPM pin=LOW (high power mode). Whether
to use the power supply circuit in this mode should need
the display confirmation by actual equipment.
Also, if improvement is insufficient even for the high
power mode setting, use either the S1D15710D10B* or
supply liquid crystal drive power externally. In either
case, be sure to check the display thoroughly.
Procedure
Description
(Command, state)
Step1
Power save
Step2
Turning off the built
-in power supply
Command sequence when the built-in power
supply is turned off
To turn off the built-in power supply, set it in the power
save state and then turn off the power supply according
to the command sequence shown in Figure 13
(procedure).
Command address
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
0
0
0
Power save command
1
(Both stand-by and
sleep can be useal)
Figure 13
1 All the built-in power supply used
(1) When using the V5 voltage adjusting built-in resistor
(Example of VSS2=VSS, quadruple boosting)
(2) When not using the V5 voltage adjusting built-in resistor
(Example of VSS2=VSS, quadruple boosting)
VDD
C1
VSS
C1
C1
C1
C1
VDD
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VDD
C2
C2
C2
C2
C2
Rev. 1.1a
M/S
IRS
C1
VSS
C1
C1
S1D15710
IRS
C1
R3
R2
VDD
C1
VSS2
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
R1
VDD
C2
V1
C2
V2
V1
V2
V3
C2
V3
V4
C2
V4
V5
C2
V5
EPSON
M/S
S1D15710
VDD
11–25
S1D15710 Series
2 Only the voltage adjusting circuit and V/F circuit used
(1) When using the V5 voltage adjusting built-in resistor
(2) When not using the V5 voltage adjusting built-in resistor
VDD
External
Power
Supply
VDD
VSS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
V5
VR
VDD
C2
C2
C2
C2
C2
IRS
VSS
External
Power
Supply
R3
R2
VDD
R1
VDD
C2
V1
C2
V2
V1
V2
V3
C2
V3
V4
C2
V4
V5
C2
V5
3 Only the V/F circuit used
4 Only the external power supply used
Depending on all external power supplies
VDD
VSS
External
Power
Supply
VDD
VSS
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VDD
C2
C2
M/S
VSS
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
VDD
VDD
V1
V3
C2
V4
C2
V5
M/S
V1
V2
C2
VDD
IRS
S1D15710
IRS
VSS
VSS
VOUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V5
VR
M/S
S1D15710
VSS
M/S
S1D15710
IRS
S1D15710
VDD
External
Power
Supply
V2
V3
V4
V5
Common reference setting example
At V 5=–8 to –12 V variable
Item Setting value Unit
C1
1.0 to 4.7
µF
C2
0.01 to 1.0
µF
Figure 14
11–26
EPSON
Rev. 1.1a
S1D15710 Series
*1 Since the VR terminal input impedance is high, use short leads and shielded lines. When the VR terminal is not
used, means should be taken to prevent capacitance of the line or others from being applied.
*2 C1 and C2 are determined according to the size of the LCD panel. Set a value so that the liquid crystal drive voltage
can be stable.
[Setting example] • Turn on the V5 adjusting circuit and the V/F circuit and apply external voltage.
• Display LCD heavy load patterns like lateral stripes and determine C 2 so that the liquid
crystal drive voltages (V 1 to V5) can be stable.
• Then turn on all built-in power supplies and determine C 1.
*3 Capacity is connected in order to stabilize voltage between VDD and VSS power supplies.
*4 When the built-in V/F circuit is used to drive an LCD panel with heavy alternating or direct current load, we
recommend that external resistance be connected in order to stabilize V/F outputs, or electric potentials, V 1, V2 ,
V3 and V4.
VDD
C2
Adjust resistance value R 4 to the optimal level by
checking driving waveform displayed on the LCD.
V1
Reference setting: R4 = 0.1 to 1.0 [MΩ]
R4
V2
C2
V3
C2
S1D15710 Series
R4
VDD
V4
C2
R4 R4
C2
V5
Figure 15
*5 Precautions when installing the COG
When installing the COG, it is necessary to duly consider
the fact that there exists a resistance of the ITO wiring
occurring between the driver chip and the externally
connected parts (such as capacitors and resistors). By the
influence of this resistance, non-conformity may occur
with the indications on the liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the driver
chip pin to the externally connected parts as much as
possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
2.
Also, as for this driver IC, pay sufficient attention to the
following points when connecting to external parts for
the characteristics of the circuit.
1. Connection to the boosting capacitors The boosting
capacitors (the capacitors connecting to respective
CAP pins and capacitor being inserted between
VOUT and VSS2) of this IC are being switched over
Rev. 1.1a
EPSON
by use of the transistor with very low ON-resistance
of about 10Ω. However, when installing the COG,
the resistance of ITO wiring is being inserted in
series with the switching transistor, thus dominating
the boosting ability.
Consequently, the boosting ability will be hindered
as a result and pay sufficient attention to the wiring
to respective boosting capacitors.
Connection of the smoothing capacitors for the
liquid crystal drive
The smoothing capacitors for the liquid crystal
driving potentials (V 1 . V 2 , V 3 and V 4 ) are
indispensable for liquid crystal drives not only for
the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs
pursuant to installation of the COG is supplemented
to these smoothing capacitors, the liquid crystal
driving potentials become unstable to cause nonconformity with the indications of the liquid crystal
display. Therefore, when using the COG module,
we definitely recommend to connect reinforcing
resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these
reinforcing resistors, current consumption will
increase.
11–27
S1D15710 Series
Indicated below is an exemplary connection diagram of external resistors.
Please make sufficient evaluation work for the display statuses with any connection tests.
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
VDD
VDD
R4
V1
V2
C2
V3
C2
V1
C2
R4
S1D15710 Series
C2
V2
C2
V3
C2
S1D15710 Series
R4
VDD
R4
V4
C2
C2
V4
R4 R4
C2
V5
C2
20. Test Mode Reset
Reference circuit examples
Reset Circuit
When the RES input is set to the LOW level, this LSI
enters each of the initial setting states
1. Display OFF
2. Display Normal Rotation
3. ADC Select: Normal rotation (ADC command
D0=0)
4. Power Control Register: (D2,D1,D0)=(0,0,0)
5. Register Data Clear within Serial Interface
6. LCD Power Supply Bias Ratio: 1/9 bias
7. n-Line Alternating Current Reversal Drive Reset
8. Power saving clear
9. Display All Lighting OFF: (Display All Lighting
ON/OFF command D0=LOW)
10. Built-in Oscillator Circuit stopped
11. Static Indicator OFF
Static Indicator Register: (D1,D2)=(0,0)
12. Read Modify Write OFF
13. Display start line set to the first line
14. Column address set to address 0
15. Page address set to page 0
16. Common Output State Normal rotation
17. V 5 Voltage Adjusting Built-in Resistance Ratio
Register: (D2,D1,D0)=(0,0,0)
18. Electronic Control Register Set Mode Reset
Electronic Control Register* (D5, D4, D3, D2,
D1, D0) = (1,0,0,0,0,0)
19. n-Line Alternating Current Reversal Register: (D3,
D2, D1, D0) = (0, 0, 0, 0)
11–28
V5
On the other hand, when using the reset command, only
the items 11 to 20 of the above-mentioned initial setting
are executed.
When the power is turned on, the initialization using the
RES pin is required. After the initialization using the
RES pin, each input pin needs to be controlled normally.
Besides, when the MPU control signal has high
impedance, overcurrent may be applied to an IC. After
turning on the power, take action so that the input pin
cannot have high impedance.
The S1D15710 Series discharge electric charges of V 5
and VOUT at RES pin is set to the LOW level. If external
power supplies for driving LCD are used, do not input
external power while the RES pin is set to the LOW
level to prevent short-circuiting between the external
power supplies and V DD.
EPSON
Rev. 1.1a
S1D15710 Series
7. COMMAND DESCRIPTION
The S1D15710 series identifies data bus signals according to the combinations of A0, RD(E), and WR(R/W). Since the
interpretation and execution of commands are performed only by the internal timing independently of external clocks,
the S1D15710 performs high-speed processing that does not require busy check normally.
The 80 series MPU interface starts commands by inputting low pulses to the RD pin at read and to the WR pin at write
operation. The 68 series MPU interface enters the read state when HIGH is input to the R/W pin. It enters the write state
when LOW is input to the same pin. It starts commands by inputting high pulses to the E pin (for the timing, see the
Timing Characteristics of Chapter 10). Therefore the 68 series MPU interface differs from the 80 series MPU interface
in that RD(E) is set to “1 (H)” at status read and display data read in the Command Description and Command Table.
The command description is given below by taking the 80 series MPU interface as an example.
When selecting the serial interface, enter sequential data from D7 .
Command description
(1) Display ON/OFF
This command specifies display ON/OFF.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
1
1
Setting
1
Display ON
0
Display OFF
For display OFF, the segment and common drivers output the VDD level.
(2) Display Start Line Set
This command specifies the display start line address of the display data RAM shown in Figure 4. The display area is
displayed for 65 lines from the specified line address to the line address increment direction. When this command is
used to dynamically change the line address, the vertical smooth scroll and page change are enabled. For details, see
the Line address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
↓
Rev. 1.1a
Line address
↓
1
1
1
1
1
0
62
1
1
1
1
1
1
63
EPSON
11–29
S1D15710 Series
(3) Page Address Set
This command specifies the page address that corresponds to the low address when accessing the display data RAM
shown in Figure 4 from the MPU side. The display data RAM can access desired bits when the page address and column
address are specified. Even when the page address is changed, the display state will not be changed. For details, see the
Page address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
1
Page address
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
↓
↓
0
1
1
1
7
1
0
0
0
8
(4) Column Address Set
This command specifies the column address of the display data RAM shown in Figure 4. The column address is split
into two sections (higher 4-bits and lower 4-bits) when it is set (set continuously in principle). Each time the display
data RAM is accessed, the column address automatically increments (+), making it possible for the MPU to
continuously read and write the display data. The column address increment is stopped at FFH, and the FFH is specified
continuously. This must be noted when you want to access continuously. In this case, the page address is not changed
continuously. For details, see “Column Address Circuit” in Function Description.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
High-order bit →
0
1
0
0
0
0
Low-order bit →
1
A7 A6
A5
A4
0
A3 A2
A1
A0
A7 A6 A5 A4 A3 A2 A1 A0 Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
↓
↓
1
1
1
1
1
1
1
0
254
1
1
1
1
1
1
1
1
255
(5) Status Read
E R/W
A0 RD WR
0
11–30
0
1
D7
D6
D5
D4
D3 D2 D1 D0
BUSY ADC ON/OFF RESET
0
0
EPSON
0
0
Rev. 1.1a
S1D15710 Series
BUSY
ADC
ON/OFF
RESET
When BUSY=1, indicates an internal operation being done or reset.
The command cannot be accepted until BUSY=0 is reached. However, if the cycle time is
satisfied, the command needs not be checked.
Indicates the correspondence relationship between the column address and segment driver.
0: Reversal (column address 199–n ↔ SEG n)
1: Normal rotation (column address n ↔ SEG n)
(Reverses the polarity of ADC command.)
ON/OFF: Specifies display ON/OFF
0: Display ON
1: Display OFF
(Reverses the polarity of display ON/OFF command.)
Indicates the RES signal or that initial setting is being done using the reset command.
0: Operating state
1: Resetting
(6) Display Data Write
This command writes 8-bit data to the specified address of the display data RAM. Since the column address is
automatically incremented by 1 after the data is written, the MPU can successively write the display data.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
Write data
(7) Display Data Read
This command reads the 8-bit data in the specified address of the display data RAM. Since the column address is
automatically incremented by 1 after the data is written, the MPU can successively read the data consisting of multiple
words.
Besides, immediately after the column address is set, dummy read is required one time. For details, see the description
of the Display data RAM and internal register access of “Function Description”.
When using the serial interface, the display cannot be read.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
Read data
(8) ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence relationship between the column address of the display RAM data shown
in Figure 4 and the segment driver output. Therefore the order of the segment driver output pin can be reversed using
the command. After the display data is written and read, the column address is incremented by 1 according to the column
address of Figure 4. For details, see the Column address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
Rev. 1.1a
0
1
0
1
0
0
0
0
Setting
0
Clockwise (normal rotation)
1
Counterclockwise (reversal)
EPSON
11–31
S1D15710 Series
(9) Display Normal Rotation/Reversal
This command can reversal display lighting and non-lighting without overwriting the contents of display data RAM.
In this case, the contents of display data RAM are held.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
1
1
Setting
0
LCD on potential (normal rotation)
RAM data HIGH
1
LCD on potential (reversal)
RAM data LOW
(10) Display All Lighting ON/OFF
This command can forcedly make all display set in the lighting state irrespective of the contents of display data RAM.
In this case, the contents of display data RAM are held.
This command has priority over the display normal rotation/reversal command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
1
0
Setting
0
Normal display state
1
Display all lighting
(11) LCD Bias Set
This command selects the bias ratio of the voltage required for liquid crystal drive. The command is valid when the V/
F circuit of the power supply circuit is operated.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
0
1
Selected state
0
1/9 bias
1
1/7 bias
(12) Read Modify Write
This command is used together with the end command. Once this command is entered, the column address can be
incremented by 1 only using the display data write command instead of being changed using the display read command.
This state is held until the end command is entered. When the end command is entered, the column address returns to
the address when the read modify write command is entered. This function can reduce the load of the MPU when
repeatedly changing data for a specific display area such as a blinking cursor.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
0
* The commands other than Display Data Read/Write can be used even in Read Modify Write mode. However, the
column address set command cannot be used.
11–32
EPSON
Rev. 1.1a
S1D15710 Series
• Sequence for cursor display
Page Address Set
Column Address Set
Read Modify Write
Dummy Read
Data Read
Data processing
Data Write
No
Is the change terminated?
Yes
End
Figure 16
(13) End
This command resets the Read Modify Write mode and returns the column address to the mode initial address.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
Read Modify Write Mode Set
•••
N+m
N
End
Figure 17
(14) Reset
This command initializes Display Start Line, Column Address, Page Address, Common Output State, V5 Voltage
Adjusting Built-in Resistance Ratio, Electronic Control, and Static Indicator and resets the Read Modify Write mode
and Test mode. This will not have any effect on the display data RAM. For details, see the Reset of “ Function
Description”.
Reset operation is performed after the reset command is entered.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
0
The initialization when the power is applied is performed using the reset signal to the RES pin. The reset command
cannot be substituted for the signal.
Rev. 1.1a
EPSON
11–33
S1D15710 Series
(15) Common Output State Selection
This command can select the scanning direction of the COM output pin. For details, see the Common Output State
Selection Circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
0
0
0
*
*
*
1
Selected state
Normal rotation COM0 → COM63
COM63 → COM0
*: Invalid bit
Reversal
(16) Power Control Set
This command sets the function of the power supply circuit. For details, see the Power Supply Circuit of “Function
Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
0
1
0
1
Selected state
Boosting circuit: OFF
Boosting circuit: ON
0
1
V adjusting circuit: OFF
V adjusting circuit: ON
0
V/F circuit: OFF
1
V/F circuit: ON
(V/F circuit: Voltage follower circuit, V adjusting circuit: voltage adjusting circuit)
(17) V5 Voltage Adjusting Built-in Resistance Ratio Set
This command sets the V5 voltage adjusting built-in resistance ratio. For details, see the Power Supply Circuit of
“Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
↓
Rb to Ra ratio
Small
↓
1
1
0
1
1
1
Large
(18) Electronic Control (2-Byte Command)
This command controls the liquid crystal drive voltage V5 output from the voltage adjusting circuit of the built-in liquid
crystal power supply and can adjust the light and shade of liquid crystal display.
Since this command is a 2-byte command that is used together with the electronic control mode set command and
electronic control register set command, always use both the commands consecutively.
• Electronic Control Mode Set
Entering this command validates the electronic control register set command. Once the electronic control mode is set,
the commands other than the electronic control register set command cannot be used. This state is reset after data is set
in the register using the electronic control register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
11–34
1
0
1
0
0
0
0
0
0
1
EPSON
Rev. 1.1a
S1D15710 Series
• Electronic Control Register Set
This command is used to set 6-bit data in the electronic volume register to allow the liquid crystal drive voltage V5 to
enter one-state voltage value among 64-state voltage values.
After this command is entered and the electronic control register is set, the electronic control mode is reset.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
*
*
0
0
0
0
0
0
0
1
0
*
*
0
0
0
0
0
1
0
1
0
*
*
0
0
0
0
1
0
| V5 |
Small
↓
0
1
0
*
*
1
1
1
↓
1
1
0
0
1
0
*
*
1
1
1
1
1
1
Large
When not using the electronic control function, set (1,0,0,0,0,0).
*: Invalid bit
• Sequence of the electronic control register set
Electronic Control Mode Set
Electronic Control Register Set
Electronic control mode reset
No
Is the change terminated?
Yes
Figure 18
(19) Static Indicator (2-Byte Command)
This command controls the indicator display of the static drive system. The static indicator display is controlled only
using this command, and this command is independent of other display control commands.
The static indicator is used to connect the SYNC pin to one of its liquid crystal drive electrodes and the FRS pin to the
other. For the electrodes used for the static indicator, the pattern separated from the electrodes for dynamic drive are
recommended. When this pattern is too adjacent, the deterioration of liquid crystal and electrodes may be caused.
Since the static indicator ON command is a 2-byte command that is used together with the static indicator register set
command, always use both the commands consecutively. (The static indicator OFF command is a 1-byte command.)
• Static Indicator ON/OFF
Entering the static indicator ON command validates the static indicator register set command. Once the static indicator
ON command is entered, the commands other than the static indicator register set command cannot be used. This state
is reset after the data is set in the register using the static indicator register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
Rev. 1.1a
0
1
0
1
0
1
1
0
Static indicator
0
OFF
1
ON
EPSON
11–35
S1D15710 Series
• Static Indicator Register Set
This command sets data in the 2-bit static indicator register and sets the blinking state of the static indicator.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
*
*
*
*
*
*
Indicator display state
0
0
OFF
0
1
ON (blinks at an interval of approximately
0.5 second.)
1
0
ON (blinks at an interval of approximately
one second.)
1
1
ON (goes on at all times.)
*: Invalid bit
• Sequence of Static Indicator Register Set
Static Indicator ON
Static Indicator Register Set
(Static indicator
mode reset)
No
Is the change terminated?
Yes
Figure 19
(20) Power Save
This command makes the static indicator enter the power save state and can greatly reduce the power consumption. The
power save state consists of the sleep state and stand-by state.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
0
0
0
1
Power save state
Stand-by state
Sleep state
The operating state before the display data and power save activation is held in the sleep and stand-by states, and the
display data RAM can also be accessed from the MPU.
• Sleep State
This command stops all the operations of LCD display systems, and can reduce the power consumption approximate
to the static current when they are not accessed from the MPU. The internal state in the sleep state is as follows:
(1) The oscillator circuit and the LCD power supply circuit are stopped.
(2) All liquid crystal drive circuit is stopped and the segment and common drivers output the VDD level.
11–36
EPSON
Rev. 1.1a
S1D15710 Series
• Stand-by State
This command stops the operation of the duty LCD display system and operates only the static drive system for
indicators. Consequently the minimum current consumption required for the static drive is obtained. The internal state
in the stand-by state is as follows:
(1) The LCD power supply circuit is stopped. The oscillator circuit is operated.
(2) The duty drive system liquid crystal drive circuit is stopped and the segment and common drivers output the VDD
level. The static drive system is operated.
* When using external power supplies, it is recommended that the function of the external power supply circuit
should be stopped at power save activation. For example, when providing each level of the liquid crystal drive
voltage using a stand-alone split resistor circuit, it is recommended that the circuit which cuts off the current
applied to the split resistor circuit should be added at power save activation. The S1D15710 series has the liquid
crystal display blanking control pin DOF and is set to LOW at power save activation. The function of the
external power supply circuit can be stopped using the DOF output.
(21) Power Save Reset
This command resets the power save state and returns the state before power save activation.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
1
(22) n-Line Reversal Drive Register Set
This command sets the number of reversal lines of the liquid crystal drive in the register. 2 to 16 lines can be set. For
details, see the Display Timing Generator Circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
↓
1
1
0
1
0
0
1
Line of reversal lines
—
2
3
↓
15
16
(23) n-Line Reversal Drive Reset
This command resets the n-line reversal alternating current drive and returns to the normal 2-frame reversal alternating
current drive system. The value of the n-line reversal alternating current drive register is not changed.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
1
0
0
(24) Built-in Oscillator Circuit ON
This command starts the operation of the built-in CR oscillator circuit. This command is valid only for the master
operation (M/S=HIGH) and built-in oscillator circuit valid (CLS=HIGH).
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
Rev. 1.1a
0
1
0
1
0
1
0
1
1
EPSON
11–37
S1D15710 Series
(25) NOP
Non-OPeration
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
1
(26) Test
IC chip test command. Do not use this command. If the test command is used incorrectly, it can be reset by setting the
RES input to LOW or by using the reset command or NOP.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
1
*
*
*
*
*: Invalid bit
(Note) Although the S1D15710 series holds the command operating state, it may change the internal state if excessive
foreign noise is entered. Such action that suppresses the generation of noise and prevents the effect of noise
needs to be taken on installation and systems. Besides, to prevent sudden noise, it is recommended that the
operating state should periodically be refreshed.
11–38
EPSON
Rev. 1.1a
S1D15710 Series
Table 16 S1D15710 Series Commands
Command
(1) Display ON/OFF
(2) Display Start Line Set
(3) Page Address Set
(4) Column Address Set
High-Order Bit
Column Address Set
Low-Order Bit
(5)
(6)
(7)
(8)
Status Read
Display Data Read
Display Data Write
ADC Select
Command code
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
0 1
0
1 0 1 0 1 1 1 0 LCD display ON/OFF
1
0: OFF, 1: ON
0 1
0
0 1
Display start address Sets the display start line
address of the display RAM.
0 1
0
1 0 1 1
Page
Sets the page address of
Address
the display RAM.
0 1
0
0 0 0 1
High order
Sets the high-order four bits of
Column
the column address of the display
address
RAM.
0 1
0
0 0 0 0
Low order
Sets the low-order four bits of
Column
the column address of the display
address
RAM.
0
1
1
0
0
1
0
1
1
0
1
0
Status
0 0
Write data
Read data
1 0 1 0 0 0
0
0
0
0
1
(9) Display Normal
Rotation/Reversal
0
1
0
1
0
1
0
0
1
0
1
(10) Display All Lighting
ON/OFF
(11) LCD Bias Set
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
(12) Read Modify Write
0
1
0
1
1
1
0
0
(13) End
(14) Reset
(15) Common Output State
Selection
0
0
0
1
1
1
0
0
0
1 1
1 1
1 1
1
1
0
0
0
0
1
0
0
(16) Power Control Set
0
1
0
0
0
1
0
1
1
(17) V5 Voltage Adjusting Internal 0
Resistance Ratio Set
(18) Electronic Control
0
Mode Set
Electronic Control
0
Register Set
(19) Static Indicator ON/OFF
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
*
*
1
0
1
0
1
Sets the V5 output voltage
in the electronic register.
0: OFF, 1: ON
Moves to the power save state.
0: Stand-by, 1: Sleep
1
Reads the status information.
Writes data on the display RAM.
Reads data from the display RAM.
Supports the SEG output of
the display RAM address.
0: normal rotation, 1: Reversal
LCD display normal rotation/
reversal
0: normal rotation, 1: Reversal
1 0 0 Display all lighting
1 0: normal display, 1: All ON
0 1 0 Sets the LCD drive voltage bias ratio.
1
0: 1/9, 1: 1/7
0 0 0 Increments the column address.
At write operation: By 1, at read: 0
1 1 0 Resets Read Modify Write.
0 1 0 Internal resetting
* * * Selects the scanning direction of
the COM output.
0: Normal rotation, 1: Reversal
Operating Selects the state of the built-in
state
power supply
Resistance Selects the state of the built-in
ratio setting resistance ratio (Rb/Ra).
0 0 1
Static Indicator
Register Set
(20) Power Save
0
1
0
*
*
*
Electronic
control value
0 1 1 0 0
1
* * * State
0
1
0
1
0
1
0
1
(21) Power Save Reset
(22) n-Line Reversal Drive
Register Set
(23) n-Line Reversal Drive Reset
0
0
1
1
0
0
1
0
1
0
1
1
0
1
Resets power save.
Sets the number of line
reversal drive lines.
Resets the line reversal drive.
Starts the operation of the built-in
CR oscillator circuit.
Non-Operation command
0
0
0
1
0
1
0
1
1
1
0
0 0 0 1
Number of
reversal Line
0 1 0 0
(24) Built-in Oscillator
Circuit ON
(25) NOP
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
1
0
0
0
1
1
(26) Test
0
1
0
1
1
1
1
*
*
*
*
Sets the blinking state.
Do not use the IC chip
test command.
*: Invalid bit
Rev. 1.1a
EPSON
11–39
S1D15710 Series
8. COMMAND SETTING
Instruction Setup: Reference
(1) Initial Setting
Turn on the VDD - VSS power supply in the RES pin=LOW *1
Power supply regulated
Reset the reset state (RES pin=HIGH)
Initial setting state (default) *2
Function setting by command input (set by user)
(24) Built-in Oscillator Circuit ON *3
(The built-in CR oscillator circuit is used)
Function setting by command input (set by user)
(11) LCD Bias Set *4
(8) ADC Select *5
(15) Common Output State Selection *6
(22) n-Line Reversal Register Set *7
(When the n-line alternating current
reversal drive is used)
Function setting by command input (set by user)
(17) V5 Voltage Adjusting Built-in Resistance
ratio Set *8
(18) Electronic Control *9
Function setting by command input (set by user)
(16) Power Control Set *10
End of initial setting
Notes: Reference items
*1: If external power supplies for driving LCD are used, do not supply voltage on VOUT or V5 pin during
the period when RES = LOW. Instead, input voltage after releasing the reset state.
6. Function Description “Reset Circuit”
*2: The contents of DDRAM are not defined even in the initial setting state after resetting.
6. Function Description Section “Reset Circuit”
*3: 7. Command Description Item (24) “Built-in oscillator circuit ON”
*4: 7. Command Description Item (11) “LCD bias set”
*5: 7. Command description Item (8) “ADC select”
*6: 7. Command Description Item (15) “Common output state selection”
*7: 6. Function Description Section “Display Timing Generator Circuit”, 7. Command Description Item (22)
“n-Line Reversal Register Set”
*8: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (17) “V5
Voltage Adjusting Built-in Resistance ratio Set”
*9: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (18)
“Electronic Control”
*10: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (16)
“Power Control Set”
11–40
EPSON
Rev. 1.1a
S1D15710 Series
(2) Data Display
End of initial setting
Function setting by command input (set by user)
(2) Display Start Line Set *11
(3) Page Address Set *12
(4) Column Address Set *13
Function setting by command input (set by user)
(6) Display Data Write *14
Function setting by command input (set by user)
(1) Display ON/OFF *15
End of data display
Notes: Reference items
*11: 7. Command Description Item (2) “Display Start Line Set”
*12: 7. Command Description Item (3) “Page Address Set”
*13: 7. Command Description Item (4) “Column Address Set”
*14: The contents of DDRAM is not defined after completing initial setting. Enter data in each DDRAM to
be used for display.
7. Command Description Item (6) “Display Data Write”
*15: Avoid activating the display function with entering space characters as the data if possible.
7. Command Description Item (1) “Display ON/OFF”
(3) Refresh *16
A desired mode
Set all commands again.
Write in the display data RAM again.
Notes: Reference items
*16: It is recommended that the operating modes and display contents be refreshed periodically to prevent
the effect of unexpected noise.
Rev. 1.1a
EPSON
11–41
S1D15710 Series
(4) Power *17
Any desired state
Function setting by command input (set by user)
(20) Power Save *18
Reset state (RES pin=LOW) *19
Set the time interval after the point when reset
state has attained and the point when VDD – VSS
power is shut off (tL) so that electric potentials, V1
through V5, attain values lower than the threshold
voltage displayed on the LCD panel. *20
VDD – VSS power OFF
Notes: Reference items
*17: This IC is a VDD – VSS power system circuit controlling the LCD driving circuit for the VDD – V5
power system. Shutting of power with voltage remaining in the VDD – V5 power system may cause
uncontrolling voltage to be output from the SEG and COM pins. Follow the Power OFF sequence.
*18: 7. Command Description Item (20) “Power Saving”
*19: When external power supplies for driving LCD are used, turn all external power supplies off before
entering reset state.
6. Function Description Item “Reset Circuit”
*20: The threshold voltage of the LCD panel is about 1 [V].
When the internal power supply circuit is used, discharge time tH from the start of resetting to the
voltage between VDD and V5 being reduced to 1 volt depends on capacitor C2 to be connected between
V1 – V 5 and VDD. Figure 5 shows the reference values.
V5 voltage discharge time [ms]
100
80
60
40
20
0
0
0.2
0.4
0.6
Capacity C2 [µF]
0.8
1
Figure 20
Set up tL so that the relationship, tL > t H, is maintained. A state of tL < tH may cause faulty display.
11–42
EPSON
Rev. 1.1a
S1D15710 Series
tL
Power saving
Power OFF
VDD
1.8 [V]
RES
As power (VDD – VSS)
is shut off, it becomes
impossible to fix output.
SEG
COM
At or under Vth on LCD.
Use 1.0 [V] as a
reference.
VDD
V1
V2
V3
V4
V5
tH
Figure 21
tL
Power OFF
Take action so that the relationship,
tL > tH, is maintained by measures
such as making the trailing
characteristic longer.
VDD
1.8 [V]
RES
As power (VDD – VSS)
is shut off, it becomes
unable to fix output.
SEG
COM
At or under Vth on LCD.
Use 1.0 [V] as a
reference.
VDD
V1
V2
V3
V4
V5
tH
If command control is disabled when power is OFF, take action so that the relationship, tL > tH, is
maintained by measures such as making the trailing characteristic of power (VDD – VSS ) longer.
Figure 22
Rev. 1.1a
EPSON
11–43
S1D15710 Series
9. ABSOLUTE MAXIMUM RATINGS
Table 17
VSS=0 V unless specified otherwise
Item
Symbol
Power supply voltage
VDD
Power supply voltage (2)
(Based on VDD )
At triple boosting
VSS2
At quadruple boosting
Specification value
–0.3
to
+7.0
–7.0
to
+0.3
–6.0
to
+0.3
–4.5
to
+0.3
Power supply voltage (3) (Based on VDD)
V5, VOUT
–22.0
to
+0.3
Power supply voltage (4) (Based on VDD)
V1, V2, V3, V 4
V5
to
+0.3
Input voltage
VIN
–0.3
to VDD+0.3
Output voltage
VO
–0.3
to VDD+0.3
TOPR
–40
to
+85
TSTR
–55
to
+100
–55
to
+125
Operating temperature
Storage temperature
TCP
Bare chip
VCC
VDD
GND
VSS
Unit
V
°C
VDD
VSS2, V1~V4
V5, VOUT
System (MPU) side
S1D15710 side
Figure 23
(Notes) 1. The values of the VSS2 , V1 to V5 , and VOUT voltages are based on VDD=0 V.
2. The V1, V2, V3, and V 4 voltages must always satisfy the condition of VDD≥V1≥V2≥V3≥V4≥V5.
3. Insure that voltage levels VSS2 and VOUT are always such that the relationship of VDD≥V SS≥V SS2≥
VOUT is maintained.
4. When LSI is used exceeding the absolute maximum ratings, the LSI may be damaged permanently.
Besides, it is desirable that the LSI should be used in the electrical characteristics condition for normal
operation. If this condition is exceeded, the LSI may malfunction and have an adverse effect on the
reliability of the LSI.
11–44
EPSON
Rev. 1.1a
S1D15710 Series
10. DC CHARACTERISTICS
Table 18
Item
Symbol
Operating Recommended V DD
voltage
operation
(1)
Operable
V DD
Operating Recommended V SS2
voltage
operation
(2)
Operable
V SS2
Operating Operable
V5
voltage
Operable
V 1, V2
(3)
Operable
V 3, V4
High level input voltage
VIHC
Low level input voltage
VILC
High level output voltage
VOHC
Low level output voltage
V OLC
Input leak current
ILI
Output leak current
ILO
Liquid crystal driver
RON
On resistance
Static current consumption I SSQ
Output leak current
I5Q
Input pin capacity
CIN
Oscillating Built-in
fOSC
frequency oscillation
External input
fCL
Condition
(Based on V DD)
(Based on V DD)
(Based on V DD)
(Based on V DD)
(Based on V DD)
IOH=–0.5mA
IOL =0.5mA
V IN=VDD or VSS
Ta=25°C
V5=–14.0V
(Based on V DD) V5=–8.0V
V 5=–18.0V (Based on VDD)
Ta=25°C, f=1MHz
Ta=25°C
VSS=0 V, VDD=3.0 V ± 10%, and Ta=–40 to 85°C
Specification value
Min.
Typ.
Max.
2.7
—
3.3
Applicable
Unit
pin
V
VDD *1
1.8
–3.3
—
—
5.5
–2.7
VDD *1
VSS2
–6.0
–18.0
0.4×V 5
V5
0.8×V DD
V SS
0.8×V DD
V SS
–1.0
–3.0
—
—
—
—
—
18
—
—
—
—
—
—
—
—
—
—
2.0
3.2
0.01
0.01
5.0
22
–1.8
–4.5
VDD
0.6×V5
VDD
0.2×VDD
VDD
0.2×VDD
1.0
3.0
3.5
5.4
5
15
8.0
26
VSS2
V5 *2
V1, V2
V3, V4
*3
*3
*4
*4
*5
*6
SEGn
COMn *7
V SS, VSS2
V5
4.5
5.5
6.5
µA
kΩ
µA
pF
kHz
*8
CL *8
Table 19
Built-in power supply circuit
Item
Input voltage
Symbol
V SS2
V SS2
Boosting output voltage VOUT
Voltage adjusting circuit VOUT
operating voltage
V/F circuit operating
V5
voltage
Reference voltage
VREG0
Condition
Specification value
Min.
Typ.
Max.
–6.0
—
–1.8
Unit
At triple boosting
(Based on V DD)
At quadruple boosting
(Based on V DD)
(Based on V DD)
(Based on V DD)
–5.0
—
–1.8
VSS2
–20.0
–20.0
—
—
—
–6.0
V OUT
V OUT
(Based on V DD)
–18.0
—
–4.5
V5 *9
–2.04
–2.10
–2.16
Ta=25°C,
–0.05%/°C
V
Applicable
pin
VSS2
*10
[*: see Page 49.]
Rev. 1.1a
EPSON
11–45
S1D15710 Series
Dynamic current consumption value (1) During display operation and built-in power supply OFF
Current values dissipated by the whole IC when the external power supply is used
Table 20 Display All White
Item
Symbol
S1D15710D00B*
/D11B *
IDD
(1)
Ta=25°C
Condition
VDD=5.0V, V5–VDD =–11.0V
VDD=3.0V, V5–VDD =–11.0V
Specification value
Min.
Typ.
Max.
—
25
42
—
25
42
Unit Remarks
µA
Table 21 Display Checker Pattern
Item
Symbol
S1D15710D00B *
/D11B *
IDD
(1)
*11
Ta=25°C
Condition
VDD=5.0V, V5–VDD =–11.0V
VDD=3.0V, V5–VDD =–11.0V
Specification value
Min.
Typ.
Max.
—
38
64
—
38
64
Unit Remarks
µA
*11
Dynamic current consumption value (2) During display operation and built-in power supply ON
Current values dissipated by the whole IC containing the built-in power supply circuit
Table 22 Display All White
Item
Symbol
S1D15710
D00B*/D11B*
IDD
(2)
Normal mode
High power mode
Normal mode
High power mode
Normal mode
High power mode
Normal mode
High power mode
Ta=25°C
Specification value
Unit Remarks
Min.
Typ.
Max.
—
132
221
µA
*12
—
280
468
—
167
279
—
350
585
—
178
297
—
330
550
—
220
367
—
406
677
Condition
VDD=5.0V, Triple boosting
V5–VDD=–11.0V
VDD=3.0V, Quadruple boosting
V5–V DD=–11.0V
VDD=5.0V, Triple boosting
V5–V DD=–11.0V
VDD=3.0V, Quadruple boosting
V5–V DD=–11.0V
S1D15710D10B*
Normal mode
High power mode
Normal mode
High power mode
Normal mode
High power mode
Normal mode
High power mode
Ta=25°C
Specification value
Unit Remarks
Min.
Typ.
Max.
—
92
154
µA
*12
—
242
405
—
129
216
—
310
518
—
135
225
—
288
480
—
176
294
—
363
605
Table 23 Display Checker Pattern
Item
Symbol
S1D15710
D00B*/D11B*
IDD
(2)
S1D15710D10B*
Condition
VDD=5.0V, Triple boosting
V5–V DD=–11.0V
VDD=3.0V, Quadruple boosting
V5–V DD=–11.0V
VDD=5.0V, Triple boosting
V5–V DD=–11.0V
VDD=3.0V, Quadruple boosting
V5–V DD=–11.0V
Current consumption at power save V SS=0 V and VDD= 3.0 V ±10%
Table 24
Item
Sleep state
Stand-by state
Ta=25°C
Symbol
Condition
IDDS1
IDDS2
Specification value
Min.
Typ.
Max.
—
0.01
5
—
4
8
Unit Remarks
µA
[*: see Page 49.]
11–46
EPSON
Rev. 1.1a
S1D15710 Series
[Reference data 1]
• Dynamic current consumption (1) External power supply used and LCD being displayed
50
IDD (1) (ISS + I5) [µA]
40
Condition: Built-in power supply OFF
External power supply used
V5 – VDD = –11.0 V
Display pattern: All white/
checker
Ta = 25°C
Checker
30
Remarks: *11
All white
20
10
0
0
2
4
VDD [V]
6
8
Figure 24
[Reference data 2]
• Dynamic current consumption (2) Built-in power supply used and LCD being displayed
S1D15710D10B*
Display checker
250
150
S1D15710D10B*
Display all white
Condition: Built-in power supply ON
Quadruple boosting
V5 – V DD = –11.0 V
Normal mode
Display pattern: All white/
checker
Ta = 25°C
100
S1D15710D00B /D11B
*
*
Display all white
Remarks: *12
IDD (2) [µA]
200
S1D15710D00B /D11B
*
*
Display checker
50
0
0
2
4
VDD [V]
6
8
[*: see page 49.]
Figure 25
Rev. 1.1a
EPSON
11–47
S1D15710 Series
[Reference data 3]
• Dynamic current consumption (3) During access
Indicates the current consumption when
the checker pattern is always written at
fCYC.
Only I DD (1) when not accessed
Condition: Built-in power supply OFF
and external power supply
used
VDD – V SS = 3.0 V,
V5 – VDD = –11.0 V
Ta = 25°C
10
IDD (3) [mA]
1
0.1
0.01
0.001
0.01
0.1
1
10
fCYC [MHz]
Figure 26
[Reference data 4]
–20
V SS and V 5 system operating voltage
ranges
S1D15710 Series
–18
Remarks: *2
V5 - VDD [V]
–15
–10
Operation
Area
–7.2
–5
–4.5
1.8
0
0
2
3.6
5.5
4
6
8
VDD [V]
Figure 27
11–48
EPSON
[*: see page 49.]
Rev. 1.1a
S1D15710 Series
Relationships between the oscillating frequency fOSC, display clock frequency f CL, and liquid
crystal frame frequency f FR
Table 25
Item
fCL
fFR
When built-in oscillator
fOSC
fOSC
circuit used
4
4*65
When built-in oscillator
External input (fCL)
fCL
circuit not used
65
(fFR indicates the alternating current cycle of the liquid crystal and does not indicate that of the FR signal.)
[Reference items marked by *]
*1 The wide operating voltage range is not warranted. However, when there is a sudden voltage change
during MPU access, it cannot be warranted.
*2 For the VDD and V5 operating voltage ranges, see Figure 27. These ranges are applied when using the
external power supply.
*3 A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF,
RES, IRS and HPM pins
*4 D0 to D7, FR, FRS, DOF and CL pins
*5 A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS and HPM pins
*6 Applied when D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF pins are in the high impedance state
*7 Resistance value when the 0.1 V voltage is applied between the output pin SEGn or COMn and power
supply pins (V1, V2, V3, and V 4). Specified within the range of operating voltage (3)
RON = 0.1 V/∆I (∆I indicates the current applied when 0.1 V is applied between the power ON.)
*8 For the relationship between the oscillating frequency and frame frequency. The specification value of
the external input item is a recommended value.
*9 The V5 voltage adjusting circuit is adjusted within the voltage follower operating voltage range.
*10 This is the internal voltage reference supply for the V5 voltage regulator circuit. The thermal slope
VREG of the S1D15710 Series is about –0.05%/°C.
*11 and *12 Indicate the current dissipated by a single IC at built-in oscillator circuit used, 1/9 bias, and display
ON.
Does not include the current due to the LCD panel capacity and wireing capacity.
Applicable only when there is no access from the MPU.
*12 When the V5 voltage adjusting built-in resistor is used
Rev. 1.1a
EPSON
11–49
S1D15710 Series
Timing Characteristics
System bus read/write characteristics 1 (80 series MPU)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
*1
tCCLR, tCCLW
WR, RD
tCCHR, tCCHW
CS1
(CS2="1")
*2
WR, RD
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 28
*1 is set when CS is LOW and access is made with WR and RD.
*2 is used when WR and RD are LOW and accessed with CS.
Table 26
Item
Signal
Address hold time
A0
Address setup time
System cycle time
A0
Control LOW pulse width (Write)
WR
Control LOW pulse width (Read)
RD
Control HIGH pulse width (Write)
WR
Control HIGH pulse width (Read)
RD
D0 to D7
Data setup time
Data hold time
RD access time
Output disable time
11–50
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
EPSON
[VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
0
—
ns
0
—
333
—
30
—
70
—
30
—
30
—
30
—
10
—
CL=100pF
—
70
5
50
Rev. 1.1a
S1D15710 Series
Table 27
Item
Signal
Address hold time
A0
Address setup time
System cycle time
A0
Control LOW pulse width (Write)
WR
Control LOW pulse width (Read)
RD
Control HIGH pulse width (Write)
WR
Control HIGH pulse width (Read)
RD
D0 to D7
Data setup time
Data hold time
RD access time
Output disable time
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
[VDD=2.7V to 4.5V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
0
—
ns
0
—
500
—
60
—
120
—
60
—
60
—
40
—
15
—
CL=100pF
—
140
10
100
Table 28
Item
Signal
Address hold time
A0
Address setup time
System cycle time
A0
Control LOW pulse width (Write)
WR
Control LOW pulse width (Read)
RD
Control HIGH pulse width (Write)
WR
Control HIGH pulse width (Read)
RD
D0 to D7
Data setup time
Data hold time
RD access time
Output disable time
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
0
—
ns
0
—
1000
—
120
—
240
—
120
—
120
—
80
—
30
—
CL=100pF
—
280
10
200
*1. This is the case of accessing by WR and RD when CS1 = LOW.
*2. This is the case of accessing by CS1 when WR and RD = LOW.
*3 The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr +tf) ≤ ( tCYC8–t CCLW–t CCHW) or (tr +tf) ≤ ( tCYC8–tCCLR– tCCHR).
*4 All timings are specified based on the 20 and 80% of VDD.
*5 tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2= HIGH) level and WR, RD are
at the LOW level.
Rev. 1.1a
EPSON
11–51
S1D15710 Series
System bus read/write characteristics 2 (68 series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
tCYC6
*1
tEWHR, tEWHW
E
tEWLR, tEWLW
CS1
(CS2="1")
*2
E
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 29
*1 is set when CS is LOW and access is made with E.
*2 is used when E is HIGH and access is made with CS.
Table 29
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
width
Enable LOW pulse
width
11–52
Signal
Symbol
A0
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
D0 to D7
Read
Write
Read
Write
E
E
EPSON
[VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
0
—
ns
0
—
333
—
30
—
10
—
CL=100pF
—
70
10
50
70
—
30
—
30
—
30
—
Rev. 1.1a
S1D15710 Series
Table 30
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
width
Enable LOW pulse
width
Signal
A0
D0 to D7
Read
Write
Read
Write
E
E
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
[VDD=2.7V to 4.5V, Ta=–40 to 85°C]
Specification value
Condition
Min.
Max.
Unit
0
—
ns
0
—
500
—
40
—
15
—
CL=100pF
—
140
10
100
120
—
60
—
60
—
60
—
Table 31
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
width
Enable LOW pulse
width
*1
*2
*3
*4
*5
Signal
Symbol
A0
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
D0 to D7
Read
Write
Read
Write
E
E
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
0
—
ns
0
—
1000
—
80
—
30
—
CL=100pF
—
280
10
200
240
—
120
—
120
—
120
—
This is the case of accessing by E when CS1 = LOW.
This is the case of accessing by CS1 when E = HIGH.
The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr +tf) ≤ ( tCYC6–tEWLW– tEWHW) or (tr +tf ) ≤ (tCYC6– tEWLR– tEWHR).
All timings are specified based on the 20 and 80% of VDD.
tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2 = HIGH) level and E is at the
HIGH level.
Rev. 1.1a
EPSON
11–53
S1D15710 Series
Serial interface
tCSS
CS1
(CS2="1")
tCSH
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Figure 30
Table 32
Item
Serial clock cycle
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Signal
Symbol
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
A0
SI
CS
[VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
200
—
ns
75
—
75
—
50
—
100
—
50
—
50
—
100
—
100
—
Table 33
Item
Serial clock cycle
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
11–54
Signal
Symbol
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
A0
SI
CS
EPSON
[VDD=2.7V to 4.5V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
250
—
ns
100
—
100
—
150
—
150
—
100
—
100
—
150
—
150
—
Rev. 1.1a
S1D15710 Series
Table 34
Item
Serial clock cycle
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
*1
*2
Signal
Symbol
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
A0
SI
CS
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Specification value
Condition
Unit
Min.
Max.
400
—
ns
150
—
150
—
250
—
250
—
150
—
150
—
250
—
250
—
The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns.
All timings are specified based on the 20 and 80% of VDD.
Display control output timing
CL
(OUT)
tDFR
FR
tDSNC
SYNC
Figure 31
Table 35
[VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Item
Signal
Symbol
Condition
FR delay time
SYNC delay time
FR
SYNC
tDFR
CL=50pF
CL=50pF
tDSNC
Specification value
Min.
Typ.
Max.
—
10
40
—
10
40
Unit
ns
ns
Table 36
[VDD=2.7V to 4.5V, Ta=–40 to 85°C]
Item
Signal
Symbol
Condition
FR delay time
SYNC delay time
FR
SYNC
tDFR
CL=50pF
CL=50pF
tDSNC
Specification value
Min.
Typ.
Max.
—
20
80
—
20
80
Unit
ns
ns
Table 37
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Item
Signal
Symbol
Condition
FR delay time
SYNC delay time
FR
SYNC
tDFR
tDSNC
CL=50pF
CL=50pF
Specification value
Min.
Typ.
Max.
—
50
200
—
50
200
Unit
ns
ns
*1 Valid only when the master mode is selected.
*2 All timings are specified based on the 20 and 80% of VDD.
*3 Pay attention not to cause delays of the timing signals CL, FR and SYNC to the salve side by wiring resistance, etc.,
while master/slave operations are in progress. If these delays occur, indication failures such as flickering may occur.
Rev. 1.1a
EPSON
11–55
S1D15710 Series
Reset input timing
tRW
RES
tR
Internal state
Resetting
Completion of reset
Figure 32
Table 38
[VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Item
Reset time
Reset LOW pulse width
Signal
RES
Symbol
tR
tRW
Condition
Specification value
Min.
Typ.
Max.
—
—
0.5
0.5
—
—
Unit
µs
Table 39
[VDD=2.7V to 4.5V, Ta=–40 to 85°C]
Item
Reset time
Reset LOW pulse width
Signal
RES
Symbol
tR
tRW
Condition
Specification value
Min.
Typ.
Max.
—
—
1
1
—
—
Unit
µs
Table 40
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Item
Reset time
Reset LOW pulse width
*1
Signal
RES
Symbol
tR
tRW
Condition
Specification value
Min.
Typ.
Max.
—
—
1.5
1.5
—
—
Unit
µs
All timings are specified based on the 20 and 80% of V DD.
11–56
EPSON
Rev. 1.1a
S1D15710 Series
11. MICROPROCESSOR (MPU) INTERFACE: REFERENCE
The S1D15710 series can directly be connected to the 80 system MPU and 68 series MUP. It can also be operated with
a fewer signal lines by using the serial interface.
The S1D15710 series is used for the multiple chip configuration to expand the display area. In this case, it can select
the ICs that are accessed individually using the Chip Select signal.
After the initialization using the RES pin, the respective input pins of the S1D15710 series need to be controlled
normally.
80 series MPU
VDD
VDD
A0
MPU
A1 to A7
IORQ
D0 to D7
RD
WR
RES
GND
A0
Decoder
RESET
CS1
CS2
D0 to D7
RD
WR
RES
VSS
C86
S1D15710
VCC
P/S
VSS
Figure 33-1
68 series MPU
VDD
VDD
MPU
A0
A1 to A15
VMA
D0 to D7
E
R/W
RES
GND
A0
Decoder
RESET
CS1
CS2
D0 to D7
E
R/W
RES
VSS
C86
S1D15710
VCC
P/S
VSS
Figure 33-2
Serial interface
VDD
A0
MPU
A1 to A7
A0
CS1
CS2
Decoder
Port 1
Port 2
RES
GND
SI
SCL
RES
VSS
RESET
C86
VDD or VSS
S1D15710
VCC
P/S
VSS
Figure 33-3
Rev. 1.1a
EPSON
11–57
S1D15710 Series
12. CONNECTION BETWEEN LCD DRIVERS: REFERENCE
The S1D15710 series is used for the multiple chip configuration to easily expand the liquid crystal display area. Use
the same device (S1D15710*****/S1D15710*****) for the master/slave.
S1D15710 (master) ↔ S1D15710 (slave)
VDD
M/S
M/S
FR
SYNC
SYNC
CL
CL
DOF
DOF
Output
S1D15710
Slave
S1D15710
Master
FR
Input
VSS
Figure 34
11–58
EPSON
Rev. 1.1a
S1D15710 Series
13. LCD PANEL WIRING: REFERENCE
The S1D15710 series is used for the multiple chip configuration to easily expand the liquid crystal display area. Use
the same device (S1D15710*****/S1D15710*****) for the multiple chip configuration.
1-chip configuration
224 x 65 Dots
COM
SEG
COM
S1D15710
Master
Figure 35-1
2-chip configuration
448 x 65 Dots
COM
SEG
SEG
S1D15710 Series
Master
COM
S1D15710 Series
Slave
Figure 35-2
Rev. 1.1a
EPSON
11–59
S1D15710 Series
14. TCP PIN LAYOUT
Reference
FRS
SYNC
COM S
COM 63
•
•
•
•
•
COM 33
COM 32
CHIP TOP VIEW
SYNC
FRS
FR
CL
DOF
CS1
CS2
RES
A0
WR,R/W
RD, E
D0
D1
D2
D3
D4
D5
D6, SCL
D7, SI
VDD
VSS
VSS2
VOUT
CAP3CAP1+
CAP1CAP2CAP2+
VRS
VDD
V1
V2
V3
V4
V5
VR
M/S
CLS
C86
P/S
HPM
IRS
SEG 223
SEG 222
•
•
•
•
•
SEG 1
SEG 0
COM S
COM 0
•
•
•
•
•
COM 30
COM 31
Note) This TCP pin layout does not specify the TCP dimensions.
11–60
EPSON
Rev. 1.1a
±0.03
5.560 (SL)
Cross sectional view of output outer lead
(190µm)
95±20µm
MIN60µm
MAX0.15
(SL)
4.800
(SL)
4.800
1.981
NC X2
FRS
SYNC
COMS
COM63
3
...
COM32
SEG223
...
(SL)
C
0.170
φ1.500 ±0.05
Detail of A (×20)
0.0575
0.170
13.000
...
NC
4.750 ±0.03
9.060 (SL)
MAX1.00
±0.07
(W:0.095,G:0.095)
2
2
V5
VR
V2
V3
V4
VRS
VDD
V1
1.500
DOF
CL
(SL)
CS1
CS2
RES
A0
20.500
MAX1.50
(SL)
17.950
0.400
20.000
Detail of B (×20)
1.000
(SL)
0.100
27.100
26.500
0.500
D0
(SR)
13.000
D2
(SL)
D3
D6(SCL)
0.500
0.500
P0.8X(44-1)=
D7(SI)
D4
D5
Detail of C (×10)
0.400
VDD
16.650
CAP1-
CAP1+
CAP3-
VOUT
34.400
CAP2-
(W:0.4,G:0.4)
(Encap. and Mark area)
(IC)
VSS2
1.500
VSS
MAX19.650
CAP2+
RD,E
13.000
MAX1.50
17.950
(SL)
20.500
20.000
(SR)
(SL)
(SL)
(SL)
1.500
P/S
(Mark)
(SR)
A
...
...
13.000
φ1.700
SEG0
COMS
COM0
NC
IRS
(SL)
MATERIAL
• Base Filem UPLEX-S 75µm
• Copper Foil 25µm
• Plating Sn
• No assigned position tolerance of Solder Resist ±0.3
• 5 sproket holes (23.75mm) for 1 pattern
27.100
26.500
28.5725
56.050
M/S
28.3725
P0.19X(296-1)=
C86
(SR)
CLS
(Mark)
HPM
28.3725
1.500 ±0.05
+0.08
-0.12
B
12.800
COM31
NC X2
MAX1.0
SL=Slit
SR=Solder Resist
MAX0.15
MAX0.8
4
IC:SED157A-0B
*Dimension are defind after 25°C × 60% × 72H exposed.
*Failure devices are punch.
• At least die area is punch out completely.
...
(Mark)
11.000
X (+)
69.950 ±0.2
13.190
8.560
28.5725
FR
0.100
(SL)
7.560
MAX0.80
WR,R/W
1.000
(IC)
2.900
0.170
0.050
0.170
D1
0.100
0.100
EPSON
45°
(SR)
8.800
(SR)
5.260
MAX1.50
MAX1.50
Rev. 1.1a
63.949
S1D15710 Series
15. TCP DIMENSIONS
11–61
FRS
SYNC
MAX5.900
(Encap.and Mark erea)
10.060 (SL)
Y (+)
S1D15710 Series
16. TEMPERATURE SENSOR CIRCUIT
Both the S1D15710*10** and S1D15710*11** have built-in temperature sensor circuits with analog voltage output
terminals having a temperature gradient of 11.4mV/°C (Typ.). By controlling the liquid crystal drive voltage at V5 by
inputting an electric volume register value corresponding to the temperature sensor output value from the MPU enables
liquid crystal to display appropriate light and shade over a wide range of temperatures.
Build a system to compensate for variations in the output voltage by feeding back the output voltage value sampled at
a constant temperature to the MPU and store it as the standard voltage in order to achieve higher control of the liquid
crystal drive voltage.
1. Terminal description
*Terminals related to the temperature sensor circuit are allocated to TEST 1 and 2, and are named VSEN1 for TEST1
and SVS1 for TEST2. Use the temperature sensor as indicated in the table below. When not in use, fix each terminal
at HIGH.
Pin name
Number of
pins
I/O
Description
SVS1
Power
Power terminal of the temperature sensor. Apply compulsory
operation voltage to VDD.
1
VSEN1
O
Analog voltage output terminal of temperature sensor. Monitor
the output voltage to VDD.
1
2. Electrical characteristics
Symbol
Operating voltage
SVS
Output voltage
VSEN
Output voltage
temperature gradient
Output voltage
linearity
Output voltage
setup time
Operating current
VGRA
(VDD standard)
(VDD standard) Ta=–40°C
(VDD standard) Ta=25°C
(VDD standard) Ta=85°C
*1
∆VL
*2
–1.5
–
tSEN
*3
100
–
11–62
ISEN
Condition
Specification value
Min.
Typ.
Max.
–5.5
–5.0
–4.5
–4.35 –3.62 –2.89
–3.48 –2.88 –2.28
–2.92 –2.20 –1.47
9.4
11.4
13.4
Item
Ta=25°C
EPSON
Unit
Applicable
V
PIN
SVS1
V
VSEN1
mV/°C
VSEN1
1.5
%
VSEN1
–
–
mS
VSEN1
40
150
µA
SVS1
Rev. 1.1a
S1D15710 Series
*Notes:
*1: Slope of approximate line of Typ. output voltage.
*2: Maximum deviation of output voltage curve and approximate line.
When the output voltage difference between –40°C and 85°C is ∆V SEN, the difference between the
approximate line and the output voltage value is ∆DIFF and the maximum value is ∆DIFF(Max.),
output voltage linearity ∆VL will be expressed using the following formula:
Output voltage VSEN[V] (VDD=0[V] standard)
∆VL =
∆DIFF( Max.)
× 100
∆VSEN
∆VDIFF
∆VSEN
∆VDIFF
=VSEN(-40°C)–VSEN(85°C)
Output voltage
Approximate
line
∆VDIFF
When ∆VDIFF becomes maximum at all
temperatures it is defined as ∆VDIFF(Max.)
–50
–25
0
25
50
75
100
Temperature Ta[°C]
*3: Waiting time until monitoring is enabled with stable output voltage after applying power voltage SVS
to terminal SVS1. The output voltage needs to be sampled after a longer than standard waiting time.
Output voltage VSEN[V] (VDD=0[V] standard)
■ Output voltage characteristics
0
–1
Min.
–2
Typ.
–3
Max.
–4
–5
–50
–25
0
25
50
75
100
Temperature Ta[°C]
Rev. 1.1a
EPSON
11–63
S1D15710 Series
3. Output terminal load
Load capacity CL of VSEN output terminal VSEN1 should be under 100pF and load resistance RL higher than 1MΩ.
Be careful not to build a current path between VSS in order to obtain an accurate output voltage value.
VDD
VDD
S1D15710 Series
CL
11–64
VSEN
RL
VSEN
EPSON
Rev. 1.1a
12. S1D15A06 Series
Rev. 1.0a
Contents
1. DESCRIPTION ..............................................................................................................................................12-1
2. FEATURES .................................................................................................................................................... 12-1
3. BLOCK DIAGRAM ......................................................................................................................................... 12-2
4. PIN LAYOUT .................................................................................................................................................12-3
5. PIN DESCRIPTION .......................................................................................................................................12-6
6. FUNCTIONAL DESCRIPTION ......................................................................................................................12-9
7. COMMANDS ...............................................................................................................................................12-25
8. COMMAND SETTING ................................................................................................................................. 12-33
9. ABSOLUTE MAXIMUM RATING ................................................................................................................. 12-37
10. DC CHARACTERISTICS .............................................................................................................................12-38
11. AC CHARACTERISTICS .............................................................................................................................12-44
12. MPU INTERFACE (EXAMPLES) ................................................................................................................. 12-49
–i–
Rev. 1.0a
S1D15A06 Series
1. DESCRIPTION
The S1D15A06 series is a single-chip liquid crystal
display (=LCD) driver for dot-matrix LCDs that can be
connected directly to a microprocessor (=MPU) bus. It
accepts 8-bit parallel or serial display data from a MPU,
stores it in an on-chip display data RAM (=DDRAM),
and generates a LCD drive signal independent of the
MPU clock.
The use of the on-chip DDRAM of 65×102 bits and a
one-to-one correspondence between LCD panel pixel
dots and on-chip DDRAM bits offer high flexibility in
graphic display.
The S1D15A06 series does not need external operation
clock for DDRAM read/write operations, and has a onchip LCD power supply circuit featuring very low
current consumption with few external components,
and moreover has a on-chip CR oscillator circuit.
And the S1D15A06 does not need smoothing capacitor
on the LCD power supply.
Consequently, the S1D15A06 series can be realize a
high-performance handy display system with a minimum
current consumption and the fewest components.
2. FEATURES
• Direct display of RAM data through the display data
RAM.
• RAM bit data :
“1” Non-illuminated
“0” Illuminated
(during normal display)
• RAM capacity
65×102 = 6630 bits
• Display driver circuits
S1D15A06***** : 55 common output and 102
segment outputs
• High-speed 8-bit MPU interface(The chip can be
connected directly to the 8080 series MPUs and the
6800 series MPUs)
• High-speed Serial interface are supported.
• Abundant command functions
Display data Read/Write, display ON/OFF, Normal/
Reverse display mode, page address set,
display start line set, column address set, display all
points ON/OFF, LCD bias set, electronic
volume, read/modify/write, segment driver direction
select, power saver, common driver
direction select, V0 voltage regulation internal
resistor ratio set.
• Low-power liquid crystal display power supply circuit
equipped internally.
Booster circuit(with Boost ratios of Double/Triple/
Quad, where the step-up voltage reference power
supply can be input externally)
• High-accuracy voltage adjustment circuit
(Thermal gradient –0.1%/°C)
• V0 voltage divider resistors equipped internally,
V1 to V4 voltage divider resistors equipped internally,
electronic volume function equipped internally,
voltage follower.
• Component that can be omitted (you may omit the
smoothing capacitor on the voltage follower).
• CR oscillator circuit equipped internally(external clock
can also be input)
• Extremely low power consumption
Operating power when the built-in power supply is
used(an example)
S1D15A06D00B* (79µA)
Condition : VDD–VSS = 1.8V, VDD2–VSS = 3.3V,V0–
VSS = 9.0V, triple boosting, all white is
displayed, Ta = 25°C
• Power supply
Operable on the low 1.8 voltage
Logic power supply : VDD–VSS = 1.8V to 3.6V
Boost reference voltage : VDD2 –VSS = 1.8V to 5.0V
Liquid crystal drive power supply : V0–VSS = 4.5V
to 9.0V
• Wide range of operating temperatures : -40 to +85°C
• CMOS process
• Shipping forms include bare chip and TCP.
• There chip not designed for resistance to light or
resistance to radiation.
Series Specifications
Product
Name
Duty
S1D15A06D00B* 1/55
*S1D15A06D01B* 1/55
*S1D15A06D02B* 1/55
*S1D15A06T00** 1/55
Rev. 1.0a
Bias
1/6,1/8
1/6,1/8
1/6,1/8
1/6,1/8
SEG Dr COM Dr
102
102
102
102
55
55
55
55
VREG Temperature
Gradient
–0.1%/°C
–0.1%/°C
–0.1%/°C
–0.1%/°C
EPSON
Power supply specification
Shipping
Forms
Built-in power supply is only used
Bare Chip
V0 or VOUT External supply voltage follower is used Bare Chip
External power supply is only used Bare Chip
TCP
* : Being planned
12–1
S1D15A06 Series
COMS
• • • • • • • • • •
COM53
COM0
• • • • • • • • • • • • • • • • • • • • • • • • •
SEG101
SEG0
3. BLOCK DIAGRAM
VDD
V1
V2
SEG Drivers
COMS
V0
COM Drivers
V3
V4
VSS
Shift register
Display data latch circuit
CAP1+
Line address
Display timing generator circuit
VR
I/O buffer
VDD2
Page address
VOUT
Power supply circuit
CAP1–
CAP2+
CAP2–
CAP3+
Display data RAM
102 x 65
Oscillator circuit
Command decoder
Bus holder
CL
Command decoder
12–2
EPSON
D0
D1
D2
D3
D4
D5
D6 (SCL)
D7 (SI)
RES
C86
P/S
WR (R/W)
RD (E)
A0
CS
MPU Interface
Rev. 1.0a
S1D15A06 Series
4. PIN LAYOUT
73
1
74
247
S1D15A06 Series
Die No.
(0, 0)
D15A6xxx
221
100
101
220
Chip Size
Chip Thickness
Bump Pitch
Bump Size PAD No.1 to 73
PAD No.74
PAD No.75 to 99
PAD No.100
PAD No.101 to 220
PAD No.221
PAD No.222 to 246
PAD No.247
Bump Height
Rev. 1.0a
EPSON
Size
X
Y
9.93 × 2.15
0.625
70 (Min.)
85 × 85
85 × 74
85 × 45
85 × 74
52 × 85
85 × 74
85 × 45
85 × 74
17 (Typ.)
Unit
mm
mm
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
12–3
S1D15A06 Series
S1D15A06***** Pad Center Coordinates
Units: µm
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
12–4
Pin
Name
(NC)
TEST0
TEST1
VSS
TEST2
TEST3
RES
CS
VSS
WR(R/W)
RD(E)
VDD
CL
A0
D7(SI)
D6(SCL)
D5
D4
D3
D2
D1
D0
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD
P/S
C86
VSS
TEST4
TEST5
TEST6
VSS
VSS
VSS
TEST7
TEST8
TEST9
TEST10
VOUT
VOUT
VOUT
VSS
VR
V0
V1
V2
X
Y
4570
4449
4300
4151
4030
3910
3789
3668
3547
3427
3306
3185
3065
2944
2823
2703
2582
2461
2340
2220
2099
1978
1858
1737
1616
1496
1375
1254
1133
1013
892
771
651
474
297
120
0
–121
–298
–475
–652
–828
–949
–1070
–1190
–1311
–1432
–1553
–1673
–1794
921
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
Name
V3
V4
CAP2+
CAP2+
(NC)
(NC)
(NC)
(NC)
(NC)
CAP2–
CAP2–
(NC)
(NC)
(NC)
(NC)
CAP1+
CAP1+
CAP1–
CAP1–
CAP3+
CAP3+
VOUT
(NC)
(NC)
COMS
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
(NC)
X
Y
–1915
–2035
–2156
–2277
–2397
–2518
–2639
–2760
–2880
–3001
–3122
–3242
–3363
–3484
–3604
–3725
–3864
–3967
–4087
–4208
–4329
–4449
–4570
–4808
921
EPSON
926
842
771
701
631
561
491
421
351
281
210
140
70
0
–70
–140
–210
–281
–351
–421
–491
–561
–631
–701
–771
–842
–926
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Pin
Name
(NC)
(NC)
COM2
COM1
COM0
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
X
Y
–4623 –921
–4545
–4467
–4389
–4312
–4234
–4156
–4079
–4001
–3923
–3846
–3768
–3690
–3613
–3535
–3457
–3380
–3302
–3224
–3146
–3069
–2991
–2913
–2836
–2758
–2680
–2603
–2525
–2447
–2370
–2292
–2214
–2136
–2059
–1981
–1903
–1826
–1748
–1670
–1593
–1515
–1437
–1360
–1282
–1204
–1127
–1049
–971
–893
–816
Rev. 1.0a
S1D15A06 Series
Units: µm
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Pin
Name
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
Rev. 1.0a
X
Y
–738
–660
–583
–505
–427
–350
–272
–194
–117
–39
39
117
194
272
350
427
505
583
660
738
816
893
971
1049
1127
1204
1282
1360
1437
1515
1593
1670
1748
1826
1903
1981
2059
2136
2214
2292
2370
2447
2525
2603
2680
2758
2836
2913
2991
3069
–921
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
Pin
Name
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
(NC)
(NC)
(NC)
(NC)
COM27
COM28
COM29
(NC)
(NC)
(NC)
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COMS
(NC)
X
Y
3146
3224
3302
3380
3457
3535
3613
3690
3768
3846
3923
4001
4079
4156
4234
4312
4389
4467
4545
4623
4808
–921
EPSON
–926
–842
–771
–701
–631
–561
–491
–421
–351
–281
–210
–140
–70
0
70
140
210
281
351
421
491
561
631
701
771
842
926
12–5
S1D15A06 Series
5. PIN DESCRIPTION
Power supply pins
Name
I/O
Description
VDD
VDD2
VSS
V0 , V1 , V2
V3 , V4
Supply
Supply
Supply
Supply
Power supply. Connect to MPU power pin VCC .
Externally-input reference power supply for booster circuit.
This is a 0V terminal connected to the system GND.
Multi-level power supply for LCD drive. The voltages are
determined by LCD cell.The voltages should maintain the following
relationship : V0 >= V1 >= V2 >= V3 >= V4 >= VSS.
When on-chip power supply circuit turns on, V0 voltage are
generated, and the following voltages are generated to V1 to V 4.
Either voltage can be selected by LCD bias set command.
V1
V2
V3
V4
Number of
pins
5
3
7
5
S1D15A06 *****
5/6 • V 0, 7/8 • V0
4/6 • V 0, 6/8 • V0
2/6 • V 0, 2/8 • V0
1/6 • V 0, 1/8 • V0
LCD power supply circuit pins
Name
I/O
CAP1+
O
CAP1-
O
CAP2+
O
CAP2-
O
CAP3+
O
VOUT
VR
O
I
12–6
Description
Boosting capacitor positive connection pin.
Capacitor is connected across CAP1- pins.
Boosting capacitor negative connection pin.
Capacitor is connected across CAP1+ pins.
Boosting capacitor positive connection pin.
Capacitor is connected across CAP2- pins.
Boosting capacitor negative connection pin.
Capacitor is connected across CAP2+ pins.
Boosting capacitor positive connection pin.
Capacitor is connected across CAP1- pins.
Booster output. Capacitor is connected across VSS or VDD2.
Voltage adjustment pin. Provides V0 voltage using external
resistors. When internal resistors are used, this pin cannot be used.
Operable only when the built-in resistor for
V0 adjustment is not used.
[V0 resistance ratio is (D2, D1, D0) = (1.1.1)]
This pin is disabled when the built-in resistor for
V0 adjustment is used.
This pin must be open in this case.
EPSON
Number of
pins
2
2
2
2
2
4
1
Rev. 1.0a
S1D15A06 Series
System bus connection pins
Pin name
I/O
D7 to D0
(SL)
(SCL)
I/O
A0
I
CS
I
I
RES
RD
(E)
I
WR
(R/W)
I
C86
I
P/S
I
Description
8-bit bi-directional data bus to be connected to the standard 8-bit or
16-bit MPU data bus.
When the serial interface is selected (P/S=LOW) ;
D7 : Serial data input (SI)
D6 : Serial clock input (SCL)
At this time, D0 through D5 will go under the Hz mode.
When the chip selects are in non-active state, D0 through D7 will
go under the Hz mode.
Control/data flag input.
A0=HIGH : The data on D7 to D0 is display data.
A0=LOW : The data on D7 to D0 is control data.
Chip select input. Data input is enable when CS is low.
When RES is caused to go low, initialization is executed.
A reset operation is performed at the signal level.
• When connected to an 8080-series MPU ;
This is active-LOW. This pin is connected to the RD signal of the
8080-series MPU. While this signal is low, S1D15A06 series data
bus in an output status.
• When connected to an 6800-series MPU ;
This is active-HIGH. This is used as an enable clock input pin of
the 6800-series MPU.
• When connected to an 8080-series MPU ;
This is active-LOW. This pin is connected to the WR signal of the
8080-series MPU. The signals on the data bus are latched at the
rising edge of the WR signal.
• When connected to an 6800-series MPU ;
This is the read/write control signal input .
R/W=HIGH : Read.
R/W=LOW : Write.
MPU interface selection pin.
C86=HIGH : 6800-series MPU interface
C86=LOW : 8080-series MPU interface
Serial data input/parallel data input selection pin.
P/S=HIGH : Parallel data input
P/S=LOW : Serial data input
The following applies depending on the P/S status :
P/S Data/Command
Data
Read/Write
HIGH
A0
D7 to D0
RD, WR
LOW
A0
SI (D7)
Write only
Number of
pins
8
1
1
1
1
1
1
1
Serial Clock
–
SCL (D6)
In serial mode, no data can be read from DDRAM.
When P/S=LOW,D5 to D0 are HZ. D5 to D0 may be HIGH, LOW or
Open, and moreover A0, RD, WR, C86 may be HIGH or LOW.
Rev. 1.0a
EPSON
12–7
S1D15A06 Series
LCD driver pins
Name
I/O
CL
I
SEG0
to SEG101
O
Description
This pin is used for enabling or disabling the built-in oscillation
circuit for the display clock.
CL = HIGH: Built-in oscillation circuit is enabled.
CL = LOW: Built-in oscillation circuit (external input) is disabled.
Select CL = LOW to turn the external clock off.
When using the built-in oscillation circuit, select CL = HIGH (VDD).
These pins output the signal for the segment drive of LCD.
One of V0, V 2, V 3 and VSS levels is selected depending on
a given combination of display RAM data and internal FR signal.
Number of
pins
1
102
Output voltage
Internal FR
signal
Normal display Reversing display
HIGH
HIGH
V0
V2
HIGH
LOW
VSS
V3
LOW
HIGH
V2
V0
LOW
LOW
V3
VSS
Power save
–
VSS
RAM data
COM0
to COM53
O
These pins output the signal for the common drive of LCD.
Following number of pins are assigned to S1D15A06*****.
Model
S1D15A06*****
COM
COM0~COM53
54
Number of COM pins
54
One of V0, V 1, V 4 and VSS levels is selected depending on
a given combination of scan data and FR signal.
Scan data
HIGH
HIGH
LOW
LOW
Power save
COMS
O
FR
HIGH
LOW
HIGH
LOW
–
Output voltage
VSS
V0
V1
V4
VSS
They are COM pins exclusively used for the indicator.
Both pins output the same signal.
They must be made open when not used.
2
Test pins
Name
TEST0
to 10
I/O
I/O
Description
These are terminals for IC chip testing. They are set to OPEN.
Number of
pins
11
Total : 220 pins for the S1D15A06*****.
Note and caution
• If control signal from MPU is Hz,an over-current may flow through the IC. A protection is required to prevent the Hz
signal at the input pins.
12–8
EPSON
Rev. 1.0a
S1D15A06 Series
6. FUNCTIONAL DESCRIPTION
Microprocessor Interface
Interface type selection
The S1D15A06 series can transfer data via 8-bit bidirectional data buses (D7 to D0) or via serial data input
(SI). Through selecting the P/S pin polarity to the HIGH
or LOW, it is possible to select either 8-bit parallel data
input or serial data input as shown in Table 1.
Table 1
P/S
CS
A0
RD
WR
C86
D7
D6
D5 to D0
HIGH:Parallel Input
CS
A0
RD
WR
C86
D7
D6
D5 to D0
LOW:Serial Input
CS
A0
–
–
–
SI
SCL
–
– : Must always be HIGH or LOW
Parallel interface
When the parallel interface has been selected (P/S
=HIGH), then it is possible to connect directly to either
an 8080-series MPU or a 6800-series MPU (as shown in
Table 2) by selecting C86 pin to either HIGH or LOW.
Table 2
C86
CS
A0
RD
WR
D7 to D0
HIGH:6800-series MPU bus
CS
A0
E
R/W
D7 to D0
LOW:8080-series MPU bus
CS
A0
RD
WR
D7 to D0
Moreover, the S1D15A06 series identifies the data bus
signal according to A0, RD(E), WR(R/W)signals, as
shown in Table 3.
Table 3
Common
6800-series
8080-series
A0
R/W
RD
WR
1
1
0
1
Reads the display data
1
0
1
0
Writes the display data
0
1
1
0
Writes control data (command)
Serial interface
When the serial interface has been selected (P/S=LOW)
then when the chip is in active state(CS=LOW) the
serial data input (SI) and the serial clock input (SCL)
can be received.
The serial data is read from the serial data input pin in
the rising edge of the serial clocks D7, D6 through D0,
in this order. This data is converted to 8 bits parallel data
in the rising edge of the eighth serial clock for the
processing.
Rev. 1.0a
Function
The A0 input is used to determine whether the serial
data input is display data or command data; when
A0=HIGH, the data is display data, and when A0=LOW
then the data is command data.
The A0 input is read and used for detection every 8th
rising edge of the serial clock after the chip becomes
active.
Figure 1 is a serial interface signal chart.
EPSON
12–9
S1D15A06 Series
CS
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
D5
D4
D3
D2
13
14
SCL
11
12
A0
Figure 1
* When the chip is inactive, the shift register and the counter is reset to the initial state.
* Data read is not available as long as the serial interface is selected.
* Reasonable care must be exercised so that SCL signal may not be exposed undesirable effects resulting from, for
instance, terminal reflection of wiring or external noises. Before using the signal, it is recommended to test the signal
in actual system.
S1D15A06 series can perform a type of pipeline
processing between LSIs using bus holder of internal
data bus when data is sent from/to the MPU. For
example, when the MPU writes data to the DDRAM,
once the data is stored in the bus holder, then it is written
to the DDRAM before the next data write cycle. And
when the MPU reads the contents of the DDRAM, the
first data read cycle (dummy read cycle) stores the read
data in the bus holder, and then the data is read from the
bus holder to the system bus at the next data read cycle.
Thus,there is a certain restriction in the DDRAM read
sequence. When an address is set, the specified address
data is NOT output at the immediately following read
instruction. The address data is output during second
data read. A single dummy read must be inserted after
address setup and after write cycle (refer to Figure 2).
Chip select input
The MPU interface (either papallel or serial) is enabled
only when CS=LOW.
When the chip select is inactive, D7 to D0 enter a high
impedance state, and A0, RD and WR inputs are disabled.
When the serial interface is selected, the shift register
and the counter are reset.
Access to DDRAM and internal registers
In accessing the DDRAM and the internal registers of
the S1D15A06 series,the MPU is required to satisfy the
only cycle time (tCYC),and is not needed to consider the
wait time. Accordingly, it is possible to transfer data at
higher speed.
In order to realize the higher speed accessing, the
Write
MPU
WR
Data
N
N+1
N+2
N+3
Latch
Internal Timing
N
BUS Holder
N+1
N+2
N+3
Write Signal
Read
MPU
WR
RD
Data
N
N
n
n+1
Internal Timing
Adsress Preset
Read Signal
Column Adsress
Preset
Write Signal
N
Increment N+1
N
Address Set
#n
n
Dummy
Read
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
Figure 2
12–10
EPSON
Rev. 1.0a
S1D15A06 Series
DDRAM
DDRAM and page/column address circuit
The DDRAM stores pixel data for LCD. It is a 65-row
(8 page by 8 bit + 1) by 102-column addressable array.
As is shown in Figure 3, the D7 to D0 display data from
the MPU corresponds to the LCD common direction.
Moreover, reading from and writing to the display
RAM from the MPU side is performed through the I/O
buffer, which is an independent operation from signal
reading for the liquid crystal driver. Consequently,
even if the display data RAM is accessed asynchronously
during liquid crystal display, it will not cause adverse
effects on the display (such as flickering).
D0
0 1 1 1
0
COM0
D1
1 0 0 0
0
COM1
D2
0 0 0 0
0
COM2
D3
0 1 1 1
0
COM3
D4
1 0 0 0
0
COM4
—
—
DDRAM
Display on LCD
Figure 3
Page address circuit
Each pixel can be selected when page address and
column address are specified(refer to Figure 5).
The MPU issues Page address set command to change
the page and access to another page. Page address 8
(D3,D2,D1,D0 = 1,0,0,0) is DDRAM area dedicate to
the indicator, and display data D0 is only valid.
The DDRAM column address is specified by Column
address set command.The specified column address is
automatically incremented by +1 when a Display data
read/write command is entered. After the last column
address (65H) ,column address returns to 00H and page
address incremented by +1 (refer to Figure 4). After the
very last address (column = 65H,page = 7H),both column
address and page address return to 00H (column address
= 00H, page address = 0H).
Data
D0
D1
D2
D3
D4
D5
D6
0H
0
1
2
100
101
D7
1H
102
103
104
202
203
2H
204
205
206
304
305
3H
306
307
308
406
407
4H
408
409
410
508
509
5H
510
511
512
610
611
6H
612
613
614
712
713
7H
714
715
716
814
815
00H
01H
02H
64H
65H
Page address
8H
Column address
Figure 4
Rev. 1.0a
EPSON
12–11
S1D15A06 Series
Column address circuit
Designate the column side address of the indication data
RAM as shown in Fig. 5, using the column address
setting command. Since the designated column address
increments (+1) each time an indication data•read/write
command is input, the MPU can make access to the
indication data in succession.
Also, as shown in Fig. 4, after an access has been made
to the final column address (65H), the column address
will return to (00H) and the page address will be
automatically incremented (by +1). Thanks to this
feature, it is possible to write continuous data being
divided between adjoining pages. Furthermore, after
accesses have been made to the final addresses of both
of the page and column (column = 65H and page = 7H),
both of the column address and the page address returns
to (00H).
(The page will not increment to “8H”. Therefore, be
careful when executing “read•modify•write” processes.)
Also, as shown in Table 4, the correlation between the
column address of the indication data RAM and the
segment output can be reversed by use of the ADC
command (segment driver direction select command).
Thanks to this feature, IC layout limitations when
constituting an LCD module can be lessened.
Table 4
Column Address
00H
01H
02H
63H
64H
65H
Normal Direction
SEG0
SEG1
SEG2
SEG99
SEG100
SEG101
Reverse Direction
SEG101
SEG100
SEG99
SEG2
SEG1
SEG0
Line address circuit
The line address circuit specifies the line address (as
shown Figure 5) relating to the COM output when the
contents of the DDRAM are displayed. The display start
line address, what is normally the top line of the display,
can be specified by Display start line address set
command. And Common driver direction select
command can be used to reverse the relationship between
the DDRAM line address and common output. For
example, as is shown in Table 5, the display start line
address corresponds to the COM0 output when the
common driver direction is normal, or the COM53
output when common driver direction is reversed.And
the display area is followed by the higher number line
addresses in ascending order from the display start line
address, corresponding to the duty cycle. This allows
flexible IC layout during LCD module assembly.
If the display start line address is changed dynamically
using the Display start line address set command,then
screen scrolling and page swapping can be performed.
Table 5 (at display start line address=1CH)
Line Address
1CH
1DH
3FH
00H
11H
12H
Normal Direction
COM0
COM1
COM35
COM36
COM52
COM53
Reverse Direction
COM53
COM52
COM18
COM17
COM1
COM0
Display data latch circuit
The display data latch circuit is a latch temporarily
stored the display data that is output to the LCD driver
circuit from the DDRAM.
Display ON/OFF command, Display normal/reverse
12–12
command, and Displayd all points ON/OFF command
control only the data within the latch,and do not change
the data within the DDRAM.
EPSON
Rev. 1.0a
S1D15A06 Series
Display data RAM
The display data RAM stores pixel data for the LCD. It
is a 102-column × 65-row addressable array as shown in
Figure 5.
Page Address
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
Normal Direction
Reverse Direction
SEG
Output
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
1
0
0
Column Address
Line
Address
Data
Start
COM Output
Normal Reverse
Direction Direction
COM0 COM53
COM1 COM52
COM2 COM51
COM3 COM50
COM4 COM49
COM5 COM48
COM6 COM47
COM7 COM46
COM8 COM45
COM9 COM44
COM10 COM43
COM11 COM42
COM12 COM41
COM13 COM40
COM14 COM39
COM15 COM38
COM16 COM37
COM17 COM36
COM18 COM35
COM19 COM34
COM20 COM33
COM21 COM32
COM22 COM31
COM23 COM30
COM24 COM29
COM25 COM28
COM26 COM27
COM27 COM26
COM28 COM25
COM29 COM24
COM30 COM23
COM31 COM22
COM32 COM21
COM33 COM20
COM34 COM19
COM35 COM18
COM36 COM17
COM37 COM16
COM38 COM15
COM39 COM14
COM40 COM13
COM41 COM12
COM42 COM11
COM43 COM10
COM44 COM9
COM45 COM8
COM46 COM7
COM47 COM6
COM48 COM5
COM49 COM4
COM50 COM3
COM51 COM2
COM52 COM1
COM53 COM0
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COMS COMS
5FH 60H 61H 62H 63H 64H 65H
SEG6 SEG95
SEG5 SEG96
SEG4 SEG97
SEG3 SEG98
SEG2 SEG99
SEG1 SEG100
SEG0 SEG101
D3
Regardless of the display start
line address, S1D15A06
accesses 55th line.
Figure 5
Rev. 1.0a
EPSON
12–13
S1D15A06 Series
Oscillation circuit
The S1D15A06 series generates display clocks using its
built-in CR oscillation circuit. The built-in oscillation
circuit is enabled when CL = HIGH is selected and the
power save mode is turned off.
You can stop operation of the CR oscillation circuit by
selecting CL = LOW. Display clock can be externally
entered via CL pin (when external clock is turned off,
CL pin must be placed in LOW).
Table 6
CL
HIGH
LOW
Clock input
Operation
Built-in CR oscillation circuit is enabled.
Built-in CR oscillation circuit is turned off [display clock is turned off].
External clock input mode
Table 7 shows relationship between frequency of external clock (fCL), frequency of built-in clock circuit (fOSC)
and fFR.
Since CL pin is used for resetting the built-in CR clock
circuit, it must satisfy the fCL requirements given in the
"DC Characteristics".
Table 7
Item
S1D15A06***** When built-in oscillation circuit is used
When external clock input is used
Display timing generator circuit
The display timing generator circuit generates the timing
signal to the line address circuit and the display data
latch circuit, and generates COM scan signal and the
LCD AC signal (dual-frame AC driver waveform).
12–14
fFR computation formula
fFR=fOSC / (55×8) [Hz]
fFR=fCL / (55×16) [Hz]
LCD driver circuits
These are multiplexers outputting the LCD panel driving
4-level signal which level is determined by a combination
of display data, COM scan signal, and LCD AC signal
(FR). Figure 6 shows an example of SEG and COM
output waveforms.
EPSON
Rev. 1.0a
S1D15A06 Series
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
VDD
VSS
FR
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
COM0
COM1
COM2
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
SEG0
SEG1
SEG2
V5
V4
V3
V2
V1
VDD
—V1
—V2
—V3
—V4
—V5
COM0—SEG0
V5
V4
V3
V2
V1
VDD
—V1
—V2
COM0—SEG1
—V3
—V4
—V5
Figure 6
Rev. 1.0a
EPSON
12–15
S1D15A06 Series
Power supply circuit
The power supply circuit generates the voltage to drive
the LCD panel at low power consumption.
The power supply circuit consists of a booster circuit,
voltage regulator circuit, and voltage follower circuit,
and is controlled by Power control set command. Using
this command, the booster circuit, the voltage regulator
circuit, and the voltage follower circuit can be independently turned ON or OFF. Consequently, the external
power supply and part of internal power supply circuit
functions can be used simultaneously. Table 8 shows
reference combinations.
Table 8 lists the functions controllable from 3 bits data
of the power control set command. And, Table 9 shows
sample combinations of the bits.
Select the models depending on the state of use.
Table 8
State
Item
“1”
ON
ON
ON
D2 Booster circuit control bit
D1 Voltage adjusting circuit (V adjusting circuit) control bit
D0 Voltage follower circuit (V/F circuit) control bit
“0”
OFF
OFF
OFF
Table 9
Usage
Built-in power supply alone is used
V adjusting and
V/F circuits alone are used
V/F circuit alone is used
External power supply alone is used
*1
*2
*2
1
0
1
1
1
1
ON
OFF
ON
ON
ON
ON
External
voltage
entered.
V DD2
VOUT *4
0
0
1
OFF
OFF
ON
V0 *4
OPEN
*3
0
0
0
OFF
OFF
OFF
V0 to V 4 *4
OPEN
Model D2 D1 D0
Booster V adjusting
V/F
circuit.
circuit.
circuit.
Pins on
booster
circuit
Used
OPEN
* Pins on the booster circuits denote CAP1+, CAP1-, CAP2+, CAP2- and CAP3+ pins.
* Although other combinations than the above are available, they are not pragmatic and thus not recommendable.
*1: S1D15A06D00B*
*2: S1D15A06D01B* *3: S1D15A06D02B*
*4: VDD2 is recommended to short-circuit to VDD
Booster circuit
Using the booster circuit, it is possible to produce Quad/
Triple/Double boosting of the VDD2 –VSS voltage level.
Quad boosting : If capacitor are inserted between CAP1+
and CAP1-, between CAP2+ and CAP2-, between
CAP3+ and CAP1-, between V OUT and V DD2 , the
potential between VDD2 and VSS is boosted to quadruple
toward the positive side and it is output at VOUT pin.
Triple boosting : If capacitor are inserted between
CAP1+ and CAP1-, between CAP2+ and CAP2-,
12–16
between V OUT and VDD2 , and jumper between CAP3+
and V OUT, the triple boosted voltage appears at VOUT
pin.
Double boosting : If capacitor are inserted between
CAP1+ and CAP1-, between V OUT and VDD2 , open
CAP2-, and jumper between CAP2+, CAP3+ and VOUT,
the double boosted voltage appears at VOUT pin.
The boosted voltage relationships are shown in Figure
7.
EPSON
Rev. 1.0a
S1D15A06 Series
+
CAP3+
CAP1–
+
CAP1+
CAP2–
+
+
CAP2+
Qualruple Boosting
VOUT = 4 x VDD2
= 7.2V
VDD2
+
VOUT
CAP3+
CAP1–
+
CAP1+
CAP2–
+
VOUT
CAP3+
CAP1–
+
CAP1+
CAP2–
OPEN
CAP2+
CAP2+
Triple Boosting
Double boosting
VOUT = 3 x VDD2
= 9.0V
VOUT = 2 x VDD2
= 6.0V
VDD2 = 1.8V
VDD2 = 3.0V
VDD2 = 3.0V
VSS = 0V
VSS = 0V
VSS = 0V
Qualruple Boosting
S1D15A06 Series
VOUT
S1D15A06 Series
+
VDD2
S1D15A06 Series
VDD2
Triple Boosting
Double boosting
Figure 7
*VDD2 voltage must be set so that V OUT voltage does not exceed the absolute maximun rated value.
*The Capacitance depend on the load of the LCD panel to be driven. Set a value that LCD driver voltage may be stable
(reference value = 1.0 to 4.7µF).
Voltage regulator circuit
The boosting voltage occurring at the VOUT pin is sent
to the voltage regulator, and the V0 voltage (LCD driver
voltage) is output.
Because the S1D15A06 series has the high-accuracy
constant voltage source, the 32-level electronic volume
function and the internal resistor for the V0 voltage
regulator (= V0-resistor), it is possible to construct a
high-accuracy voltage regulator circuit without external
component. And V 0 voltage can be adjusted by
commands only to adjust the LCD contrast.
Rev. 1.0a
The V0 voltage can be calculated using the following
equation within the range of V 0 < VOUT.
V0 = (1+Rb/Ra)•VEV
= (1+Rb/Ra)•(1– α /200)VREG (Expression A-1)
VEV = (1– α /200) •VREG
VREG is the on-chip constant voltage as shown in Table
10 at Ta=25°C.
Table 10
EPSON
Model
VREG
Thermal Gradient
S1D15A06D**
1.2V
–0.1%/°C
12–17
S1D15A06 Series
Internal Rb
+
V0
–
VEV (Constant voltage source
+ electronic volume)
Internal Ra
VSS
Figure 8
α is a value of the electronic volume, and can be set to
one of 32-states by Electronic volume command setting
the 5-bit data in the electronic volume register.Table 11
shows the value of α.
Table 12
Table 11
D4
D3
D2
D1
D0
α
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
:
:
1
1
1
1
0
0
1
1
0
1
0
1
31
30
29
:
:
3
2
1
0
1+Rb/Ra
Rb/Ra is the V0-resistor ratio, and can be set to one of 7states by V0-resistor ratio set command setting the 3-bit
D3
D2
D1
SED15A6 (Typ.)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5.45
5.71
6.00
6.32
6.67
7.06
7.50
External resistor can be used.
data in the V 0-resistor ratio register. Table 12 shows the
value of (1+Rb/Ra) ratio (reference value).
10
9
8
V0[V]
7
6
5
4
3
0
1
2
3
4
5
2
6
1
0
0
8
16
24
32
Electric Volume Resister [Decimal]
Figure 9 The V0 voltage as a function of the V0 voltage regulator internal
resister internal resistor and the electronic volume register [Ta=25°C]
12–18
EPSON
Rev. 1.0a
S1D15A06 Series
<Setup example : When setting Ta = 25C and V 0 = 7V
on an S1D15A06***** model with temperature gradient of –0.1% /˚C>
From Figure 9 and expression A-1, the following setting
will be employed.
Table 13
Content
D7
0
1
Resistance ratio of V 0 adjusting built-in resistors
Electronic volume
Table 14 shows V 0 voltage variable range and its variable step available from the electronic volume function
D6
0
0
D5
1
0
Resistors
D4 D3 D2
0
0
0
1
0
0
D1
1
0
D0
1
0
when the above setting is employed.
Table 14
V0
Variable range
Variable step
Min.
6.41[80H]
to
Typ.
7.0[90H]
37.92
to
Max.
7.58[9FH]
Unit
[V]
[mV]
[ ]: Commands selected from the electronic volume.
When external resistor is used (when the builtin resistor for V0 adjustment is not used)
It is also possible to select a supply voltage V0 for LCD
without using the built-in V0 voltage adjusting resistors
(resistance ratio select command [27H] for the built-in
V0 voltage adjusting resistors) by adding a resistor across
VSS and VR as well as VR and V0. In this case too, using
the electronic volume allows you to control LCD V 0
through the command and, thus, adjust contrast of LCD
display.
Voltage V0 is given by the following expression when
external resistance values Ra' and Rb' are specified in
the range of V0 < VOUT:
V0 = (1+Rb/Ra)•VEV
= (1+Rb/Ra)•(1– α /200)VREG (Expression B-1)
VEV = (1– α /200) •VREG
VREG represents the constant voltage source on the IC.
Its value at Ta = 25°C is constant as shown in Table 10.
External Rb'
+
VR
V0
–
External Ra'
VEV (Constant voltage source
+ electronic volume)
VSS
Figure 10
Rev. 1.0a
EPSON
12–19
S1D15A06 Series
Rb', the following expression is derived:
Ra' + Rb' = 1.4MΩ
(Expression B-3)
Thus, the following is derived from expressions B-2 and
B-3:
Rb' / Ra' = 5.31
∴Ra' = 220kΩ, Rb' = 1180kΩ
Table 14 shows the command selected from the electronic volume. Table 16 lists V0 voltage variable range
and variable steps available from the electronic volume
function.
<A setting example: When setting Ta = 25C and V 0 =
7V on an S1D15A06***** model with temperature
gradient =–0.1% C>
When the intermediate resistor values (D4, D3, D2, D1,
D0) = (1, 0, 0, 0) are selected from the electronic volume, the following is given by expression B-1 since α =
15 and V REG = 1.2V (Expression B-2).
V0 = (1+Rb'/Ra') • (1– α /200) • VREG
7V = (1+Rb'/Ra') • (1– 15 /200) • 1.2
(Expression B-2)
If you select 5 µA for the current conducted to Ra' and
Table 15
Content
D7
0
1
Resistance ratio of built-in V0 voltage adjusting resistors
Electronic volume
D6
0
0
D5
1
0
Resistors
D4 D3 D2
0
0
1
1
0
0
D1
1
0
D0
1
0
Table 16
V0
Variable range
Variable step
Min.
6.45[80H]
Typ.
7.0[90H]
38.4
to
to
Max.
7.64[9FH]
Unit
[V]
[mV]
[ ]: Commands selected from the electronic volume.
When using external resistors (When using variable resistors in stead of the built-in V0 voltage
adjusting resistors)
Adding external variable resistors to the above mentioned
external resistors allows you to select an LCD drive voltage V0 through fine tuning of Ra' and Rb'. In this case
too, using the electronic volume function permits you to
control an LCD voltage through the command and, thus,
adjust contrast of the LCD display.
You can determine the V0 voltage from the following
expression when fine adjustment of Ra' and Rb' is done
Rb'
External
resistor R3
External
resistor R2
Ra'
by specifying resistance values of external resistors R1
and R2 (variable resistors) and R3 within the range of
| V0 | < | VOUT | :
V0 = {1+(R3+R2–∆R2) / (R1+∆R2)} • VEV
= {1+(R3+R2–∆R2) / (R1+∆R2)} •
(1– α/200) • VREG
(Expression C-1)
[VEV = (1–α/200) • VREG]
Where, VREG is the constant voltage source in the IC and
its value remains at a constant level as shown in Table
10.
External
resistor R1
R1
+
VR
V0
–
VEV (Constant voltage source
+ electronic volume)
VSS
Figure 11
12–20
EPSON
Rev. 1.0a
S1D15A06 Series
<A setting example: When setting Ta = 25C and V0 = 5
to 9V on an S1D15A06***** model with Temperature gradient = –0.1% C>
α = 15 and VREG = 1.2V when intermediate resistor values (D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0) are selected
from the electronic volume. Thus, using expression C1, you can select V0 = 9V when ∆R2 = 0Ω in the following manner:
9V ={1+(R3+R2) / R1} • (1–15/200) • 1.2
R3 + R2=7.11 • R1
(Expression C-2)
If you select 5 uA for the current to be conducted across
V0 and VSS when V0 = 7V, sum of resistance of R1, R2
and R3 can be derived as shown below:
R1 + R2 + R3 = 1.4MΩ
(Expression C-3).
From expressions C-2 and C-3, R1 = 1.4MΩ /
8.11=173kΩ.
And, you can select V = 5V when ∆R2 = R2 through the
following computation:
5V = ={1+R3/(R1+R2) } • (1–15/200) • 1.2
R3/(R1 + R2) = 3.5
(Expression C-4).
R2 = [email protected] and R3 = 1.09 MΩ are derived from expressions C-2, C-3 and C-4.
Table 15 lists the commands used, and Table 17 shows
V0 voltage variable voltage range and variable steps available from the electronic volume.
Table 17
V0
Variable range
Variable step
Min.
6.39[80H]
Typ.
7.0[90H]
38.1
to
Max.
7.57[9FH]
to
Unit
[V]
[mV]
[ ]: Commands selected from the electronic volume.
* When using the built-in V0 voltage adjusting resistors or the electronic volume function, both of the voltage adjustment circuit and the voltage follower circuit must be activated, as a minimum requirement, by the power control set
command. When the booster is circuit is turned off, necessary voltage must be supplied from VOUT.
* VR pin is enabled only when the built-in V0 voltage adjusting resistors are not used. VR pin must be made open when
these resistors are used.
* Since VR pin has a higher input impedance, appropriate noise protection measures must provided including cutting the
wiring distance shorter or using shielded wire.
save mode employing the following command sequence.
You can also turn the built-in power supply off by initializing it using RES pin or the reset command. Here,
of S1D15A06D00B*with built-in power supply being
only used, LOW level signal entering RES pin discharges
VOUT, thereby introducing shorting across VOUT–VDD2
and V0–VSS. Of S1D15A06D01B*/S1D15A06D02B*
with external power supply being used, discharge the
electric charge by short-circuiting the external power
supply to VSS when the power supply is off or power is
being saved. (VOUT and V0 electric charge discharging
functions are not in the IC)
Voltage Follower Circuit
The V0 voltage is divided to generate the V1, V2, V3 and
V4 voltages by on-chip resistor circuit. And the V1, V2,
V3 and V4 voltages are impedance-converted by voltage
follower, and provide to LCD driver circuit.
LCD bias ratio can be selected by LCD bias set command
which is 1/6 bias or 1/8 bias for S1D15A06 series.
On-chip Power Supply Turn Off Sequence
Before turning the built-in power supply off, to discharge
the remaining electric charge of LCD panel and power
supply PIN etc., it is recommended to turn on the power
Table 18
Sequence
Step1
Step2
End
Rev. 1.0a
Contents
(command and state)
Display OFF
↓
Display all points on
↓
Built-in power OFF
Command address
D5 D4 D3 D2 D1
1
0
1
1
1
D7
1
D6
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
EPSON
D0
0
Power save
command
(composite
command)
12–21
S1D15A06 Series
Sample Circuits
1. When the booster, voltage adjustment and V/F circuits are all used [S1D15A06D00B*]
(1) When built-in V0 voltage adjusting resistors are used
(When VDD2 = VDD is boosted 4 times)
(2) When built-in V0 voltage adjusting resistors are not
used (When VDD2 = VDD boosted 4 times)
VDD
C1
C1
C1
VOUT
CAP3–
CAP1–
CAP1+
CAP2–
CAP2+
V0
VR
VSS
VSS
V1
C1
C1
C1
S1D15A06 Series
C1
VDD
VDD2
C1
R3
R2
V0
VR
VSS
VSS
V1
V2
V2
V3
V3
V4
V4
(2) When built-in V0 voltage adjusting resistors are used
Voltage Follower Circuit [S1D15A06D01B*]
R2
VOUT
CAP3
CAP1–
CAP1+
CAP2–
CAP2+
VOUT
CAP3
CAP1–
CAP1+
CAP2–
CAP2+
V0
VR
R1
VSS
V1
External
power supply
VDD
VDD2
S1D15A06 Series
R3
VDD
VDD2
V0
VR
VSS
VSS
V1
V2
V2
V3
V3
V4
V4
EPSON
S1D15A06 Series
VDD
External
power supply
VDD
12–22
VOUT
CAP3
CAP1–
CAP1+
CAP2–
CAP2+
R1
2. When the voltage adjustment and V/F circuits alone
are used
(1) When built-in V0 voltage adjusting resistors are not
used [S1D15A06D01B*]
VSS
VDD
VDD2
S1D15A06 Series
VDD
Rev. 1.0a
S1D15A06 Series
3. When V/F circuit alone is used [S1D15A06D01B*]
4. When built-in power supply is not used[S1D15A06D02B*]
VDD
VDD2
VOUT
CAP3
CAP1–
CAP1+
CAP2–
CAP2+
VOUT
CAP3
CAP1–
CAP1+
CAP2–
CAP2+
VR
VSS
VSS
V1
V0
External power supply
V0
S1D15A06 Series
VDD
VDD2
VSS
V2
V3
V4
VR
VSS
V1
S1D15A06 Series
VDD
External
power supply
VDD
V2
V3
V4
* Since VR pin has a higher impedance, wiring distance must be minimized or shielded wire must be used.
Sample setting
When V0 is varied between 8 and 9V.
Item
Setting
Unit
C1
1.0 to 4.7
µF
Figure 12
Rev. 1.0a
EPSON
12–23
S1D15A06 Series
Reset Circuit
When pin goes low, RES or when Reset command is
used, this LSI is initialized.
Initialized states
• Serial interface internal shift register and counter clear
• Power saver mode is entered.
• Oscillation circuit is stopped.
• The LCD power supply circuit is stopped.
• Display OFF
• Display all points ON (Display all points ON ON/
OFF command D0 = "1")
• Segment/common driver outputs go to the V SS
level.
• Display normal
• Page address=0H
• Column address=0H
• Display start line address=set at the first line
• Segment driver direction=normal
• Common driver direction=normal
• Read modify write OFF
• Power control register (D2, D1, D0) = (0, 0, 0)
• V0-resistor ratio register (D2, D1, D0) = (0, 0, 0)
• Electronic volume register (D4, D3, D2, D1, D0) = (1,
0, 0, 0, 0)
• LCD power supply bias ratio = 1/6 bias (S1D15A06)
• Test mode is released.
12–24
* Voltage short-circuit across VOUT and VDD2 as well
as Vo and VSS [allowed only when RES pin = LOW
level].
When reset is detected, this LSI is set to above initialized
states. However it has no effect on contents of DDRAM.
As seen in “Microprocessor Interface (Reference
Example)”, connect RES pin to the reset pin of the MPU
and initialize the MPU at the same time. The initialization
by RES pin is always required during power-on.
If the control signal from MPU is HZ, an overcurrent
may flow through the LSI. A protection is required to
prevent the HZ signal at the input pin during power-on.
In case the S1D15A06 series does not use the on-chip
LCD power supply circuit, after RES pin is turnd LOW
to HIGH, the external LCD power supply must be
turned on.
EPSON
Rev. 1.0a
S1D15A06 Series
7. COMMANDS
The S1D15A06 series identifies the data bus by a combination of A0, RD (E), WD(R/W) signals.
In the 8080-series MPU interface, the command is activated when a low pulse is input to RD pin for reading and when
a low pulse is input to WD pin for writing. In the 6800-series MPU interface, the S1D15A06 series enters a read mode
when a high level is input to R/W pin and a write mode when a low level is input to R/W pin, and the command is activated
when a high pulse is input to E pin. Therefore, in the command explanation and command table, the 6800-series MPU
interface is different from the 8080-series MPU interface in that RD(E) becomes “1 (H)” in Display data read command.
And when the serial interface is selected, the data is input in sequence starting with D7.
Taking the 8080-series MPU interface as an example, commands will be explained below.
Explanation of commands
(1) Display ON/OFF
This command turns the display ON and OFF.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
1
1
1
0
1
Display OFF
Display ON
When the Display OFF command is executed when in the Display all points ON mode , Power saver mode is entered.
See the section on the Power saver for details.
(2) Display normal/reverse
This command can reverse the lit and unlit display without overwriting the contents of the DDRAM.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
0
1
1
0
Normal:DDRAM Data HIGH
=LCD ON voltage
Reverse:DDRAM Data LOW
=LCD ON voltage
1
(3) Display all points ON/OFF
This command makes it possible to force all display points ON regardless of the content of the DDRAM. Even when
this is done, the DDRAM contents are maintained. This command takes priority over the Display normal/reverse
command.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
0
1
0
0
1
Normal display mode
Display all points ON
When the Display all points ON command is executed when in the Display OFF mode, Power saver mode is entered.
See the section on the Power saver for details.
Rev. 1.0a
EPSON
12–25
S1D15A06 Series
(4) Page address set
This command specifies the page address of the DDRAM (refer to Figure 5).
Specifying the page address and column address enables to access a desired bit of the DDRAM. After the last column
address (65H), page address incremented by +1 (refer to Figure 4). After the very last address (column = 65H, page =
7H), page address return to 0H.
Page address 8H is the DDRAM area dedicate to the indicator, and only D0 is valid for data change.
See the function explanation in “DDRAM and page/column address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Page address
1
0
1
1
0
0
0
0
0
0
:
1
0
0
0
1
0
1
0
1
0
1
0
0H
1H
2H
:
7H
8H
0
1
(5) Column address set
This command specifies the column address of the DDRAM (refer to Figure 5).
The column address is split into tow sections (the upper 3-bits and lower 4-bits) when it is set (fundamentally, set
continuously).
Each time the DDRAM is accessed, the column address automatically increments by +1, making it possible for the MPU
to continuously access to the display data. After the last column address (65H) ,column address returns to 00H (refer
to Figure 4).
See the function explanation in “DDRAM and page/column address circuit”, for detail.
A0
0
12–26
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
*
A3
A6
A2
A5
A1
A4
A0
Upper bit address
Lower bit address
*Disabled bit
A6
A5
A4
A3
A2
A1
A0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
0
0
0
0
0
:
0
0
1
1
0
0
0
1
00H
01H
02H
:
64H
65H
EPSON
Rev. 1.0a
S1D15A06 Series
(6) Display start line address set
This command is used to specify the display start line address of the DDRAM (refer to Figure 5).
If the display start line address is changed dynamically using this command, then screen scrolling, page swapping can
be performed.
See the function explanation in “Line address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Line address
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
0
0
0
:
1
1
1
1
1
1
0
1
00H
01H
02H
:
3EH
3FH
(7) ADC Select (Segment driver direction select)
This command can reverse the correspondence between the DDRAM column address and the segment driver output.
See the function explanation in “DDRAM and page/column address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
0
0
0
0
1
Normal
Reverse
(8) Common driver direction select
This command can reverse the correspondence between the DDRAM line address and the common driver output. See
the function explanation in “Line address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
1
0
0
0
1
*
*
*
Normal
Reverse
*Disabled bit
(9) Display data read
This command reads 8-bit data from the specified DDRAM address. Since the column address is automatically
incremented by +1 after each read ,the MPU can continuously read multiple-word data. One dummy read is required
immediately after the address has been set. See the function explanation in “Access to DDRAM and internal registers”
and “DDRAM and page/column address circuit”, for detail.
A0
1
Rev. 1.0a
E R/W
RD WR
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
EPSON
12–27
S1D15A06 Series
(10) Display data write
This command writes 8-bit data to the specified DDRAM address. Since the column address is automatically
incremented by +1 after each write ,the MPU can continuously write multiple-word data. See the function explanation
in “DDRAM and page/column address circuit”, for detail.
A0
1
E R/W
RD WR
1
D7
D6
D5
0
D4
D3
D2
D1
D0
Write Data
(11) Read modify write
This command is used paired with End command. Once this command is issued, the column address is not incremented
by Display data read command, but is incremented by Display data write command. This mode is maintained until End
command is issued. When End command is issued, the column address returns to the address it was at when Read modify
write command was issued. This function makes it possible to reduce the MPU load when there are the data to change
repeatedly in a specified display region, such as blinking cursor.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
0
0
*When End command is issued, only column address returns to the address it was at when Read modify write command
was issued, but page address does not return. Consequently, Read modify Write mode cannot be used over pages.
When you want to maintain the current page address after a read modify write operation done on a column address
between the start and the final column address (65H), you must specify the page address again after the operation is
over.
*Even if Read modify write mode, other commands besides Display data read/write can also be used. However, Column
address set command cannot be used.
The sequence for cursor display
Page address set
Column address set
Read modify Write
Dummy read
Data read
Data write
No
Completed?
Yes
End
Figure 13
12–28
EPSON
Rev. 1.0a
S1D15A06 Series
(12) End
This command releases the Read modify write mode, and returns the column address to the address it was when Read
modify write command was issued .
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
•••
N+m
N
End
Read modify write
Figure 14
(13) Power control set
This command sets the on-chip power supply function ON/OFF. See the function explanation in “Power supply circuit”,
for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
0
0
1
0
1
0
1
D1
D0
Mode
0
1
Booster : OFF
Booster : ON
Voltage regulator : OFF
Voltage regulator : ON
Voltage follower : OFF
Voltage follower : ON
0
1
(14) V 0-resistor ratio set
This command sets the internal resistor ratio “Rb/Ra” for the V0 voltage regulator to adjust the contrast of LCD panel
display. See the function explanation in “Power supply circuit”, for detail.
Rev. 1.0a
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EPSON
Rb/Ra : V 0 voltage
small
low
←
0
E R/W
RD WR
←
A0
large
high
External resistor mode
12–29
S1D15A06 Series
(15) Electronic volume
This command sets a value of electronic volume “α” for the V0 voltage regulator to adjust the contrast of LCD panel
display. See the function explanation in “Power supply circuit”, for detail.
0
D6
D5
D4
D3
D2
D1
D0
α
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
31
30
29
1
1
1
1
1
1
0
1
1
1
:
V0 voltage
low
←
1
D7
←
0
E R/W
RD WR
←
A0
1
0
high
(16) LCD bias set
This command selects the voltage bias ratio required for the LCD. This command is enabled when the voltage follower
circuit operates.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Bias
S1D15A06
1
0
1
0
0
0
1
0
1
1/8 bias
1/6 bias
(17) Power saver
When the display all points ON command is executed when in the display OFF mode, power saver mode is entered, and
the power consumption can be greatly reduced.
This mode stops every operation of the LCD display system, and can reduce current consumption nearly to a static
current value if no access is made from the MPU. The internal states in the power saver mode is as follows:
• The oscillation circuit is stopped.
• The LCD power supply circuit is stopped.
• The LCD driver circuit is stopped and segment/common driver outputs output the VSS level.
• The display data and operation mode before execution of the Power saver command are held, and the MPU can access
to the DDRAM and internal registers.
Power saver (Display OFF & Display all points ON)
Power saver mode
Power saver OFF (Display all points OFF)
Power saver mode cancel
Figure 15
12–30
EPSON
Rev. 1.0a
S1D15A06 Series
(18) Reset
When this command is issued, this LSI is initialized. This command, however, is not used for introducing short circuit
across VOUT and VDD2 or V0 and VSS (only when RES pin = LOW). Also note that initialization of the display data RAM
does not take place in parallel with initialization of the LSI. See the function explanation in “Reset circuit”, for detail.
E R/W
RD WR
A0
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
1
0
When initializing the LSI while power is turned on, reset signal to the RES pin is used. This signal cannot be replaced
by the reset command.
(19) NOP
Non-operation command
A0
E R/W
RD WR
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
1
1
(20) Test
This is a command for LSI chip testing. Please do not use. If the test command is issued by accident, it can be cleared
by applying an LOW signal to the pin, or by issuing the Reset command or the Display ON/OFF command.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
*
1
*
*
*
*
* Disabled bit
(Note):
The S1D15A06 series chip maintain their operating modes ,but excessive external noise,etc.,may happen to change
them. Thus in the packaging and system design it is necessary to suppress the noise or take measures to prevent the noise.
Moreover, it is recommended that the operating modes are refreshed periodically to prevent the effects of unanticipated
noise.
Rev. 1.0a
EPSON
12–31
S1D15A06 Series
Command Table
Table 19
(1)Display ON/OFF
A0 XR XW
0 1
0
(2)Display normal/reverce
0
1
0
(3)Display all points
ON/OFF
(4)Page address set
0
1
0
0
1
0
Code
D7 D6 D5 D4 D3 D2 D1 D0
1
0 1 0 1 1 1 0
1
1
0 1 0 0 1 1 0
1
1
0 1 0 0 1 0 0
1
1
0 1 1 address
(5)Column address set
Upper 3-bit address
Column address set
Lower 4-bit address
(6)Display start line
address set
(7)Segment driver
directuin select
0
1
0
0
0
0
1
*
0
1
0
0
0
0
0
address
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
1
(8)Common driver
direction select
0
1
0
1
1
0
0
0
1
*
*
*
(9)Display data read
1
0
1
Read data
Sets the DDRAM display start line
address.
Sets the correspondence
between the DDRAM column
address and the SEG driver output.
0:normal, 1:reverse
Sets the correspondence
between the DDRAM line address
and the COM driver output.
0:normal, 1:reverse
Reads from the DDRAM.
(10)Display data write
1
1
0
Wtite data
Writes to the DDRAM.
(11)Read modify write
0
1
0
1
1
1
0
0
0
0
0
(12)End
0
1
0
1
1
1
0
1
1
1
0
(13)Power control set
0
1
0
0
0
1
0
1
(14)V0-resistor ratio set
0
1
0
0
0
1
(15)Electronic volume
0
1
0
1
0
0
(16)LCD bias set
0
1
0
1
0
1
(17)Power saver
-
-
-
-
-
-
Operating
mode
0 0 Resistor
ratio
Electronic volume
value
0 0 0 1 0
1
- -
(18)Reset
0
1
0
1
1
1
0
0
0
1
0
Sets the LCD drive voltage bias ratio.
S1D15A06 0:1/8bias, 1:1/6bias
Compound command of Display
OFF and Display all points ON
Internal reset
(19)NOP
0
1
0
1
1
1
0
0
0
1
1
Non-operation
(20)Test
0
1
0
1
1
*
1
*
*
*
*
IC test command. Do not use.
Command
address
address
Function
LCD display
0:OFF, 1:ON
LCD display
0:normal, 1:reverce
LCD display
0:normal display, 1:all points ON
Sets the DDRAM page address
Sets the DDRAM column address
Column address increment
at write:+1, at read:0.
Releases Read modify write mode.
Sets the on-chip power supply
circuit operating mode.
Sets the V0-resistor ratio value.
Sets the electronic volume value.
(Note)*:disabled bit
12–32
EPSON
Rev. 1.0a
S1D15A06 Series
8. COMMAND SETTING
Instruction Setup Example
(For your reference)
Note: If charge remains on the smoothing capacitor connected across the LCD drive voltage output pin and VDD2
pin, troubles (such as momentary blackening) can occur
on the display screen during its powering on process. In
order to avoid such troubles, it is recommended to implement the following flow.
1. When switching to the built-in power supply takes
place immediately after powering on:
Turn VDD-VSS power on while RES pin = LOW is selected.
Wait until power is settled.
Cancel the reset mode (RES pin = HIGH).
Turn on the initial setup mode (default). * 1
Selecting necessary functions using the commands
(User setup)
(2) Select either Normal/reversing display. * 2
(6) Specify the display start line. * 3
(7) Implement ADC select. * 4
(8) Select the common output mode. * 5
(16) Set LCD bias voltage. * 6
Selecting necessary functions from the commands
(User setup)
(14) Specify resistance ratio of the built-in
V0 voltage adjusting resistors. * 7
(15) Set up the electronic volume. * 8
Selecting necessary function from the command
(User setup)
(13) Set up the power control. * 9
Canceling the power save mode (User setup)
(3) Turn of Display At All Points. * 10
Initial setup is complete.
[The built-in power supply is turned on and the display is turned off.]
Rev. 1.0a
Note: Reference Items
* 1: Refer to the 6. Functions Description “Reset Circuit”.
In the initial setup mode (default), too, contents of
the display data RAM is still uncertain.
* 2: Refer to the 7. Commands Description “(2) Normal/reversing Display”.
* 3: Refer to the 7. Commands Description “(6) Display
Line Setup”.
* 4: Refer to the 7. Commands Description “(7) ADC
Select”.
* 5: Refer to the 7. Commands Description “(8) Common Output Mode Select”.
* 6: Refer to the 7. Commands Description “(16) LCD
Bias Set”.
* 7: Refer to the 6. Functions Description Power Supply
Circuit and 7. Commands Description “(14) Specifying resistance ratio of built-in V0 voltage adjusting resistors”.
* 8: Refer to the 6. Functions Description Power Supply
Circuit and 7.Commands Description “(15) Electronic Volume”.
* 9: Refer to the 6. Functions Description Power Supply
Circuit and 7. Commands Description “(13) Setting
Up Power Control”.
* 10: Refer to the 7. Commands Description “(17) Power
Save”.
EPSON
12–33
S1D15A06 Series
2. Data display
Initialization is complete
Selecting necessary function from the command (User setup)
(6) Select the display start line. * 9
(4) Select the page address. * 10
(5) Select the column address. * 11
Selecting necessary function from the command (User setup)
(10) Turn on the display data write operation. * 12
Selecting necessary function from the command (User setup)
(1) Turn on or off the display. * 13
Data display is ended.
Note: Reference Items
* 9: Refer to the 7. Commands Description “(6) Setup
of Display Start Line”.
* 10: Refer to the 7. Commands Description “(4) Page
Address Set”.
* 11: Refer to the 7. Commands Description “(5) Column Address Set”.
* 12: Refer to the 7. Commands Description “(10) Display Data Write”.
* 13: Refer to the 7. Commands Description “(1) Display Data ON/OFF”.
The all-white display of data should be avoided as much
as practicable right after the display mode is turned on
(right after the display has been turned on).
3. Powering off * 14
1) Turn on any desired mode.
Selecting necessary function from the command (User setup)
(17) Select the power save mode. * 15
Select the reset active (RES pin = LOW).
Turn VDD-VSS power off.
The time (tL) provided between turning on of the reset active and turning off of VDD-VSS power (VDD-VSS
= 1.8V) must be longer than the time required for V0V4 potential to go lower (tH) than the threshold voltage set on the LCD (usually 1V).
For “tH ”, see the “Reference data” in the following
section. If “tH” is excessively long, it must be cut short
by installing a resistor across V0 and VSS.
Note:
* 14: This IC is provided on the power supply VDD-VSS logic circuit to offer control over the V0-VSS drivers on the LCD
power supply. Thus, if the power supply V0-VSS is turned off while voltage is still remaining on the LCD power
supply V0-VSS, the drivers (both COM and SEG) can generate uncontrolled output. Make sure to observe the
following powering off procedure:
• Turn off the built-in power supply first, then, after making sure that potential on V0 to V4 is lower than the LCD
panel threshold voltage, turn the IC power (VDD-VSS) off. Also refer to the 6. Functions Description "Power
Supply Circuit".
* 15: Refer to the 7. Command Description “(17) Power Save”.
After entering the power save command, you must implement reset procedure from the RES pin before turning off
VDD-VSS power.
12–34
EPSON
Rev. 1.0a
S1D15A06 Series
4. Refresh
It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of
unexpected noise.
Refresh sequence
Display ON/OFF command
Select every command
Implement DDRAM refresh.
5. Precautions on powering off
<Powering off (VDD-VSS) off>
Turn the power (V0-VSS) save mode off -> Then, turn
the power (VDD-VSS) off.
* The requirement "tL > tH" must be strictly observed.
* If "tL < tH", display failures can result.
Power save
tL must be specified on software from MPU.
tH depends on discharging capability of the drivers.
See the "Reference data" in the following section. It
also depends on a given LCD panel, thus actual timing must be determined after experimenting on your
LCD panel.
Power OFF
tL
VDD
1.8V
SEG
Since power (VDD-VSS) is turned off,
VSS
output cannot be maintained at a fixed level.
COM
VSS
V0
V1
V2
V3
V4
VSS
Approximately 1V: Lower than the threshold voltage on the LCD panel.
tH
Rev. 1.0a
For tH, see the "Reference data".
EPSON
12–35
S1D15A06 Series
time of power supply (VDD-VSS) should be considered.
tH depends on the drivers' discharging capability. See
the “Reference data” in the following section. It also
depends on model of a given LCD panel, thus actual
timing must be determined after experimentation on
your LCD panel.
<When powering off (VDD-VSS) is not available with the
command>
Turn off the reset mode (LCD power (V0-VSS) system).
-> Then, turn power (VDD-VSS ) off.
* The requirement “tL > tH” must be observed.
* When specifying tL, measures such as extending fall
Reset
Power OFF
tL
VDD
1.8V
SEG
Since power (VDD-VSS) is turned off,
VSS
output cannot be maintained at a fixed level.
COM
VSS
V0
V1
V2
V3
V4
VSS
Approximately 1V: Lower than threshold voltage on the LCD panel.
tH
For tH, see the "Reference data".
6. Reference data
The following data is for your reference alone. tH is
significantly affected by capacity of V0 pin, thus you must
verify appropriateness of a selected tH on the panel being equipped with the pin.
[Conditions: VDD = 1.8V, voltage is tripled and capacity
of the boosting capacitor = 1.0 µF]
12–36
When V 0 is under no-load, t H per voltage is 22 µs. It
becomes 220 µs when V0 = 9V.
Capacity dependency is 1 pF. ∆tH per voltage is 50 ns.
An example: When VDD = 1.8V, V0 = 8V and V0 pin
capacity [board capacity] (CL) = 100 pF.
tH = 22µs × 8V + 50ns × 100pF × 8V = 216µs
EPSON
Rev. 1.0a
S1D15A06 Series
9. ABSOLUTE MAXIMUM RATING
Unless otherwise noted, VSS = 0V.
Table 20
Parameter
Power supply voltage (1)
Power supply voltage (2)
Symbol
VDD
VDD2
Conditions
–0.3 to 0.6
–0.3 to 0.6
–0.3 to 5.0
–0.3 to 3.3
–0.3 to 2.5
Unit
V
V
V0, VOUT
V1 , V2 , V3 , V4
VIN
VO
TOPR
TSTR
–0.3 to 10.0
–0.3 to V0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–40 to 85
–55 to 100
–55 to 125
V
V
V
V
°C
°C
Double boosting
Triple boosting
Quadruple boosting
Power supply voltage (3)
Power supply voltage (4)
Input voltage
Output voltage
Operating temperature
Storage temperature
TCP
Bare chip
V0, VOUT
V1 to V4
VCC
VDD, VDD2
VSS
VSS
System
VSS
S1D15A06 series
Notes and Conditions
1. VSS = 0V is assumed for every voltage indicated above.
2. Voltage V0, V1, V2, V3, V4 must always keep up the condition of V0 >= V1 >= V2 >= V3 >= V4 >= VSS and VOUT >= V0 >= VSS.
3. If the LSI exceeds its absolute maximum rating, it may be damage permanently. It is desirable to use it under electrical
characteristics conditions during general operation. Otherwise, a malfunction of the LSI may be caused and LSI
reliability may be affected.
Rev. 1.0a
EPSON
12–37
S1D15A06 Series
10. DC CHARACTERISTICS
Table 21
V SS=0V, V DD=3V±10%, Ta=–40~85°C unless otherwise noted.
Item
Supply
voltage(1)
Supply
voltage(2)
Supply
voltage(3)
Symbol
Recommended
operation
Operational
available
VDD
Recommended
operation
Operational
available
Operational
available
VDD2
VDD
V0
V1, V2
Operational
available
High-level input voltage
Low-level input voltage
High-level output voltage
V3, V4
Low-level output voltage
Input leak current
Output leakage current
VOL
ILI
ILO
LCD driver ON resistance
RON
Static current consumption
IDDQ
VIH
VIL
V OH
Output leak current
I0Q
Input terminal capacitance
Oscillation Built-in oscillation
frequency
External input
C IN
f OSC
f CL
Condition
(Vss is used as the
reference)
(Vss is used as the
reference)
(Vss is used as the
reference)
(Vss is used as the
reference)
(Vss is used as the
reference)
(Vss is used as the
reference)
I OH=–0.5mA
I OL=0.5mA
V IN=VDD or VSS
Min.
2.7
Unit
V
Pin used
V DD *1
1.8
–
3.6
V
1.8
–
5.0
V
4.5
–
9.0
0.6×V 0
–
V0
VSS
–
0.4×V 0
0.7×V DD
VSS
0.7×V DD
–
–
–
V DD
0.3×V DD
V DD
V
V
V
VSS
–1.0
–3.0
–
–
–
0.3×V DD
1.0
3.0
V
µA
µA
–
2.0
5.0
kΩ
–
0.01
5.0
µA
V DD,VDD2
–
0.01
15.0
µA
V0
10.0
35.20
15.0
38.72
pF
31.68
35.2
70.4
140.8
V 0=7.0V
Ta=25°C
Ta=25°C
V 0=7.0V
Ta=25°C
Ta=25°C, f =1MHz
Ta=25°C
Standard value
Typ.
Max.
–
3.3
V DD2 *1
V0
V
*2
V 1 , V2
V 3 , V4
kHz
*3
*4
*5
*6
SEGn,
COMn *7
*8
CL *8
Table 22
Item
Symbol
Condition
Built-in power supply circuit
When voltage is doubled
(Vss is used as the reference)
Input voltage
Boosted output voltage
Operating current of
voltage adjustment circuit
V/F circuit operating
voltage
Reference voltage
Standard value
Min. Typ. Max.
1.8
–
5.0
1.8
–
3.3
1.8
–
2.5
V OUT
When voltage is tripled
(Vss is used as the reference)
When voltage is quadrupled
(Vss is used as the reference)
(Vss is used as the reference)
–
–
10.0
V OUT
(Vss is used as the reference)
5.0
–
10.0
V0
(Vss is used as the reference)
4.5
–
9.0
VREG
–0.1%/°C
Ta=25°C
(Vss is used as the reference)
1.16
1.2
1.24
VDD2
Unit
Pin used
V DD2 *1
V
V OUT
V OUT
V0
*9
*10
Note 1: VSS = 0V is assumed for every voltage indicated.
Note 2: Voltages V 0, V1, V2 , V3 and V4 must conform to the requirements that V0>=V1>=V2>=V 3=>V 4=>V SS as well as VOUT >= V0 => VSS.
Note 3: Operating the LSI is operated beyond the maximum absolute rating can damage it permanently. In the normal operation, it
is desirable to use the LSI in compliance with its electric characteristics. If the LSI is used under any conditions conflicting
with its electric characteristics, not only its malfunctioning but also serious loss of reliability can result.
12–38
EPSON
Rev. 1.0a
S1D15A06 Series
◊ Dynamic operating current (1) - When display is turned on with the built-in power supply being disconnected
[Ta = 25°C and output under no-load].
Following shows current consumed by entire IC when external power supply is used.
Table 23-1 Display: All-white
Item
S1D15A06*****
Symbol
ISS(1)
ISS(1)
Requirement
VDD =VDD2=1.8V, V 0=7.2V
VDD =VDD2=1.8V, V 0=9.0V
Min.
–
–
Typ.
23
25
Max.
48
50
Unit Remarks
Min.
–
–
Typ.
26
29
Max.
54
57
Unit Remarks
µA
*11
Table 23-2 Display: Checker pattern
Item
S1D15A06*****
Symbol
ISS(1)
ISS(1)
Requirement
VDD =VDD2=1.8V, V0=7.2V
VDD =VDD2=1.8V, V0=9.0V
µA
*11
◊ Dynamic operating current (2) - When display is turned on with the built-in power supply being connected [Ta = 25°C
and output under no-load].
Table 24-1 Display: All-white
Item
S1D15A06*****
Symbol
ISS(2)
ISS(2)
Requirement
VDD=1.8V,V DD2=3.3V, V0=7.2V,
and voltage is tripled.
VDD=1.8V,V DD2=3.3V, V0=7.2V,
and voltage is tripled.
Min.
–
Typ.
68
Max.
101
–
79
112
Min.
–
Typ.
75
Max.
103
–
87
112
Unit Remarks
µA
*12
Table 24-2 Display: Checker pattern
Item
S1D15A06*****
Symbol
ISS(2)
ISS(2)
Requirement
VDD=1.8V,VDD2=3.3V, V0=7.2V,
and voltage is tripled.
VDD=1.8V,VDD2=3.3V, V0=7.2V,
and voltage is tripled.
Unit Remarks
µA
*12
◊ Current consumption in the power save mode [Ta = 25°C and output under no-load]
Table 25
Item
S1D15A06*****
Rev. 1.0a
Symbol
ISS(3)
Requirement
VDD =VDD2=1.8~3.6V
EPSON
Min.
–
Typ.
0.01
Max.
5
Unit Remarks
µA
12–39
S1D15A06 Series
[Reference data 1]
◊ Dynamic operating current (1) - When LCD display is turned on with external power supply being connected (Allwhite display)
50.0
Conditions:
Built-in power supply OFF
External power supply ON
VDD2-VSS = 1.8V
VDD-VSS = 1.8V
V0-VSS = 7.2V
V0-VSS = 9.0V
Ta = 25°C
Display pattern: All-white.
Remarks: See * 11.
ISS(1) [µA]
40.0
30.0
20.0
10.0
(VO = 7.2V)
(VO = 9.0V)
0.0
0.0
2.0
4.0
VDD [V]
6.0
8.0
Figure 16
◊ Dynamic operating current (1) - When LCD display is turned on with external power supply being connected (Checker
pattern display)
50.0
Conditions:
Built-in power supply OFF
External power supply ON
VDD2-VSS = 1.8V
VDD-VSS = 1.8V
V0-VSS = 7.2V
V0-VSS = 9.0V
Ta = 25°C
Display pattern: Checker.
Remarks: See * 11.
ISS(1) [µA]
40.0
30.0
20.0
10.0
(VO = 7.2V)
(VO = 9.0V)
0.0
0.0
2.0
4.0
VDD [V]
6.0
8.0
Figure 17
12–40
EPSON
Rev. 1.0a
S1D15A06 Series
[Reference data 2]
◊ Dynamic operating current (2) - When LCD display is turned on with built-in power supply being connected (Allwhite display)
140.0
Conditions:
Built-in power supply ON
Voltage tripled
VDD2-VSS = 3.3V
VDD-VSS = 1.8V
V0-VSS = 7.2V
V0-VSS = 9.0V
Ta = 25°C
Display pattern: All-white.
Remarks: See * 12.
120.0
ISS(2) [µA]
100.0
80.0
60.0
40.0
20.0
(VO = 7.2V)
(VO = 9.0V)
0.0
0.0
2.0
4.0
VDD [V]
6.0
8.0
Figure 18
◊ Dynamic operating current (2) - When LCD display is turned on with built-in power supply being connected (Checker
pattern display)
140.0
Conditions:
Built-in power supply ON
Voltage tripled
VDD2-VSS = 3.3V
VDD-VSS = 1.8V
V0-VSS = 7.2V
V0-VSS = 9.0V
Ta = 25°C
Display pattern: Checker.
Remarks: See * 12.
120.0
ISS(2) [µA]
100.0
80.0
60.0
40.0
20.0
(VO = 7.2V)
(VO = 9.0V)
0.0
0.0
2.0
4.0
VDD [V]
6.0
8.0
Figure 19
Rev. 1.0a
EPSON
12–41
S1D15A06 Series
[Reference data 3]
◊ Dynamic operating current (3) - During an access is
being made
10
This chart shows current
consumption when the
checker pattern write is
constantly implemented
in fCYC.
Iss (1) alone is consumed
when an access is not
taking place.
IDD[mA]
1
Conditions:
Built-in power supply OFF
External power supply ON
VDD2—VSS=3.0V
V0—VSS=9.0V
Ta=25¡C
0.1
VDD=1.8V
VDD=3.0V
0.01
0.001
0.01
1
0.1
10
fCYC[MHz]
Figure 20
[Reference data 4]
◊ Operating voltage range of VDD and V0 systems.
S1D15A06 Series
10.0
9.0
7.2
V0-VSS[V]
Operating range
5.0
4.5
1.8
2.25
3.6
0
0
2
4
5
VDD[V]
Figure 21
12–42
EPSON
Rev. 1.0a
S1D15A06 Series
[Reference items]
* 1 : Although wide operating voltage range is warranted, an exemption to it is when an access made by MPU is
accompanied with radical voltage fluctuations.
* 2 : See Figure 21 for the operating voltage range of VDD and V0 systems. It is applicable when an external power
supply is used.
* 3 : A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS, CL, C86, P/S and RES pins. VIH = 0.8 × VDD to VDD,
VIL = VSS to 0.2 × VDD when VDD = 1.8V to 2.7V.
* 4 : D0 to D7 pins. I OH = –0.25mA, I OL = 0.25mA when VDD = 1.8V to 2.7V.
* 5 : A0, RD (E), WR (R/W), CS, C86, CL and RES pins.
* 6 : It is applicable when D0 to D5, D6 (SCL) and D7 (SI) pins are placed in high impedance.
* 7 : It represents the resistance value to be employed when 0.1V is applied across the output pin SEGn or COMn and
respective power terminals (V1, V2, V3 and V4). It must be selected within the operating voltage range (3).
RON = 0.1V/∆I (∆I represents the current conducted when 0.1V is applied when the power supply is turned on).
* 8 : For the relationship between the oscillating frequency and frame frequency, refer to Table 6. External inputs
listed in the standard value space are recommended values.
* 9 : Adjustment of the V0 voltage adjustment circuit must be done within the operating voltage range of the voltage
follower circuit.
* 10 : The built-in reference voltage source of the V0 voltage adjustment circuit. Two types of VREG temperature gradients are supported by the S1D15A06; (1) Approximately –0.1%/°C and (2) External input.
* 11/12 : The built-in oscillation circuit is used. It indicates current consumed by the independent IC when the display
is turned on. Current consumption of the S1D15A06 indicated here is one when the 1/6 bias mode is turned on.
It does not includes current consumed due to the LCD panel capacity or wiring capacity (driver output is under
no-load). These values are applicable when an access is not made by MPU.
* 12 : These values are applicable when the V0 voltage adjusting built-in resistors are used on an S1D15A06 model with
VREG optional temperature gradient of –0.1%/˚C.
Rev. 1.0a
EPSON
12–43
S1D15A06 Series
11. AC CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080-series MPU)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
*1
tCCLR, tCCLW
WR, RD
tCCHR, tCCHW
CS1
(CS2="1")
*2
tf
tr
WR, RD
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 22
Table 26
Item
Address hold time
Address setup time
System cycle time
Control LOW pulse width(Write)
Control LOW pulse width(Read)
Control HIGH pulse width(Write)
Control HIGH pulse width(Read)
Data setup time
Data hold time
Access time
Output disable time
12–44
[VDD=2.7V to 3.6V, Ta=–40 to 85°C]
Signal
A0
WR
RD
WR
RD
D7 to D0
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
Condition
tDS8
tDH8
tACC8
tOH8
EPSON
CL=100pF
Min.
0
0
500
100
200
100
100
Max.
–
–
–
–
–
–
–
70
0
–
10
–
–
180
100
Units
ns
Rev. 1.0a
S1D15A06 Series
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Table 27
Item
Address hold time
Address setup time
System cycle time
Control LOW pulse width(Write)
Control LOW pulse width(Read)
Control HIGH pulse width(Write)
Control HIGH pulse width(Read)
Data setup time
Data hold time
Access time
Output disable time
Signal
A0
WR
RD
WR
RD
D7 to D0
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
Condition
CL=100pF
Min.
0
0
1000
150
300
150
150
Max.
–
–
–
–
–
–
–
120
0
–
10
–
–
260
200
Units
ns
*1. This is in the case of making the access by WR and RD, setting the CS1=LOW.
*2. This is in the case of making the access by CS1, setting the WR, RD=LOW.
*3. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr+tf) <
= (tCYC8-tCCLW ) or (tr+tf) <
= (tCYC8-tCCLR-tCCHR).
*4. All timings are specified based on the 20 and 80% of VDD.
*5. tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and WR,RD are at
the LOW level.
Rev. 1.0a
EPSON
12–45
S1D15A06 Series
System Bus Read/Write Characteristics 2 (For the 6800-series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
*1
tEWHR, tEWHW
tCYC6
E
tEWLR, tEWLWW
CS1
(CS2="1")
*2
tr
tf
E
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 23
Table 28
Item
Address hold time
Address setup time
System cycle time
Enable
HIGH pulse width
Enable
LOW pulse width
Signal
A0,
WR
width
Read
width
Read
Data setup time
Data hold time
Access time
Output disable time
E
D7 to D0
Symbol
tAH6
tAW6
tCYC6
tEWHW
tEWHR
tEWLW
tEWLR
Data setup time
Data hold time
Access time
Output disable time
Condition
tDS6
tDH6
tACC6
tOH6
Table 29
Item
Address hold time
Address setup time
System cycle time
Enable
width
HIGH pulse width Read
Enable
width
LOW pulse width Read
[VDD=2.7V to 3.6V, Ta=–40 to 85°C]
CL=100pF
Min.
0
0
500
100
200
100
100
Max.
–
–
–
–
–
–
–
70
0
–
10
–
–
180
100
Units
ns
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Signal
A0,
WR
E
D7 to D0
Symbol
tAH6
tAW6
tCYC6
tEWHW
tEWHR
tEWLW
tEWLR
tDS6
tDH6
tACC6
tOH6
Condition
CL=100pF
Min.
0
0
1000
150
300
150
150
Max.
–
–
–
–
–
–
–
120
0
–
10
–
–
260
200
Units
ns
*1. This is in the case of making the access by E, setting the CS1=LOW.
*2. This is in the case of making the access by CS1, setting the E=HIGH.
*3. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr+tf) <
= (tCYC6-tEWLW-tEWHW) or (tr+tf) <
= (t CYC6-tEWLR -tEWHR).
*4. All timings are specified based on the 20 and 80% of VDD.
*5. tEWLW and t EWLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and E is at the HIGH
level.
12–46
EPSON
Rev. 1.0a
S1D15A06 Series
Serial interface
tCSS
CS
tCSH
tSAH
tSAS
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Figure 24
[VDD=2.7V to 3.6V, Ta=–40 to 85°C]
Table 30
Parameter
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS serial clock time
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
Condition
tCSS
tCSH
Table 31
Parameter
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS serial clock time
Min.
125
50
50
75
75
50
50
Max.
–
–
–
–
–
–
–
75
75
–
–
Units
ns
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
Condition
tCSS
tCSH
Min.
200
75
75
75
75
50
50
Max.
–
–
–
–
–
–
–
100
100
–
–
Units
ns
Note : 1. The input Signal rise and fall times must be with in 15ns.
2. Every timing is specified on the basis of 20% and 80% of VDD .
Rev. 1.0a
EPSON
12–47
S1D15A06 Series
Reset timing
tRW
RES
tR
Internal circuit
state
During reset
Normal operation
Figure 25
Table 32
Parameter
Reset time
Reset LOW pulse width
[VDD=2.7V to 3.6V, Ta=–40 to 85°C]
Signal
Symbol
tR
RES
tRW
Condition
Table 33
Parameter
Reset time
Reset LOW pulse width
Min.
–
Max.
1000
1000
–
Units
ns
[VDD=1.8V to 2.7V, Ta=–40 to 85°C]
Signal
Symbol
tR
RES
tRW
Condition
Min.
–
Max.
1500
1500
–
Units
ns
Note : 1. The input Signal rise and fall times must be with in 15ns.
2. Every timing is specified on the basis of 20% and 80% of V DD.
12–48
EPSON
Rev. 1.0a
S1D15A06 Series
12. MPU INTERFACE (EXAMPLES)
The S1D15A06 series can be directly connected to the
80 series MPU or 68 series MPU. Adding a serial interface allows you to drive the S1D15A06 with less number of signal lines.
After initialization is completed from the RES pin, make
sure that respective input pins on the S1D15A06 series
are normally controlled.
(1) 80 series MPU
VDD
VDD
A0
A1 to A7
MPU
IORQ
CS
Decoder
D0 to D7
D0 to D7
RD
RD
WR
WR
RES
RES
GND
C86
A0
S1D15A06 Series
VCC
P/S
VSS
RESET
VSS
Figure 26
(2) 68 series MPU
VDD
VDD
A0
A1 to A15
MPU
VMA
CS
Decoder
D0 to D7
D0 to D7
E
E
R/W
R/W
RES
RES
GND
C86
A0
S1D15A06 Series
VCC
P/S
VSS
RESET
VSS
Figure 27
(3) Serial interface
VDD
VCC
VDD
Decoder
CS
MPU
A1 to A7
C86
A0
GND
Part1
SI
Part2
SCL
RES
RES
RESET
VDD or VSS
S1D15A06 Series
A0
P/S
VSS
VSS
Figure 28
Rev. 1.0a
EPSON
12–49
13. S1D15B01 Series
Rev. 1.1a
Contents
1. DESCRIPTION ..............................................................................................................................................13-1
2. FEATURES .................................................................................................................................................... 13-1
3. BLOCK DIAGRAM ......................................................................................................................................... 13-2
4. PIN LAYOUT .................................................................................................................................................13-3
5. PIN DESCRIPTION .......................................................................................................................................13-6
6. FUNCTIONAL DESCRIPTION ......................................................................................................................13-8
7. COMMAND DESCRIPTION ........................................................................................................................ 13-24
8. COMMAND SETTING ................................................................................................................................. 13-32
9. ABSOLUTE MAXIMUM RATING ................................................................................................................. 13-36
10. ELECTRICAL CHARACTERISTICS ............................................................................................................13-37
11. THE MPU INTERFACE (REFERENCE EXAMPLES) .................................................................................13-53
12. CAUTION ..................................................................................................................................................... 13-54
–i–
Rev. 1.1a
S1D15B01 Series
1. DESCRIPTION
2. FEATURES
The S1D15B01 series is a single-chip liquid crystal
display (=LCD) driver for dot-matrix LCDs that can be
connected directly to a microprocessor (=MPU) bus. It
accepts 8-bit parallel or serial display data from a MPU,
stores it in an on-chip display data RAM (=DDRAM),
and generates a LCD drive signal independent of the
MPU clock.
The use of the on-chip DDRAM of 65×132 bits and a
one-to-one correspondence between LCD panel pixel
dots and on-chip DDRAM bits offer high flexibility in
graphic display.
The S1D15B01 series does not need external operation
clock for DDRAM read/write operations, and has a onchip LCD power supply circuit featuring very low
current consumption with few external components,
and moreover has a on-chip CR oscillator circuit.
Consequently, the S1D15B01 can be realize a highperformance handy display system with a minimum
current consumption and the fewest components.
• Direct display by DDRAM :
Bit data of DDRAM “0” .... a dot of display is OFF
“1” .... a dot of display is ON
(at Display normal)
• DDRAM capacity : 65×132=8580bits
• High-speed 8-bit Serial interface/8-bit MPU interface
(The chip can be connected directly to both the 8080series MPUs and the 6800-series MPUs) .
• Many command functions :
Display ON/OFF, Display normal/reverse, Display
all points ON/OFF,
Page address set, Column address set, Display start
line address set,
Segment/Common driver direction select,
Display data Read/Write ,Read modify write,
Power control set, Electronic contrast control, LCD
bias set,
Power saver, Reset
• On-chip low power supply circuit for LCD driving
voltage generation
Booster circuit (with boost ratios of Double/Triple/
Quadruple/Quintuple)
Voltage regulator circuit (with high-accuracy
electronic voltage adjustment function)
Voltage follower (with V1 to V4 voltage dividing
resistors)
• On-chip CR oscillation circuit (external clock can
also be input.)
• Very low power consumption
• Power supply :
Logic power supply : VDD-V SS=1.7 to 5.5V
Booster reference supply : VDD2-VSS =1.7 to 5.5V
LCD driving power supply : V0-VSS=4.5 to 16.0V
• Wide range of operating temperatures -40 to 85°C
• CMOS process
• Package : Au bump chip and TCP
• These ICs are not designed for strong radio/optical
activity proof.
Series Specifications
Product Name
Duty
Bias
SEG Dr
COM Dr
VREG
Temperature
Gradient
Voltage
Condition
S1D15B01D00B* 1/65
*S1D15B01D01B* 1/65
1/9,1/7
1/9,1/7
132
132
65
65
–0.05%/˚C
–0.05%/˚C
Internal voltage
V0 or VOUT
*S1D15B01D02B* 1/65
1/9,1/7
132
65
–0.05%/˚C
*S1D15B01T00** 1/65 1/9,1/7
132
* : Start the development on demands
** : Under development
65
–0.05%/˚C
Rev. 1.1a
EPSON
Shipping Forms
Bare Chip
Bare Chip
external voltage
V0 ~ V4 extarnal
Bare Chip
voltage
TCP
13–1
S1D15B01 Series
COMS
• • • • • • • • • •
COM63
COM0
• • • • • • • • • • • • • • • • • • • • • • • • •
SEG131
SEG0
3. BLOCK DIAGRAM
VDD
V2
V3
SEG Drivers
COMS
V0
V1
COM Drivers
V4
VSS
Shift register
Display data latch circuit
CAP1+
Display timing generator circuit
VOUT
Line address
VDD2
I/O buffer
CAP4+
Page address
CAP2+
CAP2–
CAP3+
Power supply circuit
CAP1–
Display data RAM
132 x 65
VR
Oscillator circuit
Column address
Command decoder
13–2
EPSON
D0
D1
D2
D4
D5
D6 (SCL)
Interface
D7 (SI)
RD (E)
WR (R/W)
CS
RES
A0
P/S
C86
MPU
Status
D3
Bus holder
CL
Rev. 1.1a
S1D15B01 Series
4. PIN LAYOUT
73
1
74
282
y
(0, 0)
Alignment mark 1
D15B1D0B
Die No.
x
Alignment mark 2
247
110
111
246
Chip size
10.82mm×2.81mm
Bump pitch
70µm (Min.)
Bump size
PAD No.1 to 73
PAD No.74 to 110
PAD No.111 to 246
PAD No.247 to 282
Bump height
17µm (Typ.)
Chip thickness
625µm
Ground bias
VSS
91µm× 91µm
91µm×45.5µm
45.5µm× 91µm
91µm×45.5µm
Alignment mark 1 Center coordinates (µm)
(µm)
31 70
Alignment mark 2 Center coordinates (µm)
(4947, –1224)
Size
Size
Rev. 1.1a
(–4965, –1231)
(µm)
EPSON
81
13–3
S1D15B01 Series
Pad Center Coordinates
Unit: µm
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
13–4
Pin
Name
(NC)
(NC)
TEST0
TEST1
TEST2
VSS
TEST3
TEST4
TEST5
RES
CS
VSS
WR
RD
VDD
CL
A0
D7,SI
D6,SCL
D5
D4
D3
D2
D1
D0
VDD
VDD
VDD
VDD2
VDD2
VDD2
TEST6
VDD
P/S
C86
VSS
TEST7
TEST8
TEST9
VSS
VSS
VSS
(NC)
VOUT
VOUT
VOUT
(NC)
TEST10
TEST11
TEST12
X
Y
4852 1248
4722
4592
4462
4332
4202
4072
3942
3812
3682
3552
3422
3292
3162
3032
2902
2772
2642
2512
2382
2252
2122
1992
1862
1732
1602
1472
1342
1212
1082
952
822
692
562
432
302
172
3
–166
–335
–465
–595
–725
–855
–985
–1115
–1245
–1414
–1583
–1713
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
Name
TEST13
VSS
VR
V0
V1
V2
V3
V4
CAP2+
CAP2+
CAP2–
CAP2–
CAP4+
CAP4–
VOUT
CAP1+
CAP1+
CAP1–
CAP1–
CAP3+
CAP3+
(NC)
(NC)
(NC)
(NC)
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
X
Y
–1882 1248
–2051
–2181
–2311
–2441
–2571
–2701
–2831
–2961
–3091
–3221
–3351
–3481
–3611
–3741
–3871
–4001
–4131
–4261
–4391
–4521
–4651
–4781
–5255 1264
1194
1124
1054
984
913
843
774
703
633
562
492
422
352
282
211
141
71
1
–69
–140
–210
–280
–350
–420
–491
–561
EPSON
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Pin
Name
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
(NC)
(NC)
(NC)
(NC)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
X
Y
–5255 –631
–701
–771
–842
–912
–982
–1052
–1122
–1193
–1263
–4738 –1248
–4668
–4598
–4528
–4458
–4388
–4317
–4247
–4177
–4107
–4037
–3966
–3896
–3826
–3756
–3686
–3615
–3545
–3475
–3405
–3335
–3264
–3194
–3124
–3054
–2984
–2913
–2843
–2773
–2703
–2633
–2562
–2492
–2422
–2352
–2282
–2211
–2141
–2071
–2001
Rev. 1.1a
S1D15B01 Series
Unit: µm
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Pin
Name
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
Rev. 1.1a
X
Y
–1931 –1248
–1860
–1790
–1720
–1650
–1580
–1509
–1439
–1369
–1299
–1229
–1158
–1088
–1018
–948
–878
–807
–737
–667
–597
–527
–456
–386
–316
–246
–176
–105
–35
35
105
175
246
316
386
456
526
597
667
737
807
877
948
1018
1088
1158
1228
1299
1369
1439
1509
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Pin
Name
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
(NC)
(NC)
(NC)
COM32
COM33
COM34
X
Y
1579 –1248
1650
1720
1790
1860
1930
2001
2071
2141
2211
2281
2352
2422
2492
2562
2632
2703
2773
2843
2913
2983
3054
3124
3194
3264
3334
3405
3475
3545
3615
3685
3756
3826
3896
3966
4036
4107
4177
4247
4317
4387
4458
4528
4598
4668
4738
5248 –1225
–1155
–1085
–1015
EPSON
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
369
270
271
272
273
274
275
276
277
278
279
280
281
282
Pin
Name
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
(NC)
(NC)
X
Y
5248
–944
–874
–804
–734
–664
–593
–523
–453
–383
–313
–242
–172
–102
–32
38
109
179
249
319
389
460
530
600
670
740
811
881
951
1021
1091
1162
1232
13–5
S1D15B01 Series
5. PIN DESCRIPTION
Power supply pins
Name
I/O
VDD
VDD2
VSS
V0 , V1 , V2
V3 , V4
Supply
Supply
Supply
Supply
Description
Power supply. Connect to MPU power pin VCC.
Externally-input reference power supply for booster circuit.
This is a 0V terminal connected to the system GND.
Multi-level power supply for LCD drive. The voltages are
determined by LCD cell.The voltages should maintain the following
relationship : V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS.
When on-chip power supply circuit turns on, V0 voltage are
generated, and the following voltages are generated to V1 to V 4.
Either voltage can be selected by LCD bias set command.
V1
V2
V3
V4
Number of
pins
5
3
7
5
SED15B1
6/7 • V 0, 8/9 • V0
5/7 • V 0, 7/9 • V0
2/7 • V 0, 2/9 • V0
1/7 • V 0, 1/9 • V0
LCD power supply circuit pins
Name
CAP1+
CAP1–
CAP2+
CAP2–
CAP3+
CAP4+
VOUT
VR
I/O
O
O
O
O
O
O
O
I
Number of
pins
Boosting capacitor positive connection pin.
2
Boosting capacitor negative connection pin.
2
Boosting capacitor positive connection pin.
2
Boosting capacitor negative connection pin.
2
Boosting capacitor positive connection pin.
2
Boosting capacitor positive connection pin.
2
Booster output.
4
Voltage adjustment pin. Provides V0 voltage using external resistors.
1
When internal resistors are used, this pin cannot be used.
Description
System bus connection pins
Name
I/O
D7 to D0
I/O
(SI)
(SCL)
A0
I
CS
I
I
RES
13–6
Description
8-bit bi-directional data bus to be connected to the standard 8-bit or
16-bit MPU data bus.
When the serial interface is selected (P/S=LOW) ;
D7 : Serial data input (SI)
D6 : Serial clock input (SCL)
Control/data flag input.
A0=HIGH : The data on D7 to D0 is display data.
A0=LOW : The data on D7 to D0 is control data.
Chip select input. Data input is enable when CS is low.
When RES is caused to go low, initialization is executed.
A reset operation is performed at the RES signal level.
EPSON
Number of
pins
8
1
1
1
Rev. 1.1a
S1D15B01 Series
Pin name
I/O
RD
(E)
I
WR
(R/W)
I
C86
I
P/S
I
Description
• When connected to an 8080-series MPU ;
This is active-LOW. This pin is connected to the RD signal of the
8080-series MPU. While this signal is low, SED15B1 series data
bus is an output status.
• When connected to an 6800-series MPU ;
This is active-HIGH. This is used as an enable clock input pin of the
6800-series MPU.
• When connected to an 8080-series MPU ;
This is active-LOW. This pin is connected to the WR signal of the
8080-series MPU. The signals on the data bus are latched at the
rising edge of the WR signal.
•When connected to an 6800-series MPU ;
This is the read/write control signal input .
R/W=HIGH : Read.
R/W=LOW : Write.
MPU interface selection pin.
C86=HIGH : 6800-series MPU interface
C86=LOW : 8080-series MPU interface
Serial data input/parallel data input selection pin.
P/S=HIGH : Parallel data input
P/S=LOW : Serial data input
The following applies depending on the P/S status :
P/S Data/Command
Data
Read/Write
HIGH
A0
D7 to D0
RD, WR
LOW
A0
SI (D7)
Write only
Number of
pins
1
1
1
1
Serial Clock
SCL (D6)
In serial mode, no data can be read from DDRAM.
When P/S=LOW,D5 to D0 are HZ. D5 to D0 may be HIGH, LOW or
Open, and moreover A0, RD, WR, C86 may be HIGH, LOW or
Open.
LCD driver pins
Name
I/O
Description
Number of
pins
1
CL
I
SEG0 to
SEG131
COM0 to
COM63
COMS
O
External clock input. When external clock is halted, CL must be LOW.
If internal clock (on-chip CR oscillation circuit) is selected, CL
connected to V DD.
LCD segment driver output.
O
LCD common driver output.
64
O
LCD common driver output for the indicator. When it is not used,
it is made open.
2
132
Test pins
Name
I/O
TEST0 to
TEST13
I/O
Description
These are terminals for IC chip testing.
TEST1 to TEST4 are recommended to connect to VDD or VSS.The others set to open.
Number of
pins
14
Note and caution
• If control signal from MPU is HZ, an over-current may flow through the IC. A protection is required to prevent
the HZ signal at the input pins.
Rev. 1.1a
EPSON
13–7
S1D15B01 Series
6. FUNCTIONAL DESCRIPTION
Microprocessor Interface
Interface type selection
or LOW, it is possible to select either 8-bit parallel data
input or 8-bit serial data input as shown in Table 1.
The S1D15B01 series can transfer data via 8-bit bidirectional data buses (D7 to D0) or via serial data input
(SI). Through selecting the P/S pin polarity to the HIGH
Table 1
P/S
CS
A0
RD
WR
C86
D7
D6
D5 to D0
HIGH:Parallel Input
CS
A0
RD
WR
C86
D7
D6
D5 to D0
LOW:Serial Input
CS
A0
–
–
–
SI
SCL
–
– : HIGH, LOW or Open
Parallel interface
When the parallel interface has been selected (P/S=
HIGH), then it is possible to connect directly to either an
8080-series MPU or a 6800-series MPU (as shown in
Table 2) by selecting C86 pin to either HIGH or LOW.
Table 2
C86
CS
A0
RD
WR
D7 to D0
HIGH:6800-series MPU bus
CS
A0
E
R/W
D7 to D0
LOW:8080-series MPU bus
CS
A0
RD
WR
D7 to D0
Moreover, the S1D15B01 series identifies the data bus
signal according to A0, RD(E), WR(R/W) signals, as
shown in Table 3.
Table 3
Common
6800-series
8080-series
Function
A0
R/W
RD
WR
1
1
0
1
Reads the display data
1
0
1
0
Writes the display data
0
0
1
0
Writes control data (command)
Serial interface
When the serial interface has been selected (P/S=
LOW),only writing display data and control data is
possible by four input signals. The serial data input (SI)
and serial clock input (SCL) are enabled when CS is
low. When chip is not selected, the shift register and
counter which compose serial interface are reset.
The serial data is read from the serial data input pin in
the rising edge of the serial clocks D7,D6 through D0,
in this order. This data is converted to 8 bits parallel data
13–8
in the rising edge of the eighth serial clock for the
processing.
The A0 input is used to determine whether the serial
data input is display data or command data; when
A0=HIGH, the data is display data, and when A0=LOW
then the data is command data. The A0 input is read and
used for detection every 8th rising edge of the serial
clock after the chip becomes active.
Figure 1 is a serial interface signal chart.
EPSON
Rev. 1.1a
S1D15B01 Series
CS
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
D5
D4
D3
D2
13
14
SCL
11
12
A0
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their states.
* Reading is not possible while in serial interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise.
We recommend that operation be rechecked on the actual equipment.
In order to realize the higher speed accessing, the
S1D15B01 series can perform a type of pipeline
processing between LSIs using bus holder of internal
data bus when data is sent from/to the MPU. For
example, when the MPU writes data to the DDRAM,
once the data is stored in the bus holder, then it is written
to the DDRAM before the next data write cycle. And
when the MPU reads the contents of the DDRAM, the
first data read cycle (dummy read cycle) stores the read
data in the bus holder, and then the data is read from the
bus holder to the system bus at the next data read cycle.
Thus, there is a certain restriction in the DDRAM read
sequence. When an address is set, the specified address
data is NOT output at the immediately following read
instruction. The address data is output during second
data read. A single dummy read must be inserted after
address setup and after write cycle (refer to Figure 2).
Chip select input
The MPU interface (either parallel or serial) is enabled
only when CS=LOW.
When the chip select is inactive, D7 to D0 enter a high
impedance state, and A0, RD and WR inputs are disabled.
When the serial interface is selected, the shift register
and the counter are reset.
Access to DDRAM and internal registers
In accessing the DDRAM and the internal registers of
the S1D15B01 series, the MPU is required to satisfy the
only cycle time (tCYC ), and is not needed to consider the
wait time. Accordingly, it is possible to transfer data at
higher speed.
Internal timing
MPU
Write
WR
DATA
N
N+1
N+2
N+3
Latch
N+1
N
BUS Holder
N+2
N+3
Write Signal
Read
MPU
WR
RD
Internal timing
DATA
N
N
n
n+1
Address Preset
Read Signal
Column Address
Preset N
Bus Holder
Increment N+1
N
Address Set
#n
n
Dummy
Read
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
Figure 2
Rev. 1.1a
EPSON
13–9
S1D15B01 Series
DDRAM and page/column address circuit
The DDRAM stores pixel data for LCD. It is a 65-row
(8 page by 8 bit + 1) by 132-column addressable array.
As is shown in Figure 3, the D7 to D0 display data from
the MPU corresponds to the LCD common direction.
D0
0 1 1 1
0
COM0
D1
1 0 0 0
0
COM1
D2
0 0 0 0
0
COM2
D3
0 1 1 1
0
COM3
D4
1 0 0 0
0
COM4
—
—
DDRAM
Display on LCD
Figure 3
Each pixel can be selected when page address and
column address are specified(refer to Figure 5).
The MPU issues Page address set command to change
the page and access to another page. Page address 8
(D3,D2,D1,D0 = 1,0,0,0) is DDRAM area dedicate to
the indicator, and display data D0 is only valid.
The DDRAM column address is specified by Column
address set command. The specified column address is
automatically incremented by +1 when a Display data
read/write command is entered. After the last column
address (83H), column address returns to 00H and page
address incremented by +1 (refer to Figure 4). After the
very last address (column = 83H,page = 8H),both column
address and page address return to 00H (column address
= 00H, page address = 0H).
Data
D0
D1
D2
D3
D4
D5
D6
0H
0
1
2
130
131
D7
1H
132
133
134
262
263
2H
264
265
266
394
395
3H
396
397
398
526
527
4H
528
529
530
658
659
5H
660
661
662
790
791
6H
792
793
794
922
923
7H
924
925
926
1054
1055
8H
1056 1057 1058
1186
1187
00H
82H
83H
Page address
01H
02H
Column address
D0
Data for the page address 8H
Figure 4
The MPU reads from and writes to the DDRAM through
the I/O buffer independent of the LCD controller
operation. Therefore, data can be written to the DDRAM
at the same time as data is being displayed, without
causing the LCD to flicker.
13–10
Furthermore, as is shown in Table 4, Segment driver
direction select command can be used to reverse the
relationship between the DDRAM column address and
segment output. This allows flexible IC layout during
LCD module assembly.
EPSON
Rev. 1.1a
S1D15B01 Series
Table 4
Column Address
00H
01H
02H
81H
82H
83H
Normal Direction
SEG0
SEG1
SEG2
SEG129
SEG130
SEG131
Reverse Direction
SEG131
SEG130
SEG129
SEG2
SEG1
SEG0
Line address circuit
The line address circuit specifies the line address (as
shown Figure 5) relating to the COM output when the
contents of the DDRAM are displayed. The display start
line address, what is normally the top line of the display,
can be specified by Display start line address set
command. And Common driver direction select
command can be used to reverse the relationship between
the DDRAM line address and common output. For
example, as is shown in Table 5, the display start line
address corresponds to the COM0 output when the
common driver direction is normal, or the COM63
output when common driver direction is reversed.And
the display area is followed by the higher number line
addresses in ascending order from the display start line
address, corresponding to the duty cycle. This allows
flexible IC layout during LCD module assembly.
If the display start line address is changed dynamically
using the Display start line address set command,then
screen scrolling and page swapping can be performed.
Table 5 (at display start line address=1CH)
Line Address
1CH
1DH
3FH
00H
1AH
1BH
Normal Direction
COM0
COM1
COM35
COM36
COM62
COM63
Reverse Direction
COM63
COM62
COM28
COM27
COM1
COM0
Display data latch circuit
The display data latch circuit is a latch temporarily
stored the display data that is output to the LCD driver
circuit from the DDRAM.
Display ON/OFF command, Display normal/reverse
Rev. 1.1a
command, and Displayed all points ON/OFF command
control only the data within the latch, and do not change
the data within the DDRAM.
EPSON
13–11
S1D15B01 Series
Display Data RAM
The display data RAM stores pixel data for the LCD.
It is a 132-colunm×65-row addressale array as shown in Figure 5.
Page Address
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
7DH 7EH 7FH 80H 81H 82H 83H
Normal Direction
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
Page 8
00H 01H 02H 03H 04H 05H 06H
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Reverse Direction
SEG131
SEG130
SEG129
SEG128
SEG127
SEG126
SEG125
1
0
0
Column Address
Line
Address
Data
SEG
Output
Start
COM Output
Normal Reverse
Direction Direction
COM0 COM63
COM1 COM62
COM2 COM61
COM3 COM60
COM4 COM59
COM5 COM58
COM6 COM57
COM7 COM56
COM8 COM55
COM9 COM54
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COMS COMS
Regardless of the display start
line address, S1D15B01
accesses 65th line.
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
D3
Figure 5
13–12
EPSON
Rev. 1.1a
S1D15B01 Series
Oscillation circuit
The S1D15B01 series has a complete on-chip CR
oscillation circuit, and its output is used as the display
timing signal source.
The on-chip oscillation circuit is available when CL =
HIGH.
And the S1D15B01 series is also capable external clock
input from CL pin. (When external clock is halted, CL
must be LOW.)
Display timing generator circuit
and the display data latch circuit. The display data is
latched to the display data latch circuit and is output to
the segment drive output pin by synchronizing to the
display clocks. The read operation of display data to the
liquid crystal drive circuit is completely independent of
the access to the display data RAM from MPU. Therefore
even when the display data RAM is asynchronously
accessed during liquid crystal display, the access will
not have any adverse effect on the display such as
flickering.
The circuit also generates COM scan signal and the
LCD AC signal (FR) from the display clocks. As shown
in Figure 6, the FR normally generates the 2- frame AC
drive waveforms .
The display timing generator circuit generates the timing
signals from the display clocks to the line address circuit
2-frame AC drive waveforms
64 65 1
2
3
4
5
6
60 61 62 63 64 65 1
2
3
4
5
6
CL
FR
V0
V1
COM0
V4
VSS
V0
V1
COM1
V4
VSS
RAM
DATA
V0
V2
SEGn
V3
VSS
Figure 6
Rev. 1.1a
EPSON
13–13
S1D15B01 Series
LCD driver circuits
These are multiplexers outputting the LCD panel driving
4-level signal which level is determined by a combination
of display data, COM scan signal, and LCD AC signal
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
(FR). Figure 7 shows an example of SEG and COM
output waveforms.
FR
VDD
VSS
COM0
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
COM1
COM2
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
SEG0
SEG1
SEG2
V5
V4
V3
V2
V1
VDD
—V1
—V2
—V3
—V4
—V5
COM0—SEG0
V5
V4
V3
V2
V1
VDD
—V1
—V2
—V3
—V4
—V5
COM0—SEG1
Figure 7
13–14
EPSON
Rev. 1.1a
S1D15B01 Series
Power supply circuit
The power supply circuit generates the voltage to drive
the LCD panel at low power consumption.
The power supply circuit consists of a booster circuit,
voltage regulator circuit, and voltage follower circuit,
and is controlled by Power control set command. Using
this command, the booster circuit, the voltage regulator
circuit, and the voltage follower circuit can be
independently turned ON or OFF. In the case of using
S1D15B01D00B* which use a booster circuit, voltage
regulator circuit, and voltage follower circuit, every
circuit is required to be turnend ON or OFF at the same
time by Power control set command. In the case of
using S1D15B01D00B*/S1D15B01D02B* which need
the external power supply and use part of on-chip power
supply circuit, each must be set the appropriate state as
shown in the Table 6.
Table 6
Power supply
condition
Product name*2
On-chip power
supply used
S1D15B01D00B*
ON
ON
Voltage regulator
circuit and Voltage
follower circuit only
S1D15B01D01B*
OFF
Voltage follower
circuit only
S1D15B01D01B*
OFF
Booster Voltage Voltage
circuit regulator follower
circuit
circuit
External
voltage
input
Boosting
system pin* 3
ON
VDD2
Used
ON
ON
VOUT
Open
OFF
ON
V0=V OUT*4
Open
External power
S1D15B01D02B*
OFF
OFF
OFF
V0=V OUT*4
supply only
V1 to V4
*1 Combinations other than those shown in above table are possible but impractical.
*2 Chose the appropriate product according to the power supply condition.
*3 The boosting system pin indicates the CAP+, CAP1–, CAP2+, CAP2–, CAP3+, and CAP4+ pin.
*4 Both V0 pin and V OUT pin should be connected to external power supply.
Open
Booster circuit
Using the booster circuit, it is possible to produce
Quintuple/Quadruple/Triple/Double boosting of the
VDD2-V SS voltage level.
Quintuple boosting :
Connect capacitor between CAP1+ and CAP1–, between
CAP2+ and CAP2–, between CAP3+ and CAP1–,
between CAP4+ and CAP2–, between VOUT and VDD2,
the potential between VDD2 and VSS is boosted to
quintuple toward the positive side and it is output at
VOUT pin.
Quadruple boosting :
Connect capacitor between CAP1+ and CAP1–, between
CAP2+ and CAP2–, between CAP3+ and CAP1–,
between VOUT and VDD2, and jumper between CAP4+
and V OUT , the potential between VDD2 and VSS is
Rev. 1.1a
boosted to quadruple toward the positive side and it is
output at VOUT pin.
Triple boosting :
Connect capacitor between CAP1+ and CAP1–, between
CAP2+ and CAP2–, between VOUT and VDD2, and
jumper between CAP3+, CAP4+ and VOUT, the triple
boosted voltage appears at VOUT pin.
Double boosting :
Connect capacitor between CAP1+ and CAP1–, between
VOUT and V DD2, open CAP2–, and jumper between
CAP2+, CAP3+, CAP4+ and VOUT, the double boosted
voltage appears at VOUT pin.
The boosted voltage relationships are shown in Figure
8.
EPSON
13–15
S1D15B01 Series
CAP3+
CAP1–
+
CAP1+
+
CAP4+
VOUT
+
CAP3+
CAP1–
+
CAP4+
CAP2–
+
CAP1+
+
VOUT
CAP3+
CAP1–
+
CAP1+
CAP4+
CAP2–
+
CAP2+
CAP2–
+
CAP2+
+
VOUT
CAP3+
CAP1–
+
CAP1+
CAP4+
OPEN
CAP2+
Quadruple Boosting
Quintuple Boosting
VDD2 or VSS
S1D15B01 Series
+
+
S1D15B01 Series
VOUT
VDD2 or VSS
S1D15B01 Series
+
VDD2 or VSS
S1D15B01 Series
VDD2 or VSS
CAP2–
CAP2+
Triple Boosting
Double boosting
VOUT = 5 x VDD2
= 13.5V
VOUT = 4 x VDD2
= 10.8V
VOUT = 3 x VDD2
= 8.1V
VOUT = 2 x VDD2
= 5.4V
VDD2 = 2.7V
VDD2 = 2.7V
VDD2 = 2.7V
VDD2 = 2.7V
VSS = 0V
VSS = 0V
VSS = 0V
VSS = 0V
Quintuple Boosting
Quadruple Boosting
Triple Boosting
Double boosting
Figure 8
* VDD2 voltage must be set so that VOUT voltage does not exceed the absolute maximum rated value.
* The Capacitance depend on the load of the LCD panel to be driven. Set a value that LCD driver voltage may be stable
(reference value = 1.0 to 4.7 µF).
Voltage regulator circuit
The boosting voltage occurring at the VOUT pin is sent
to the voltage regulator, and the V0 voltage (LCD driver
voltage) is output.
Because the S1D15B01 series has the high-accuracy
constant voltage source, the 32-level electronic volume
function and the internal resistor for the V0 voltage
regulator (= V0 -resistor), it is possible to construct a
high-accuracy voltage regulator circuit without external
component. And V 0 voltage can be adjusted by
commands only to adjust the LCD contrast.
(A) When the V0-resistor is used.
Through the use of the V0 -resistor and the electronic
volume function, V0 voltage can be controlled by
commands only (without adding any external resistors).
The V0 voltage can be calculated using the following
13–16
equations within the range of V0 < VOUT.
V 0 = (1+Rb/Ra)•VEV
VEV = (1–α/200) •VREG (Equation A-1)
VREG is the on-chip constant voltage as shown in Table
7 at Ta=25°C.
EPSON
Table 7
Model
VREG
Thermal Gradient
S1D15B01*****
1.3V
–0.05%/°C
Rev. 1.1a
S1D15B01 Series
Internal Rb
–
V0
+
VEV (Constant voltage source
+ electronic volume)
Internal Ra
VSS
Figure 9
α is a value of the electronic volume, and can be set to
one of 32-states by Electronic volume command setting
the 5-bit data in the electronic volume register. Table 8
shows the value of α.
Table 8
Rb/Ra is the V0-resistor ratio, and can be set to one of
7-states by V0-resistor ratio set command setting the 3bit data in the V0 -resistor ratio register. Table 9 shows
the value of (1+Rb/Ra) ratio (reference value).
Table 9
D4
D3
D2
D1
D0
α
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
:
:
1
1
1
0
1
1
1
0
1
31
30
29
:
:
2
1
0
1+Rb/Ra
D3
D2
D1
S1D15B01
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5.60
5.86
6.15
6.46
6.81
7.20
7.64
External resistor can be used.
Figure 10 shows V0 voltage measured by V0-resistor ratio and electronic voltage at Ta=25°C.
V0 - resister ratio
11
110
101
100
011
010
001
000
10
9
8
V0 [V]
7
6
5
4
3
2
1
1EH
19H
14H
0FH
0AH
05H
00H
0
Electronic volume resister
Figure 10
Rev. 1.1a
EPSON
13–17
S1D15B01 Series
<Setup example>
When selection Ta=25°C and V0=7V for S1D15B01 series on which temperature gradient=–0.05%/°C. Using Figure
10 and equation A-1, the following setup is enabled.
Table 10
Commands
Register
D7
D6
D5
D4
D3
D2
D1
D0
V0-resister ratio set
0
0
1
0
0
0
0
1
Electronic volume
1
0
0
1
0
0
0
1
In this case, the variable range and the notch width of the V0 voltage is shown as Table 11, as dependent on the electronic
volume.
Table 11
V0
Min.
Typ.
Max.
Units
Variable range
Notch width
6.44[α=31]
7.05[α=15]
37
7.62[α=0]
[V]
[mV]
(B) When external resistors are used. (1)
(The V0-resistor is not used.)
The V0 voltage can also be set without using the V0-resistor by adding resistors Ra' and Rb' between VSS and VR, and
between VR and V 0, respectively. In this case, the electronic volume command makes it possible to adjust the contrast
of the LCD by controlling V0 voltage. In the range where V0 < VOUT, the V0 voltage can be calculated using equation
B-1 based on the external resistors Ra' and Rb'.
V0=(1+Rb'/Ra')•V EV
VEV=(1–α/200)•VREG
(Equation B-1)
VREG is the on-chip constant voltage as shown in Table 8 at Ta=25°C.
External Rb'
–
V0
+
VEV (Constant voltage source + electronic volume)
External Ra'
VSS
Figure 11
13–18
EPSON
Rev. 1.1a
S1D15B01 Series
<Setup example>
When selection Ta=25°C and V0=11V for S1D15B01 series on which temperature gradient=–0.05%/°C.
The central value of the electronic volume register is (D5, D4, D3, D2, D1, D0)=(1, 0, 0, 0, 0,), that is α=15.
So, according to equation B-1 and VREG=1.3V, the Rb'/Ra' is shown as follows.
V0 =(1+Rb'/Ra')•(1–α/200) •VREG
11V =(1+Rb'/Ra')•(1–15/200) •1.3V
(Equation B-2)
Moreover, when the value of the current running through Ra' and Rb' is set to 5 µA,
Ra'+Rb'=2.2MΩ
(Equation B-3)
Consequently, by equation B-2 and B-3,
Rb'+Ra'=8.15
Ra'=240kΩ
Ra'=1960kΩ
In this case, the variable range and the notch width of the V0 voltage is, as shown Table 12, as dependent on the electronic
volume.
Table 12
V0
Min.
Typ.
Max.
Units
Variable range
Notch width
10.01[α=31]
11.0[α=15]
59
11.9[α=0]
[V]
[mV]
(C) When external resistors are used. (2)
(The V0 -resistor is not used.)
When the external resistors described above are used, adding a variable resistor as well make it possible to perform fine
adjustments on Ra' and Rb', to set the V0 voltage. In this case, the electronic volume function makes it possible to control
the V0 voltage by commands to adjust the LCD contrast. In the range where V0<VOUT the V0 voltage can be calculated
by equation C-1 below based on the R1 and R2 (variable resistors) and R3 settings, where R2 can be subjected to fine
adjustments (∆ R2).
V0 ={1+(R3+R2–∆ R2)/(R1+∆ R2)}•VEV
={1+(R3+R2–∆ R2)/(R1+∆ R2)}• (1–α/200)•VREG
∴
[
VEV=(1–α/200)•VREG]
Rb'
(Equation C-1)
External
resistor R3
External
resistor R2
R2
+
VR
V0
–
Ra'
External
resistor R1
VEV (Constant voltage source + electronic volume)
VSS
Figure 12
Rev. 1.1a
EPSON
13–19
S1D15B01 Series
<Setup example>
When selection Ta=25°C and V0 =5V to V0=9V (using R2) for S1D15B01 series on which temperature gradient=–
0.05%/°C.
The central value of the electronic volume register is (D5, D4, D3, D2, D1, D0)=(1, 0, 0, 0, 0,), that is α=15.
So, according to equation C-1 and VREG=1.3V, the R1, R2, R3, are shown as follows. (when ∆ R2=0Ω at V0=9V and
∆ R2=R2 at V0=5V)
9V ={1+(R3+R2)/R1}•(1–15/200) •1.3V
(Equation C-2)
5V ={1+R3/(R1+R2)}•(1–15/200) •1.3V
(Equation C-3)
Moreover, when the value of the current running through V0 and VSS is set to 5 µ A at V 0=7V (central value),
R1+R2+R3=1.4MΩ
(Equation C-3)
With this, according to equation C-2, C-3 and C-4,
R1=187kΩ
R2=150kΩ
R3=1063kΩ
In this case, if V0 is set to 7V as central value, ∆ R2 becomes 53kΩ
And, the variable range and the notch width of the V0 voltage is, as shown Table 13, as dependent on the electronic
volume. (∆ R2=53kΩ)
Table 13
V0
Min.
Typ.
Max.
Units
Variable range
Notch width
6.41[α=31]
7.0[α=15]
37
7.58[α=0]
[V]
[mV]
* When the V0-resistor or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit
and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary
to provide a voltage from VOUT when the Booster circuit is OFF.
* The VR terminal is enabled only when the V0-resistor is not used. When the V0-resistor is used, then the VR terminal
is left open.
* Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield
cables, etc. to handle noise.
Voltage Follower Circuit
The V0 voltage is divided to generate the V1 , V2 , V3 and V4 voltages by on-chip resistor circuit. And the V1, V2, V3
and V4 voltages are impedance-converted by voltage follower,and provide to LCD driver circuit.
LCD bias ratio can be selected by LCD bias set command which is 1/7 bias or 1/9 bias for S1D15B01 series.
Power supply turn off sequence
Only S1D15B01D00B* which is used as on-chip power supply LCD driver, has the faculty of VOUT shorts to VDD2
when the RES pin is LOW, and V0 shorts to VSS when the RES pin is LOW or reset command is issued. When the onchip power supply is turned off, it is recommended to be the RES pin is LOW., for the purpose of the electric discharge
on the LCD panel.
S1D15B01D00B*/S1D15B01D02B* which is used as external power supply LCD driver, don't have such a discharge
faculty, so that VOUT and V0 need to short to VSS, when the external power supply turn off or power saver.
See the section on the Command Description for details.
13–20
EPSON
Rev. 1.1a
S1D15B01 Series
Reference Circuit Examples
Figure 13 ~ 18 shoes reference circuit examples.
(1) When used all of the booster circuit, voltage regulator circuit and V/F circuit [S1D15B01D00B*]
C1
C1
C1
C1
C1
VDD
VDD2
VOUT
CAP3+
CAP1CAP1+
CAP4+
CAP2CAP2+
V0
VR
VDD
C1
C1
C1
S1D15B01 Series
VDD
2 Use the voltage regulator with external resistor
(Example where VDD=VDD2, with 5 × boosting)
C1
C1
R3
VR
R1
V1
VSS
V0
R2
VSS
VDD
VDD2
VOUT
CAP3+
CAP1CAP1+
CAP4+
CAP2CAP2+
S1D15B01 Series
1 Use the voltage regulator with V0 -resistor
(Example where VDD=VDD2, with 5 × boosting)
VSS
V1
VSS
V2
V2
V3
V3
V4
V4
Figure 13
Figure 14
(2) When used only the voltage regulator circuit and V/F circuit [S1D15B01D01B*]
Extemal
power
supply
VDD
VDD2
VOUT
CAP3+
CAP1CAP1+
CAP4+
CAP2CAP2+
V0
VR
VDD
Extemal
power
S1D15B01 Series
VDD
2 Use the voltage regulator with external resistor
supply
R3
R2
R1
VSS
V1
VSS
VSS
V0
VR
VSS
V1
V2
V2
V3
V3
V4
V4
Figure 15
Rev. 1.1a
VDD
VDD2
VOUT
CAP3+
CAP1CAP1+
CAP4+
CAP2CAP2+
S1D15B01 Series
1 Use the voltage regulator with V0 -resistor
Figure 16
EPSON
13–21
S1D15B01 Series
(3) When used only the V/F circuit
[S1D15B01D01B *]
power
supply
V0
VR
VDD
VDD
VDD2
VOUT
CAP3+
CAP1CAP1+
CAP4+
CAP2CAP2+
V0
VR
VSS
VSS
V1
VSS
S1D15B01 Series
Extemal
VDD
VDD2
VOUT
CAP3+
CAP1CAP1+
CAP4+
CAP2CAP2+
S1D15B01 Series
VDD
(4) When the on-chip power supply is not used
[S1D15B01D02B*]
V1
VSS
Extemal
V2
V2
power
V3
V3
supply
V4
Figure 17
V4
Figure 18
Example of shared reference settings
When V0 can vary between 8 and 12V
ltem
C1
Set value
1.0 ~ 4.7
Units
µF
Figure 14
* Because the VR terminal input impedance is high, use short leads and shield lines.
13–22
EPSON
Rev. 1.1a
S1D15B01 Series
Reset Circuit
When RES pin goes low,or when Reset command is
used,this LSI is initialized.
Initialized states :
• Serial interface internal shift register and counter
clear
• Power saver mode is entered.
• Oscillation circuit is stopped.
• The LCD power supply circuit is stopped.
• Display OFF
• Display all points ON
• Segment/common driver outputs go to the VSS
level.
• Display normal
• Page address=0H
• Column address=00H
• Display start line address=00H
• Segment driver direction = normal
• Common driver direction = normal
• Read modify write OFF
• Power control register (D2, D1, D0) = (0, 0, 0)
• V0 -resistor ratio register (D2, D1, D0) = (0, 0, 0)
• Electronic volume register (D4, D3, D2, D1, D0) =
(1, 0, 0, 0, 0)
• LCD power supply bias ratio = 1/7 bias
• Test mode is released.
• V0 is shorted to VSS *1
• VOUT is shorted to VDD2 *1*2
When reset is detected, this LSI is set to above initialized
states. However it has no effect on contents of DDRAM.
As seen in “Microprocessor Interface (Reference
Example)”, connect RES pin to the reset pin of the MPU
and initialize the MPU at the same time. The initialization
by RES pin is always required during power-on.
If the control signal from MPU is HZ, an overcurrent
may flow through the LSI. A protection is required to
prevent the HZ signal at the input pin during power-on.
In case the S1D15B01 series does not use the on-chip
LCD power supply circuit, RES pin must be HIGH
when the external LCD power supply is turned on.
* 1 This faculty is available only S1D15B01D00B*.
* 2 This faculty is not available by reset command, it is abailable only when hard reset : RES=LOW is active.
Rev. 1.1a
EPSON
13–23
S1D15B01 Series
7. COMMAND DESCRIPTION
The S1D15B01 series identifies the data bus by a combination of A0, RD (E), WR (R/W) signals.
In the 8080-series MPU interface, the command is activated when a low pulse is input to RD pin for reading and when
a low pulse is input to WR pin for writing. In the 6800-series MPU interface, the S1D15B01 series enters a read mode
when a high level is input to R/W pin and a write mode when a low level is input to R/W pin, and the command is activated
when a high pulse is input to E pin. Therefore, in the command explanation and command table, the 6800-series MPU
interface is different from the 8080-series MPU interface in that RD (E) becomes “1 (H)” in Display data read command.
And when the serial interface is selected, the data is input in sequence starting with D7.
Taking the 8080-series MPU interface as an example, commands will be explained below.
Explanation of commands
(1) Display ON/OFF
This command turns the display ON and OFF.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
1
1
1
0
1
Display OFF
Display ON
When the Display OFF command is executed when in the Display all points ON mode , Power saver mode is entered.
See the section on the Power saver for details.
(2) Display normal/reverse
This command can reverse the lit and unlit display without overwriting the contents of the DDRAM.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
0
1
1
0
Normal:DDRAM Data HIGH
=LCD ON voltage
Reverse:DDRAM Data LOW
=LCD ON voltage
1
(3) Display all points ON/OFF
This command makes it possible to force all display points ON regardless of the content of the DDRAM. Even when
this is done, the DDRAM contents are maintained. This command takes priority over the Display normal/reverse
command.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
0
1
0
0
1
Normal display mode
Display all points ON
When the Display all points ON command is executed when in the Display OFF mode, Power saver mode is entered.
See the section on the Power saver for details.
13–24
EPSON
Rev. 1.1a
S1D15B01 Series
(4) Page address set
This command specifies the page address of the DDRAM (refer to Figure 5).
Specifying the page address and column address enables to access a desired bit of the DDRAM. After the last column
address (83H), page address incremented by +1 (refer to Figure 4). After the very last address (column = 83H, page =
8H), page address return to 0H.
Page address 8H is the DDRAM area dedicate to the indicator, and only D0 is valid for data change.
See the function explanation in “DDRAM and page/column address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Page address
1
0
1
1
0
0
0
0
0
0
:
1
0
0
0
1
0
1
0
1
0
1
0
0H
1H
2H
:
7H
8H
0
1
(5) Column address set
This command specifies the column address of the DDRAM (refer to Figure 5).
The column address is split into two sections (the upper 4-bits and lower 4-bits) when it is set (fundamentally, set
continuously).
Each time the DDRAM is accessed, the column address automatically increments by +1, making it possible for the MPU
to continuously access to the display data. After the last column address (83H) ,column address returns to 00H (refer
to Figure 4).
See the function explanation in “DDRAM and page/column address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
A7
A3
A6
A2
A5
A1
A4
A0
Upper bit address
Lower bit address
A7
A6
A5
A4
A3
A2
A1
A0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
:
0
0
0
0
1
1
0
1
00H
01H
02H
:
82H
83H
(6) Display start line address set
This command is used to specify the display start line address of the DDRAM (refer to Figure 5).
If the display start line address is changed dynamically using this command, then screen scrolling, page swapping can
be performed.
See the function explanation in “Line address circuit”, for detail.
A0
0
Rev. 1.1a
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Line address
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
0
0
0
:
1
1
1
1
1
1
0
1
00H
01H
02H
:
3EH
3FH
EPSON
13–25
S1D15B01 Series
(7) ADC Select (Segment driver direction select)
This command can reverse the correspondence between the DDRAM column address and the segment driver output.
See the function explanation in “DDRAM and page/column address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
0
0
0
0
1
Normal
Reverse
(8) Common driver direction select
This command can reverse the correspondence between the DDRAM line address and the common driver output. See
the function explanation in “Line address circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
1
0
0
0
1
*
*
*
Normal
Reverse
*Disabled bit
(9) Display data read
This command reads 8-bit data from the specified DDRAM address. Since the column address is automatically
incremented by +1 after each read ,the MPU can continuously read multiple-word data. One dummy read is required
immediately after the address has been set. See the function explanation in “Access to DDRAM and internal registers”
and “DDRAM and page/column address circuit”, for detail.
A0
1
E R/W
RD WR
0
D7
D6
D5
1
D4
D3
D2
D1
D0
Read Data
(10) Display data write
This command writes 8-bit data to the specified DDRAM address. Since the column address is automatically
incremented by +1 after each write ,the MPU can continuously write multiple-word data. See the function explanation
in “DDRAM and page/column address circuit”, for detail.
A0
1
13–26
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write Data
EPSON
Rev. 1.1a
S1D15B01 Series
(11) Read modify write
This command is used paired with End command. Once this command is issued, the column address is not incremented
by Display data read command, but is incremented by Display data write command. This mode is maintained until End
command is issued. When End command is issued, the column address returns to the address it was at when Read modify
write command was issued. This function makes it possible to reduce the MPU load when there are the data to change
repeatedly in a specified display region, such as blinking cursor.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
0
0
*When End command is issued, only column address returns to the address it was at when Read modify write
command was issued, but page address does not return. Consequently, Read modify Write mode cannot be used
over pages.
*Even if Read modify write mode, other commands besides Display data read/write can also be used. However,
Column address set command cannot be used.
The sequence for cursor display
Page Address Set
Column Address Set
Read Modify Write
Dummy Read
Data Read
Data Write
No
Completed?
Yes
End
Figure 19
Rev. 1.1a
EPSON
13–27
S1D15B01 Series
(12) End
This command releases the Read modify write mode, and returns the column address to the address it was when Read
modify write command was issued .
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
•••
N+m
N
End
Read Modify Write
Figure 20
(13) Power control set
This command sets the on-chip power supply function ON/OFF. See the function explanation in “Power supply circuit”,
for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
0
0
1
0
1
0
1
D1
D0
Mode
0
1
Booster : OFF
Booster : ON
Voltage regulator : OFF
Voltage regulator : ON
Voltage follower : OFF
Voltage follower : ON
0
1
(14) V0-resistor ratio set
This command sets the internal resistor ratio “Rb/Ra” for the V0 voltage regulator to adjust the contrast of LCD panel
display. See the function explanation in “Power supply circuit”, for detail.
A0
0
13–28
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EPSON
Rb/Ra : V 0 voltage
SMALL
LOW
↓
↓
LARGE
HIGH
External resistor mode
Rev. 1.1a
S1D15B01 Series
(15) Electronic volume
This command sets a value of electronic volume “α” for the V0 voltage regulator to adjust the contrast of LCD panel
display. See the function explanation in “Power supply circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
α
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
31
LOW
↓
↓
1
1
1
1
0
0
0
↓
1
1
1
1
0
1
0
HIGH
:
V0 voltage
(16) LCD bias set
This command selects the voltage bias ratio required for the LCD. This command is enabled when the voltage follower
circuit operates.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Bias
S1D15B01
1
0
1
0
0
0
1
0
1
1/9 bias
1/7 bias
(17) Power saver
When the display all points ON command is executed when in the display OFF mode, power saver mode is entered, and
the power consumption can be greatly reduced.
Power saver (Display OFF & Display all points ON)
Power saver mode
Power saver OFF (Display all points OFF)
Power saver mode cancel
Figure 21
This mode stops every operation of the LCD display system, and can reduce current consumption nearly to a static
current value if no access is made from the MPU. The internal states in the power saver mode is as follows:
• The oscillation circuit is stopped.
• The LCD power supply circuit is stopped.
• The LCD driver circuit is stopped and segment/common driver outputs output the VSS level.
• The display data and operation mode before execution of the Power saver command are held, and the MPU can
access to the DDRAM and internal registers.
Rev. 1.1a
EPSON
13–29
S1D15B01 Series
(18) Reset
This LSI is in initialized by this command. And when S1D15B01D00B* is used, V0 is shorted to VSS. (Only when RES=
LOW, VOUT is shorted to VSS. So VOUT is not shorted to VSS by this commands.) See the function explanation in “Reset
circuit”, for detail.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
1
1
(19) NOP
Non-operation command
A0
0
E R/W
RD WR
1
0
(20) Test
This is a command for LSI chip testing. Please do not use. If the test command is issued by accident, it can be cleared
by applying an LOW signal to the RES pin, or by issuing the Reset command or the Display ON/OFF command.
A0
0
E R/W
RD WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
*
1
*
*
*
*
* Disabled bit
(Note):
The S1D15B01 series chip maintain their operating modes ,but excessive external noise, etc., may happen to change
them. Thus in the packaging and system design it is necessary to suppress the noise or take measures to prevent the noise.
Moreover, it is recommended that the operating modes are refreshed periodically to prevent the effects of unanticipated
noise.
13–30
EPSON
Rev. 1.1a
S1D15B01 Series
Command Table
Table 14
Code
A0 XR XW D7 D6 D5 D4 D3 D2 D1 D0
Function
0 1
0
1
0 1 0 1 1 1 0
LCD display
1
0:OFF, 1:ON
(2) Display normal/reverce 0 1
0
1
0 1 0 0 1 1 0
LCD display
1
0:normal, 1:reverce
(3) Display all points ON/OFF 0 1
0
1
0 1 0 0 1 0 0
LCD display
1
0:normal display, 1:all points ON
(4) Page address set
0 1
0
1
0 1 1 address
Sets the DDRAM page address
Command
(1) Display ON/OFF
(5) Column address set
Upper 4-bit address
Column address set
Lower 4-bit address
(6) Display start line
address set
(7) Segment driver
directuin select
0
1
0
0
0
0
1
address
Sets the DDRAM column address
0
1
0
0
0
0
0
address
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
1
(8) Common driver
direction select
0
1
0
1
1
0
0
0
1
*
*
*
(9) Display data read
1
0
1
Read data
Sets the DDRAM display start line
address.
Sets the correspondence
between the DDRAM column
address and the SEG driver output.
0:normal, 1:reverse
Sets the correspondence
between the DDRAM line address
and the COM driver output.
0:normal, 1:reverse
Reads from the DDRAM.
(10) Display data write
1
1
0
Write data
Writes to the DDRAM.
(11) Read modify write
0
1
0
1
1
1
0
0
0
0
0
(12) End
0
1
0
1
1
1
0
1
1
1
0
(13) Power control set
0
1
0
0
0
1
0
1
(14) V 0-resistor ratio set
0
1
0
0
0
1
(15) Electronic volume
0
1
0
1
0
0
(16) LCD bias set
0
1
0
1
0
1
(17) Power saver
-
-
-
-
-
-
Operating
mode
0 0 Resistor
ratio
Electronic volume
value
0 0 0 1 0
1
- -
(18) Reset
0
1
0
1
1
1
0
0
0
1
0
Sets the LCD drive voltage bias ratio.
S1D15B01 0:1/9bias, 1:1/7bias
Compound command of Display
OFF and Display all points ON
Internal reset
(19) NOP
0
1
0
1
1
1
0
0
0
1
1
Non-operation
(20) Test
0
1
0
1
1
*
1
*
*
*
*
IC test command. Do not use.
address
Column address increment
at write:+1, at read:0.
Releases Read modify write mode.
Sets the on-chip power supply
circuit operating mode.
Sets the V0-resistor ratio value.
Sets the electronic volume value.
(Note)*:disabled bit
Rev. 1.1a
EPSON
13–31
S1D15B01 Series
8. COMMAND SETTING
Instruction Setup of S1D15B01D00B* : Reference
(1) Initialization
Turn on the VDD - VSS, VDD2 - VSS keeping
the RES pin = LOW *1
When the power is stabilized
Release the reset state. (RES pin = HIGH)
Initialize state (Default) *2
Function set up by command input (user setup)
(2)Display normal/reverse *3
(7)Segment driver direction set *4
(8)Common driver direction set *5
(16)LCD bias set *6
Function set up by command input (user setup)
(14)Setting built-in resistance ratio for
regulation of the V0 voltage *7
(15)Electronic volume control set *8
Power saver OFF
(17)Display all points OFF *9
Function set up by command input (user setup)
(13)Power control set *10
This concludes the initialization
Notes: Refer to respective sections or paragraphs listed below
*1: Description of Timing characteristics; Notes for Power on Sequence
*2: Description of functional; Reset Circuit
*3: 7.Command Description; Display normal/reverse
*4: 7.Command Description; Segment driver direction select
*5: 7.Command Description; Common driver direction select
*6: 7.Command Description; LCD bias set
*7: Description of functions; Power supply circuit & Command description; V0-resistor ratio set
*8: Description of functions; Power supply circuit & Command description; Electronic volume
*9: 7.Command Description; Power saver
*10: Description of functions; Power supply circuit & Command description; Power control set
13–32
EPSON
Rev. 1.1a
S1D15B01 Series
(2) Data display
End of initialization
Function set up by command input (user setup)
(6) Display start line address set *11
(4) Page address set *12
(5) Column address set *13
Function set up by command input (user setup)
(10) Display data write *14
Function set up by command input (user setup)
(1) Display ON/OFF *15
End of data display
Notes:
*11:
*12:
*13:
*14:
*15:
Reference items
7.Command Description; Display start line address set
7.Command Description; Page address set
7.Command Description; Column address set
7.Command Description; Display data write
7.Command Description; Display ON/OFF
(3) Power OFF *16
Optional status
Function set up by command input (user setup)
(17)Power saver *17
Reset active
(18)RES pin = LOW or reset command *18
(19)Turn OFF the VDD2 - VSS, VDD - VSS *19
Notes: Reference items
*16: After turning OFF the internal power supply, turn OFF the power supply of this IC.
(Function Description; Power supply circuit)
When the power of this IC is turned OFF with the internal power supply is held in the ON status, since the where
the voltage is supplied, even though an only little, to on chip LCD drive circuit is still continued, it is featured
to ill affect the display quality of the LCD panel. To avoid this, be sure to observe the power OFF sequence
strictly.
*17: 7.Command Description; Power saver
*18: It is recommended to be RES pin=LOW. Only if it is not possible to be RES pin=LOW, ase reset command.
*19: Set the time tL from reset active to turning off the V DD2/VDD power, longer then the time tH when the potential
of V 0 ~ V4 becomes below the threshold voltage (approximately 1V) of the LCD panel. (tL > t H) If t L < tH, an
irregular display may occur.
Refer to the < Reference Data > as below. When tH is too long, insert a resis for between V0 and V SS to reduce
it.
Rev. 1.1a
EPSON
13–33
S1D15B01 Series
<Reference Data>
Condition: VDD=VDD2=1.8V, Quintuple boosting, Boosting Capacitance 1 µ F,
Set the V0 voltage to 8V
tH (µ s) is calculated the following equation.
tH=tH0×V0+∆ tH×CL×V0
CL
:The capacitance of LCD panel connected between V0 and VSS
tH0
:tH at the CL=0
∆ tH :tH when the V0 drops 1V per the CL=1pF.
This is reference data, so it is needed to estimate a real LCD module since t H is depends on the V DD/VDD2 voltage and
the capacitance of LCD panel.
1 In case of RES pin=LOW
RES = L
VDD2
/VDD
Power
saver
Power OFF
tL
1.7V
SEG
VSS
As power VDD, VDD2 is
shut off, it becomes
COM
VSS
impossible to fix output
V0
V1
V2
V3
V4
VSS
At or under Vth on LCD.
Use 1.0[V] as a reference.
tH
Figure 22
S1D15B01D00B* has the discharge faculty that is shorted VOUT to VDD2, when RES pin=LOW.
As tH0=70(µs/V), ∆ tH=0.079(µs/V/nF) by measurement, tH is calculated as follows, when V 0=7V and CL=100pF.
tH=tH0×V0+∆ tH×CL×V0=70×7+0.079×100×7=545µs
2 In case of reset command
reset
command
VDD2
/VDD
Power
saver
Power OFF
tL
1.7V
SEG
VSS
COM
VSS
As power VDD, VDD2 is
shut off, it becomes
impossible to fix output
V0
V1
V2
V3
V4
VSS
At or under Vth on LCD.
Use 1.0[V] as a reference.
tH
Figure 23
VOUT is not shorted to VDD2 by reset command, so tH is longer than the case of RES pin=LOW.
As tH0=175(µs/V), ∆ tH=0.23(µs/V/nF) by measurement, tH is calculated as follows, when V 0=7V and CL=100pF.
tH=tH0×V0+∆ tH×CL×V0=175×7+0.23×100×7=1386µs
13–34
EPSON
Rev. 1.1a
S1D15B01 Series
(3) Refresh
It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of
unexpected noise.
Refresh sequence
Set all commands to ready state
Test mode reset command
(Display ON/OFF) *20
Refreshing DDRAM
Notes: Reference items
*20: 7.Command description; Display ON/OFF
Rev. 1.1a
EPSON
13–35
S1D15B01 Series
9. ABSOLUTE MAXIMUM RATING
Unless otherwise noted, VSS = 0V.
Table 15
Parameter
Power supply voltage (1)
Power supply voltage (2)
Symbol
VDD
VDD2
Conditions
–0.3 to 7.0
–0.3 to 7.0
–0.3 to 7.0
–0.3 to 6.0
–0.3 to 4.5
–0.3 to 3.6
Unit
V
V
V0, VOUT
V 1, V 2, V 3, V 4
VIN
VO
TOPR
TSTR
–0.3 to 18.0
–0.3 to V0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–40 to 85
–55 to 100
–55 to 125
V
V
V
V
°C
°C
Double boosting
Triple boosting
Quadruple boosting
Quintuple boosting
Power supply voltage (3)
Power supply voltage (4)
Input voltage
Output voltage
Operating temperature
Storage temperature
TCP
Bare chip
V0, VOUT
V1 to V4
VCC
VDD, VDD2
VSS
GND
System
VSS
S1D15B01 series
Notes and Conditions
1. Voltage V0 ≥ V 1 ≥ V2 ≥ V 3 ≥ V4 ≥ V SS must always be satisfied.
2. If the LSI exceeds its absolute maximum rating, it may be damage permanently. It is desirable to use it under electrical
characteristics conditions during general operation. Otherwise, a malfunction of the LSI may be caused and LSI
reliability may be affected.
13–36
EPSON
Rev. 1.1a
S1D15B01 Series
10. ELECTRICAL CHARACTERISTICS
DC Characteristics
Table 16
V SS=0V, VDD =3V±10%, Ta=–40 to 85°C unless otherwise noted.
Item
Power
Recommended
voltage(1) operation
Power
voltage(2)
Symbol
V DD
Condition
(Relative to VSS)
Min.
1.8
Typ.
–
Max.
3.6
Unit
V
V DD2
(Relative to VSS)
1.7
1.8
–
–
5.5
3.6
V
V
VDD2 *1
1.7
–
5.5
Booster circuit
operatinal
Double boosting
Triple boosting
3.0
2.0
–
–
5.5
5.0
voltage
Quadruple boosting
Quintuple boosting
(Relative to VSS)
1.7
1.7
6.0
–
–
–
4.0
3.0
16.0
V
VOUT
Operational
Recommended
operation
Operational
Voltage regulator
operational voltage
Voltage follower
V OUT
V0
4.5
–
16.0
operational voltage
V1, V2
V3, V4
VREG
V IH
0.6×V0
V SS
1.26
0.8×VDD
–
–
1.30
–
V0
0.4×V0
1.34
V DD
V
V SS
0.8×VDD
V SS
–1.0
–
–
–
–
0.2×VDD
V DD
0.2×VDD
–1.0
V
V
V
µA
–3.0
–
2.0
–3.0
5.0
µA
kΩ
–
0.01
5
µA
–
0.01
15
µA
20
35
pF
5.2
5.85
kHz
Reference voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
V IL
VOH
VOL
ILI
Output leakage current
LCD driver ON resistance
ILO
R ON
Static current
consumption
I DDQ
I0Q
Input terminal
capacitance
Oscillation frequency
CIN
fOSC
Ta=25°C
IOH=-0.5mA
IOL=0.5mA
V0=8V
Ta=25°C
Ta=25°C
V0=16V
Ta=25°C
f =1MHz
Ta=25°C
Ta=25°C
4.55
Pin used
VDD *1
V0 *2
V
V
V1,V2
V3,V4
*3
*4
*5
*6
*7
SEGn,
COMn *8
VDD ,
VDD2
V5
*9
Relationship between oscillation frequency f osc and frame rate frequency fFR : f FR = fosc/ 65
Relationship between external clock (CL) frequency fCL and frame rate frequency fFR : fFR =fCL/ 8/ 65
Rev. 1.1a
EPSON
13–37
S1D15B01 Series
Current consumption
Dynamic current consumption (1) : During display, when the internal power supply circuit is OFF
(external power supply is used).
Table 17
Display Pattern OFF
Item
Symbol
S1D15B01*****
I0(1)
Table 18
Condition
VDD=VDD2=2.7V, V0=8.0V
VDD=VDD2=2.7V, V0=11.0V
Display Pattern Checker
Item
Symbol
S1D15B01*****
I0(1)
Ta=25˚C
Min.
–
–
Typ.
20
29
Max.
33
48
Unit
µA
Notes
*10
Min.
–
–
Typ.
24
33
Max.
40
55
Unit
µA
Notes
*10
Unit
µA
Notes
*9
Unit
µA
Notes
*9
Unit
µA
Notes
*9
Ta=25˚C
Condition
VDD=VDD2=2.7V, V0=8.0V
VDD=VDD2=2.7V, V0=11.0V
Dynamic current consumption (2) : During display, when the internal power supply circuit is ON.
Table 19
Display Pattern OFF
Item
Symbol
S1D15B01***** IDD+ IDD2
(2)
Table 20
Table 21
Power saver
Item
Symbol
S1D15B01***** IDD(2)
13–38
Condition
VDD=VDD2=2.7V, V0=8.0V
Triple boosting
VDD=VDD2=2.7V, V0=8.0V
Quadruple boosting
VDD=VDD2=2.7V, V0=8.0V
Quadruple boosting
Display Pattern Checker
Item
Symbol
S1D15B01***** IDD+ IDD2
(2)
Ta=25˚C
Min.
–
Typ.
75
Max.
125
–
96
160
–
119
198
Min.
–
Typ.
86
Max.
143
–
110
183
–
136
227
Min.
–
Typ.
0.01
Max.
5
Ta=25˚C
Condition
VDD=VDD2=2.7V, V0=8.0V
Triple boosting
VDD=VDD2=2.7V, V0=8.0V
Quadruple boosting
VDD=VDD2=2.7V, V0=8.0V
Quadruple boosting
Ta=25˚C
Condition
VDD=VDD2=1.7V to 3.6V
EPSON
Rev. 1.1a
S1D15B01 Series
Reference data
Dynamic current consumption (1) : During display, when the internal power supply circuit is OFF
(external power supply is used).
Conditions : Internal power supply OFF. External supply in use.
V0 =8.0V, Display pattern : OFF, Ta=25˚C
50
IDD = IDD2 [µA]
40
30
V0 = 11.0V
20
V0 = 8.0V
10
0
0
1
2
3
4
5
VDD = VDD2 [V]
6
7
8
Figure 24
Conditions : Internal power supply OFF. External supply in use.
V0 =8.0V, Display pattern : Checker, Ta=25˚C
50
IDD = IDD2 [µA]
40
30
V0 = 11.0V
20
V0 = 8.0V
10
0
0
1
2
3
4
5
VDD = VDD2 [V]
6
7
8
Figure 25
Rev. 1.1a
EPSON
13–39
S1D15B01 Series
Dynamic current consumption (2) : During display, when the internal power supply circuit is ON.
Conditions : Internal power supply ON.
V0=8.0V, Display pattern : OFF, Ta=25˚C
140
×5
IDD + IDD2 [µA]
120
×4
100
×3
80
×2
60
40
20
0
0
1
2
3
4
5
6
VDD + VDD2 [V]
Figure 26
Conditions : Internal power supply ON.
V0 =8.0V, Display pattern : Checker, Ta=25˚C
160
×5
140
×4
IDD + IDD2 [µA]
120
×3
100
×2
80
60
40
20
0
0
1
2
3
4
5
6
VDD + VDD2 [V]
Figure 27
13–40
EPSON
Rev. 1.1a
S1D15B01 Series
Dynamic current consumption (3) : During access and display (Checker pattern is constantly written at fCYC and
displayed), when the on-chip power supply circuit is ON.
10
IDD [mA]
1
0.1
0.01
0.001
0.001
0.01
0.1
1
10
fCYC [MHz]
Figure 28
Rev. 1.1a
EPSON
13–41
S1D15B01 Series
VDD, VDD2 and V0 (VOUT) operation voltage range
(1) S1D15B01D00B *
1 VDD=VDD2
In the range of VDD=VDD2<3.2V, the maximum V0 voltage is determined by VOUT voltage of the quintuple boosting.
It is necessary to keep VOUT > V0 for preventing irregular display. The voltage of VOUT - V0 is determined by LCD
panel, so it is recommended to check the actual LCD module and set them.
20
16
V0 - VSS [V]
15
Operating range
10
8.5
4.5
5
1.7
3.2
5.5
0
0
1
2
3
4
VDD = VDD2 [V]
5
6
Figure 29
2 VDD<VDD2
In the case, it is necessary to keep 1.7V≤V DD≤VDD2≤3.6V. And the VDD2 should be set to keep VOUT>V0.
20
16
V0 - VSS [V]
15
11
10
Operating range
4.5
5
1.7
3.6
0
0
1
2
3
VDD [V]
4
5
6
Figure 30
13–42
EPSON
Rev. 1.1a
S1D15B01 Series
(2) S1D15B01D01B*
If VDD=VDD2, the operating range of VDD/VDD2 is 1.7V≤VDD=VDD2≤4.5V. And if VDD<VDD2, the operating range
of VDD/VDD2 is 1.7V≤VDD<VDD2≤3.6V
1 Eternal voltage : VOUT
In this case, the relationship between VOUT and V DD/VDD2 is required as shown in Figure 31.
20
VDD < VDD2
VDD = VDD2
16
VOUT - VSS [V]
15
Operating range
10
8
5
6
1.7
2.4
3.6
4.5
0
0
1
2
3
4
VDD / VDD2 [V]
5
6
Figure 31
2 Eternal voltage : V0
In this case, the relationship between V0 and VDD/VDD2 is required as shown in Figure 32.
20
VDD < VDD2
16
VDD = VDD2
V0 - VSS [V]
15
11
Operating range
10
4.5
5
1.7
3.6
2
3
4
VDD / VDD2 [V]
4.5
0
0
1
5
6
Figure 32
(3) S1D15B01D02B*
Eternal voltage: V0 , V1 to V4
In this case, V0 operating range is same as Figure 32, and V 0≥V1 ≥V2 ≥V3 ≥V4≥VSS is required.
Rev. 1.1a
EPSON
13–43
S1D15B01 Series
*1. Though the wide range of operating voltage is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage during being accessed from MPU.
This VDD, V DD2 operational voltage range (1.7V to 5.5V) is in case of VDD=VDD2. If VDD≠VDD2, it becomes to
be 1.7V≤VDD<VDD2≤3.6V.
*2. VDD, VDD2 and V0 operating voltage range is shown in Figure.
*3. VREG is internal constant voltage source for V0 voltage regulator circuit.
*4. D7 (SI), D6 (SCL), D5 to D0, A0, CS, RES, RD (E), WR (R/W),C86, P/S and CL pins
*5. D7 to D0 pins
*6. A0, CS, RES, RD (E), WE (R/W), C86, P/S and CL pins
*7. D7 (SI), D6 (SCL) and D5 to D0 pins
*8. Resistance value when 0.1V is applied between the output pin SEGn or COMn and each power supply pin (V0, V1 ,
V2, V3, V4, VSS). This is specified in the “Voltage follower operating voltage” range. RON = 0.1V/∆I (∆I : Current
flowing when 0.1V is applied between that output pin and those power supply pin).
*9. Current that each IC unit consumes. It does not include the current of the LCD panel capacity, wiring capacity, etc.
13–44
EPSON
Rev. 1.1a
S1D15B01 Series
Timing Characteristics
System Bus Read/Write Characteristics 1 (For the 8080-series MPU)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
*1
tCCLR, tCCLW
WR, RD
tCCHR, tCCHW
CS1
(CS2="1")
*2
tf
tr
WR, RD
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 33
[VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Table 22
Item
Address hold time
Address setup time
System cycle time
Control LOW pulse width(Write)
Control LOW pulse width(Read)
Control HIGH pulse width(Write)
Control HIGH pulse width(Read)
Data setup time
Data hold time
Access time
Output disable time
Rev. 1.1a
Signal
A0
WR
RD
WR
RD
D7 to D0
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
EPSON
Condition
CL=100pF
Min.
0
0
160
30
70
30
30
Max.
–
–
–
–
–
–
–
20
0
–
5
–
–
70
50
Units
ns
13–45
S1D15B01 Series
Table 23
Item
Address hold time
Address setup time
System cycle time
Control LOW pulse width(Write)
Control LOW pulse width(Read)
Control HIGH pulse width(Write)
Control HIGH pulse width(Read)
Data setup time
Data hold time
Access time
Output disable time
[VDD=2.7V to 4.5V, Ta=–40 to 85°C]
Signal
A0
WR
RD
WR
RD
D7 to D0
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tOH8
Table 24
Item
Address hold time
Address setup time
System cycle time
Control LOW pulse width(Write)
Control LOW pulse width(Read)
Control HIGH pulse width(Write)
Control HIGH pulse width(Read)
Data setup time
Data hold time
Access time
Output disable time
Condition
CL=100pF
Min.
0
0
260
60
120
60
60
Max.
–
–
–
–
–
–
–
35
0
–
10
–
–
120
100
Units
ns
[VDD=1.7V to 2.7V, Ta=–40 to 85°C]
Signal
A0
WR
RD
WR
RD
D7 to D0
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
Condition
tDS8
tDH8
tACC8
tOH8
CL=100pF
Min.
0
0
700
120
240
120
120
Max.
–
–
–
–
–
–
–
90
0
–
10
–
–
240
200
Units
ns
*1. This is in the case of making the access by WR and RD, setting the CS1=LOW.
*2. This is in the case of making the access by CS1, setting the WR, RD=LOW.
*3. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr+tf) <
= (tCYC8-tCCLW) or (tr+tf) <
= (tCYC8-tCCLR-tCCHR).
*4. All timings are specified based on the 20 and 80% of VDD.
*5. tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and WR,RD are at
the LOW level.
13–46
EPSON
Rev. 1.1a
S1D15B01 Series
System Bus Read/Write Characteristics 2 (For the 6800-series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
*1
tEWHR, tEWHW
tCYC6
E
tEWLR, tEWLWW
CS1
(CS2="1")
*2
tr
tf
E
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 34
Table 25
Item
Address hold time
Address setup time
System cycle time
Enable
HIGH pulse width
Enable
LOW pulse width
Data setup time
Data hold time
Access time
Output disable time
Rev. 1.1a
[VDD=4.5V to 5.5V, Ta=–40 to 85°C]
Signal
A0,
WR
Width
Read
Width
Read
E
E
D7 to D0
Symbol
tAH6
tAW6
tCYC6
tEWHW
tEWHR
tEWLW
tEWLR
tDS6
tDH6
tACC6
tOH6
EPSON
Condition
CL=100pF
Min.
0
0
160
30
70
30
30
20
0
–
5
Max.
–
–
–
–
–
–
–
–
–
70
50
Units
ns
13–47
S1D15B01 Series
Table 26
Item
Address hold time
Address setup time
System cycle time
Enable
HIGH pulse width
Enable
LOW pulse width
Data setup time
Data hold time
Access time
Output disable time
[VDD=2.7V to 4.5V, Ta=–40 to 85°C]
Signal
A0,
WR
Width
Read
Width
Read
E
D7 to D0
Symbol
tAH6
tAW6
tCYC6
tEWHW
tEWHR
tEWLW
tEWLR
tDS6
tDH6
tACC6
tOH6
Table 27
Item
Address hold time
Address setup time
System cycle time
Enable
HIGH pulse width
Enable
LOW pulse width
Data setup time
Data hold time
Access time
Output disable time
Condition
CL=100pF
Min.
0
0
260
60
120
60
60
35
0
–
10
Max.
–
–
–
–
–
–
–
–
–
120
100
Units
ns
[VDD=1.7V to 2.7V, Ta=–40 to 85°C]
Signal
A0,
WR
Width
Read
Width
Read
E
D7 to D0
Symbol
tAH6
tAW6
tCYC6
tEWHW
tEWHR
tEWLW
tEWLR
tDS6
tDH6
tACC6
tOH6
Condition
CL=100pF
Min.
0
0
700
120
240
120
120
90
0
–
10
Max.
–
–
–
–
–
–
–
–
–
240
200
Units
ns
*1. This is in the case of making the access by E, setting the CS1=LOW.
*2. This is in the case of making the access by CS1, setting the E=HIGH.
*3. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr+tf) <
= (tCYC6-tEWLW-tEWHW) or (tr+tf) <
= (t CYC6-tEWLR -tEWHR).
*4. All timings are specified based on the 20 and 80% of VDD.
*5. tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and E is at the HIGH
level.
13–48
EPSON
Rev. 1.1a
S1D15B01 Series
Serial interface
tCSS
CS
tCSH
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Figure 35
Table 28
Item
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS serial clock time
VDD=4.5 to 5.5V, Ta=–40 to 85°C
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
CS serial clock time
Rev. 1.1a
Min.
40
15
15
10
20
3
3
Max.
–
–
–
–
–
–
–
10
25
–
–
Units
ns
VDD=2.7 to 4.5V, Ta=–40 to 85°C
Table 29
Item
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
Condition
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
EPSON
Condition
Min.
70
25
25
20
40
5
5
Max.
–
–
–
–
–
–
–
15
50
–
–
Units
ns
13–49
S1D15B01 Series
Table 30
Item
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS serial clock time
VDD=1.7 to 2.7V, Ta=–40 to 85°C
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
Condition
tCSS
tCSH
Min.
150
50
50
45
90
10
10
Max.
–
–
–
–
–
–
–
50
100
–
–
Units
ns
Note : 1. The input Signal rise and fall times must be with in 10ns.
2. Every timing is specified on the basis of 20% and 80% of V DD.
13–50
EPSON
Rev. 1.1a
S1D15B01 Series
Reset timing
tRW
RES
tR
Internal circuit
state
During reset
Normal operation
Figure 36
Table 31
Parameter
Reset time
Reset LOW pulse width
Signal
Symbol
tR
RES
tRW
VDD=4.5 to 5.5V, Ta=–40 to 85°C
Condition
Min.
Max.
Units
–
250
ns
250
VDD=2.7 to 4.5V, Ta=–40 to 85°C
Table 32
Parameter
Reset time
Reset LOW pulse width
Signal
Symbol
tR
RES
tRW
Condition
Reset LOW pulse width
Min.
–
Max.
500
500
–
Units
ns
VDD=1.7 to 2.7V, Ta=–40 to 85°C
Table 33
Parameter
Reset time
–
Signal
Symbol
tR
RES
tRW
Condition
Min.
–
Max.
1000
1000
–
Units
ns
Note : 1. The input Signal rise and fall times must be with in 10ns.
2. Every timing is specified on the basis of 20% and 80% of VDD.
Rev. 1.1a
EPSON
13–51
S1D15B01 Series
Notes for Power on Sequence
It is preferable to turn on power supply VDD and VDD2
at the same time, but if VDD turn on after VDD2, then it
is necessary that the below 3 conditions are satisfied.
VDD2
VDD
t1
CS
t2
RES
Figure 37
A. t1 < 1ms, during this timing, all input pins are fixed to VSS.
B. CS becomes HIGH simultaneously with VDD.
C. t2 > 100ns (Reset is canceled after VDD2 and rise up).
13–52
EPSON
Rev. 1.1a
S1D15B01 Series
11. THE MPU INTERFACE (REFERENCE EXAMPLES)
The S1D15B01 series can directly be connected to the 80 system MPU and 68 series MPU. It can also be operated with
a fewer signal lines by using the serial interface.
After the initialization using the RES pin, the respective input pins of the S1D15B01 series need to controlled normally.
(1) 80 series MPU
VDD
VDD
A0
MPU
A1 to A7
IORQ
CS
Decoder
D0 to D7
D0 to D7
RD
WR
RES
VSS
RD
WR
RES
GND
C86
A0
S1D15B01 Series
VCC
P/S
RESET
VSS
Figure 38
(2) 6800 series MPU
VDD
VDD
A0
A1 to A15
VMA
GND
C86
A0
CS
Decoder
D0 to D7
D0 to D7
E
R/W
RES
VSS
E
R/W
RES
S1D15B01 Series
MPU
VCC
P/S
RESET
VSS
Figure 39
(3) Using serial interface
VDD
VDD
A0
Decoder
CS
MPU
A1 to A7
C86
A0
S1D15B01 Series
VCC
SI
SCL
RES
Port1
Port2
GND
RES
VDD or VSS
P/S
VSS
RESET
VSS
Figure 40
Rev. 1.1a
EPSON
13–53
S1D15B01 Series
12. CAUTION
Please be advised on the following points in the use of
this development specification.
1. This development specification is subject to change
without previous notice.
2. This development specification does not guarantee or
furnish the industrial property right not its execution.
Application examples in this development
specification are intended to ensure your better
understanding of the product. Thus the manufacturer
shall not be liable for any trouble arising in your
circuits from using such application example.
Numerical values provided in the property table of
this manual are represented with their magnitude on
the numerical line.
3. No part of this development specification may not be
reproduced, copied or used for commercialpurpose
without a written permission from the manufacturer.
In handling of semiconductor devices, your attention is
required to following points.
13–54
[Precaution on light]
Property of semiconductor devices may be affected
when they are exposed to light, possibly resulting in
malfunctioning of the ICs. To prevent such
malfunctioning of the ICs mounted on the boards or
products, make sure that:
(1) Your design and mounting layout done are so that
the IC is not exposed to light in actual use.
(2) The IC is protected from light in the inspection
process.
(3) The IC is protected from light in its front, rear and
side faces.
[Precautions when installing the COG]
When installing the COG, it is necessary to duly
consider the fact that there exists a resistance of the
ITO wiring occurring between the driver chip and the
externally connected parts (such as capacitors and
resistors). By the influence of this resistance, nonconformity may occur with the indications on the
liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the
driver chip pin to the externally connected parts
as much as possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
EPSON
Rev. 1.1a
International Sales Operations
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ASIA
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HEADQUARTERS
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80992 Munich, GERMANY
Phone : +49- (0) 89-14005-0
SEIKO EPSON CORPORATION
KOREA OFFICE
Fax : +49- (0) 89-14005-110
SALES OFFICE
Altstadtstrasse 176
51379 Leverkusen, GERMANY
Phone : +49- (0) 2171-5045-0 Fax : +49- (0) 2171-5045-10
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone : 02-784-6027
Fax : 02-767-3677
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
UK BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
Phone : +44- (0) 1344-381700 Fax : +44- (0) 1344-381701
FRENCH BRANCH OFFICE
1 Avenue de l’ Atlantique, LP 915 Les Conquerants
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
Phone : +33- (0) 1-64862350 Fax : +33- (0) 1-64862355
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Prima Sant Cugat
Avda. Alcalde Barrils num. 64-68
` SPAIN
E-08190 Sant Cugat del Valles,
Phone : +34-93-544-2490
Fax: +34-93-544-2491
Electronic Device Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5816
Fax: +81-(0)42-587-5624
ED International Marketing Department
Europe & U.S.A.
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5812
Fax: +81-(0)42-587-5564
ED International Marketing Department
Asia
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814
Fax: +81-(0)42-587-5110
In pursuit of “Saving” Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
NOTICE
No parts of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this
material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover,
no license to any intellectual property rights is granted by implication or otherwise, and there is no
representation or warranty that anything made in accordance with this material will be free from any patent
or copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of
Japan and may require an export licence from teh Ministry of International Trade and Industry or other
approval from another government agency.
© Seiko Epson corporation 2001, All rights reserved.
i8088 and i8086 are registered trademarks of Intel Corporation.
Z80 is registered trademark of Zilog Corporation.
V20 and V30 are registered trademarks of Nippon Electric Corporation.
4.5mm
MF424-21
S1D15000 Series
Technical Manual
IEEE1394
LCD
driverController
with RAM
S1R75801F00A
S1D15000
Series
Technical Manual
S1D15000 Series Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
This manual was made with recycle paper,
and printed using soy-based inks.
First issue December,1992 U
Printed May,2001 in Japan H B
4.5mm

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