SLB-Technical-Specifications

SLB-Technical-Specifications
Sundance Multiprocessor Technology Limited
Design Specification
Unit / Module Name:
Form : QCF51
Dated : 20 June 2003
Revision : 6
Sundance Local Bus (SLB)
Unit / Module Number:
Used On:
Various TIMs
Document Issue:
8
Date:
21/08/2007
CONFIDENTIAL
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This documents is the property of Sundance and may not be copied nor
communicated to a third party without the written permission of
Sundance. © Sundance Multiprocessor Technology Limited 2003
Specification Reference SLB
Page 1 of 20
21/08/2007
Revision History
Issue
Changes Made
Date
Initials
1
Original Document completed.
30/04/04
PSR
2
Probe connector references and photos added
07/05/04
PSR
3
Mistakes corrected
10/05/04
PSR
4
JTAG lines missing on Power Connector.
19/05/04
PSR
5
Trigger, FPGASysClock and RSLClock signals added
to Bank A and Bank C.
17/02/05
PSR
6
Removed requirement for 1.5V supply to mounting
hole.
03/03/05
GKP
7
Added alternative pin-out for power.
01/08/05
GKP
8
Generic Local Bus spec produced.
21/08/07
GKP
Specification Reference SLB
Page 2 of 20
21/08/2007
Table of Contents
1
2
Introduction ................................................................................................................................... 5
1.1
Overview ................................................................................................................................. 5
1.2
SLB Features ........................................................................................................................... 5
1.3
Related Documents.................................................................................................................. 6
Mechanical Specifications............................................................................................................. 7
2.1
Type of connector – Data and control signals ......................................................................... 7
2.2
Type of connector – Power Supplies....................................................................................... 8
2.3
Mounting Hole Location ......................................................................................................... 9
2.3.1
Main or Base Module ...................................................................................................... 9
2.3.2
Daughter Module........................................................................................................... 10
2.3.3
Mounting Holes Notes................................................................................................... 12
3
Electrical Specifications and Pin Assignment ........................................................................... 13
3.1
Data and Control connectors (QSH and QTH)...................................................................... 13
3.2
Trace Routing Requirements................................................................................................. 13
3.2.1
Data Routing.................................................................................................................. 13
3.2.2
Control Routing............................................................................................................. 13
4
3.3
Connector (Bank A - data) Pin-out........................................................................................ 14
3.4
Connector (Bank B - control) Pin-out ................................................................................... 15
3.5
Connector (Bank C - data) Pin-out........................................................................................ 17
3.6
Power Supplies Connectors (BKS and BKT)........................................................................ 18
Probe Connector.......................................................................................................................... 20
4.1
High Density Ribbon Cable .................................................................................................. 20
4.2
PCB for probing purpose – SMT598..................................................................................... 20
Specification Reference SLB
Page 3 of 20
21/08/2007
Table of Figures
Figure 1 - QTH-060-01-F-D-DP-A (Top View)..........................................................................7
Figure 2 - QSH-060-01-F-D-DP-A (Top View) .........................................................................7
Figure 3 - BKS-133-01-F-V-A – Top View................................................................................8
Figure 4 - BKT-133-03-F-V-A – Top View. ...............................................................................8
Figure 5 - Main/Base Module - Top View – Mounting Hole Location .......................................9
Figure 8 - Daughter Module - Top View - location of QSH and BKT connectors ...................10
Figure 9 - Daughter Module - Top View – location of large mounting holes ..........................11
Figure 10 - Daughter Module - Top View - location of small mounting holes .........................12
Figure 12 - High Density Ribbon cable...................................................................................20
Figure 13 - SMT598. ..............................................................................................................20
Tables of Tables
Table 1 QSH/QTH Characteristics.
13
Table 2 Pin Assignment - Data/Control Connector - Bank A.
14
Table 3 Pin Assignment - Data/Control Connector - Bank B.
15
Table 4 Optional SLB power pins
16
Table 5 Pin Assignment - Data/Control Connector - Bank C.
17
Table 6 Pin Assignment - Power Supplies Connector.
19
Specification Reference SLB
Page 4 of 20
21/08/2007
1 Introduction
1.1
Overview
Every DSP or FPGA application has varying input and output requirements. These can be
simple USB interfaces, CameraLink, or high-speed analog I/O. Utilising a standard base
module, a flexible system can be tailored by attaching a wide variety of daughter modules.
For this reason, the SLB mezzanine concept was introduced.
This concept consists of a carrier board (often a DSP or FPGA TIM module) which includes a
high density connector. This connector accepts a daughter module (or mezzanine) which is
mounted above the carrier (or in some case can be mounted separately and joined using a
flexible cable).
The SLB connector is of a differential construction (based on a Samtec QSH/QTH-DP series
0.5mm pitch connectors) and characterised for high-speed data of over 1Gb/s per pin pair.
The connector is split into three sections, 2 for high-speed differential (LVDS) data transfer,
and one for control. A separate connector provides power to the mezzanine board.
This document describes how the SLB works and specifies mechanical and electrical
characteristics.
1.2
SLB Features
Below are listed the features of the SLB:
-
Low Voltage Differential Signalling (LVDS), supported by Xilinx FPGAs,
-
One control signal port,
-
Two differential data ports,
-
A set of power supplies: +3.3, +5, +12 and –12 Volts.
-
Two-extra mounting holes to hold Main/Base and Daughter modules together.
Specification Reference SLB
Page 5 of 20
21/08/2007
1.3
Related Documents
Samtec – QTH Specifications:
http://www.samtec.com/signal_integrity/technical_specifications/overview.asp?series=QTHDP&menu=Signal_Integrity
Samtec – QSH Specifications:
http://www.samtec.com/signal_integrity/technical_specifications/overview.asp?series=QSHDP
Samtec – BKS Specifications:
http://www.samtec.com/signal_integrity/technicalhttp://www.samtec.com/technical_specificati
ons/overview.asp?series=BKS
Samtec – BKT Specifications:
http://www.samtec.com/technical_specifications/overview.asp?series=BKT
Sundance – SMT598:
http://lux/sundance/edge/files/productpage.asp?STRFilter=SMT598
Samtec HQDP cable series:
http://www.samtec.com/technical_specifications/overview.asp?series=HQDP
Precision Interconnect:
http://www.precisionint.com/
Specification Reference SLB
Page 6 of 20
21/08/2007
2 Mechanical Specifications
2.1
Type of connector – Data and control signals
The SLB data/control connectors used to stack up modules, are manufactured by Samtec.
They are 5mm-stack height, 0.5-mm pitch and specially made to carry differential pair
signals. Both connectors on Main/Base and Daughter modules have 120 pins. The Samtec
part numbers are as follow:
-
QTH-060-01-F-D-DP-A for the base module.
Bank A
Bank B
13 57
Bank C
41 43
81 83
24 68
Figure 1 - QTH-060-01-F-D-DP-A (Top View)
-
QSH-060-01-F-D-DP-A for the daughter module.
Bank A
Bank B
24 68
42 44
Bank C
82 84
13 57
Figure 2 - QSH-060-01-F-D-DP-A (Top View)
Each of the two connectors shows 60 differential pairs, split into three Banks A, B and C.
Banks A and C are ideally suited for data and Bank B for control signals. In addition to the
shielding provided by the differentials pairs, connections to ground are added along the
centre-line of the connectors.
Specification Reference SLB
Page 7 of 20
21/08/2007
2.2
Type of connector – Power Supplies
The SLB power supplies connectors used to stack up modules, are manufactured by
Samtec. They are 5mm-stack height, 1-mm pitch and specially made to carry high currents.
Both connectors on Main/Base and Daughter modules have 23 pins. The Samtec part
numbers are as follow:
-
BKS-133-01-F-V-A for the base module and
Figure 3 - BKS-133-01-F-V-A – Top View.
-
BKT-133-03-F-V-A for the daughter module.
Figure 4 - BKT-133-03-F-V-A – Top View.
Specification Reference SLB
Page 8 of 20
21/08/2007
2.3
Mounting Hole Location
Note that Sundance can provide a gerber file of an existing board in order to check the right
location of the connectors. It is an easy and quick test to make sure of the right location of
the connectors and mounting holes.
To see an example of how both modules are interconnected, please go to Sundance’s
website,
http://www.sundance.com/web/files/picture.asp?STRFilter=SMT390&type=side&unsupported
=&page_type=more_pics.
2.3.1
Main or Base Module
Figure 5 - Main/Base Module - Top View – Mounting Hole Location
Specification Reference SLB
Page 9 of 20
21/08/2007
2.3.2
Daughter Module
Figure 6 - Daughter Module - Top View - location of QSH and BKT connectors
Specification Reference SLB
Page 10 of 20
21/08/2007
Figure 7 - Daughter Module - Top View – location of large mounting holes
Specification Reference SLB
Page 11 of 20
21/08/2007
Figure 8 - Daughter Module - Top View - location of small mounting holes
2.3.3
Mounting Holes Notes
As you can see on the previous figures, modules don’t only have the usual pair of 3.3 Volt
mounting holes but they also have two smaller (in diameter) ones. They have been added to
maintain both modules tight together and to provide the daughter module with a 2.5 Volt
supply.
Location and dimensions of these extra mounting holes are shown on the above figures.
If none of the extra mounting holes are used, make sure that they are left unconnected as
they are plated through.
Specification Reference SLB
Page 12 of 20
21/08/2007
3 Electrical Specifications and Pin Assignment
3.1
Data and Control connectors (QSH and QTH)
The following table gathers the characteristics of both connectors provided by Samtec:
Table 1 QSH/QTH Characteristics.
Maximum impedance
Mismatch and Crosstalk
System Bandwidth
Signal Rise Time
5%
Up to 700MHz
No faster than 500ps.
10%
Up to 1.33GHz
No faster than 263ps
Data Valid up to
12GHz
30ps
3.2
3.2.1
Trace Routing Requirements
Data Routing
For the high-speed data ports (banks A and C), the signals should be routed differentially
and with each pair having closely matched lengths.
Separation of the LVDS pairs should be sufficient to reduce crosstalk.
Ideally, the differential impedance should be 100 Ohms, and the lengths matched to within
0.1”.
Sundance can assist with impedance calculations for custom carriers or mezzanines if
required.
De-skewing of data can be performed in some LVDS receiving devices (e.g. Xilinx Virtex 5
FPGAs), and therefore the length requirement can be less constraining.
3.2.2
Control Routing
The control signals (bank B) have a more relaxed routing requirement. These are typically
LVTTL (3.3V) signals that do not have any high-speed data present.
Specification Reference SLB
Page 13 of 20
21/08/2007
3.3
Connector (Bank A - data) Pin-out
This bank includes two 8-bit differential buses, a single differential clock (output ready) and
an out-of-range signal.
Typically, the ClkOI pair will be connected to an FPGA clock capable input (contact
Sundance for full details on existing SLB carriers and modules). The FPGASysClk pair can
be used to transfer a clock from the carrier to the mezzanine.
Table 2 Pin Assignment - Data/Control Connector - Bank A.
Pin No
Pin Name
Signal Description
Pin No
Pin Name
Dir
Bi-directional
1
DOAI0p
3
DOAI0n
Dir
Bi-directional
5
DOAI1p
Data Out 1, Channel A (pos).
7
DOAI1n
Data Out 1, Channel A (neg).
Dir
Bi-directional
9
DOAI2p
11
DOAI2n
Dir
Bi-directional
13
DOAI3p
15
DOAI3n
Dir
Bi-directional
17
DOAI4p
19
DOAI4n
Dir
Bi-directional
21
DOAI5p
23
DOAI5n
Dir
Bi-directional
25
DOAI6p
27
DOAI6n
Dir
Bi-directional
29
DOAI7p
31
DOAI7n
Dir
Signal Description
Dir
Bi-directional
Data Out 0, Channel A (pos).
2
DOBI0p
Data Out 8, Channel A (pos).
Data Out 0, Channel A (neg).
4
DOBI0n
Data Out 8, Channel A (neg).
Dir
Bi-directional
6
DOBI1p
Data Out 9, Channel A (pos).
Data Out 9, Channel A (neg).
8
DOBI1n
Dir
Bi-directional
Data Out 2, Channel A (pos).
10
DOBI2p
Data Out 10, Channel A (pos).
Data Out 2, Channel A (neg).
12
DOBI2n
Data Out 10, Channel A (neg).
Dir
Bi-directional
Data Out 3, Channel A (pos).
14
DOBI3p
Data Out 11, Channel A (pos).
Data Out 3, Channel A (neg).
16
DOBI3n
Data Out 11, Channel A (neg).
Dir
Bi-directional
Data Out 4, Channel A (pos).
18
DOBI4p
Data Out 12, Channel A (pos).
Data Out 4, Channel A (neg).
20
DOBI4n
Data Out 12, Channel A (neg).
Dir
Bi-directional
Data Out 5, Channel A (pos).
22
DOBI5p
Data Out 13, Channel A (pos).
Data Out 5, Channel A (neg).
24
DOBI5n
Data Out 13, Channel A (neg).
Dir
Bi-directional
Data Out 6, Channel A (pos).
26
DOBI6p
Data Out 14, Channel A (pos).
Data Out 6, Channel A (neg).
28
DOBI6n
Data Out 14, Channel A (neg).
Dir
Bi-directional
Data Out 7, Channel A (pos).
30
DOBI7p
Data Out 15, Channel A (pos).
Data Out 7, Channel A (neg).
32
DOBI7n
Data Out 15, Channel A (neg).
Daughter Card to Main Module
Dir
Daughter Card to Main Module
33
ClkOIp
Output Ready, Channel A (pos).
34
DOIRIp
Out of Range, Channel A (pos).
35
ClkOIn
Output Ready, Channel A
(neg).
36
DOIRIn
Out of Range, Channel A (neg).
Dir
Main Module to Daughter Card.
Dir
Daughter Card to Main Module.
37
FPGASysClkp
Clock Generated on Daughter
module to FPGA (pos)
38
ExtTriggerI0
External Trigger from Daughter
Module to FPGA (pos).
39
FPGASysClkn
Clock Generated on Daughter
module to FPGA (neg)
40
ExtTriggerI1
External Trigger from Daughter
Module to FPGA (neg).
Specification Reference SLB
Page 14 of 20
21/08/2007
3.4
Connector (Bank B - control) Pin-out
Bank B is dedicated for control signals. It includes an SMB interface, a serial number data
line, control lines, power supply enable signals, mode lines, dedicated signals and control
signals such as JTAG lines.
Table 3 Pin Assignment - Data/Control Connector - Bank B.
Pin No
Pin Name
Type
Signal Description
Pin No
Pin Name
Signal Description
System Signals
Type
System Signals
Dir
Daughter Card to Main Module
Dir
Daughter Card to Main Module
41
SMBClk
SMB Interface – Clock.
42
SMBData
SMB Interface – Data.
43
SMBnAlert
SMB Interface – Alerts Line
44
SerialNo
Serial Number Data Line.
Dir
Bi-directional
Dir
Bi-directional
45
Cntrl0
Control Line 0
46
Cntrl2
Control Line 2
47
Cntrl1
Control Line 1
48
Cntrl3
Control Line 3
Dir
Main Module to Daughter Card
Dir
Main Module to Daughter Card
49
PSEnable0
Power Supply 0 Enable
50
PSEnable1
Power Supply 1 Enable
51
Mode0
Mode Line 0.
52
Mode1
Mode Line 1
Type
Specific Signals
Type
Specific Signals
Dir
Bi-directional
Dir
Bi-directional
53
Signal0
Signal 0
54
Signal6
Signal 6
55
Signal1
Signal 1
56
Signal7
Signal 7
Dir
Bi-directional
Dir
Bi-directional
57
Signal2
Signal 2
58
Signal8
Signal 8
59
Signal3
Signal 3
60
Signal9
Signal 9
Dir
Bi-directional
Dir
Bi-directional
61
Signal4
Signal 4
62
Signal10
Signal 10
63
Signal5
Signal 5
64
Signal11
Signal 11
Type
Control Signals
Type
Control Signals
Dir
Bi-directional
Dir
Bi-directional
65
Cntrl4
Control Line 4
66
Cntrl7
Control Line 7
67
Cntrl5
Control Line 5
68
Cntrl8
Control Line 8
Dir
Bi-directional
Dir
Reserved
69
Cntrl6
Control Line 6
70
FpgaVRef
JTAG FPGA Vref.
71
FpgaTck
JTAG FPGA tck.
72
FpgaTms
JTAG FPGA tms.
Dir
Reserved
Dir
Reserved
73
FpgaTdi
JTAG FPGA tdi.
74
FpgaTdo
JTAG FPGA tdo.
75
MspVRef
JTAG MSP430 Vref
76
MspTck
JTAG MSP430 tck.
Dir
Reserved
Dir
Reserved
77
MspTms
JTAG MSP430 tms.
78
MspTdi
JTAG MSP430 tdi.
79
Msptdo
JTAG MSP430 tdo.
80
MspnTrst
JTAG MSP430 reset
Specification Reference SLB
Page 15 of 20
21/08/2007
Table 4 Optional SLB power pins
75
V33
+3.3V
76
V12
+12V
77
V33
+3.3V
78
V12
+12V
79
V33
+3.3V
80
V12
+12V
The MSP430 JTAG signals are only required to be connected to the SLB module if the MSP
micro-controller (fitted on some TIM base modules) needs to be re-programmed or debugged
with the SLB mezzanine present. Typically this is only used in such a manner during
Sundance test and debug. These signals are not required for normal operation.
Some SLB carriers will provide power supplies to these pins. Please check with the
respective user manuals.
Specification Reference SLB
Page 16 of 20
21/08/2007
3.5
Connector (Bank C - data) Pin-out
This bank includes two 8-bit differential buses, a single differential clock (output ready) and
an out-of-range signal.
Typically, the ClkOI pair will be connected to an FPGA clock capable input (contact
Sundance for full details on existing SLB carriers and modules). The FPGARslClk pair can
be used to transfer a clock from the carrier to the mezzanine.
Table 5 Pin Assignment - Data/Control Connector - Bank C.
Pin No
Pin Name
Signal Description
Pin No
Pin Name
Dir
Bi-directional
81
DOAQ0p
83
DOAQ0n
Dir
Bi-directional
85
DOAQ1p
Data Out 1, Channel B (pos).
87
DOAQ1n
Data Out 1, Channel B (neg).
Dir
Bi-directional
89
DOAQ2p
91
DOAQ2n
Dir
Bi-directional
93
DOAQ3p
95
DOAQ3n
Dir
Bi-directional
97
DOAQ4p
99
DOAQ4n
Dir
Bi-directional
101
DOAQ5p
103
DOAQ5n
Dir
Bi-directional
105
DOAQ6p
107
DOAQ6n
Dir
Bi-directional
109
DOAQ7p
111
DOAQ7n
Dir
Signal Description
Dir
Bi-directional
Data Out 0, Channel B (pos).
82
DOBQ0p
Data Out 8, Channel B (pos).
Data Out 0, Channel B (neg).
84
DOBQ0n
Data Out 8, Channel B (neg).
Dir
Bi-directional
86
DOBQ1p
Data Out 9, Channel B (pos).
Data Out 9, Channel B (neg).
88
DOBQ1n
Dir
Bi-directional
Data Out 2, Channel B (pos).
90
DOBQ2p
Data Out 10, Channel B (pos).
Data Out 2, Channel B (neg).
92
DOBQ2n
Data Out 10, Channel B (neg).
Dir
Bi-directional
Data Out 3, Channel B (pos).
94
DOBQ3p
Data Out 11, Channel B (pos).
Data Out 3, Channel B (neg).
96
DOBQ3n
Data Out 11, Channel B (neg).
Dir
Bi-directional
Data Out 4, Channel B (pos).
98
DOBQ4p
Data Out 12, Channel B (pos).
Data Out 4, Channel B (neg).
100
DOBQ4n
Data Out 12, Channel B (neg).
Dir
Bi-directional
Data Out 5, Channel B (pos).
102
DOBQ5p
Data Out 13, Channel B (pos).
Data Out 5, Channel B (neg).
104
DOBQ5n
Data Out 13, Channel B (neg).
Dir
Bi-directional
Data Out 6, Channel B (pos).
106
DOBQ6p
Data Out 14, Channel B (pos).
Data Out 6, Channel B (neg).
108
DOBQ6n
Data Out 14, Channel B (neg).
Dir
Bi-directional
Data Out 7, Channel B (pos).
110
DOBQ7p
Data Out 15, Channel B (pos).
Data Out 7, Channel B (neg).
112
DOBQ7n
Data Out 15, Channel B (neg).
Daughter Card to Main Module
Dir
Daughter Card to Main Module
113
ClkOQp
Output Ready, Channel B
(pos).
114
DOIRQp
Out of Range, Channel B (pos).
115
ClkOQn
Output Ready, Channel B
(neg).
116
DOIRQn
Out of Range, Channel B (neg).
Dir
Main Module to Daughter Card.
Dir
Daughter Card to Main Module.
117
FPGARslClkp
Clock Generated on Mezzanine
module to FPGA (pos)
118
ExtTriggerQ0
External Trigger from Daughter
Module to FPGA (pos).
119
FPGARslClkn
Clock Generated on Mezzanine
module to FPGA (neg)
120
ExtTriggerQ1
External Trigger from Daughter
Module to FPGA (neg).
Specification Reference SLB
Page 17 of 20
21/08/2007
3.6
Power Supplies Connectors (BKS and BKT)
Each pin on the power connector (33 pins in total) can carry 1.5A. Digital 5V (D+5V0), digital
3V3 (D+3V3) and digital ground (DGND) is provided over this connector. D+3V3 and D+5V0
are assigned four pins each. The daughter card can thus draw a total of 6A from each of
these two supplies. The integral ground plane on the differential connector provides
additional grounding.
Some JTAG lines are also mapped onto this connector to be used in case the daughter
module has a TI Processor. They would allow debugging and programming via JTAG. If not,
leave them all unconnected.
The following table (next page) shows the pin assignment on the power connector:
Specification Reference SLB
Page 18 of 20
21/08/2007
Table 6 Pin Assignment - Power Supplies Connector.
Pin Number
Pin Name
Description of Signal
1
D+3V3
Digital 3.3 Volts
2
DGND
Digital Ground
3
D+3V3
Digital 3.3 Volts
4
DGND
Digital Ground
5
D+3V3
Digital 3.3 Volts
6
DGND
Digital Ground
7
D+3V3
Digital 3.3 Volts
8
DGND
Digital Ground
9
D+5V0
Digital 5.0 Volts
10
DGND
Digital Ground
11
D+5V0
Digital 5.0 Volts
12
DGND
Digital Ground
13
D+5V0
Digital 5.0 Volts
14
DGND
Digital Ground
15
D+5V0
Digital 5.0 Volts
16
DGND
Digital Ground
17
D+12V0
Digital +12.0 Volts – not used on the SMT390
18
DGND
Digital Ground
19
D+12V0
Digital +12.0 Volts – not used on the SMT390
20
DGND
Digital Ground
21
D-12V0
Digital –12.0 Volts – not used on the SMT390
22
DGND
Digital Ground
23
D-12V0
Digital –12.0 Volts – not used on the SM390
24
DGND
Digital Ground
25
DGND
Digital Ground
26
EMU0
Emulation Control 0
27
EMU1
Emulation Control 1
28
TMS
JTAG Mode Control
29
nTRST
JTAG Reset
30
TCK
JTAG Test Clock
31
TDI
JTAG Test Input
32
TDO
JTAG Test Output
33
DGND
Digital Ground
Specification Reference SLB
Page 19 of 20
21/08/2007
4 Probe Connector
In order to debug a specific system or to connect it to an external module, it might be useful
to have access to signals carried by the QTH connector on the base module.
4.1
High Density Ribbon Cable
Figure 9 - High Density Ribbon cable.
Such cables are produced by Samtec (HQDP Series) or Precision Interconnect. Their
websites allow user to build specific cables and order them.
4.2
PCB for probing purpose – SMT598
Figure 10 - SMT598.
Sundance produces the SMT598 that allow probing clock, data and over-range differential
lines from Banks A and Bank C.
Specification Reference SLB
Page 20 of 20
21/08/2007
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement