datasheet for VL470T5663B

datasheet for VL470T5663B
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
General Information
2GB 256Mx64 DDR2 SDRAM NON-ECC UNBUFFERED SODIMM 200-PIN
Description:
The VL470T5663B is a 256Mx64 DDR2 SDRAM high density SODIMM. This memory module consists of
sixteen CMOS 128Mx8 bit with 8 banks DDR2 Synchronous DRAMs in BGA packages and a 2K EEPROM in
an 8-pin TSSOP package. This module is a 200-pin small-outline dual in-line memory module and is intended
for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each
DDR2 SDRAM.
Features:
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Pin Name
Function
A0~A13
Address Inputs
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS7
Data Strobes
DQS0#~DQS7#
Data Strobes Complement
ODT0,ODT1
On-die Termination Control
CK0,CK0#,CK1,CK1#
Clock Input
CKE0,CKE1
Clock Enables
CS0#,CS1#
Chip Selects
RAS#
Row Address Strobes
C AS#
Column Address Strobes
WE#
Write Enable
VD D
Voltage Supply 1.8V +/- 0.1V
VSS
Ground
SA0~SA1
SPD Address
DRAM DIE (option)
SD A
SPD Data Input/Output
DRAM MANUFACTURER
S - SAMSUNG
SC L
SPD Clock Input
DM0~DM7
Data Masks
A10/AP
Address Input/Autoprecharge
VREF
SSTL_18 Reference Voltage
VD D SPD
SPD Voltage Supply 1.7V to
3.6V
NC
No Connect
200-pin, small-outline dual in-line memory module (SODIMM)
Fast data transfer rates: PC2-6400 & PC2-5300
VDD = VDDQ = 1.8V
VDDSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18 compatible)
Differential data strobe (DQS, DQS# ) option
Four-bit prefetch architecture
DLL aligns DQ and DQS transition with CK
Programmable CAS# Latency (CL): 6 (DDR2-800), 5 (DDR2-667)
Programmable burst; length (4, 8)
On-die termination (ODT)
Auto & Self refresh, (8K/64ms refresh)
Serial presence detect (SPD) with EEPROM
Gold edge PCB contacts
Lead-free, RoHS compliant
PCB: Height 30mm (1.181”), double sided components
Order Information:
VL470T5663B-E7 S X
MODULE SPEED
E7: PC2-6400 @ CL6
E6: PC2-5300 @ CL5
VL : Lead-free/RoHS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 1 OF 10
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
Pin Configuration
200-PIN DDR2 SODIMM FRONT
200-PIN DDR2 SODIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
51
DQS2
101
A1
151
DQ42
2
VSS
52
DM2
102
A0
152
DQ46
3
VSS
53
VSS
103
VD D
153
DQ43
4
DQ4
54
VSS
104
VD D
154
DQ47
5
DQ0
55
DQ18
105
A10/AP
155
VSS
6
DQ5
56
DQ22
106
BA1
156
VSS
7
DQ1
57
DQ19
107
BA0
157
DQ48
8
VSS
58
DQ23
108
RAS#
15 8
DQ52
9
VSS
59
VSS
109
WE#
159
DQ49
10
DM0
60
VSS
110
C S 0#
160
DQ53
11
DQS0#
61
DQ24
111
VD D
161
VSS
12
VSS
62
DQ28
112
VD D
162
VSS
13
DQS0
63
DQ25
113
C AS#
163
NC
14
DQ6
64
DQ29
114
OTD0
164
C K1
15
VSS
65
VSS
115
C S 1#
165
VSS
16
DQ7
66
VSS
116
A 13
166
C K 1#
17
DQ2
67
DM3
117
VD D
167
DQS6#
18
VSS
68
DQS3#
118
VD D
168
VSS
19
DQ3
69
NC
119
ODT1
169
DQS6
20
DQ12
70
DQS3
120
NC
170
DM6
21
VSS
71
VSS
121
VSS
171
VSS
22
DQ13
72
VSS
122
VSS
172
VSS
23
DQ8
73
DQ26
123
DQ32
173
DQ50
24
VSS
74
DQ30
124
DQ36
174
DQ54
25
DQ9
75
DQ27
125
DQ33
175
DQ51
26
DM1
76
DQ31
126
DQ37
176
DQ55
27
VSS
77
VSS
127
VSS
177
VSS
28
VSS
78
VSS
128
VSS
178
VSS
29
DQS1#
79
C KE0
129
DQS4#
179
DQ56
30
C K0
80
C KE1
130
DM4
180
DQ60
31
DQS1
81
VD D
131
DQS4
181
DQ57
32
C K 0#
82
VD D
132
VSS
182
DQ61
33
VSS
83
NC
133
VSS
183
VSS
34
VSS
84
NC
134
DQ38
184
VSS
35
DQ10
85
BA2
135
DQ34
185
DM7
36
DQ14
86
NC
136
DQ39
186
DQS7#
37
DQ11
87
VD D
137
DQ35
187
VSS
38
DQ15
88
VD D
138
VSS
188
DQS7
39
VSS
89
A 12
139
VSS
189
DQ58
40
VSS
90
A11
140
DQ44
190
VSS
41
VSS
91
A9
141
DQ40
191
DQ59
42
VSS
92
A7
142
DQ45
192
DQ62
43
DQ16
93
A8
143
DQ41
193
VSS
44
DQ20
94
A6
144
VSS
194
DQ63
45
DQ17
95
VD D
145
VSS
195
SD A
46
DQ21
96
VD D
146
DQS5#
196
VSS
47
VSS
97
A5
147
DM5
197
SC L
48
VSS
98
A4
148
DQS5
198
SA0
49
DQS2#
99
A3
149
VSS
199
VD D SPD
50
NC
100
A2
150
VSS
200
SA1
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 2 OF 10
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
Functional Block Diagram
3 ohm + 5%
CKE1
ODT1
CS1#
CKE0
ODT0
CS0#
C
K
E
0
DQS CS0#
DQS#
DM
I/O 0
I/O 1
D8
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
O
D
T
1
C
K
E
1
DQS4
DQS4#
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS CS0#
DQS#
DM
I/O 8
I/O 9
D9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
O
D
T
1
C
K
E
1
DQS5
DQS5#
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS CS0# O
DQS#
D
DM
T
0
I/O 8
I/O 9
D1
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
0
DQS CS0# O
D
DQS#
T
DM
1
I/O 0
I/O 1
D10
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
1
DQS6
DQS6#
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
D2
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS CS0# O
D
DQS#
T
DM
1
I/O 8
I/O 9
D11
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
1
DQS7
DQS7#
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS CS0# O
D
DQS#
T
DM
0
I/O 8
I/O 9
D3
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS0
DQS0#
DM0
DQS1
DQS1#
DM1
DQS2
DQS2#
DM2
DQS3
DQS3#
DM3
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
D4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS CS0# O
D
DQS#
T
DM
1
I/O 0
I/O 1
D12
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS CS0# O
DQS#
D
DM
T
0
I/O 8
I/O 9
D5
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
0
DQS CS0# O
DQS#
D
DM
T
1
I/O 8
I/O 9
D13
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
D6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS CS0# O
D
DQS#
T
DM
1
I/O 0
I/O 1
D14
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS CS0# O
D
DQS#
T
DM
0
I/O 8
I/O 9
D7
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
0
DQS CS0# O
D
DQS#
T
DM
1
I/O 8
I/O 9
D15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
1
* Clock Wiring
10 ohms + 5%
BA0 - BA2
DDR2 SDRAMs D0 - D15
A0 - A13
DDR2 SDRAMs D0 - D15
RAS#
DDR2 SDRAMs D0 - D15
CAS#
DDR2 SDRAMs D0 - D15
WE#
DDR2 SDRAMs D0 - D15
SCL
SA0
SA1
SCL
A0
SPD
A1
A2
SDA
Clock Input
DDR2 SDRAMs
*CK0/CK0#
*CK1/CK1#
8 DDR2 SDRAMs
8 DDR2 SDRAMs
WP
* Wire per Clock Loading
Table/Wiring Diagrams
VDDSPD
Serial PD
VREF
DDR2 SDRAMs D0 - D15
VDD
DDR2 SDRAMs D0 - D15, VDD and VDDQ
VSS
DDR2 SDRAMs D0 - D15, SPD
Notes :
1. DQ,DM, DQS/DQS# resistors : 22 Ohms +/- 5%
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 3 OF 10
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
Unit
VDD
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage temperature
-55
100
Command/Address,
RAS#, CAS#, WE#, BA
-80
80
uA
CS#, CKE, ODT
-40
40
uA
C K, C K#
-40
40
uA
DM
-10
10
uA
DQ, DQS, DQS#
-10
10
uA
-32
32
uA
VIN, VOUT
TSTG
Input leakage current; Any input
0V<VIN<VDD; VREF input
0V<VIN<0.95V; Other pins not under
test = 0V
IL
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT
are disabled
IOZ
VREF leakage current; VREF = Valid VREF level
IVREF
0
C
DC Operating Conditions
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
VD D
1.7
1.8
1.9
V
1
I/O Supply voltage
VD D Q
1.7
1.8
1.9
V
4
VDDL Supply voltage
VD D L
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Supply voltage
Notes: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2
percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 4 OF 10
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
Operating Temperature Condition
Parameter
Operating temperature
Symbol
Rating
TOPER
0 to 95
Units
0
C
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At 0 - 850C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85 °C < TOPER<= 95 °
Input DC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage DDR2-667 & DDR2-800
VIH(AC)
VREF + 0.200
-
V
AC Input Low (Logic 0) Voltage DDR2-667 & DDR2-800
VIL(AC)
-
VREF - 0.200
V
Input AC Logic Level
All voltages referenced to VSS
Parameter
Input/Output Capacitance
TA=250C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
20
36
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1)
CIN2
12
20
pF
Input capacitance (CS0#, CS1#)
CIN3
12
20
pF
Input capacitance (CK0, CK0#, CK1, CK1#)
CIN4
12
20
pF
Input/Output capacitance (DQ, DQS, DQS#, DM)
CIO
9
11
pF
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 5 OF 10
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
IDD Specification
Condition
Symbol
-E7
-E6
Unit
Operating one bank active-precharge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0*
496
480
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4; CL = CL(IDD);tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1*
544
520
mA
Precharge pow er-dow n current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD2P**
160
160
mA
Precharge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
IDD2Q**
368
368
mA
Precharge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are SWITCHING.
IDD2N**
448
432
mA
Active pow er-dow n current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs
are FLOATING.
416
400
mA
IDD3P**
240
240
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open;tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD));CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD3N**
592
560
mA
Operating burst w rite current;
All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W*
656
600
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD4R*
800
720
mA
Burst auto refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD5**
1920
1840
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING.
IDD6**
160
160
mA
IDD7*
1440
1320
mA
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD);
tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Notes:
IDD specification is based on Samsung E-die components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 6 OF 10
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
AC Timing Parameters & Specifications
-E7
Parameter
-E6
Symbol
Min
Max
Min
Max
Unit
CL=6
tCK (6)
2500
8000
-
-
ps
CL=5
tCK (5)
3000
8000
3000
8000
ps
CK high-level width
tCH
0.48
0.52
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
MIN
(tCH,tCL)
Clock jitter
tJIT
-100
100
-125
125
ps
DQ output access time from CK/CK#
tAC
-400
400
-450
+450
ps
Data-out high impedance window from CK/CK#
tHZ
tAC (MAX)
ps
Data-out low-impedance window from CK/CK#
tLZ
tAC (MIN)
tAC (MAX)
ps
DQ and DM input setup time relative to DQS
tDS
50
100
DQ and DM input hold time relative to DQS
tDH
125
175
DQ and DM input pulse width (for each input)
tDIPW
0.35
0.35
Data hold skew factor
tQHS
DQ–DQS hold, DQS to first DQ to go nonvalid,
p e r a cce ss
tQH
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
tDQSH
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
tCK
DQS output access time fromCK/CK#
tDQSCK
-350
DQS falling edge to CK rising – setup time
tDSS
0.2
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per group,
p e r a cce ss
tDQSQ
DQS read preamble
tRPRE
0.9
1.1
DQS read postamble
tRPST
0.4
0.6
DQS write preamble setup time
tWPRES
0
0
ps
DQS write preamble
tWPRE
0.35
0.35
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Data Strobe
Data
Clock
Clock cycle time
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MIN)
300
350
tCK
340
-400
200
+400
ps
ps
240
ps
0.9
1.1
tCK
0.4
0.6
tCK
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 7 OF 10
ps
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
AC Timing Parameters & Specifications ( cont')
-E7
Parameter
Min
Command and Address
Address and control i nput pulse wi dth for each
i nput
Self Refresh
Min
Max
U nit
0.6
0.6
tCK
tIS
175
200
ps
Address and control i nput hold ti me
tIH
250
275
ps
C AS# to C AS# command delay
tCCD
2
2
ps
AC TIVE to AC TIVE (same bank) command
tRC
60
60
ns
AC TIVE bank a to AC TIVE bank b command
tRRD
7.5
7.5
ns
AC TIVE to READ or WRITE delay
tRCD
15
15
ns
Four Bank Acti vate peri od
tFAW
37.5
37.5
ns
AC TIVE to PREC HARGE command
tRAS
45
Internal READ to precharge command delay
tRTP
7.5
70,000
45
70,000
ns
7.5
ns
Wri te recovery ti me
tWR
15
15
ns
Auto precharge wri te recovery + precharge ti me
tDAL
tWR+tRP
tWR+tRP
ns
Internal WRITE to READ command delay
tWTR
10
7.5
ns
PREC HARGE command peri od
tRP
15
15
ns
PREC HARGE ALL command peri od
tRPA
tRP+tCK
tRP+tCK
ns
LOAD MOD E command cycle ti me
ODT
tIPW
Max
Address and control i nput setup ti me
tMRD
2
2
tCK
tDELAY
tIS+tCK+tIH
tIS+tCK+tIH
ns
REFRESH to Acti ve or Refresh to Refresh
command i nterval
tRFC
127.5
Average peri odi c refresh i nterval
tREFI
C KE low to C K,C K# uncertai nty
Power-Down
-E6
Symbol
70,000
127.5
7.8
70,000
ns
7.8
us
Exi t self refresh to non-READ command
tXSNR
tRFC(MIN)+10
tRFC(MIN)+10
ns
Exi t self refresh to READ
tXSRD
200
200
tCK
Exi t self refresh ti mi ng reference
tISXR
tIS
OD T turn-on delay
tAOND
2
2
2
2
tCK
OD T turn-on
tAON
tAC(MIN)
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
700
ps
OD T turn-off delay
tAOFD
2.5
2.5
2.5
2.5
tCK
OD T turn-off
tAOF
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
ps
tAONPD
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
ps
OD T turn-off (power-down mode)
tAOFPD
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
ps
OD T to power-down entry latency
tANPD
3
3
tCK
OD T turn-on (power-down mode)
tIS
ps
OD T power-down exi t latency
tAXPD
10
8
tCK
Exi t acti ve power-down to READ command,
MR[bi t12=0]
tXARD
2
2
tCK
Exi t acti ve power-down to READ command,
MR[bi t12=1]
tXARDS
8-AL
7-AL
tCK
Exi t precharge power-down to any non-READ
command.
tXP
2
2
tCK
C KE mi ni mum hi gh/low ti me
tCKE
3
3
tCK
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 8 OF 10
Product Specifications
PART NO:
REV: 1.1
VL470T5663B-E7S/E6S
Package Dimensions
FRONT VIEW
3.40
M AX
67.60
4.00 +/- 0.10 (2X)
30.00
1.80 (2X)
TYP
20.00 TYP
6.00 TYP
2.55 TYP
1.00 +/- 0.10
2.15 TYP
0.45 TYP
1.00 TYP
0.60 TYP
PIN 199
PIN 1
63.60 TYP
BACK VIEW
PIN 2
4.20 TYP
PIN 200
47.40 TYP
11.40 TYP
NOTE:
All dimesions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 9 OF 10
Product Specifications
PART NO:
VL470T5663B-E7S/E6S
Revision History:
Date
Rev.
P ag e
C h an g es
06/17/09
1.0
All
Spec release
08/25/10
1.1
All
Update datasheet
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 10 OF 10
REV: 1.1
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