datasheet for MR26V01G53L by LAPIS Semiconductor

datasheet for MR26V01G53L by LAPIS Semiconductor
FEDR26V01G53L-002-01
Issue Date: Oct. 01, 2008
MR26V01G53L
64M–Word × 16–Bit or 128M–Word × 8–Bit Page Mode
P2ROM
FEATURES
·
·
·
·
·
·
·
·
·
64M-word × 16-bit / 128M-word × 8-bit electrically
switchable configuration
Page size of 8-word x 16-Bit or 16-word x 8-Bit
3.0 V to 3.6 V power supply
Random Access time 105 ns MAX
Page Access time
35 ns MAX
Operating current
100 mA MAX
Standby current
10 mA MAX
Input/Output TTL compatible
Three-state output
PACKAGES
·
MR26V01G53L-xxxMB
70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits over
the other non-volatile technologies, which include the
following;
PIN CONFIGURATION (TOP VIEW)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A23
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
BYTE#
A0
D0
D8
D1
D9
Vcc
D2
D10
D3
D11
GND
1
70 CE#
2
69 A12
3
68 A13
4
67 A14
5
66 A15
6
65 Vcc
7
64 A16
8
63 A17
9
62 A18
10
61 A19
11
60 A20
12
59 A21
13
58 NC
14
57 NC
15
56 NC
16
55 NC
54 NC
17
18
70SSOP
53 GND
19
52 NC
20
51 NC
21
50 NC
22
49 NC
23
48 A22
24
47 A24
25
46 OE#2
26
45 OE#1
27
44 D15/A-1
28
43 D7
29
42 D14
30
41 D6
31
40 D13
32
39 D5
33
38 D12
34
37 D4
35
36 Vcc
· Short lead time, since the P2ROM is programmed at the final
stage of the production process, a large P2ROM inventory
"bank system" of un-programmed packaged products are
maintained to provide an aggressive lead-time and minimize
liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and OTP
that require additional programming and handling costs, the
P2ROM already has the code loaded at the factory with
minimal effect on the production throughput. The cost is
included in the unit price.
· Custom Marking is available at no additional charge
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
BLOCK DIAGRAM
A–1
× 8 / × 16 Switch
OE#2
CE
OE1
OE2
Row Decoder
OE#1
BYTE#
Memory Cell Matrix
64M × 16-Bit or 128M × 8-Bit
Column Decoder
Address Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
CE#
Multiplexer
Output Buffer
D0
D2
D1
D4
D3
D6
D5
D8
D7
D10
D9
D12
D11
D14
D13
D15
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
D15 / A–1
A0 to A24
D0 to D14
CE#
OE#1 OE#2
BYTE#
VCC
VSS
NC
Functions
Data output / Address input
Address inputs
Data outputs
Chip enable input
Output enable input
Word / Byte select input
Power supply voltage
Ground
No connect
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
FUNCTION TABLE
(Vcc=3.0V~3.6V)
Mode
Read (16-Bit)
Read (8-Bit)
Address
CE#
0000000-1FFFFFF
2000000-3FFFFFF
0000000-3FFFFFF
4000000-7FFFFFF
L
L
OE#1
OE#2
L
H
L
H
H
L
H
L
Output disable
∗
L
H
H
Standby
∗
H
∗
∗
BYTE#
D0 to D7
D15/A–1
DOUT(MSB=0)
DOUT(MSB=1)
H
L
D8 to D14
DOUT
H
L
H
L
Hi–Z
L/H
Hi–Z
∗
Hi–Z
∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Power dissipation per package
Output short circuit current
Symbol
Ta
Tstg
VI
VO
VCC
PD
IOS
Condition
—
Relative to VSS
Ta = 25°C
—
Value
0 to 70
–55 to 125
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–0.5 to 5
1.0
10
Unit
°C
°C
V
V
V
W
mA
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter
VCC power supply voltage
Input “H” level
Input “L” level
Symbol
VCC
VIH
VIL
Condition
VCC = 3.0 to 3.6 V
Min.
3.0
2.2
–0.5∗∗
Typ.
—
—
—
Max.
3.6
VCC+0.5∗
0.6
Unit
V
V
V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
(VCC = 3.3 V, Ta = 25°C, f = 1 MHz)
Parameter
Input
BYTE#
Output
Symbol
CIN1
CIN2
COUT
Condition
VI = 0 V
VO = 0 V
Min.
—
—
—
Typ.
—
—
—
Max.
15
400
15
Unit
pF
3/8
FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
Parameter
Input leakage current
Output leakage current
VCC power supply current
(Standby)
Symbol
ILI
ILO
ICCSC
ICCST
Condition
VI = 0 to VCC
VO = 0 to VCC
CE# = VCC
CE# = VIH
Min.
—
—
—
—
Typ.
—
—
—
—
Max.
10
10
10
10
Unit
µA
µA
mA
mA
VCC power supply current
(Read)
ICCA1
CE# = VIL, OE# = VIH
f=5MHz
—
—
100
mA
Input “H” level
VIH
—
2.2
—
Input “L” level
Output “H” level
Output “L” level
VIL
VOH
VOL
—
IOH = –1 mA
IOL = 2 mA
–0.5∗∗
2.4
—
—
—
—
VCC+0.5
∗
0.6
—
0.4
V
V
V
V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
Parameter
Address cycle time
Symbol
tC
Address access time
tACC
Page cycle time
tPC
Page access time
tPAC
CE# access time
OE# access time
OE# delay time
tCE
tOE
tOES
tCHZ
tOHZ
Output disable time
Output hold time
tOH
Condition
—
CE# = VIL
OE1# or OE2#= VIL
—
CE# = VIL
OE1# or OE2#= VIL
OE1# or OE2#= VIL
CE# = VIL
—
OE1# or OE2#= VIL
CE# = VIL
CE# = VIL
OE1# or OE2#= VIL
Min.
105
Max.
—
Unit
ns
—
105
ns
35
—
ns
—
35
ns
—
—
0
0
0
105
30
—
20
20
ns
ns
ns
ns
ns
0
—
ns
Measurement conditions
Input signal level ---------------------------------- 0 V/3 V
Input timing reference level --------------------- 1/2Vcc
Output load ----------------------------------------- 50 pF
Output timing reference level ------------------- 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
tC
tC
Address
tOH
tACC
tCE
CE#
tCHZ
tOE
tOH
OE#1or OE#2
OE#2or OE#1
TOES
tOHZ
tACC
Dout
Valid Data
Valid Data
Hi-Z
Hi-Z
Page Access Mode Read Cycle
tC
A3 to A24
tPC
tPC
A-1 to A2 (Byte mode)
A0 to A2 (Word mode)
tOH
tCE
CE#
tOE
tCHZ
OE#1 or OE#2
OE#2 or OE#1
TOES
tACC
Dout
Hi-Z
tPAC
Valid Data
tPAC
Valid Data
tOHZ
Valid Data
Hi-Z
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
FEDR26V01G53L-02-01
Jul. 29, 2005
–
–
Final edition 1
FEDR26V01G53L-002-01
Oct. 1, 2008
–
–
Changed company logo and name
to OKI SEMICONDUCTOR
Description
7/8
FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
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