Transitioning APEX Designs to Stratix Stratix GX Devices

Transitioning APEX Designs to Stratix Stratix GX Devices
3. Transitioning APEX
Designs to Stratix &
Stratix GX Devices
S52012-3.0
Introduction
Stratix® and Stratix GX devices are Altera’s next-generation, system-ona-programmable-chip (SOPC) solution. Stratix and Stratix GX devices
simplify the block-based design methodology and bridge the gap
between system bandwidth requirements and programmable logic
performance.
This chapter highlights the new features in the Stratix and Stratix GX
devices and provides assistance when transitioning designs from
APEXTM II or APEX 20K devices to the Stratix or Stratix GX architecture.
Designers using this chapter should be familiar with the APEX II or
APEX 20K architecture and available device features. Use this chapter in
conjunction with the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet
section of the Stratix GX Device Handbook, Volume 1.
General
Architecture
Stratix and Stratix GX devices offer many new features and architectural
enhancements. Enhanced logic elements (LEs) and the MultiTrackTM
interconnect structure offer reduced resource utilization and
considerable design performance improvement. The MultiTrack
interconnect uses DirectDriveTM technology to ensure the availability of
deterministic routing resources for any design block, regardless of its
placement within the device.
All architectural changes between Stratix and Stratix GX and APEX II or
APEX 20K devices described in this section do not require any design
changes. However, you must resynthesize your design and recompile in
the Quartus® II software to target Stratix and Stratix GX devices.
Altera Corporation
February 2005
3–1
General Architecture
Logic Elements
Stratix and Stratix GX device LEs include several new, advanced features
that improve design performance and reduce logic resource consumption
(see Table 3–1). The Quartus II software automatically uses these new LE
features to improve device utilization.
Table 3–1. Stratix & Stratix GX LE Features
Feature
Function
Register chain interconnects Direct path between the register output
of an LE and the register input of an
adjacent LE within the same logic array
block (LAB)
Benefit
„ Conserves LE resources
„ Provides fast shift register
implementation
„ Saves local interconnect routing
resources within an LAB
Look-up table (LUT) chain
interconnects
Direct path between the combinatorial „ Allows LUTs within the same LAB to
output of an LE and the fast LUT input cascade together for high-speed wide
of an adjacent LE within the same LAB fan-in functions, such as wide XOR
operations
„ Bypasses local interconnect for
faster performance
Register-to-LUT feedback
path
Allows the register output to feed back
into the LUT of the same LE, such that
the register is packed with its own fanout LUT
„ Enhanced register packing mode
„ Uses resources more efficiently
Dynamic arithmetic mode
Uses one set of LEs for implementing
both an adder and subtractor
„ Improves performance for functions
that switch between addition and
subtraction frequently, such as
correlators
Carry-select chain
Calculates outputs for a possible carry- „ Gives immediate access to result for
in of 1 or 0 in parallel
both a carry-in of 1 or 0
„ Increases speed of carry functions
for high-speed operations, such as
counters, adders, and comparators
Asynchronous clear and
asynchronous preset
function
Supports direct asynchronous clear
and preset functions
„ Conserves LE resources
„ Does not require additional logic
resources to implement NOT-gate
push-back
In addition to the new LE features described in Table 3–1, there are
enhancements to the chains that connect LEs together. Carry chains are
implemented vertically in Stratix and Stratix GX devices, instead of
horizontally as in APEX II and APEX 20K devices, and continue across
rows, instead of across columns, as shown in Figure 3–1. Also note that
the Stratix and Stratix GX architectures do not support the cascade
primitive. Therefore, the Quartus II Compiler automatically converts
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February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
cascade primitives in APEX II and APEX 20K designs to a wire primitive
when compiled for Stratix and Stratix GX devices. These architectural
changes are transparent to the user and do not require design changes.
Figure 3–1. Carry Chain Implementation in APEX II & APEX 20K Devices vs.
Stratix & Stratix GX Devices
APEX II & APEX 20K Devices
Stratix Devices
Carry Chains
Carry-Select
Chains
LABs (with 10 LEs Each)
MultiTrack Interconnect
Stratix and Stratix GX devices use the MultiTrack interconnect structure
to provide a high-speed connection between logic resources using
performance-optimized routing channels of different lengths. This
feature maximizes overall design performance by placing critical paths
on routing lines with greater speed, resulting in minimal propagation
delay.
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February 2005
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Stratix GX Device Handbook, Volume 3
General Architecture
Stratix and Stratix GX device MultiTrack interconnect resources are
described in Table 3–2.
Table 3–2. Stratix & Stratix GX Device MultiTrack Interconnect Resources
Routing Type
Row
Interconnect
Direct link
Span
Adjacent LABs and/or blocks
Row
R4
Four LAB units horizontally
Row
R8
Eight LAB units horizontally
Row
R24
Horizontal routing across the width of the device
Column
C4
Four LAB units vertically
Column
C8
Eight LAB units vertically
Column
C16
Vertical routing across the length of the device
Direct link routing saves row routing resources while providing fast
communication paths between resource blocks. Direct link interconnects
allow an LAB, digital signal processing (DSP) block, or TriMatrixTM
memory block to drive data into the local interconnect of its left and right
neighbors. LABs, DSP blocks, and TriMatrix memory blocks can also use
direct link interconnects to drive data back into themselves for feedback.
The Quartus II software automatically uses these routing resources to
enhance design performance.
f
For more information about LE architecture and the MultiTrack
interconnect structure in Stratix and Stratix GX devices, see the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1
or the Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
DirectDrive Technology
When using APEX II or APE 20K devices, you must place critical paths in
the same MegaLABTM column to improve performance. Additionally, you
should place critical paths in the same MegaLAB structure for optimal
performance. However, this restriction does not exist in Stratix and
Stratix GX devices because they do not contain MegaLAB structures.
With the new DirectDriveTM technology in Stratix and Stratix GX devices,
the actual distance between the source and destination of a path is the
most important criteria for meeting timing performance. DirectDrive
technology ensures that the same routing resources are available to each
design block, regardless of its location in the device.
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February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
Architectural Element Names
The architectural element naming system within Stratix and Stratix GX
devices differs from the row-column coordinate system (for example,
LC1_A2, LAB_B1) used in previous Altera device families. Stratix and
Stratix GX devices uses a new naming system based on the X-Y
coordinate system, (X, Y). A number (N) designates the location within the
block where the logic resides, such as LEs within an LAB. Because the
Stratix and Stratix GX architectures are column-based, this naming
simplifies location assignments. Stratix and Stratix GX architectural
blocks include:
■
■
■
■
■
■
LAB: logic array block
DSP: digital signal processing block
DSPOUT: adder/subtractor/accumulator or summation block of the
DSP block
M512: 512-bit memory block
M4K: 4-Kbit memory block
M-RAM: 512-Kbit memory block
Elements within architectural blocks include:
■
■
■
■
■
■
Altera Corporation
February 2005
LE: logic element
IOC: I/O element
PLL: phase-locked loop
DSPMULT: DSP block multiplier
SERDESTX: transmitter serializer/deserializer
SERDESRX: receiver serializer/deserializer
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Stratix GX Device Handbook, Volume 3
General Architecture
Table 3–3 highlights the new location syntax used for Stratix and
Stratix GX devices.
Table 3–3. Stratix & Stratix GX Location Assignment Syntax
Example of Location Syntax
Architectural
Elements
Element Name
Location Syntax
Location
Description
Blocks
LAB, DSP,
<element_name>_X<number> LAB_X1_Y1
DSPOUT, M512, _Y<number>
M4K, M-RAM
Logic
LE, IOC, PLL,
DSPMULT,
SERDESTX,
SERDESRX
<element_name>_X<number> LC_X1_Y1_N0
_Y<number>_N<number>
Designates the first
LE, N0, in the LAB
located in row 1,
column 1
Pins (1)
I/O pins
pin_<pin_label>
Pin 5
pin_5
Designates the LAB in
row 1, column 1
Note to Table 3–3:
(1)
You can make assignments to I/O pads using IOC_X<number>_Y<number>_N<number>.
Use the following guidelines with the new naming system:
■
■
■
■
■
The anchor point, or origin, in Stratix and Stratix GX devices is in the
bottom-left corner, instead of the top-left corner as in APEX II and
APEX 20K devices.
The anchor point, or origin, of a large block element (e.g., a M-RAM
or DSP block) is also the bottom-left corner.
All numbers are zero-based, meaning the origin at the bottom-left of
the device is X0, Y0.
The I/O pins constitute the first and last rows and columns in the
X-Y coordinates. Therefore, the bottom row of pins resides in
X<number>, Y0, and the first left column of pins resides in X0,
Y<number>.
The sub-location of elements, N, numbering begins at the top.
Therefore, the LEs in an LAB are still numbered from top to bottom,
but start at zero.
Figure 3–2 show the Stratix and Stratix GX architectural element
numbering convention. Figure 3–3 displays the floorplan view in the
Quartus II software.
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February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
Figure 3–2. Stratix & Stratix GX Architectural Elements Note (1)
M4K RAM Blocks are
Two Units Wide and
One Unit High
LAB
(1,18)
LAB
(11,18)
M512
(12,18)
LAB
(13,18)
M4K
(14,18)
LAB
(16,18)
LAB
(1,17)
LAB
(11,17)
M512
(12,17)
LAB
(13,17)
M4K
(14,17)
LAB
(16,17)
LAB
(1,16)
LAB
(11,16)
M512
(12,16)
LAB
(13,16)
M4K
(14,16)
LAB
(16,16)
LAB
(1,15)
LAB
(11,15)
M512
(12,15)
LAB
(13,15)
M4K
(14,15)
LAB
(16,15)
M4K
(14,14)
M4K
(14,13)
Mega RAM Block is
13 Units Wide and
13 Units High
DSP Block (17,1)
is Two Units Wide
and Eight Units High
DSPMULT
(17,7,0)
and
(17,7,1)
(3)
DSPMULT
(17,5,0)
and
(17,5,1)
LAB
(16,14)
DSPOUT
(18,1,0)
and
(18,1,7)
LAB
(16,13)
DSPMULT
(17,3,0)
and
(17,3,1)
Mega RAM (1,2)
M4K
(14,2)
Pins
LAB
(16,2)
DSPMULT
(17,1,0)
and
(17,1,1)
(2)
PLL
(0,1,0)
LAB
(1,1)
LAB
(11,1)
M512
(12,1)
M4K
(14,1)
LAB
(13,1)
(2)
LAB
(16,1)
(2)
Origin (0, 0)
Notes to Figure 3–2:
(1)
(2)
(3)
Figure 3–2 shows part of a Stratix and Stratix GX device.
Large block elements use their lower-left corner for the coordinate location.
The Stratix GX architectural elements include transceiver blocks on the right side of the device.
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February 2005
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Stratix GX Device Handbook, Volume 3
TriMatrix Memory
Figure 3–3. LE Numbering as Shown in the Quartus II Software
TriMatrix
Memory
TriMatrix memory has three different sizes of memory blocks, each
optimized for a different purpose or application. M512 blocks consist of
512 bits plus parity (576 bits), M4K blocks consist of 4K bits plus parity
(4,608 bits), and M-RAM blocks consist of 512K bits plus parity
(589,824 bits). This new structure differs from APEX II and APEX 20K
devices, which feature uniformly sized embedded system blocks (ESBs)
either 4 Kbits (APEX II devices) or 2 Kbits (APEX 20K devices) large.
Stratix and Stratix GX TriMatrix memory blocks give you advanced
control of each memory block, with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode operation.
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February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
Table 3–4 compares TriMatrix memory with ESBs.
Table 3–4. Stratix & Stratix GX TriMatrix Memory Blocks vs. APEX II & APEX 20K ESBs
Stratix & Stratix GX
Features
APEX II ESB
M512 RAM
Size (bits)
576
M4K RAM
4,608
APEX 20K ESB
M-RAM
589,824
4,096
2,048
Parity bits
Yes
Yes
Yes
No
No
Byte enable
No
Yes
Yes
No
No
True dual-port
mode
No
No
Yes
Yes
Yes
Includes support Includes support Includes support
for mixed width for mixed width for mixed width
Embedded shift
register
Yes
Yes
No
No
No
Dedicated
contentaddressable
memory (CAM)
support
No
No
No
Yes
Yes
Pre-loadable
initialization with a
.mif (1)
Yes
Yes
No
Yes
Yes
Packed mode (2)
No
Yes
No
Yes
Yes
Feed-through
behavior
Rising edge
Rising edge
Rising edge
Falling edge
Falling edge
Output power-up
condition
Powers up
cleared even if
using a .mif (1)
Powers up
cleared even if
using a .mif (1)
Powers up with
unknown state
Powers up
cleared or to
initialized value,
if using a .mif (1)
Powers up
cleared or to
initialized value,
if using a .mif (1)
Notes to Table 3–4:
(1)
(2)
.mif: Memory Initialization File.
Packed mode refers to combining two single-port RAM blocks into a single RAM block that is placed into true
dual-port mode.
Stratix and Stratix GX TriMatrix memory blocks only support pipelined
mode, while APEX II and APEX 20K ESBs support both pipelined and
flow-through modes. Since all TriMatrix memory blocks can be
pipelined, all input data and address lines are registered, while outputs
can be either registered or combinatorial. You can use Stratix and
Stratix GX memory block registers to implement input and output
registers without utilizing additional resources. You can compile designs
containing pipelined memory blocks (inputs registered) for Stratix and
Stratix GX devices without any modifications. However, if an APEX II or
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February 2005
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Stratix GX Device Handbook, Volume 3
TriMatrix Memory
APEX 20K design contains flow-through memory, you must modify the
memory modules to target the Stratix and Stratix GX architectures (see
“Memory Megafunctions” on page 3–12 for more information).
f
For more information about TriMatrix memory and converting flowthrough memory modules to pipelined, see the TriMatrix Embedded
Memory Blocks in Stratix & Stratix GX Devices chapter in the Stratix GX
Device Handbook and AN 210: Converting Memory from Asynchronous to
Synchronous for Stratix & Stratix GX Designs.
Same-Port Read-During-Write Mode
In same-port read-during-write mode, the RAM block can be in singleport, simple dual-port, or true dual-port mode. One port from the RAM
block both reads and writes to the same address location using the same
clock. When APEX II or APEX 20K devices perform a same-port readduring-write operation, the new data is available on the falling edge of
the clock cycle on which it was written, as shown in Figure 3–4. When
Stratix and Stratix GX devices perform a same-port read-during-write
operation, the new data is available on the rising edge of the same clock
cycle on which it was written, as shown in Figure 3–5. This holds true for
all TriMatrix memory blocks.
Figure 3–4. Falling Edge Feed-Through Behavior
(APEX II & APEX 20K Devices) Note (1)
inclock
data_in
A
B
wren
data_out
Old
A
Note to Figure 3–4:
(1)
Figures 3–4 and 3–5 assume that the address stays constant throughout and that
the outputs are not registered.
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February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
Figure 3–5. Rising Edge Feed-Through Behavior
(Stratix & Stratix GX Devices) Note (1)
inclock
data_in
A
B
wren
data_out Old
A
Note to Figure 3–5:
(1)
Figures 3–4 and 3–5 assume that the address stays constant throughout and that
the outputs are not registered.
Mixed-Port Read-During-Write Mode
Mixed-port read-during-write mode occurs when a RAM block in simple
or true dual-port mode has one port reading and the other port writing to
the same address location using the same clock. In APEX II and
APEX 20K designs, the ESB outputs the old data in the first half of the
clock cycle and the new data in the second half of the clock cycle, as
indicated by Figure 3–6.
Figure 3–6. Mixed-Port Feed-Through Behavior
(APEX II & APEX 20K Devices) Note (1)
inclock
Port A
data_in
A
B
Port A
wren
Port B
wren
Port B
data_out
Old
A
B
Note to Figure 3–6:
(1)
Figure 3–6 assumes that outputs are not registered.
Stratix and Stratix GX device RAM outputs the new data on the rising
edge of the clock cycle immediately after the data was written. When you
use Stratix and Stratix GX M512 and M4K blocks, you can choose whether
to output the old data at the targeted address or output a don’t care value
during the clock cycle when the new data is written. M-RAM blocks
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February 2005
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Stratix GX Device Handbook, Volume 3
TriMatrix Memory
always output a don’t care value. Figures 3–7 and 3–8 show the feedthrough behavior of the mixed-port mode. You can use the altsyncram
megafunction to set the output behavior during mixed-port read-duringwrite mode.
Figure 3–7. Mixed-Port Feed-Through Behavior (OLD_DATA) Note (1)
inclock
addressA and
addressB
Port A
data_in
Address Q
A
B
Port A
wren
Port B
wren
Port B
data_out
Old
A
B
Note to Figure 3–7:
(1)
Figures 3–7 and 3–8 assume that the address stays constant throughout and that
the outputs are not registered.
Figure 3–8. Mixed-Port Feed-Through Behavior (DONT_CARE) Note (1)
inclock
addressA and
addressB
Port A
data_in
Address Q
A
B
Port A
wren
Port B
wren
Port B
data_out
Unknown
B
Note to Figure 3–8:
(1)
Figures 3–7 and 3–8 assume that the address stays constant throughout and that
the outputs are not registered.
Memory Megafunctions
To convert RAM and ROM originally targeting the APEX II or APEX 20K
architecture to Stratix or Stratix GX memory, specify Stratix or Stratix GX
as the target family in the MegaWizard Plug-In Manager. The software
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Transitioning APEX Designs to Stratix & Stratix GX Devices
updates the memory module for the Stratix or Stratix GX architecture and
instantiates the new synchronous memory megafunction, altsyncram,
which supports both RAM and ROM blocks in the Stratix and Stratix GX
architectures.
FIFO Conditions
First-in first-out (FIFO) functionality is slightly different in Stratix and
Stratix GX devices compared to APEX II and APEX 20K devices. Stratix
and Stratix GX devices do not support simultaneous reads and writes
from an empty FIFO buffer. Also, Stratix and Stratix GX devices do not
support the lpm_showahead parameter when targeting a FIFO buffer
because the TriMatrix memory blocks are synchronous. The
lpm_showahead parameter for APEX II and APEX 20K devices puts the
FIFO buffer in “read-acknowledge” mode so the first data written into the
FIFO buffer immediately flows through to the output. Other than these
two differences, all APEX II and APEX 20K FIFO functions are fully
compatible with the Stratix and Stratix GX architectures.
Design Migration Mode in Quartus II Software
The Quartus II software features a migration mode for simplifying the
process of converting APEX II and APEX 20K memory functions to the
Stratix or Stratix GX architecture. If the design can use the Stratix or
Stratix GX altsyncram megafunction as a replacement for a previous
APEX II or APEX 20K memory function while maintaining functionally
similar behavior, the Quartus II software automatically converts the
memory. The software produces a warning message during compilation
reminding you to verify that the design migrated correctly.
For memory blocks with all inputs registered, the existing megafunction
is converted to the new altsyncram megafunction. The software
generates a warning when the altsyncram megafunction is
incompatible. For example, a RAM block with all inputs registered except
the read enable compiles with a warning message indicating that the
read-enable port is registered.
You can suppress warning messages for the entire project or for
individual memory blocks by setting the
SUPPRESS_MEMORY_CONVERSION_WARNINGS parameter to “on” as a
global parameter by selecting Assignment Organizer (Tools menu). In
the Assignment Organizer window, click Parameters in the Assignment
Categories box. Type SUPPRESS_MEMORY_CONVERSION_WARNINGS in
the Assignment Name box and type ON in the Assignment Setting box.
To suppress these warning messages on a per-memory-instance basis, set
the SUPPRESS_MEMORY_CONVERSION_WARNINGS parameter in the
Assignment Organizer to “on” for the memory instance.
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February 2005
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TriMatrix Memory
If the functionality of the APEX II or APEX 20K memory megafunction
differs from the altsyncram functionality and at least one clock feeds
the memory megafunction, the Quartus II software converts the APEX II
or APEX 20K memory megafunction to the Stratix or Stratix GX
altsyncram megafunction. This conversion is useful for an initial
evaluation of how a design might perform in Stratix or Stratix GX devices
and should only be used for evaluation purposes. During this process, the
Quartus II software generates a warning that the conversion may be
functionally incorrect and timing results may not be accurate. Since the
functionality may be incorrect and the compilation is only intended for
comparative purposes, the Quartus II software does not generate a
programming file. A functionally correct conversion requires manually
instantiating the altsyncram megafunction and may require additional
design changes.
If the previous memory function does not have a clock (fully
asynchronous), the fitting-evaluation conversion results in an error
message during compilation and does not successfully convert the
design.
f
See AN 210: Converting Memory from Asynchronous to Synchronous for
Stratix & Stratix GX Designs for more information.
Table 3–5 summarizes the possible scenarios when using design
migration mode and the resulting behavior of the Quartus II software.
The most common cases where design-migration mode may have
difficulty converting the existing design are when:
■
A port is reading from an address that is being written to by another
port (mixed-port read-during-write mode). If both ports are using
the same clock, the read port in Stratix and Stratix GX devices do not
see the new data until the next clock cycle, after the new data was
written.
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February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
■
There are differences in power-up behavior between APEX II,
APEX 20K, and Stratix and Stratix GX devices. You should manually
account for these differences to maintain desired operation of the
system.
Table 3–5. Migration Mode Summary
Memory
Configuration
Single-port
Conditions
Possible
Instantiated
Megafunctions
All inputs are registered. altram
Quartus II Warning
Message(s)
Programming
File
Generated
Power-up differences. (1)
Yes
Power-up differences.
Mixed-port read- duringwrite. (1)
Yes
Yes
altrom
lpm_ram_dq
lpm_ram_io
lpm_rom
All inputs are registered. altdpram
Multi-port (two-,
three-, or four-port
lpm_ram_dp
functions)
altqpram
alt3pram
Dual-port
Read-enable ports are
unregistered.
Other inputs registered.
altdpram
lpm_ram_dp
altqpram
alt3pram
Power-up differences.
Mixed-port read- duringwrite.
Read enable will be
registered. (1)
Dual-port
Any other unregistered
port except read-enable
ports.
Clock available.
altdpram
lpm_ram_dp
altqpram
alt3pram
Compile for fitting- evaluation No
purposes.
Single-port
At least one registered
input.
Clock available.
altram
lpm_ram_dq
lpm_ram_io
Compile for fitting- evaluation No
purposes.
No clock
No clock.
altram
altrom
altdpram
altqpram
alt3pram
altdpram
lpm_ram_dq
lpm_ram_io
lpm_rom
lpm_ram_dp
lpm_ram_dp
Error – no conversion
possible.
No
Note to Table 3–5:
(1)
If the SUPPRESS_MEMORY_COUNVERSION_WARNINGS parameter is turned on, the Quartus II software does not
issue these warnings.
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February 2005
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Stratix GX Device Handbook, Volume 3
DSP Block
DSP Block
Stratix and Stratix GX device DSP blocks outperform LE-based
implementations for common DSP functions. Each DSP block contains
several multipliers that can be configured for widths of 9, 18, or 36 bits.
Depending on the mode of operation, these multipliers can optionally
feed an adder/subtractor/accumulator or summation unit.
You can configure the DSP block’s input registers to efficiently
implement shift registers for serial input sharing, eliminating the need for
external shift registers in LEs. You can add pipeline registers to the DSP
block for accelerated operation. Registers are available at the input and
output of the multiplier, and at the output of the
adder/subtractor/accumulator or summation block.
DSP blocks have four modes of operation:
■
■
■
■
Simple multiplier mode
Multiply-accumulator mode
Two-multipliers adder mode
Four-multipliers adder mode
Associated megafunctions are available in the Quartus II software to
implement each mode of the DSP block.
DSP Block Megafunctions
You can use the lpm_mult megafunction to configure the DSP block for
simple multiplier mode. You can set the lpm_mult Multiplier
Implementation option in the MegaWizard Plug-In Manager to either
use the default implementation, ESBs, or the DSP blocks. If you select the
Use Default option, the compiler first attempts to place the multiplier in
the DSP blocks. However, under certain conditions, the compiler may
implement the multiplier in LEs. The placement depends on factors such
as DSP block resource consumption, the width of the multiplier, whether
an operand is a constant, and other options chosen for the megafunction.
Stratix and Stratix GX devices do not support the Use ESBs option. If you
select this option, the Quartus II software tries to place the multiplier in
unused DSP blocks.
You can recompile APEX II or APEX 20K designs using the lpm_mult
megafunction for Stratix and Stratix GX devices in the Quartus II
software without changing the megafunction. This makes converting
lpm_mult megafunction designs to Stratix or Stratix GX devices
straightforward.
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Transitioning APEX Designs to Stratix & Stratix GX Devices
APEX II and APEX 20K designs use pipeline stages to improve registered
performance of LE-based multipliers at the expense of latency. However,
you may not need to use pipeline stages when targeting Stratix and
Stratix GX high-speed DSP blocks. The DSP blocks offer three sets of
dedicated pipeline registers. Therefore, Altera recommends that you
reduce the number of pipeline stages to three or fewer and implement
them in the DSP blocks. Additional pipeline stages are implemented in
LEs, which add latency without providing any performance benefit.
For example, you can configure a DSP block for 36 × 36-bit multiplication
using the lpm_mult megafunction. If you specify two pipeline stages,
the software uses the DSP block input and pipeline registers. If you
specify three pipeline stages, the software places the third pipeline stage
in the DSP block output registers. This design yields the same
performance with three pipeline stages because the critical path for a
36 × 36-bit operation is within the multiplier. With four or more pipeline
stages, the device inefficiently uses LE resources for the additional
pipeline stages. Therefore, if multiplier modules in APEX II or APEX 20K
designs are converted to Stratix or Stratix GX designs and do not require
the same number of pipeline stages, the surrounding circuitry must be
modified to preserve the original functionality of the design.
A design with multipliers feeding an accumulator can use the
altmult_accum (MAC) megafunction to set the DSP block in multiplyaccumulator mode. If the APEX II or APEX 20K design already uses LEbased multipliers feeding an accumulator, the Quartus II software does
not automatically instantiate the new altmult_accum (MAC)
megafunction. Therefore, you should use the MegaWizard Plug-In
Manager to instantiate the altmult_accum (MAC) megafunction. You
can also use LeonardoSpectrum™ or Synplify synthesis tools, which have
DSP block inference support, to instantiate the megafunction.
Designs that use multipliers feeding into adders can instantiate the new
altmult_add megafunction to configure the DSP blocks for twomultipliers adder or four-multipliers adder mode. You can also use the
altmult_add megafunction for stand-alone multipliers to take
advantage of the DSP blocks features such as dynamic sign control of the
inputs and the input shift register connections. These features are not
accessible through the lpm_mult megafunction. If your APEX II or
APEX 20K designs already use multipliers feeding an adder/subtractor,
the Quartus II software does not automatically infer the new
altmult_add megafunction. Therefore, you should step through the
MegaWizard Plug-In Manager to instantiate the new altmult_add
megafunction or use LeonardoSpectrum or Synplify synthesis tools,
which have DSP block inference support.
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February 2005
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PLLs & Clock Networks
Furthermore, the altmult_add and altmult_accum (MAC)
megafunctions are only available for Stratix and Stratix GX devices
because these megafunctions target Stratix and Stratix GX DSP blocks,
which are not available in other device families. If you attempt to use
these megafunctions in designs that target other Altera device families,
the Quartus II software reports an error message. Use lpm_mult and an
lpm_add_sub or an altaccumulate megafunction for similar
functionality in other device families.
If you use a third-party synthesis tool, you may be able to avoid the
megafunction conversion process. LeonardoSpectrum and Synplify
provide inference support for lpm_mult, altmult_add, and
altmult_accum (MAC) to use the DSP blocks.
If your design does not require you to implement all the multipliers in
DSP blocks, you must manually set a global parameter or a parameter for
each instance to force the tool to implement the lpm_mult megafunction
in LEs. Depending on the synthesis tools, inference of DSP blocks is
handled differently.
f
PLLs & Clock
Networks
For more information about using DSP blocks in Stratix and Stratix GX
devices, see the DSP Blocks in Stratix & Stratix GX Devices chapter of the
Stratix Device Handbook.
Stratix and Stratix GX devices provide exceptional clock management
with a hierarchical clock network and up to four enhanced phase-locked
loops (PLLs) and eight fast PLLs versus the four general-purpose PLLs
and four True-LVDSTM PLLs in APEX II devices. By providing superior
clock interfacing, numerous advanced clocking features, and significant
enhancements over APEX II and APEX 20K PLLs, the Stratix and
Stratix GX device PLLs increase system performance and bandwidth.
Clock Networks
There are 16 global clock networks available throughout each Stratix or
Stratix GX device as well as two fast regional and four regional clock
networks per device quadrant, resulting in up to 40 unique clock
networks per device. The increased number of dedicated clock resources
available in Stratix and Stratix GX devices eliminate the need to use
general-purpose I/O pins as clock inputs.
Stratix EP1S25 and smaller devices have 16 dedicated clock pins and
EP1S30 and larger devices have four additional clock pins to feed various
clocking networks. In comparison, APEX II devices have eight dedicated
clock pins and APEX 20KE and APEX 20KC devices have four dedicated
clock pins.
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Transitioning APEX Designs to Stratix & Stratix GX Devices
The dedicated clock pins in Stratix and Stratix GX devices can feed the
PLL clock inputs, the global clock networks, and the regional clock
networks. PLL outputs and internally-generated signals can also drive
the global clock network. These global clocks are available throughout
the entire device to clock all device resources.
Stratix and Stratix GX devices are divided into four quadrants, each
equipped with four regional clock networks. The regional clock network
can be fed by either the dedicated clock pins or the PLL outputs within its
device quadrant. The regional clock network can only feed device
resources within its particular device quadrant.
Each Stratix and Stratix GX device provides eight dedicated fast clock
I/O pins FCLK[7..0] versus four dedicated fast I/O pins in APEX II
and APEX 20K devices. The fast regional clock network can be fed by
these dedicated FCLK[7..0] pins or by the I/O interconnect. The I/O
interconnect allows internal logic or any I/O pin to drive the fast regional
clock network. The fast regional clock network is available for generalpurpose clocking as well as high fan-out control signals such as clear,
preset, enable, TRDY and IRDY for PCI applications, or bidirectional or
output pins.
EP1S25 and smaller devices have eight fast regional clock networks, two
per device quadrant. The quadrants in EP1S30 and larger devices are
divided in half, and each half-quadrant can be clocked by one of the eight
fast regional networks. Additionally, each fast regional clock network can
drive its neighboring half-quadrant (within the same device quadrant).
PLLs
Table 3–6 highlights Stratix and Stratix GX PLL enhancements to existing
APEX II, APEX 20KE and APEX 20KC PLL features.
Table 3–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 1 of 2)
Stratix & Stratix GX
Feature
APEX II PLLs
Enhanced PLLs
Fast PLLs
APEX 20KE &
APEX 20KC PLLs
Number of PLLs
Two (EP1S30 and
smaller devices);
four (EP1S40 and
larger devices) (9)
Four (EP1S25 and Four generalpurpose PLLs and
smaller devices);
four LVDS PLLs
eight (EP1S30
and larger
devices) (10)
Up to four generalpurpose PLLs. Up
to two LVDS PLLs.
(1)
Minimum input frequency
3 MHz
15 MHz
1.5 MHz
1.5 MHz
Maximum input frequency
250 to 582 MHz (2) 644.5 MHz (11)
420 MHz
420 MHz
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February 2005
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PLLs & Clock Networks
Table 3–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 2 of 2)
Stratix & Stratix GX
Feature
APEX II PLLs
Enhanced PLLs
Fast PLLs
APEX 20KE &
APEX 20KC PLLs
Internal clock outputs per
PLL
6
3 (3)
2
2
External clock outputs per
PLL
Four
differential/eight
singled-ended or
one single-ended
(4)
Yes (5)
1
1
Phase Shift
Down to 160-ps
increments (6)
Down to 125-ps
increments (6)
500-ps to 1-ns
resolution
0.4- to 1-ns
resolution
Time shift
250-ps increments No
for ± 3 ns (7)
No
No
M counter values
1 to 512
1 to 32
1 to 160
2 to 160
N counter values
1 to 512
N/A
1 to 16
1 to 16
PLL clock input sharing
No
Yes
Yes
Yes
T1/E1 rate conversion (8)
No
No
Yes
Yes
Notes to Table 3–6:
(1)
EP20K200E and smaller devices only have two general-purpose PLLs. EP20K400E and larger devices have two
LVDS PLLs and four general-purpose PLLs. For more information, see AN 115: Using the ClockLock & ClockBoost
PLL Features in APEX Devices.
(2) The maximum input frequency for Stratix and Stratix GX enhanced PLLs depends on the I/O standard used with
that input clock pin. For more information, see the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook.
(3) Fast PLLs 1, 2, 3, and 4 have three internal clock output ports per PLL. Fast PLLs 7, 8, 9, and 10 have two internal
clock output ports per PLL.
(4) Every Stratix device has two enhanced PLLs with eight single-ended or four differential outputs each. Two
additional enhanced PLLs in EP1S80, EP1S60, and EP1S40 devices each have one single-ended output.
(5) Any I/O pin can be driven by the fast PLL global or regional outputs as an external clock output pin.
(6) The smallest phase shift unit is determined by the voltage-controlled oscillator (VCO) period divided by 8.
(7) There is a maximum of 3 ns between any two PLL clock outputs.
(8) The T1 clock frequency is 1.544 MHz and the E1 clock frequency is 2.048 MHz, which violates the minimum clock
input frequency requirement of the Stratix PLL.
(9) Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX40 contains four.
(10) Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX40 contains four.
(11) Stratix GX supports clock rates of 1 Gbps using DPA.
Enhanced PLLs
Stratix and Stratix GX devices provide up to four enhanced PLLs with
advanced PLL features. In addition to the feature changes mentioned in
Table 3–6, Stratix and Stratix GX device PLLs include many new,
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advanced features to improve system timing management and
performance. Table 3–7 shows some of the new features available in
Stratix and Stratix GX enhanced PLLs.
Table 3–7. Stratix & Stratix GX Enhanced PLL Features
Feature
Description
Programmable duty cycle (1) Allows variable duty cycle for each PLL clock output.
PLL clock outputs can feed
logic array (1)
Allows the PLL clock outputs to feed data ports of registers or combinatorial logic.
PLL locked output can feed
the logic array (1)
Allows the PLL locked port to feed data ports of registers or combinatorial logic.
Multiplication allowed in
zero-delay buffer mode or
external feedback mode
The PLL clock outputs can be a multiplied or divided down ratio of the PLL input
clock.
Programmable phase shift
allowed in zero-delay buffer
mode or external feedback
mode (2)
The PLL clock outputs can be phase shifted. The phase shift is relative to the PLL
clock output.
Phase frequency detector
(PFD) disable
Allows the VCO to operate at its last set control voltage and frequency with some
long term drift.
Clock output disable (3)
PLL maintains lock with output clocks disabled. (4)
Programmable lock detect &
gated lock
Holds the lock signal low for a programmable number of input clock cycles.
Dynamic clock switchover
Enables the PLL to switch between two reference input clocks, either for clock
redundancy or dual-clock domain applications.
PLL reconfiguration
Allows the counters and delay elements within the PLL to be reconfigured in realtime without reloading a programmer object file (.pof).
Programmable bandwidth
Provides advanced control of the PLL bandwidth by using the programmable
control of the PLL loop characteristics.
Spread spectrum
Modulates the target frequency over a frequency range to reduce
electromagnetic interference (EMI) emissions.
Notes to Table 3–7:
(1)
(2)
(3)
(4)
These features are also available in fast PLLs.
In addition to the delay chains at each counter, you can specify the programmable phase shift for each PLL output
at fine and coarse levels.
Each PLL clock output has an associated clock enable signal.
If the PLL is used in external feedback mode, the PLL will need to relock.
Fast PLLs
Stratix and Stratix GX fast PLLs are similar to the APEX II True-LVDS
PLLs in that the W setting, which governs the relationship between the
clock input and the data rate, and the J setting, which controls the width
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February 2005
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PLLs & Clock Networks
of the high-speed differential I/O data bus, do not have to be equal.
Additionally, Stratix and Stratix GX fast PLLs offer up to three clock
outputs, two multiplied high-speed PLL clocks to drive the
serializer/deserializer (SERDES) block and/or an external pin, and a
low-speed clock to drive the logic array. You can use fast PLLs for both
high-speed interfacing and for general-purpose PLL applications.
Table 3–8 shows the differences between Stratix and Stratix GX fast PLLs
and APEX II and APEX 20K True-LVDS PLLs.
Table 3–8. Stratix & Stratix GX Fast PLL vs. APEX II & APEX 20K True-LVDS PLL
Feature
Stratix & Stratix GX
APEX 20KE
APEX 20KC
APEX II
Number of fast PLLs or TrueLVDS PLLs (1)
Four (EP1S25 and smaller
devices) fast PLLs
Eight (EP1S30 and larger
devices) fast PLLs (4)
Four True-LVDS
PLLs
Two True-LVDS
PLLs (2)
Number of channels per
transmitter/receiver block
20
18
18
VCO frequency
300 to 840 MHz (5)
200 MHz to 1GHz
200 to 840 MHz
Minimum input frequency
M = 4, 5, 6
300 – M MHz
50 MHz
50 MHz
M = 4 (3)
Minimum input frequency
M = 7, 8, 9, 10
300 – M MHz
30 MHz
30 MHz
M = 7, 8 (3)
Notes to Table 3–8:
(1)
(2)
(3)
(4)
(5)
You can also use Stratix and Stratix GX device fast PLLs for general-purpose PLL applications.
EP20K400E and larger devices have two True-LVDS PLLs.
In APEX 20KE and APEX 20KC devices, M = 4, 7, or 8.
Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX10 contains four.
Stratix GX supports a frequency range of 300–1000 MHz (using DPA).
The Stratix and Stratix GX fast PLL VCO frequency range is 300 to 840
MHz, and the APEX II True-LVDS PLL VCO frequency range is 200 MHz
to 1 GHz. Therefore, you must update designs that use a data rate of less
than 300 megabits per second (Mbps) to use the enhanced PLLs and M512
RAM blocks in SERDES bypass mode. Additionally, you must update
designs that use a data rate faster than 840 Mbps.
altpll Megafunction
Altera recommends that you replace instances of the altclklock
megafunction with the altpll megafunction to take advantage of new
Stratix and Stratix GX PLL features. Although in most cases you can
retarget your APEX II or APEX 20K design to a Stratix or Stratix GX
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device with the altclklock megafunction, there are specific cases
where you must use the altpll megafunction, as explained in this
section.
In the MegaWizard Plug-In Manager, select the altpll megafunction in
the I/O directory from the Available Megafunctions box (see
Figure 3–9). The altclklock megafunction is also available from the
Quartus II software for backward compatibility, but instantiates the new
altpll megafunction when targeting Stratix or Stratix GX devices. The
Quartus II Compiler automatically selects whether the altpll module
uses either an enhanced PLL or a fast PLL based on the design’s PLL
needs and the feature requirements of each PLL.
Figure 3–9. altpll Megafunction Selection in the MegaWizard Plug-In Manager
You can compile APEX II, APEX 20KE, and APEX 20KC designs using the
altclklock megafunction in normal mode for Stratix and Stratix GX
devices without updating the megafunction. However, you should
replace the altclklock megafunction with the altpll megafunction.
If the Quartus II software cannot implement the requested clock
multiplication and division of the PLL, the compiler reports an error
message with the appropriate reason stated.
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February 2005
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PLLs & Clock Networks
APEX II, APEX 20KE, and APEX 20KC devices have only one external
clock output available per PLL. Therefore, when retargeting an APEX II,
APEX 20KE, or APEX 20KC design that uses PLLs in zero delay buffer
mode or external feedback mode to a Stratix or Stratix GX device, you
should replace instances of the altclklock megafunction. If an
APEX II, APEX 20KE, or APEX 20KC altclklock module only uses one
PLL clock output (internal or external) and is compiled to target a Stratix
or Stratix GX device, the design compiles successfully with a warning
that the design uses the Stratix or Stratix GX PLL external clock output,
extclk0. However, if the APEX II, APEX 20KE, or APEX 20KC PLL has
more than one PLL clock output, you must replace instances of the
altclklock megafunction with the altpll megafunction because the
Quartus II Compiler does not know which PLL clock output is fed to an
external output pin or fed back to the Stratix or Stratix GX device fbin
pin. For example, if an APEX II, APEX 20KE, or APEX 20KC design with
an altclklock megafunction uses the clock0 output port to feed the
external clock output pin and the clock1 output port to feed the internal
logic array, the Quartus II software generates an error during
compilation and you must use the MegaWizard Plug-In Manager to
instantiate the altpll megafunction. By using the altpll
megafunction, you can choose which of the four external clock outputs to
use and take advantage of the new Stratix and Stratix GX PLL features
now available in the zero delay buffer mode or external feedback mode.
Timing Analysis
When the Quartus II software performs a timing analysis for APEX II,
APEX 20KE, or APEX 20KC designs, PLL clock settings override the
project clock settings. However, during timing analysis for Stratix and
Stratix GX designs using PLLs, the project clock settings override the PLL
input clock frequency and duty cycle settings. The MegaWizard Plug-In
Manager does not use the project clock settings to determine the altpll
parameters. This saves time with designs that use features such as clock
switchover or PLL reconfiguration because the Quartus II software can
perform a timing analysis without recompiling the design. It is important
to note the following:
■
■
■
■
A warning during compilation reports that the project clock settings
overrides the PLL clock settings.
The project clock setting overrides the PLL clock settings for timingdriven compilation.
The compiler will check the lock frequency range of the PLL. If the
frequency specified in the project clock settings is outside the lock
frequency range, the PLL clock settings will not be overridden.
Performing a timing analysis without recompiling your design does
not change the programming files. You must recompile your design
to update the programming files.
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■
A Default Required fMAX setting does not override the PLL clock
settings. Only individual clock settings override the PLL clock
settings.
Therefore, you can enter different project clock settings corresponding to
new PLL settings and accelerate timing analysis by eliminating a full
compilation cycle.
f
I/O Structure
For more information about using Stratix and Stratix GX PLLs, see the
General-Purpose PLLs in Stratix & Stratix GX Devices chapter.
The Stratix and Stratix GX I/O element (IOE) architecture is similar to the
APEX II architecture, with a total of six registers and a latch in each IOE.
The registers are organized in three sets: two output registers to drive a
single or double-data rate (DDR) output path, two input registers and a
latch to support a single or DDR input path, and two output enable
registers to enhance clock-to-output enable timing or for DDR SDRAM
interfacing. A new synchronous reset signal is available to each of the
three sets of registers for preset or clear, or neither. In addition to the
advanced IOE architecture, the Stratix and Stratix GX IOE features
dedicated circuitry for external RAM interfacing, new I/O standards,
differential on-chip termination, and high-speed differential I/O
standard support.
External RAM Interfacing
The advanced Stratix and Stratix GX IOE architecture includes dedicated
circuitry to interface with external RAM. This circuitry provides
enhanced support for external high-speed memory devices such as DDR
SDRAM and FCRAM. The DDR SDRAM interface uses a bidirectional
signal, DQS, to clock data, DQ, at both the transmitting and receiving
device. Stratix and Stratix GX devices transmit the DQS signal with the DQ
data signals to minimize clock to data skew.
Stratix and Stratix GX devices include groups of programmable DQS and
DQ pins, in the top and bottom I/O banks of the device. Each group
consists of a DQS pin that supports a fixed number of DQ pins. The number
of DQ pins depends on the DQ bus mode. When using the external RAM
interfacing circuitry, the DQS pin drives a dedicated clock network that
feeds the DQ pins residing in that bank. The Stratix and Stratix GX IOE has
programmable delay chains that can phase shift the DQS signal by 90° or
72° to ensure data is sampled at the appropriate point in time. Therefore,
the Stratix and Stratix GX devices make full use of the IOEs, and remove
the need to build the input data path in the logic array. You can make
these I/O assignments in the Quartus II Assignment Organizer.
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February 2005
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I/O Structure
f
For more information on external RAM interfacing, see the Stratix Device
Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the
Stratix GX Device Family Data Sheet in the Stratix GX Device Family
Handbook.
I/O Standard Support
The Stratix and Stratix GX devices support all of the I/O standards that
APEX II and APEX 20K devices support, including high-speed
differential I/O standards such as LVDS, LVPECL, PCML, and
HyperTransportTM technology, differential HSTL on input and output
clocks, and differential SSTL on output clocks. Stratix and Stratix GX
devices also introduce support for SSTL-18 class I & II. Similar to APEX II
devices, Stratix and Stratix GX devices only support certain I/O
standards in designated I/O banks. In addition, vref pins are dedicated
pins in Stratix and Stratix GX devices and now support up to 40 input
pins.
f
For more information about I/O standard support in Stratix and
Stratix GX devices, see the Selectable I/O Standards in Stratix &
Stratix GX Devices chapter.
High-Speed Differential I/O Standards
Stratix and Stratix GX devices support high-speed differential interfaces
at speeds up to 840 Mbps using high-speed PLLs that drive a dedicated
clock network to the SERDES. Each fast PLL can drive up to 20 highspeed channels. Stratix and Stratix GX devices use enhanced PLLs and
M512 RAM blocks to provide up to 420 Mbps performance for SERDES
bypass clock interfacing. There is no restriction on the number of
channels that can be clocked using this scenario.
Stratix and Stratix GX devices have a different number of differential
channels than APEX II devices. Tables 3–9 and 3–10 highlight the number
of differential channels supported in Stratix and Stratix GX devices.
Table 3–9. Number of Dedicated DIfferential Channels in Stratix Devices
(Part 1 of 2) Note (1)
Pin Count
Number of Receiver
Channels
Number of
Transmitter Channels
EP1S10
672
36
36
780
44
44
EP1S20
672
50
48
780
66
66
Device
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Table 3–9. Number of Dedicated DIfferential Channels in Stratix Devices
(Part 2 of 2) Note (1)
Device
EP1S25
EP1S30
EP1S40
Pin Count
Number of Receiver
Channels
Number of
Transmitter Channels
672
58
56
780
66
70
1,020
78
78
780
66
70
956
80
80
1,020
80
80
2
2
956
80
80
1,020
1,508
EP1S60
EP1S80
80
80
10
10
80
80
10
10
956
80
80
1,020
80
80
10
12
1,508
80
80
36
36
956
80
80
0
40
1,508
80
80
56
72
Note to Table 3–9:
(1)
For information on channel speeds, see the Stratix Device Family Data Sheet section
of the Stratix Device Handbook, Volume 1 and the High-Speed Differential I/O
Interfaces chapter in the Stratix Device Handbook, Volume 2.
Table 3–10. Number of Dedicated DIfferential Channels in Stratix GX Devices (Part 1 of 2) Note (1)
Pin Count
Number of
Transceivers
Number of SourceSynchronous
Channels
EP1SGX10 C
672
4
22
EP1SGX10 D
672
8
22
Device
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I/O Structure
Table 3–10. Number of Dedicated DIfferential Channels in Stratix GX Devices (Part 2 of 2) Note (1)
Pin Count
Number of
Transceivers
Number of SourceSynchronous
Channels
EP1SGX25 C
672
4
39
EP1SGX25 D
672/1,020
8
39
EP1SGX25 F
1,020
16
39
EP1SGX40 D
1,020
8
45
EP1SGX40 G
1,020
20
45
Device
Note to Table 3–10:
(1)
For information on channel speeds, see the Stratix GX Device Family Data Sheet
section of the Stratix GX Device Handbook, Volume 1 and the High-Speed
Source-Synchronous Differential I/O Interfaces in Stratix GX Devices chapter of the
Stratix GX Device Handbook, Volume 2.
The differential I/O within Stratix GX also provides dynamic phase
alignment (DPA). DPA enables the differential I/O to operate up to
1 Gbps per channel. DPA automatically and continuously tracks
fluctuations caused by system variations and self-adjusts to eliminate the
phase skew between the multiplied clock and the serial data. The block
contains a dynamic phase selector for phase detection and selection, a
SERDES, a synchronizer, and a data realigner circuit. You can bypass the
dynamic phase aligner without affecting the basic source-synchronous
operation of the channel by using a separate deserializer.
If you compile an APEX II LVDS design that uses clock-data
synchronization (CDS) for a Stratix or Stratix GX device, the Quartus II
software issues a warning during compilation that Stratix and Stratix GX
devices do not support CDS.
Stratix and Stratix GX devices offer a flexible solution using new byte
realignment circuitry to correct for byte misalignment by shifting, or
slipping, data bits. Stratix and Stratix GX devices activate the byte
realignment circuitry when an external pin (rx_data_align) or an
internal custom-made state machine asserts the SYNC node high.
APEX II, APEX 20KE, and APEX 20KCdevices have a dedicated
transmitter clock output pin (LVDSTXOUTCLK). In Stratix and Stratix GX
devices, a transmitter dataout channel with an LVDS clock (fast clock)
generates the transmitter clock output. Therefore, you can drive any
channel as an output clock to an I/O pin, not just dedicated clock output
pins. This solution offers better versatility to address various applications
that require more complex clocking schemes.
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Stratix GX Device Handbook, Volume 3
Altera Corporation
February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
f
For more information on differential I/O support, data realignment, and
the transmitter clock output in Stratix and Stratix GX devices, see the
High-Speed Differential I/O Interfaces in Stratix Devices chapter.
altlvds Megafunction
To take full advantage of the high-speed differential I/O standards
available in Stratix and Stratix GX devices, you should update each
instance of the altlvds megafunction in APEX II, APEX 20KE, and
APEX 20KC designs. In the MegaWizard Plug-In Manager, choose the
altlvds megafunction, select Stratix or Stratix GX as the target device
family, update the megafunction, and recompile your design.
The altlvds megafunction supports new Stratix and Stratix GX
parameters that are not available for APEX II, APEX 20KE, and
APEX 20KC devices. Tables 3–11 and 3–12 describe the new parameters
for the LVDS receiver and LVDS transmitter, respectively.
Table 3–11. New altlvds Parameters for Stratix LVDS Receiver Note (1)
Parameter
Function
input_data_rate (2)
Specifies the data rate in Mbps. This parameter replaces the
multiplication factor W.
inclock_data_alignment
Indicates the alignment of rx_inclk and rx_in data.
rx_data_align
Drives the data alignment port of the fast PLL and enables byte
realignment circuitry.
registered_data_align_input Registers the rx_data_align input port to be clocked by
rx_outclock.
common_rx_tx_pll (3)
Indicates the fast PLL can be shared between receiver and transmitter
applications.
Table 3–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 1 of 2) Note (1)
Parameter
Function
output_data_rate (2)
Specifies the data rate in Mbps. This parameter replaces the
multiplication factor W.
inclock_data_alignment
Indicates the alignment of tx_inclk and tx_in data.
outclock_alignment
Specifies the alignment of tx_outclock and tx_out data.
registered_input
Specifies the clock source for the input synchronization registers,
which can be either tx_inclock or tx_coreclock. Used only
when the Registered Inputs option is selected.
Altera Corporation
February 2005
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Stratix GX Device Handbook, Volume 3
Configuration
Table 3–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 2 of 2) Note (1)
Parameter
Function
Indicates the fast PLL can be shared between receiver and transmitter
applications.
common_rx_tx_pll (3)
Notes to Tables 3–11 and 3–12:
(1)
(2)
(3)
You can specify these parameters in the MegaWizard Plug-In Manager.
You must specify a data rate in the MegaWizard Plug-In Manager instead of a W factor.
The same fast PLL can be used to clock both the receiver and transmitter only if both are running at the same
frequency.
Above the standard I/O offered by APEX II, APEX 20K, and Stratix
devices, Stratix GX devices provide up to 20 3.175 Gbps transceivers. The
transceivers provide high-speed serial links for chip-to-chip, backplane,
and line-side connectivity and support a number of the emerging
high-speed protocols. You can find more information in the Stratix GX
Family Data Sheet in the Stratix GX Family Handbook, Volume 1.
Configuration
The Stratix and Stratix GX devices supports all current configuration
schemes, including the use of enhanced configuration devices, passive
serial (PS), passive parallel asynchronous (PPA), fast passive parallel
(FPP), and JTAG. Stratix and Stratix GX devices also provide a number of
new configuration enhancements that you can take advantage of when
migrating APEX II and APEX 20K designs to Stratix and Stratix GX
devices.
Configuration Speed & Schemes
You can configure Stratix and Stratix GX devices at a maximum clock
speed of 100 MHz, which is faster than the 66-MHz and 33-MHz
maximum configuration speeds for APEX II and APEX 20K devices,
respectively. Similar to APEX II devices, you can use 8-bit parallel data to
configure Stratix and Stratix GX devices (the target device can receive
byte-wide configuration data on each clock cycle) significantly speeding
up configuration times.
You can select a configuration scheme based on how the MSEL pins are
driven. Stratix and Stratix GX devices have three MSEL pins (APEX II and
APEX 20K devices have two MSEL pins) for determining the
configuration scheme.
f
For more information about Stratix and Stratix GX configuration
schemes, see the Configuring Stratix & Stratix GX Devices chapter.
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February 2005
Transitioning APEX Designs to Stratix & Stratix GX Devices
Remote Update Configuration
The APEX 20K device family introduced the concept of remote update
configuration, where you could send the APEX 20K device new
configuration files from a remote source and the device would store the
files in flash memory and reconfigure itself with the new configuration
data. The Stratix and Stratix GX devices enhance support for remote
update configuration with new, dedicated circuitry to handle and recover
from errors. If an error occurs either during device configuration or in
user mode, this new circuitry reconfigures the Stratix or Stratix GX device
to a known state. Additionally, the Stratix and Stratix GX devices have a
user watchdog timer to ensure the application configuration data
executes successfully during user mode. User logic must continually reset
this watchdog timer in order to validate that the application
configuration data is functioning properly.
f
For more information about how to use the remote and local update
modes, see the Remote System Configuration with Stratix & Stratix GX
Devices chapter.
JTAG Instruction Support
Stratix and Stratix GX devices support two new JTAG instructions,
PULSE_NCONFIG and CONFIG_IO. The PULSE_NCONFIG instruction
emulates pulsing the nCONFIG signal low to trigger reconfiguration,
while the actual nCONFIG pin on the device is unaffected. The
CONFIG_IO instruction allows you to use the JTAG chain to configure
I/O standards for all pins. Because this instruction interrupts device
configuration, you should reconfigure the Stratix or Stratix GX device
after you finish JTAG testing to ensure proper device operation.
Table 3–13 compares JTAG instruction support in Stratix and Stratix GX
devices versus APEX II and APEX 20K devices. For further information
about the supported JTAG instructions, see the appropriate device family
data sheet.
Table 3–13. JTAG Instruction Support (Part 1 of 2)
JTAG Instruction
Altera Corporation
February 2005
Stratix
APEX II
APEX 20K
SAMPLE/PRELOAD
v
v
v
EXTEST
v
v
v
BYPASS
v
v
v
USERCODE
v
v
v
IDCODE
v
v
v
ICR Instructions
v
v
v
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Stratix GX Device Handbook, Volume 3
Conclusion
Table 3–13. JTAG Instruction Support (Part 2 of 2)
JTAG Instruction
Conclusion
Stratix
APEX II
APEX 20K
SignalTapTM II Instructions
v
v
v
HIGHZ
v
v
CLAMP
v
v
PULSE_NCONFIG
v
CONFIG_IO
v
The Stratix and Stratix GX devices extend the advanced features available
in the APEX II and APEX 20K device families to deliver a complete
system-on-a-programmable-chip (SOPC) solution. By following these
guidelines, you can easily transition current APEX II and APEX 20K
designs to take advantage of the new features available in Stratix and
Stratix GX devices.
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Stratix GX Device Handbook, Volume 3
Altera Corporation
February 2005
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