High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
5. High-Speed Differential I/O
Interfaces with DPA in Stratix II
and Stratix II GX Devices
SII52005-2.2
Introduction
Stratix® II and Stratix® II GX device family offers up to 1-Gbps
differential I/O capabilities to support source-synchronous
communication protocols such as HyperTransport™ technology, Rapid
I/O, XSBI, and SPI.
Stratix II and Stratix II GX devices have the following dedicated circuitry
for high-speed differential I/O support:
■
■
■
■
■
■
■
Differential I/O buffer
Transmit serializer
Receive deserializer
Data realignment circuit
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Analog PLLs (fast PLLs)
For high-speed differential interfaces, Stratix II and Stratix II GX devices
can accommodate different differential I/O standards, including the
following:
■
■
■
■
■
1
I/O Banks
Altera Corporation
January 2008
LVDS
HyperTransport technology
HSTL
SSTL
LVPECL
HSTL, SSTL, and LVPECL I/O standards can be used only for
PLL clock inputs and outputs in differential mode.
Stratix II and Stratix II GX inputs and outputs are partitioned into banks
located on the periphery of the die. The inputs and outputs that support
LVDS and HyperTransport technology are located in row I/O banks, two
on the left and two on the right side of the Stratix II device and two on the
left side of the Stratix II GX device. LVPECL, HSTL, and SSTL standards
are supported on certain top and bottom banks of the die (banks 9 to 12)
when used as differential clock inputs/outputs. Differential HSTL and
SSTL standards can be supported on banks 3, 4, 7, and 8 if the pins on
these banks are used as DQS/DQSn pins. Figures 5–1 and 5–2 show
where the banks and the PLLs are located on the die.
5–1
I/O Banks
Figure 5–1. Stratix II I/O Banks Note (1), (2), (3), (4), (5), (6), and (7)
DQS8T
VREF0B3
DQS7T
VREF1B3
DQS6T
VREF2B3
VREF3B3
DQS5T
VREF4B3
PLL11
PLL5
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL7
PLL10
VR EF1B 5
VREF 4B5
VREF 0B2
VR EF3B5
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
operations. HSTL-18 Class II, HSTL-15-Class II,
SSTL-18 Class II standards are only supported
for input operations.
PLL1
PLL4
VR EF1B6
VREF 2B6
VREF 3B6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VREF 4B6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
Bank 6
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
VREF 0B1
VREF 1B1
Bank 1
VR EF3B1
VR EF0B6
PLL3
VR EF4B1
PLL2
VREF 2B1
VR EF2B5
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
Bank 5
VR EF2B2
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VR EF1B2
Bank 2
VR EF3B 2
VREF 0B5
Bank 4
VREF 4B2
Bank 3
Bank 12
Bank 8
Bank 10
Bank 7
PLL8
PLL9
VREF4B8
DQS8B
VREF3B8
VREF2B8
DQS7B
VREF1B8
DQS6B
VREF0B8
DQS5B
PLL12
PLL6
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Notes to Figure 5–1:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Figure 5–1 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only. See the pin list and Quartus II software for exact locations.
Depending on the size of the device, different device members have different numbers of VREF groups.
Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
Differential HSTL and differential SSTL standards are available for bidirectional operations on DQS pin and
input-only operations on PLL clock input pins; LVDS, LVPECL, and HyperTransport standards are available for
input-only operations on PLL clock input pins. See the Selectable I/O standards in Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook for more details.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks. See
the Selectable I/O standards in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook if
you need to implement these standards at these I/O banks.
Banks 11 and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
PLLs 7, 8, 9, 10, 11, and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
5–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Figure 5–2. Stratix II GX I/O Banks Note (1), (2), (3), (4), (5), (6), and (7)
DQS ×8
PLL7
DQS ×8
DQS ×8
DQS ×8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 4
Bank 9
VREF3B1 VREF4B1
Bank 1
VREF0B1 VREF1B1
14
17
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output
operations. HSTL, SSTL-18 class II,
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
PLL2
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
This I/O bank supports LVDS
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
and LVPECL standards for input clock
Differential HSTL and differential
operation. Differential HSTL and differential
SSTL standards are supported
SSTL standards are supported
for both input and output operations. (3)
for both input and output operations. (3)
Bank 8
PLL8
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 12
Bank 10
PLL12
PLL6
16
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
PLL1
VREF2B1
DQS ×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
13
Bank 11
PLL5
15
Bank 2
VREF0B2 VREF1B2
VREF2B2
VREF3B2 VREF4B2
Bank 3
PLL11
Bank 7
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Notes to Figure 5–2:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Figure 5–2 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
Depending on size of the device, different device members have different number of VREF groups. Refer to the pin
list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
Horizontal I/O banks feature transceiver and DPA circuitry for high speed differential I/O standards.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks.
Refer to the “Differential Pin Placement Guidelines” on page 5–21 if you need to implement these standards at these
I/O banks.
Banks 11 and 12 are available only in EP2SGX60C/D/E, EP2SGX90E/F, and EP2SGX130G.
PLLs 7, 8, 11, and 12 are available only in EP2SGX60C/D/E, EP2SGXE/F, and EP2SGX130G.
Altera Corporation
January 2008
5–3
Stratix II Device Handbook, Volume 2
I/O Banks
Table 5–1 lists the differential I/O standards supported by each bank.
Table 5–1. Supported Differential I/O Types
Bank
Row I/O (Banks 1, 2, 5 and 6) (2)
Type
Clock Inputs
Clock
Outputs
Data or
Regular I/O
Pins
Column I/O (Banks, 3, 4 and 7 through 12)
Clock Inputs
Clock
Outputs
Data or
Regular I/O
Pins
Differential HSTL
v
v
(1)
Differential SSTL
v
v
(1)
v
v
v
v
LVPECL
LVDS
v
v
v
HyperTransport
technology
v
v
v
Note to Table 5–1:
(1)
(2)
Used as both inputs and outputs on the DQS/DQSn pins.
Banks 5 and 6 are not available in Stratix II GX devices.
Table 5–2 shows the total number of differential channels available in
Stratix II devices. The available channels are divided evenly between the
left and right banks of the die. Non-dedicated clocks in the left and right
banks can also be used as data receiver channels. The total number of
receiver channels includes these four non-dedicated clock channels. Pin
migration is available for different size devices in the same package.
Table 5–2. Differential Channels in Stratix II Devices (Part 1 of 2) Notes (1), (2), and (3)
484-Pin
484-Pin Hybrid
FineLine BGA FineLine BGA
672-Pin
FineLine BGA
EP2S15
38 transmitters
42 receivers
38 transmitters
42 receivers
EP2S30
38 transmitters
42 receivers
58 transmitters
62 receivers
EP2S60
38 transmitters
42 receivers
58 transmitters
62 receivers
Device
EP2S90
38 transmitters
42 receivers
EP2S130
5–4
Stratix II Device Handbook, Volume 2
780-Pin
FineLine BGA
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Within the
1,508-pin Fin
84 transmitters
84 receivers
64 transmitters
68 receivers
90 transmitters 118 transmitters
94 receivers
118 receivers
64 transmitters
68 receivers
88 transmitters 156 transmitters
92 receivers
156 receivers
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Table 5–2. Differential Channels in Stratix II Devices (Part 2 of 2) Notes (1), (2), and (3)
Device
484-Pin
484-Pin Hybrid
FineLine BGA FineLine BGA
672-Pin
FineLine BGA
EP2S180
780-Pin
FineLine BGA
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Within the
1,508-pin Fin
88 transmitters 156 transmitters
92 receivers
156 receivers
Notes to Table 5–2:
(1)
(2)
(3)
Pin count does not include dedicated PLL input pins.
The total number of receiver channels includes the four non-dedicated clock channels that can optionally be used as data
channels.
Within the 1,508-pin FineLine BGA package, 92 receiver channels and 92 transmitter channels are vertically migratable.
Table 5–3 shows the total number of differential channels available in
Stratix II GX devices. Non-dedicated clocks in the left bank can also be
used as data receiver channels. The total number of receiver channels
includes these four non-dedicated clock channels. Pin migration is
available for different size devices in the same package.
Table 5–3. Differential Channels in Stratix II GX Devices
Device
780-Pin FineLine
BGA
EP2SGX30
29 transmitters
31receivers
EP2SGX60
29 transmitters
31 receivers
EP2SGX90
EP2SGX130
1,152-Pin FineLine
BGA
Notes (1), (2), (3)
1,508-Pin FineLine
BGA
42 transmitters
42 receivers
45 transmitters
47 receivers
59 transmitters
59 receivers
71 transmitters
73 receivers
Notes to Table 5–3:
(1)
(2)
(3)
Altera Corporation
January 2008
Pin count does not include dedicated PLL input pins.
The total number of receiver channels includes the four non-dedicated clock
channels that can optionally be used as data channels.
EP2SGX30CF780 devices with four transceiver channels are vertically migratable to
EP2SGX60CF780 devices with four transceiver channels. EP2SGX30DF780 devices
with eight transceiver channels are vertically migratable to EP2SGX60DF780
devices with eight transceiver channels. EP2SGX60EF1152 devices with 12
transceiver channels are vertically migratable to EP2SGX90EF1152 devices with 12
transceiver channels. EP2SGX90FF1508 devices with 16 transceiver channels are
vertically migratable to EP2SGX130GF1508 devices with 20 transceiver channels.
5–5
Stratix II Device Handbook, Volume 2
Differential Transmitter
Differential
Transmitter
The Stratix II and Stratix II GX transmitter has dedicated circuitry to
provide support for LVDS and HyperTransport signaling. The dedicated
circuitry consists of a differential buffer, a serializer, and a shared fast
PLL. The differential buffer can drive out LVDS or HyperTransport signal
levels that are statically set in the Quartus® II software. The serializer
takes data from a parallel bus up to 10 bits wide from the internal logic,
clocks it into the load registers, and serializes it using the shift registers
before sending the data to the differential buffer. The most significant bit
(MSB) is transmitted first. The load and shift registers are clocked by the
diffioclk (a fast PLL clock running at the serial rate) and controlled by
the load enable signal generated from the fast PLL. The serialization
factor can be statically set to × 4, × 5, × 6, × 7, × 8, × 9, or × 10 using the
Quartus II software. The load enable signal is automatically generated by
the fast PLL and is derived from the serialization factor setting. Figure 5–3
is a block diagram of the Stratix II transmitter.
Figure 5–3. Transmitter Block Diagram
Serializer
10
TX_OUT
Internal
Logic
diffioclk
Fast PLL
load_en
Each Stratix II and Stratix II GX transmitter data channel can be
configured to operate as a transmitter clock output. This flexibility allows
the designer to place the output clock near the data outputs to simplify
board layout and reduce clock-to-data skew. Different applications often
require specific clock to data alignments or specific data rate to clock rate
factors. The transmitter can output a clock signal at the same rate as the
data with a maximum frequency of 717 MHz. The output clock can also
be divided by a factor of 2, 4, 8, or 10, depending on the serialization
factor. The phase of the clock in relation to the data can be set at 0° or 180°
(edge or center aligned). The fast PLL provides additional support for
5–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
other phase shifts in 45° increments. These settings are made statically in
the Quartus II MegaWizard® software. Figure 5–4 shows the transmitter
in clock output mode.
Figure 5–4. Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
tx_outclock
Internal
Logic
diffioclk
load_en
The serializer can be bypassed to support DDR (× 2) and SDR (× 1)
operations. The I/O element (IOE) contains two data output registers that
each can operate in either DDR or SDR mode. The clock source for the
registers in the IOE can come from any routing resource, from the fast
PLL, or from the enhanced PLL. Figure 5–5 shows the bypass path.
Figure 5–5. Serializer Bypass
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
Internal Logic
tx_out
Serializer
Not used (connection exists)
Altera Corporation
January 2008
5–7
Stratix II Device Handbook, Volume 2
Differential Receiver
Differential
Receiver
The receiver has dedicated circuitry to support high-speed LVDS and
HyperTransport signaling, along with enhanced data reception. Each
receiver consists of a differential buffer, dynamic phase aligner (DPA),
synchronization FIFO buffer, data realignment circuit, deserializer, and a
shared fast PLL. The differential buffer receives LVDS or HyperTransport
signal levels, which are statically set by the Quartus II software. The DPA
block aligns the incoming data to one of eight clock phases to maximize
the receiver’s skew margin. The DPA circuit can be bypassed on a
channel-by-channel basis if it is not needed. Set the DPA bypass statically
in the Quartus II MegaWizard Plug-In Manager or dynamically by using
the optional RX_DPLL_ENABLE port.
The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that
compensates for any phase difference between the DPA block and the
deserializer. If necessary, the data realignment circuit inserts a single bit
of latency in the serial bit stream to align the word boundary. The
deserializer includes shift registers and parallel load registers, and sends
a maximum of 10 bits to the internal logic. The data path in the receiver is
clocked by either the diffioclk signal or the DPA recovered clock. The
deserialization factor can be statically set to 4, 5, 6, 7, 8, 9, or 10 by using
the Quartus II software. The fast PLL automatically generates the load
enable signal, which is derived from the deserialization factor setting.
Figure 5–6 shows a block diagram of the receiver.
Figure 5–6. Receiver Block Diagram
DPA Bypass Multiplexer
Up to 1 Gbps
+
–
D
Q
Data
Realignment
Circuitry
10
Internal
Logic
Dedicated
Receiver
Interface
data retimed_data
DPA
Synchronizer
DPA_clk
Eight Phase Clocks
8
rx_inclk
Fast
PLL
5–8
Stratix II Device Handbook, Volume 2
diffioclk
load_en
Regional or
Global Clock
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
The deserializer, like the serializer, can also be bypassed to support DDR
(× 2) and SDR (× 1) operations. The DPA and data realignment circuit
cannot be used when the deserializer is bypassed. The IOE contains two
data input registers that can operate in DDR or SDR mode. The clock
source for the registers in the IOE can come from any routing resource,
from the fast PLL, or from the enhanced PLL. Figure 5–7 shows the
bypass path.
Figure 5–7. Deserializer Bypass
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
rx_in
Deserializer
PLD Logic
Array
DPA
Circuitry
Receiver Data Realignment Circuit
The data realignment circuit aligns the word boundary of the incoming
data by inserting bit latencies into the serial stream. An optional
RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each
receiver independently controlled from the internal logic. The data slips
one bit for every pulse on the RX_CHANNEL_DATA_ALIGN port. The
following are requirements for the RX_CHANNEL_DATA_ALIGN port:
■
■
■
■
Altera Corporation
January 2008
The minimum pulse width is one period of the parallel clock in the
logic array.
The minimum low time between pulses is one period of parallel
clock.
There is no maximum high or low time.
Valid data is available two parallel clock cycles after the rising edge
of RX_CHANNEL_DATA_ALIGN.
5–9
Stratix II Device Handbook, Volume 2
Differential Receiver
Figure 5–8 shows receiver output (RX_OUT) after one bit slip pulse with
the deserialization factor set to 4.
Figure 5–8. Data Realignment Timing
inclk
rx_in
3
2
1
0
3
2
1
0
3
2
1
0
rx_outclock
rx_channel_data_align
3210
rx_out
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion
before a rollover occurs. The programmable bit rollover point can be from
1 to 11 bit-times independent of the deserialization factor. An optional
status port, rx_cda_max, is available to the FPGA from each channel to
indicate when the preset rollover point is reached.
Figure 5–9 illustrates a preset value of four bit-times before rollover
occurs. The rx_cda_max signal pulses for one rx_outclk cycle to
indicate that the rollover has occurred.
Figure 5–9. Receiver Data Re-alignment Rollover
inclk
rx_channel_data_align
rx_outclk
rx_cda_max
Dynamic Phase Aligner
The DPA block takes in high-speed serial data from the differential input
buffer and selects one of eight phase clocks to sample the data. The DPA
chooses a phase closest to the phase of the serial data. The maximum
phase offset between the data and the phase-aligned clock is 1/8 UI,
which is the maximum quantization error of the DPA. The eight phases
5–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
are equally divided, giving a 45-degree resolution. Figure 5–10 shows the
possible phase relationships between the DPA clocks and the incoming
serial data.
Figure 5–10. DPA Clock Phase to Data Bit Relationship
rx_in
D0
D1
D2
D3
D4
Dn
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
Tvco
0.125Tvco
Each DPA block continuously monitors the phase of the incoming data
stream and selects a new clock phase if needed. The selection of a new
clock phase can be prevented by the optional RX_DPLL_HOLD port, which
is available for each channel.
The DPA block requires a training pattern and a training sequence of at
least 256 repetitions of the training pattern. The training pattern is not
fixed, so you can use any training pattern with at least one transition on
each channel. An optional output port, RX_DPA_LOCKED, is available to
the internal logic, to indicate when the DPA block has settled on the
closest phase to the incoming data phase. The RX_DPA_LOCKED
de-asserts, depending on what is selected in the Quartus II MegaWizard
Plug-In, when either a new phase is selected, or when the DPA has moved
two phases in the same direction. The data may still be valid even when
the RX_DPA_LOCKED is deasserted. Use data checkers to validate the data
when RX_DPA_LOCKED is deasserted.
An independent reset port, RX_RESET, is available to reset the DPA
circuitry. The DPA circuit must be retrained after reset.
Altera Corporation
January 2008
5–11
Stratix II Device Handbook, Volume 2
Differential I/O Termination
Synchronizer
The synchronizer is a 1-bit × 6-bit deep FIFO buffer that compensates for
the phase difference between the recovered clock from the DPA circuit
and the diffioclk that clocks the rest of the logic in the receiver. The
synchronizer can only compensate for phase differences, not frequency
differences between the data and the receiver’s INCLK. An optional port,
RX_FIFO_RESET, is available to the internal logic to reset the
synchronizer. The synchronizer is automatically reset when the DPA first
locks to the incoming data. Altera® recommends using RX_FIFO_RESET
to reset the synchronizer when the DPA signals a loss-of-lock condition
beyond the initial locking condition.
Differential I/O
Termination
f
Stratix II and Stratix II GX devices provide an on-chip 100-Ω differential
termination option on each differential receiver channel for LVDS and
HyperTransport standards. The on-chip termination eliminates the need
to supply an external termination resistor, simplifying the board design
and reducing reflections caused by stubs between the buffer and the
termination resistor. You can enable on-chip termination in the Quartus II
assignments editor. Differential on-chip termination is supported across
the full range of supported differential data rates.
For more information, refer to the High-Speed I/O Specifications section
of the DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook or the High-Speed I/O Specifications section of the
DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
Figure 5–11 illustrates on-chip termination.
Figure 5–11. On-Chip Differential Termination
Stratix II Differential
Receiver with On-Chip
100 Ω Termination
LVDS/HT
Transmitter
Z0 = 50 Ω
RD
Z0 = 50 Ω
On-chip differential termination is supported on all row I/O pins and on
clock pins CLK[0, 2, 8, 10]. The clock pins CLK[1, 3, 9, 11],
and FPLL[7..10]CLK, and the clocks in the top and bottom I/O banks
(CLK[4..7, 12..15]) do not support differential on-chip termination.
5–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Fast PLL
The high-speed differential I/O receiver and transmitter channels use the
fast PLL to generate the parallel global clocks (rx- or tx- clock) and
high-speed clocks (diffioclk). Figure 5–12 shows the locations of the
fast PLLs. The fast PLL VCO operates at the clock frequency of the data
rate. Each fast PLL offers a single serial data rate support, but up to two
separate serialization and/or deserialization factors (from the C0 and C1
fast PLL clock outputs) can be used. Clock switchover and dynamic fast
PLL reconfiguration is available in high-speed differential I/O support
mode.
f
For additional information on the fast PLL, refer to the PLLs in Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II Handbook or
the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Handbook.
Figure 5–12 shows a block diagram of the fast PLL in high-speed
differential I/O support mode.
Figure 5–12. Fast PLL Block Diagram
Global or
regional clock (2)
Clock (1)
Switchover
Circuitry
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
diffioclk0 (3)
4
loaden0 (4)
÷c0
(5)
Clock
Input
Post-Scale
Counters
÷n
PFD
Charge
Pump
Loop
Filter
VCO
÷k
diffioclk1 (3)
8
loaden1 (4)
÷c1
4
Global clocks
÷c2
4
Global or
regional clock (2)
8
Regional clocks
÷c3
÷m
Shaded Portions of the
PLL are Reconfigurable
8
to DPA block
Notes to Figure 5–12:
(1)
(2)
(3)
(4)
(5)
Stratix II fast PLLs only support manual clock switchover.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or pin-driven dedicated global or regional clock.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix II devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
If the design enables this ÷2 counter, the device can use a VCO frequency range of 150 to 520 MHz.
Altera Corporation
January 2008
5–13
Stratix II Device Handbook, Volume 2
Clocking
Clocking
The fast PLLs feed in to the differential receiver and transmitter channels
through the LVDS/DPA clock network. The center fast PLLs can
independently feed the banks above and below them. The corner PLLs
can feed only the banks adjacent to them. Figures 5–13 and 5–14 show the
LVDS and DPA clock networks of the Stratix II devices.
Figure 5–13. Fast PLL and LVDS/DPA Clock for EP2S15, EP2S30, and EP2S60 Devices Note (1)
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock 4
4
4
2
2
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
4
2
2
4
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock 4
Note to Figure 5–13:
(1)
Figure 5–13 applies to EP2S60 devices in the 484 and 672 pin packages.
5–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Figure 5–14. Fast PLL and LVDS/DPA Clocks for EP2S60, EP2S90, EP2S130 and EP2S180 Devices Note (1)
Fast
PLL 7
Fast
PLL 10
2
2
4
LVDS
Clock
DPA
Clock
Quadrant
DPA
Clock
Quadrant
LVDS
Clock
4
4
4
2
2
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
LVDS
Clock
4
DPA
Clock
Quadrant
DPA
Clock
Quadrant
LVDS
Clock
2
2
4
2
2
Fast
PLL 8
Fast
PLL 9
Note to Figure 5–14:
(1)
Figure 5–14 applies only to the EP2S60 in the 1020 Stratix II GX device.
Figures 5–15 and 5–16 show the Fast PLL and LVDS/DPA clock of the
Stratix II GX devices.
Figure 5–15. Fast PLL and LVDS/DPA Clock for EP2SGX30C/D and EP2SGX60C/D Devices
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
2
Fast
PLL 1
No Fast PLLs on
Right Side of
Stratix II GX Devices
Fast
PLL 2
4
4
Altera Corporation
January 2008
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
5–15
Stratix II Device Handbook, Volume 2
Clocking
Figure 5–16. Fast PLL and LVDS/DPA Clocks for EP2SGX60E, EP2SGX90 and EP2SGX130 Devices
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 1
No Fast PLLs on
Right Side of
Stratix II GX Devices
Fast
PLL 2
2
Quadrant
4
LVDS
Clock
Quadrant
DPA
Clock
2
Fast
PLL 8
Source Synchronous Timing Budget
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Stratix II and Stratix II GX devices.
LVDS and HyperTransport I/O standards enable high-speed data
transmission. This high data transmission rate results in better overall
system performance. To take advantage of fast system performance, it is
important to understand how to analyze timing for these high-speed
signals. Timing analysis for the differential block is different from
traditional synchronous timing analysis techniques.
Rather than focusing on clock-to-output and setup times,
source-synchronous timing analysis is based on the skew between the
data and the clock signals. High-speed differential data transmission
requires the use of timing parameters provided by IC vendors and is
strongly influenced by board skew, cable skew, and clock jitter. This
section defines the source-synchronous differential data orientation
timing parameters, the timing budget definitions for Stratix II and
Stratix II GX devices, and how to use these timing parameters to
determine a design's maximum performance.
5–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 1 Gbps and SERDES factor of 10, the external clock
is multiplied by 10, and phase-alignment can be set in the PLL to coincide
with the sampling window of each data bit. The data is sampled on the
falling edge of the multiplied clock. Figure 5–17 shows the data bit
orientation of the × 10 mode.
Figure 5–17. Bit Orientation in the Quartus II Software
inclock/outclock
10 LVDS Bits
MSB
data in
n-1
n-0
9
8
7
6
5
4
3
LSB
2
1
0
high-frequency clock
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies. Figure 5–18 shows the data bit orientation for a channel
operation. These figures are based on the following:
■
■
■
SERDES factor equals clock multiplication factor
Edge alignment is selected for phase alignment
Implemented in hard SERDES
For other serialization factors use the Quartus II software tools and find
the bit position within the word. The bit positions after deserialization are
listed in Table 5–4.
Figure 5–18 also shows a functional waveform. Timing waveforms may
produce different results. Altera recommends performing a timing
simulation to predict actual device behavior.
Altera Corporation
January 2008
5–17
Stratix II Device Handbook, Volume 2
Clocking
Figure 5–18. Bit Order for One Channel of Differential Data
Transmitter Channel
Operation (x8 Mode)
tx_outclock
Previous Cycle
tx_out
X
X
X
X
X
X
X
Current Cycle
7
X
6
5
4
3
Next Cycle
2
1
MSB
0
X
X
X
X
X
X
X
X
X
X
X
X
LSB
Receiver Channel
Operation (x4 Mode)
rx_inclock
rx_in
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
XXXX
rx_out [3..0]
XXXX
XXXX
3210
Receiver Channel
Operation (x8 Mode)
rx_inclock
rx_in
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
rx_out [7..0]
XXXXXXXX
5–18
Stratix II Device Handbook, Volume 2
XXXXXXXX
XXXX7654
3210XXXX
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Table 5–4 shows the conventions for differential bit naming for
18 differential channels. The MSB and LSB positions increase with the
number of channels used in a system.
Table 5–4. LVDS Bit Naming
Receiver Channel Data
Number
Internal 8-Bit Parallel Data
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
17
135
128
18
143
136
Receiver Skew Margin for Non-DPA
Changes in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, the receiver's setup and hold times, and
internal skew, reduce the sampling window for the receiver. The timing
margin between the receiver’s clock input and the data input sampling
window is called Receiver Skew Margin (RSKM). Figure 5–19 shows the
relationship between the RSKM and the receiver’s sampling window.
Altera Corporation
January 2008
5–19
Stratix II Device Handbook, Volume 2
Clocking
TCCS, RSKM, and the sampling window specifications are used for
high-speed source-synchronous differential signals without DPA. When
using DPA, these specifications are exchanged for the simpler single DPA
jitter tolerance specification. For instance, the receiver skew is why each
input with DPA selects a different phase of the clock, thus removing the
requirement for this margin.
Figure 5–19. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
Receiver
Input Data
TCCS
Sampling
Window (SW)
RSKM
tSW (min)
Bit n
Timing Budget
RSKM
Internal tSW (max)
Clock
Bit n
Falling Edge
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
RSKM
RSKM
TCCS
TCCS
2
TSWEND
Receiver
Input Data
TSWBEGIN
5–20
Stratix II Device Handbook, Volume 2
Sampling
Window
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Differential Pin
Placement
Guidelines
In order to ensure proper high-speed operation, differential pin
placement guidelines have been established. The Quartus II compiler
automatically checks that these guidelines are followed and will issue an
error message if these guidelines are not met. PLL driving distance
information is separated into guidelines with and without DPA usage.
High-Speed Differential I/Os and Single-Ended I/Os
When a differential channel or channels of side banks are used (with or
without DPA), you must adhere to the guidelines described in the
following sections.
■
■
■
■
■
Altera Corporation
January 2008
Single-ended I/Os are allowed in the same bank as the LVDS
channels (with or without DPA) as long as the single-ended I/O
standard uses the same VCCIO as the LVDS bank.
Single-ended inputs can be in the same LAB row. Outputs cannot be
on the same LAB row with LVDS I/Os. If input registers are used in
the IOE, single-ended inputs cannot be in the same LAB row as an
LVDS SERDES block.
LVDS (non-SERDES) I/Os are allowed in the same row as LVDS
SERDES but the use of IOE registers are not allowed.
Single-ended outputs are limited to 120 mA drive strength on LVDS
banks (with or without DPA).
●
LVTTL equation for maximum number of I/Os in an LVDS
bank:
• 120 mA = (number of LVTTL outputs) × (drive strength of
each LVTTL output)
●
SSTL-2 equation:
• 120 mA = (number of SSTL-2 I/Os) × (drive strength of each
output) ÷ 2
●
LVTTL and SSTL-2 mix equation:
• 120 mA= (total drive strength of all LVTTL outputs) + (total
drive strength of all SSTL2 outputs) ÷ 2
Single-ended inputs can be in the same LAB row as a differential
channel using the SERDES circuitry; however, IOE input registers are
not available for the single-ended I/Os placed in the same LAB row
as differential I/Os. The same rule for input registers applies for nonSERDES differential inputs placed within the same LAB row as a
SERDES differential channel. The input register must be
implemented within the core logic. The same rule for input registers
applies for non-SERDES differential inputs placed within the same
LAB row as a SERDES differential channel.
5–21
Stratix II Device Handbook, Volume 2
Differential Pin Placement Guidelines
■
Single-ended output pins must be at least one LAB row away from
differential output pins, as shown in Figure 5–20.
Figure 5–20. Single-Ended Output Pin Placement with Respect to Differential I/O Pins
Single-Ended Output Pin
Differential I/O Pin
Single_Ended Input
Single-Ended Outputs
Not Allowed
Row Boundary
DPA Usage Guidelines
The Stratix II and Stratix II GX device have differential receivers and
transmitters on the Row banks of the device. Each receiver has a
dedicated DPA circuit to align the phase of the clock to the data phase of
its associated channel. When a channel or channels of left or right banks
are used in DPA mode, the guidelines listed below must be adhered to.
Fast PLL/DPA Channel Driving Distance
■
Each fast PLL can drive up to 25 contiguous rows in DPA mode in a
single bank (not including the reference clock row). The unbonded
SERDES I/O rows are included in the 25 row calculation. These
channels can be anywhere in the bank, their distance from the PLL is
not relevant, but the channels must be within 25 rows of each other.
5–22
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
■
■
Unused channels can be within the 25 row span, but all used
channels must be in DPA mode from the same fast PLL. Center fast
PLLs can drive two I/O banks simultaneously, up to 50 channels (25
on the upper bank and 25 on the lower bank) as shown in
Figure 5–21.
If one center fast PLL drives DPA channels in the upper and lower
banks, the other center fast PLL cannot be used for DPA.
Figure 5–21. Driving Capabilities of a Center Fast PLL
DPA
DPA
Top Channels Driven
by Center PLL
DPA
DPA
DPA
Ref CLK
Ref Clk
Fast PLL
Center PLL
Used for DPA
Fast PLL
Center PLL
Used for DPA
Ref CLK
Ref Clk
DPA
DPA
DPA
DPA
Bottom Channels
Driven by Center PLL
DPA
Altera Corporation
January 2008
5–23
Stratix II Device Handbook, Volume 2
Differential Pin Placement Guidelines
Using Corner and Center Fast PLLs
■
■
If a differential bank is being driven by two fast PLLs, where the
corner PLL is driving one group and the center fast PLL is driving
another group, there must be at least 1 row of separation between the
two groups of DPA channels (see Figure 5–22). The two groups can
operate at independent frequencies. Not all the channels are bonded
out of the die. Each LAB row is considered a channel, whether or not
it has I/O support.
No separation is necessary if a single fast PLL is driving DPA
channels as well as non-DPA channels as long as the DPA channels
are contiguous.
Figure 5–22. Usage of Corner and Center Fast PLLs Driving DPA Channels in a
Single Bank
Fast PLL
Corner PLL
Used for DPA
Ref CLK
Ref Clk
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Channels Driven
by Corner PLL
Diff I/O
Unused
One Unused
Channel for Buffer
Diff I/O
Diff I/O
Channels Driven
by Center PLL
Diff I/O
Diff I/O
Diff I/O
Ref CLK
Fast PLL
5–24
Stratix II Device Handbook, Volume 2
Ref Clk
Center PLL
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Using Both Center Fast PLLs
■
■
Both center fast PLLs can be used for DPA as long as they drive DPA
channels in their adjacent quadrant only. See Figure 5–23.
Both center fast PLLs cannot be used for DPA if one of the fast PLLs
drives the top and bottom banks, or if they are driving cross banks
(e.g., the lower fast PLL drives the top bank and the top fast PLL
drives the lower bank).
Figure 5–23. Center Fast PLL Usage When Driving DPA Channels
DPA
DPA
Channels Driven by
the Upper Center PLL
DPA
DPA
DPA
Ref CLK
Ref Clk
Fast PLL
Center PLL
Driving Top Bank
Fast PLL
Center PLL
Driving Lower Bank
Ref CLK
Ref Clk
DPA
DPA
DPA
DPA
Channels Driven by
the Lower Center PLL
DPA
Altera Corporation
January 2008
5–25
Stratix II Device Handbook, Volume 2
Differential Pin Placement Guidelines
Non-DPA Differential I/O Usage Guidelines
When a differential channel or channels of left or right banks are used in
non-DPA mode, you must adhere to the guidelines in the following
sections.
Fast PLL/Differential I/O Driving Distance
■
As shown in Figure 5–24, each fast PLL can drive all the channels in
the entire bank.
Figure 5–24. Fast PLL Driving Capability When Driving Non-DPA Differential
Channels
Fast PLL
Corner PLL
Ref CLK
Ref CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Each PLL Can Drive
the Entire Bank
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
5–26
Stratix II Device Handbook, Volume 2
Ref CLK
Ref CLK
Fast PLL
Center PLL
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Using Corner and Center Fast PLLs
■
■
■
The corner and center fast PLLs can be used as long as the channels
driven by separate fast PLLs do not have their transmitter or receiver
channels interleaved. Figure 5–25 shows illegal placement of
differential channels when using corner and center fast PLLs.
If one fast PLL is driving transmitter channels only, and the other fast
PLL drives receiver channels only, the channels driven by those fast
PLLs can overlap each other.
Center fast PLLs can be used for both transmitter and receiver
channels.
Figure 5–25. Illegal Placement of Interlaced Duplex Channels in an I/O Bank
Fast PLL
Corner PLL
Ref CLK
Ref CLK
Duplex Channel Driven
by Center PLL
Duplex Channel Driven
by Corner PLL
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Interleaved Duplex
Channel is Not Allowed
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Board Design
Considerations
f
Altera Corporation
January 2008
Ref CLK
Ref CLK
Fast PLL
Center PLL
This section explains how to achieve the optimal performance from the
Stratix II and Stratix II GX high-speed I/O block and ensure first-time
success in implementing a functional design with optimal signal quality.
For more information on board layout recommendations and I/O pin
terminations, refer to AN 224: High-Speed Board Layout Guidelines.
5–27
Stratix II Device Handbook, Volume 2
Conclusion
To achieve the best performance from the device, pay attention to the
impedances of traces and connectors, differential routing, and
termination techniques.
f
Use this section together with the Stratix II Device Family Data Sheet in
volume 1 of the Stratix II Device Handbook.
The Stratix II and Stratix II GX high-speed module generates signals that
travel over the media at frequencies as high as one Gbps. Board designers
should use the following guidelines:
■
■
■
■
■
■
■
■
■
■
■
■
■
Conclusion
Base board designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
Place external reference resistors as close to receiver input pins as
possible.
Use surface mount components.
Avoid 90° or 45° corners.
Use high-performance connectors such as HMZD or VHDM
connectors for backplane designs. Two suppliers of highperformance connectors are Teradyne Corp (www.teradyne.com)
and Tyco International Ltd. (www.tyco.com).
Design backplane and card traces so that trace impedance matches
the connector’s or the termination’s impedance.
Keep an equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins when the TCCS value increases.
Limit vias, because they cause impedance discontinuities.
Use the common bypass capacitor values such as 0.001, 0.01, and
0.1 μF to decouple the fast PLL power and ground planes. You can
also use 0.0047 μF and 0.047 μF.
Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
Do not route TTL clock signals to areas under or above the
differential signals.
Route signals on adjacent layers orthogonally to each other.
Stratix II and Stratix II GX high-speed differential inputs and outputs,
with their DPA and data realignment circuitry, allow users to build a
robust multi-Gigabit system. The DPA circuitry allows users to
compensate for any timing skews resulting from physical layouts. The
data realignment circuitry allows the devices to align the data packet
between the transmitter and receiver. Together with the on-chip
differential termination, Stratix II and Stratix II GX devices can be used as
a single-chip solution for high-speed applications.
5–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
■
Document
Revision History
AN 224: High-Speed Board Layout Guidelines
DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook
DC & Switching Characteristics chapter in volume 1 of the
Stratix II GX Device Handbook
PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II Handbook
PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Handbook
Selectable I/O standards in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook
Stratix II Device Family Data Sheet in volume 1 of the Stratix II Device
Handbook
Table 5–5 shows the revision history for this chapter.
Table 5–5. Document Revision History (Part 1 of 2)
Date and
Document Version
Changes Made
January 2008, v2.2 Updated Figure 5–2.
May 2007, v2.1
Altera Corporation
January 2008
Summary of Changes
—
Added “Referenced Documents” section.
—
Minor text edits.
—
Added Figure 5–9.
—
Updated “Receiver Data Realignment Circuit”.
—
For the Stratix II GX Device Handbook only:
Formerly chapter 10. The chapter number changed
due to the addition of the Stratix II GX Dynamic
Reconfiguration chapter.
—
Updated entire chapter to include Stratix II GX
information.
—
Changed chapter part number.
—
Fixed two types in “High-Speed Differential I/Os
and Single-Ended I/Os” section
—
5–29
Stratix II Device Handbook, Volume 2
Document Revision History
Table 5–5. Document Revision History (Part 2 of 2)
Date and
Document Version
February 2007
v2.0
Changes Made
Summary of Changes
This chapter changed from High-Speed, SourceSynchronous Differential I/O Interfaces in Stratix II
GX Devices to “High-Speed Differential I/O
Interfaces with DPA in Stratix II and Stratix II GX
Devices”.
—
Added the “Document Revision History” section to
this chapter.
—
Added “and Stratix II GX” after each instance of
“Stratix II”.
—
Updated Figures 10–4, 10–20, 10–22.
—
Updated Note (4) of Figure 10–2.
—
Updated Table 10–1.
—
Updated the following sections:
● “I/O Banks”
● “Differential I/O Termination”
● “Fast PLL ”
● “Differential I/O Bit Position”
● “DPA Usage Guidelines”
● “Fast PLL/DPA Channel Driving Distance”
—
Updated Note (1) of Tables 10–2 and 10–3.
—
Added Note (5) to Figure 10–11.
—
Added Table 10–3.
—
Added Figures 10–14, 10–15, 10–19.
—
Deleted old section called High-Speed Differential
I/Os and Single-Ended I/Os and added a new
“High-Speed Differential I/Os and Single-Ended
I/Os” section.
—
Deleted DPA and Single-Ended I/Os section.
—
Updated title and added Note (1) to Figure 10–12.
—
Added Note (1) to Figure 10–13.
April 2006, v1.2
●
●
—
Updated all the MegaWizard Plug-In Manager
figures to match the Quartus II software GUI.
Updated “Dedicated Source-Synchronous
Circuitry” section, including Table 10–3.
—
February 2006,
v1.1
●
Updated chapter number from 9 to 10.
Updated Figures 10–11 and 10–12.
—
October 2005
v1.0
Added chapter to the Stratix II GX Device
Handbook.
—
●
5–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
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