datasheet for PUMA2E1000 by Apta Group

datasheet for PUMA2E1000 by Apta Group
OM MODULE
32K x 32 EEPR
EEPROM
PUMA 2E1000-70/90/12
HMP Ltd, West Chirton, North Shields, Tyne & Wear NE29 8SE England
Tel. (+44) 191 293 0500 Fax. (+44) 191 259 0997
Issue 4.4 : January 2001
Description
1,048,576 bit CMOS High Speed EEPROM
The PUMA 2E1000 is a 1Mbit High Speed
EEPROM module user configurable as
32Kx32, 64Kx16 or 128Kx8.
Features
Very Fast access times of 70/90/120 ns.
User Configurable as 8 / 16 / 32 bit wide.
Upgradeable footprint.
Operating Power
1760 mW (max).
Standby Power
1320 mW (max).
Package Suitable for Thermal Ladder Applications.
Single byte and Page Write operation.
DATA Polling and Toggle Bit for End of Write Detection.
Hardware and Software Data Protection.
May be screened in accordance with MIL-STD-883.
Available with access times of 70, 90 &
120ns the device has an industry standard
ceramic 66 pin P.G.A footprint.
The device features byte and page write
facility, 10,000 Write Erase cycle capability
and data retention time of 10 years.
The device may be screened in accordance
with MIL-STD-883
Pin Definition
Block Diagram
1
D8
A0~A14
OE
WE4
WE3
WE2
WE1
32K x 8
EEPROM
32K x 8
EEPROM
32K x 8
EEPROM
32K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
12
WE2
23
34
45
56
D15
D24
VCC
D31
2
13
24
35
46
57
D9
CS2
D14
D25
CS4
D30
3
14
25
36
47
58
D10
GND
D13
D26
WE4
D29
37
4
15
26
A13
D11
D12
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0-31
OE
NC
GND
59
D28
VIEW
FROM
ABOVE
38
49
60
A7
A3
A0
39
50
61
A1
5
16
27
A14
A10
OE
6
17
28
NC
A11
NC
NC
A4
7
18
29
40
51
62
NC
A12
WE1
A8
A5
A2
8
19
30
41
52
63
NC
VCC
D7
A9
WE3
D23
9
20
31
42
53
64
D0
CS1
D6
D16
CS3
D22
10
21
32
43
54
65
D1
NC
D5
D17
GND
D21
11
22
33
44
55
66
D2
D3
D4
D18
D19
D20
Pin Functions
A0-14
CS1-4
WE1-4
VCC
48
D27
A6
Data Inputs/Outputs
Output Enable
No Connect
Ground
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Temperature Under Bias
Storage Temperature
All input voltages (including N.C. pins) with Respect to GND
All output voltages with respect to GND
Voltage on OE and A9 with Respect to GND
TBIAS
TSTG
VT
VOUT
VOEA
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to VCC +0.6
-0.6 to +13.5
°C
°C
V
V
V
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated below is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
min
typ
max
VCC
VIL
VIH
TA
TAI
TAM
4.5
-0.1
2.0
0
-40
-55
5.0
-
5.5
0.8
VCC+1
70
85
125
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
V
V
V
°
C
°
C (2E1000I)
°
C (2E1000M, MB)
DC Electrical Characteristics (VCC=5.0V±10%, TA=-55 to +125°C)
Parameter
Symbol Test Condition
min
typ
max
Unit
Input Leakage Current Address, OE
CS1~4, WE1~4
Output Leakage Current
ILI1
ILI2
ILO
0V ≤ VIN≤ VCC+1V
As above.
CS1~4=VIH, VI/O=GND to VCC
-
-
40
10
40
µA
µA
µA
Operating Supply Current
Standby Supply Current
ICC32
ISB1
f=5MHz, II/O=0mA
2.0V≤CS1~4≤VCC+1V
-
-
320
240
mA
mA
Output Low Voltage
Output High Voltage
VOL
VOH
IOL = 6.0mA
IOH = -4.0mA
2.4
-
0.45
-
V
V
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Input Capacitance:
I/O Capacitance:
Symbol
CIN
CI/O
Test Condition
typ
max
Unit
VIN =0V
VI/O=0V, 8 bit mode
26
42
34
58
pF
pF
AC Test Conditions
Output Test Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* VCC=5V±10%
I/O Pin
645Ω
1.76V
100pF
2
PUMA 2E1000-70/90/12
ISSUE 4.4 : January 2001
AC READ CHARACTERISTICS
Read Cycle
Parameter
Symbol
Read Cycle Time
Address to Output Delay
CS1~4 to Output Delay(1)
OE to Output Delay (2)
CS1~4 or OE to Output Float (3,4)
Output Hold from OE, CS1~4 or
Address, (whichever occured first)
tRC
tACC
tCS
tOE
tDF
tOH
-70
min max
0
0
0
70
70
70
40
40
-
-90
min max
0
0
0
90
90
90
45
45
-
-12
min max
0
0
0
Unit
120
120
120
50
50
-
ns
ns
ns
ns
ns
ns
Notes: (1) CS1~4 may be delayed up to tACC - tCS after the address transition without impact on tACC.
(2) OE may be delayed up to tCS - tOE after the falling edge of CS1~4 without impact on tCS or by tACC - tOE after an
address change without impact on tACC.
(3) tDF is specified from OE or CS1~4 whichever occurs first (CL = 5pF).
(4) This parameter is only sampled and is not 100% tested.
Write Cycle
Parameter
Symbol
min
typ
max
Unit
Address, OE Set-up Time
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE1~4 or CS1~4)
Data Set-up Time
Data, OE Hold Time
Time to Data Valid
tAS, tOES
tAH
tCS
tCH
tWP
tDS
tDH, tOEH
tDV
0
50
0
0
100
50
0
NR(1)
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
min
typ
max
Unit
tWC
tAS
tAH
tDS
tDH
tWP
tBLC
tWPH
0
50
50
0
100
50
5
-
10
150
-
ms
ns
ns
ns
ns
ns
µs
ns
min
0
0
typ
-
max
-
0
-
-
Note: (1) NR = No Restriction
Page Mode Write Cycle
Parameter
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte/Word Load Cycle Time
Write Pulse Width High
See notes on page 6, Mode Write Waveform.
DATA Polling Characteristics
Parameter
Data Hold Time
OE Hold Time
OE to Output Delay(1)
Write Recovery Time
Symbol
tDH
tOEH
tOE
tWR
Note : (1) See AC Read Characteristics.
3
Unit
ns
ns
ns
ns
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
Toggle Bit Characteristics (1,2,3,4)
Parameter
Data Hold Time
OE Hold Time
OE to Output Delay (1)
OE High Pulse
Write Recovery Time
Symbol
tDH
tOEH
tOE
tOEHP
tWR
min
10
10
typ
-
max
-
150
0
-
-
Note : (1) See AC Read Characteristics.
(2) Toggling either OE or CS1~4, or both OE and CS1~4 will operate toggle bit.
(3) Beginning and ending state of D6 will vary.
(4) Any address location may be used but the address should not vary.
Read Cycle Timing Waveform (1,2,3,4)
Address Valid
Address
tRC
CS1~4
tCS
tOE
tDF
OE
tOH
tACC
Output
Valid
HIGH Z
DATA OUT
AC Write Waveform - WE1~4 Controlled
t WC
Address
tAH
t AS
tWPH
tWP
WE1~4
t CS
t CH
CS1~4
tOES
OE
t OEH
t DV
DATA IN
High-Z
Data Valid
t DS
4
t DH
Unit
ns
ns
ns
ns
ns
PUMA 2E1000-70/90/12
ISSUE 4.4 : January 2001
AC Write Waveform - CS1~4 Controlled
t WC
Address
t AS
t CS
t AH
t CH
WE1~4
t WP
CS1~4
t WPH
t OES
OE
t OEH
t DV
High-Z
DATA IN
Data Valid
t DS
Page Mode Write Waveform
t DH
(1,2)
OE
CS1~4
tWPH
tWP
tBLC
WE1~4
tAS
A0-A5
tAH
tDH
Valid
Add
tDS
Data
Valid
Data
Byte 0
Byte 1
Byte 2
Byte 3
Byte 62
B
Note: (1) A6 through A14 must specify the page address during each high to low transition of WE1~4 (or CS1~4).
(2) OE must be high only when WE1~4 and CS1~4 are both low.
5
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
DATA Polling Waveform (1)
WE1~4
CS1~4
tOEH
OE
tDH
tOE
High Z
D7,D15,
D23,D31
An
A0-A14
An
An
An
Toggle Bit Waveform (1,2,3,4)
WE1~4
CS1~4
tOEH
tOEHP
OE
tOE
tDH
HIGH-Z
HIGH-Z
D6,D14,
D22,D30
HIGH-Z
Software Protected Write Waveform (1,2)
OE
CS1~4
tWP
t BLC
WE1~4
tAS
tWPH
tAH
A0~A5
BYTE ADDRESS
05555
02AAA
05555
A6~A14
PAGE ADDRESS
tDS
Data
AA
tDH
55
A0
Byte 0
Byte 62
B
Notes: (1) A6 through A14 must specify the page address during each high to low transition of WE1~4 (or CS1~4).
(2) OE must be high only when WE1~4 and CS1~4 are both low.
6
PUMA 2E1000-70/90/12
ISSUE 4.4 : January 2001
Chip Erase Waveform
VIH
CS1~4
VIL
VH
OE
VIL
tS
tH
VIH
tW
WE1~4
VIL
tS = tH = 5µs (min)
tW = 10 ms (min)
7
VH = 12V ± 0.5V
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
Device Operation
Where references are made to byte/word operations, the user will control the memory configuration of 8, 16, or
32 bits wide using CS1~4.
Read
The PUMA 2E1000 read operations are initiated by both Output Enable and Chip Select(s) LOW, while Write
Enable(s) is HIGH. The read operation is terminated by either Chip Select(s) or Output Enable returning HIGH.
This dual-line control architecture eliminates bus contention in a system environment. The data bus will be in a high
impendence state when either Output Enable or Chip Select is HIGH.
Write
Write operations are initiated when both Chip Select(s) and Write Enable(s) are LOW and Output Enable is HIGH.
The PUMA 2E1000 supports both a Chip Select(s) and Write Enable(s) controlled write cycle. That is, the address
is latched by the falling edge of either Chip Select(s) or Write Enable(s), whichever occurs last. Similarly, the data
is latched internally by the rising edge of either Chip Select(s) or Write Enable(s), whichever occurs first. A byte/
word write operation, once initiated, will automatically continue to completion, within 10 ms max.
Page Mode Write
The page write feature of the PUMA 2E1000 allows the entire memory to be written in typically 5.12 seconds. Page
Write allows 1 to 64 bytes/words of data to be written into the device during a single programming cycle. The host
can fetch data from another location within the system during a page write operation (change the source address),
but the page address (A6 through A14) for each subsequent valid write cycle to the part, during this operation must
be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte/word write cycle, the
host can write up to 63 bytes/words in the same manner as the first byte/word written. Each successive byte/word
load cycle, started by the Write Enable(s) HIGH to LOW transition, must begin within 150 µs of the falling edge of
the preceding Write Enable(s). If a subsequent Write Enable(s) HIGH to LOW transition is not detected within 150
µs, the internal automatic programming cycle will commence.
The A0 to A5 inputs are used to specify which bytes/words within the page are to be written. The bytes/words may
be loaded in any order and altered within the same load period. Only bytes/words which are specified for writing
will be written; unnecessary cycling of other bytes/words within the page does not occur.
DATA Polling
The PUMA 2E1000 features DATA Polling to indicate if the write cycle is completed. During the internal
programming cycle, any attempt to read the last byte/word written will produce the complement of that data on D7.
Once the programming is complete, D7 will refect the true data. Note: If the the PUMA 2E1000 is in a protected
state and an illegal write operation is attempted DATA Polling will not operate. DATA Polling may begin at any time
during the write cycle.
TOGGLE bit
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 toggling between 1 and 0. Once a write is complete,
this toggling will stop and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.
8
PUMA 2E1000-70/90/12
ISSUE 4.4 : January 2001
Hardware Data Protection
The PUMA 2E1000 provides hardware features to protect non-volatile data from inadvertent writes.
•
•
VCC Sense - If VCC is below 3.8V (typical) the write function is inhibited.
VCC Power-on-Delay - Once VCC has reached 3.8V the device will automatically time out 5ms (typical) before
allowing a write.
• Write Inhibit - Holding any one of OE Low, CS High, WE High inhibits write cycles
• Noise Filter - Pulses of less than 15ns (typical) on the WE or CS inputs will not initiate a write cycle.
Software Data Protection
The PUMA 2E1000 can be automatically protected during power-up and power-down without the need for external
circuits by employing the software data protect feature. The internal software data protection circuit is enabled after
the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of
the device unless the reset command is issued.
Once the software protection is enabled, the PUMA 2E1000 is also protected against inadvertent and accidental
writes in that, the software algorithm must be issued prior to writing additional data to the device.
Operating Modes
The table below shows the logic inputs required to control the operation of the PUMA 2E1000.
CS1~4 OE WE1~4 OUTPUTS
MODE
Read
Write
Standby/Write inhibit
Write Inhibit
Output Disable
Chip Erase (1)
0
0
1
X
0
1
X
1
0
X
1
Data Out
Data in
High-Z
X
X
0
X
X
1
X
High-Z
0
1
0
High-Z
0 = VIL : 1 = VIH : X = VIH or VIL
Notes : (1) OE must be 12.0V ± 0.5V
Device Indentification
An extra 64 bytes of EEPROM memory are avaliable to the user for device identification, accessed by placing
12V±0.5V on A9 and using locations 7FC0H to 7FFFH. These locations can be used during the initial programming
of each EEPROM to record data such as issue number and release date, and subsequent reprogramming can
change these locations to record the alterations performed.
Chip Erase
All of the memory locations on the PUMA 2E1000 can be erased in 10 ms by placing 12.0V±0.5V onto OE and
controlling WE1~4 and CS1~4 to follow the Chip Erase timing characteristics. This function will operate even if the
module is in Software Data Protection Mode as explained later.
9
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
Software Data Protection
Software controlled data protection, once enabled by the user, necessitates the use of a software algorithm before
any Write can be performed. To enable this feature a special sequence of 3 Writes to 3 specific addresses must
be performed, and must be reused for each subsequent Write cycle. Once set the data protection remains
operational until it is disabled by using a second algorithm; power transitions will not reset this feature.
Note that the PUMA 2E1000 is supplied with the Software data Protection feature disabled.
The algorithms to enable and disable the protection are shown below:
SDP Enable
SDP Disable
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
WRITES
ENABLED (2)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS (4)
LOAD LAST BYTE/
WORD TO
LAST ADDRESS
LOAD DATA 55
TO
ADDRESS2AAA
ENTER DATA
PROTECT
STATE
LOAD DATA 20
TO
ADDRESS 5555
Once initiated, the enable sequence of
write operations should not be interrupted
Notes :
EXIT DATA
PROTECT
STATE (3)
LOAD DATA XX
TO
ANY ADDRESS (4)
(1) Data D7 - D0 (hex); Address A14 - A0 (hex).
(2) Write Protect Mode will be activated at end of
Write even if no other data is loaded.
LOAD LAST BYTE/
WORD TO
LAST ADDRESS
(3) Write protect state will be disabled at end of
write period even if no other data is loaded.
(4) 1 to 64 bytes/words of data can be loaded.
Note: Load Data above represents 8 bit mode. For 16 or 32 bit mode, place the load data in the 2 bytes or
all 4 bytes on the data lines, respectively. Eg/ 8 bit load data = 55HEX, 16 bit load data = 5555HEX.
All software write commands must obey the Page Write timing specifications.
The process of disabling the Data Protection mode is very similar to that described for enable, except 6 bytes/words
must be loaded to specific locations in the EEPROM as shown.
Note here the use of the word 'load' to describe enabling and disabling the protection modes in preference to 'write'.
Although it may seem that if the Write command sequence is performed to enable protection then the three bytes/
words at those addresses will be overwritten with AA,55,A0, this is not the case.
10
PUMA 2E1000-70/90/12
ISSUE 4.4 : January 2001
Package Details Dimensions in mm (inches).
27.69 (1.090) Sq. Max.
4.83 (0.190)
2.54 (0.100) typ.
4.32 (0.170)
0.53 (0.021)
0.38 (0.015)
1.40 (0.055)
1.14 (0.045)
1.27 (0.050)
0.64 (0.025)
8.13 (0.320) max
1.52 (0.060)
1.02 (0.040)
Military Screening Procedure
Module Screening Flow for high reliability product is in accordance with MIL-STD-883 method 5004 Level B and
is detailed below:
MB MODULE SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
External visual
Temperature cycle
2017 Condition B (or manufacturers equivalent)
1010 Condition C (10 Cycles,-65°C to +150°C)
100%
100%
Pre Burn-in Electrical
Burn-In
Per Applicable device Specifications at TA = +25°C (optional)
Method 1015, Condition D, TA = +125°C
100%
100%
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective Allowable (PDA)
Calculated at Post Burn-in at TA=+25°C
10%
Quality Conformance
Per applicable Device Specification
Sample
External Visual
2009 Per HMP or customer specification
Burn-In
11
ISSUE 4.4 : January 2001
PUMA 2E1000-70/90/12
Ordering Information
PUMA 2E1000MB-70
Speed
70
90
12
= 70 ns
= 90 ns
= 120 ns
Temp. range/screening
Blank
I
M
MB
= Commercial Temp.
= Industrial Temp.
= Military Temp.
= Screened in accordance with
MIL-STD-883
Memory Type
E1000 = EEPROM (Configurable as
32Kx32, 64Kx16 or 128Kx8)
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantability or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of a
company director.
12
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement