datasheet for MR36V02G54B by LAPIS Semiconductor

datasheet for MR36V02G54B by LAPIS Semiconductor
FEDR36V02G54B-002-01
Issue Date: Oct. 01, 2008
MR36V02G54B
64M–Word × 32–Bit Page Mode
P2ROM
PIN CONFIGURATION (TOP VIEW)
FEATURES
· 64Mx32 or 128Mx16-bit
electrically switchable configuration
· Page size of 8-word x 32-Bit or 16-word x 16-Bit
· 3.0 V to 3.6 V power supply
· Random Access time
105 ns MAX
· Page Access time
25 ns MAX
· Operating current 100 mA MAX
· Standby current
50 mA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
·70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits
over the other non-volatile technologies, which include the
following;
· Short lead time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and OTP
that require additional programming and handling costs, the
P2ROM already has the code loaded at the factory with
minimal effect on the production throughput. The cost is
included in the unit price.
· Custom Marking is available at no additional charge.
Vcc
1
70 D28
Vss
2
69 D20
A24
3
68 D12
A23
4
67 D4
A22
5
66 D29
A21
6
65 D21
A20
7
64 D13
A19
8
63 D5
A18
9
62 D30
A17
10
61 D22
A16
11
60 D14
A15
12
59 D6
A14
13
58 D31
A25
14
57 D23
CE#
15
56 D15
A13
16
55 D7
A12
17
54 OE#
A11
18
53 A_1
Vcc
19
52 A0
Vss
20
51 Vcc
A1
21
50 WORD#
A2
22
49 Vss
A3
23
48 D0
A4
24
47 D8
A5
25
46 D16
A6
26
45 D24
A7
27
44 D1
A8
28
43 D9
A9
29
42 D17
A10
30
41 D25
Vss
31
40 Vcc
D27
32
39 D2
D19
33
38 D10
D11
34
37 D18
D3
35
36 D26
70-pin SSOP
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FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
BLOCK DIAGRAM
A-1
Column Decoder
Address Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
Row Decoder
× 16/× 32 Switch
CE#
OE#
CE
OE
WORD#
Memory Cell Matrix
64M × 32-Bit or 128M × 16-Bit
Multiplexer & Sense Amp.
Output Buffer
D0 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30
D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31
In16-bit output mode, these pins
are placed in a high-Z state
PIN DESCRIPTIONS
Pin name
A0 to A25
A–1
D0 to D31
CE#
OE#
WORD#
VCC
VSS
Functions
Address inputs
Address -1 input
Data outputs
Chip enable input
Output enable input
Word -Byte select input
Power supply voltage
Ground
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FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
FUNCTION TABLE
Mode
CE#
OE#
WORD#
Read (32-Bit)
Read (16Bit)
Output
disable
L
L
L
L
L
H
H
∗
H
L
H
L
H
L
Standby
VCC
D0 to D15
D16 to D31
DOUT
DOUT
3.3 V
Hi–Z
A-1
∗
L/H
Hi–Z
∗
Hi–Z
∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Output short circuit current
Power dissipation per package
Symbol
Ta
Tstg
VI
VO
VCC
Ios
PD
Condition
—
relative to VSS
—
Ta=25°C
Value
0 to 70
–55 to 125
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–0.5 to 4.6
10
1.0
Unit
°C
°C
V
V
V
mA
W
RECOMMENDED OPERATING CONDITIONS
Parameter
VCC power supply voltage
Input “H” level
Input “L” level
Symbol
VCC
VIH
VIL
Condition
VCC = 3.0 to 3.6 V
Min.
3.0
2.2
–0.5∗∗
Typ.
—
—
—
(Ta = 0 to 70°C)
Max.
Unit
3.6
V
VCC+0.5∗
V
0.6
V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
Parameter
Input(except Word#)
Output
Symbol
CIN1
COUT
Condition
VI = 0 V
VO = 0 V
Min.
—
—
(VCC = 3.3 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
20
pF
—
20
pF
3/9
FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input leakage current
ILI
VI = 0 to VCC
—
—
20
µA
Output leakage current
ILO
VO = 0 to VCC
—
—
20
µA
VCC power supply current
(Standby)
VCC power supply current
(Read)
ICCSC
CE# =
Add.=VCC
VCC=3.6V
—
—
50
mA
ICCA1
CE# = VIL
OE# = VIH
tc = 200 ns
—
—
100
mA
—
2.2
—
Input “L” level
VIL
—
–0.5∗∗
—
VCC+0.5
∗
0.6
Output “H” level
VOH
IOH = –2 mA
2.4
—
—
V
Output “L” level
VOL
IOL = 2 mA
—
—
0.4
V
Input “H” level
VIH
V
V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Address cycle time
tC
Address access time
Address skew time
CE Address skew time
Page cycle time
Page access time
CE# access time
OE# access time
tACC
tASK
TCSK
tPC
tPAC
tCE
tOE
tCHZ
tOHZ
tOH
Output disable time
Output hold time
Condition
Min.
Max.
Unit
Address access
CE# access
—
—
—
—
CE# = OE# = VIL
OE# = VIL
CE# = VIL
OE# = VIL
CE# = VIL
CE# = OE# = VIL
105
105
—
—
—
25
—
—
—
0
0
0
—
—
105
10
10
—
25
105
25
20
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measurement conditions
Input signal level-----------------------------------Input timing reference level ---------------------Output load -----------------------------------------Output timing reference level--------------------
0 V/3 V
1/2Vcc
50 pF
1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
4/9
FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
tC
tC
Address
tOH
tASK
tCE
tACC
CE#
tCHZ
tOE
tOH
OE#
tOHZ
tACC
Dout
Valid Data
Valid Data
Hi-Z
Hi-Z
Page Access Mode Read Cycle
tC
A3 to A25
tPC
tPC
A-1 to A2 (X16 mode)
A0 to A2 (X32 mode)
tOH
tCE
CE#
tCSK
tOE
tCHZ
OE#
tACC
tPAC
tPAC
tOHZ
Dout
Hi-Z
Hi-Z
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FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
Power ON Characteristics
Parameter
VCC set up time
Power on sequence hold time
Power off hold time
Symbol
tvset
tposh
tvpoff
Condition
—
—
—
Min.
5
1
1
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Max.
Unit
270
us
—
ms
—
ms
TIMING CHART (POWER ON)
Don’t power-on
Unavailable
tvpoff
VCC
LEVEL = 3.0 V
tposh
LEVEL=VSS
VCC
0.1V
tvset
Note: A start-up delay of 1ms is required after power-on.
If you power-off VCC ,you must wait 1ms to power-on.
CE# must be HIGH while VCC power on sequence.
6/9
FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
REVISION HISTORY
Document
No.
Page
Date
Previous
Edition
Current
Edition
FEDR36V02G54B-02-01
Jul. 29,2007
–
–
Final edition 1
FEDR36V02G54B-002-01
Oct. 1,2008
–
–
Changed company logo and name
to OKI SEMICONDUCTOR
Description
8/9
FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
NOTICE
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