datasheet for VL495T2863E

datasheet for VL495T2863E
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
General Information
1GB 128Mx72 DDR2 SDRAM VLP ECC REGISTERED Mini-DIMM 244-PIN
Description
The VL495T2863E is a 128Mx72 DDR2 SDRAM high density Mini-DIMM. This memory module is single rank,
consists of nine CMOS 128Mx8 bits with 8 banks DDR2 synchronous DRAMs in BGA packages, a 25-bit registered
buffers in BGA package, a zero delay PLL clock in BGA package, and a 2K EEPROM in an 8-pin TSSOP package.
This module is a 244-pin mini dual in-line memory module and is intended for mounting into an edge connector
socket. Decoupling capacitors are mounted on the printed circuit board for each DDR2 SDRAM.
Features
Pin Description
244-pin, mini dual in-line memory module (Mini-DIMM)
JEDEC pin out
Supports ECC error detection and correction
Fast data transfer rates: PC2-5300, PC2-4200, PC2-3200
VDD = VDDQ = 1.8V +/-0.1V
JEDEC standard 1.8V (SSTL_18 compatible)
VDDSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS# ) option
Differential clock inputs (CK, CK#)
Four-bit pre-fetch architecture
DLL aligns DQ and DQS transition with CK
Nominal and dynamic on-die termination (ODT)
Programmable CAS# latency:
5 (DDR2-667), 4 (DDR2-533), 3 (DDR2-400)
Write latency = Read latency - 1 tCK
Eight internal component banks for concurrent operation
Programmable burst; length (4, 8)
Adjustable data-output drive strength
Auto & self refresh, (8K/64ms refresh)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 18.29mm (0.720”), double sided component
o
o
Operating temperature (TOPER): - Commercial (0 C <= Tc <= 95 C)
o
o
- Industrial (-40 C <= Tc <= 95 C)
Notes: Double refresh rate is required when 85oC < TOPER <= 95oC.
TOPER is DRAM case temperature (Tc)
Order Information:
VL495T2863E - E6 S X - X
Pin Name
Function
A0~A13
Address Inputs
A10/AP
Address Input/ Autoprecharge
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS8
Data Strobes
DQS0#~DQS8#
Data Strobes Complement
CB0~CB7
Check Bits
DM0~DM8
Data Masks
CK0, CK0#
Clock Input
ODT0
On-die Termination Control
CKE0
Clock Enables
CS0#
Chip Selects
RAS#
Row Address Strobes
CAS#
Column Address Strobes
WE#
Write Enable
RESET#
Reset Input
VDD
Voltage Supply
VSS
Ground
SA0~SA2
SPD Address
SDA
SPD Data Input/Output
OPERATING TEMPERATURE
None: Commercial
S1:
Industrial screening
SCL
SPD Clock Input
DRAM DIE (Option)
VDDSPD
SPD Voltage Supply
VREF
SSTL_18 Reference Voltage
NC
No Connect
DRAM MANUFACTURER
S - SAMSUNG
MODULE SPEED
E6: PC2-5300 @ CL5
D5: PC2-4200 @ CL4
CC: PC2-3200 @ CL3
VL: Lead-free/RoHS
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1
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
Pin Configuration
244-PIN DDR2 Mini-DIMM FRONT SIDE
244-PIN DDR2 Mini-DIMM BACK SIDE
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
32
VSS
63
VDDQ
93
VSS
123
VSS
154
DQ28
185
A3
215
DM5
2
VSS
33
DQ24
64
A2
94
DQS5#
124
DQ4
155
DQ29
186
A1
216
NC
3
DQ0
34
DQ25
65
VDD
95
DQS5
125
DQ5
156
VSS
187
VDD
217
VSS
4
DQ1
35
VSS
96
VSS
126
VSS
157
DM3
218
DQ46
5
VSS
36
DQS3#
66
VSS
97
DQ42
127
DM0
158
NC
188
CK0
219
DQ47
6
DQS0#
37
DQS3
67
VSS
98
DQ43
128
NC
159
VSS
189
CK0#
220
VSS
7
DQS0
38
VSS
68
NC
99
VSS
129
VSS
160
DQ30
190
VDD
221
DQ52
8
VSS
39
DQ26
69
VDD
100
DQ48
130
DQ6
161
DQ31
191
A0
222
DQ53
9
DQ2
40
DQ27
70
A10/AP
101
DQ49
131
DQ7
162
VSS
192
BA1
223
VSS
10
DQ3
41
VSS
71
BA0
102
VSS
132
VSS
163
CB4
193
VDD
224
NC
11
VSS
42
CB0
72
VDD
103
SA2
133
DQ12
164
CB5
194
RAS#
225
NC
12
DQ8
43
CB1
73
WE#
104
NC
134
DQ13
165
VSS
195
VDDQ
226
VSS
13
DQ9
44
VSS
74
VDDQ
105
VSS
135
VSS
166
DM8
196
CS0#
227
DM6
14
VSS
45
DQS8#
75
CAS#
106
DQS6#
136
DM1
167
NC
197
VDDQ
228
NC
15
DQS1#
46
DQS8
76
VDDQ
107
DQS6
137
NC
168
VSS
198
ODT0
229
VSS
16
DQS1
47
VSS
77
CS1#*
108
VSS
138
VSS
169
CB6
199
A13
230
DQ54
17
VSS
48
CB2
78
OTD1*
109
DQ50
139
NC
170
CB7
200
VDD
231
DQ55
18
RESET#
49
CB3
79
VDDQ
110
DQ51
140
NC
171
VSS
201
NC
232
VSS
19
NC
50
VSS
80
NC
111
VSS
141
VSS
172
NC
202
VSS
233
DQ60
20
VSS
51
NC
81
VSS
112
DQ56
142
DQ14
173
VDDQ
203
DQ36
234
DQ61
21
DQ10
52
VDDQ
82
DQ32
113
DQ57
143
DQ15
174
CKE1*
204
DQ37
235
VSS
22
DQ11
53
CKE0
83
DQ33
114
VSS
144
VSS
175
VDD
205
VSS
236
DM7
23
VSS
54
VDD
84
VSS
115
DQS7#
145
DQ20
176
A15 *
206
DM4
237
NC
24
DQ16
55
BA2
85
DQS4#
116
DQS7
146
DQ21
177
A14 *
207
NC
238
VSS
25
DQ17
56
NC
86
DQS4
117
VSS
147
VSS
178
VDDQ
208
VSS
239
DQ62
26
VSS
57
VDDQ
87
VSS
118
DQ58
148
DM2
179
A12
209
DQ38
240
DQ63
27
DQS2#
58
A11
88
DQ34
119
DQ59
149
NC
180
A9
210
DQ39
241
VSS
28
DQS2
59
A7
89
DQ35
120
VSS
150
VSS
181
VDD
211
VSS
242
SDA
29
VSS
60
VDD
90
VSS
121
SA0
151
DQ22
182
A8
212
DQ44
243
SCL
30
DQ18
61
A5
91
DQ40
122
SA1
152
DQ23
183
A6
213
DQ45
244
VDDSPD
31
DQ19
62
A4
92
DQ41
153
VSS
184
VDDQ
214
VSS
KEY
KEY
*: These pins are not used in this module.
RESET# (Pin 18) is connected to both OE of the PLL and RESET# of the register
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2
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
Function Block Diagram
RCS0#
DQS4
DQS4#
DM4
DQS0
DQS0#
DM0
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
D5
DQS6
DQS6#
DM6
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D4
DQS5
DQS5#
DM5
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D6
DQS7
DQS7#
DM7
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D7
DQS8
DQS8#
DM8
CK0
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
P
L
L
CK0#
RESET#
D8
PCK0, PCK4-PCK6, PCK9
-> CK: SDRAMs D0-D8
PCK0#, PCK4#-PCK6#, PCK9# -> CK#: SDRAMs D0-D8
PCK7 -> CK: Registers
PCK7# -> CK#: Registers
OE#
Serial PD
SCL
WP
Vss
A0
A1
A2
SDA
SA0 SA1 SA2
22 ohm +/-5%
CS0#
A0-A13
BA0-BA2
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
1:1
R
E
G
I
S
T
E
R
RCS0# -> CS0#: SDRAMs D0-D8
RA0-RA13 -> A0-A13: SDRAMs D0-D8
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D8
RRAS# -> RAS#: SDRAMs D0-D8
RCAS# -> CAS#: SDRAMs D0-D8
RWE# -> WE#: SDRAMs D0-D8
RCKE0 -> CKE0: SDRAMs D0-D8
RODT0 -> ODT0: SDRAMs D0-D8
VDDSPD
VDD/ VDDQ
Serial PD
D0-D8
VREF
D0-D8
VSS
D0-D8
RST #
PCK7
PCK7#
Notes:
1. Unless otherw ise noted, resistor values are 22 ohms +/-5%
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3
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
Absolute Maximum Ratings
Symbol
MIN
MAX
Unit
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
VDD
VIN, VOUT
TSTG
IL
IOZ
IVREF
Parameter
Storage temperature
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
V
0
-55
100
Address, BA,
RAS#, CAS#, WE#
-5
5
uA
CS#, CKE, ODT
-5
5
uA
CK, CK#
-250
250
uA
DM
-5
5
uA
-5
5
uA
-18
18
uA
DQ, DQS, DQS#
VREF supply leakage current; VREF = Valid VREF level
C
DC Operating Conditions
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
1.7
1.8
1.9
V
1
VDDQ
I/O supply voltage
1.7
1.8
1.9
V
4
VDDL
VDDL supply voltage
1.7
1.8
1.9
V
4
VREF
I/O reference voltage
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
VREF-0.04
VREF
VREF+0.04
V
3
VDD
VTT
Parameter
I/O termination voltage
Notes:
1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This
measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and
must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
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4
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
Operating Temperature Condition
Symbol
TOPER
Parameter
Operating temperature
Rating
Commercial
Units
0 to +95
Industrial
0
C
-40 to +95
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At -40 to +85 C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
o
o
85 C < TOPER <= 95 C.
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
VIH(DC)
Input High (Logic 1) Voltage (DDR2-400/533/667)
VREF + 0.125
VDDQ + 0.300
V
VIL(DC)
Input Low (Logic 0) Voltage (DDR2-400/533/667)
-0.300
VREF - 0.125
V
Min
Max
Unit
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
VIH(AC)
Input High (Logic 1) Voltage (DDR2-533/400)
VREF + 0.250
-
V
VIL(AC)
Input Low (Logic 0) Voltage (DDR2-533/400)
-
VREF - 0.250
V
VIH(AC)
Input High (Logic 1) Voltage (DDR2-667)
VREF + 0.200
-
V
VIL(AC)
Input Low (Logic 0) Voltage (DDR2-667)
-
VREF - 0.200
V
Input/Output
Capacitance
0
TA=25 C, f=100MHz
Parameter
Symbol
E6
(DDR2-667)
D5
(DDR2-553)
CC
(DDR2-400)
Min
Max
Min
Max
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
6.5
7.5
6.5
7.5
6.5
7.5
pF
Input capacitance (CKE0, ODT0, CS0#)
CIN2
6.5
7.5
6.5
7.5
6.5
7.5
pF
Input capacitance (CK0, CK0#)
CIN3
6
7
6
7
6
7
pF
Input/Output capacitance (DQ, DQS, DQS#, DM, CB)
CIO
6.5
7.5
6.5
8
6.5
8
pF
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5
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
IDD Specification
Condition
Symbol
E6
(DDR2-667)
D5
(DDR2-533)
CC
(DDR2-400)
Unit
IDD0*
1065
1020
675
mA
IDD1*
1155
1110
1065
mA
IDD2P**
435
435
435
mA
IDD2Q**
660
660
615
mA
IDD2N**
705
705
660
mA
660
615
615
mA
462
462
462
mA
IDD3N**
840
840
795
mA
IDD4W*
1470
1380
1245
mA
IDD4R*
1560
1470
1335
mA
IDD5**
1650
1650
1605
mA
IDD6**
135
135
135
mA
IDD7*
2460
2460
2325
mA
Operating one bank active-pre-charge current;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
Operating one bank active-read-pre-charge current;
IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0; t CK= tCK(IDD); tRC= tRC(IDD);
tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDD4W
Pre-charge power-down current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Pre-charge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Pre-charge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; Other control and address
bus inputs are STABLE; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
IDD3P**
Active standby current;
All banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst write current;
All banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL =
CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W.
Burst refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH;
CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING.
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL =
tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD =
1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs
are SWITCHING.
Notes:
IDD specification is based on Samsung D-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
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6
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
E6
(DDR2-667)
D5
(DDR2-533)
CC
(DDR2-400)
Max
Min
Max
Min
Max
Min
Unit
Clock Timing
CL5
tCK(5)
3,000
8,000
-
-
-
-
ps
CL4
tCK(4)
3,750
8,000
3,750
8,000
-
-
ps
CL3
tCK(3)
5000
8000
5000
8000
5000
8000
ps
CK high-level width
tCH(avg)
0.48
0.52
0.48
0.52
0.45
0.55
tCK
CK low-level width
tCL(avg)
0.48
0.52
0.48
0.52
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH, tCL)
-
MIN
(tCH, tCL)
-
MIN
(tCH, tCL)
-
ps
Clock jitter
tJIT
-125
125
-
-
-
-
ps
DQ output access time from CK/CK#
tAC
-450
+450
-500
500
-600
600
ps
Data-out high impedance window from CK/CK#
tHZ
-
tAC(MAX)
-
tAC(MAX)
-
tAC(MAX)
ps
Data-out low impedance window from CK/CK#
tLZ
tAC(MiN)
tAC(MAX)
tAC(MiN)
tAC(MAX)
tAC(MiN)
tAC(MAX)
ps
DQ and DM input setup time relative to DQS
tDS
100
-
100
-
150
-
ps
DQ and DM input hold time relative to DQS
tDH
175
-
225
-
275
-
ps
DQ and DM input pulse width ( for each input)
tDIPW
0.35
-
0.35
-
0.35
-
tCK
Data hold skew factor
tQHS
-
340
-
400
-
450
ps
DQ-DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP - tQHS
-
tHP - tQHS
-
tHP - tQHS
-
ps
Data valid output window (DVW)
tDVW
tQH-tDQSQ
-
tQH-tDQSQ
-
tQH-tDQSQ
-
ns
DQS input high pulse width
tDQSH
0.35
-
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
0.35
-
tCK
DQS output access time from CK/CK#
tDQSCK
-400
+400
-450
+450
-500
+500
ps
DQS failing edge to CK rising-setup time
tDSS
0.2
-
0.2
-
0.2
-
tCK
DQS failing edge from CK rising-hold time
tDSH
0.2
-
0.2
-
0.2
-
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
-
240
-
300
-
350
ps
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read preamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS read preamble setup time
tWPRES
0
-
0
-
0
-
ps
DQS read preamble
tWPRE
0.35
-
0.35
-
0.35
-
tCK
DQS read preamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock Cycle Time
Data Timing
Data Strobe Timing
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7
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
E6
(DDR2-667)
Min
Max
D5
(DDR2-533)
Min
Max
CC
(DDR2-400)
Min
Unit
Max
Command and Address Timing
Address and control input pulse width for each input
tIPW
0.6
-
0.6
-
0.6
-
tCK
Address and control input setup time
tIS
200
-
250
-
350
-
ps
Address and control input hold time
tIH
275
-
375
-
475
-
ps
tCCD
2
-
2
-
2
-
ps
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
tRC
60
-
60
-
55
-
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
-
7.5
-
7.5
-
ns
ACTIVE to READ or WRITE delay
tRCD
15
-
15
-
15
-
ns
Four Bank Activate period
tFAW
37.5
-
37.5
-
37.5
-
ns
ACTIVE to PRECHARGE command
tRAS
45
70,000
45
70,000
40
70,000
ns
Internal READ to precharge Command delay
tRTP
7.5
-
7.5
-
7.5
-
ns
Write recovery time
tWR
15
-
15
-
15
-
ns
Auto precharge write recovery + precharge time
tDAL
t WR+t RP
-
t WR+t RP
-
t WR+tnRP
-
ns
Internal WRITE to READ Command delay
-
7.5
-
10
-
ns
ns
tWTR
7.5
PRECHARGE command period
tRP
15
-
15
-
15
-
PRECHARGE ALL command period
tRPA
tRP+tCK
-
tRP+tCK
-
tRP+tCK
-
ns
LOAD MODE command cycle time
tMRD
2
-
2
-
2
-
tCK
tDELAY
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
ns
Refresh to Active or Refresh to Refresh command
interval
tRFC
127.5
-
127.5
-
127.5
-
ns
Average periodic Refresh interval
tREFI
-
7.8
-
7.8
-
7.8
us
Exit Self Refresh to non-READ command
tXSNR
t RFC(MIN)
+10
-
t RFC(MIN)
+10
-
t RFC(MIN)
+10
-
ns
Exit Self Refresh to READ
tXSRD
200
-
200
-
200
-
tCK
Exit Self Refresh timing reference
tISXR
tIS
-
tIS
-
tIS
-
ps
tAOND
2
2
2
2
2
2
tCK
ps
tCK
CKE low to CK, CK# uncertainty
Self Refresh
ODT
ODT turn-on delay
ODT turn-on
tAON
t AC(MIN)
t AC(MAX)+
700
t AC(MIN)
t AC(MAX)+
1,000
t AC(MIN)
t AC(MAX)+
1000
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
ODT turn-off
tAOF
t AC(MIN)
t AC(MAX)+
600
t AC(MIN)
t AC(MAX)+
600
t AC(MIN)
ODT turn-on(power-down mode)
tAONPD
t AC(MIN)+
2,000
2 x tCK +
t AC(MAX)+
1,000
t AC(MIN)+
2,000
2 x tCK +
t AC(MAX)+
1,000
t AC(MIN)+
2000
ODT turn-off (power-down mode)
tAOFPD
t AC(MIN)+
2,000
2.5 xtCK+
t AC(MAX)+
1,000
t AC(MIN)+
2,000
2.5 xtCK+
t AC(MAX)+
1,000
t AC(MIN)+
2000
ODT to power-down entry latency
tANPD
3
-
3
-
3
-
tCK
ODT power-down exit latency
tAXPD
8
-
8
-
8
-
tCK
t AC(MAX)+
600
2tCK +
t
AC(MAX)+1
000
2.5xtCK +
tAC(MAX)+
1000
ps
ps
ps
Power Down
Exit active power-down to READ command, MR[bit12=0]
tXARD
2
-
2
-
2
-
tCK
Exit active power-down to READ command, MR[bit12=1]
tXARDS
7-AL
-
6-AL
-
6-AL
-
tCK
Exit precharge power-down to any non-READ command
tXP
2
-
2
-
2
-
tCK
CKE minimum high/low time
tCKE
3
-
3
-
3
-
tCK
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8
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
Package Dimensions
FRONT VIEW
3.70
MAX
82.00 TYP
1.00 R (2X)
18.29
10.00
6.00 TYP
0.5 R
PIN 1
PIN 122
3.60
3.20
2.00 (2X)
1.00 +/- 0.10
3.20
33.60 TYP
38.40 TYP
40.90 TYP
2.30
78.00
BACK VIEW
2.00 +/- 0.10 (2X)
1.80 (2X)
TYP
3.80 +/- 0.10
2.55 TYP
PIN 123
PIN 244
1.00 +/- 0.10
0.60
TYP
0.45
TYP
0.25 MAX
1.00 (2X)
Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
2. The dimensional diagram is for reference only.
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9
Product Specifications
PART NO.:
VL495T2863E-E6/D5/CCS
REV: 1.0
Revision History:
Date
05/11/2011
Rev.
Page
1.0
All
Changes
Spec released
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10
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