Selectable I/O Standards in Stratix Stratix GX Devices

Selectable I/O Standards in Stratix Stratix GX Devices
16. Selectable I/O Standards
in Stratix &
Stratix GX Devices
S52004-3.4
Introduction
The proliferation of I/O standards and the need for higher I/O
performance have made it critical that devices have flexible I/O
capabilities. Stratix® and Stratix GX programmable logic devices (PLDs)
feature programmable I/O pins that support a wide range of industry
I/O standards, permitting increased design flexibility. These I/O
capabilities enable fast time-to-market and high-performance solutions to
meet the demands of complex system designs. Additionally, Stratix and
Stratix GX devices simplify system board design and make it easy to
connect to microprocessors, peripherals, memories, gate arrays,
programmable logic circuits, and standard logic functions.
This chapter provides guidelines for using one or more industry I/O
standards in Stratix and Stratix GX devices, including:
■
■
■
■
■
■
■
■
Stratix & Stratix
GX I/O
Standards
Stratix and Stratix GX I/O standards
High-speed interfaces
Stratix and Stratix GX I/O banks
Programmable current drive strength
Hot socketing
Differential on-chip termination
I/O pad placement guidelines
Quartus® II software support
Stratix and Stratix GX devices support a wide range of industry I/O
standards as shown in the Stratix Device Family Data Sheet section in the
Stratix Device Handbook, Volume 1 and the Stratix GX Device Family Data
Sheet section of the Stratix GX Device Handbook, Volume 1. Several
applications that use these I/O standards are listed in Table 16–1.
Table 16–1. I/O Standard Applications & Performance (Part 1 of 2) Note (1)
I/O Standard
Altera Corporation
June 2006
Application
Performance
3.3-V LVTTL/LVCMOS
General purpose
350 MHz
2.5-V LVTTL/LVCMOS
General purpose
350 MHz
1.8-V LVTTL/LVCMOS
General purpose
250 MHz
1.5-V LVCMOS
General purpose
225 MHz
PCI/CompactPCI
PC/embedded systems
66 MHz
16–1
Stratix & Stratix GX I/O Standards
Table 16–1. I/O Standard Applications & Performance (Part 2 of 2) Note (1)
I/O Standard
Application
Performance
PCI-X 1.0
PC/embedded systems
133 MHz
AGP 1× and 2×
Graphics processors
66 to 133 MHz
SSTL-3 Class I and II
SDRAM
167 MHz
SSTL-2 Class I and II
DDR I SDRAM
160 to 400 Mbps
HSTL Class I
QDR SRAM/SRAM/CSIX
150 to 225 MHz
HSTL Class II
QDR SRAM/SRAM/CSIX
150 to 250 MHz
Differential HSTL
Clock interfaces
150 to 225 MHz
GTL
Backplane driver
200 MHz
GTL+
Pentium processor interface
133 to 200 MHz
LVDS
Communications
840 Mbps
HyperTransport
technology
Motherboard interfaces
800 Mbps
LVPECL
PHY interface
840 Mbps
PCML
Communications
840 Mbps
Differential SSTL-2
DDR I SDRAM
160 to 400 Mbps
CTT
Back planes and bus interfaces 200 MHz
Note to Table 16–1:
(1)
These performance values are dependent on device speed grade, package type
(flip-chip or wirebond) and location of I/Os (top/bottom or left/right). See the
DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1.
3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) EIA/JEDEC Standard JESD8-B
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVTTL-compatible devices.
The LVTTL input standard specifies a wider input voltage range of
–0.5 V ≤VI ≤ 3.8 V. Altera allows an input voltage range of –0.5 V ≤VI ≤ 4.1
V. The LVTTL standard does not require input reference voltages or board
terminations.
Stratix and Stratix GX devices support both input and output levels for
3.3-V LVTTL operation.
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B
The 3.3-V low voltage complementary metal oxide semiconductor
(LVCMOS) I/O standard is a general-purpose, single-ended standard
used for 3.3-V applications. The LVCMOS standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVCMOS-compatible
devices.
The LVCMOS standard specifies the same input voltage requirements as
LVTTL (–0.5 V ≤VI ≤ 3.8 V). The output buffer drives to the rail to meet the
minimum high-level output voltage requirements. The 3.3-V I/O
standard does not require input reference voltages or board terminations.
Stratix and Stratix GX devices support both input and output levels for
3.3-V LVCMOS operation.
2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
2.5-V devices. The input and output voltage ranges are:
■
■
The 2.5-V normal range input standards specify an input voltage
range of – 0.3 V ≤ VI ≤ 3.0 V.
The normal range minimum high-level output voltage requirement
(VOH) is 2.1 V.
Stratix and Stratix GX devices support both input and output levels for
2.5-V LVTTL operation.
2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
2.5-V parts. The input and output voltage ranges are:
■
■
Altera Corporation
June 2006
The 2.5-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 3.0 V.
The normal range minimum VOH requirement is 2.1 V.
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Stratix & Stratix GX I/O Standards
Stratix and Stratix GX devices support both input and output levels for
2.5-V LVCMOS operation.
1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-7
The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
1.8-V parts. The input and output voltage ranges are:
■
■
The 1.8-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 2.3 V.
The normal range minimum VOH requirement is VCCIO – 0.45 V.
Stratix and Stratix GX devices support both input and output levels for
1.8-V LVTTL operation.
1.8-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-7
The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other
1.8-V devices. The input and output voltage ranges are:
■
■
The 1.8-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 2.5 V.
The normal range minimum VOH requirement is VCCIO – 0.45 V.
Stratix and Stratix GX devices support both input and output levels for
1.8-V LVCMOS operation.
1.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
JESD8-11
The 1.5-V I/O standard is used for 1.5-V applications. This standard
defines the DC interface parameters for high-speed, low-voltage, nonterminated digital circuits driving or being driven by other 1.5-V devices.
The input and output voltage ranges are:
■
■
The 1.5-V normal range input standards specify an input voltage
range of – 0.5 V ≤ VI ≤ 2.0 V.
The normal range minimum VOH requirement is 1.05 V.
16–4
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix and Stratix GX devices support both input and output levels for
1.5-V LVCMOS operation.
1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6
The high-speed transceiver logic (HSTL) I/O standard is used for
applications designed to operate in the 0.0- to 1.5-V HSTL logic switching
range. This standard defines single ended input and output specifications
for all HSTL-compliant digital integrated circuits. The single ended input
standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V.
Stratix and Stratix GX devices support both input and output levels
specified by the 1.5-V HSTL I/O standard. The input clock is
implemented using dedicated differential input buffers. Two singleended output buffers are automatically programmed to have opposite
polarity so as to implement a differential output clock. Additionally, the
1.5-V HSTL I/O standard in Stratix and Stratix GX devices is compatible
with the 1.8-V HSTL I/O standard in APEXTM 20KE and APEX 20KC
devices because the input and output voltage thresholds are compatible.
See Figures 16–1 and 16–2. Stratix and Stratix GX devices support both
input and output levels with VREF and VTT.
Figure 16–1. HSTL Class I Termination
VTT = 0.75 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
Figure 16–2. HSTL Class II Termination
VTT = 0.75 V
VTT = 0.75 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
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June 2006
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Stratix & Stratix GX I/O Standards
1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6
The differential HSTL I/O standard is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data
rate (QDR) memory clock interfaces. The differential HSTL specification
is the same as the single ended HSTL specification. The standard specifies
an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. Differential HSTL
does not require an input reference voltage, however, it does require a
50 Ω resistor termination resistor to VTT at the input buffer (see
Figure 16–3). Stratix and Stratix GX devices support both input and
output clock levels for 1.5-V differential HSTL. The input clock is
implemented using dedicated differential input buffer. Two single-ended
output buffers are automatically programmed to have opposite polarity
so as to implement a differential output clock.
Figure 16–3. 1.5-V Differential HSTL Class I Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus
Specification Rev. 2.3
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
specification revision 2.3 defines the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expansion boards. This standard
requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant
with the 3.3-V PCI Local Bus Specification Revision 2.3 and meet
64-bit/66-MHz operating frequency and timing requirements. The 3.3-V
PCI standard does not require input reference voltages or board
terminations. Stratix and Stratix GX devices support both input and
output levels.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus
Specification Revision 1.0a
The PCI-X 1.0 standard is used for applications that interface to the PCI
local bus. The standard enables the design of systems and devices that
operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for
a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to
operate much more efficiently, providing more usable bandwidth at any
clock frequency. By using the PCI-X 1.0 standard, devices can be designed
to meet PCI-X 1.0 requirements and operate as conventional 33- and
66-MHz PCI devices when installed in those systems. This standard
requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant
with the 3.3-V PCI-X Specification Revision 1.0a and meet the 133-MHz
operating frequency and timing requirements. The 3.3-V PCI standard
does not require input reference voltages or board terminations. Stratix
and Stratix GX devices support both input and output levels.
3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification
Revision 2.3
The Compact PCI local bus specification is used for applications that
interface to the PCI local bus. It follows the PCI Local Bus Specification
Revision 2.3 plus additional requirements in PCI Industrial Computers
Manufacturing Group (PICMG) specifications PICMG 2.0 R3.0,
CompactPCI specification, and the hot swap requirements in PICMG 2.1
R2.0, CompactPCI Hot Swap Specification. This standard has similar
electrical requirements as LVTTL and requires 3.3-V VCCIO. Stratix and
Stratix GX devices are compliant with the Compact PCI electrical
requirements. The 3.3-V PCI standard does not require input reference
voltages or board terminations. Stratix and Stratix GX devices support
both input and output levels.
3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The AGP interface is a platform bus specification that enables highperformance graphics by providing a dedicated high-speed port for the
movement of large blocks of 3-dimensional texture data between a PC's
graphics controller and system memory. The 1× AGP I/O standard is a
single-ended standard used for 3.3-V graphics applications. The 1× AGP
input standard specifies an input voltage range of
– 0.5 V ≤ VI ≤ VCCIO + 0.5 V. The 1× AGP standard does not require input
reference voltages or board terminations. Stratix and Stratix GX devices
support both input and output levels.
Altera Corporation
June 2006
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3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The 2× AGP I/O standard is a voltage-referenced, single-ended standard
used for 3.3-V graphics applications. The 2× AGP input standard
specifies an input voltage range of – 0.5V ≤ VI ≤ VCCIO + 0.5V. The 2× AGP
standard does not require board terminations. Stratix and Stratix GX
devices support both input and output levels.
GTL - EIA/JEDEC Standard EIA/JESD8-3
The GTL I/O standard is a low-level, high-speed back plane standard
used for a wide range of applications from ASICs and processors to
interface logic devices. The GTL standard defines the DC interface
parameters for digital circuits operating from power supplies of 2.5, 3.3,
and 5.0 V. The GTL standard is an open-drain standard, and Stratix and
Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this standard.
GTL requires a 0.8-V VREF and open-drain outputs with a 1.2-V VTT (see
Figure 16–4). Stratix and Stratix GX devices support both input and
output levels.
Figure 16–4. GTL Termination
VTT = 1.2 V
Output Buffer
VTT = 1.2 V
50 Ω
Z = 50 Ω
50 Ω
Input Buffer
VREF = 0.8 V
GTL+
The GTL+ I/O standard is used for high-speed back plane drivers and
Pentium processor interfaces. The GTL+ standard defines the DC
interface parameters for digital circuits operating from power supplies of
2.5, 3.3, and 5.0 V. The GTL+ standard is an open-drain standard, and
Stratix and Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this
standard. GTL+ requires a 1.0-V VREF and open-drain outputs with a
1.5-V VTT (see Figure 16–5). Stratix and Stratix GX devices support both
input and output levels.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 16–5. GTL+ Termination
VTT = 1.5 V
VTT = 1.5 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.0 V
CTT - EIA/JEDEC Standard JESD8-4
The CTT I/O standard is used for backplanes and memory bus interfaces.
The CTT standard defines the DC interface parameters for digital circuits
operating from 2.5- and 3.3-V power supplies. The CTT standard does not
require special circuitry to interface with LVTTL or LVCMOS devices
when the CTT driver is not terminated. The CTT standard requires a 1.5-V
VREF and a 1.5-V VTT (see Figure 16–6). Stratix and Stratix GX devices
support both input and output levels.
Figure 16–6. CTT Termination
VTT = 1.5 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.5 V
SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8
The SSTL-3 I/O standard is a 3.3-V memory bus standard used for
applications such as high-speed SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies
an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. SSTL-3 requires a 1.5V VREF and a 1.5-V VTT to which the series and termination resistors are
connected (see Figures 16–7 and 16–8). Stratix and Stratix GX devices
support both input and output levels.
Altera Corporation
June 2006
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Stratix & Stratix GX I/O Standards
Figure 16–7. SSTL-3 Class I Termination
VTT = 1.5 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 1.5 V
Figure 16–8. SSTL-3 Class II Termination
VTT = 1.5 V
VTT = 1.5 V
50 Ω
50 Ω
Output Buffer
25 Ω
Z = 50 Ω
Input Buffer
VREF = 1.5 V
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
– 0.3 V ≤ VI ≤ VCCIO + 0.3 V. SSTL-2 requires a 1.25-V VREF and a 1.25-V VTT
to which the series and termination resistors are connected (see
Figures 16–9 and 16–10). Stratix and Stratix GX devices support both
input and output levels.
Figure 16–9. SSTL-2 Class I Termination
VTT = 1.25 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 1.25 V
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 16–10. SSTL-2 Class II Termination
VTT = 1.25 V
VTT = 1.25 V
Output Buffer
50 Ω
25 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.25 V
SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3
The SSTL-18 I/O standard is a 1.8-V memory bus standard. This standard
is similar to SSTL-2 and defines input and output specifications for
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT to which the
series and termination resistors are connected. See Figures 16–11 and
16–12 for details on SSTL-18 Class I and II termination. Stratix and Stratix
GX devices support both input and output levels.
Figure 16–11. SSTL-18 Class I Termination
VTT = 0.9 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Figure 16–12. SSTL-18 Class II Termination
VTT = 0.9 V
VTT = 0.9 V
50 Ω
50 Ω
Output Buffer
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A
The differential SSTL-2 I/O standard is a 2.5-V standard used for
applications such as high-speed DDR SDRAM clock interfaces. This
standard supports differential signals in systems using the SSTL-2
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June 2006
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Stratix & Stratix GX I/O Standards
standard and supplements the SSTL-2 standard for differential clocks.
The differential SSTL-2 standard specifies an input voltage range of
– 0.3 V ≤ VI ≤ VCCIO + 0.3 V. The differential SSTL-2 standard does not
require an input reference voltage differential. See Figure 16–13 for
details on differential SSTL-2 termination. Stratix and Stratix GX devices
support output clock levels for differential SSTL-2 Class II operation. The
output clock is implemented using two single-ended output buffers
which are programmed to have opposite polarity.
Figure 16–13. Differential SSTL-2 Class II Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard requiring a 3.3-V
VCCIO. This standard is used in applications requiring high-bandwidth
data transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix and Stratix GX
devices meet the ANSI/TIA/EIA-644 standard.
Due to the low voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than CMOS,
TTL, and PECL. This low EMI makes LVDS ideal for applications with
low EMI requirements or noise immunity requirements. The LVDS
standard does not require an input reference voltage, however, it does
require a 100 Ω termination resistor between the two signals at the input
buffer. Stratix and Stratix GX devices include an optional differential
LVDS termination resistor within the device using differential on-chip
termination. Stratix and Stratix GX devices support both input and
output levels.
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f
For more information on the LVDS I/O standard in Stratix devices, see
the High-Speed Differential I/O Interfaces in Stratix Devices chapter.
LVPECL
The LVPECL I/O standard is a differential interface standard requiring a
3.3-V VCCIO. The standard is used in applications involving video
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swing than LVDS. The LVPECL
standard does not require an input reference voltage, but it does require
a 100-Ω termination resistor between the two signals at the input buffer.
See Figures 16–14 and 16–15 for two alternate termination schemes for
LVPECL. Stratix and Stratix GX devices support both input and output
levels.
Figure 16–14. LVPECL DC Coupled Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
Figure 16–15. LVPECL AC Coupled Termination
VCCIO
VCCIO
Output Buffer
10 to 100 nF
Z = 50 Ω
R1
R1
R2
R2
Input Buffer
100 Ω
10 to 100 nF
Z = 50 Ω
Pseudo Current Mode Logic (PCML)
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applications such as networking and
telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O
standard consumes less power than the LVPECL I/O standard. The
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June 2006
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PCML standard is similar to LVPECL, but PCML has a reduced voltage
swing, which allows for a faster switching time and lower power
consumption. The PCML standard uses open drain outputs and requires
a differential output signal. See Figure 16–16 for details on PCML
termination. Stratix and Stratix GX devices support both input and
output levels.
Additionally, Stratix GX devices support 1.5-V PCML as described in the
Stratix GX Device Handbook, Volume 1.
Figure 16–16. PCML Termination
VTT
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
50 Ω
50 Ω
Input Buffer
Z = 50 Ω
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential highspeed, high-performance I/O interface standard requiring a 2.5-V VCCIO.
This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport
technology I/O standard is a point-to-point standard in which each
HyperTransport technology bus consists of two point-to-point
unidirectional links. Each link is 2 to 32 bits. The HyperTransport
technology standard does not require an input reference voltage.
However, it does require a 100-Ω termination resistor between the two
signals at the input buffer. See Figure 16–17 for details on HyperTransport
technology termination. Stratix and Stratix GX devices support both
input and output levels.
Figure 16–17. HyperTransport Technology Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
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f
High-Speed
Interfaces
See the Stratix Device Family Data Sheet section in the Stratix Device
Handbook, Volume 1; the Stratix GX Device Family Data Sheet section of the
Stratix GX Device Handbook, Volume 1; and the High-Speed Differential I/O
Interfaces in Stratix Devices chapter for more information on differential
I/O standards.
In addition to current industry physical I/O standards, Stratix and
Stratix GX devices also support a variety of emerging high-speed
interfaces. This section provides an overview of these interfaces.
OIF-SPI4.2
This implementation agreement is widely used in the industry for
OC-192 and 10-Gbps multi-service system interfaces. SONET and SDH
are synchronous transmission systems over which data packets are
transferred. POS-PHY Level 4 is a standard interface for switches and
routers, and defines the operation between a physical layer (PHY) device
and link layer devices (ATM, Internet protocol, and Gigabit Ethernet) for
bandwidths of OC-192 ATM, POS, and 10-Gigabit Ethernet applications.
Some key POS-PHY Level 4 system features include:
■
■
■
■
■
■
■
■
■
Large selection of POS-PHY Level 4-based PHYs
Independent of data protocol
Wide industry support
LVDS I/O standard to improve signal integrity
Inband addressing/control
Out of band flow control
Scalable architecture
Over 622-Mbps operation
Dynamic interface timing mode
POS-PHY Level 4 operates at a wide range of frequencies.
OIF-SFI4.1
This implementation agreement is widely used in the industry for
interfacing physical layer (PHY) to the serializer-deserializer (SERDES)
devices in OC-192 and 10 Gbps multi-service systems. The POS-PHY
Level 4 interface standard defines the SFI-4 standard. POS-PHY
Level 4: SFI-4 is a standardized 16-bit × 622-Mbps line-side interface for
10-Gbps applications. Internet LAN and WAN architectures use
telecommunication SONET protocols for data transferring data over the
PHY layer. SFI-4 interfaces between OC-192 SERDES and SONET
framers.
Altera Corporation
June 2006
16–15
Stratix GX Device Handbook, Volume 2
High-Speed Interfaces
10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft
Standard P802.3ae/D2.0
10 Gigabit Ethernet XSBI is an interface standard for LANs, metropolitan
area networks (MANs), storage area networks (SANs), and WANs.
10 Gigabit Ethernet XSBI provides many features for efficient, effective
high-speed networking, including easy migration to higher performance
levels without disruption, lower cost of ownership including acquisition
and support versus other alternatives, familiar management tools and
common skills, ability to support new applications and data protocols,
flexibility in network design, and multiple vendor sourcing and
interoperability.
Under the ISO Open Systems Interconnection (OSI) model, Ethernet is a
Layer 2 protocol. 10 Gigabit Ethernet XSBI uses the IEEE 802.3 Ethernet
media access control (MAC) protocol, Ethernet frame format, and the
minimum/maximum frame size. An Ethernet PHY corresponding to OSI
layer 1 connects the media to the MAC layer that corresponds to OSI
layer 2. The PHY is divided into a physical media dependent (PMD)
element, such as optical transceivers, and a physical coding sub-layer
(PCS), which has coding and a serializer/multiplexor. This standard
defines two PHY types, including the LAN PHY and the WAN PHY,
which are distinguished by the PCS. The 10 Gigabit Ethernet XSBI
standard is a full-duplex technology standard that can increase the speed
and distance of Ethernet.
RapidIO Interconnect Specification Revision 1.1
The RapidIO interface is a communications standard used to connect
devices on a circuit board and circuit boards on a backplane. RapidIO is a
packet-switched interconnect standard designed for embedded systems
such as those used in networking and communications. The RapidIO
interface standard is a high-performance interconnect interface used for
transferring data and control information between microprocessors,
DSPs, system memory, communications and network processors, and
peripheral devices in a system.
RapidIO replaces existing peripheral bus and processor technologies
such as PCI. Some features of RapidIO include multiprocessing support,
an open standard, flexible topologies, higher bandwidth, low latency,
error management support in hardware, small silicon footprint, widely
available process and I/O technologies, and transparency to existing
applications and operating system software. The RapidIO standard
provides 10-Gbps device bandwidth using 8-bit-wide input and output
data ports. RapidIO uses LVDS technology, has the capability to be scaled
to multi-GHz frequencies, and features a 10-bit interface.
16–16
Stratix GX Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential
high-speed, high performance I/O interface standard developed for
communications and networking chip-to-chip communications.
HyperTransport technology is used in applications such as highperformance networking, telecommunications, embedded systems,
consumer electronics, and Internet connectivity devices. The
HyperTransport technology I/O standard is a point-to-point (one source
connected to exactly one destination) standard that provides a highperformance interconnect between integrated circuits in a system, such as
on a motherboard.
Stratix devices support HyperTransport technology at data rates up to
800 Mbps and 32 bits in each direction. HyperTransport technology uses
an enhanced differential signaling technology to improve performance.
HyperTransport technology supports data widths of 2, 4, 8, 16, or 32 bits
in each direction. HyperTransport technology in Stratix and Stratix GX
devices operates at multiple clock speeds up to 400 MHz.
UTOPIA Level 4 – ATM Forum Technical Committee Standard AFPHY-0144.001
The UTOPIA Level 4 frame-based interface standard allows device
manufacturers and network developers to develop components that can
operate at data rates up to 10 Gbps. This standard increases interface
speeds using LVDS I/O and advanced silicon technologies for fast data
transfers.
UTOPIA Level 4 provides new control techniques and a 32-, 16-, or 8-bit
LVDS bus, a symmetric transmit/receive bus structure for easier
application design and testability, nominal data rates of 10 Gbps, in-band
control of cell delimiters and flow control to minimize pin count, sourcesynchronous clocking, and supports variable length packet systems.
UTOPIA Level 4 handles sustained data rates for OC-192 and supports
ATM cells. UTOPIA Level 4 also supports interconnections across
motherboards, daughtercards, and backplane interfaces.
Stratix & Stratix
GX I/O Banks
Altera Corporation
June 2006
Stratix devices have eight I/O banks in addition to the four enhanced PLL
external clock output banks, as shown in Table 16–2 and Figure 16–18.
I/O banks 3, 4, 7, and 8 support all single-ended I/O standards. I/O
banks 1, 2, 5, and 6 support differential HSTL (on input clocks), LVDS,
LVPECL, PCML, and HyperTransport technology, as well as all singleended I/O standards except HSTL Class II, GTL, SSTL-18 Class II,
PCI/PCI-X 1.0, and 1× /2× AGP. The four enhanced PLL external clock
output banks (I/O banks 9, 10, 11, and 12) support clock outputs all
16–17
Stratix GX Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
single-ended I/O standards in addition to differential SSTL-2 and HSTL
(both on the output clock only). Since Stratix devices support both nonvoltage-referenced and voltage-referenced I/O standards, there are
different guidelines when working with either separately or when
working with both.
Table 16–2. I/O Standards Supported in Stratix I/O Banks (Part 1 of 2)
Enhanced PLL External
Clock Output Banks
I/O Bank
I/O Standard
1
2
3
4
5
6
7
8
9
10
11
12
3.3-V LVTTL/LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
2.5-V LVTTL/LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
1.8-V LVTTL/LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
1.5-V LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
PCI/PCIX//Compact PCI
v
v
v
v
v
v
v
v
AGP 1×
v
v
v
v
v
v
v
v
AGP 2×
v
v
v
v
v
v
v
v
SSTL-3 Class I
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-3 Class II
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-2 Class I
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-2 Class II
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-18 Class I
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-18 Class II
Differential SSTL-2
(output clocks)
HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
1.5-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
1.8-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
HSTL Class II
v
v
v
v
v
v
v
v
1.5-V HSTL Class II
v
v
v
v
v
v
v
v
1.8-V HSTL Class II
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Differential HSTL (input
clocks)
v
v
Differential HSTL (output
clocks)
16–18
Stratix GX Device Handbook, Volume 2
v
v
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Table 16–2. I/O Standards Supported in Stratix I/O Banks (Part 2 of 2)
Enhanced PLL External
Clock Output Banks
I/O Bank
I/O Standard
1
2
GTL
3
4
v
v
5
6
7
8
9
10
11
12
v
v
v
v
v
v
GTL+
v
v
v
v
v
v
v
v
v
v
v
v
CTT
v
v
v
v
v
v
v
v
v
v
v
v
LVDS
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
HyperTransport
technology
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
LVPECL
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
PCML
v
v
(1)
(1)
v
v
(1)
(1)
(2)
(2)
(2)
(2)
Notes to Table 16–2:
(1)
(2)
This I/O standard is only supported on input clocks in this I/O bank.
This I/O standard is only supported on output clocks in this I/O bank.
Altera Corporation
June 2006
16–19
Stratix GX Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
Figure 16–18. Stratix I/O Banks Notes (1), (2), (3)
DQS5T
9
DQS4T
PLL11
DQS1T
10
DQS0T
Bank 4
(5)
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
I/O Banks 1, 2, 5, and 6 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X 1.0, and AGP 1×/2×
PLL2
Bank 1
DQS2T
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
(5)
PLL1
Bank 8
PLL3
DQS8B
DQS7B
DQS6B
DQS5B
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
11
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
DQS9B
PLL4
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
PLL8
DQS3T
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
Bank 2
VREF1B2 VREF2B2 VREF3B2 VREF4B2
Bank 3
VREF1B1 VREF2B1 VREF3B1 VREF4B1
PLL5
12
PLL6
Bank 5
DQS6T
VREF4B5 VREF3B5 VREF2B5 VREF1B5
DQS7T
Bank 6
DQS8T
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
VREF4B6 VREF3B6 VREF2B6 VREF1B6
DQS9T
PLL7
Bank 7
PLL12
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
DQS4B
DQS3B
DQS2B
DQS1B
PLL9
DQS0B
Notes to Figure 16–18:
(1)
(2)
(3)
(4)
(5)
Figure 16–18 is a top view of the silicon die. This corresponds to a top-down view for non-flip-chip packages, but is
a reverse view for flip-chip packages.
Figure 16–18 is a graphic representation only. See the pin list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the
I/O standards except HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2×.
For guidelines on placing single-ended I/O pads next to differential I/O pads, see “I/O Pad Placement Guidelines”
on page 16–30.
16–20
Stratix GX Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Tables 16–3 and 16–4 list the I/O standards that Stratix GX enhanced and
fast PLL pins support. Figure 16–19 shows the I/O standards that each
Stratix GX I/O bank supports.
Table 16–3. I/O Standards Supported in Stratix & Stratix GX Enhanced PLL Pins
Input
Output
I/O Standard
INCLK
FBIN
PLLENABLE
EXTCLK
LVTTL
v
v
v
v
LVCMOS
v
v
v
v
2.5 V
v
v
v
1.8 V
v
v
v
1.5 V
v
v
v
3.3-V PCI
v
v
v
3.3-V PCI-X 1.0
v
v
v
LVPECL
v
v
v
3.3-V PCML
v
v
v
LVDS
v
v
v
HyperTransport technology
v
v
v
Differential HSTL
v
v
v
Differential SSTL
3.3-V GTL
v
v
v
3.3-V GTL+
v
v
v
1.5-V HSTL Class I
v
v
v
1.5-V HSTL Class II
v
v
v
SSTL-18 Class I
v
v
v
SSTL-18 Class II
v
v
v
SSTL-2 Class I
v
v
v
SSTL-2 Class II
v
v
v
SSTL-3 Class I
v
v
v
SSTL-3 Class II
v
v
v
AGP (1× and 2×)
v
v
v
CTT
v
v
v
Altera Corporation
June 2006
16–21
Stratix GX Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
Table 16–4. I/O Standards Supported in Stratix & Stratix GX Fast PLL Pins
Input
I/O Standard
INCLK
PLLENABLE
LVTTL
v
v
LVCMOS
v
v
2.5 V
v
1.8 V
v
1.5 V
v
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
v
3.3-V PCML
v
LVDS
v
HyperTransport technology
v
Differential HSTL
v
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5V HSTL Class I
v
1.5V HSTL Class II
SSTL-18 Class I
v
SSTL-18 Class II
SSTL-2 Class I
v
SSTL-2 Class II
v
SSTL-3 Class I
v
SSTL-3 Class II
v
AGP (1× and 2×)
CTT
16–22
Stratix GX Device Handbook, Volume 2
v
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 16–19. Stratix GX I/O Banks
I/O Bank 2
I/O Banks 1 & 2 Support:
■ Differential I/O Standards
- True LVDS
- LVPECL
- 3.3-V PCML
- HyperTransport Technology
■ Single-Ended I/O Standard
- 3.3 -, 2.5 -, 1.8 -V LVTTL
- GTL+
- CTT
- SSTL-18 Class I
- SSTL-2 Class I and II
- SSTL-3 Class I and II
- 1.5 -, 1.8 -V HSTL Class I
I/O Bank 1
I/O Bank 3
I/O Bank 4
I/O Banks 3, 4, 6 & 7 Support:
■ 3.3-, 2.5-, 1.8-V LVTTL
■ 3.3-V PCI, PCI-X 1.0
■ GTL
■ GTL+
■ AGP
■ CTT
■ SSTL-18 Class I and II
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ HSTL Class I and II
Individual
Power Bus
I/O Bank 7
I/O Bank 6
I/O Bank 5
I/O Bank 5 Contains Transceiver Blocks
There is some flexibility with the number of I/O standards each Stratix
I/O bank can simultaneously support. The following sections provide
guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Stratix devices.
Altera Corporation
June 2006
16–23
Stratix GX Device Handbook, Volume 2
Stratix & Stratix GX I/O Banks
Non-Voltage-Referenced Standards
Each Stratix I/O bank has its own VCCIO pins and supports only one
VCCIO, either 1.5, 1.8, 2.5 or 3.3 V. A Stratix I/O bank can simultaneously
support any number of input signals with different I/O standard
assignments, as shown in Table 16–5.
Table 16–5. Acceptable Input Levels for LVTTL/LVCMOS
Acceptable Input Levels
Bank VCCIO
3.3 V
2.5 V
1.8 V
1.5 V
3.3 V
v
v
2.5 V
v
v
1.8 V
v (2)
v (2)
v
v (1)
1.5 V
v (2)
v (2)
v
v
Notes to Table 16–5:
(1)
(2)
Because the input signal will not drive to the rail, the input buffer does not
completely shut off, and the I/O current will be slightly higher than the default
value.
These input values overdrive the input buffer, so the pin leakage current will be
slightly higher than the default value.
For output signals, a single I/O bank can only support non-voltagereferenced output signals driving at the same voltage as VCCIO. A Stratix
I/O bank can only have one VCCIO value, so it can only drive out that one
value for non-voltage referenced signals. For example, an I/O bank with
a 2.5-V VCCIO setting can support 2.5-V LVTTL inputs and outputs,
HyperTransport technology inputs and outputs, and 3.3-V LVCMOS
inputs (not output or bidirectional pins).
1
If the output buffer overdrives the input buffer, you must turn
on the Allow voltage overdrive for LVTTL/LVCMOS option in
the Quartus II software. To see this option, click the Device &
Pin Options button in the Device page of the Settings dialog
box (Assignments menu). Then click the Pin Placement tab in
the Device & Pin Options dialog box.
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix I/O
bank supports multiple VREF pins feeding a common VREF bus. The
number of available VREF pins increases as device density increases. If
these pins are not used as VREF pins, they can not be used as generic I/O
pins.
16–24
Stratix GX Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards
use the same VREF setting. For example, although one I/O bank can
implement both SSTL-3 and SSTL-2 I/O standards, I/O pins using these
standards must be in different banks since they require different VREF
values
For voltage-referenced inputs, the receiver compares the input voltage to
the voltage reference and does not take into account the VCCIO setting.
Therefore, the VCCIO setting is irrelevant for voltage referenced inputs.
Voltage-referenced bidirectional and output signals must be the same as
the I/O bank’s VCCIO voltage. For example, although you can place an
SSTL-2 input pin in any I/O bank with a 1.25-V VREF level, you can only
place SSTL-2 output pins in an I/O bank with a 2.5-V VCCIO.
Mixing Voltage Referenced & Non-Voltage Referenced
Standards
Non-voltage referenced and voltage referenced pins can safely be mixed
in a bank by applying each of the rule-sets individually. For example, on
I/O bank can support SSTL-3 inputs and 1.8-V LVCMOS inputs and
outputs with a 1.8-V VCCIO and a 1.5-V VREF. Similarly, an I/O bank can
support 1.5-V LVCMOS, 3.3-V LVTTL (inputs, but not outputs), and
HSTL I/O standards with a 1.5-V VCCIO and 0.75-V VREF.
For the voltage-referenced examples, see the “I/O Pad Placement
Guidelines” section. For details on how the Quartus II software supports
I/O standards, see the “Quartus II Software Support”section.
Altera Corporation
June 2006
16–25
Stratix GX Device Handbook, Volume 2
Drive Strength
Drive Strength
Each I/O standard supported by Stratix and Stratix GX devices drives out
a minimum drive strength. When an I/O is configured as LVTTL or
LVCMOS I/O standards, you can specify the current drive strength, as
summarized in Table 16–7.
Standard Current Drive Strength
Each I/O standard supported by Stratix and Stratix GX devices drives out
a minimum drive strength. Table 16–6 summarizes the minimum drive
strength of each I/O standard.
Table 16–6. Minimum Current Drive Strength of Each I/O Standard
I/O Standard
Current Strength, IOL/IOH (mA)
GTL
40 (1)
GTL+
34 (1)
SSTL-3 Class I
8
SSTL-3 Class II
16
SSTL-2 Class I
8.1
SSTL-2 Class II
16.4
SSTL-18 Class I
6.7
SSTL-18 Class II
13.4
1.5-V HSTL Class I
8
1.5-V HSTL Class II
16
CTT
8
AGP 1×
IOL = 1.5, IOH = –0.5
Note to Table 16–6:
(1)
Because this I/O standard uses an open drain buffer, this value refers to IOL.
When the SSTL-2 Class I and II I/O standards are implemented on top or
bottom I/O pins, the drive strength is designed to be higher than the
drive strength of the buffer when implemented on side I/O pins. This
allows the top or bottom I/O pins to support 200-MHz operation with the
standard 35-pF load. At the same time, the current consumption when
using top or bottom I/O pins is higher than the side I/O pins. The high
current strength may not be necessary for certain applications where the
value of the load is less than the standard test load (e.g., DDR interface).
The Quartus II software allows you to reduce the drive strength when the
I/O pins are used for the SSTL-2 Class I or Class II I/O standard and
being implemented on the top or bottom I/O through the Current
Strength setting. Select the minimum strength for lower drive strength.
16–26
Stratix GX Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Programmable Current Drive Strength
The Stratix and Stratix GX device I/O pins support various output
current drive settings as shown in Table 16–7. These programmable drive
strength settings help decrease the effects of simultaneously switching
outputs (SSO) in conjunction with reducing system noise. The supported
settings ensure that the device driver meets the IOH and IOL specifications
for the corresponding I/O standard.
Table 16–7. Programmable Drive Strength
I/O Standard
IOH / IOL Current Strength Setting (mA)
3.3-V LVTTL
24 (1), 16, 12, 8, 4
3.3-V LVCMOS
24 (2), 12 (1), 8, 4, 2
2.5-V LVTTL/LVCMOS
16 (1), 12, 8, 2
1.8-V LVTTL/LVCMOS
12 (1), 8, 2
1.5-V LVCMOS
8 (1), 4, 2
Notes to Table 16–7:
(1)
(2)
This is the Quartus II software default current setting.
I/O banks 1, 2, 5, and 6 do not support this setting.
These drive-strength settings are programmable on a per-pin basis (for
output and bidirectional pins only) using the Quartus II software. To
modify the current strength of a particular pin, see “Programmable Drive
Strength Settings” on page 16–40.
Hot Socketing
Stratix devices support hot socketing without any external components.
In a hot socketing situation, a device’s output buffers are turned off
during system power-up or power-down. Stratix and Stratix GX devices
support any power-up or power-down sequence (VCCIO and VCCINT) to
simplify designs. For mixed-voltage environments, you can drive signals
into the device before or during power-up or power-down without
damaging the device. Stratix and Stratix GX devices do not drive out until
the device is configured and has attained proper operating conditions.
Even though you can power up or down the VCCIO and VCCINT power
supplies in any sequence you should not power down any I/O bank(s)
that contains the configuration pins while leaving other I/O banks
powered on. For power up and power down, all supplies (VCCINT and all
VCCIO power planes) must be powered up and down within 100 ms of one
another. This prevents I/O pins from driving out.
Altera Corporation
June 2006
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Stratix GX Device Handbook, Volume 2
I/O Termination
You can power up or power down the VCCIO and VCCINT pins in any
sequence. The power supply ramp rates can range from 100 ns to 100 ms.
During hot socketing, the I/O pin capacitance is less than 15 pF and the
clock pin capacitance is less than 20 pF.
DC Hot Socketing Specification
The hot socketing DC specification is | IIOPIN | < 300 μ A.
AC Hot Socketing Specification
The hot socketing AC specification is | IIOPIN | < 8 mA for 10 ns or less.
This specification takes into account the pin capacitance, but not board
trace and external loading capacitance. Additional capacitance for trace,
connector, and loading must be considered separately.
IIOPIN is the current at any user I/O pin on the device. The DC
specification applies when all VCC supplies to the device are stable in the
powered-up or powered-down conditions. For the AC specification, the
peak current duration because of power-up transients is 10 ns or less. For
more information, refer to the Hot-Socketing & Power-Sequencing Feature &
Testing for Altera Devices white paper.
I/O Termination
Although single-ended, non-voltage-referenced I/O standards do not
require termination, Altera recommends using external termination to
improve signal integrity where required.
The following I/O standards do not require termination:
■
■
■
■
■
■
■
■
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI/Compact PCI
3.3-V PCI-X 1.0
3.3-V AGP 1×
Voltage-Referenced I/O Standards
Voltage-referenced I/O standards require both an input reference
voltage, VREF, and a termination voltage, VTT. Off-chip termination on the
board should be used for series and parallel termination.
16–28
Stratix GX Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
For more information on termination for voltage-referenced I/O
standards, see the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter in the Stratix Device Handbook, Volume 2; or the Stratix GX Device
Handbook, Volume 2.
Differential I/O Standards
Differential I/O standards typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the bus. Stratix and Stratix GX
devices provide an optional differential termination on-chip resistor
when using LVDS.
See the High-Speed Differential I/O Interfaces in Stratix Devices chapter for
more information on differential I/O standards and their interfaces.
For differential I/O standards, I/O banks support differential
termination when VCCIO equals 3.3 V.
Differential Termination (RD)
Stratix devices support differential on-chip termination for sourcesynchronous LVDS signaling. The differential termination resistors are
adjacent to the differential input buffers on the device. This placement
eliminates stub effects, improving the signal integrity of the serial link.
Using differential on-chip termination resistors also saves board space.
Figure 16–20 shows the differential termination connections for Stratix
and Stratix GX devices.
Figure 16–20. Differential Termination
Differential
Transmitter
Stratix LVDS
Receiver Buffer with
Differential On-Chip Termination
Z0
RD
Z0
Altera Corporation
June 2006
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Stratix GX Device Handbook, Volume 2
I/O Pad Placement Guidelines
Differential termination for Stratix devices is supported for the left and
right I/O banks. Differential termination for Stratix GX devices is
supported for the left, source-synchronous I/O bank. Some of the clock
input pins are in the top and bottom I/O banks, which do not support
differential termination. Clock pins CLK[1,3,8,10] support differential
on-chip termination. Clock pins CLK[0,2,9,11], CLK[4-7], and CLK[12-15]
do not support differential on-chip termination.
Transceiver Termination
Stratix GX devices feature built-in on-chip termination within the
transceiver at both the transmit and receive buffers. This termination
improves signal integrity and provides support for the 1.5-V PCML I/O
standard.
I/O Pad
Placement
Guidelines
This section provides pad placement guidelines for the programmable
I/O standards supported by Stratix and Stratix GX devices and includes
essential information for designing systems using the devices' selectable
I/O capabilities. These guidelines will reduce noise problems so that
FPGA devices can maintain an acceptable noise level on the line from the
VCCIO supply. Since Altera FPGAs require that a separate VCCIO power
each bank, these noise issues do not have any effect when crossing bank
boundaries and these guidelines do not apply. Although pad placement
rules need not be considered between I/O banks, some rules must be
considered if you are using a VREF signal in a PLLOUT bank. Note that the
signals in the PLLOUT banks share the VREF supply with neighboring I/O
banks and, therefore, must adhere to the VREF rules discussed in “VREF
Pad Placement Guidelines”.
Differential Pad Placement Guidelines
To avoid cross coupling and maintain an acceptable noise level on the
VCCIO supply, there are restrictions on the placement of single-ended I/O
pads in relation to differential pads. Use the following guidelines for
placing single-ended pads with respect to differential pads in Stratix
devices. These guidelines apply for LVDS, HyperTransport technology,
LVPECL, and PCML I/O standards. The differential pad placement
guidelines do not apply for differential HSTL and differential SSTL
output clocks since each differential output clock is essentially
implemented using two single-ended output buffers. These rules do not
apply to differential HSTL input clocks either even though the dedicated
input buffers are used. However, both differential HSTL and differential
SSTL output standards must adhere to the single-ended (VREF) pad
placement restrictions discussed in “VREF Pad Placement Guidelines”.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
■
■
For flip-chip packages, there are no restrictions for placement of
single-ended input signals with respect to differential signals (see
Figure 16–21). For wire-bond packages, single ended input pads may
only be placed four or more pads away from a differential pad.
Single-ended outputs and bidirectional pads may only be placed five
or more pads away from a differential pad (see Figure 16–21),
regardless of package type.
Figure 16–21. Legal Pin Placement Note (1)
Wirebond
Input
Input, Output,
Bidirectional
Differential Pin
FlipChip
Input
Input
Input, Output,
Bidirectional
Note to Figure 16–21:
(1)
Input pads on a flip-chip packages have no restrictions.
VREF Pad Placement Guidelines
Restrictions on the placement of single-ended voltage-referenced I/O
pads with respect to VREF pads help maintain an acceptable noise level
on the VCCIO supply and to prevent output switching noise from shifting
the VREF rail. The following guidelines are for placing single-ended pads
in Stratix devices.
Input Pins
Each VREF pad supports a maximum of 40 input pads with up to 20 on
each side of the VREF pad.
Output Pins
When a voltage referenced input or bidirectional pad does not exist in a
bank, there is no limit to the number of output pads that can be
implemented in that bank. When a voltage referenced input exists, each
VREF pad supports 20 outputs for thermally enhanced FineLine BGA®
and thermally enhanced BGA cavity up packages or 15 outputs for Nonthermally enhanced cavity up and non-thermally enhanced
FineLine BGA packages.
Altera Corporation
June 2006
16–31
Stratix GX Device Handbook, Volume 2
I/O Pad Placement Guidelines
Bidirectional Pins
Bidirectional pads must satisfy input and output guidelines
simultaneously. If the bidirectional pads are all controlled by the same OE
and there are no other outputs or voltage referenced inputs in the bank,
then there is no case where there is a voltage referenced input active at the
same time as an output. Therefore, the output limitation does not apply.
However, since the bidirectional pads are linked to the same OE, the
bidirectional pads act as inputs at the same time. Therefore, the input
limitation of 40 input pads (20 on each side of the VREF pad) applies.
If any of the bidirectional pads are controlled by different output enables
(OE) and there are no other outputs or voltage referenced inputs in the
bank, then there may be a case where one group of bidirectional pads is
acting as inputs while another group is acting as outputs. In such cases,
apply the formulas shown in Table 16–8.
Table 16–8. Input-Only Bidirectional Pin Limitation Formulas
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> – <Total number of pads from the
thermally enhanced BGA cavity up
smallest group of pads controlled by an OE> ≤20 (per VREF pad)
Non-thermally enhanced cavity up and <Total number of bidirectional pads> – <Total number of pads from the
non-thermally enhanced FineLine BGA smallest group of pads controlled by an OE> ≤15 (per VREF pad).
Consider a thermally enhanced FineLine BGA package with eight
bidirectional pads controlled by OE1, eight bidirectional pads controlled
by OE2, and six bidirectional pads controlled by OE3. While this totals 22
bidirectional pads, it is safely allowable because there would be a
maximum of 16 outputs per VREF pad possible assuming the worst case
where OE1 and OE2 are active and OE3 is inactive. This is particularly
relevant in DDR SDRAM applications.
When at least one additional voltage referenced input and no other
outputs exist in the same VREF bank, then the bidirectional pad limitation
must simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> ≤40 (20 on
each side of the VREF pad)
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
The previous equation accounts for the input limitations, but you must
apply the appropriate equation from Table 16–9 to determine the output
limitations.
Table 16–9. Bidirectional pad Limitation Formulas (Where VREF Inputs Exist)
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> ≤20 (per VREF pad)
thermally enhanced BGA cavity up
Non-thermally enhanced cavity up and <Total number of bidirectional pads> ≤15 (per VREF pad)
non-thermally enhanced FineLine BGA
When at least one additional output exists but no voltage referenced
inputs exist, apply the appropriate formula from Table 16–10.
Table 16–10. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist)
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> + <Total number of additional
thermally enhanced BGA cavity up
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> ≤20 (per VREF pad)
Non-thermally enhanced cavity up and <Total number of bidirectional pads> + <Total number of additional
non-thermally enhanced FineLine BGA output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> ≤15 (per VREF pad)
When additional voltage referenced inputs and other outputs exist in the
same VREF bank, then the bidirectional pad limitation must again
simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> ≤40 (20 on
each side of the VREF pad)
Altera Corporation
June 2006
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Stratix GX Device Handbook, Volume 2
I/O Pad Placement Guidelines
The previous equation accounts for the input limitations, but you must
apply the appropriate equation from Table 16–9 to determine the output
limitations.
Table 16–11. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs & Outputs)
Package Type
Formula
Thermally enhanced FineLine BGA and <Total number of bidirectional pads> + <Total number of additional
thermally enhanced BGA cavity up
output pads> ≤20 (per VREF pad)
non-thermally enhanced cavity up and <Total number of bidirectional pads> + <Total number of additional
non-thermally enhanced FineLine BGA output pads> ≤15 (per VREF pad)
In addition to the pad placement guidelines, use the following guidelines
when working with VREF standards:
■
■
Each bank can only have a single VCCIO voltage level and a single
VREF voltage level at a given time. Pins of different I/O standards can
share the bank if they have compatible VCCIO values (see Table 16–12
for more details).
In all cases listed above, the Quartus II software generates an error
message for illegally placed pads.
Output Enable Group Logic Option in Quartus II
The Quartus II software can check a design to make sure that the pad
placement does not violate the rules mentioned above. When the
software checks the design, if the design contains more bidirectional pins
than what is allowed, the Quartus II software returns a fitting error. When
all the bidirectional pins are either input or output but not both (for
example, in a DDR memory interface), you can use the Output Enable
Group Logic option. Turning on this option directs the Quartus II Fitter
to view the specified nodes as an output enable group. This way, the Fitter
does not violate the requirements for the maximum number of pins
driving out of a VREF bank when a voltaged-referenced input pin or
bidirectional pin is present.
In a design that implements DDR memory interface with dq, dqs and dm
pins utilized, there are two ways to enable the above logic options. You
can enable the logic options through the Assignment Editor or by adding
the following assignments to your project’s ESF file:
OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
dq : OUTPUT_ENABLE_GROUP 1;
dqs : OUTPUT_ENABLE_GROUP 1;
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
dm : OUTPUT_ENABLE_GROUP 1;
}
As a result, the Quartus II Fitter does not count the bidirectional pin
potential outputs, and the number of VREF bank outputs remains in the
legal range.
Toggle Rate Logic Option in Quartus II
You should specify the pin’s output toggling rate in order to perform a
stricter pad placement check in the Quartus II software. Specify the
frequency at which a pin toggles in the Quartus II Assignment Editor.
This option is useful for adjusting the pin toggle rate in order to place
them closer to differential pins. The option directs the Quartus II Fitter
toggle-rate checking while allowing you to place a single-ended pin
closer to a differential pin.
DC Guidelines
Variables affecting the DC current draw include package type and desired
termination methods. This section provides information on each of these
variables and also shows how to calculate the DC current for pin
placement.
1
The Quartus II software automatically takes these variables into
account during compilation.
For any 10 consecutive output pads in an I/O bank, Altera recommends
a maximum current of 200 mA for thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up packages and 164 mA for
non-thermally enhanced cavity up and non-thermally enhanced FineLine
BGA packages. The following equation shows the current density
limitation equation for thermally enhanced FineLine BGA and thermally
enhanced BGA cavity up packages:
pin + 9
Σ
Ipin < 200 mA
pin
The following equation shows the current density limitation equation for
non-thermally enhanced cavity up and non-thermally enhanced
FineLine BGA packages:
Altera Corporation
June 2006
16–35
Stratix GX Device Handbook, Volume 2
I/O Pad Placement Guidelines
pin + 9
Σ
Ipin < 164 mA
pin
Table 16–12 shows the DC current specification per pin for each I/O
standard. I/O standards not shown in the table do not exceed these
current limitations.
Table 16–12. I/O Standard DC Specification Note (1)
IPIN (mA)
Pin I/O Standard
3.3-V VCCIO
2.5-V VCCIO
1.5-V VCCIO
GTL
40
40
-
GTL+
34
34
-
SSTL-3 Class I
8
-
-
SSTL-3 Class II
16
-
-
CTT
8
-
-
SSTL-2 Class I
-
8.1
-
SSTL-2 Class II
-
16.4
-
HSTL Class I
-
-
8
HSTL Class II
-
-
16
Note to Table 16–12:
(1)
f
The current rating on a VREF pin is less than 10μA.
For more information on Altera device packaging, see the Package
Information for Stratix Devices chapter in the Stratix Device Handbook,
Volume 2.
16–36
Stratix GX Device Handbook, Volume 2
Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 16–22. Current Draw Limitation Guidelines
I/O Pin Sequence
of an I/O Bank
Any 10 Consecutive I/O Pins,
VCC
GND
Any 10 consecutive I/O pads cannot exceed 200 mA in thermally
enhanced FineLine BGA and thermally enhanced BGA cavity up
packages or 164 mA in non-thermally enhanced cavity up and nonthermally enhanced FineLine BGA packages.
For example, consider a case where a group of 10 consecutive pads are
configured as follows for a thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up package:
■
■
■
Number of SSTL-3 Class I output pads = 3
Number of GTL+ output pads = 4
The rest of the surrounding I/O pads in the consecutive group of 10
are unused
In this case, the total current draw for these 10 consecutive I/O pads
would be:
(# of SSTL-3 Class I pads × 8 mA) +
(# of GTL+ output pads × 34 mA) = (3 × 8 mA) + (4 × 34 mA) = 160 mA
In the above example, the total current draw for all 10 consecutive I/O
pads is less than 200 mA.
Altera Corporation
June 2006
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Stratix GX Device Handbook, Volume 2
Power Source of Various I/O Standards
Power Source of
Various I/O
Standards
For Stratix and Stratix GX devices, the I/O standards are powered by
different power sources. To determine which source powers the input
buffers, see Table 16–13. All output buffers are powered by VCCIO.
Table 16–13. The Relationships Between Various I/O Standards and the
Power Sources
I/O Standard
Quartus II
Software
Support
Power Source
2.5V/3.3V LVTTL
VCCIO
PCI/PCI-X 1.0
VCCIO
AGP
VCCIO
1.5V/1.8V
VCCIO
GTL
VCCINT
GTL+
VCCINT
SSTL
VCCINT
HSTL
VCCINT
CTT
VCCINT
LVDS
VCCINT
LVPECL
VCCINT
PCML
VCCINT
HyperTransport
VCCINT
You specify which programmable I/O standards to use for Stratix and
Stratix GX devices with the Quartus II software. This section describes
Quartus II implementation, placement, and assignment guidelines,
including
■
■
■
■
■
■
Compiler Settings
Device & Pin Options
Assign Pins
Programmable Drive Strength Settings
I/O Banks in the Floorplan View
Auto Placement & Verification
Compiler Settings
You make Compiler settings in the Compiler Settings dialog box
(Processing menu). Click the Chips & Devices tab to specify the device
family, specific device, package, pin count, and speed grade to use for
your design.
16–38
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Device & Pin Options
Click Device & Pin Options in the Compiler Settings dialog box to
access the I/O pin settings. For example, in the Voltage tab you can select
a default I/O standard for all pins for the targeted device. I/O pins that
do not have a specific I/O standard assignment default this standard.
Click OK when you are done setting I/O pin options to return to the
Compiler Settings dialog box.
Assign Pins
Click Assign Pins in the Compiler Settings dialog box to view the
device’s pin settings and pin assignments (see Figure 16–23). You can
view the pin settings under Available Pins & Existing Assignments. The
listing does not include VREF pins because they are dedicated pins. The
information for each pin includes:
■
■
■
■
■
■
■
■
Number
Name
I/O Bank
I/O Standard
Type (e.g., row or column I/O and differential or control)
SignalProbe Source Name
Enabled (that is, whether SignalProbe routing is enabled or disabled
Status
Figure 16–23. Assign Pins
Altera Corporation
June 2006
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Stratix GX Device Handbook, Volume 2
Quartus II Software Support
When you assign an I/O standard that requires a reference voltage to an
I/O pin, the Quartus II software automatically assigns VREF pins. See the
Quartus II Help for instructions on how to use an I/O standard for a pin.
Programmable Drive Strength Settings
To make programmable drive strength settings, perform the following
steps:
1.
In the Tools menu, choose Assignment Organizer.
2.
Choose the Edit specific entity & node settings for: setting, then
select the output or bidirectional pin to specify the current strength
for.
3.
In the Assignment Categories dialog box, select Options for
Individual Nodes Only.
4.
Select Click here to add a new assignment.
5.
In the Assignment dialog box, set the Name field to Current
Strength and set the Setting field to the desired, allowable value.
6.
Click Add.
7.
Click Apply, then OK.
I/O Banks in the Floorplan View
You can view the arrangement of the device I/O banks in the Floorplan
View (View menu) as shown in Figure 16–24. You can assign multiple
I/O standards to the I/O pins in any given I/O bank as long as the VCCIO
of the standards is the same. Pins that belong to the same I/O bank must
use the same VCCIO signal.
Each device I/O pin belongs to a specific, numbered I/O bank. The
Quartus II software color codes the I/O bank to which each I/O pin and
VCCIO pin belong. Turn on the Show I/O Banks option to display the I/O
bank color and the bank numbers for each pin.
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Altera Corporation
June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 16–24. Floorplan View Window
Auto Placement & Verification of Selectable I/O Standards
The Quartus II software automatically verifies the placement for all I/O
and VREF pins and performs the following actions.
■
■
■
■
■
Altera Corporation
June 2006
Automatically places I/O pins of different VREF standards without
pin assignments in separate I/O banks and enables the VREF pins of
these I/O banks.
Verifies that voltage-referenced I/O pins requiring different VREF
levels are not placed in the same bank.
Reports an error message if the current limit is exceeded for a Stratix
or Stratix GX power bank, as determined by the equation
documented in “DC Guidelines” on page 16–35.
Reserves the unused high-speed differential I/O channels and
regular user I/O pins in the high-speed differential I/O banks when
any of the high-speed differential I/O channels are being used.
Automatically assigns VREF pins and I/O pins such that the current
requirements are met and I/O standards are placed properly.
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Stratix GX Device Handbook, Volume 2
Conclusion
Conclusion
Stratix and Stratix GX devices provide the I/O capabilities to allow you
to work with current and emerging I/O standards and requirements.
Today’s complex designs demand increased flexibility to work with the
wide variety of available I/O standards and to simplify board design.
With Stratix and Stratix GX device features, such as hot socketing and
differential on-chip termination, you can reduce board design interface
costs and increase your development flexibility.
More
Information
For more information, see the following sources:
■
■
■
■
References
The Stratix Device Family Data Sheet section in the Stratix Device
Handbook, Volume 1
The Stratix GX Device Family Data Sheet section of the Stratix GX
Device Handbook, Volume 1
The High-Speed Differential I/O Interfaces in Stratix Devices chapter
AN 224: High-Speed Board Layout Guidelines
For more information, see the following references:
■
■
■
■
■
■
■
■
Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9B,
Electronic Industries Association, December 2000.
High-Speed Transceiver Logic (HSTL) – A 1.5-V Output Buffer
Supply Voltage Based Interface Standard for Digital Integrated
Circuits, EIA/JESD8-6, Electronic Industries Association, August
1995.
1.5-V +/- 0.1 V (Normal Range) and 0.9 V – 1.6 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-11, Electronic Industries
Association, October 2000.
1.8-V +/- 0.15 V (Normal Range) and 1.2 V – 1.95 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-7, Electronic Industries
Association, February 1997.
Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits, JESD8-9A, Electronic
Industries Association, November 1993.
2.5-V +/- 0.2V (Normal Range) and 1.8-V to 2.7V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-5, Electronic Industries
Association, October 1995.
Interface Standard for Nominal 3V/ 3.3-V Supply Digital Integrated
Circuits, JESD8-B, Electronic Industries Association, September 1999.
Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits, JESD8-3, Electronic
Industries Association, November 1993.
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June 2006
Selectable I/O Standards in Stratix & Stratix GX Devices
■
■
■
■
■
■
■
■
Altera Corporation
June 2006
Accelerated Graphics Port Interface Specification 2.0, Intel
Corporation.
Stub Series Terminated Logic for 1.8-V (SSTL-18), Preliminary JC42.3,
Electronic Industries Association.
PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group,
December 1998.
PCI-X Local Bus Specification, Revision 1.0a, PCI Special Interest
Group.
UTOPIA Level 4, AF-PHY-0144.001, ATM Technical Committee.
POS-PHY Level 4: SPI-4, OIF-SPI4-02.0, Optical Internetworking
Forum.
POS-PHY Level 4: SFI-4, OIF-SFI4-01.0, Optical Internetworking
Forum.
Electrical Characteristics of Low Voltage Differential Signaling
(LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National
Standards Institute/Telecommunications Industry/Electronic
Industries Association, October 1995.
16–43
Stratix GX Device Handbook, Volume 2
References
16–44
Stratix GX Device Handbook, Volume 2
Altera Corporation
June 2006
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