MSC CXB CD945 User Manual

User’s Manual

CXB-CD945

MSC COM Express™ Basic Module

Rev. 1.6

May 6th, 2010

MSC CXB-CD945 User's Manual

Preface

Copyright Notice

Copyright © 2008 MSC Vertriebs GmbH. All rights reserved.

Copying of this document, and giving it to others and the use or communication of the contents thereof, are forbidden without express authority. Offenders are liable to the payment of damages.

All rights are reserved in the event of the grant of a patent or the registration of a utility model or design.

Important Information

This documentation is intended for qualified audience only. The product described herein is not an end user product. It was developed and manufactured for further processing by trained personnel.

Disclaimer

Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied. The information in this document is provided “as is” and is subject to change without notice.

EMC Rules

This unit has to be installed in a shielded housing. If not installed in a properly shielded enclosure, and used in accordance with the instruction manual, this product may cause radio interference in which case the user may be required to take adequate measures at his or her own expense.

Trademarks

All used product names, logos or trademarks are property of their respective owners.

Certification

MSC Vertriebs GmbH is certified according to DIN EN ISO 9001:2000 standards.

Life-Cycle-Management

MSC products are developed and manufactured according to high quality standards. Our lifecycle-management assures long term availability through permanent product maintenance.

Technically necessary changes and improvements are introduced if applicable. A product- change-notification and end-of-life management process assures early information of our customers.

Product Support

MSC engineers and technicians are committed to provide support to our customers whenever needed.

Before contacting Technical Support of MSC Vertriebs GmbH, please consult the respective pages on our web site at www.msc-ge.com/support-boards for the latest documentation, drivers and software downloads.

If the information provided there does not solve your problem, please contact our Technical

Support:

Email: [email protected]

Phone: +49 8165 906-200

2


Content

1 General Information ........................................................................................................................................ 5

1.1

Revision History...................................................................................................................................... 5

1.2

Reference Documents ............................................................................................................................. 5

1.3

Introduction ............................................................................................................................................. 6

2 Technical Description ..................................................................................................................................... 7

2.1

Key features ............................................................................................................................................ 7

2.2

Block diagram ......................................................................................................................................... 8

2.3

COM Express implementation ................................................................................................................ 9

2.4

Functional units ..................................................................................................................................... 10

2.5

Power Supply ........................................................................................................................................ 12

2.6

Power dissipation (DOS Prompt, 512MB DDR2 SO-DIMM) .............................................................. 12

2.7

Mechanical Dimensions ........................................................................................................................ 13

2.8

Thermal specifications .......................................................................................................................... 14

2.9

Signal description .................................................................................................................................. 15

2.9.1

AC97 Audio / High Definition Audio ........................................................................................... 15

2.9.2

Ethernet ......................................................................................................................................... 15

2.9.3

IDE ................................................................................................................................................ 16

2.9.4

Serial ATA .................................................................................................................................... 17

2.9.5

PCI Express Lanes x1 ................................................................................................................... 18

2.9.6

PCI Express Lanes x16 ................................................................................................................. 18

2.9.7

Express Card Support .................................................................................................................... 19

2.9.8

PCI Bus ......................................................................................................................................... 19

2.9.9

USB ............................................................................................................................................... 21

2.9.10

LVDS Flat Panel ........................................................................................................................... 21

2.9.11

LPC Bus ....................................................................................................................................... 22

2.9.12

Analogue VGA .............................................................................................................................. 22

2.9.13

TV Out .......................................................................................................................................... 23

2.9.14

SVDO ............................................................................................................................................ 23

2.9.15

Miscellaneous ................................................................................................................................ 24

2.9.16

Power and System Management ................................................................................................... 25

2.9.17

General Purpose I/O ...................................................................................................................... 26

2.9.18

Module Type Definition ................................................................................................................ 27

2.9.19

Power and GND ............................................................................................................................ 27

2.10

Pin List for MSC 945GM module (Type 2) .......................................................................................... 28

3 Watchdog ...................................................................................................................................................... 30

4 System resources ........................................................................................................................................... 31

4.1

PCI Devices CXB-945 .......................................................................................................................... 31

4.2

Carrier Board PCI Resource Allocation ................................................................................................ 32

4.3

SMB Address Map ................................................................................................................................ 32

5 BIOS ............................................................................................................................................................. 33

5.1

Introduction ........................................................................................................................................... 33

5.1.1

Startup Screen Overview ............................................................................................................... 33

5.1.2

Activity Detection Background ..................................................................................................... 33

5.2

TrustedCore Setup Utility ..................................................................................................................... 34

5.2.1

Configuring the System BIOS ....................................................................................................... 34

5.2.2

The Main Menu ............................................................................................................................. 37

5.2.2.1

Board Information ............................................................................................................... 37

5.2.2.2

Masters & Slaves ................................................................................................................ 38

5.2.2.3

Boot Options ........................................................................................................................ 39

5.2.2.4

Keyboard Features ............................................................................................................. 39

5.2.3

The Advanced Menu ..................................................................................................................... 40

5.2.3.1

Cache Memory Control Menu ................................................................................................... 41

5.2.3.2

Yonah / Merom CPU Control Sub-Menu .................................................................................. 41

5.2.3.3

MCH Control Sub-Menu ........................................................................................................... 43

5.2.3.4

Video (Intel IGD) Control Sub-Menu ....................................................................................... 44

5.2.3.5

ICH Control Sub Menu ............................................................................................................. 45

5.2.3.6

ACPI Control Sub-Menu ........................................................................................................... 50

5.2.3.7

I/O Device Configuration Menu ................................................................................................ 51

5.2.3.8

Watchdog Options ..................................................................................................................... 52

3


5.2.4

The Security Menu ........................................................................................................................ 53

5.2.5

The Power Menu ........................................................................................................................... 54

5.2.5.1

Hardware Monitoring Menu ............................................................................................... 54

5.2.6

The Boot Menu ............................................................................................................................. 55

5.2.7

The Exit Menu............................................................................................................................... 56

5.3

Bios Update ........................................................................................................................................... 57

5.4

Bios Crisis Recovery ............................................................................................................................. 58

5.5

Diagnostics Postcodes ........................................................................................................................... 60

5.5.1

Bootblock Bios Postcodes ............................................................................................................. 60

5.5.2

System Bios Postcodes .................................................................................................................. 61

5.5.3

Memory Detection Postcodes ........................................................................................................ 64

5.5.4

ACPI Postcodes ............................................................................................................................. 64

4

MSC CXB-CD945 User's Manual General Information

1 General Information

1.1 Revision History

Rev. Date Responsible

0.1

0.2

0.3

0.4

0.5

22. Feb. 2007

26. Feb. 2007

Description

Initial version

Page size changed to DINA4

Minor fixes

0.6

0.7

0.8

1.0

13. March 2007 WST

31. May 2007

IFEL

1. June 2007

6. June 2007

New formatting

BIOS chapter integrated

Modifications

Bios Chapter updated

Review Version

Final Version

1.1

1.2

1.3

20. March 2008

14.08.2008

IFEL

10.11.2008 UGU

Preface added ALO

Bios Chapter updated, added crisis recovery and postcodes

Reset Signal definition corrected

1.4 2.2.2010 SVAN Bios chapter updated

1.5 8.2.2010 SVAN Updated System Resource table

1.6 6.5.2010 SVAN Minor fixes

1.2 Reference Documents

[1] COM Express Module Base Specification

COM Express Revision 1.0

Last update: July 10 th

, 2005

[2] PCI Local Bus Specification Rev. 2.1

PCI21.PDF

Last update: June 1 st

, 1995 http://www.pcisig.com

[3] ATA/ATAPI-6 Specification d1410r3b.pdf http://www.t13.org/

[4] Serial ATA Specification

Serial ATA 1.0 gold.pdf

Last update: August 29 th

, 2002 Rev.1.0 http://www.sata-io.org/

[5] IEEE Std. 802.3-2002

802.3-2002.pdf http://www.ieee.org

[6] Universal Bus Specification usb_20.pdf

Last update: April 27 th

, 2000 http://www.usb.org

5


1.3 Introduction

COM Express™, an open specification of the PICMG (PCI Industrial Computer

Manufacturer Group), is a module concept to bring PCI Express and other latest technologies like SATA, USB 2.0 and LVDS on a COM (Computer On Module).

A COM Express™ module is plugged onto an application-specific base board similar to the ETX concept, but offers more options and a growth path to future CPU technologies.

Utilizing different sizes, COM Express™ can be used for highly embedded solutions up to high performance platforms.

The design of the MSC CXB-CD945 module supports the dual core CPU technology enabling you to boost your embedded application to highest performance levels. For low power requirements we also support the LV-version in a single core configuration.

For evaluation and designin of the COM Express™ modules we provide evaluation baseboards and develop motherboards providing the interface infrastructure for the

COM Express™ module offering PC type connectors for external access.

Two module sizes are defined: the Basic Module and the Extended Module. The primary difference between the Basic Module and the Extended Module is the over-all physical size and the performance envelope supported by each. The Extended Module is larger and can support larger processor and memory solutions. The Basic Module and

Extended Module use the same connectors and pin-outs and utilize several common mounting hole positions. This level of compatibility allows that a carrier board designed to accommodate an Extended Module can also support a Basic Module.

Up to 440 pins of connectivity are available between COM Express™ modules and the

Carrier Board. Legacy buses such as PCI, parallel ATA, LPC, AC'97 are supported as well as new high speed serial interconnects such as PCI Express, Serial ATA and

Gigabit Ethernet.

To enhance interoperability between COM Express™ modules and Carrier Boards, five common signaling configurations (Pin-out Types) have been defined to ease system integration.

6

MSC CXB-CD945 User's Manual Technical Description

2 Technical Description

2.1 Key features

The MSC 945GM COM Express module is designed as a type 2 module.

Key features include

 Module size: 125 mm x 95 mm

 18 mm „z‟ height with heat-spreader (with 5 mm stack option)

 Dual 220 pin connector (440 pins)

 DDR2 SO-DIMM module

 8 USB 2.0 ports; 4 shared over-current lines

 2 Serial ATA ports

 4 PCI Express x1 lanes

 Support pins for up to 2 ExpressCards

 One dual 24-bit LVDS channel

 Analog VGA

 AC '97 / High definition digital audio interface (external CODEC)

 Single Ethernet interface with integrated PHY (Gigabit Ethernet option available)

 LPC interface

 8 GPIO pins

 +12V primary power supply input

 +5V standby and 3.3V RTC power supply inputs

 32 bit PCI interface

 IDE port (to support legacy ATA devices such as CD-ROM drives and Compact

Flash storage cards)

 20 PCI Express lanes (4 on A-B and 16 on C-D)

 16 of 20 PCI Express lanes used for PCI Express Graphics

 SDVO option (pins shared with PCI Express Graphics)

 TPM module (option, TPM 1.2, SLB9635)

7


2.2 Block diagram

Technical Description

8


2.3 COM Express implementation

COM Expre ss™ required and optional features of pin-out type 2 are summarized in the following table. The features identified as Minimum (Min.) shall be implemented by all modules. Features identified up to Maximum (Max) may be additionally implemented by a module.

The column MSC 945GM shows the implemented features of the MSC module:

System I/O

Type 2

Min / Max

PCI Express Graphics (PEG)

PCI Express Lanes 0 - 5

PCI Express Lanes 16-31

(same as PEG pins)

SDVO Channels

LVDS Channels

VGA Port

TV-Out

PATA Port

SATA Ports

AC‟97 Digital Interface

USB 2.0 Ports

LAN 0 (10/100Base-T min)

PCI Bus - 32 Bit

Express Card Support

LPC Bus

System Management

General Purpose Inputs

General Purpose Outputs

0 / 1

2 / 6

0 / 16

0 / 2

0 / 2

0 / 1

0 / 1

1 / 1

2 / 4

0 / 1

4 / 8

1 / 1

1 / 1

1 / 2

1 / 1

4 / 4

4 / 4

MSC 945GM

1

4 x1

1 x16

2

signals are multiplexed with

SDVO signals one lane optionally reserved for

GBit LAN

off-module x16 PCI Express

Graphics signals are multiplexed with

PEG signals

1x dual channel, 2x24 Bit

0

1

2

1

Note not implemented

4

1

8

1

1

AC97 or High Definition Audio

GBit option available

1

1

4

4

9


SMBus

I2C

Watch Dog Timer

Speaker Out

External BIOS ROM support

Reset Functions

Power Management

Thermal Protection

Battery Low Alarm

Suspend

Wake

Power Button Support

Power Good

1 / 1

1 / 1

0 / 1

1 / 1

0 / 1

1 / 1

0 / 1

0 / 1

0 / 1

0 / 2

1 / 1

1 / 1

1

1

1

1

1

1

1

1

1

1

1

2

CPUs

TPM

2.4 Functional units

0 / 0 1 optional TPM 1.2 module

Intel® Celeron® M 440 (Yonah,1.86 GHz, FSB 533MHz, 479µFCBGA)

Intel® Core™ Duo L2400 (Yonah, Low Voltage, 1.66 GHz, FSB

667MHz, 479µFCBGA)

Intel® Core™ Duo T2500 (Yonah,2.0 GHz, FSB 667MHz, 479µFCBGA)

Chipset Intel® 82945GM GMCH (Graphics Memory Controller Hub)

Memory

Intel® ICH7-M I/O Controller Hub

200-pin DDR2 SO-DIMM socket for up to 2GB (max. height 1250mil =

31.75mm)

PC5300 DDR2 SDRAM (DDR400/533/667)

SATA 2 SATA-2 channels up to 300MB/s each

EIDE 1 Enhanced IDE port ATA/UDMA100

USB 8 x USB 2.0

COM Express™ Type 2 interface, fully compliant

P CI Express™ Four channels, PCIe x1, one channel shared with GBit Ethernet option

PCI 32 Bit standard interface

10


LPC

Graphics

Controller

Video Memory

LCD Interface

Low Pincount Bus for heritage interfaces

Intel® Graphics Media Accelerator 950 (integrated in Intel® 945GM chipset)

UMA, up to 224 MB

LVDS 2x24Bit, dual channel, max. resolution 1.600 x 1.200

SDVO Interface 2 indepenent SDVO interfaces (SDVOB, SDVOC) or external PCIe x16 graphics (multiplexed by Intel® Graphics Media

Accelerator 950)

CRT Interface max. resolution 2.048 x 1.536

Ethernet 10/100Base-TX (Intel® 82562EZ) controller or

10/100/1000Base-TX (Intel® 82573E)

Sound Interface AC97 / High Definition Audio Interface

Watchdog Timer PIC12C509A

Creates system reset (programma ble, 1s … 255h)

TPM (option) Optional TPM module, TPM 1.2, SLB9635

Fan Supply 3-pin header (12V)

Real Time Clock

(RTC) integrated in ICH7-M

External Battery

System

Monitoring

Voltage , Temperature , Fan

 Core voltage

 3.3V

 1.5V

 0.9V

 2.5V

 CPU thermal diode

11


2.5 Power Supply

+12V primary power supply input

+5V standby

Option, is not required for module operation.

If not present, there is no support for power management states and ATX power supply functionality.

3.3V RTC power supply

Option, is not required for module operation.

BIOS SETUP data is stored in a non volatile backup memory device (EEPROM), therefore configuration data will not get lost during power off (except for time and date information)

Voltage Input range Current

+12V +11.4V - 12.6 V See next table

+5V Standby +4.75V - 5.25 V 150mA

+3V RTC power supply +2.0V - 3.3V max. 6µA

2.6 Power dissipation (DOS Prompt, 512MB DDR2 SO-DIMM)

Module (CPU) Voltage (V) Current (A) (typ.)

Intel® Celeron® M 440 (Yonah,1,86 GHz)

Intel® Core™ Duo L2400 (Yonah, Low Voltage,

1.66 GHz)

Intel® Core™ Duo T2500 (Yonah,2.0 GHz)

+12V

+12V

+12V

1,5A

1.2A

2 A

12


2.7 Mechanical Dimensions

Basic module


There are two height options defined in the COM Express specification : 5mm and 8mm.

The height option is defined by the connectors on the baseboard.

13


2.8 Thermal specifications

The cooling solution of a COM Express module is based on a heatspreader concept.

A heatspreader is a metal plate (typically aluminium) mounted on the top of the module.

The connection between this plate and the module components is typically done by thermal interface materials like phase change foils, gap pads and copper or aluminium blocks. A very good thermal conductivity is required in order to conduct the heat from the cpu and the chipset to the heatspreader plate.

The heatspreader of the MSC module is thermally attached using phase change materials and small aluminium blocks filling the gap between cpu and chipset dies and the heatspreader plate.

The heatspreader is not a heatsink! It is a defined thermal interface for the system designer with fixed mechanical dimensions, so it should be possible to change different module types without problems. There must be a cooling solution for the system, the surface temperature of the heatspreader should not exceed 60°C .

Main issue for the thermal functionality of a system is that each device of the module is operated within its specified thermal values. The max values of cpu and chipset are

100°C, so there may be system implementations where the heatspreader temperature could be higher.

But there are other chips on the module and it has to be validated that there are no thermal spec violations for these devices over the system temperature range.

14


2.9 Signal description

Pins are marked in the following tables with the power rail associated with the pin, and, for input and I/O pins, with the input voltage tolerance. The pin power rail and the pin input voltage tolerance may be different. For example, the PCI group is defined as having a 3.3V power rail, meaning that the output signals will only be driven to 3.3V, but the pins are tolerant of 5V signals.

An additional label, “Suspend” indicates that the pin is active during suspend states

(S3,S4,S5). If suspend modes are used, then care must be taken to avoid loading signals that are active during suspend to avoid excessive suspend mode current draw.

2.9.1 AC97 Audio / High Definition Audio

AC97 Audio / High

Definition Audio

Pin Type

AC_RST#

AC_SYNC

AC_BITCLK

AC_SDOUT

AC_SDIN[0:2]

O

CMOS

O

CMOS

I/O

CMOS

O

CMOS

I

CMOS

Pwr Rail /

Tolerance

Description

3.3V /3.3V Reset output to AC97 CODEC, active low.

Suspend

3.3V

3.3V/

3.3V/

/3.3V 48kHz fixed-rate, samplesynchronization signal to the

CODEC(s).

3.3V 12.228 MHz serial data clock generated by the external

CODEC(s).

3.3V Serial TDM data output to the

CODEC.

MSC

945GM device

ICH7-M

ICH7-M

ICH7-M

ICH7-M

3.3V/ 3.3V Serial TDM data inputs from up to

3 CODECs.

Suspend

ICH7-M

2.9.2 Ethernet

(Gigabit)

Ethernet

Pin

Type

GBE0_MDI[0

:3]+

GBE0_MDI[0

:3]-

I/O

Analog

GBE0_ACT# OD

CMOS

GBE0_LINK# OD

CMOS

Pwr Rail /

Tolerance

3.3V max

Suspend

3.3V /3.3V

Suspend

3.3V / 3.3V

Suspend

Description MSC

945GM device

Gigabit Ethernet Controller 0: Media

Dependent Interface Differential Pairs 0,1,2,3.

The MDI can operate in 1000, 100 and 10

Mbit / sec modes. Some pairs are unused in some modes, per the following:

82573 82562

1000BASE-T 100BASE-

TX

MDI[0]+/- B1_DA+/- TX+/-

10BASE-

T

TX+/-

MDI[1]+/- B1_DB+/-

MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

RX+/- RX+/-

Gigabit Ethernet Controller 0 activity indicator, active low.

Depends on LAN option,

82573 or

82562

82573 /

82562

Gigabit Ethernet Controller 0 link indicator, active low.

82573 /

82562

15


GBE0_LINK1

00#

GBE0_LINK1

000#

GBE0_CTRE

F

OD

CMOS

OD

CMOS

REF

3.3V / 3.3V

Suspend

3.3V / 3.3V

Suspend

GND min

3.3V max

Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.

Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.

82562 ( 100MBit) : floating

82573 (1000MBit) : 2,5V

82573 /

82562

82573 /

82562

82573 /

82562

2.9.3 IDE

IDE

IDE_D[0:15]

IDE_A[0:2]

IDE_IOW#

IDE_IOR#

IDE_REQ

IDE_ACK#

IDE_CS1#

IDE_CS3#

IDE_IORDY

IDE_RESET#

IDE_IRQ

IDE_CBLID#

Pin

Type

I/O

CMOS

O

CMOS

O

CMOS

O

CMOS

I

CMOS

O

CMOS

O

CMOS

O

CMOS

I

CMOS

O

CMOS

I

CMOS

I

CMOS

Pwr Rail /

Tolerance

Description MSC

945GM device

3.3V / 5V Bidirectional data to / from IDE device.

3.3V / 3.3V Address lines to IDE device.

3.3V / 3.3V I/O write line to IDE device.

Data latched on trailing (rising) edge.

3.3V / 3.3V I/O read line to IDE device.

3.3V / 5V IDE Device DMA Request.

It is asserted by the IDE device to request a data transfer.

3.3V / 3.3V IDE Device DMA Acknowledge.

3.3V / 3.3V IDE Device Chip Select for 1F0h to 1FFh range.

3.3V / 3.3V IDE Device Chip Select for 3F0h to 3FFh range.

3.3V / 5V IDE device I/O ready input.

Pulled low by the IDE device to extend the cycle.

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

3.3V / 3.3V Reset output to IDE device, active low.

3.3V / 5V Interrupt request from IDE device.

3.3V / 5V Input from off-module hardware indicating the type of IDE cable being used. High indicates a 40-pin cable used for legacy IDE modes.

Low indicates that an 80-pin cable with interleaved grounds is used. Such a cable is required for Ultra-DMA 66, 100 and 133 modes.

ICH7-M

ICH7-M

ICH7-M

16


2.9.4 Serial ATA


Serial ATA Pin

Type

Pwr Rail /

Tolerance

Description MSC

945GM device

ICH7-M SATA0_TX+

SATA0_TX-

O AC coupled Serial ATA Channel 0 transmit differential pair.

SATA on module

SATA0_RX+ I AC coupled Serial ATA Channel 0 receive differential pair.

SATA0_RX- SATA on module

SATA1_TX+

SATA1_TX-


SATA on module



SATA2_TX+

SATA2_TX-


SATA on module

ICH7-M

ICH7-M

ICH7-M

SATA2_RX+

SATA3_TX+

SATA3_TX-



ATA_ACT#

I


SATA on module

O

CMOS

AC coupled Serial ATA Channel 2 receive differential pair.

SATA2_RX- SATA on module not supported not supported not supported not supported not supported not supported not supported not supported

ICH7-M 3.3V / 3.3V ATA (parallel and serial) activity indicator, active low.

(SATALED#

)

17


2.9.5 PCI Express Lanes x1


PCI Express

Lanes

(Gen. Purpose)

Pin

Type

Pwr Rail /

Tolerance

Description

PCIE_TX[0:3]+ O AC coupled PCI Express Differential Transmit Pairs 0 through 3

PCIE_TX[0:3]- PCIE on module (0 through 2 with GigaBit Option)

PCIE_RX[0:3]+ I AC coupled PCI Express Differential Receive Pairs 0 through 3

PCIE_RX[0:3]- PCIE off module (0 through 2 with GigaBit Option)

PCIE_TX[4:5]+

PCIE_TX[4:5]- PCIE on module

PCIE_RX[4:5]+

O

I

AC coupled PCI Express Differential Transmit Pairs 4 through 5

AC coupled PCI Express Differential Receive Pairs 4 through 5

PCIE_RX[4:5]- PCIE off module

PCIE_TX[16:31]+ O AC coupled PCI Express Differential Transmit Pairs 16 through 31

PCIE_TX[16:31]- PCIE on module These are same lines as PEG_TX[0:15]+ and -

PCIE_RX[16:31]+ I AC coupled PCI Express Differential Receive Pairs 16 through 31

PCIE_RX[16:31]- PCIE off module These are the same lines as

PEG_RX[0:15]+ and -

PCIE_CLK_REF

+

PCIE_CLK_REF-

O

CMOS

3.3V / 3.3V Reference clock output for all PCI Express and

PCI Express Graphics lanes.

MSC

945GM device

ICH7-M

ICH7-M not supported not supported not supported not supported

945GM

GMCH

945GM

GMCH

CY28411

2.9.6 PCI Express Lanes x16

PCI Express

Lanes

Pin

Type

Pwr Rail /

Tolerance

Description x16 Graphics

PEG_TX[0:15]+

PEG_TX[0:15]-

O

PCIE

PEG_RX[0:15]+

PEG_RX[0:15]-

I

PCIE

AC coupled on module

PCI Express Graphics transmit differential pairs.

Some of these are multiplexed with SDVO lines (see SDVO section).

These are the same lines as

PCIE_TX[16:31]+ and - in module pin-out types 4 and 5.

AC coupled off module

PCI Express Graphics receive differential pairs.

Some of these are multiplexed with SDVO lines (see SDVO section).

These are the same lines as

PCIE_RX[16:31]+ and - in module pin-out types 4 and 5.

MSC

945GM device

945GM

GMCH

945GM

GMCH

18


PEG_LANE_RV# I

CMOS

PEG_ENABLE# I

CMOS

3.3V / 3.3V PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane order. Be aware that the

SDVO lines that share this interface do not necessarily reverse order if this strap is low.

3.3V / 3.3V Strap to enable PCI Express x16 external graphics interface. Pull low to disable internal graphics and enable the x16 interface.

945GM

GMCH

(CFG9)

ICH7-M

(GPI3)

2.9.7 Express Card Support

ExpressCard

Support

Pin

Type

Pwr Rail /

Tolerance

Description MSC

945GM device

ICH7-M EXCD[0]_CPPE#

I

I

CMOS

EXCD[1]_CPPE#

I

I

CMOS

EXCD[0]_RST# O

CMOS

EXCD[1]_RST# O

CMOS

3.3V / 3.3V PCI ExpressCard: PCI Express capable card request, active low, one per card

3.3V / 3.3V PCI ExpressCard: PCI Express capable card request, active low, one per card

3.3V / 3.3V PCI ExpressCard: reset, active low, one per card

3.3V / 3.3V PCI ExpressCard: reset, active low, one per card not supported

ICH7-M not supported

2.9.8 PCI Bus

PCI Bus Pin

Type

Pwr Rail /

Tolerance

Description

PCI_AD[0:31]

PCI_C/BE[0:3]# I/O

CMOS

PCI_DEVSEL# I/O

CMOS

PCI_FRAME# I/O

CMOS

PCI_IRDY#

I/O

CMOS

I/O

CMOS

PCI_TRDY#

PCI_STOP#

PCI_PAR

PCI_PERR#

I/O

CMOS

I/O

CMOS

I/O

CMOS

I/O

CMOS

PCI_REQ[0:3]#

PCI_GNT[0:3]#

I

CMOS

O

CMOS

3.3V / 5V PCI bus multiplexed address and data lines

3.3V / 5V PCI bus byte enable lines, active low

3.3V / 5V PCI bus Device Select, active low.

3.3V / 5V PCI bus Frame control line, active low.

3.3V / 5V PCI bus Initiator Ready control line, active low.

3.3V / 5V PCI bus Target Ready control line, active low.

3.3V / 5V PCI bus STOP control line, active low, driven by cycle initiator.

3.3V / 5V PCI bus parity

3.3V / 5V Parity Error: An external PCI device drives

PERR# when it receives data that has a parity error.

3.3V / 5V PCI bus master request input lines, active low.

3.3V / 5V PCI bus master grant output lines, active low.

MSC

945GM device

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

19


PCI_RESET#

PCI_LOCK#

O

CMOS

I/O

CMOS

PCI_SERR# I/O OD

CMOS

3.3V / 5V

Suspend

PCI Reset output, active low.

3.3V / 5V PCI Lock control line, active low.

PCI_PME# I

CMOS

PCI_CLKRUN# I/O

PCI_IRQ[A:D]#

CMOS

I

CMOS

PCI_CLK

PCI_M66EN

O

CMOS

I

CMOS

3.3V / 5V System Error: SERR# may be pulsed active by any PCI device that detects a system error condition.

3.3V / 5V

Suspend

PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states S1 –S5.

3.3V / 5V Bidirectional pin used to support PCI clock run protocol for mobile systems.

3.3V / 5V PCI interrupt request lines.

3.3V / 3.3V PCI 33MHz clock output.

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

3.3V / 5V Module input signal indicates whether an off-module PCI device is capable of

66MHz operation. Pulled to GND by

Carrier Board device or by Slot Card if the devices are NOT capable of 66 MHz operation.

If the module is not capable of supporting

66 MHz PCI operation, this input may be a no-connect on the module.

If the module is capable of supporting 66

MHz PCI operation, and if this input is held low by the Carrier Board, the module PCI interface shall operate at 33 MHz. not supported

20


2.9.9 USB

USB Pin

Type

Pwr Rail /

Tolerance


Description

USB[0:7]+

USB[0:7]-

USB_0_1_OC#

I/O

USB

I

CMOS

USB_2_3_OC# I

CMOS

USB_4_5_OC#

USB_6_7_OC#

I

CMOS

I

CMOS

3.3V / 3.3V

Suspend

USB differential pairs, channels 0 through

7

3.3V / 3.3V

Suspend

USB over-current sense, USB channels 0 and 1. A pull-up for this line is present on the module. An open drain driver from a

USB current monitor on the Carrier Board may drive this line low.

Do not pull this line high on the Carrier

Board.

3.3V / 3.3V

Suspend




Board.

3.3V / 3.3V

Suspend




Board.

3.3V / 3.3V

Suspend




Board.

MSC

945GM device

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

2.9.10 LVDS Flat Panel

LVDS Flat Panel Pin

Type

Pwr Rail /

Tolerance

Description

LVDS_A[0:3]+ O

LVDS_A[0:3]- LVDS

LVDS_A_CK+ O

LVDS_A_CK- LVDS

LVDS_B[0:3]+ O

LVDS_B[0:3]- LVDS

LVDS_B_CK+ O

LVDS_B_CK- LVDS

LVDS_VDD_EN O

CMOS

LVDS_BKLT_EN O

CMOS

LVDS Channel A differential pairs

LVDS Channel A differential clock

LVDS Channel B differential pairs

LVDS Channel B differential clock

3.3V / 3.3V LVDS panel power enable

3.3V / 3.3V LVDS panel backlight enable

MSC

945GM device

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

21


LVDS_BKLT_CT

RL

O 3.3V / 3.3V LVDS panel backlight brightness control

LVDS_I2C_CK

CMOS

O

CMOS

3.3V / 3.3V I2C clock output for LVDS display use

LVDS_I2C_DAT I/O OD 3.3V / 3.3V I2C data line for LVDS display use

CMOS


945GM

GMCH

945GM

GMCH

945GM

GMCH

2.9.11 LPC Bus

LPC Interface Pin

Type

Pwr Rail /

Tolerance

Description MSC

945GM device

ICH7-M LPC_AD[0:3]

LPC_FRAME#

LPC_DRQ[0:1]#

LPC_SERIRQ

LPC_CLK

I/O 3.3V / 3.3V LPC multiplexed address, command and data bus

CMOS

O

CMOS

3.3V / 3.3V LPC frame indicates the start of an LPC cycle

I

CMOS

3.3V / 3.3V LPC serial DMA request

I/O 3.3V / 3.3V LPC serial interrupt

CMOS

O

CMOS

3.3V / 3.3V LPC clock output - 33MHz nominal

ICH7-M

ICH7-M

ICH7-M

ICH7-M

2.9.12 Analogue VGA

Analog VGA Pin

Type

Pwr Rail /

Tolerance

Description MSC

945GM device

945GM

GMCH

VGA_RED

VGA_GRN

VGA_BLU

O

Analog

O

Analog

O

Analog

Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.

Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.

Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.

3.3V / 3.3V Horizontal sync output to VGA monitor VGA_HSYNC

VGA_VSYNC

VGA_I2C_CK

O

CMOS

O

CMOS

O

CMOS

VGA_I2C_DAT I/O OD

CMOS

3.3V / 3.3V Vertical sync output to VGA monitor

3.3V / 3.3V DDC clock line (I2C port dedicated to identify

VGA monitor capabilities)

3.3V / 3.3V DDC data line.

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

22


2.9.13 TV Out


TV Out

TV_DAC_A

TV_DAC_B

TV_DAC_C

Pin

Type

O

Analog

O

Analog

O

Analog

Pwr Rail /

Tolerance

Description MSC

945GM device

TVDAC Channel A Output supports the following not

Composite video: CVBS Component video: supported

Chrominance (Pb) analog signal

S-Video: not used

TVDAC Channel B Output supports the following:

Composite video: not used

Component video: Luminance (Y) analog signal

S-Video: Luminance analog signal. not supported

TVDAC Channel C Output supports the following:

Composite video: not used

Component: Chrominance (Pr) analog signal.

S-Video: Chrominance analog signal. not supported

2.9.14 SVDO

SDVO Pin

Type

Pwr Rail /

Tolerance

Description MSC

945GM device

945GM SDVOB_RED+ O AC coupled Serial Digital Video B red output differential pair

SDVOB_RED- PCIE on module Multiplexed with PEG_TX[0]+ and

PEG_TX[0]- pair

SDVOB_GRN+ O AC coupled Serial Digital Video B green output differential pair

SDVOB_GRN- PCIE on module Multiplexed with PEG_TX[1]+ and

PEG_TX[1]-

SDVOB_BLU+ O AC coupled Serial Digital Video B blue output differential pair

SDVOB_BLU- PCIE on module Multiplexed with PEG_TX[2]+ and

PEG_TX[2]-

SDVOB_CK+ O AC coupled Serial Digital Video B clock output differential pair.

SDVOB_CK- PCIE on module Multiplexed with PEG_TX[3]+ and

PEG_TX[3]-

SDVOB_INT+ I AC coupled Serial Digital Video B interrupt input differential pair.

SDVOB_INT- PCIE off module Multiplexed with PEG_RX[1]+ and

PEG_RX[1]-

SDVOC_RED+ O AC coupled Serial Digital Video C red output differential pair.

SDVOC_RED- PCIE on module Multiplexed with PEG_TX[4]+ and

PEG_TX[4]-

SDVOC_GRN+ O AC coupled Serial Digital Video C green output differential pair.

SDVOC_GRN- PCIE on module Multiplexed with PEG_TX[5]+ and

PEG_TX[5]-

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

945GM

GMCH

23


SDVOC_BLU+

SDVOC_CK+

O AC coupled Serial Digital Video C blue output differential pair.

SDVOC_BLU- PCIE on module Multiplexed with PEG_TX[6]+ and

PEG_TX[6]-

O AC coupled Serial Digital Video C clock output differential pair.

SDVOC_CK- PCIE on module Multiplexed with PEG_TX[7]+ and

PEG_TX[7]-

SDVOC_INT+ I AC coupled Serial Digital Video C interrupt input differential pair.

SDVOC_INT- PCIE off module Multiplexed with PEG_RX[5]+ and

PEG_RX[5]-

SDVO_TVCLKIN

+

SDVO_TVCLKIN

-

I

PCIE


Serial Digital Video TVOUT synchronization clock

input differential pair.

Multiplexed with PEG_RX[0]+ and

PEG_RX[0]-

SDVO_FLDSTAL

L+

SDVO_FLDSTAL

L-

I

PCIE

SDVO_I2C_CK O

CMOS

SDVO_I2C_DAT I/O OD

CMOS


Serial Digital Video Field Stall input differential pair.

Multiplexed with PEG_RX[2]+ and

PEG_RX[2]-

2.5V / 2.5V SDVO I2C clock line - to set up SDVO peripherals.

2.5V / 2.5V SDVO I2C data line - to set up SDVO peripherals.


945GM

GMCH

945GM

GMCH

945GM

GMCH not supported

945GM

GMCH

945GM

GMCH

945GM

GMCH

2.9.15 Miscellaneous

Miscellaneous Pin

Type

Pwr Rail / Description MSC 945GM device

Tolerance

I2C_CK

I2C_DAT

O

CMOS

I/O OD

CMOS

3.3V / 3.3V General purpose I2C port clock output

3.3V / 3.3V General purpose I2C port data I/O line

ICH7-M/

GPIO2

ICH7-M/

GPIO1

SPKR CMOS 3.3V / 3.3V Output for audio enunciator - the "speaker" in PC-AT systems

BIOS_DISABLE# I 3.3V / 3.3V Module BIOS disable input.

CMOS Pull low to disable module BIOS.

ICH7-M

Disables firmware hub

WDT

KBD_RST#

O

CMOS

I

CMOS

3.3V / 3.3V Output indicating that a watchdog time-out event has occurred.

PIC12C509

ICH7-M

KBD_A20GATE I

CMOS

3.3V / 3.3V Input to module from (optional) external keyboard controller that can force a reset.

Pulled high on the module. This is a legacy artifact of the PC-AT.

3.3V / 3.3V Input to module from (optional) external keyboard controller that can be used to control the CPU A20 gate line. The

A20GATE restricts the memory access to the bottom megabyte and is a legacy artifact of the PC- AT. Pulled high on the module.

ICH7-M

24


2.9.16 Power and System Management


Power and

System

Management

PWRBTN#

Pin

Type

Pwr Rail /

Tolerance

Description MSC 945GM device

SYS_RESET#

CB_RESET#

PWR_OK

SUS_STAT#

SUS_S3#

SUS_S4#

SUS_S5#

WAKE0#

WAKE1#

BATLOW#

I

CMOS

I

CMOS

O

CMOS

I

CMOS

O

CMOS

O

CMOS

O

CMOS

O

CMOS

I

CMOS

I

CMOS

I

CMOS

3.3V / 3.3V

Suspend

Power button to bring system out of S5

(soft off), active on rising edge.

3.3V / 3.3V

Suspend

Reset button input.

When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the

ICH attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts.

If at any point during the count the SMBus goes idle the reset occurs. If, however, the counter expires and the SMBus is still active, a reset is forced upon the system even though activity is still occurring.

Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYS_RESET# input remains asserted or not. It cannot occur again until

SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state.

This behavior is a result of Intel ICH internal chipset logic which is different to the COM Express Module Base

Specification stating that the system shall remain in reset as long as SYS_RESET# input is low.

3.3V / 3.3V

Suspend

Reset output from module to Carrier

Board. Active low. Issued by module chipset and may result from a low

SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.

3.3V / 3.3V Power OK from main power supply. A high value indicates that the power is good.

3.3V / 3.3V

Suspend

Indicates imminent suspend operation; used to notify LPC devices.

3.3V / 3.3V

Suspend

Indicates system is in Suspend to RAM state. Active low output.

3.3V / 3.3V

Suspend

Indicates system is in Suspend to Disk state. Active low output.

3.3V / 3.3V

Suspend

Indicates system is in Soft Off state. Also known as "PS_ON" and can be used to control an ATX power supply.

3.3V / 3.3V PCI Express wake up signal.

Suspend

3.3V / 3.3V

Suspend

General purpose wake up signal. May be used to implement wake-up on PS2 keyboard or mouse activity.

3.3V / 3.3V

Suspend

Indicates that external battery is low.

ICH7-M

ICH7-M

945GM

ICH7-M

FWH

LAN

TPM

LTC1727

ICH7-M

ICH7-M

ICH7-M

ICH7-M

ICH7-M

(82573)

ICH7-M

ICH7-M

25


THRM#

THERMTRIP#

I

CMOS

O

CMOS

3.3V / 3.3V Input from off-module temp sensor indicating an over-temp situation.

3.3V / 3.3V Active low output indicating that the CPU has entered thermal shutdown.

ICH7-M

(GPI12)

CPU

945GM

ICH7-M

ICH7-M SMB_CK I/O OD

CMOS

3.3V / 3.3V System Management Bus bidirectional

Suspend Rail clock line. Power sourced through 5V standby rail and main power rails.

SMB_DAT I/O OD

CMOS

3.3V / 3.3V System Management Bus bidirectional

Suspend Rail data line. Power sourced through 5V standby rail and main power rails.

SMB_ALERT# I

CMOS

3.3V / 3.3V System Management Bus Alert – active

Suspend Rail low input can be used to generate an SMI#

(System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.

ICH7-M

ICH7-M

2.9.17 General Purpose I/O

General

Purpose I/O

GPO[0:3]

GPI[0:3]

Pin

Type

O

CMOS

I

CMOS

Pwr Rail / Description MSC 945GM device

Tolerance

3.3V / 3.3V General purpose output pins. ICH7-M

Upon a hardware reset, these outputs are low.

GPIOs

[33,34,38,39]

3.3V / 3.3V General purpose input pins.

Pulled high internally on the module.

ICH7-M

GPIOs

[21,19,36,37]

26


2.9.18 Module Type Definition


Module Type

Definition

TYPE[0:2]#

Pin

Type

PDS

Pwr Rail /

Tolerance

Description MSC

945GM device

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) rare no-connects

(NC). For Pin-out Type 1, these pins are don‟t care (X).

TYPE2

#

X

TYPE1

#

X

TYPE0

#

X Pin-out Type 1

NC NC NC Pin-out Type 2

NC NC GND Pin-out Type 3

(no IDE)

NC GND NC Pin-out Type 4

(no PCI)

NC GND GND Pin-out Type 5

(no IDE, no PCI)

The Carrier Board should implement combinatorial logic that monitors the module

TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin- out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.

MSC

945GM

2.9.19 Power and GND

Power and GND Pin

Type

VCC_12V Power

VCC_5V_SBY Power

VCC_RTC

GND

Power

Power

Pwr Rail /

Tolerance

Description

Primary power input: +12V (+/- 5%)

Standby power input: +5.0V (+/- 5%)

If VCC5_SBY is used, all available

VCC_5V_SBY pins on the connector(s) shall be used.

Only used for standby and suspend functions.

May be left unconnected if these functions are not used in the system design.

Real-time clock circuit-power input : +3.0V

(+2.0V – 3.3V)

Ground - DC power and signal and AC signal return path. All available GND connector pins shall be used and tied to

Carrier Board GND plane.

MSC 945GM device

Voltage regulators

VCC3.3V

SUS regulator

ICH7-M

27


2.10 Pin List for MSC 945GM module (Type 2)

Row

A

A1

A2

A3

A4

A5

A6

A11

A12

A13

A18

A19

A20

A25

A26

A27

A34

A36

A37

A38

A39

GND (FIXED)

GBE0_MDI3-

GBE0_MDI3+

GBE0_LINK100#

GBE0_MDI2-

A7

A8

GBE0_MDI2+

GBE0_LINK#

A9 GBE0_MDI1-

A10 GBE0_MDI1+

GND (FIXED)

GBE0_MDI0-

GBE0_MDI0+

A14 GBE0_CTREF

A15 SUS_S3#

A16 SATA0_TX+

A17 SATA0_TX-

SUS_S4#

SATA0_RX+

SATA0_RX-

A21 GND (FIXED)

A22 SATA2_TX+

A23 SATA2_TX-

A24 SUS_S5#

SATA2_RX+

SATA2_RX-

BATLOW#

A28 ATA_ACT#

A29 AC_SYNC

A30 AC_RST#

A31 GND (FIXED)

A32 AC_BITCLK

A33 AC_SDOUT

BIOS_DISABLE#

A35 THRMTRIP#

USB6-

USB6+

USB_6_7_OC#

USB4-

Row

B

B1

B2

B3

B4

GBE0_LINK1000# B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B32

B33

B34

B35

GND (FIXED)

GBE0_ACT#

LPC_FRAME#

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_DRQ0#

LPC_DRQ1#

LPC_CLK

GND (FIXED)

PWRBTN#

SMB_CK

SMB_DAT

SMB_ALERT#

SATA1_TX+

SATA1_TX-

SUS_STAT#

SATA1_RX+

SATA1_RX-

GND (FIXED)

SATA3_TX+

SATA3_TX-

PWR_OK

SATA3_RX+

SATA3_RX-

WDT

B28 AC_SDIN2

B29 AC_SDIN1

B30 AC_SDIN0

B31 GND (FIXED)

SPKR

I2C_CK

I2C_DAT

THRM#

Row

C

C1

C2

GND (FIXED)

IDE_D7

C3 IDE_D6

C4 IDE_D3

C5 IDE_D15

C6 IDE_D8

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

IDE_D9

IDE_D2

IDE_D13

IDE_D1

GND (FIXED)

IDE_D14

IDE_IORDY

IDE_IOR#

PCI_PME#

PCI_GNT2#

PCI_REQ2#

PCI_GNT1#

PCI_REQ1#

PCI_GNT0#

GND (FIXED)

PCI_REQ0#

PCI_RESET#

PCI_AD0

PCI_AD2

PCI_AD4

PCI_AD6

PCI_AD8

PCI_AD10

PCI_AD12

GND (FIXED)

PCI_AD14

PCI_C/BE1#

PCI_PERR#

PCI_LOCK#

Row

D

D1

D2

GND (FIXED)

IDE_D5

D3 IDE_D10

D4 IDE_D11

D5 IDE_D12

D6 IDE_D4

D7

D8

D9

D10

IDE_D0

IDE_REQ

IDE_IOW#

IDE_ACK#

D11 GND (FIXED)

D12 IDE_IRQ

D13 IDE_A0

D14

D15

D16

D17

IDE_A1

IDE_A2

IDE_CS1#

IDE_CS3#

D18 IDE_RESET#

D19 PCI_GNT3#

D20 PCI_REQ3#

D21

D22

D23

D24

GND (FIXED)

PCI_AD1

PCI_AD3

PCI_AD5

D25 PCI_AD7

D26 PCI_C/BE0#

D27 PCI_AD9

D28

D29

D30

D31

PCI_AD11

PCI_AD13

PCI_AD15

GND (FIXED)

D32 PCI_PAR

D33 PCI_SERR#

D34 PCI_STOP#

D35 PCI_TRDY#

B36 USB7-

B37 USB7+

C36 PCI_DEVSEL# D36 PCI_FRAME#

C37 PCI_IRDY# D37 PCI_AD16

B38 USB_4_5_OC# C38 PCI_C/BE2#

B39 USB5- C39 PCI_AD17

D38

D39

PCI_AD18

PCI_AD20

A40 USB4+

A41 GND (FIXED)

A42 USB2-

A43 USB2+

A44 USB_2_3_OC#

A45 USB0-

A46 USB0+

B40 USB5+

B41 GND (FIXED)

B42 USB3-

B43 USB3+

B45 USB1-

B46 USB1+

C40 PCI_AD19

C41 GND (FIXED)

C42

C43 PCI_AD23

B44 USB_0_1_OC# C44 PCI_C/BE3#

C45

C46

PCI_AD21

PCI_AD25

PCI_AD27

A47 VCC_RTC B47 EXCD1_PERST# C47 PCI_AD29

A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 PCI_AD31

A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA#

A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB#

D40 PCI_AD22

D41 GND (FIXED)

D42 PCI_AD24

D43 PCI_AD26

D44 PCI_AD28

D45 PCI_AD30

D46 PCI_IRQC#

D47 PCI_IRQD#

D48 PCI_CLKRUN#

D49 PCI_M66EN

D50 PCI_CLK

= not supported on MSC 945GM module

28


Row

A

A51 GND (FIXED)

A52 PCIE_TX5+

A53 PCIE_TX5-

A54 GPI0

A55 PCIE_TX4+

A56 PCIE_TX4-

A57 GND

A58 PCIE_TX3+

A59 PCIE_TX3-

A60 GND (FIXED)

A61 PCIE_TX2+

A62 PCIE_TX2-

A63 GPI1

Row

B

B51 GND (FIXED)

B52 PCIE_RX5+

B53 PCIE_RX5-

B54 GPO1

B55 PCIE_RX4+

B56 PCIE_RX4-

B57 GPO2

B58 PCIE_RX3+

B59 PCIE_RX3-

B60 GND (FIXED)

B61 PCIE_RX2+

B62 PCIE_RX2-

B63 GPO3

A64 PCIE_TX1+

A65 PCIE_TX1-

A66 GND

A67 GPI2

A68 PCIE_TX0+

A69 PCIE_TX0-

A70 GND (FIXED)

B64 PCIE_RX1+

B65 PCIE_RX1-

B66 WAKE0#

B67 WAKE1#

B68 PCIE_RX0+

B69 PCIE_RX0-

B70 GND (FIXED)

A71 LVDS_A0+

A72 LVDS_A0-

A73 LVDS_A1+

A74 LVDS_A1-

B71 LVDS_B0+

B72 LVDS_B0-

B73 LVDS_B1+

B74 LVDS_B1-

A75 LVDS_A2+

A76 LVDS_A2-

B75

B76

LVDS_B2+

LVDS_B2-

A77 LVDS_VDD_EN B77 LVDS_B3+

Row

C

Row

D

C51 GND (FIXED) D51 GND (FIXED)

C52 PEG_RX0+ D52 PEG_TX0+

C53 PEG_RX0-

C54 TYPE0#

C55 PEG_RX1+

D53

D54

D55

PEG_TX0-

PEG_LANE_RV#

PEG_TX1+

C56 PEG_RX1-

C57 TYPE1#

C58 PEG_RX2+

C59 PEG_RX2-

D56 PEG_TX1-

D57 TYPE2#

D58 PEG_TX2+

D59 PEG_TX2-



C62 PEG_RX3-

C63 RSVD

D62

D63

PEG_TX3-

RSVD

C64 RSVD

C65 PEG_RX4+

C66 PEG_RX4-

D64 RSVD

D65 PEG_TX4+

D66 PEG_TX4-

C67 RSVD

C68 PEG_RX5+

D67 GND

D68 PEG_TX5+

C69 PEG_RX5- D69 PEG_TX5-


C71 PEG_RX6+

C72 PEG_RX6-

D71 PEG_TX6+

D72 PEG_TX6-

C73 SDVO_DATA D73 SDVO_CLK


C75 PEG_RX7-

C76 GND

C77 RSVD

D75

D76

D77

PEG_TX7-

GND

IDE_CBLID#

A78 LVDS_A3+

A79 LVDS_A3-

A80 GND (FIXED)

A81 LVDS_A_CK+

B78 LVDS_B3- C78 PEG_RX8+

B79 LVDS_BKLT_EN C79 PEG_RX8-

B80 GND (FIXED)

B81 LVDS_B_CK+

C80

C81

GND (FIXED)

PEG_RX9+

D78

D79

D80

D81

PEG_TX8+

PEG_TX8-

GND (FIXED)

PEG_TX9+

A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9-

A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 RSVD

A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND

D82

D83

D84

PEG_TX9-

RSVD

GND

A85 GPI3

A86 KBD_RST#

B85 VCC_5V_SBY

B86 VCC_5V_SBY

A87 KBD_A20GATE B87 VCC_5V_SBY

A88 PCIE0_CK_REF+ B88 RSVD

A89 PCIE0_CK_REF- B89 VGA_RED

A90 GND (FIXED) B90 GND (FIXED)

A91 RSVD B91 VGA_GRN

C85

C86

C87

C88

C89

C90

C91

PEG_RX10+

PEG_RX10-

GND

PEG_RX11+

PEG_RX11-

GND (FIXED)

PEG_RX12+

D85

D86

D87

D88

D89

D90

D91

PEG_TX10+

PEG_TX10-

GND

PEG_TX11+

PEG_TX11-

GND (FIXED)

PEG_TX12+

A92 RSVD

A93 GPO0

A94 RSVD

A95 RSVD

A96 GND

A97 VCC_12V

A98 VCC_12V

A99 VCC_12V

A100 GND (FIXED)

A101 VCC_12V

A102 VCC_12V

A103 VCC_12V

A104 VCC_12V

A105 VCC_12V

A106 VCC_12V

A107 VCC_12V

A108 VCC_12V

A109 VCC_12V

A110 GND (FIXED)

B92

B93

B94

B95

B96

B97

B98

B99

VGA_BLU

VGA_HSYNC

VGA_VSYNC

VGA_I2C_CK

VGA_I2C_DAT

TV_DAC_A

TV_DAC_B

TV_DAC_C

B100 GND (FIXED)

B101 VCC_12V

B102 VCC_12V

B103 VCC_12V

B104 VCC_12V

B105 VCC_12V

B106 VCC_12V

B107 VCC_12V

B108 VCC_12V

B109 VCC_12V

B110 GND (FIXED)

C92 PEG_RX12-

C93 GND

C94 PEG_RX13+

C95 PEG_RX13-

C96 GND

C97 RSVD

C98 PEG_RX14+

C99 PEG_RX14-



C102 PEG_RX15-

C103 GND

C104 VCC_12V

C105 VCC_12V

C106 VCC_12V

C107 VCC_12V

C108 VCC_12V

D92 PEG_TX12-

D93 GND

D94 PEG_TX13+

D95 PEG_TX13-

D96 GND

D97 PEG_ENABLE#

D98 PEG_TX14+

D99 PEG_TX14-

D102 PEG_TX15-

D103 GND

D104 VCC_12V

D105 VCC_12V

D106 VCC_12V

D107 VCC_12V

D108 VCC_12V

C109 VCC_12V D109 VCC_12V


= not supported on MSC 945GM module

29

MSC CXB-CD945 User's Manual Watchdog

3 Watchdog

The module has a watchdog function implemented using a PIC microcontroller with an

SMBus interface. Via SETUP the watchdog can be enabled and configured.

If the watchdog is enabled a counter is started which creates a reset if it is not retriggered within a programmable time window.

The watchdog menu in the BIOS provides the following parameters:

Watchdog:

Initial Delay:

Timeout:

Enabled / Disabled (default)

1s, 5s, 10s, 30s (default), 1min, 5min, 10min, 30min

0,4s, 1s, 5s, 10s, 30s (default), 1min, 5 min, 10min

Start on Boot: if yes, watchdog starts at the end of POST (power on selftest) before the OS is loaded

ICH7M Pin

GPIO6

GPIO9

GPIO7

Label

WDEN

Description

Watchdog Enable. 1 = watchdog counter counts

WDTRIG Watchdog Trigger. If watchdog is enabled (WDEN=1), the signal level on this line has to be inverted within the timeout delay to trigger this chip (which means to avoid to get a reset)

WDSTS Watchdog Status. 0 = no Timeout , Default after Power-Up or after setting of Bit0.

1 = Timeout event has occurred; a reset has been triggered. In this case, the watchdog counter will be stopped.

Please find programming information, register layout etc. in the datasheet of the ICH7-M.

The timeout and the delay time can be written into the watchdog controller via the SMB.

The register layout is as follows:

Address

0

1

2

3

Data Byte

TimeOut low Byte

TimeOut high Byte

Delay low Byte

Delay high Byte

Default value

100d

0

100d

0

Read/

Write

W

W

W

W

Bit

Byte

Byte

Byte

Byte

Remark

The SMB-Address of the watchdog controller is B0h/B1h. The data structure to access the byte registers is:

Device Address B0 - Register Address - Data Byte

Reading these registers is not supported. While writing into these registers, the watchdog timer has to be stopped.

For information about accessing the SMB please consult the Intel® ICH7-M datasheet.

30


4 System resources

4.1 PCI Devices CXB-945

Slot Number

(or Onboard

Device)

IDSEL # or

DEV. #

1

2

3

4

AD20 /

Dev 04h

AD21 /

Dev 05h

AD22 /

Dev 06h

AD23 /

Dev 07h

Dev 02h Internal

Graphic

Device

PCI Express

Root Port

USB UHCI

Host Controller

USB UHCI

Host Controller

Dev 28 Fkt

0/1/2/3

Dev 29 Fkt 0

Dev 29 Fkt 1

USB UHCI

Host Controller

USB UHCI

Host Controller

USB EHCI

Controller

Dev 29 Fkt 7

AC ‟97 Audio Dev 30 Fkt 2

SATA

PATA

Dev 31 Fkt 2

Dev 31 Fkt 1

SMBus

100MB Lan

Controller

PCIe Slot 1

PCIe Slot 2

PCIe Slot 3

PCIe Slot 4

Or

GB Lan

Controller

Dev 29 Fkt 2

Dev 29 Fkt 3

Dev 31 Fkt 3

Dev 8 Fkt 0

Dev 0 Fkt 0

Dev 0 Fkt 0

Dev 0 Fkt 0

Dev 0 Fkt 0

-

-

-

-

0

0

0

0

0

0

0

0

0

0

0

-

-

-

-

-

Interrupts of Controller (ICH-7M)

A

D

B

A

C D

C

B

A

D

C

B

B

A

C D

-- --

A

--

System resources

A B C D

A

D

C

B

B

A

D

C

C

B

A

D

D

C

B

A

A

A

B

B

B

B

C

D

A

D

31

MSC CXB-CD945 User's Manual System resources

4.2 Carrier Board PCI Resource Allocation

The external PCI resource allocation on the carrier board should be as follows:

The signals PCI_IRQx, PCI_REQx or PCI_GNTx are are routed exclusively to the COM

Express connector. They are not shared on the CPU board.

4.3 SMB Address Map

Device A6 A5 A4 A3 A2 A1 A0 R/W

SMBus host

(ICH7-M slave)

Winbond

W83L786R

Watchdog

(PIC12C509)

CY28411 Clock

Synthesizer

CY25823 Clock

Synthesizer

CMOS backup

EEPROM

0

0

1

1

1

1

0

1

0

1

1

0

0

0

1

0

0

1

1

1

1

1

1

0

0

1

0

0

0

1

0

1

0

0

1

0

0

0

0

1

0

0 x x x x x x

SPD EEPROM

(SO-DIMM)

1 0 1 0 0 0 0 x

*) 8 bit address (with R/W) / 7 bit address (without R/W) address *)

10h / 08h

5Ch / 2Eh

B0h / 58h

D2h / 69h

D4h / 6Ah

A8h / 54h

A0h / 50h

32

MSC CXB-CD945 User's Manual BIOS

5 BIOS

5.1 Introduction

This guide describes the Phoenix TrustedCore Startup screen and contains information on how to access Phoenix TrustedCore setup to modify the settings which control

Phoenix pre-OS (operating system) functions.

5.1.1 Startup Screen Overview

The Phoenix TrustedCore Startup screen is a graphical user interface (GUI) that is included in Phoenix TrustedCore products. The default bios behavior is to show an informational text screen during bios POST phase, but the graphical boot screen can be enabled in the bios setup. The standard boot screen is a black screen, including a progress bar at the bottom of the screen. This bar indicates the progress of the Startup

Screen functions and provides user prompting and POST status. The following figure shows the various parts of a generic Startup Screen at 1024x768 resolution:

5.1.2 Activity Detection Background

While the TrustedCore Startup screen is displayed, press the Setup Entry key (F2 –

TrustedCore default). The TrustedCore Startup Status Bar acknowledges the input, and at the end of POST, the screen clears and setup launches.

An example of the Startup Status Bar displaying changing state is shown in the following figure. The “Please Wait…” text is displayed after the F2 key is pressed to acknowledge user input.

Active status bar:

33


5.2 TrustedCore Setup Utility

With the Phoenix TrustedCore Setup program, you can modify TrustedCore settings and control the special features of your computer. The Setup program uses a number of menus for making changes and turning the special features on or off. This chapter provides an overview of the Setup utility and describes at a high-level how to use it.

5.2.1 Configuring the System BIOS

To start the Phoenix TrustedCore Setup utility, press [F2] to launch Setup. The Setup main menu appears.

The BIOS Menu Structure

The BIOS Menu is structured in the following way:

Main

Board Information

IDE Channel 0 Master

IDE Channel 0 Slave

SATA Port 0

SATA Port 1

Boot Options

Keyboard Features

Advanced

Cache Memory

CPU Control Sub-Menu

MCH Control Sub-menu

Video (Intel IGD) Control Sub-menu

ICH Control Sub-menu

PCI Express Control Sub-menu

PCI Control Sub-menu

ICH USB Control Sub-menu

ACPI Control Sub-menu

I/O Device Configuration

Watchdog Options

Security

Power

Hardware Monitor

Boot

Exit

34


The Menu Bar

The Menu Bar at the top of the window lists these selections:

Menu Items Description

Main Use this menu for basic system configuration.

Advanced

Security

Power

Boot

Use this menu to set the Advanced Features available on your system‟s chipset.

Use this menu to set User and Supervisor Passwords and the

Backup and Virus-Check reminders.

Use this menu to configure Power-Management features.

Use this menu to set the boot order in which the BIOS attempts to boot to OS.

Exit Exits the current menu.

Use the left and right arrow keys on your keyboard to make a menu selection.

The Legend Bar

Use the keys listed in the legend bar on the bottom of the screen to make your selections, or to exit the current menu. The following table describes the legend keys and their alternates:

Key Function

F1 or Alt-H

Esc

Arrow keys

Up and down arrow keys

Tab or Shift-Tab

Home or End

PgUp or PgDn

F5 or -

F6 or + or Space

F9

F10

Enter

General Help window.

Exit this menu.

Select a different menu.

Move cursor up and down.

Move cursor left and right (i.e. at System Time / System Date).

Move cursor to top or bottom of window.

Move cursor to next or previous page.

Select the previous value for the field.

Select the next value for the field.

Load the Default Configuration values (for all menus).

Save and exit.

Execute command or select submenu.

35


Select an item

To select an item, use the arrow keys to move the cursor to the field you want. Then use the plus-and-minus value keys to select a value for that field. The Save Values commands in the Exit Menu save the values currently displayed in all the menus.

Display a submenu

To display a submenu, use the arrow keys to move the cursor to the sub menu you want.

Then press Enter. A pointer marks all submenus.

36


CPU String

CPU Speed

CPU Class

CPU Model

CPU Stepping

CPU Cores

Northbridge

Southbridge

System Memory

Extended Memory

Informative

Informative

Informative

Informative

Informative

Informative

Informative

Informative

Informative

Informative

5.2.2 The Main Menu

You can make the following selections on the Main Menu itself. Use the sub menus for other selections.

Feature Options Description

Board Information Submenu Displays BIOS Version

System Time

System Date

IDE Channel 0 Master

IDE Channel 0 Slave

SATA Port 0

SATA Port 1

Enter Time (HH:MM:SS) Set the System Time.

Enter Date (DD/MM/YYYY) Set the System Date.

Submenu “Master & Slaves” Configure IDE Channel 0 Master

Submenu “Master & Slaves” Configure IDE Channel 0 Slave

Submenu “Master & Slaves” Configure SATA Port 0

Submenu “Master & Slaves” Configure SATA Port 1

Configure Boot Options Boot Options

5.2.2.1 Board Information

Feature

Submenu

Options Description

Bios Version

HW Platform

HW Revision

Serial #

Boot Counter

Informative

Informative

Informative

Informative

Informative

Shows current bios version.

Name of the hardware platform

Hardware revision number

Hardware Serial Number

The number of times this board has booted up.

CPU Identification string

CPU Speed

CPU ID Class code

CPU ID Model code

CPU ID Stepping

Number of CPU cores

Identification of the northbridge

Identification of the southbridge

Amount of memory below 1MB

Total amount of memory

37


5.2.2.2 Masters & Slaves

The Master and Slave settings on the Main Menu control these types of devices:

• Hard-disk drives (IDE and SATA)

• Removable-disk drives

• CD-ROM drives

There is one IDE connector on your motherboard, usually labeled "Primary IDE". There are usually two connectors on each ribbon cable attached to IDE connector. When you have connected two drives to this connector, the one on the end of the cable is the

Master.

When you enter Setup, the Main Menu displays the results of Autotyping information each drive provides about its own size and other characteristics

–and how they are arranged as Masters or Slaves on your machine.

Note : Do not attempt to change these settings unless you have an installed drive that does not autotype properly (such as an older hard-disk drive that does not support autotyping).

If you need to change your drive settings, select one of the Master or Slave drives on the

Main Menu. This will display a menu like this:

Note: The capacity is displayed in „real‟ Mbytes (1MB=1024*1024 Bytes) Drives with a total capacity greater than 8Gbyte operate in LBA format only.


Type None,

Auto,

User,

IDE Removable,

ATAPI Removable,

Other ATAPI,

CD-ROM

Cylinders

Heads

Sectors

Multi-Sector Transfers

LBA Mode Control

1 to 65536

1 to 16

1 to 63

Disabled, 2 sectors,

4 sectors, 8 sectors,

16 sectors

Disabled, Enabled

None = Autotyping is not able to supply the drive type or end user has selected None, disabling any drive that may be installed.

Auto = Autotyping, the drive itself supplies the information.

User = You supply the hard-disk drive information in the following fields.

IDE Removable = Removable Disk

Drive

ATAPI Removable = Removable Disk

Drive

Other ATAPI = non-specific ATAPI

Device

CD-ROM = CD-ROM drive.

Number of Cylinders

Number of read/write heads

Number of sectors per track

Any selection except Disabled determines the number of sectors transferred per block.

Enabling LBA causes Logical Block

Addressing to be used in place of

Cylinders, Heads, & Sectors.

38



32 Bit I/O

Transfer Mode

Ultra DMA Mode

Disabled, Enabled

Standard

Fast PIO 1

Fast PIO 2

Fast PIO 3

Fast PIO 4

FPIO 3 / DMA 1

FPIO 4 / DMA 2

Disabled

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Enables 32-bit communication between CPU and IDE card. Requires

PCI or local bus.

Selects the method for transferring the data between the hard disk and system memory.

The Setup menu only lists those options supported by the drive and platform.

Ultra DMA Mode supports 33/66/100

MB/sec transfer rate for fixed disk drives.

SMART Monitoring Disabled, Enabled Displays the status of SMART

Monitoring if supported by the used drive.

WARNING: Incorrect settings can cause your system to malfunction.

5.2.2.3 Boot Options


Summary screen Disabled, Enabled

Boot-time Diagnostic

Screen

Post Errors

Disabled, Enabled

Disabled, Enabled

Extended Memory Testing Normal, Just zero it, None

Enabled displays system configuration on boot.

Enabled displays the diagnostic screen during boot.

Disabled displays the Boot Logo.

Pauses and displays Setup entry or resume boot prompt if error occurs on boot. If disabled, system always attempts to boot.

Determines which type of test will be performed on extended memory during

POST (above 1 MB).

5.2.2.4 Keyboard Features

Feature

NumLock

Key Click

Options

On, Off

Disabled, Enabled

Description

Selects Power-on state for NumLock

Enables key Click

39


Keyboard auto-repeat delay

Feature Options

Keyboard auto-repeat rate 30/s, 26.7/s, 21.8/s, 18.5/s,

13.3/s, 10/s, 6/s, 2/s

1/4s, 1/2s, 3/4s, 1s

Description

Selects key repeat rate

Selects delay before key repeat

5.2.3 The Advanced Menu

Feature

Installed O/S Other,

Win95,

Win98,

WinMe,

Win2000,

WinXP

Options

Reset configuration Data No, Yes

Large Disk Access Mode Other, DOS

Small Disk Access Mode No, Yes

Port 80 Cycles

Local Bus IDE adapter

LPC Bus, PCI Bus

Disabled, Enabled

Cache Memory Submenu

Yonah / Merom CPU

Control Sub-Menu

Submenu

MCH Control Sub-Menu Submenu

Video (Intel IGD) Control

Sub-Menu

Submenu

Description

Select the operating system installed on your system which you will use most commonly.

NOTE: An incorrect setting can cause some operating systems to display unexpected behavior.

Select „Yes‟ if you want to clear the

Extended System Configuration Data

(ESCD) area.

Select Other for UNIX, Novell

NetWare. Select DOS for all other operating systems.

Select if CHS translation should be made for a LBA-capable harddisk with less than 1024 cylinders, e.g.

CompactFlash(R). If you have problems with booting from a

CompactFlash(R), try to change this setting.

No = translate CHS only if HDD has

>1024 cyls.

Yes = translate CHS for all LBAcapable disks.

Control where the Port 80h cycles are sent.

Enable the integrated local bus IDE adapter.

Configure Cache Memory

Configure Yonah / Merom CPU

Control

Configure MCH Control

Configure Video (Intel IGD) Control

40


Feature

ICH Control Sub-Menu Submenu

ACPI Control Sub-Menu Submenu

I/O Device Configuration Submenu

Options

Watchdog Options Submenu

5.2.3.1 Cache Memory Control Menu

Feature Options

Cache System BIOS area Uncached,

Write Protect

Description

Configure ICH Control

Configure ACPI Control

Configure I/O Device

Configure Watchdog Options

Description

Enables caching of system BIOS area.

Cache Video BIOS area Uncached,

Write Protect

Enables caching of video BIOS area.

Cache D000 – D3FF

Cache D400 – D7FF

Cache D800 – DBFF

Disabled,

Write Through,

Write Protect,

Write Back

Disabled = This block is not cached.

Write through = Writes are cached and sent to main memory at once.

Write Protect = Writes are ignored.

Write Back = Writes are cached but not sent to main memory until necessary.

5.2.3.2 Yonah / Merom CPU Control Sub-Menu

Note: Depending on the CPU type you are using some options of the Control Sub-Menu can be hidden in consequence of different CPU type features that exist.


Core Multi Processing Disabled, Enabled Determines whether the 2 nd

core is enabled.

Disabled = 2nd core is disabled

Enabled = 2nd core is enabled

41


Feature

Processor Power

Management

Options

Disabled,

GV3 only,

C-States Only,

Enabled

Enhanced C-States

Enable

Timestamp Counter

Updates

Thermal Control Circuit

PROCHOT# Enable

Disabled, Enabled

Disabled, Enabled

Disabled,

TM1,

TM2,

TM1 and TM2

Disabled, Enabled

Description

Selects the Processor Power

Management desired:

Disabled = C-States and GV3 are disabled.

GV3 Only = C-States are disabled.

C-States Only = GV3 is disabled.

Enabled = C-States und GV3 are enabled.

Note: GV3 refers to the speed step capability of the CPU.

Note: If GV3 is disabled, OS will not run with maximum frequency. To use maximum frequency, GV3 has to be enabled and OS must Control the CPU frequency via Power managment.

Note: For optimal response times the

GV3 (Speed step) must be enabled and C-States disabled.

Enables Enhanced C-State support.

Disabled = Enhanced C-States disabled.

Enabled = Enhanced C-State enable.

Control TSC updates after C3/C4 through this Setup Option.

Setting this bit enables the thermal control circuit (TCC) portion of the

Thermal Monitor feature of the CPU.

TM1 = 50% duty Cycle

TM2 = Geyserville III

Enables the processors‟s PROCHOT# signal.

If asserted, the TMx circuit will be engaged.

PROCHOT# is in addition to the TCC and Enhanced TCC circuitry inside the processor, and either may engage

TMx.

42


Feature

DTS Enable

Options

Disabled, Enabled

No Execute Mode Mem

Protection

Intel (R) Virtualization

Technology

Set Max Ext CPUID = 3

Enabled, Disabled

Disabled, Enabled

Disabled, Enabled

5.2.3.3 MCH Control Sub-Menu

Feature

PCI Express Graphics

Port

Options

Disabled, Auto

Port ASPM Support Disabled, Auto

GPLL Power-Down

Enable:

Disabled, Enabled

MDA Support Disabled, Enabled

Description

Enabled the Yonah DTS to be used for platform Thermal Management.

Sets Max CPUID extended function value to 3.

Description

Disabled = Port always disabled.

Auto = Only enable if card found.

Control ASPM support for the PEG

Device.

Auto = will set APMC to the highest common supported ASPM between the Port and Endpoint.

Controls the ability of the PEG port to power down the GPLL.

Disabled = The GPLL will always remain actice.

Enabled = The GPLL may be powered down.

Control MDA support for the PEG

Device.

43


5.2.3.4 Video (Intel IGD) Control Sub-Menu

Feature Options

Default Primary Video

Adapter

IGD, PEG

Description

Select „IGD‟ to have Internal Graphics, if supported and enabled, be used for the boot display device.

Select „PEG‟ to have PCI Express

Graphics, if supported and enabled, be used for the boot display device.

To use PCI Video, select IGD.

IGD

IGD

IGD

IGD

IGD

IGD

– Device 2

– Boot Type

– LCD Panel Type

– Panel Scaling

– Backlight

Brightness

Disabled, Auto

– Device 2, Function1 Disabled, Auto

Enables or Disable the Internal

Graphics Device by setting item to the desired value.

Enables or Disable Function 1 of the

Internal Graphics Device by setting item to the desired value.

Select the Video Device that will be activated during POST.

VBIOS default,

CRT,

LFP,

EFP,

EFP2,

CRT+LFP,

CRT+EFP,

CRT+EFP2

640x480 1 PPC, 18b

800x600 1 PPC, 18b

1024x768 1 PPC, 18b

1280x1024 2 PPC, 18b

1400x900 2 PPC, 24b

1400x1050 2 PPC, 24b

1600x1200 2 PPC, 24b

1280x1024 2 PPC, 24b

1024x768 1 PPC, 24b

10: Reserved

11: Reserved

12: Reserved

13: Reserved

14: Reserved

15: Reserved

16: Reserved

Auto, Force Scaling, Off

Select the LCD panel used by the

Internal Graphics Device by selecting the appropriate setup item.

The first item is Panel 1, the last item is Panel 16.

Some Panels are not numbered due to size constraints.

Note: Due to size constrains not all

Panels are exactly numbered. The first item is Panel 1, the last one Panel 16.

0%, 10%, 20%, 30%, 40%,

50%, 60%, 70%, 80%, 90%,

100%

Selects the LCD panel scaling option used by the Internal Graphics Device.

1. Auto

2. Force Scaling

3. Off

Select the starting brightness for the

LVDS backlight signal.

Note: some backlight inverters use an inverted level for brightness control – please check the inverter spec. for the display panel

44


Size

Feature

Spread Spectrum Clock

Chip

DVMT 3.0 Mode

Pre-Allocated Memory

Options

Off, Hardware, Software

Fixed, DVMT, Combo

1 MB, 8 MB

Total graphics Memory 64MB, 128 MB, MaxDVMT

Description

Control programming of the Spread

Spectrum Clock Chip.

Hardware = Spread is Chip Controlled.

Software = Spread is BIOS Controlled with the following supported ranges:

Down Spread: 0.8% - 3.0%.

Center Spread: 0.3% - 1.5%.

Select the configuration of DVMT 3.0

Graphics Memory that Driver will allocate for use by the Internal

Graphics Device. 1. Fixed

2. DVMT

3. Combo

Select the amount of Pre-Allocated

Graphics Memory for use by the

Internal Graphics Device.

Select the amount of Total Graphics

Memory

Pre-Allocated + Fixed + DVMT for use by the Internal for use by the Internal

Graphics Device.

Displays the Memory size of the Video device.

DVMT Graphics Memory N/A

5.2.3.5 ICH Control Sub Menu

Feature

Submenu. PCI Express Control

Submenu

PCI Control Submenu Submenu

Options

ICH USB Contol Submenu Submenu

Azalia – Device 27,

Function 0

Disabled, Auto

Description

Configure PCI Express Control

Configure PCI Control

Configure ICH USB Control

Control Detection of the Azalia Device.

Disabled = Azalia will be unconditionally disabled, regardless of presence.

Auto = Azalia will be enabled if present, disabled otherwise.

45


Feature

AC97A – Device 30,

Function 2

AC97M – Device 30,

Function 3

AC97 Modem PNE Enable Disabled, Enabled

SATA – Device 31,

Function 2

Compatible, Enhanced

AHCI Configuration

Disable Vacant Ports

On –board LAN

PXE OPROM

Disabled, Auto

Options

Disabled, Auto

Disabled, Enabled

Disabled, Enabled

Disabled, Enabled

Disabled, Enabled

Description

Control Detection of the AC97 Audio

Device.

Disabled = AC97 Audio will be unconditionally disabled, regardless of presence.

Auto = AC97 Audio will be enabled if present, disabled otherwise.

Control Detection of the AC97 Modem

Device.

Disabled = AC97 Modem will be unconditionally disabled, regardless of presence.

Auto = AC97 Modem will be enabled if present, disabled otherwise.

Control the ability to wake the System from an AC97 Modem Device

Compatible:

SATA Drive = Primary on SATA

Controller, in Legacy Mode.

PATA Drive = Secondary on SATA

Controller, in Legacy Mode

Enhanced:

SATA Drive = Primary on SATA

Controller, in Native Mode.

PATA Drive = Primary on PATA

Controller, in Legacy Mode

Enhanced AHCI:

WinXP-SP1+IAA driver supports AHCI mode.

Controls automatic disabling if vacant

SATA ports.

Setting item to “Disabled” will remove the LAN from PCI Config Space.

Setting item to “Enabled” will allow the

LAN to operate correctly.

Enable PXE Option ROM.

46


Feature

Pop Up Mode Enable

Options

Disabled, Enabled

Description

Pop Down Mode Enable Disabled, Enabled

DMI Link ASPM Support Enabled, Disabled

Select the proper mode:

If disabled, bus master traffic is a break event and it will return from

C3/C4 to C0 based on break events.

If enabled, ICH will observe a bus master request and it will take the system from a C3/C4 state to a C2 state and auto enable bus masters.

Should be enabled only if Pop up is enabled:

If disabled, ICH will NOT attempt to automatically return.

If enabled, ICH will observe a NO bus master request and it can return to a previous C3 or C4 state.

Control ASPM support for DMI link between GMCH and ICH.

5.2.3.5.1 PCI Express Control Sub-Menu

Feature

PCI Express – Root Port

1-4

Root Port ASPM Support

Options

Disabled,

Enabled,

Auto

Disabled, Auto

Description

Control PCI Express Port via this setup option.

Disabled = Port always Disabled.

Auto = Only enable if card found.

Note that if Root Port 1 is disabled

Root Ports 2-4 will be disabled as well.

Control ASPM support for all the enabled Root Ports.

Auto = will set APMC to the highest common supported ASPM between the Port and Endpoint.

ASPM Latency Checking Disabled, Enabled Disabled:

ASPM latencies are ignored when enabling ASPM.

Enabled:

Enables ASPM latency checking when enabling ASPM.

Note: Does not check below switches.

47


5.2.3.5.2 PCI Control Sub-Menu

Feature

PCI IRQ line 1


Disabled, Auto Select, 3, 4, 5,

6, 7, 10, 11, 12

Select which Interrupt should be assigned to this PCI Irq.

Devices:IGD, PEG Port, PCI Slot 1,

PCIe Port1, PCIe Port5

PCI IRQ line 2

PCI IRQ line 3

PCI IRQ line 4

PCI IRQ line 5

PCI IRQ line 6

PCI IRQ line 7

PCI IRQ line 8

PCI-Bridge SERR propagation


6, 7, 10, 11, 12


Devices: PCI Slot 2, PCIe Slot2,

PCIe Port 6


6, 7, 10, 11, 12


Devices: PCI Slot 3, PCIe Port 3


6, 7, 10, 11, 12


Devices: PCI Slot 4, PCIe Port 4


6, 7, 10, 11, 12


Devices: UHCI Controller 1,

Internal Lan Controller


6, 7, 10, 11, 12



PATA/SATA Controller, SMBus


6, 7, 10, 11, 12



HD Audio or AC97 Audio


6, 7, 10, 11, 12


Devices: UHCI Controller 4, EHCI

Controller, AC97 Modem

Disabled, Enabled Select if the PCI bridge should forward the SERR signal from the secondary bus to the primary bus.

48


5.2.3.5.3 ICH USB Control Sub-Menu

Feature Options

USB 1.1 Controllers

USB 2.0 Controller

Boot from USB Port 1

Description

Enable 1, Enable 2, Enable 3,

Enable 4

Select the number of UHCI controllers that should be enabled.

Enable, Disable

Enable, Disable

Control USB 2.0 functionality through this Setup Item.

Set the boot capability for this usb port

When set to disabled, mass storage devices will not be able to boot from this port.

Boot from USB Port 2 Enable, Disable




Enable, Disable

Enable, Disable

Enable, Disable












Enable, Disable

Enable, Disable

Enable, Disable







49


5.2.3.6 ACPI Control Sub-Menu

Feature

Enable ACPI

Disable ACPI _Sx

FACP – RTC S4 Flag

Value


No, Yes En/Disable ACPI BIOS (Advanced

Configuration and Power Interface)

None, S1, S2, S3 Select one of the ACPI power states:

S1, S2, or S3. If selected, the corresponding power state will be disabled.

Disabled, Enabled Valid only for ACPI

Control the value for the RTC S4 flag in the FACP Table

FACP – PM Timer Flag

Value

HPET Support

HPET Base Address

Disabled, Enabled Valid only for ACPI

Controls the timer used by the OS through the FACP Tables Flags.

This is now possible with WINXP

SP2 and beyond.

Disabled, Enabled This field is valid only in the

WindowsXP OS.

Control the High Performance Event

Timer through this setup option when enabled. The HPET Table will then be pointed to by the RSDT and the proper enable bits will be set.

0xFED00000,

0xFED01000,

0xFED02000,

0xFED03000

Select the Base Address for the High

Performance Event Timer.

Passive Cooling Trip Point Disabled,

15 C, 23 C, 31 C, 39 C, 47 C,

55 C, 63 C, 71 C, 79 C, 87 C,

95 C, 103 C, 111 C, 119 C

This value controls the temperature of the ACPI Passive Trip Point – the point in which the OS will begin throttling the CPU.

Note: If the DTS is enabled, only values below 97C are valid.

Passive TC1 Value,

Passive TC2 Value,

Passive TSP Value

0 - 15

1 - 15

This value sets the TC1-2 value for the ACPI Passive Cooling Formula.

This item sets the TSP value for the

ACPI Passive Cooling Formula.

It represents in tenths of a second how often the OS will read the temperature when Passive Cooling is Enabled.

50



Critical Trip Point POR,

15 C, 23 C, 31 C, 39 C, 47 C,

55 C, 63 C, 71 C, 79 C, 87 C,

95 C, 103 C, 111 C, 119 C,

127 C

This value controls the temperature of the ACPI Critical Trip Point – the point in which the OS will shut the system off.

Notes: (1)100C is POR for all Intels

CPUs. (2) If value is > 100C and

DTS is enabled, the Out-of-Spec Bit will be used.

(3) The EC value will be set to 127 after ACPI initialation.

5.2.3.7 I/O Device Configuration Menu


Serial Port A Disabled, Enabled, Auto Disabled = Disabled the device

Enabled = User configuration

Auto = BIOS or OS chooses configuration

Base I/O address 3F8, 2F8, 3E8, 2E8

Interrupt

Serial Port B

Mode

Base I/O address

Interrupt

Parallel Port

Mode

3, 4

Disabled, Enabled, Auto

Normal, IR, ASK-IR

3F8, 2F8, 3E8, 2E8

3, 4

Disabled, Enabled, Auto

Set the base I/O address for Serial

Port A.

Set the interrupt for Serial Port A.

Disabled = Disabled the device



Set the mode for Serial Port B (wired

/ infrared).

Set the base I/O address for Serial

Port B.

Set the interrupt for Serial Port B.

Disabled = Disabled the device



Set the mode for Parallel Port.

Base I/O address

Output only,

Bi-directional,

ECP

378, 278, 3BC

Interrupt

DMA channel

5, 7

1, 3

Set the base I/O address for Parallel

Port.

Set the interrupt for Parallel Port.

Set the DMA channel for Parallel

Port (only available if mode was set to ECP).

51


Warning : If you choose the same I/O address or Interrupt for more than one port, the menu displays an asterisk ( * ) at the conflicting settings.

5.2.3.8 Watchdog Options


Watchdog delay After watchdog is activated, he waits selected delay time before he starts counting the timeout period.

Watchdog timeout

1 second,

5 seconds,

10 seconds,

30 seconds

1 minute ,

5 minutes,

10 minutes,

30 minutes

0.4 second,

1 second,

5 seconds,

10 seconds,

30 seconds,

1 minute ,

5 minutes,

10 minutes

Select the maximum watchdog trigger period.

If the watchdog will not be triggered during selected period, system reset will be generated.

Watchdog start on boot No, Yes Select if the watchdog should be started at the end of POST.

52


5.2.4 The Security Menu


Supervisor Password Is Displays Supervisor

User Password Is

Password Is

Displays the current status of the

Supervisor password (“Clear” or “Set”)

Displays User Password Is Displays the current status of the User password (“Clear” or “Set”)

Set Supervisor

Password

Set User Password

Password on boot

TPM Support

Current TPM State

Change TPM State

Press return to enter supervisor password

Disabled,

Enabled

Supervisor Password controls access to the setup utility.

Press return to enter user password

User Password controls access to the system at boot.

Enables password entry on boot

Enable Trusted Platform Module support. Disabled,

Enabled

Displays Current TPM

State

Displays the current TPM status.

No Change,

Enable & Activate,

Deactivate & Disable,

Clear

Changes TPM state.

53


5.2.5 The Power Menu

Feature

After Power Failure

CK-410 Clock Chip

Options

Stay Off,

Last State,

Power On

Default,

Program

Spread Spectrum Mode Off, On

Description

Sets the mode of operation if an AC power loss occurs.

Power On will turn the power on as soon as the power supply is back on.

Last State will only turn the power on, if the system was active when the power loss occurred.

Stay Off will keep the power off until the power button is pressed.

Control Programming of the CK-410 Clock Chip.

Default = Power On Default Values.

Program = Fine tune the clock setup according to hardware capabilities.

Control programming of the Spread Spectrum Mode bit in CK-410 chip.

Configure Hardware Monitor Hardware Monitor Submenu

5.2.5.1 Hardware Monitoring Menu

Feature

CPU Vcore

VRam (V+2.5)

Description

Displays the current CPU voltage.

Displays the current voltage.

Vcc (V+3.3)

VIN1 (V+1.5)

VIN2 (V+0.9)

Temperature Sensor 0



FAN 1 speed




Displays the current CPU temperature.

Displays the current memory temperature.

Displays the current system temperature.

Displays the current fan speed.

54


5.2.6 The Boot Menu

After you turn on your computer, it will attempt to load the operating system (such as DOS, Windows XP or Linux) from a device listed in the boot priority order. If it cannot find the operating system on that device, it will attempt to load it from the next device in that list.

Boot devices (i.e., with access to an operating system) can include: hard drives, floppy drives, CD ROMs, removable devices (e.g. USB sticks), and network cards.

Note: Specifying any device as a boot device on the Boot Menu requires the availability of an operating system on that device.

Selecting "Boot" from the Menu Bar displays the Boot menu, which looks like this:

Feature

Boot priority order:

1: USB KEY:

2: USB FDC:

3: IDE 4:

4: IDE 5:

5: IDE 0:

6: IDE 2:

7: PCI LAN:

8:

Description

Boot priority order for next boot. System tries to boot the first bootable device in this list.

Use <+> and <-> to change order.

Use <x> to exclude or include device to boot priority list.

Exclude from boot order:

: IDE 1:

: IDE 3:

: USB HDD:

: USB CDROM:

: USB ZIP:

: USB LS120:

: PCI SCSI:

System does not try to boot a device from this list.

Pressing the “F10” key during the bios boot phase will bring up the bios boot menu, which will allow you to select a different boot device for the current boot process only. In this boot menu, only devices in the “Boot priority list” will selectable. Devices excluded from boot order will not be shown.

55


5.2.7 The Exit Menu

The following sections describe each of the options on this menu. Note that <Esc> does not exit this menu. You must select one of the items from the menu or menu bar to exit.

Exit Saving Changes

After making your selections on the Setup menus, always select "Exit Saving Changes".

This procedures stores the selections displayed in the menus in CMOS (short for

"battery-backed CMOS RAM") a special section of memory that stays on after you turn your system off. The next time you boot your computer, the BIOS configures your system according to the Setup selections stored in CMOS.

If you attempt to exit without saving, the program asks if you want to save before exiting.

During boot-up, PhoenixBIOS attempts to load the values saved in CMOS. If those values cause the system boot to fail, reboot and press <F2> to enter Setup. In Setup, you can get the Default Values (as described below) or try to change the selections that caused the boot to fail.

Exit Discarding Changes

Use this option to exit Setup without storing in CMOS any new selections you may have made. The selections previously in effect remain in effect.

Load Setup Defaults

To display the default values for all the Setup menus, select "Load Setup Defaults" from the Main Menu.

If, during boot-up, the BIOS program detects a problem in the integrity of values stored in

CMOS, it displays these messages:

System CMOS checksum bad - run SETUP Press <F1> to resume, <F2> to Setup

The CMOS values have been corrupted or modified incorrectly, perhaps by an application program that changes data stored in CMOS.

Press <F1> to resume the boot or <F2> to run Setup with the ROM default values already loaded into the menus. You can make other changes before saving the values to

CMOS.

Discard Changes

If, during a Setup Session, you change your mind about changes you have made and have not yet saved the values to CMOS, you can restore the values you previously saved to CMOS.

Selecting “Discard Changes” on the Exit menu updates all the selections with their previous values.

Save Changes

Selecting “Save Changes” saves all the selections without exiting Setup. You can return to the other menus if you want to review and change your selections.

56


5.3 Bios Update

If a System-BIOS update is required please follow these instructions:

1.) Create a bootable DOS disk/usb-stick/hdd.

2.) Copy PHLASH16.EXE, BIOS.WPH and UPDATE.BAT to this device.

3.) Boot the system from this device.

4.) Type "update.bat" to update the System BIOS.

5.) When the BIOS update has finished, reboot the system.

Note: After the system has been updated, the CMOS has been changed to defaults and therefore it is necessary to enter Setup (press F2 at boot time) to configure the system settings.

57


5.4 Bios Crisis Recovery

Note: Contact your sales for information how to get the CRISDISK.ZIP and an USB recovery dongle.

Please follow these simple steps to create a bootable crisis recovery medium:

1. Unzip CRISDISK.ZIP and start the windows-based program WINCRIS.EXE on the host system. A window will pop up as shown below:

2. In the drop-down box, e ither select “Floppy Drive A” to create a recovery disk, or select “Removable Disk 0 (xxxMb)” to create a recovery usb stick. Disk options should be left at “Create MINIDOS Crisis Disk”.

3. Press the start button to generate the selected crisis recovery medium.

There are two possibilities to force the target system into crisis recovery mode: either by USB crisis recovery dongle or by crisis recovery jumper.

1. With the dongle, you just have to plug it into a free USB port before switching the system on. Please make sure that you use different USB controllers for USB dongle and USB crisis recovery medium. After powerup, crisis recovery mode should automatically start.

58


2. The crisis recovery jumper is located between CPU and northbridge, near the edge of the board (see picture below). You have to shorten the two pins before applying power to the board. As soon as crisis recovery is started, you can remove the jumper.

The programming process is signalled by short beeps and terminated after successfull programming with one long beep. After that, the system is automatically rebooted.

Important Notes:

USB recovery dongle and USB crisis recovery device must not be plugged to the same USB controller.

Crisis recovery may take up to 5 minutes

A long beep indicated successful recovery

Crisis recovery does not include the bootblock.

59


5.5 Diagnostics Postcodes

Postcodes can be seen on a special Postcode display, either on the MSC mainboard or on an external Postcode PCI card. There is an item in the bios setup to select the bus that should get the postcode data: either PCI (for external cards) or LPC (for onboard displays).

If a postcode display has only 2 digits, only the lower byte of word-value postcodes will be shown.

5.5.1 Bootblock Bios Postcodes

Code

BBH

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

95h

96h

97h

99h

Bootblock Task Description

Bootblock Early Init after Reset

Chipset Init

Bridge Init

CPU Init

System Timer Init

System I/O Init

Check forced Recovery Boot, CMOS & CMOS Backup Clear

Check BIOS Checksum

Goto BIOS, start early BIOS initialzations

Init Multi Processor

Set Huge Segment

OEM Initializations

Init Interrupt and DMA Controller

Init Memory Type

Init Memory Size

Shadow Boot Block

Init SMM

System Memory Test

Init Interrupt Vectors

Init Realtime Clock

Init Standard Video

Init Beeper

Initialize USB Controller

Init Boot

Clear Huge Segment

Boot OS

Init Security

60


5.5.2 System Bios Postcodes

Code Beeps

04h

03h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Eh

0Fh

10h

11h

12h

13h

14h

16h 1-2-2-3

17h

18h

1Ah

1Ch

20h 1-3-1-1

22h 1-3-1-3

24h

28h

29h

2Ah

2Ch 1-3-4-1

2Eh 1-3-4-3

2Fh

32h

33h

36h

38h

3Ah

3Ch

3Dh

41h

42h

45h

46h 2-1-2-3

47h

48h

49h

4Ah

4Bh

4Ch

4Eh

4Fh

50h

51h

52h

POST Task Description

Get CPU type

Disable Non-Maskable Interrupt (NMI)

Initialize system hardware

Disable shadow and execute code from the ROM.

Initialize chipset with initial POST values

Set IN POST flag

Initialize CPU registers

Enable CPU cache

Initialize caches to initial POST values

Initialize I/O component

Initialize fixed disk drives

Initialize Power Management

Load alternate registers with initial POST values

Restore CPU control word during warm boot

Initialize PCI Bus Mastering devices

Initialize keyboard controller

BIOS ROM checksum

Initialize cache before memory Autosize

8254 timer initialization

8237 DMA controller initialization

Reset Programmable Interrupt Controller

Test DRAM refresh

Test 8742 Keyboard Controller

Set ES segment register to 4 GB

Autosize DRAM

Initialize POST Memory Manager

Clear 512 kB Base RAM

RAM Address test

Base RAM Test

Enable cache before system BIOS shadow

Compute CPU clock speed in MHz

Initialize Phoenix Dispatch Manager

Warm start shut down

Shadow system BIOS ROM

Autosize cache

Advanced configuration of chipset registers

Load alternate registers with CMOS values

Initialize RomPilot

Initialize interrupt vectors

POST device initialization

Check ROM copyright notice

Initialize I20 support

Check video configuration against CMOS

Initialize PCI bus and devices

Initialize all video adapters in system

QuietBoot start (optional)

Shadow video BIOS ROM

Display BIOS copyright notice

Initialize MultiBoot

Display CPU type and speed

Initialize EISA board

Test keyboard

61


99h

9Ah

9Ch

9Dh

9Eh

9Fh

A0h

A2h

A4h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Fh

90h

91h

92h

93h

95h

96h

97h

98h

7Ch

7Dh

7Eh

80h

81h

82h

83h

68h

69h

6Ah

6Bh

6Ch

70h

72h

76h

Code Beeps

54h

55h

58h 2-2-3-1

59h

5Ah

5Bh

5Ch

60h

62h

64h

66h

67h

1-2


Set key click if enabled

Configure USB devices

Test for unexpected interrupts

Initialize POST display service

Display prompt "Press F2 to enter SETUP"

Disable CPU cache

Conventional memory test

Extended memory test

Address Test on Extended Memory

Jump to UserPatch1

Configure advanced cache registers

CPU feature, MP, and APIC initialization

Enable external and CPU caches

Setup System Management Mode (SMM) area

Display external L2 cache size

Load custom defaults (optional)

Display BIOS shadow status

Display error messages

Check for configuration errors

Check for keyboard errors

Set up hardware interrupt vectors

Initialilze Intelligent System Monitoring

Initialize coprocessor if present

Disable onboard Super I/O ports and IRQs

Late POST device initialisation

Detect and install external RS232 ports

Configure non-MCD IDE controllers

Detect and install external parallel ports

Initialize PC-compatible PnP ISA devices

Re-initialize onboard I/O ports.

Configure Motheboard Configurable Devices (optional)

Initialize BIOS Data Area

Enable Non-Maskable Interrupts (NMIs)

Initialize Extended BIOS Data Area

Test and initialize PS/2 mouse

Initialize floppy controller

Determine number of ATA drives (optional)

Initialize hard-disk controllers

Program timing registers according to PIO modes

Jump to UserPatch2

Build MPTABLE for multi-processor boards

Install CD ROM for boot

Clear huge ES segment register

Fixup Multi Processor table

Enable PCI devices and ROM Scan One long, two short beeps on checksum failure

Check for SMART Drive

Shadow option ROMs

Set up Power Management

Initialize security engine (optional)

Enable hardware interrupts

Determine number of ATA and SCSI drives

Set time of day

Check key lock

Initialize typematic rate

62


C2h

C3h

C4h

C5h

C6h

C7h

C8h

B9h

BAh

BCh

BDh

BEh

BFh

C0h

C1h

Code Beeps

A8h

AAh

ACh

AEh

B0h

B1h

B2h

B3h

B4h

B5h

B6h

B7h

C9h

CAh

CBh

CCh

CDh

CEh

D2h


Erase F2 prompt

Scan for F2 key stroke

Enter SETUP

Clear Boot flag

Check for errors

Inform RomPilot about the end of POST.

POST done - prepare to boot operating system store enhanced CMOS values in non-volatile area

1 One short beep before boot

Terminate QuietBoot (optional)

Check password (optional)

Initialize ACPI BIOS

Prepare Boot

Initialize DMI parameters

Clear parity checkers

Display MultiBoot menu

Clear screen (optional)

Check virus and backup reminders

Try to boot with INT 19

Initialize POST PEM Error Manager

Initialize PEM error logging

Initialize error PEM display function

Initialize PEM system error handler

PnPnd dual CMOS (optional)

Initialize note dock (optional)

Initialize note dock late

Force check (optional)

Extended checksum (optional)

Redirect Int 15h to enable remote keyboard

Redirect Int 13h to Memory Technologies

Redirect Int 10h to enable remote serial video

Remap I/O and memory for PCMCIA

Initialize digitizer and display message

Unknown interrupt or exception

63


5.5.3 Memory Detection Postcodes

Code

FFA0h

FF01h

FF02h

FF03h

FF04h

FF05h

Calistoga Memory Detection

Start memory detection

Enable MCHBAR

Check for DRAM initialisation interrupt and reset fail

Verify all DIMMs are DDR2 and unbuffered

Detect an improper warm reset and handle

Detect if ECC SO-DIMMs are present in the system

FF06h Verify all DIMMs are single or double sided and not asymmetric

FF07h Verify all DIMMs are x8 or x16 width

FF08h Find a common CAS latency between the DIMMS and the MCH

FF09h Determine the memory frequency and CAS latency to program

FF10h Determine the smallest common TRAS for all DIMMs

FF11h

FF12h

FF13h

FF14h

FF15h

FF16h

FF17h

Determine the smallest common TRP for all DIMMs

Determine the smallest common TRCD for all DIMMs

Determine the smallest refresh period for all DIMMs

Verify burst length of 8 is supported by all DIMMs

Determine the smallest tWR supported by all DIMMs

Determine DIMM size parameters

Program Graphics frequency and PLL settings

FF18h

FF19h

FF20h

FF21h

Program system memory frequency

Determine and set the mode of operation for the memory channels

Program clock crossing registers

Disable Fast Dispatch

FF22h Program the DRAM Row Attributes and DRAM Row Boundary registers

FF23h Program the DRAM Bank Architecture register

FF24h

FF25h

Program the DRAM Timing & and DRAM Control registers

Program ODT

FF26h Perform steps required before memory init

FF27h Program the receive enable reference timing control register

Program the DLL Timing Control Registers , RCOMP settings

FF28h

FF29h

FF30h

FF31h

FF32h

Enable DRAM Channel I/O Buffers

Enable all clocks on populated rows

Perform JEDEC memory initialization for all memory rows

Program PM Settings

Perform additional steps required after memory init

FF33h Program DRAM throttling and throttling event registers

FF34h Setup DRAM control register for normal operation and enable

FF35h Setup DRAM control register for normal operation and enable

FF36h

FF37h

Enable RCOMP

Clear DRAM initialization bit in the ICH

5.5.4 ACPI Postcodes

Code

03h

04h

05h

ABh

CDh

ACPI Codes

Enter Suspend State S3

Enter Hibernate State S4

Enter Softoff State S5

Enter Wakeup from Powerstate

End Wakeup from Powerstate

64


65

MSC CXB CD945 User Manual

User’s Manual

CXB-CD945

MSC COM Express™ Basic Module

Preface

Copyright Notice

Important Information

Disclaimer

EMC Rules

Trademarks

Certification

Life-Cycle-Management

Product Support

Content

1 General Information

1.1 Revision History

1.2 Reference Documents

1.3 Introduction

2 Technical Description

2.1 Key features

2.2 Block diagram

2.3 COM Express implementation

2.4 Functional units

2.5 Power Supply

2.6 Power dissipation (DOS Prompt, 512MB DDR2 SO-DIMM)

2.7 Mechanical Dimensions

2.8 Thermal specifications

2.9 Signal description

2.10 Pin List for MSC 945GM module (Type 2)

3 Watchdog

4 System resources

4.1 PCI Devices CXB-945

4.2 Carrier Board PCI Resource Allocation

4.3 SMB Address Map

5 BIOS

5.1 Introduction

5.2 TrustedCore Setup Utility

The BIOS Menu Structure

The Menu Bar

The Legend Bar

Select an item

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Exit Saving Changes

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Load Setup Defaults

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5.3 Bios Update

5.4 Bios Crisis Recovery

5.5 Diagnostics Postcodes

Related manuals

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COME8X80

DFI

NP900-B16C

MiTAC

M230

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