Texas Instruments Comparison of Electrical & Thermal Parameters of Widebus SMD and LFBGA Packages Application Note

Application Report

SCYA007 - October 1999

Comparison of Electrical and Thermal Parameters of

Widebus



SMD SSOP, TSSOP, TVSOP, and LFBGA

Packages

Johannes Huchzermeier Standard Linear and Logic

ABSTRACT

The trend toward 16- and 32-bit-wide bus systems, in conjunction with continuing advances in surface-mount technology during the 1980s and 1990s, led to the development of ever-smaller packages combined with increased integrated-circuit performance. The improvement in the electrical characteristics of the packages also made possible development of smaller-footprint packages for Widebus



circuits. In the mid-1980s, Texas

Instruments produced Widebus



devices with improved electrical characteristics and expanded data width, supporting up to 20 bits in a single package.

Now, Texas Instruments is launching the low-profile, fine-pitch, ball grid array (LFBGA). The

LFBGA is the first ball grid array package (BGA) for logic components, featuring improved signal characteristics, as well as increased integration.

With new designs that support up to 36 bits in a single package, doubling of component density on the printed circuit board using Widebus packages has been achieved.

The purpose of this report is to familiarize designers with the advantages of this package option by comparing the mechanical data, electrical characteristics, and thermal parameters of four packages: 48-pin SSOP (Shrink Small-Outline Package), 48-pin TSSOP (Thin Shrink

Small-Outline Package), 48-pin TVSOP (Thin Very Small-Outline Package), and 96-pin

LFBGA (Low-profile Fine-pitch Ball Grid Array), using the 244-function (unidirectional) buffer/driver of the LVC logic family.

Widebus is a trademark of Texas Instruments Incorporated

1

SCYA007

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packages and Package Parameters Investigated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Simultaneous-Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Increase in Propagation Delay Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

27

Thermal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Package Dimensions and Size Comparison

Summary

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

41

Acknowlegment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

42

44

List of Figures

1.

16-Bit Widebus Package for 48-Pin SSOP, TSSOP, and TVSOP Packages

2.

32-Bit Package for 96-Ball Low-Profile Fine-Pitch Ball Grid Arrays

. . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . .

6

7

3.

Influence of Slew Rate on Propagation Delay Time and the Principle Behind OEC

4.

Basic Structure of the OEC Output Stage

. . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

14

5.

Simultaneous-Switching Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.

Simultaneous Switching Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.

Measured Simultaneous-Switching Ground Bounce, SSOP 48-Pin Package . . . . . . . . . . . . . . . . .

18

18

8.

Measured Simultaneous-Switching Ground Bounce, TSSOP 48-Pin Package . . . . . . . . . . . . . . . . 19

9.

Measured Simultaneous-Switching Ground Bounce, TVSOP 48-Pin Package

10. Measured Simultaneous-Switching Ground Bounce, LFBGA 96 Ball

. . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . .

19

20

11. Measured Simultaneous-Switching High Bounce, SSOP 48-Pin Package . . . . . . . . . . . . . . . . . . . 20

12. Measured Simultaneous-Switching High Bounce, TSSOP 48-Pin Package

13. Measured Simultaneous-Switching High Bounce, TVSOP 48-Pin Package

. . . . . . . . . . . . . . . . . . 21

. . . . . . . . . . . . . . . . . . 21

14. Measured Simultaneous-Switching High Bounce, LFBGA 96 Ball . . . . . . . . . . . . . . . . . . . . . . . . . .

15. Simultaneous-Switching Ground Bounce, SSOP 48 Pin (top), TSSOP 48 Pin (bottom) . . . . . . . .

22

23

16. Simultaneous-Switching Ground Bounce, TVSOP 48 Pin (top), LFBGA 96 Ball (bottom)

17. Simultaneous-Switching Ground Bounce, SSOP 48 Pin (top), TSSOP 48 Pin (bottom)

. . . . . . . 24

. . . . . . . . 25

18. Simultaneous-Switching High Bounce, TVSOP 48-Pin (top), LFBGA 96 Ball (bottom) . . . . . . . . . 26

19. Rising-Edge Propagation Delay Time Relative to the Number of Simultaneously

Switching Outputs for the SSOP, TSSOP, TVSOP, and LFBGA Packages . . . . . . . . . . . . . . . . . . . 28

20. Falling-Edge Propagation Delay Time Relative to the Number of Simultaneously

Switching Outputs for the SSOP, TSSOP, TVSOP, and LFBGA Packages . . . . . . . . . . . . . . . . . . . 28

21. Maximum Power Consumption Relative to Ambient Temperature,

T

J

= 150

°

C, SSOP 48-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34


T

J

= 150

°

C, TSSOP 48-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34


T

J

= 150

°

C, TVSOP 48-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35


T

J

= 150

°

C, LFBGA 96 Ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

25. Dimensions of the SSOP 28-, 48-, and 56-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2 Comparison of Electrical and Thermal Parameters of Widebus



SMD SSOP, TSSOP, TVSOP, and LFBGA Packages

SCYA007

List of Figures (continued)

26. Dimensions of the TSSOP 48-, 56-, and 64-Pin Packages

27. Dimensions of the TVSOP 48-, 56-, and 64-Pin Packages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37

38

28. Dimensions of the LFBGA 96-Ball Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29. Space Needed for a 32-Bit Interface Using Various Packages Options . . . . . . . . . . . . . . . . . . . . . .

39

40

List of Tables

1.

SSOP 48-Pin Capacitance, Inductance, and Coupling-Factor (k) Package Parameters . . . . . . . . . 8

2.

TSSOP 48-Pin Capacitance, Inductance, and Coupling-Factor (k) Package Parameters . . . . . . . . 9

3.

TVSOP 48-Pin Capacitance, Inductance, and Coupling-Factor (k) Package Parameters . . . . . . . 10

4.

LFBGA 96-Ball Package Parameters (Balls 1 – 48) (Balls 49 – 96 Analog) . . . . . . . . . . . . . . . . . . 11

5.

Comparison of Capacitance, Inductance, and Coupling-Factor (k) Package Parameters . . . . . . . 12

6.

Comparison of the Thermal Resistance (R θ

JA

) of Different Packages . . . . . . . . . . . . . . . . . . . . . . . 29

Comparison of Electrical and Thermal Parameters of Widebus



SMD SSOP, TSSOP, TVSOP, and LFBGA Packages 3

SCYA007

Introduction

The introduction of surface-mount technology at the beginning of the 1980s led to a major reduction in the component space needed on the circuit board. Users exploited this advantage either by reducing the space needed for a given system or by increasing system performance, while using the same amount of space. The steadily increasing integration of electrical circuitry also created pressure for advances in the miniaturization of packages. Standard components, such as bus drivers, also were produced in ever-smaller space-saving packages.

During the same period, the transition from 8-bit processors to 16- and 32-bit processors occurred. The associated enlargement of data and address buses tended to counteract the space advantage that had been gained because two or four modules now had to be used in place of a single bus driver.

In order to satisfy the user’s need for more compact equipment, Texas Instruments (TI



) developed new packages suitable for surface-mount technology:

•

SSOP (Shrink Small-Outline Package) doubles the number of bits within one package, while requiring no more space than the usual 8-bit SOP (Small Outline Package) modules

•

TSSOP (Thin Shrink Small-Outline Package) represents a significant space saving over the

SSOP package, and also is suitable for use in PCMCIA plug-in boards due its reduced package height

•

TVSOP (Thin Very Small-Outline Package) permits a further space saving of up to 38% compared to the TSSOP package

Also, emphasis was placed on important factors, such as the speed of the new functions, while striving to keep interference voltages as low as possible.

However, miniaturization of package types to 0.4 mm pin-to-pin distance, reached the limit for reliable manufacturing processes, and led to the development of ball grid arrays.

The LFBGA (Low-profile Fine-pitch Ball Grid Array) package represents the ideal solution because it combines minimal space requirements with low package parasitics and a high level of functional density.

This report compares the dimensions, electrical characteristics, and thermal parameters of four packages:

SSOP (Shrink Small-Outline Package) for Widebus 48-pin DL

TSSOP (Thin Shrink Small-Outline Package) for Widebus

TVSOP (Thin Very Small-Outline Package) for Widebus

LFBGA (Low-profile Fine-pitch Ball Grid Array)

48-pin DGG

48-pin DGV

96-ball GKE

In addition to package names and the number of external connections, each package type is designated by a clearly defined abbreviation (e.g., DL, DGG, DGV, and GKE), which is used when ordering a component.

The influence of package type on electrical characteristics is investigated in this application report, using measurements on the unidirectional buffer components SN74LVH16244A and

SN74LVCH32244A.

TI is a trademark of Texas Instruments Incorporated





SCYA007

Package Parameters

The increasing speed of integrated circuits makes the electrical characteristics of the package even more important.

In addition to the inevitable parasitic capacitances of the leads within a package, their inductance is the major factor determining the behavior of fast digital circuits, limiting ranges of applications in some cases.

Furthermore, with reduced distances between pins, the pins’ coupling factors are increasingly important.

Supply-voltage connections should have low inductance values. For all signal lines a good package should show the lowest possible values for the following electrical variables:

•

Capacitance of a pin against ground

•

Inductance of the pins

•

The pins’ mutual-coupling factors.

The pins’ mutual-coupling factors can be determined, using the general-transformer equation. k +

Ǹ

L

1

M

L

2

Where:

M = coupling inductance

L k

1 and L

2

= respective self-inductance of the pin connections

= the inductive coupling factor

(1)

The three electrical variables of a package are determined by:

•

Line length of the pins in the package

•

Distance between the lines

•

Length of the bonding wires.

For purposes of comparison, note that large dual in-line packages, PDIPs (plastic dual in-line packages), for example, have significantly longer leads than SSOP, TSSOP, TVSOP, or LFBGA packages.

A long lead produces high inductance and high coupling factors. Also, the large surfaces resulting from the long line result in higher capacitance. With small package types, such as the

TSSOP, the inductance and capacitance of the leads is significantly less. However, the coupling-factor advantage gained by the short leads is partially offset by the minimal distance between the leads, thereby increasing the coupling factor.

To a lesser extent, the size of the chips and the lead frame used for the chip also have an influence on the electrical characteristics. Accordingly, the measurement results given in this chapter should be regarded as typical values that relate only to the component tested in each package. However, typical dependencies for each package type may be inferred from the measurements obtained.





SCYA007

Packages and Package Parameters Investigated

Figures 1 and 2 show the pin and ball layout, respectively, of the Widebus and the LFBGA packages. Tables 1 through 4 show the capacitance and inductance of the individual pins of the

48-pin SSOP, TSSOP, and TVSOP, and the 96-pin low-profile fine-pitch ball grid array packages.

Additionally, the tables give the coupling factors between neighboring pins. As a basis for this comparison, the respective SPICE package models have been used. Minor deviations are possibly due to the use of different lead frames, i.e., the metal masks to which the chip is attached inside the package.

Tables 1 through 4 give capacitance, inductance, and coupling-factor parameters for each of the packages discussed in this report.

GND

VCC

GND

GND

VCC

GND

1

14

15

16

11

12

13

8

9

6

7

10

2

3

4

5

20

21

22

23

17

18

19

24

42

41

40

39

38

48

47

46

45

44

43

33

32

31

30

29

28

27

26

37

36

35

34

25

GND

VCC

GND

GND

VCC

GND

Figure 1. 16-Bit Widebus Package for 48-Pin SSOP, TSSOP, and TVSOP Packages





51 50

53 54

49

52

48 47

45 43

46

44

56 57 55 42 40 41

59 60 58 39 37 38

61 62 63 34 35 36

64 65 66 31 32 33

67 68 69 28 29 30

70 71 72 25 26 27

75 74 73 24 23 22

77 78 76 21 19 20

80 81 79 18 16 17

83 84 82 15 13 14

85

88

86

89

87

90

10

7

11 12

8 9

91 92 93

94 95 96

4

3

5

2

6

1

VCC

GND

Control/GND Data I/O

I/O

6 5 4 3 2 1

Figure 2. 32-Bit Package for 96-Ball Low-Profile Fine-Pitch Ball Grid Arrays

SCYA007





SCYA007

Table 1. SSOP 48-Pin Capacitance, Inductance, and Coupling-Factor (k) Package Parameters

17

18

19

14

15

16

11

12

13

8

9

10

20

21

22

23

24

5

6

7

2

3

4

Capacitance

Pin Pin to GND

(pF)

1 0.44

0.24

0.20

0.18

0.16

0.16

0.18

0.16

0.18

0.20

0.24

0.44

0.07

0.08

0.10

0.12

0.18

0.16

0.12

0.10

0.08

0.07

0.21

0.21

Inductance

5.08

5.19

5.30

5.50

5.66

5.80

5.50

5.30

5.19

5.08

5.86

5.86

5.86

6.27

6.76

7.30

7.97

(nH)

7.97

7.30

6.76

6.27

5.86

5.80

5.66

Coupling Factor (k)

Pin Pin

20

21

22

17

18

19

23

24

14

15

16

11

12

13

8

9

10

5

6

7

1

2

3

4

21

22

23

18

19

20

24

25

15

16

17

12

13

14

9

10

11

6

7

8

2

3

4

5

Factor

0.47

0.46

0.46

0.48

0.49

0.49

0.48

0.06

0.44

0.54

0.44

0.48

0.48

0.47

0.48

0.49

0.49

0.48

0.46

0.46

0.47

0.47

0.48

0.48

32

31

30

35

34

33

38

37

36

41

40

39

29

28

27

26

25

44

43

42

47

46

45

Capacitance

Pin Pin to GND

(pF)

48 0.44

0.24

0.20

0.18

0.16

0.16

0.18

0.16

0.18

0.20

0.24

0.44

0.07

0.08

0.10

0.12

0.18

0.16

0.12

0.10

0.08

0.07

0.21

0.21

Inductance

5.08

5.19

5.30

5.50

5.66

5.80

5.50

5.30

5.19

5.08

5.86

5.86

5.86

6.27

6.76

7.30

7.97

(nH)

7.97

7.30

6.76

6.27

5.86

5.80

5.66


Pin Pin

29

28

27

32

31

30

26

25

35

34

33

38

37

36

41

40

39

44

43

42

48

47

46

45

30

29

28

33

32

31

27

26

36

35

34

39

38

37

42

41

40

45

44

43

1

48

47

46

Factor

0.47

0.47

0.46

0.46

0.48

0.49

0.49

0.48

0.48

0.44

0.54

0.44

0.48

0.48

0.06

0.48

0.49

0.49

0.48

0.46

0.46

0.47

0.47

0.48





SCYA007

Table 2. TSSOP 48-Pin Capacitance, Inductance, and Coupling-Factor (k) Package Parameters

17

18

19

14

15

16

11

12

13

8

9

10

20

21

22

23

24

5

6

7

2

3

4

Capacitance

Pin Pin to GND

(pF)

1 0.41

0.22

0.19

0.18

0.19

0.20

0.12

0.17

0.17

0.19

0.22

0.40

0.08

0.09

0.10

0.11

0.15

0.18

0.12

0.10

0.09

0.08

0.08

0.08

Inductance

2.45

2.50

2.55

2.62

2.69

2.83

2.70

2.59

2.54

2.46

2.43

2.42

2.98

3.06

3.34

3.66

3.96

(nH)

3.92

3.63

3.37

3.02

2.99

2.81

2.71


Pin Pin

11 12

12 13

13 14

14 15

15 16

16 17

17 18

18 19

19 20

20 21

21 22

22 23

23 24

24 25

8

9

10

5

6

7

1

2

3

4

9

10

11

6

7

8

2

3

4

5

Factor

0.33

0.33

0.34

0.35

0.37

0.39

0.39

0.03

0.36

0.35

0.35

0.35

0.35

0.34

0.39

0.38

0.36

0.35

0.34

0.31

0.32

0.33

0.35

0.35

32

31

30

35

34

33

38

37

36

41

40

39

29

28

27

26

25

44

43

42

47

46

45

Capacitance

Pin Pin to GND

(pF)

48 0.40

0.22

0.19

0.17

0.17

0.18

0.16

0.17

0.17

0.19

0.22

0.40

0.08

0.09

0.10

0.11

0.16

0.18

0.11

0.10

0.09

0.08

0.08

0.08

Inductance

2.38

2.44

2.51

2.57

2.69

2.78

2.58

2.52

2.45

2.37

2.37

2.37

2.87

2.98

3.26

3.55

3.89

(nH)

3.99

3.63

3.31

3.06

2.91

2.80

2.69


Pin Pin

29

28

27

32

31

30

26

25

35

34

33

38

37

36

41

40

39

44

43

42

48

47

46

45

30

29

28

33

32

31

27

26

36

35

34

39

38

37

42

41

40

45

44

43

1

48

47

46

Factor

0.34

0.33

0.33

0.33

0.35

0.37

0.39

0.4

0.34

0.36

0.35

0.36

0.36

0.34

0.03

0.4

0.39

0.37

0.35

0.34

0.34

0.33

0.34

0.35





SCYA007

Table 3. TVSOP 48-Pin Capacitance, Inductance, and Coupling-Factor (k) Package Parameters

Capacitance

0.05

0.06

0.06

0.07

0.08

0.12

0.07

0.06

0.06

0.05

0.05

0.05

0.12

0.12

0.14

0.18

0.30

(pF)

0.30

0.18

0.14

0.12

0.12

0.12

0.08

20

21

22

17

18

19

23

24

14

15

16

11

12

13

8

9

10

5

6

7

1

2

3

4

Inductance

2.46

2.59

2.65

2.79

2.96

3.21

2.58

2.51

2.40

2.40

2.40

2.43

3.49

3.49

3.74

3.99

4.31

(nH)

4.02

3.72

3.46

3.21

2.93

2.80

2.68


Pin Pin

20

21

22

17

18

19

23

24

14

15

16

11

12

13

8

9

10

5

6

7

1

2

3

4

21

22

23

18

19

20

24

25

15

16

17

12

13

14

9

10

11

6

7

8

2

3

4

5

Factor

0.39

0.39

0.41

0.39

0.39

0.38

0.38

0.12

0.41

0.42

0.42

0.42

0.41

0.4

0.38

0.39

0.39

0.4

0.42

0.38

0.4

0.4

0.41

0.42

32

31

30

35

34

33

38

37

36

41

40

39

29

28

27

26

25

44

43

42

47

46

45

Capacitance

Pin Pin to GND

(pF)

48 0.30

0.18

0.14

0.12

0.12

0.12

0.08

0.12

0.12

0.14

0.18

0.30

0.05

0.06

0.06

0.07

0.08

0.11

0.07

0.06

0.06

0.05

0.05

0.05

Inductance

2.47

2.55

2.64

2.78

2.88

3.23

2.56

2.47

2.43

2.39

2.38

2.42

3.52

3.52

3.70

3.93

4.29

(nH)

4.01

3.72

3.44

3.20

2.93

2.80

2.67


Pin Pin

29

28

27

32

31

30

26

25

35

34

33

38

37

36

41

40

39

44

43

42

48

47

46

45

30

29

28

33

32

31

27

26

36

35

34

39

38

37

42

41

40

45

44

43

1

48

47

46

Factor

0.4

0.39

0.37

0.42

0.4

0.38

0.39

0.38

0.41

0.41

0.42

0.42

0.41

0.4

0.13

0.38

0.39

0.39

0.4

0.42

0.37

0.39

0.39

0.41





Table 4. LFBGA 96-Ball Package Parameters (Balls 1 – 48) (Balls 49 – 96 Analog)

SCYA007

Capacitance

(pF)

Inductance

(nH)

0.05

0.05

0.12

0.05

0.05

0.06

0.05

0.11

0.05

0.05

0.11

0.05

0.05

0.14

0.06

0.07

0.12

0.05

0.05

0.11

0.05

0.10

0.05

0.05

0.10

0.05

0.05

0.05

0.11

0.05

0.10

0.05

0.05

0.10

0.10

0.05

0.05

0.11

0.05

12

13

14

15

16

8

9

10

11

17

18

19

20

3

4

1

2

5

6

7

30

31

32

33

34

35

26

27

28

29

36

37

38

39

21

22

23

24

25

1.70

1.91

1.73

2.63

1.86

1.66

1.75

2.66

1.62

1.70

2.67

1.91

1.68

2.87

1.65

1.76

2.83

1.74

1.77

2.75

1.70

2.68

1.76

1.70

2.63

1.79

1.60

1.72

2.68

1.74

1.75

1.76

2.60

1.68

2.68

1.72

1.60

2.85

2.85

2

1

5

6

8

9

12

11

14

13

17

16

20

19

23

22

26

27

29

30

32

33

36

35

0.17

0.08

0.16

0.18

0.18

0.22

0.29

0.07

0.18

0.06

0.16

0.06

0.12

0.06

0.09

0.06

0.17

0.16

0.19

0.17

0.19

0.19

0.30

0.09

0.17

0.19

0.24

0.08

0.16

0.18

0.15

0.16

0.16

0.25

0.17

0.06

0.15

0.16

0.17

0.16

0.19

0.15

0.15

0.16

0.16

0.15

0.17

0.11

0.08

0.14

0.15

0.15

0.20

0.12

0.14

0.32

0.17

0.17

0.13

0. 05

9

11

12

10

13

14

15

16

17

7

8

5

6

3

2

1

4

27

28

29

30

31

32

23

22

25

26

33

35

36

34

18

20

19

21

24

8

10

11

87

15

13

82

18

16

4

5

90

7

96

3

2

93

26

69

28

29

66

31

24

23

72

25

32

34

35

63

79

19

21

76

73

0.19

0.09

0.08

0.09

0.19

0.10

0.11

0.11

0.32

0.10

0.32

0.09

0.11

0.17

0.09

0.06

0.07

0.09

0.07

0.10

0.08

0.10

0.10

0.10

11

15

13

82

18

7

8

87

10

16

79

21

19

2

3

96

93

4

5

90

29

66

31

32

63

34

25

26

69

28

35

39

37

58

76

23

24

73

72

0.24

0.16

0.18

0.15

0.16

0.19

0.17

0.08

0.19

0.16

0.15

0.12

0.20

0.06

0.17

0.25

0.15

0.16

0.17

0.16

0.16

0.15

0.17

0.17

0.05

0.23

0.15

0.15

0.15

0.16

0.13

0.17

0.12

0.11

0.14

0.08

0.11

0.32

0.14

14

16

17

18

19

11

12

15

13

20

21

23

22

4

7

6

5

8

9

10

33

34

35

36

39

37

29

30

31

32

38

40

41

42

24

27

26

25

28

0.25

0.29

0.25

0.29

0.26

0.29

0.29

0.24

0.15

0.29

0.15

0.30

0.16

0.30

0.33

0.21

0.32

0.33

0.21

0.32

0.21

0.31

0.22

0.17

0.18

0.21

13

18

16

79

21

10

11

82

15

19

76

24

23

5

4

93

90

7

8

87

32

63

34

35

58

39

28

29

66

31

37

42

40

55

73

26

25

72

69

0.08

0.17

0.16

0.18

0.18

0.22

0.07

0.29

0.06

0.18

0.06

0.16

0.06

0.12

0.06

0.09

0.17

0.16

0.19

0.17

0.19

0.19

0.09

0.30

0.06

0.19

6

5

8

9

0.09

0.19

0.08

0.09

11

12

0.19

0.10

13

14

0.11

0.11

1

2

5

6

8

9

11

12

0.25

0.29

0.25

0.29

0.26

0.29

0.29

0.24

17 0.10

14 0.29

16

20

19

22

0.32

0.09

13 0.15

17 0.30

23 0.17

19 0.16

27

26

29

30

32

33

35

36

37

38

0.32

0.11

0.06

0.09

0.07

0.09

0.07

0.10

0.08

0.10

0.10

0.10

16

20

22

29

30

32

33

35

36

0.15

0.30

0.33

23 0.21

26 0.21

27 0.33

0.21

0.32

0.21

0.31

0.22

0.30

41 0.10

38 0.21

40 0.33

37 0.18





SCYA007

Table 4. LFBGA 96-Ball Package Parameters (Balls 1 – 48) (Balls 49 – 96 Analog) (Continued)

Capacitance Inductance

(pF) (nH)

44

45

46

47

48

40

41

42

43

0.06

0.11

0.06

0.06

0.14

0.05

0.05

0.11

0.05

1.85

2.83

1.75

1.66

2.87

1.81

1.66

2.75

1.84

38 0.19

37

41

0.06

0.18

40 0.06

44

43

0.13

0.06

41

42

44

43

45

37

38

39

40

0.15

0.15

0.25

0.13

0.16

0.17

0.12

0.11

0.17

40

55

43

45

52

39

37

58

42

0.33

0.10

0.25

0.09

0.13

0.16

43

52

47

48

49

42

40

55

45

0.17

0.28

0.17

0.28

0.28

0.25

45

43

52

48

47

49

0.06

0. 18

0.06

0.13

43

44

45

47

46

48

0.17

0.15

0.15

0.13

0.25

0.16

44 0.09

43

46

47

0.25

0.13

0.16

41 0.28

40

44

43

0.17

0.28

0.17

46 0.28

Table 5 gives the maximum and minimum values of capacitance and inductance and the maximum value for the mutual coupling of two pins from Tables 1 through 4.

Table 5. Comparison of Capacitance, Inductance, and Coupling-Factor (k) Package Parameters

SSOP 48 pin

TSSOP 48 pin

TVSOP 48 pin

LFBGA 96 ball

Capacitance

Pin to GND

(pF)

MAX

MIN

DELTA

MAX

0.443

0.074

0.369

0.410

MIN

DELTA

MAX

MIN

DELTA

MAX

MIN

DELTA

0.077

0.333

0.296

0.048

0.248

0.145

0.046

0.099

Inductance

Die to Pin

(nH)

7.970

5.080

2.890

3.990

2.370

1.620

4.310

2.380

1.930

2.866

1.597

1.269


Pin to Pin

(nH)

0.54

0.40

0.42

0.42

The lower the parasitic parameters for a package are, the better the electrical quality of the package. In this comparison, the SSOP package showed the highest values for all parameters and the largest difference between maximum and minimum values. The SSOP maximum value is 180% higher than the value for the LFBGA 96-ball packages, and the difference between its maximum and minimum values is more than twice as great as for the LFBGA 96-ball package.

A comparison of the LFBGA 96-ball package with the dual in-line Widebus package types also demonstrates the superiority of the ball grid array package over the dual in-line Widebus package. The effects of lead inductance are examined in greater detail in the Electrical

Characteristics section.





SCYA007

Electrical Characteristics

If one or more outputs switch, current flowing through the output lines leads to voltage drops, particularly to the inductance (L

P drop (U

LP

) of the lines of the supply voltage (V

) can be calculated using equation 2:

CC

) and GND. This voltage

U

Lp

+ –Lp

D

D i t

(2)

U

Lp

is superimposed within the circuit on the supply-voltage pins and ground pins and also is directly superimposed on the potential of the outputs, which do not switch. Because the amplitude of the interference is dependent on the current, it increases with increasing numbers of simultaneously switching outputs. Simultaneous switching interference is interference caused by the simultaneous switching of several outputs. There are various methods of reducing the amplitude of the interference.

First, the output current [

∆ i in equation (2)], i.e., the current drive capability, which influences the amplitude of the interference, can be limited. However, this solution is not applicable in many packages because a large current is needed to drive low-impedance lines.

The second option is to reduce the slew rate at the start of switching, or, in other words, to increase the switching duration (

∆ t) in equation 2.

However, because the propagation delay time is measured at the threshold voltage, which is one-half the supply voltage with CMOS or 1.5 V with bipolar technology, the propagation delay time increases proportionately with a steeper output signal edge. Therefore, this solution also is of very limited use.

To reduce signal slew-rate (see Figure 3), TI uses a switching technique known as Output Edge

Control (OEC



) in the output stages of modern logic circuits (see Figure 4).

OEC is a trademark of Texas Instruments Incorporated.





SCYA007

∆ t

1fall

∆ t

2fall

∆ t

1rise

∆ t

2rise

Threshold

Voltage

Threshold

Voltage t

PD1 HL t

PD2 HL

∆ t

PD HL t

PD1 LH t

PD2 LH

∆ t

PD LH

Input Signal Output Signal

Steep Edge

Output Signal

With Output

Edge Control

Output Signal

Slow Edge

Figure 3. Influence of Slew Rate on Propagation Delay Time and the Principle Behind OEC

V

OUT

Q a1

Q a2

Q a3

Q an

Q

G1

Q

G2

Q

Gm

Figure 4. Basic Structure of the OEC Output Stage





SCYA007

The output stage, as a whole, is divided into several mini-output stages whose drain and source connections are each switched in parallel. The gates of these transistors are triggered in a delayed fashion. The resistance of these transistors before the gates, together with the input capacitance of the transistors (Miller capacitance), creates a signal delay line. When a signal is applied to this arrangement, the whole transistor does not switch on at once, rather the individual part transistors conduct one after the other. Thus, the closing of the circuit is delayed so that, on output, there is a transition rise time or fall time of about 2 ns. When switching off, the gates of the output transistors are switched off without delay via transistors Q

G1

to Q

Gm

to limit the current spikes occurring when switching from push-pull output stages. However, any further delaying of edges by this method is not possible.

The measures cited thus far are not sufficient to adequately damp the interference mentioned above. Accordingly, the inductance of the supply-voltage lead (L

P

) must be reduced. The distance of the silicon from the pin connections and, therefore, the inductance, is determined decisively by the length of the lead. Therefore, the best solution is to reduce the size of the package as much as possible. In the case of modern logic circuits, with a propagation delay time of less than 6 ns, a reduction of the inductance in the supply leads results in an increase in speed because the braking effect of lead inductance is reduced.

In Widebus packages, additional grounding and supply connections are inserted along the whole width of the circuit, an arrangement known as staggered pinout. This does increase the number of pins, but the main advantage is that the interference voltages that can arise due to crosstalk between two neighboring connections are significantly reduced. Additionally, this distribution of supply connections results in a significant reduction in lead inductance.

Simultaneous-Switching Behavior

Figure 5 shows the simultaneous-switching measurement setup and the position of the outputs examined.





SCYA007

500

Ω 30 pF

500

Ω

30 pF

Point of measurement

3.3 V

500 Ω

500

Ω

30 pF

500 Ω

30 pF

30 pF

3.3 V

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

VCC

4Y1

4Y2

GND

4Y3

4Y4

40E

1OE

1Y1

1Y2

GND

1B3

1Y4

VCC

2Y1

2Y2

GND

’16244

2A3

2A4

3A1

3A2

GND

3A3

3A4

VCC

4A1

4A2

GND

4A3

4A4

3OE

2OE

1A1

1A2

GND

1A3

1A4

VCC

2A1

2A2

GND

3.3 V

3.3 V

3.3 V

VCC

GND

Control/GND Data

I/O

I/O

Inputs Analog Setup to

Widebus Packages

51 50 49 48 47 46

53 54 52 45 43 44

56 57 55 42 40 41

59 60 58 39 37 38

61 62 63 34 35 36

64 65 66 31 32 33

67 68 69 28 29 30

70 71 72 25 26 27

75 74 73 24 23 22

77 78 76 21 19 20

80 81 79 18 16 17

83 84 82 15 13 14

85 86 87 10 11 12

88 89 90 7 8 9

5 6 91 92 93

94 95 96

4

3 2 1

Outputs Analog Setup to

Widebus Packages

Point of Measurement

Figure 5. Simultaneous-Switching Measurement Setup





SCYA007

For this measurement procedure, one input is connected to a fixed low (L) state, or high (H) state, while all other inputs are switched simultaneously. The outputs of the connecting driver react to the changes in the various inputs with a certain delay, while the nonswitched output should maintain a constant low state (or high state).

However, three factors lead to a reaction by the nonconnected input:

•

Crosstalk between neighboring pins

•

A brief notch in the supply voltage, not measurable from outside, caused by the inductance of the V

CC

lead

•

A brief increase in the grounding level, not measurable from outside, caused by the ground lead

The worst case possible for the measurement procedure is when the distance to the GND and supply pins is greatest. Accordingly, for the Widebus package, measurements are made at pin

37 (2A2) and for the LFBGA at ball 23 (4A4).

Figure 6 sets out the parameters and definitions of significance for this measurement procedure.

Points on the curves are defined as:

V

OHP

(voltage output high peak): High bounce: peak output-voltage value during a static high at the nonswitched output

V

OHV

(voltage output high valley): High bounce: minimum output-voltage value during a static high at the nonswitched output

V

OLP

(voltage output low peak): Ground bounce: peak output-voltage value during a static low at the nonswitched output

V

OLV

(voltage output low valley): Ground bounce: minimum output-voltage value during a static low at the nonswitched output

The critical parameters are V

OLP switching thresholds V

IH

and V

IL

.

and V

OHV

because, in the worst case, they could exceed the





SCYA007

5.00

4.00

3.00

2.00

1.00

0.00

VOHP

VOLP

VOHV

Unswitched Output

in High State

VIH Threshold

VIL Threshold

Unswitched Output in Low State

VOLV

320 330 340 350 360

Time – ns

370 380

Figure 6. Simultaneous-Switching Parameter

390 400

The ground- and high-bounce measurements for the simultaneous switching of several outputs are given in Figures 7 through 14 for the package types investigated in this report.

Ground Bounce SSOP 48-Pin Package, 15 Bits Switching, One Static at Low State

2.0

1.6

1.2

0.8

0.4

0.0

– 0.4

– 0.8

Measured at Unswitched Output in Low State

TSSOP 15 Bits

VIL Threshold

– 1.2

330 335 340 345 350

Input Signal(s)

355 360 365 370 375

3

2

1

380

0

Time – ns

Figure 7. Measured Simultaneous-Switching Ground Bounce, SSOP 48-Pin Package





SCYA007

Ground Bounce TSSOP 48-Pin Package, 15 Bits Switching, One Static at Low State

0.8

0.4

0.0

– 0.4

– 0.8

2.0

1.6

1.2


TSSOP 15 Bits

VIL Threshold

– 1.2

Input Signal(s)

3

2

1

380

0

330 335 340 345 350 355

Time – ns

360 365 370 375

Figure 8. Measured Simultaneous-Switching Ground Bounce, TSSOP 48-Pin Package

Ground Bounce TVSOP 48-Pin Package, 15 Bits Switching, One Static at Low State

2.0

1.6

1.2

VIL Threshold

0.8

0.4

0.0


TVSOP 15 Bits

– 0.4

– 0.8

– 1.2

Input Signal(s)

3

2

1

380

0

330 335 340 345 350 355

Time – ns

360 365 370 375

Figure 9. Measured Simultaneous-Switching Ground Bounce, TVSOP 48-Pin Package





SCYA007

Ground Bounce LFBGA 96-Ball Package, 16/31 Bits Switching, One Static at Low State

2.0

1.6

1.2

0.8

0.4

0.0

– 0.4


LFBGA 16 Bits

LFBGA 31 Bits

VIL Threshold

– 0.8

Input Signal(s)

– 1.2

330 335 340 345 350 355

Time – ns

360 365 370 375

Figure 10. Measured Simultaneous-Switching Ground Bounce, LFBGA 96 Ball

3

2

1

380

0

High Bounce, SSOP 48-Pin Package, 15 Bits Switching, One Static at High State

4.5

4.0

Measured at Unswitched Output in High State

3.5

3.0

2.5

SSOP 15 BIts

VIH Threshold

2.0

1.5

1.0

Input Signal(s)

0.5

0.0

770 780 790 800

Time – ns

810 820

3

2

1

830

0

Figure 11. Measured Simultaneous-Switching High Bounce, SSOP 48-Pin Package





SCYA007

High Bounce, TSSOP 48-Pin Package, 15 Bits Switching, One Static at High State

4.5

4.0

3.5


3.0

2.5

TSSOP 15 Bits

VIH Threshold

2.0

1.5

1.0

Input Signal(s)

0.5

0.0

770

3

2

1

830

0

780 790 800

Time – ns

810 820

Figure 12. Measured Simultaneous-Switching High Bounce, TSSOP 48-Pin Package

High Bounce, TVSOP 48-Pin Package, 15 Bits Switching, One Static at High State

4.5

4.0

3.5


3.0

2.5

2.0

TVSOP 15 Bits

VIH Threshold

1.5

1.0

Input Signal(s)

0.5

0.0

770 780 790 800

Time – ns

810 820

3

2

1

830

0

Figure 13. Measured Simultaneous-Switching High Bounce, TVSOP 48-Pin Package





SCYA007

High Bounce, LFBGA 96-Ball Package, 16/31 Bits Switching, One Static at High State

4.5

4.0

3.5

3.0

2.5

2.0

1.5


LFBGA 16 Bits

LFBGA 31 Bits

VIH Threshold

1.0

Input Signal(s)

0.5

0.0

770 780 790 800

Time – ns

810 820

3

2

1

830

0

Figure 14. Measured Simultaneous-Switching High Bounce, LFBGA 96 Ball

The results shown in Figures 7 through 14 examine only the case in which all outputs but one are connected. It is also of interest to know the relationship between the number of simultaneously switching outputs and the level of interference. These results are shown in

Figures 15 through 18. The dotted lines show the linearized increase in the ground/high bounce relative to the number of connected outputs.





1500

1000

500

0

–500

–1000

SSOP VOLP

Linear (SSOP VOLP)

LVCH16244A in SSOP 48-Pin Package

SSOP VOLV

Linear (SSOP VOLV)

VOLP (Number Switching)

VOLV (Number Switching)

GND

–1500

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Number of Simultaneously Switching Outputs

LVCH16244A in TSSOP 48-Pin Package

1500

TSSOP VOLP

Linear (TSSOP VOLP)

TSSOP VOLV

Linear (TSSOP VOLV)


1000

500

SCYA007

0

–500

–1000


GND

–1500

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


Figure 15. Simultaneous-Switching Ground Bounce ,

SSOP 48 Pin (top), TSSOP 48 Pin (bottom)





SCYA007

1500

1000

500

0

TVSOP VOLP

LVCH16244A in TVSOP 48-Pin Package

Linear (TVSOP VOLP)

TVSOP VOLV

Linear (TVSOP VOLV)


GND

–500

–1000


–1500

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


1500

LVCH16244A in LFBGA 96-Ball Package

LFBGA VOLP

Linear (LFBGA VOLP)

LFBGA VOLV

Linear (LFBGA VOLV)

1000

500


GND 0

–500


–1000

–1500

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Figure 16. Simultaneous-Switching Ground Bounce,

TVSOP 48 Pin (top), LFBGA 96 Ball (bottom)





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LVCH16244A in SSOP 48-Pin Package

4.5

4

3.5

3

2.5


VOH Static Condition

2

1.5


1

SSOP VOHP

Linear (SSOP VOHP)

SSOP VOHV

Linear (SSOP VOHV)

0.5

0

1 2 3 4 5 6 7 8 9 10 11


12 13 14 15

LVCH16244A in TSSOP 48-Pin Package

4.5

4

TSSOP VOHP

Linear (TSSOP VOHP)

TSSOP VOHV

Linear (TSSOP VOHV)


3.5


3

2.5

2

1.5


1

0.5

0

1 2 3 4 5 6 7 8 9 10 11


12 13 14 15

Figure 17. Simultaneous-Switching Ground Bounce,

SSOP 48 Pin (top), TSSOP 48 Pin (bottom)





SCYA007

4.5

4

3.5

3

2.5

2

1.5

1

TVSOP VOHP

Linear (TVSOP VOHP)

LVCH16244A in TVSOP 48-Pin Package

TVSOP VOHV

Linear (TVSOP VOHV)




1.5

1

0.5

0.5

0

4.5

4

1 2 3 4 5 6 7 8 9 10 11 12 13


LVCH16244A in LFBGA 96-Ball Package

14 15

LFBGA VOHP

Linear (LFBGA VOHP)

LFBGA VOHV

Linear (LFBGA VOHV)


3.5


3

2.5

2


0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Figure 18. Simultaneous-Switching High Bounce,

TVSOP 48-Pin (top), LFBGA 96 Ball (bottom)





SCYA007

The ground- and high-bounce interference voltages produced by simultaneous switching must not exceed the threshold voltage range for the subsequent input stage (1.4 V to 1.5 V). All the package types investigated meet this requirement for the investigated logic functions

SN74LVCH16244A and SN74LVCH32244A. Although the components in the SSOP and TSSOP packages slightly exceed the input voltage threshold for the relevant logic states, switching of the subsequent stage is not expected because the typical threshold voltage of 1.5 V is not reached under any circumstances.

The best result obtained in this investigation was for the ball grid array package. The positive effect of the favorable ball arrangement with additional GND balls is evident.

A small part of the differences measured could be due to component spread rather than being exclusively the result of the package being measured.

The process technology involved also has a decisive effect on the interference level. However, the results here give an idea of the general tendencies that apply to other logic families as well.

Increase in Propagation Delay Time

The package type also influences the increase in propagation delay that occurs when several outputs switch simultaneously. The inductance of the supply and ground leads is the decisive factor. To measure this behavior for various packages, the relation between propagation delay and the number of outputs switching was measured. (see Figures 19 and 20). In all cases, the devices measured were from the LVC family operated at a supply voltage of 3.3 V and whose outputs were, in accordance with the data sheet, loaded with 30 pF and 500

Ω

:

SN74LVCH16244A for the Widebus package and SN74LVCH32244A for the LFBGA 96-pin package.





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Rise Edge, Low-to-High Transition

1.2

1.1

1

1.5

1.4

1.3

0.9

0.8

0.7

TSSOP 48 Pin

SSOP 48 Pin

TVSOP 48 Pin

LFBGA 96 Ball

0.6

0.5

0.4

0.3

0.2

0.1

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Number of Outputs Switching

Figure 19. Rising-Edge Propagation Delay Time Relative to the Number of

Simultaneously Switching Outputs for the SSOP, TSSOP, TVSOP, and LFBGA Packages

Falling Edge, High-to-Low Transition

1.2

1.1

1

0.9

0.8

0.7

1.5

1.4

1.3

0.6

0.5

0.4

0.3

0.2

0.1

SSOP 48 Pin

TSSOP 48 Pin

LFBGA 96 Ball

TVSOP 48 Pin

0

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Number of Outputs Switching

Figure 20. Falling-Edge Propagation Delay Time Relative to the Number of

Simultaneously Switching Outputs for the SSOP, TSSOP, TVSOP, and LFBGA Packages





SCYA007

In Figures 19 and 20, the Y-axis shows the increase in propagation delay time and the X-axis shows the number of outputs switching. The representation of the increase in propagation delay time was selected in order to eliminate fluctuations in absolute switching speed that occur as a result of variations in component tolerances. Because the absolute increase in propagation delay time for the rising edges is 0.3 ns to 0.8 ns (for the falling edge, 0.9 ns to 1.3 ns), the measurements are at the upper limits of achievable measurement accuracy, the given measurement setup, and the measuring instruments used. This is the reason for the nonlinearities of the data curves.

The SSOP package produced the worst results for all tests, while the TVSOP 48-pin gave the best values for a Widebus package.

Again, the LFBGA package performed well.





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Thermal Properties

When developing a digital system, the thermal behavior of the package must be taken into account.

The small size of surface-mounted devices means that the dissipation of the heat arising from power loss becomes increasingly critical as components become smaller.

The thermal resistance of packages relative to airflow is given in Table 6. The maximum power consumption curves in relation to the ambient temperature for the package types investigated in this report are given in Figures 21 through 24.

Table 6. Comparison of the Thermal Resistance (R θ

JA of Different Packages

)

Package

SSOP 48 pin

TSSOP 48 pin

TVSOP 48 pin

LFBGA 96 ball

Thermal Resistance at Various Airflows

0 m/s

93.5

89.1

92.9

40

0.83 m/s

69.9

78.5

80.9

37.5

1.38 m/s

63.8

75.1

77.1

37

2.78 m/s

57.1

69.4

71

35.7

In equation 3, the chip temperature is derived from the thermal resistance, the component’s overall power loss, and the ambient temperature.

T

J

+ R

QJA

P

TOT

) T

A

Where:

T

J

R

QJA

P

TOT

T

A

= chip temperature (J = junction)

= thermal resistance of the chip (junction) at the ambient air temperature

= component’s overall power loss

= ambient temperature

(3)

The total power consumption (P

TOT

) of a circuit is determined mainly by:

•

Circuit standby power consumption (P

Stat

)

•

Power consumption (P

S

) caused by the current spike that occurs when switching an output

•


L

) necessary for the transition from one logic state to the other of the capacitive load connected at the output.

The equation for calculating P

TOT

is:

P

TOT

+ P

Stat

) P

S

) P

L

Where:

P

Stat

P

S

P

L

= static power consumption

= dynamic power consumption caused by current spikes

= dynamic power consumption caused by capacitance load

(4)

The static share (P

Stat

) of the power consumption, which is caused by the component itself, can be calculated from the parameters I

CCL

, I

CCH

, and I

CCZ

, given in the specification sheet, the supply voltage, and the relationship of active high, low, and high impedance. Equation 6 gives the amount of static power consumption. However, this power consumption does not depend on the number of switched outputs, but on the share of the signal.





SCYA007

The dynamic share of the power consumption depends on the factor’s line impedance and length; the output load of the input and output rates; the duty cycle from active high, low, and high impedance; and the amplitude and duration of current peaks at the moment of switching.

The definition of share is given in equation 5: share high(low; Z

)

+

T

T high(low; Z) high

)

T low

)

T

Z

Where:

T high,low,Z

= average amount of time within a signal period

(5)

P

Stat n

+ S k

+ 1

V

CC(share( k )high

I

CCH

) share low

( k ) I

CCL n

) share

Z

( k ) I

CCZ

) (6)

Where:

V

CC

I

CCL

, share low

= supply voltage

(k) = current consumption for static low at output, average percentage share of the k th

output

I

CCH

, share high

(k) = current consumption for static high at output, average percentage share of the k th

output

I

CCZ

, share

Z

(k) = current consumption for high-impedance state at output, average percentage share of the k th

output k = number of the switched output of the circuit n = number of inputs in the circuit

The power consumption caused by the current spikes can be calculated using equation 7:

P

S n

+ S k

+ 1

V

CC

I

S t s

f k

Where:

I s

= amplitude of current spikes t s

= duration of current spikes f = clock rate (repetition rate) k = number of the switched outputs of the circuit n = number of switched outputs

(7)

The technology involved is a major factor in the amplitude of current spikes. With bipolar output stages, the amplitude of current spikes is less. They are more clearly revealed by the rising signal edges.





SCYA007


L

) is caused by external loads at the outputs of the circuit. This power is taken up by the circuit for the transition from one logic state to the other, and can be calculated by equation 8:

P

L

+ n

S k

+ 1

V

CC

V swing

C

L

( k ) f( k )

2

Where:

C

L

(k) = capacitive load connected to the k th

output

V swing

= signal swing V

OH

– V

OL f(k) = frequency applied to the k th

input

(8)

In addition to the power consumption shares mentioned above, additional power consumption can result from bus conflicts. A bus conflict occurs when two drivers on a line simultaneously create different logic levels. This problem can be avoided when designing a circuit by using proper timing arrangements.

Power consumption and chip temperature can be calculated, using the LVTH16244A as an example.

The SN74LVTH16244A 16-bit driver, with V

CC

= 3.6 V, runs at a clock speed of 33 MHz. All of the outputs are switched. The symmetrical driver output load in the static case is 1 M

Ω.

The overall capacitive load totals 90 pF per output. On average, each output delivers logical high, low, and high-impedance one-third of the time. The current spikes at the moment of switching reach values of 20 mA in the LVT family. The duration of the current spike is 5 ns, and there are no bus conflicts.

Because the assigned load conditions and frequency are the same for all inputs and outputs, equations 5 through 8 are simplified. The summation and the control variables n and k are eliminated from equation 6. The factor 16 is added in equations 7 and 8 to reflect 16 inputs and outputs.

On the basis of the data-sheet values for the supply current (I

CC high-impedance state, for the component SN74LVTH16244A:

) in the high, low, and

•

I

CCH/Z

= 190

µ

A (for V

CC

= 3.6 V, I

O

= 0, V

I

= V

CC

or GND, outputs high or high impedance)

•

I

CCL

= 5 mA (for V

CC

= 3.6 V, I

O

= 0, V

I

= V

CC

or GND, outputs low)

P

Stat

is derived for one-third low, one-third high, and one-third high impedance of the driver as follows:

P

Stat

+

3.6 V ǒ

5 mA

3

) 0.19 mA

3

) 0.19 mA

Ǔ

+

3

6.46 mW

(9)

These values also give the dynamic share in accordance with equations 7 and 8, and result in equation 10.

P dyn

+

16 ǒ

P s

)

P

L

Ǔ

(10)

With the given values, equation 10 results in

P dyn

+

16 ǒ

3.6 V 20 mA 5 ns 33 MHz

)

3.6 V

3.6 V 90 pF 33 MHz

2

Ǔ

+ 0.19 W ) 0.308 W + 0.498 W

(11)





SCYA007

The overall result in this case is:

P

TOT

+

6.46 mW

)

0.498 W

+

~ 0.5 W

The temperature on the silicon can be determined from the thermal resistance (R

QJA

) of the package, and the ambient temperature, with the aid of equation 3. R

QJA

corresponds to the capacity to dissipate heat to the ambient environment. Four package options are available:

SSOP: R

QJA

= 89

°

C/W

TSSOP: R

QJA

= 93

°

C/W

TVSOP: R

QJA

= 94

°

C/W

LFBGA: R

QJA

= 40

°

C/W

(12)

The thermal resistance given in each case is without any additional cooling measures. For the packages investigated, the following chip temperatures (T

J temperature of 25

°

C, and without additional cooling:

) are derived at an ambient

SSOP package: T

J

= 89

°

C/W

×

0.5 W + 25

°

C = 69.5

°

C

TSSOP package: T

J

= 93

°

C/W

×

0.5 W + 25

°

C = 71.5

°

C

TVSOP package : T

J

= 94

°

C/W

×

0.5 W + 25

°

C = 72.0

°

C

LFBGA 96 package: T

J

= 40

°

C/W

×

0.5 W + 25

°

C = 45.0

°

C

If the temperature rises further as a result of greater output loads, leading to chip temperatures in excess of 150

°

C, additional cooling devices or fans must be used to dissipate the excess heat.

Figures 21 through 24 show the characteristic curves for power consumption relative to ambient temperature. In all cases, an upper limit value for the chip temperature of 150

°

C is assumed.

Airflow ranges from 0 m/s to 2.78 m/s. An airflow of 0 m/s relates to an application using no additional cooling measures, while 2.78 m/s is for a system application using a cooling fan.





SCYA007

1.75

1.50

1.25

1.00

0.75

Power Derating Curves for SSOP 48-Pin Package

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

1.38 m/s

0.83 m/s

2.78 m/s

0 m/s

0.25

0.00

20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

Ambient Temperature

Figure 21. Maximum Power Consumption Relative to Ambient Temperature,

T

J

= 150

°

C, SSOP 48-Pin Package

Power Derating Curves for TSSOP 48-Pin Package

2.00

1.38 m/s 2.78 m/s

0.83 m/s

0 m/s

0.50

0.25

0.00

20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

Ambient Temperature – o C


T

J

= 150

°

C, TSSOP 48-Pin Package





SCYA007

Power Derating Curves for TVSOP 48-Pin Package

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

1.38 m/s

2.78 m/s

0.83 m/s

0 m/s

0.00

20 25 30 35 40 45 50 55 60 65

Ambient Temperature – o

C

70 75 80 85 90 95 100


T

J

= 150

°

C, TVSOP 48-Pin Package

Power Derating Curves for LFBGA 96-Ball Package

3.75

2.78 m/s

1.38 m/s

3.25

2.75

0.83 m/s

0 m/s

2.25

1.75

1.25

25 30 35 40 45 50 55 60 65

Ambient Temperature –

°

C

70 75 80 85 90


T

J

= 150

°

C, LFBGA 96 Ball

Although the LFBGA 96-pin package is the smallest, in this comparison it showed the lowest heat resistance. Table 6 shows that the LFBGA 96-pin package dissipates heat more effectively by a factor of more than two, compared to any of the other packages investigated. This leads to the added advantage that many systems do not require additional cooling provisions.





SCYA007

Package Dimensions and Size Comparison

Dimensions of the packages discussed in this report are provided in Figures 25 through 28.

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

48

0.012 (0,305)

0.008 (0,203)

25

0.005 (0,13) M

0.006 (0,15) NOM

0.299 (7,59)

0.291 (7,39)

0.420 (10,67)

0.395 (10,03) Gage Plane

0.010 (0,25)

1 24

0

°

– 8

°

A

0.040 (1,02)

0.020 (0,51)

Seating Plane

0.004 (0,10)

0.110 (2,79) MAX 0.008 (0,20) MIN

DIM

PINS **

A MAX

A MIN

28

0.380

(9,65)

0.370

(9,40)

48 56

0.630

(16,00)

0.730

(18,54)

0.620

(15,75)

0.720

(18,29)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

Figure 25. Dimensions of the SSOP 28-, 48-, and 56-Pin Packages

4040048 / D 08/97





DGG (R-PDSO-G**)

48 PINS SHOWN

48

0,50

0,27

0,17

25

0,08 M

SCYA007

PLASTIC SMALL-OUTLINE PACKAGE

1

A

24

6,20 8,30

6,00 7,90 0,15 NOM

Gage Plane

0

°

– 8

°

0,25

0,75

0,50

1,20 MAX

0,15

0,05

Seating Plane

0,10

DIM

PINS **

A MAX

48

12,60

56 64

14,10 17,10

A MIN 12,40 13,90 16,90

NOTES: A. All linear dimensions are in millimeters.


C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

Figure 26. Dimensions of the TSSOP 48-, 56-, and 64-Pin Packages

4040078 / F 12/97





SCYA007

DGV (R-PDSO-G**)

24 PINS SHOWN

0,40

24

0,23

0,13

13

0,07 M

PLASTIC SMALL-OUTLINE PACKAGE

1 12

4,50

4,30

6,60

6,20

0,16 NOM

0

°

– 8

°

Gage Plane

0,25

0,75

0,50

A

1,20 MAX

0,15

0,05

Seating Plane

0,08

PINS **

DIM

A MAX

A MIN

14

3,70

3,50

16

3,70

3,50

20

5,10

4,90

24

5,10

4,90

48

9,80

9,60

56

11,40

11,20



C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

Figure 27. Dimensions of the TVSOP 48-, 56-, and 64-Pin Packages

4073251/C 08/98





GKE (R-PBGA-N96)

5,60

5,40

13,60

13,40

0,95

0,85

0,55

0,45

0,08 M

0,45

0,35

1,40 MAX

Seating Plane

0,10

SCYA007

PLASTIC BALL GRID ARRAY

E

D

C

B

A

H

G

F

L

K

J

T

R

P

N

M

0,80

4,00 TYP

0,40

1 2 3 4 5 6

12,00 TYP

4188953/A 10/98



C. MicroStar BGA



configuration

Figure 28.

Dimensions of the LFBGA 96-Ball Package

MicroStar BGA is a trademark of Texas Instruments Incorporated.





SCYA007

Figure 29 shows the amount of space needed for a 32-bit interface using the package types discussed in this report. The LFBGA 96-ball package requires the least amount of space.

Creating the interface using two SSOP packages requires 4.5 times as much space.

The low-profile, fine-pitch, 96-ball grid array package requires 2.32 mm

2

per bit, while the

TVSOP package requires almost twice as much space at 4.14 mm

2

per bit. The space required using the TSSOP package is 6.65 mm

2

per bit, and for the SSOP package the space is

10.69 mm 2 per bit.

Height 2.8 mm

0.635 mm Pitch

Height 1.2 mm

0.5 mm Pitch

48-Pin

DL

SSOP

Height 1.4 mm

0.8 mm Pitch

Height 1.2 mm

0.4 mm Pitch

48-Pin

DGV

TVSOP

48-Pin

DGG

TSSOP

96-Ball

GKE

LFBGA

48-Pin

DGV

TVSOP

48-Pin

DGG

TSSOP

48-Pin

DL

SSOP

5.5 mm 6.4 mm 8.1 mm 10.32 mm

32-Bits

74.25 mm2

32-Bits

132.5 mm2

32-Bits

213.0 mm2

32-Bits

342.0 mm2

Figure 29. Space Needed for a 32-Bit Interface Using Various Packages Options





SCYA007

Summary

The trend toward 32-bit, or wider, bus systems reflects the need to increase the data rate in modern computer systems, and there is a corresponding demand for bus drivers supporting wider data formats.

To meet these requirments, TI has introduced the Widebus devices and low-profile fine-pitch ball grid array package.

Optimizing the voltage supply via staggered pinning for the Widebus packages ensures extremely low interference voltages, even during simultaneous switching of several outputs

(simultaneous-switching interference). Additionally, Widebus packages allow the very high speeds that can be achieved with modern semiconductor technology to be fully exploited at the system level as well.

The TVSOP package is the smallest Widebus package. It gives the best results among the

Widebus dual in-line packages for the ground-bounce and simultaneous-switching parameters of several outputs. The additional delay caused by simultaneously switching outputs also was the smallest with this package. However, the TVSOP package currently is still relatively difficult to process due to its very small pin-to-pin spacing of 0.4 mm.

The LFBGA package features another improvement: terminals are in the form of balls, leading to a further reduction in parasitic inductance.

In addition to the circuit-board space advantages it affords, the LFBGA package achieves a marked improvement in signal quality for all measurements as a result of its low package parasitics and, particularly, its minimal inductance.

The LFBGA package also demonstrates good heat resistance. A

θ

JA

of 40

°

C/W represents at least twice the heat dissipation efficiency of any of the other Widebus packages investigated for this report.

Acknowlegment

The author of this application report is Johannes Huchzermeier.





SCYA007

Glossary

AC

ABT

AHC

ALVC

Advanced CMOS

Advanced BiCMOS Technology

Advanced High-Speed CMOS

Advanced Low-Voltage CMOS

ALVT

ALS

AS

AVC

Auto3-state

Advanced Low-Voltage Technology

Advanced Low-Power Schottky

Advanced Schottky

Advanced Very-Low-Voltage CMOS

Devices with Auto3-state tolerate a higher voltage level at the outputs during active-high state at the output. (also called overvoltage protection)

BCT

BiCMOS

BiCMOS technology

Combination of the bipolar and CMOS manufacturing processes, with

CMOS input structure and bipolar output structure

Bonding wire

Bus hold

Coupling factor

GND

HC

I/O

Leadframe

LFBGA

LS

LVC

LV

LVT

Wire connecting the chip and the pin

An input circuit that holds the last valid state before the onset of the undefined state on the bus until a new valid logic state ensues

Reciprocal inductive coupling between two neighboring pins on the basis of the transformer equation

Ground (UK = Earth)

High-speed CMOS

Input/Output

Metal mask to which the chip is attached, with the pins leading outward.

Low-profile fine-pitch ball grid array

Low-Power Schottky

Low-Voltage CMOS

Low-Voltage CMOS, originally designed for 3.3-V V

CC

, but also usable with a 5-V V

CC

Low-voltage technology





OEC

TM

R

Load

S

SPICE

SSOP

TSSOP

TVSOP

TTL

V

CC

SCYA007

Output Edge Control, a procedure patented by Texas Instruments that reduces the output-signal slew rate.

Load resistance

Schottky

Simulation Program with Integrated Circuit Emphasis

Shrink Small-Outline Package

Thin Shrink Small-Outline Package

Thin Very Small-Outline Package

5-V Logic, Transistor-Transistor Logic

Supply voltage





SCYA007

Bibliography (Texas Instruments Publications)

1.

AVC Logic family Technology and Applications, 1998, literature number SCEA006A

2.

ABT Logic Advanced BiCMOS Technology, Databook, 1998, literature number SCBD002C

3.

Advanced CMOS Logic, Databook, 1996, literature number SCADE02

4.

Logic Selection Guide and Databook CD-ROM, April 1998, literature number SCBC001B

5.

Cross Bar Technology & Cross Bar Technology Low Voltage (CBT & CBTLV), 1999, literature number SCDD001B

6.

AHC/AHCT Logic, Databook 1997, literature number SCLD003A

7.

Design Considerations for Logic, 1997, literature number SDYA002

8.

Digital Design Seminar – Reference Manual, 1998, literature number SDYDE01B

9.

What a Designer Should Know, November 1994, literature number SDZAE03

10.

Electromagnetic Emission from Logic Circuits, March 1998, literature number SDZAE17,

11.

The Bergeron Method, September 1985, literature number SDZAE02

12.

Bus-Interface Devices with Output-Damping Resistors or Reduced-Drive Outputs, August

1997, literature number SCBA012A

13.

Live Insertion, November 1995, literature number SCZAE07

14.

TVSOP Thin Very Small Outline Package, August 1997, literature number SDZAE02

15.

Low Voltage Logic Families, April 1997, literature number SCVAE01A

16.

Bushold Circuit, July 1992, literature number SDZAE15

17.

PCB Design Guidelines for Reduced EMI, Mai 1998, literature number SDYA017

18.

Input and Output - Characteristics of Digital Integrated Circuits at V

CC

Voltage, literature number SCYA002

= 5 V Supply

19.

Input and Output - Characteristics of Digital Integrated Circuits at V

CC

Voltage, literature numberSCYA003

= 3.3 V Supply

20.

G.Becke, E.Haseloff, Das TTL- Kochbuch (The TTL Cook Book), literature number

SDYZG17





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Texas Instruments Comparison of Electrical & Thermal Parameters of Widebus SMD and LFBGA Packages Application Note

Assistant Bot

Application Report

Comparison of Electrical and Thermal Parameters of

Widebus

SMD SSOP, TSSOP, TVSOP, and LFBGA

Packages

Introduction

Package Parameters

Packages and Package Parameters Investigated

Electrical Characteristics

Simultaneous-Switching Behavior

Increase in Propagation Delay Time

Thermal Properties

Package Dimensions and Size Comparison

DL (R-PDSO-G) PLASTIC SMALL-OUTLINE PACKAGE**

DGG (R-PDSO-G)**

PLASTIC SMALL-OUTLINE PACKAGE

DGV (R-PDSO-G)**

PLASTIC SMALL-OUTLINE PACKAGE

GKE (R-PBGA-N96)

PLASTIC BALL GRID ARRAY

Summary

Acknowlegment

Glossary

Bibliography (Texas Instruments Publications)