Si5350C B

Si5350C B
S i 5 3 5 0 C -B
F ACTORY - P ROGRAMMABLE A NY - F REQUENCY CMOS
C L O C K G ENERATOR + PLL
Features
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www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz
Exact frequency synthesis at each
output (0 ppm error)
Glitchless frequency changes
Low output period jitter: < 70 ps pp, typ
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Loss of Lock Status (LOLB)
Supports static phase offset
Rise/fall time control
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Operates from a low-cost, fixed
frequency crystal: 25 or 27 MHz
Separate voltage supply pins provide
level translation:
Core VDD: 1.8V, 2.5 V or 3.3 V
Output VDDO: 1.8 V, 2.5 V, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption (25 mA
core, typ)
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld instrumentation
20-QFN
Ordering Information:
See Page 18
Applications
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10-MSOP
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Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5350C generates free-running and/or synchronized clocks selectable on each
of its outputs. A dual PLL + high resolution MultiSynthTM fractional divider
architecture enables this user-definable custom timing device to generate any of the
specified output frequencies at any of its outputs. This allows the Si5350C to replace
a combination of crystals, crystal oscillators, and synchronized clocks (PLL). Custom
pin-controlled Si5350C devices can be requested using the ClockBuilder web-based
part number utility (www.silabs.com/ClockBuilder).
Functional Block Diagram
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si5350C-B
Si5350C-B
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number
I2C or Pin
Frequency Reference
Programmed?
Outputs
Datasheet
Si5351A-B-GT
I2C
XTAL only
Blank
3
Si5351-B
Si5351A-B-GM
I2C
XTAL only
Blank
8
Si5351-B
Si5351B-B-GM
I2C
XTAL and/or Voltage
Blank
8
Si5351-B
Si5351C-B-GM
I2C
XTAL and/or CLKIN
Blank
8
Si5351-B
Si5351A-Bxxxxx-GT
I2C
XTAL only
Factory Pre-Programmed
3
Si5351-B
Si5351A-Bxxxxx-GM
I2C
XTAL only
Factory Pre-Programmed
8
Si5351-B
Si5351B-Bxxxxx-GM
I2C
XTAL and/or Voltage
Factory Pre-Programmed
8
Si5351-B
Si5351C-Bxxxxx-GM
I2C
XTAL and/or CLKIN
Factory Pre-Programmed
8
Si5351-B
Si5350A-Bxxxxx-GT
Pin
XTAL only
Factory Pre-Programmed
3
Si5350A-B
Si5350A-Bxxxxx-GM
Pin
XTAL only
Factory Pre-Programmed
8
Si5350A-B
Si5350B-Bxxxxx-GT
Pin
XTAL and/or Voltage
Factory Pre-Programmed
3
Si5350B-B
Si5350B-Bxxxxx-GM
Pin
XTAL and/or Voltage
Factory Pre-Programmed
8
Si5350B-B
Si5350C-Bxxxxx-GT
Pin
XTAL and/or CLKIN
Factory Pre-Programmed
3
Si5350C-B
Si5350C-Bxxxxx-GM
Pin
XTAL and/or CLKIN
Factory Pre-Programmed
8
Si5350C-B
Notes:
1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2. Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
2
Rev. 1.0
Si5350C-B
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si5350C Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Configuring the Si5350C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. External Clock Input Pin (CLKIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1. 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.2. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9. 10-pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
10. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Rev. 1.0
3
Si5350C-B
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter
Symbol
Ambient Temperature
TA
Core Supply Voltage
Output Buffer Voltage
Test Condition
VDD
VDDOx
Min
Typ
Max
Unit
–40
25
85
°C
1.71
1.8
1.89
V
2.25
2.5
2.75
V
3.0
3.3
3.60
V
1.71
1.8
1.89
V
2.25
2.5
2.75
V
3.0
3.3
3.60
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD
and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all
VDDOx be powered up either before or at the same time as VDD.
Table 3. DC Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Core Supply Current*
Output Buffer Supply
Current (Per Output)*
Input Current
Output Impedance
Symbol
Test Condition
Min
Typ
Max
Unit
Enabled 3 outputs
—
20
35
mA
Enabled 8 outputs
—
25
45
mA
Power Down (PDN = VDD)
—
—
50
µA
IDDOx
CL = 5 pF
—
2.2
5.6
IP1-P3
Pins P1, P2, P3
VP1-P3 < 3.6 V
—
—
10
µA
IP0
Pin P0
—
—
30
µA
ZOI
3.3 V VDDO, default high
drive.
—
50
—

IDD
*Note: Output clocks less than or equal to 100 MHz.
4
Rev. 1.0
mA
Si5350C-B
Table 4. AC Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Power-Up Time
TRDY
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
2
10
ms
Powerup Time, PLL Bypass
Mode
TBYP
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
0.5
1
ms
Output Enable Time
TOE
From OEB assertion to valid
clock output, CL = 5 pF, fCLKn
> 1 MHz
—
—
10
µs
Output Frequency Transition
Time
TFREQ
fCLKn > 1 MHz
—
—
10
µs
Spread Spectrum Frequency
Deviation
SSDEV
Down Spread
Selectable in 0.1% steps
–0.1
—
–2.5
%
30
31.5
33
kHz
Spread Spectrum
Modulation Rate
SSMOD_C
Table 5. Input Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Min
Typ
Max
Units
fXTAL
25
—
27
MHz
P0-P3 Input Low Voltage
VIL_P0-3
–0.1
—
0.3 x VDD
V
P0-P3 Input High Voltage
VIH_P0-3
VDD = 2.5 V or 3.3 V
0.7 x VDD
—
3.60
V
VDD = 1.8 V
0.8 x VDD
—
3.60
V
CLKIN Frequency Range
fCLKIN
10
—
100
MHz
CLKIN Input Low Voltage
VIL_CLKIN
–0.1
—
0.3 x VDD
V
CLKIN Input High Voltage
VIH_CLKIN
0.7 x VDD
—
3.60
V
Crystal Frequency
Symbol
Test Condition
Rev. 1.0
5
Si5350C-B
Table 6. Output Characteristics
VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Frequency Range
Symbol
1
Test Condition
Min
Typ
Max
Units
0.0025
—
200
MHz
FCLK < 100 MHz
—
—
15
pF
FCLK < 160 MHz, Measured
at VDD/2
45
50
55
%
FCLK > 160 MHz, Measured
at VDD/2
40
50
60
%
20%–80%, CL = 5 pF
—
1
1.5
ns
VDD – 0.6
—
—
V
—
—
0.6
V
20-QFN, 4 outputs running,
1 per VDDO
‐
40
95
ps, pk‐pk
10-MSOP or 20-QFN, all
outputs running
‐
70
155
ps, pk‐pk
20-QFN, 4 outputs running,
1 per VDDO
—
50
90
ps, pk
10-MSOP or 20-QFN, all
outputs running
—
70
150
ps, pk
FCLK
Load Capacitance
CL
Duty Cycle
DC
Rise/Fall Time
tr/tf
Output High Voltage
VOH
Output Low Voltage
VOL
Period Jitter2,3
JPER
Cycle-to-cycle Jitter2,3
JCC
CL = 5 pF
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50  output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,
24.576, 22.5792, 28.322, 125, and 48 MHz.
Table 7. 25 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
—
25
—
MHz
Load Capacitance
CL
6
—
12
pF
rESR
—
—
150

dL
100
—
—
µW
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
6
Rev. 1.0
Si5350C-B
Table 8. 27 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
—
27
—
MHz
Load Capacitance
CL
6
—
12
pF
rESR
—
—
150

dL
100
—
—
µW
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 9. Thermal Characteristics
Parameter
Symbol
Test Condition
Thermal Resistance
Junction to Ambient
JA
Still Air
Thermal Resistance
Junction to Case
JC
Still Air
Package
Value
Unit
10-MSOP
131
°C/W
20-QFN
119
°C/W
20-QFN
16
°C/W
Table 10. Absolute Maximum Ratings
Parameter
DC Supply Voltage
Input Voltage
Junction Temperature
Symbol
Test Condition
VDD_max
Value
Unit
–0.5 to 3.8
V
VIN_P1-3
Pins P1, P2, P3
–0.5 to 3.8
V
VIN_P0
P0
–0.5 to (VDD+0.3)
V
VIN_XA/B
Pins XA, XB
–0.5 to 1.3 V
V
–55 to 150
°C
TJ
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Rev. 1.0
7
Si5350C-B
2. Typical Application
2.1. Si5350C Replaces Multiple Clocks and XOs
The Si5350C is a clock generation device that provides both synchronous and free-running clocks for applications
where power, board size, and cost are critical. An example application is shown in Figure 1. Any other combination
is possible.
Free-running
Clocks
XA
OSC
27 MHz
PLL
Multi
Synth
0
Multi
Synth
1
XB
Multi
Synth
2
CLKIN
PLL
54 MHz
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Si5350C
CLK0
125 MHz
CLK1
48 MHz
CLK2
28.322 MHz
Ethernet
PHY
USB
Controller
HDMI
Port
CLK3
74.25 MHz
CLK4
74.25/1.001 MHz
CLK5
24.576 MHz
Video/Audio
Processor
Synchronous
Clocks
Figure 1. Replacing multiple XTAL/XOs and PLLs with one Si5350C
2.2. Applying a Reference Clock at XTAL Input
The Si5350C can be driven with a clock signal through the XA input pin. This is especially useful when in need of
generating clock outputs in two synchronization domains; one reference clock can be provided at the CLKIN pin
and at XA.
VIN = 1 VPP
25/27 MHz
XA
0.1 µF
XB
PLLA
Multi
Synth
1
OSC
PLLB
Note: Float the XB input while driving
the XA input with a clock
Figure 2. Si5350C Driven by a Clock Signal
8
Rev. 1.0
Multi
Synth
0
Multi
Synth
N
Si5350C-B
2.3. HCSL Compatible Outputs
The Si5350C can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair.
ZO = 50 
PLLA
Multi
Synth
0
0
R1
511 
240 
OSC
PLLB
Multi
Synth
1
ZO = 50 
0
HCSL
CLKIN
R1
511 
240 
Multi
Synth
N
R2
R2
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
Figure 3. Si5350C Output is HCSL Compatible
Rev. 1.0
9
Si5350C-B
3. Functional Description
The architecture of the Si5350C generates up to eight non-integer-related frequencies in any combination of freerunning and/or synchronous clocks. A block diagram of both the 3-output and the 8-output versions are shown in
Figure 4. Free-running clocks are generated using the on-chip oscillator + PLL, and the clock input pin (CLKIN)
provides an external input reference for the synchronous clocks. Each MultiSynthTM is configurable with two
frequencies (F1_x, F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK5).
10-MSOP
XA
OSC
VDDO
VDD
MultiSynth 0
F1_0
PLL
A
XB
F2_0
R0
CLK0
R1
CLK1
R2
CLK2
FS
MultiSynth 1
F1_1
PLL
B
CLKIN
F2_1
FS
P0
MultiSynth 2
F1_2
Control
Logic
F2_2
FS
MultiSynth 3
GND
VDD
20-QFN
MultiSynth 0
F1_0
XA
OSC
PLL
A
F2_0
R0
CLK0
FS
XB
MultiSynth 1
F1_1
PLL
B
CLKIN
VDDOA
F2_1
CLK1
R1
FS
MultiSynth 2
F1_2
F2_2
VDDOB
R2
CLK2
FS
MultiSynth 3
F1_3
F2_3
CLK3
R3
FS
MultiSynth 4
F1_4
F2_4
VDDOC
R4
CLK4
FS
MultiSynth 5
F1_5
P0
P1
P2
F2_5
Control
Logic
CLK5
R5
FS
VDDOD
MultiSynth 6
F1_6
P3
R6
CLK6
MultiSynth 7
F1_7
CLK7
R7
GND
Figure 4. Block Diagrams of the Si5350C Devices with 3 and 8 outputs
10
Rev. 1.0
Si5350C-B
4. Configuring the Si5350C
The Si5350C is a factory-programmed custom clock generator that is user definable with a simple to use webbased utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that
allows the user to enter input and output frequencies along with other custom features as described in the following
sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum
configuration. A unique part number is assigned to each custom configuration.
4.1. Crystal Inputs (XA, XB)
The Si5350C uses an optional fixed-frequency non-pullable standard AT-cut crystal as a reference to generate
free-running output clocks. Note that a XTAL is not required for generating synchronous clocks that are locked to
CLKIN.
4.1.1. Crystal Frequency
The Si5350C can operate using either a 25 MHz or a 27 MHz crystal.
4.1.2. Internal XTAL Load Capacitors
Internal load capacitors are provided to eliminate the need for external components when connecting a XTAL to the
Si5350C. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8 or 10 pF. XTALs with alternate
load capacitance requirements are supported using additional external load capacitance  2 pF (e.g., by using  4
pF capacitors on XA and XB) as shown in Figure 5.
XA
XB
Optional internal
load capacitance
0, 6, 8,10 pF
Optional additional
external load
capacitance
(< 2 pF)
Figure 5. External XTAL with Optional Load Capacitors
4.2. External Clock Input Pin (CLKIN)
The external clock input is used as a reference for generating synchronous clocks. The input frequency can be
specified from 10 to 100 MHz including fractional frequencies (e.g., 74.25 MHz x 1000/1001). The ClockBuilder
utility automatically determines the exact synthesis ratio to guarantee an output frequency with 0 ppm error with
respect to its reference.
4.3. Output Clocks (CLK0–CLK7)
The Si5350C is orderable as a 3-output (10-MSOP) or 8-output (20-QFN) clock generator. Output clocks CLK0 to
CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional frequency
select pins (FS0/1). See “4.4.3. Frequency Select (FS_0, FS_1)” for more details on the operation of the frequency
select pins. Each output clock can select its reference for either of the PLLs.
4.3.1. Output Clock Frequency
Outputs can be configured at any frequency from 2.5 kHz up to 200 MHz. However, only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKS4-7).
Rev. 1.0
11
Si5350C-B
4.3.2. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not
available on clocks synchronized to PLLB.
The Si5350C supports several levels of spread spectrum allowing the designer to choose an ideal compromise
between system performance and EMI compliance. If the CLKIN pin already has spread spectrum applied to it, it
will get passed through to the outputs that are referenced to it. In this case, do not configure the synchronous
outputs for spread spectrum as the device will erroneously try to add additional spread to them.
An optional spread spectrum enable pin (SSEN) is configurable to enable or disable the spread spectrum feature.
See “4.4.1. Spread Spectrum Enable (SSEN)” for details.
Reduced
Am plitude
and EM I
Center
Frequency
Am plitude
fc
fc
No Spread
Spectrum
D ow n Spread
Figure 6. Available Spread Spectrum Profiles
4.3.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
4.3.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350C as described in “4.4.4. Output Enable
(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as output high,
output low, or high-impedance.
4.3.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
4.4. Programmable Control Pins (P0–P3) Options
Up to four programmable control pins (P0-P3) are configurable allowing direct pin control of the following features:
4.4.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
4.4.2. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350C to minimize power consumption when its
output clocks are not being used. The Si5350C is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 3 on
page 4.
4.4.3. Frequency Select (FS_0, FS_1)
The Si5350C offers the option of configuring up to two frequencies per clock output (CLK0-CLK5) for either freerunning or synchronous clocks. This is a useful feature for applications that need to support more than one freerunning or synchronous clock rate on the same output. An example of this is shown in Figure 7. The FS pins select
which frequency is generated from the clock output. In this example, FS0 selects the output frequency on CLK0
12
Rev. 1.0
Si5350C-B
and FS1 selects the frequency on CLK1.
27 MHz
FS0
Bit Level
F1_0:
74.25 MHz
1
F2_0:
74.25
MHz
1.001
FS1
Bit Level
XA
Free-running Frequency
0
XB
FS0
FS1
Synchronous Frequency
0
F1_1:
24.576 MHz
1
F2_1:
22.5792 MHz
CLK0
Si5350C
Synchronous Clock
CLK1
54MHz
Free-running Clock
74.25
MHz
1.001
74.25 MHz or
24.576 MHz or 22.5792 MHz
Video/Audio
Processor
CLKIN
Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output
Up to two frequency select pins are available on the Si5350C. Each of the frequency select pins can be linked to
any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency
selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and
CLK4. Any other combination is also possible. The frequency select feature is not available for CLKs 6 and 7.
The Si5350C uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
Customizable FS Control
FS
FS
FS_0 Output Frequency
0
F1_0, F1_3, F1_5
1
F2_0, F2_3, F2_5
FS_0
FS
FS
FS
FS_1 Output Frequency
0
F1_1, F1_2, F1_4
1
F2_1, F2_2, F2_4
FS_1
FS
Glitchless Frequency Changes
MultiSynth 0
CLK0
MultiSynth 1
CLK1
MultiSynth 2
CLK2
MultiSynth 3
CLK3
MultiSynth 4
CLK4
MultiSynth 5
CLK5
New frequency starts
at its leading edge
Frequency_A
Frequency_B
Frequency_A
CLKx
Cannot be controlled
by FS pins
CLK6
Full cycle completes before
changing to a new frequency
CLK7
Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)
Rev. 1.0
13
Si5350C-B
4.4.4. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350C. Similar to the FS pins, each OEB pin
can be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0,
CLK3, and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4,
and CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the
pin forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
Customizable OEB Control
Glitchless Output Enable
CLK0
OEB_0
0
1
Output State
CLK Enabled
CLK Disabled
OEB
OEB_0
CLK1
OEB
Clock starts on the
first leading edge
CLK2
OEB
OEB_1
0
1
Output State
CLK Enabled
CLK Disabled
Clock continues until
cycle is complete
CLK3
OEB_1
CLKx
OEB
CLK4
OEBx
OEB
CLK5
OEB
OEB_2
0
1
Output State
CLK Enabled
CLK Disabled
CLK6
OEB_2
OEB
CLK7
OEB
Figure 9. Example Configuration of a Pin-Controlled Output Enable
4.4.5. Loss Of Lock (LOLB)
A loss of lock pin (LOLB) is available to indicate the status of the synchronous clock outputs. The LOLB pin is set to
a high state when the synchronous clock outputs are locked to the clock input (CLKIN). This is the normal
operating state for the synchronous clocks. The LOLB pin will go low when the reference clock at the CLKIN input
is removed or if its frequency deviates by more than 2000 ppm from its defined center frequency. In this case, the
synchronous clocks will continue to free-run. An option to disable the synchronous output clocks during an LOLB
condition (LOLB pin = low) is available. This only affects the clock outputs that were designated as synchronous
clock outputs. An external pull up resistor (recommended 10 kohms) is needed on LOLB as it is an open-drain
signal, not a push-pull output.
4.5. Design Considerations
The Si5350C is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance.
4.5.1. Power Supply Decoupling/Filtering
The Si5350C has built-in power supply filtering circuitry to help keep the number of external components to a
minimum. All that is recommended is one 0.1 to 1.0 µF decoupling capacitor per power supply pin. This capacitor
should be mounted as close to the VDD and VDDO pins as possible without using vias.
4.5.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
14
Rev. 1.0
Si5350C-B
4.5.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
4.5.4. External Crystal Load Capacitors
The Si5350C provides the option of using internal and external crystal load capacitors. If external load capacitors
are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for
more details.
4.5.5. Unused Pins
Unused control pins (P0–P3) should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "2.2. Applying a Reference Clock at XTAL Input" on page 8
when using XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left unconnected.
4.5.6. Trace Characteristics
The Si5350C features various output drive strength settings. It is recommended to configure the trace
characteristics as shown in Figure 10 when the default high output drive setting is used.
ZO = 50 ohms
R = 0 ohms
CLK
(Optional resistor for
EMI management)
Figure 10. Recommended Trace Characteristics with Default Drive Strength Setting
Rev. 1.0
15
Si5350C-B
5. Pin Descriptions
XA
1
XB
2
16 CLK6
17 CLK5
18 VDDOC
19 CLK4
20 VDD
5.1. 20-pin QFN
GND
PAD
15
CLK7
14
VDDOD
13
CLK0
VDDOA
VDDOB 10
11
9
5
CLK2
P2
8
CLK1
CLK3
12
7
4
P3
P1
6
3
CLKIN
P0
Figure 11. Si5350C 20-QFN Top View
Table 11. Si5350C 20-QFN Pin Descriptions
Pin Name
XA
XB
CLKIN
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
P0
P1
P2
P3
VDD
VDDOA
VDDOB
VDDOC
VDDOD
GND
Pin Number
1
2
6
13
12
9
8
19
17
16
15
3
4
5
7
20
11
10
18
14
Center Pad
Pin Type
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
P
P
P
P
P
P
Function
Input pin for external XTAL
Input pin for external XTAL
External reference clock input
Output clock 0
Output clock 1
Output clock 2
Output clock 3
Output clock 4
Output clock 5
Output clock 6
Output clock 7
User configurable pin 0. See 4.5.5
User configurable pin 1. See 4.5.5
User configurable pin 2. See 4.5.5
User configurable pin 3. See 4.5.5
Core voltage supply pin. See 4.5.2
Output voltage supply pin for CLK0 and CLK1. See 4.5.2
Output voltage supply pin for CLK2 and CLK3. See 4.5.2
Output voltage supply pin for CLK4 and CLK5. See 4.5.2
Output voltage supply pin for CLK6 and CLK7. See 4.5.2
Ground
Note: Pin Types: I = Input, O = Output, P = Power
16
Rev. 1.0
Si5350C-B
5.2. 10-pin MSOP
VDD
1
10
CLK0
XA
2
9
CLK1
XB
3
8
GND
P0
4
7
VDDO
CLKIN
5
6
CLK2
Figure 12. Si5350C 10-MSOP Top View
Table 12. Si5350C 10-MSOP Pin Descriptions
Pin Name Pin Number Pin Type
XA
2
I
XB
3
I
CLKIN
5
I
CLK0
10
O
CLK1
9
O
CLK2
6
O
P0
4
I
VDD
1
P
VDDO
7
P
GND
8
P
Function
Input pin for external XTAL
Input pin for external XTAL
External reference clock input
Output clock 0
Output clock 1
Output clock 2
User configurable pin 0. See 4.5.5
Core voltage supply pin. See 4.5.2
Output voltage supply pin for CLK0, CLK1, and CLK2. See 4.5.2
Ground
Note: Pin Types: I = Input, O = Output, P = Power
Rev. 1.0
17
Si5350C-B
6. Ordering Information
Factory-programmed Si5350C devices can be requested using the ClockBuilder web-based utility available at:
www.silabs.com/ClockBuilder. A unique part number is assigned to each custom configuration as indicated in
Figure 13.
Si5350 C
BXXXXX
XXX
Blank = Bulk
R = Tape and Reel
GT =10-MSOP
GM =20-QFN
B = Product Revision B
XXXXX = Unique Custom Code. A five character code will be
assigned for each unique custom configuration
Evaluation Boards
Si535x-B20QFN-EVB
For evaluation of
Si5350 C-Bxxxxx-GM (20 QFN)
Figure 13. Custom Clock Part Numbers
18
Rev. 1.0
Si5350C-B
7. Package Outline
Seating Plane
7.1. 20-Pin QFN
C
D2
B
D
A
D2/2
A1
L
E
E2
E2/2
b
A
e
Figure 14. 20-pin QFN Package Drawing
Rev. 1.0
19
Si5350C-B
Table 13. Package Dimensions
Dimension
A
Min
0.80
Nom
0.85
Max
0.90
A1
0.00
—
0.05
b
D
D2
e
E
E2
L
0.20
0.30
2.65
0.35
0.25
4.00 BSC
2.70
0.50 BSC
4.00 BSC
2.70
0.40
2.75
0.45
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
2.65
2.75
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
20
Rev. 1.0
Si5350C-B
7.2. 10-Pin MSOP
Figure 15. 10-pin MSOP Package Drawing
Table 14. 10-MSOP Package Dimensions
Dimension
Min
Nom
Max
A
—
—
1.10
A1
0.00
—
0.15
A2
0.75
0.85
0.95
b
0.17
—
0.33
c
0.08
—
0.23
D
3.00 BSC
E
4.90 BSC
E1
3.00 BSC
e
L
0.50 BSC
0.40
0.60
L2
0.80
0.25 BSC
q
0
—
8
aaa
—
—
0.20
bbb
—
—
0.25
ccc
—
—
0.10
ddd
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
21
Si5350C-B
8. Land Pattern: 20-Pin QFN
Figure 16 shows the recommended land pattern details for the Si5350 in a 20-Pin QFN package. Table 15 lists the
values for the dimensions shown in the illustration.
Figure 16. 20-Pin QFN Land Pattern
22
Rev. 1.0
Si5350C-B
Table 15. PCB Land Pattern Dimensions
Symbol
Millimeters
C1
4.0
C2
4.0
E
0.50 BSC
X1
0.30
X2
2.70
Y1
0.80
Y2
2.70
Notes:
General
1. All dimensions shown are in millimeters
(mm) unless otherwise noted.
2. This land pattern design is based on IPC7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask
defined (NSMD). Clearance between the
solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electropolished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm
(5 mils).
6. The ratio of stencil aperture to land pad size
should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on
1.30 mm pitch should be used for the center
ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is
recommended.
9. The recommended card reflow profile is per
the JEDEC/IPC J-STD-020 specification for
Small Body components.
Rev. 1.0
23
Si5350C-B
9. 10-pin MSOP Package Outline
Figure 17 illustrates the package details for the Si5350C-B in a 10-pin MSOP package. Table 16 lists the values for
the dimensions shown in the illustration.
Figure 17. 10-pin MSOP Package Drawing
24
Rev. 1.0
Si5350C-B
Table 16. 10-MSOP Package Dimensions
Dimension
A
A1
A2
b
c
D
E
E1
e
L
L2
q
aaa
bbb
ccc
ddd
Min
—
0.00
0.75
0.17
0.08
Nom
—
—
0.85
—
—
3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
0.25 BSC
—
—
—
—
—
0.40
0
—
—
—
—
Max
1.10
0.15
0.95
0.33
0.23
0.80
8
0.20
0.25
0.10
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
25
Si5350C-B
10. Land Pattern: 10-Pin MSOP
Figure 18 shows the recommended land pattern details for the Si5350C-B in a 10-Pin MSOP package. Table 17
lists the values for the dimensions shown in the illustration.
Figure 18. 10-Pin MSOP Land Pattern
26
Rev. 1.0
Si5350C-B
Table 17. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
Max
C1
4.40 REF
E
0.50 BSC
G1
3.00
—
X1
—
0.30
Y1
Z1
1.40 REF
—
5.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD020C specification for Small Body components.
Rev. 1.0
27
Si5350C-B
11. Top Marking
11.1. 20-Pin QFN Top Marking
Figure 19. 20-Pin QFN Top Marking
11.2. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Filled Circle = 0.50 mm Diameter
(Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
Si5350
Line 2 Mark Format:
TTTTTT = Mfg Code*
Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the assembly date.
*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used
for package assembly quality tracking purposes only.
28
Rev. 1.0
Si5350C-B
11.3. 10-Pin MSOP Top Marking
Figure 20. 10-Pin MSOP Top Marking
11.4. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Mold Dimple (Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
Si5350
Line 2 Mark Format:
TTTT = Mfg Code*
Line 2 from the “Markings” section of the Assembly
Purchase Order form.
Line 3 Mark Format:
YWW = Date Code
Assigned by the Assembly House.
Y = Last Digit of Current Year (Ex: 2013 = 3)
WW = Work Week of Assembly Date.
*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
package assembly quality tracking purposes only.
Rev. 1.0
29
Si5350C-B
DOCUMENT CHANGE LIST
Revision 0.75 to Revision 0.76

Updated Table 4 on page 5.
Updated
spread-spectrum frequency deviation
parameter test condition and minimum spec value.

Updated “6. Ordering Information” .
Updated
Figure 13, “Custom Clock Part Numbers,” on
page 18.
Revision 0.76 to Revision 1.0











30
Extended frequency range from 8 MHz-160 MHz to
2.5 kHz-200 MHz.
Added 1.8V VDD support.
Updated block diagrams for clarity.
Added complete Si5350/51 family table, Table 1.
Added top mark information.
Added landing pattern drawings.
Added PowerUp Time, PLL Bypass, Table 4.
Clarified Down Spread step sizes in Table 4.
Updated max jitter specs (typ unchanged) in Table 6.
Clarified power supply sequencing requirement,
Section 4.5.2.
Updated 4.4.5 Loss of Lock (LOLB) section.
Rev. 1.0
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
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Support and Community
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community.silabs.com
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device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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