User manual | Trannergy PVI4000TL G83/2 Certificate

G83/2
2
Engineerin
ng Reco
ommenda
ation
Type Approval
A
and
d manufactturer/supplie
er declaration of comp
pliance with
h the requirrements
of Engin
neering Reccommendattion G83/2.
SSEG Type
T
refere
ence numbe
er
P
PVI4000TL
SSEG Type
T
P
Photovoltaic
c Grid Tied Inverter
I
System
m Supplier name
T
Trannergy
Co.,
C Ltd.
Addresss
N 188 Weiiwu Rd, Sha
No.
anghai 2018
802, China
Tel
0086
6 021 38953
3908
Fax
F
0086 021
1 38953908
8
E:mail
[email protected]
Web
W site
www.tran
nnergy.com
m
3.65
5
Maximu
um rated
capacityy, use sepa
arate
sheet iff more than one
connection option.
Co
onnection Option
kW single ph
hase, single
e, split or three phase system
s
kW three phase
kW two phas
ses in three
e phase system
kW two phas
ses split pha
ase system
m
SSEG manufacture
m
er/supplier declaration.
I certifyy on behalf of the company name
ed above as
s a manufaccturer/supplier of Small Scale
Embedd
ded Genera
ators, that all products manufacttured/suppliied by the company with
w the
above SSEG
S
Type
e reference
e number will
w be manu
ufactured an
nd tested to
o ensure th
hat they
perform
m as stated in this Type
e Verificatio
on Test Rep
port, prior to
o shipment to site and that no
site mo
odifications are require
ed to ensure that the product meets
m
all the requirem
ments of
G83/2.
Signed
O behalf off
On
Trannerrgy Co., Ltd
d.
Note th
hat testing can be do
one by the manufactu
urer of an individual ccomponent,, by an
externa
al test house
e, or by the
e supplier of
o the complete system
m, or any co
ombination of
o them
as apprropriate.
Where parts of th
he testing are carried
d out by pe
ersons or organisation
o
ns other th
han the
supplier then the supplier
s
sha
all keep cop
pies of all te
est records and resultss supplied to
t them
to verifyy that the te
esting has been
b
carried
d out by peo
ople with su
ufficient tech
hnical comp
petency
to carryy out the tessts.
Power Quality. Harmonics. The requirement is specified in section 5.4.1, test procedure
in Annex A or B 1.4.1
SSEG rating per phase (rpp)
kW
NV=MV*3.68/rpp
3.65
Harmonic
At 45-55% of rated
output
Measured Normalised
Value
Value
(MV) in
(NV) in
Amps
Amps
100% of rated output
Measured
Value
(MV) in
Amps
Normalised
Value
(NV) in
Amps
Limit in Higher limit for
BS EN
odd harmonics
6100021 and above
3-2 in
Amps
2
0.053
0.053
0.066
0.066
1.080
3
0.076
0.076
0.064
0.064
2.300
4
0.021
0.021
0.007
0.007
0.430
5
0.139
0.140
0.077
0.078
1.140
6
0.007
0.007
0.007
0.007
0.300
7
0.141
0.142
0.029
0.029
0.770
8
0.007
0.007
0.012
0.012
0.230
9
0.069
0.069
0.059
0.060
0.400
10
0.006
0.006
0.010
0.010
0.184
11
0.039
0.039
0.087
0.088
0.330
12
0.008
0.008
0.022
0.022
0.153
13
0.057
0.057
0.044
0.044
0.210
14
0.007
0.007
0.023
0.023
0.131
15
0.100
0.101
0.038
0.038
0.150
16
0.007
0.007
0.015
0.016
0.115
17
0.126
0.127
0.044
0.044
0.132
18
0.010
0.010
0.008
0.008
0.102
19
0.115
0.115
0.074
0.075
0.118
20
0.015
0.015
0.014
0.014
0.092
21
0.102
0.103
0.103
0.104
0.107
0.160
22
0.015
0.015
0.013
0.013
0.084
23
0.081
0.082
0.018
0.018
0.098
0.147
24
0.010
0.010
0.010
0.011
0.077
25
0.024
0.024
0.036
0.036
0.090
0.135
26
0.013
0.013
0.019
0.020
0.071
27
0.024
0.024
0.050
0.051
0.083
0.124
28
0.011
0.011
0.016
0.016
0.066
29
0.020
0.020
0.042
0.043
0.078
0.117
30
0.007
0.007
0.023
0.023
0.061
31
0.019
0.019
0.023
0.024
0.073
0.109
32
0.008
0.008
0.004
0.004
0.058
33
0.018
0.018
0.011
0.011
0.068
0.102
34
0.006
0.006
0.010
0.010
0.054
35
0.020
0.020
0.034
0.035
0.064
0.096
36
0.008
0.008
0.006
0.006
0.051
37
0.025
0.026
0.023
0.023
0.061
0.091
38
0.006
0.006
0.005
0.006
0.048
39
0.035
0.035
0.033
0.033
0.058
0.087
40
0.010
0.010
0.005
0.005
0.046
Note the higher limits for odd harmonics 21 and above are only allowable under certain
conditions, if these higher limits are utilised please state the exemption used as detailed in
part 6.2.3.4 of BS EN 61000-3-2 in the box below.
Power Quality. Voltage fluctuations and Flicker. The requirement is specified in section
5.4.2, test procedure in Annex A or B 1.4.3
Starting
Stopping
Running
dmax
dc
dmax
dc
Pst
Plt 2 hours
d(t)
d(t)
Measured
0.38
Values
Normalised
0.38
to standard
impedance
and 3.68kW
for multiple
units
Limits
set 4%
under BS EN
61000-3-2
0.28
0.32
1.65
0.28
0.32
0.225
0.185
0.28
0.32
1.65
0.28
0.32
0.225
0.185
3.3%
3.3%
4%
3.3%
3.3%
1.0
0.65
500ms
500ms
Test start date
2014.02.20
Test end date
2014.02.20
Test location
Floor 2, Building 2, No. 188, weiwu Road, jiading District,
Shanghai
Power quality. DC injection. The requirement is specified in section 5.5, test procedure in
Annex A or B 1.4.4
Test power 10%
55%
100%
level
Recorded
5.5mA
7.6mA
9.8mA
value
as % of 0.03%
0.05%
0.06%
rated AC
current
Limit
0.25%
0.25%
0.25%
Power Quality. Power factor. The requirement is specified in section 5.6, test procedure
in Annex A or B 1.4.2
216.2V
230V
253V
Measured at three voltage levels and at
full output. Voltage to be maintained
within ±1.5% of the stated level during
Measured
0.995
0.997
0.996
the test.
value
Limit
>0.95
>0.95
>0.95
Protection. Frequency tests The
in Annex A or B 1.3.3
Function
Setting
Frequency Time
delay
U/F stage 1 47.5Hz
20s
requirement is specified in section 5.3.1, test procedure
Trip test
Frequency
47.49 Hz
Time
delay
18S
“No trip tests”
Frequency
Confirm no trip
/time
47.7Hz
No trip
25s
U/F stage 2
47Hz
0.5s
46.99 Hz
0.4S
O/F stage 1 51.5Hz
90s
51.51 Hz
88S
O/F stage 2 52Hz
0.5s
52.01 Hz
0.4S
47.2Hz
19.98s
46.8Hz
0.48s
51.3Hz
95s
51.8Hz
89.98s
52.2Hz
0.48s
No trip
No trip
No trip
No trip
No trip
Protection. Voltage tests The requirement is specified in section 5.3.1, test procedure in
Annex A or B 1.3.2
Function
Setting
Trip test
“No trip tests”
Voltage
Time
Voltage
Time
Voltage
Confirm no trip
delay
delay
/time
U/V stage 1
200.1V
2.5s
200.1V
2.4S
204.1V
No trip
3.5s
U/V stage 2
184V
0.5s
184.0V
0.4S
188V
No trip
2.48s
180V
No trip
0.48s
O/V stage 1
262.2V
1.0s
262.2V
0.9S
258.2V
No trip
2.0s
O/V stage 2
273.7V
0.5s
273.7V
0.4S
269.7V
No trip
0.98s
277.7V
No trip
0.48s
Note for Voltage tests the Voltage required to trip is the setting ±3.45V. The time delay can
be measured at a larger deviation than the minimum required to operate the protection. The
No trip tests need to be carried out at the setting ±4V and for the relevant times as shown in
the table above to ensure that the protection will not trip in error.
Protection. Loss of Mains test. The requirement is specified in section 5.3.2, test
procedure in Annex A or B 1.3.4
To be carried out at three output power levels with a tolerance of plus or minus 5% in Test
Power levels.
Test Power
10%
55%
100%
10%
55%
100%
Balancing load
on islanded
network
95%
SSEG
output
Trip time. Limit is 0.380S
0.5 seconds
of 95%
SSEG
output
0.365S
of 95% of 105% of 105% of 105%
SSEG
SSEG
SSEG
SSEG
output
output
output
output
0.420S
0.395S
0.340S
of
0.405S
Protection. Frequency change, Stability test The requirement is specified in section
5.3.3, test procedure in Annex A or B 1.3.6
Start
Change
End
Confirm no trip
Frequency
Frequency
Positive Vector Shift
49.5Hz
+9 degrees
No trip
Negative Vector Shift
50.5Hz
- 9 degrees
No trip
Positive Frequency drift
49.5Hz
+0.19Hz/sec
51.5Hz
No trip
Negative Frequency drift
50.5Hz
-0.19Hz/sec
47.5Hz
No trip
Protection. Re-connection timer. The requirement is specified in section 5.3.4, test
procedure in Annex A or B 1.3.5
Test should prove that the reconnection sequence starts after a minimum delay of 20
seconds for restoration of voltage and frequency to within the stage 1 settings of table 1.
Time delay Measured
Checks on no reconnection when voltage or frequency
setting
delay
is brought to just outside stage 1 limits of table 1.
At 266.2V At 196.1V At 47.4Hz At 51.6Hz
30
32
Confirmation that the SSEG does NoNoNoNo-reconnect
not re-connect.
reconnect reconnect reconnect
Fault level contribution. The requirement is specified in section 5.7, test procedure in
Annex A or B 1.4.6
For a directly coupled SSEG
For a Inverter SSEG
Parameter
Symbol
Peak Short Circuit current
ip
-
Time
after fault
20ms
Initial Value of aperiodic
current
Initial symmetrical shortcircuit current*
Decaying
(aperiodic)
component of short circuit
current*
Reactance/Resistance
Ratio of source*
A
-
100ms
32.8
0.38
Ik
-
250ms
32.5
0.25
iDC
-
500ms
31.6
0.16
Time to
trip
0.085S
In seconds
X
/R
Value
Volts
Amps
33.5
0.56

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