Renesas µPD789046 Subseries µPD789046, µPD78F9046 8-Bit Single-Chip Microcontroller User's Manual
Below you will find brief information for µPD789046 Subseries µPD789046, µPD789046 Subseries µPD78F9046. This document provides information on the pin functions, CPU architecture, internal block functions, instruction set, and other internal peripheral functions of the µPD789046 Subseries. The µPD789046 Subseries is a family of 8-bit single-chip microcontrollers designed for use in a wide range of applications. These devices feature hardware and software features that simplify the design and development of embedded systems. They offer a powerful CPU core, a variety of peripherals, and a range of memory options.
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On April 1
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, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics document. We appreciate your understanding.
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st
, 2010
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Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
User’s Manual
µµµµ
PD789046 Subseries
8-Bit Single-Chip Microcontrollers
µµµµ
PD789046
µµµµ
PD78F9046
Document No. U13600EJ2V0UMJ1 (2nd edition)
Date Published October 2000 N CP(K)
©
Printed in Japan
1998, 1999
[MEMO]
2
User's Manual U13600EJ2V0UM00
SUMMARY OF CONTENTS
CHAPTER 1 GENERAL ....................................................................................................................................23
CHAPTER 2 PIN FUNCTIONS..........................................................................................................................29
CHAPTER 3 CPU ARCHITECTURE.................................................................................................................37
CHAPTER 4 PORT FUNCTIONS......................................................................................................................59
CHAPTER 5 CLOCK GENERATION CIRCUIT ................................................................................................75
CHAPTER 6 16-BIT TIMER ..............................................................................................................................85
CHAPTER 7 8-BIT TIMER/EVENT COUNTER...............................................................................................101
CHAPTER 8 WATCH TIMER ..........................................................................................................................113
CHAPTER 9 WATCHDOG TIMER ..................................................................................................................119
CHAPTER 10 SERIAL INTERFACE 20 ............................................................................................................125
CHAPTER 11 INTERRUPT FUNCTIONS .........................................................................................................159
CHAPTER 12 STANDBY FUNCTION...............................................................................................................175
CHAPTER 13 RESET FUNCTION ....................................................................................................................183
CHAPTER 14
µµµµ
PD78F9046 ..............................................................................................................................187
CHAPTER 15 INSTRUCTION SET ...................................................................................................................193
APPENDIX A DEVELOPMENT TOOLS ...........................................................................................................203
APPENDIX B EMBEDDED SOFTWARE..........................................................................................................211
APPENDIX C REGISTER INDEX .....................................................................................................................213
APPENDIX D REVISION HISTORY ..................................................................................................................217
User's Manual U13600EJ2V0UM00
3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM is a trademark of NEC Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun-Microsystems, Inc.
OSF/Motif is a trademark of Open Software Foundation, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
4
User's Manual U13600EJ2V0UM00
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed:
µ
PD78F9046
The customer must judge the need for license:
µ
PD789046
•
•
•
•
•
•
The information in this document is current as of October, 1999. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
User's Manual U13600EJ2V0UM00
5
6
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
User's Manual U13600EJ2V0UM00
Major Revision in This Edition p.102
p.105
p.107
p.108
p.110
p.188
Page
Throughout p.34
p.86
p.92
p.98
p.190
p.191
p.206
p.210
p.211
Description
Completion of development of
µ
PD789046 and
µ
PD78F9046
Change of recommended connection of unused pins in Table 2-1
Correction of Figure 6-1
Addition of cautions on rewriting CR90 to Section 6.4.1
Addition of cautions on 16-bit timer to Section 6.5
Addition of cautions on rewriting CR80 to Section 7.2 (1)
Addition of description of operation to Section 7.4.1
Addition of description of operation to Section 7.4.2
Addition of description of operation to Section 7.4.3
Addition of description of operation to Section 7.4.4
Correction of pins used in pseudo 3-wire mode in Table 14-2
Change of connection of P01 and P02 pins in Figure 14-4
Addition of setting example to Section 14.1.4
Correction of product name of flash memory writing adapter in Section A.2
Addition of NP-44GB-TQ as emulation probe to Section A.3.1
Addition of package drawing to Section A.5
Addition of part number of MX78K0S to Appendix B
The mark shows the major revised points.
User's Manual U13600EJ2V0UM00
7
[MEMO]
8
User's Manual U13600EJ2V0UM00
INTRODUCTION
Readers
Purpose
Organization
This manual is intended for user engineers who understand the functions of the
µ
PD789046 Subseries to design and develop its application systems and programs.
Target products:
• µ
PD789046 Subseries:
µ
PD789046 and
µ
PD78F9046
This manual is intended for users to understand the functions described in the
Organization below.
Two manuals are available for the
µ
PD789046 Subseries: this manual and
Instruction Manual (common to the 78K/0S Series).
µ
PD789046 Subseries
User's Manual
•
•
•
Pin functions
Internal block functions
Interrupt
•
Other internal peripheral functions
78K/0S Series
User's Manual
Instruction
•
CPU function
•
Instruction set
•
Instruction description
How to Read This Manual It is assumed that the readers of this manual have general knowledge on electric engineering, logic circuits, and microcontrollers.
◊
To understand the overall functions of the
µ
PD789046 Subseries
→
Read this manual in the order of the TABLE OF CONTENTS.
◊
How to read register formats
→ The name of a bit whose number is enclosed with <> is reserved for the assembler and is defined for the C compiler by the header file sfrbit.h.
◊
To learn the detailed functions of a register whose register name is known
→
See Appendix C.
◊
To learn the details of the instruction functions of the 78K/0S Series
→
Refer to 78K/0S Series User's Manual
Instruction (U11047E) separately available.
Legend Data significance
Active low
: Left: higher digit, right: lower digit
:
×××
(top bar over pin or signal name)
: Footnote Note
Caution : Important information
Remark : Supplement
Numerical representation : Binary ...
××××
or
××××
B
Decimal ...
××××
Hexadecimal ...
××××
H
User's Manual U13600EJ2V0UM00
9
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
µ
PD789046 Data Sheet
µ
PD78F9046 Preliminary Product Information
µ
PD789046 Subseries User's Manual
78K/0S Series User's Manual
Instruction
Document No.
English Japanese
U13380E
U13546E
This manual
U11047E
U13380J
U13546J
U13600J
U11047J
Documents Related to Development Tools (User's Manual)
Document Name Document No.
English Japanese
RA78K0S Assembler Package Operation
Assembly Language
U11622E
U11599E
Structured Assembly Language U11623E
CC78K0S C Compiler Operation
Language
Reference SM78K0S System Simulator Windows
TM
Based
SM78K Series System Simulator External Parts User Open
Interface Specifications
ID78K0S-NS Integrated Debugger Windows Based Reference
U11816E
U11817E
U11489E
U10092E
U12901E
U11622J
U11599J
U11623J
U11816J
U11817J
U11489J
U10092J
U12901J
Documents for Embedded Software (User's Manual)
Document Name Document No.
English Japanese
U12938E U12938J 78K/0S Series OS MX78K0S Basics
Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc.
10
User's Manual U13600EJ2V0UM00
Other Related Documents
Document Name Document No.
English Japanese
SEMICONDUCTORS SELECTION GUIDE Products & Package
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Device
X13769X
C10535E
C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Semiconductor Device Quality Control/Reliability Handbook
Guide for Products Related to Micro-Computer: Other Companies
−
−
C10535J
C11531J
C10983J
C11892J
C12769J
U11416J
Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc.
User's Manual U13600EJ2V0UM00
11
[MEMO]
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User's Manual U13600EJ2V0UM00
TABLE OF CONTENTS
CHAPTER 1 GENERAL.............................................................................................................................23
1.1 Features ......................................................................................................................................23
1.2 Applications................................................................................................................................23
1.3 Ordering Information .................................................................................................................23
1.4 Pin Configuration (Top View)....................................................................................................24
1.5 78K/0S Series Development ......................................................................................................25
1.6 Block Diagram ............................................................................................................................27
1.7 Functions ....................................................................................................................................28
CHAPTER 2 PIN FUNCTIONS ..................................................................................................................29
2.1 Pin Function List ........................................................................................................................29
2.2 Description of Pin Functions ....................................................................................................31
2.2.1 P00 to P07 (Port 0)......................................................................................................................31
2.2.2 P10 to P17 (Port 1)......................................................................................................................31
2.2.3 P20 to P27 (Port 2)......................................................................................................................31
2.2.4 P30, P31 (Port 3).........................................................................................................................32
2.2.5 P40 to P47 (Port 4)......................................................................................................................32
2.2.6 RESET.........................................................................................................................................33
2.2.7 X1, X2..........................................................................................................................................33
2.2.8 XT1, XT2 .....................................................................................................................................33
2.2.9
DD0
, V
DD1
....................................................................................................................................33
2.2.10
SS0
, V
SS1
.....................................................................................................................................33
2.2.11
PP
(
µ
PD78F9046 only)...............................................................................................................33
2.2.12 IC0 (masked ROM version only) .................................................................................................33
2.3 Pin Input/Output Circuits and Handling of Unused Pins .......................................................34
CHAPTER 3 CPU ARCHITECTURE .........................................................................................................37
3.1 Memory Space ............................................................................................................................37
3.1.1 Internal program memory space..................................................................................................39
3.1.2 Internal data memory (internal high-speed RAM) space .............................................................39
3.1.3 Special function register (SFR) area ...........................................................................................39
3.1.4 Data memory addressing ............................................................................................................40
3.2 Processor Registers ..................................................................................................................42
3.2.1 Control registers ..........................................................................................................................42
3.2.2 General-purpose registers...........................................................................................................45
3.2.3 Special function register (SFR)....................................................................................................46
3.3 Instruction Address Addressing ..............................................................................................49
3.3.1 Relative addressing .....................................................................................................................49
3.3.2 Immediate addressing .................................................................................................................50
User's Manual U13600EJ2V0UM00
13
3.3.3 Table indirect addressing ............................................................................................................51
3.3.4 Register addressing ....................................................................................................................51
3.4 Operand Address Addressing .................................................................................................. 52
3.4.1 Direct addressing ........................................................................................................................52
3.4.2 Short direct addressing ...............................................................................................................53
3.4.3 Special function register (SFR) addressing .................................................................................54
3.4.4 Register addressing ....................................................................................................................55
3.4.5 Register indirect addressing........................................................................................................56
3.4.6 Based addressing........................................................................................................................57
3.4.7 Stack addressing.........................................................................................................................57
CHAPTER 4 PORT FUNCTIONS .............................................................................................................. 59
4.1 Port Functions............................................................................................................................ 59
4.2 Port Configuration ..................................................................................................................... 61
4.2.1 Port 0 ...........................................................................................................................................61
4.2.2 Port 1 ...........................................................................................................................................62
4.2.3 Port 2 ...........................................................................................................................................63
4.2.4 Port 3 ...........................................................................................................................................68
4.2.5 Port 4 ...........................................................................................................................................69
4.3 Port Function Control Registers .............................................................................................. 70
4.4 Operation of Port Functions ..................................................................................................... 73
4.4.1 Writing to I/O port ........................................................................................................................73
4.4.2 Reading from I/O port ..................................................................................................................73
4.4.3 Arithmetic operation of I/O port....................................................................................................73
CHAPTER 5 CLOCK GENERATION CIRCUIT......................................................................................... 75
5.1 Clock Generation Circuit Functions......................................................................................... 75
5.2 Clock Generation Circuit Configuration .................................................................................. 75
5.3 Registers Controlling Clock Generation Circuit ..................................................................... 77
5.4 System Clock Oscillators .......................................................................................................... 79
5.4.1 Main system clock oscillator........................................................................................................79
5.4.2 Subsystem clock oscillator ..........................................................................................................79
5.4.3 Scaler ..........................................................................................................................................81
5.4.4 When no subsystem clocks are used..........................................................................................81
5.5 Clock Generation Circuit Operation ......................................................................................... 82
5.6 Changing Setting of System Clock and CPU Clock ............................................................... 83
5.6.1 Time required for switching between system clock and CPU clock ............................................83
5.6.2 Switching between system clock and CPU clock ........................................................................84
CHAPTER 6 16-BIT TIMER ....................................................................................................................... 85
6.1 16-Bit Timer Functions .............................................................................................................. 85
6.2 16-Bit Timer Configuration........................................................................................................ 85
6.3 Registers Controlling 16-Bit Timer........................................................................................... 88
6.4 16-Bit Timer Operation .............................................................................................................. 92
14
User's Manual U13600EJ2V0UM00
6.4.1 Operation as timer interrupt.........................................................................................................92
6.4.2 Operation as timer output ............................................................................................................94
6.4.3 Capture operation........................................................................................................................95
6.4.4 16-bit timer counter 90 readout ...................................................................................................96
6.4.5 Buzzer output operation ..............................................................................................................97
6.5 Notes on 16-Bit Timer ................................................................................................................98
CHAPTER 7 8-BIT TIMER/EVENT COUNTER .......................................................................................101
7.1 Functions of 8-Bit Timer/Event Counter ................................................................................101
7.2 8-Bit Timer/Event Counter Configuration ..............................................................................102
7.3 8-Bit Timer/Event Counter Control Registers........................................................................103
7.4 Operation of 8-Bit Timer/Event Counter ................................................................................105
7.4.1 Operation as interval timer ........................................................................................................105
7.4.2 Operation as external event counter .........................................................................................107
7.4.3 Operation as square wave output..............................................................................................108
7.4.4 PWM output operation...............................................................................................................110
7.5 Notes on Using 8-Bit Timer/Event Counter ...........................................................................111
CHAPTER 8 WATCH TIMER...................................................................................................................113
8.1 Watch Timer Functions ...........................................................................................................113
8.2 Watch Timer Configuration .....................................................................................................114
8.3 Watch Timer Control Register ................................................................................................115
8.4 Watch Timer Operation............................................................................................................116
8.4.1 Operation as watch timer...........................................................................................................116
8.4.2 Operation as interval timer ........................................................................................................116
CHAPTER 9 WATCHDOG TIMER...........................................................................................................119
9.1 Watchdog Timer Functions.....................................................................................................119
9.2 Watchdog Timer Configuration .............................................................................................. 120
9.3 Watchdog Timer Control Registers........................................................................................121
9.4 Watchdog Timer Operation .....................................................................................................123
9.4.1 Operation as watchdog timer.....................................................................................................123
9.4.2 Operation as interval timer ........................................................................................................124
CHAPTER 10 SERIAL INTERFACE 20...................................................................................................125
10.1 Serial Interface 20 Functions ..................................................................................................125
10.2 Serial Interface 20 Configuration ............................................................................................125
10.3 Serial Interface 20 Control Registers .....................................................................................129
10.4 Serial Interface 20 Operation...................................................................................................136
10.4.1 Operation stop mode .................................................................................................................136
10.4.2 Asynchronous serial interface (UART) mode ............................................................................137
10.4.3 3-wire serial I/O mode ...............................................................................................................149
CHAPTER 11 INTERRUPT FUNCTIONS................................................................................................ 159
User's Manual U13600EJ2V0UM00
15
11.1 Interrupt Function Types......................................................................................................... 159
11.2 Interrupt Sources and Configuration ..................................................................................... 159
11.3 Interrupt Function Control Registers.....................................................................................162
11.4 Interrupt Processing Operation .............................................................................................. 168
11.4.1 Non-maskable interrupt request acceptance operation.............................................................168
11.4.2 Maskable interrupt request acceptance operation ....................................................................170
11.4.3 Multiplexed interrupt processing................................................................................................172
11.4.4 Interrupt request reserve ...........................................................................................................174
CHAPTER 12 STANDBY FUNCTION ..................................................................................................... 175
12.1 Standby Function and Configuration..................................................................................... 175
12.1.1 Standby function........................................................................................................................175
12.1.2 Standby function control register...............................................................................................176
12.2 Operation of Standby Function .............................................................................................. 177
12.2.1 HALT mode ...............................................................................................................................177
12.2.2 STOP mode...............................................................................................................................180
CHAPTER 13 RESET FUNCTION........................................................................................................... 183
CHAPTER 14
µµµµ
PD78F9046 ..................................................................................................................... 187
14.1 Flash Memory Programming................................................................................................... 188
14.1.1 Selecting communication mode.................................................................................................188
14.1.2 Function of flash memory programming ....................................................................................189
14.1.3 Flashpro III connection ..............................................................................................................189
14.1.4 Setting Example with Flashpro III (PG-FP3)..............................................................................191
CHAPTER 15 INSTRUCTION SET.......................................................................................................... 193
15.1 Operation .................................................................................................................................. 193
15.1.1 Operand identifiers and description methods ............................................................................193
15.1.2 Description of "Operation" column.............................................................................................194
15.1.3 Description of "Flag" column .....................................................................................................194
15.2 Operation List........................................................................................................................... 195
15.3 Instructions Listed by Addressing Type ............................................................................... 200
APPENDIX A DEVELOPMENT TOOLS.................................................................................................. 203
A.1 Language Processing Software.............................................................................................. 205
A.2 Flash Memory Writing Tools ................................................................................................... 206
A.3 Debugging Tools...................................................................................................................... 206
A.3.1 Hardware ...................................................................................................................................206
A.3.2 Software ....................................................................................................................................207
A.4 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint....................... 208
A.5 Conversion Adapter (TGB-044SAP) Drawing........................................................................ 210
16
User's Manual U13600EJ2V0UM00
APPENDIX B EMBEDDED SOFTWARE.................................................................................................211
APPENDIX C REGISTER INDEX ............................................................................................................213
C.1 Register Name Index (Alphabetic Order) ...............................................................................213
C.2 Register Symbol Index (Alphabetic Order)............................................................................215
APPENDIX D REVISION HISTORY.........................................................................................................217
User's Manual U13600EJ2V0UM00
17
LIST OF FIGURES (1/3)
Figure No.
Title Page
2-1 Pin Input/Output Circuits ............................................................................................................................35
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Memory Map (
µ
PD789046)........................................................................................................................37
Memory Map (
µ
PD78F9046)......................................................................................................................38
Data Memory Addressing Modes (
µ
PD789046) ........................................................................................40
Data Memory Addressing Modes (
µ
PD78F9046) ......................................................................................41
Program Counter Configuration .................................................................................................................42
Program Status Word Configuration ..........................................................................................................42
Stack Pointer Configuration .......................................................................................................................44
Data to be Saved to Stack Memory ...........................................................................................................44
3-9 Data to be Restored from Stack Memory ...................................................................................................44
3-10 General-Purpose Register Configuration ...................................................................................................45
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
Port Types..................................................................................................................................................59
Block Diagram of P00 to P07 .....................................................................................................................61
Block Diagram of P10 to P17 .....................................................................................................................62
Block Diagram of P20 ................................................................................................................................63
Block Diagram of P21 ................................................................................................................................64
Block Diagram of P22 and P24 to P26.......................................................................................................65
Block Diagram of P23 ................................................................................................................................66
Block Diagram of P27 ................................................................................................................................67
4-9 Block Diagram of P30 and P31 ..................................................................................................................68
4-10 Block Diagram of P40 to P47 .....................................................................................................................69
4-11 Format of Port Mode Register....................................................................................................................71
4-12 Format of Pull-Up Resistor Option Register 0............................................................................................71
4-13 Format of Pull-Up Resistor Option Register B2 .........................................................................................72
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Block Diagram of Clock Generation Circuit................................................................................................76
Format of Processor Clock Control Register..............................................................................................77
Format of Suboscillation Mode Register ....................................................................................................78
Format of Subclock Control Register .........................................................................................................78
External Circuit of Main System Clock Oscillator .......................................................................................79
External Circuit of Subsystem Clock Oscillator ..........................................................................................79
Unacceptable Resonator Connections ......................................................................................................80
Switching between System Clock and CPU Clock.....................................................................................84
6-1
6-2
6-3
6-4
6-5
6-6
Block Diagram of 16-Bit Timer ...................................................................................................................86
Format of 16-Bit Timer Mode Control Register 90 .....................................................................................89
Format of Buzzer Output Control Register 90............................................................................................90
Format of Port Mode Register 3.................................................................................................................91
Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation .....................................92
Timing of Timer Interrupt Operation ...........................................................................................................93
18
User's Manual U13600EJ2V0UM00
LIST OF FIGURES (2/3)
Figure No.
Title Page
6-7
6-8
Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation ....................................... 94
Timer Output Timing ................................................................................................................................. 94
6-9 Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation ............................................... 95
6-10 Capture Operation Timing (Both Edges of CPT90 Pin Are Specified) ...................................................... 95
6-11 16-Bit Timer Counter 90 Readout Timing.................................................................................................. 96
6-12 Settings of Buzzer Output Control Register 90 for Buzzer Output Operation ........................................... 97
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
Block Diagram of 8-Bit Timer/Event Counter .......................................................................................... 102
Format of 8-Bit Timer Mode Control Register 80 .................................................................................... 103
Format of Port Mode Register 2 .............................................................................................................. 104
Interval Timer Operation Timing.............................................................................................................. 106
External Event Counter Operation Timing (with Rising Edge Specified)................................................. 107
Square Wave Output Timing ................................................................................................................... 109
PWM Output Timing ................................................................................................................................ 110
Start Timing of 8-Bit Timer Counter 80.................................................................................................... 111
External Event Counter Operation Timing .............................................................................................. 111
8-1
8-2
8-3
Block Diagram of Watch Timer ............................................................................................................... 113
Format of Watch Timer Mode Control Register....................................................................................... 115
Watch Timer/Interval Timer Operation Timing ........................................................................................ 117
9-1
9-2
9-3
Block Diagram of Watchdog Timer ......................................................................................................... 120
Format of Timer Clock Selection Register 2 ........................................................................................... 121
Format of Watchdog Timer Mode Register ............................................................................................. 122
10-1
10-2
Block Diagram of Serial Interface 20....................................................................................................... 126
Block Diagram of Baud Rate Generator 20............................................................................................. 127
10-3 Format of Serial Operation Mode Register 20......................................................................................... 129
10-4 Format of Asynchronous Serial Interface Mode Register 20 .................................................................. 130
10-5 Format of Asynchronous Serial Interface Status Register 20 ................................................................. 132
10-6 Format of Baud Rate Generator Control Register 20.............................................................................. 133
10-7 Asynchronous Serial Interface Transmit/Receive Data Format .............................................................. 143
10-8 Asynchronous Serial Interface Transmission Completion Interrupt Timing ............................................ 145
10-9 Asynchronous Serial Interface Reception Completion Interrupt Timing.................................................. 146
10-10 Receive Error Timing .............................................................................................................................. 147
10-11 3-Wire Serial I/O Mode Timing ................................................................................................................ 152
11-1 Basic Configuration of Interrupt Function................................................................................................ 161
11-2 Format of Interrupt Request Flag Register.............................................................................................. 163
11-3 Format of Interrupt Mask Flag Register .................................................................................................. 164
11-4 Format of External Interrupt Mode Register 0 ......................................................................................... 165
11-5 Program Status Word Configuration ....................................................................................................... 166
User's Manual U13600EJ2V0UM00
19
LIST OF FIGURES (3/3)
Figure No.
Title Page
11-6 Format of Key Return Mode Register 00 .................................................................................................167
11-7 Block Diagram of Falling Edge Detection Circuit .....................................................................................167
11-8 Flowchart from Non-Maskable Interrupt Request Generation to Acceptance ..........................................169
11-9 Timing of Non-Maskable Interrupt Request Acceptance..........................................................................169
11-10 Accepting Non-Maskable Interrupt Request ............................................................................................169
11-11 Interrupt Request Acceptance Processing Algorithm...............................................................................171
11-12 Interrupt Request Acceptance Timing (Example of MOV A,r)..................................................................172
11-13 Interrupt Request Acceptance Timing
(When Interrupt Request Flag Is Set at the Last Clock During Instruction Execution).............................172
11-14 Example of Multiple Interrupt ...................................................................................................................173
12-1 Format of Oscillation Settling Time Selection Register ............................................................................176
12-2 Releasing HALT Mode by Interrupt..........................................................................................................178
12-3 Releasing HALT Mode by RESET Input ..................................................................................................179
12-4 Releasing STOP Mode by Interrupt .........................................................................................................181
12-5 Releasing STOP Mode by RESET Input..................................................................................................181
13-1 Block Diagram of Reset Function.............................................................................................................183
13-2 Reset Timing by RESET Input .................................................................................................................184
13-3 Reset Timing by Overflow in Watchdog Timer.........................................................................................184
13-4 Reset Timing by RESET Input in STOP Mode.........................................................................................184
14-1 Format of Communication Mode Selection ..............................................................................................188
14-2 Flashpro III Connection Example in 3-Wire Serial I/O Mode....................................................................189
14-3 Flashpro III Connection Example in UART Mode ....................................................................................190
14-4 Flashpro III Connection Example in Pseudo 3-Wire Mode (When P0 Is Used) .......................................190
A-1
A-2
A-3
A-4
Development Tools ..................................................................................................................................204
EV-9200G-44 Package Drawing (Reference) (unit: mm) ........................................................................208
EV-9200G-44 Footprints (Reference) (unit: mm) ....................................................................................209
TGB-044SAP Package Drawing (Reference) (unit: mm) ........................................................................210
20
User's Manual U13600EJ2V0UM00
LIST OF TABLES (1/2)
Table No.
Title Page
2-1 Type of Input/Output Circuit for Each Pin and Handling of Unused Pins .................................................. 34
3-1
3-2
3-3
Internal ROM Capacity .............................................................................................................................. 39
Vector Table.............................................................................................................................................. 39
Special Function Registers ....................................................................................................................... 47
4-1
4-2
4-3
Port Functions ........................................................................................................................................... 60
Configuration of Port ................................................................................................................................. 61
Port Mode Register and Output Latch Settings for Using Alternate Functions ......................................... 70
5-1
5-2
Configuration of Clock Generation Circuit................................................................................................. 75
Maximum Time Required for Switching CPU Clock .................................................................................. 83
6-1
6-2
6-3
6-4
6-5
Configuration of 16-Bit Timer .................................................................................................................... 85
Interval Time of 16-Bit Timer ..................................................................................................................... 92
Settings of Capture Edge .......................................................................................................................... 95
Buzzer Frequency of 16-Bit Timer ............................................................................................................ 97
Operating Status of 16-Bit Timer under Each Condition ........................................................................... 98
7-1
7-2
7-3
7-4
7-5
Interval Time of 8-Bit Timer/Event Counter ............................................................................................. 101
Square Wave Output Range of 8-Bit Timer/Event Counter..................................................................... 101
8-Bit Timer/Event Counter Configuration ................................................................................................ 102
Interval Time of 8-Bit Timer/Event Counter ............................................................................................. 105
Square Wave Output Range of 8-Bit Timer/Event Counter..................................................................... 108
8-1
8-2
8-3
Interval Generated Using Interval Timer ................................................................................................. 114
Watch Timer Configuration ..................................................................................................................... 114
Interval Generated Using Interval Timer ................................................................................................. 116
9-1
9-2
9-3
9-4
9-5
Inadvertent Loop Detection Time of Watchdog Timer............................................................................. 119
Interval Time ........................................................................................................................................... 119
Configuration of Watchdog Timer ........................................................................................................... 120
Inadvertent Loop Detection Time of Watchdog Timer............................................................................. 123
Interval Generated Using Interval Timer ................................................................................................. 124
10-1 Configuration of Serial Interface 20......................................................................................................... 125
10-2 Serial Interface 20 Operating Mode Settings .......................................................................................... 131
10-3 Example of Relationships between System Clock and Baud Rate ......................................................... 134
10-4 Relationships between ASCK20 Pin Input Frequency and Baud Rate
(When BRGC20 Is Set to 80H) ............................................................................................................... 135
10-5 Example of Relationships between System Clock and Baud Rate ......................................................... 142
User's Manual U13600EJ2V0UM00
21
LIST OF TABLES (2/2)
Table No.
Title Page
10-6 Relationships between ASCK20 Pin Input Frequency and Baud Rate
(When BRGC20 Is Set to 80H) ................................................................................................................142
10-7 Receive Error Causes ..............................................................................................................................147
11-1 Interrupt Sources .....................................................................................................................................160
11-2 Interrupt Request Signals and Corresponding Flags ...............................................................................162
11-3 Time from Generation of Maskable Interrupt Request to Processing ......................................................170
12-1 Operation Statuses in HALT Mode ..........................................................................................................177
12-2 Operation after Release of HALT Mode...................................................................................................179
12-3 Operation Statuses in STOP Mode..........................................................................................................180
12-4 Operation after Release of STOP Mode ..................................................................................................181
13-1 State of the Hardware after a Reset.........................................................................................................185
14-1 Differences between Flash Memory and Masked ROM Versions............................................................187
14-2 Communication Mode ..............................................................................................................................188
14-3 Major Functions of Flash Memory Programming .....................................................................................189
14-4 Setting Example with PG-FP3..................................................................................................................191
15-1 Operand Identifiers and Description Methods..........................................................................................193
22
User's Manual U13600EJ2V0UM00
CHAPTER 1 GENERAL
1.1 Features
• ROM and RAM capacity
Product Name
Item Program Memory Data Memory
(Internal High-Speed RAM)
µ
PD789046
µ
PD78F9046
Masked ROM
Flash memory
16 Kbytes
16 Kbytes
512 bytes
• Minimum instruction execution time changeable from high-speed (0.4
µ s: Main system clock 5.0-MHz operation) to ultra-low speed (122
µ s: Subsystem clock 32.768-kHz operation)
• I/O port: 34 lines
• Serial interface: 1 channel
3-wire serial I/O mode/UART mode selectable
• Timer: 4 channels
•
•
16-bit timer counter : 1 channel
8-bit timer/event counter : 1 channel
•
•
Watch timer
Watchdog timer
: 1 channel
: 1 channel
• Vectored interrupt source: 12
• Supply voltage: V
DD
= 1.8 to 5.5 V
• Operating ambient temperature: T
A
= -40
°
C to +85
°
C
1.2 Applications
Cordless telephones, etc.
1.3 Ordering Information
Part Number Package Internal ROM
µ
PD789046GB-
×××
-8ES
µ
PD78F9046GB-8ES
44-pin plastic LQFP (10
44-pin plastic LQFP (10
×
×
10 mm)
10 mm)
Mask ROM
Flash memory
Remark
××× indicates ROM code suffix.
User's Manual U13600EJ2V0UM00
23
1.4 Pin Configuration (Top View)
• 44-pin plastic LQFP (10
××××
10 mm)
µ
PD789046GB-
×××
-8ES
µ
PD78F9046GB-8ES
CHAPTER 1 GENERAL
P12
P11
P10
P47/KR07
P46/KR06
P45/KR05
P44/KR04
P43/KR03
P42/KR02
P41/KR01
P40/KR00
5
6
3
4
1
44 43 42 41 40 39 38 37 36 35 34
33
2 32
31
30
29
28
7
8
9
10
27
26
25
24
11
12 13 14 15 16 17 18 19 20 21 22
23
P04
P05
P06
P07
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SS20
P24/INTP0
P25/INTP1
P26/INTP2/CPT90
Caution Connect the IC0 (internally connected) pin directly to the V
SS0
or V
SS1
pin.
Remark Pin connections in parentheses are intended for the
µ
PD78F9046.
ASCK20 : Asynchronous Serial Input
BZO90
CPT90
: Buzzer Output
: Capture Trigger Input
IC0 : Internally Connected
INTP0 to INTP2 : Interrupt from Peripherals
KR00 to KR07 : Key Return
P00 to P07 : Port 0
P10 to P17
P20 to P27
P30, P31
: Port 1
: Port 2
: Port 3
P40 to P47
RESET
: Port 4
: Reset
RxD20
SCK20
SI20
SO20
SS20
TI80
TO80, TO90
TxD20
V
DD0
, V
DD1
V
PP
V
SS0
, V
SS1
X1, X2
XT1, XT2
: Receive Data
: Serial Clock
: Serial Input
: Serial Output
: Chip Select Input
: Timer Input
: Timer Output
: Transmit Data
: Power Supply
: Programming Power Supply
: Ground
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
24
User's Manual U13600EJ2V0UM00
CHAPTER 1 GENERAL
1.5 78K/0S Series Development
The 78K/0S Series products are shown below. Subseries names are indicated in frames.
In production
Under development
For small-scale, generalpurpose applicationns
44-pin
42/44-pin
28-pin expanding ROM and RAM
With built-in UART bus and capable of low-voltage (1.8 V) operation
For small-scale, general-purpose applications and A/D function
With built-in EEPROM TM
44/48-pin
44/48-pin
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
30-pin
30-pin Device developed by adding the A/D function and multiplier to the
PD789026
For inverter control
44-pin With built-in inverter control circuit and UART bus
78K/0S
Series
For LCD driving
With built-in UART bus and dot LCD 88-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin Basic subseries for LCD driving
For ASSP
44-pin
44-pin
20-pin
20-pin
Device for a PC keyboard, with a built-in USB function
Device for a keypad, with a built-in POC
Device for a keyless entry, with built-in POC and key return circuit
For IC card
5-pin With built-in EEPROM and security circuit
User's Manual U13600EJ2V0UM00
25
CHAPTER 1 GENERAL
The following table lists the major differences in functions between the subseries.
Subseries
Function ROM Size Timer
8-Bit 16-Bit Watch WDT
8-Bit
A/D
10-Bit
A/D
Serial Interface
−
1 ch (UART: 1 ch) Small-scale, generalpurpose applications
µ
µ
PD789046
PD789026
µ
PD789014
16 K
4 K to 16 K
2 K to 4 K
1 ch
2 ch
1 ch
−
1 ch
−
1 ch
−
Small-scale, generalpurpose applications and A/D function
µ
PD789217AY
µ
PD789197AY
16 K to 24 K 3 ch
µ
PD789177
µ
PD789167
µ
PD789156
µ
PD789146
µ
PD789134A
µ
PD789124A
8 K to 16 K
2 K to 8 K
1 ch
Inverter control
µ
PD789114A
µ
PD789104A
µ
PD789842 8 K to 16 K 3 ch
1 ch
Note
1 ch
−
1 ch
1 ch
1 ch
−
8 ch
−
4 ch
−
4 ch
−
4 ch
8 ch
LCD driving
µ
PD789830
µ
PD789417A
µ
PD789407A
µ
PD789457
µ
PD789447
µ
PD789437
µ
PD789427
µ
PD789316
24 K
12 K to 24 K
16 K to 24 K
8 K to 16 K
1 ch
3 ch
2 ch
1 ch 1 ch 1 ch
−
7 ch
−
4 ch
−
4 ch
−
8 ch
−
4 ch
−
4 ch
−
4 ch
−
−
−
7 ch
−
4 ch
−
4 ch
−
2 ch UART : 1 ch
SMB : 1 ch
1 ch (UART: 1 ch)
1 ch (UART: 1 ch)
1 ch (UART: 1 ch)
2 ch (UART: 1 ch)
I/O
34 pins 1.8 V
22 pins
31 pins
20 pins
1.8 V
30 pins 4.0 V
30 pins
43 pins
25 pins
23 pins
Minimum
V
DD
Value
2.7 V
1.8 V
ASSP
IC card
µ
µ
PD789800
µ
PD789840
µ
PD789861
µ
µ
PD789306
PD789860
PD789810
8 K
4 K
6 K
2 ch
−
1 ch
−
−
−
−
1 ch
1 ch
−
4 ch
−
−
−
−
2 ch (USB: 1 ch)
1 ch
−
−
31 pins
29 pins
14 pins
1 pin
4.0 V
2.8 V
1.8 V
2.7 V
Remarks
−
RC-oscillator version, on-chip
EEPROM
On-chip
EEPROM
−
On-chip
EEPROM
RC-oscillator version
−
−
−
RC-oscillator version
−
RC-oscillator version
−
−
RC-oscillator version
−
On-chip
EEPROM
26
User's Manual U13600EJ2V0UM00
1.6 Block Diagram
TI80/TO80/P27
CPT90/INTP2/P26
TO90/P30
BZO90/P31
8-bit TIMER80
16-bit TIMER90
WATCH TIMER
WATCHDOG TIMER
SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
SS20/P23
INTP0/P24
INTP1/P25
INTP2/CPT90/P26
KR00/P40 to KR07/P47
SIO20
INTERRUPT
CONTROL
CHAPTER 1 GENERAL
78K/0S
CPU CORE
ROM
RAM
V
DD0
V
SS0
IC0
V
DD1
V
SS1
(V
PP
)
Remark Pin connections in parentheses are intended for the
µ
PD78F9046.
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
SYSTEM
CONTROL
P00 to P07
P10 to P17
P20 to P27
P30, P31
P40 to P47
RESET
X1
X2
XT1
XT2
User's Manual U13600EJ2V0UM00
27
CHAPTER 1 GENERAL
1.7 Functions
Product
µ
PD789046
µ
PD78F9046
Item
Internal memory ROM structure Masked ROM Flash memory
ROM capacity 16 Kbytes
High-speed RAM 512 bytes
Minimum instruction execution time
General-purpose registers
• 0.4/1.6
µ s (operation with main system clock running at 5.0 MHz)
• 122
µ s (operation with subsystem clock running at 32.768 kHz)
8 bits
×
8 registers
Instruction set
I/O ports
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
34 CMOS input/output pins
Serial interface Switchable between three-wire serial I/O and UART modes
Timers
Timer output
Vectored interrupt sources
Maskable
Nonmaskable
• 16-bit timer : 1 channel
• 8-bit timer/event counter : 1 channel
• Clock timer
• Watchdog timer
: 1 channel
: 1 channel
Two outputs
Seven internal and four external interrupts
Power supply voltage
Operating ambient temperature
Package
One internal interrupt
V
DD
= 1.8 to 5.5 V
T
A
=
−
40°C to
+
85°C
44-pin plastic LQFP (10
×
10 mm)
The outline of the timer is as follows.
Operating mode
Function
Interval timer
External event counter
Timer output
PWM output
Square-wave output
Buzzer output
Capture
Interrupt source
16-Bit Timer
−
−
1 output
−
−
1 output
1 input
1
8-Bit Timer/Event
Counter
1 channel
1 channel
1 output
1 output
1 output
−
−
1
Watch Timer
1 channel
Note 1
−
−
−
−
−
−
1
Watchdog Timer
1 channel
Note 2
−
−
−
−
−
−
1
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer provides the watchdog timer function and interval timer function. Use either of the functions.
28
User's Manual U13600EJ2V0UM00
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
(1) Port pins
Pin Name I/O Function
P00 to P07 I/O Port 0
8-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
P10 to P17 I/O Port 1
8-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
P20
P21
P22
P23
I/O Port 2
8-bit input/output port
Can be set to either input or output in 1-bit units
Whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register B2 (PUB2).
P24
P25
P26
P27
P30
P31
I/O Port 3
2-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
P40 to P47 I/O Port 4
8-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
After Reset Alternate Function
Input
−
Input
Input
Input
Input
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
SS20
INTP0
INTP1
INTP2/CPT90
TI80/TO80
TO90
BZO90
−
KR00 to KR07
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
XT2
RESET
V
DD0
V
DD1
V
SS0
V
SS1
IC0
Pin Name
INTP0
INTP1
INTP2
I/O Function
Input External interrupt input for which effective edges (rising and/or falling edges) can be set
KR00 to KR07 Input Detection of key return signal
SI20 Input Serial data input to serial interface
SO20
SCK20
SS20
ASCK20
RxD20
TxD20
TI80
TO80
TO90
Output
I/O
Serial data output from serial interface
Serial clock input to serial interface
Input Chip select input to serial interface
Input Serial clock input to asynchronous serial interface
Input Serial data input to asynchronous serial interface
BZO90
CPT90
X1
X2
XT1
V
PP
Output Serial data output from asynchronous serial interface
Input External count clock input to 8-bit timer (TM80)
Output 8-bit timer (TM80) output
Output 16-bit timer (TM90) output
Output 16-bit timer (TM90) buzzer output
Input Capture edge input
Input
−
Input
−
Connected to crystal for main system clock oscillation
Connected to crystal for subsystem clock oscillation
Input System reset input
−
−
−
−
−
Positive supply voltage for ports
Positive supply voltage (for circuits other than ports)
Ground potential for ports
Ground potential (for circuits other than ports)
This pin is internally connected. Connect this pin directly to the V
SS0
or V
SS1
pin.
−
This pin is used to set the flash memory programming mode and applies a high voltage when a program is written or verified. In normal operation mode, connect this pin directly to the V
SS0
or V
SS1
pin.
Input
Input
Input
Input
−
−
−
−
−
Input
−
−
−
−
After Reset Alternate Function
Input P24
Input
Input
P25
P26/CPT90
P40 to P47
P22/RxD20
Input
Input
Input
Input
Input
Input
Input
P21/TxD20
P20/ASCK20
P23
P20/SCK20
P22/SI20
P21/SO20
P27/TO80
P27/TI80
P30
P31
P26/INTP2
−
−
−
−
−
−
−
−
−
−
− −
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P07 (Port 0)
These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0).
2.2.2 P10 to P17 (Port 1)
These pins constitute an 8-bit I/O port. Can be set to input or output port mode in 1-bit units by using port mode register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pullup resistor option register 0 (PU0).
2.2.3 P20 to P27 (Port 2)
These pins constitute an 8-bit I/O port. In addition, these pins provide a function to perform input/output to/from the timer, to input/output the data and clock of the serial interface, and to input the external interrupt.
Port 2 can be set to the following operation modes bit-wise.
(1) Port mode
In port mode, P20 to P27 function as an 8-bit I/O port. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). For P20 to P27, whether to use on-chip pull-up resistors can be specified in 1-bit units by using pull-up resistor option register B2 (PUB2), regardless of the setting of port mode register 2 (PM2).
(2) Control mode
In this mode, P20 to P27 function as the timer input/output, the data input/output and the clock input/output of the serial interface, and the external interrupt input.
(a) TI80
This is the external clock input pin for the 8-bit timer/event counter.
(b) TO80
This is the timer output pin of the 8-bit timer/event counter.
(c) SI20, SO20
This is the serial data I/O pin of the serial interface.
(d) SCK20
This is the serial clock I/O pin of the serial interface.
(e) SS20
This is the chip select input pin of the serial interface.
(f) RxD20, TxD20
These are the serial data I/O pins of the asynchronous serial interface.
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CHAPTER 2 PIN FUNCTIONS
(g) ASCK20
This is the serial clock input pin of the asynchronous serial interface.
(h) CPT90
This is the capture edge input pin of the 16-bit timer counter.
(i) INTP0 to INTP2
These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both the rising and falling edges) can be specified.
Caution When using P20 to P27 as serial interface pins, the input/output mode and output latch must be set according to the functions to be used. For details of the setting, see Table
10-2.
2.2.4 P30, P31 (Port 3)
These pins constitute a 2-bit I/O port. In addition, these pins function as the timer output and the buzzer output.
Port 3 can be set to the following operation modes bit-wise.
(1) Port mode
In port mode, P30 and P31 function as a 2-bit I/O port. Port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (PM3). When this port is used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0).
(2) Control mode
In this mode, P30 and P31 function as the timer output and the buzzer output.
(a) TO90
This is the output pin of the 16-bit timer counter.
(b) BZO90
This is the buzzer output pin of the 16-bit timer counter.
2.2.5 P40 to P47 (Port 4)
These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection pins.
Port 4 can be set to the following operation modes bit-wise.
(1) Port mode
In port mode, P40 to P47 function as an 8-bit I/O port. Port 4 can be set to input or output mode in 1-bit units by using port mode register 4 (PM4). When this port is used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0).
(2) Control mode
In this mode, P40 to P47 function as key return signal detection pins (KR00 to KR07).
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2.2.6 RESET
An active-low system reset signal is input to this pin.
2.2.7 X1, X2
These pins are used to connect a crystal resonator for main system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
2.2.8 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
2.2.9 V
DD0
, V
DD1
V
DD0
supplies positive power to the ports.
V
DD1
supplies positive power to circuits other than those of the ports.
2.2.10 V
SS0
, V
SS1
V
SS0
is the ground pin for the ports.
V
SS1
is the ground pin for circuits other than those of the ports.
2.2.11 V
PP
(
µµµµ
PD78F9046 only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified.
Directly connect this pin to V
SS0
or V
SS1
in normal operation mode.
2.2.12 IC0 (masked ROM version only)
The IC0 (Internally Connected) pin is used to set the
µ
PD789046 to test mode before shipment. In normal operation mode, directly connect this pin to the V
SS0
or V
SS1
pin with as short a wiring length as possible.
If a potential difference is generated between the IC0 pin and V
SS0
or V
SS1
pin due to a long wiring length between the IC0 pin and V
SS0
or V
SS1
pin or an external noise superimposed on the IC0 pin, a user program may not run correctly.
••••
Directly connect the IC0 pin to the V
SS0
or V
SS1
pin.
V
SS0
,
V
SS1
IC0
Keep short
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin Input/Output Circuits and Handling of Unused Pins
Table 2-1 lists the types of input/output circuits for each pin and explains how unused pins are handled.
Figure 2-1 shows the configuration of each type of input/output circuit.
Table 2-1. Type of Input/Output Circuit for Each Pin and Handling of Unused Pins
Pin Name
P00 to P07
P10 to P17
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SS20
P24/INTP0
P25/INTP1
P26/INTP2/CPT90
P27/TI80/TO80
P30/TO90
P31/BZO90
P40/KR00 to P47/KR07
XT1
XT2
RESET
IC0 (masked ROM version)
V
PP
(flash memory version)
I/O Circuit Type
5-H
8-C
5-H
8-C
−
2
−
I/O
I/O
Recommended Connection of Unused Pins
Input: Connect these pins to the V
DD0
, V
DD1
, V
SS0
, or V
SS1
pin via respective resistors.
Output: Leave these pins open.
Input Connect this pin to the V
SS0
or V
SS1
pin.
−
Leave this pin open.
Input
−
−
Connect these pins directly to the V
SS0
or V
SS1
pin.
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User's Manual U13600EJ2V0UM00
Type 5-H
Pull-up enable
Data
Output disable
Input enable
Type 2
IN
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin Input/Output Circuits
Type 8-C
Pull-up enable
Schmitt trigger input with hysteresis
Data
Output disable
V
DD0
V
DD0
P-ch
P-ch
IN/OUT
V
SS0
N-ch
V
DD0
V
DD0
P-ch
P-ch
IN/OUT
V
SS0
N-ch
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[MEMO]
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The
µ
PD789046 Subseries can each access up to 64 Kbytes of memory space. Figures 3-1 and 3-2 show the memory maps.
Figure 3-1. Memory Map (
µµµµ
PD789046)
F F F F H
Special Function Register
256
×
8 bits
F F 0 0 H
F E F F H
Internal High-Speed RAM
512
×
8 bits
F D 0 0 H
F C F F H
Unusable
Data Memory Space
3 F F F H
4 0 0 0 H
3 F F F H
Program Area
Program Memory
Space
0 0 0 0 H
Internal ROM
16,384
×
8 bits
0 0 8 0 H
0 0 7 F H
0 0 4 0 H
0 0 3 F H
0 0 1 A H
0 0 1 9 H
0 0 0 0 H
CALLT Table Area
Program Area
Vector Table Area
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37
Data Memory Space
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (
µµµµ
PD78F9046)
F F F F H
F F 0 0 H
F E F F H
Special Function Register
256
×
8 bits
Internal High-Speed RAM
512
×
8 bits
F D 0 0 H
F C F F H
Unusable
3 F F F H
4 0 0 0 H
3 F F F H
Program Memory
Space
0 0 0 0 H
Flash Memory
16,384
×
8 bits
Program Area
0 0 8 0 H
0 0 7 F H
0 0 4 0 H
0 0 3 F H
0 0 1 A H
0 0 1 9 H
0 0 0 0 H
CALLT Table Area
Program Area
Vector Table Area
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC).
The
µ
PD789046 Subseries provide the following internal ROMs (or flash memory) containing the following capacities.
µ
PD789046
µ
PD78F9046
Part Number
Table 3-1. Internal ROM Capacity
Structure
Masked ROM
Flash memory
Internal ROM
Capacity
16,384
×
8 bits
16,384
×
8 bits
The following areas are allocated to the internal program memory space:
(1) Vector table area
A 26-byte area of addresses 0000H to 0019H is reserved as a vector table area. This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation. Of a
16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address.
Vector Table Address
0000H
0004H
0006H
0008H
000AH
000CH
Table 3-2. Vector Table
Interrupt Request
RESET input
INTWDT
INTP0
INTP1
INTP2
INTSR20/INTCSI20
Vector Table Address
000EH
0010H
0012H
0014H
0016H
0018H
Interrupt Request
INTST20
INTWT
INTWTI
INTTM80
INTTM90
INTKR00
(2) CALLT instruction table area
In a 64-byte area of addresses 0040H to 007FH, the subroutine entry address of a 1-byte call instruction
(CALLT) can be stored.
3.1.2 Internal data memory (internal high-speed RAM) space
The
µ
PD789046 Subseries provide 512-byte internal high-speed RAM.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated to an area of FF00H to FFFFH
(see Table 3-3).
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CHAPTER 3 CPU ARCHITECTURE
3.1.4 Data memory addressing
Each of the
µ
PD789046 Subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. A data memory area (FD00H to FFFFH) can be accessed using a unique addressing mode according to its use, such as a special function register (SFR). Figures 3-3 and 3-4 illustrate the data memory addressing modes.
Figure 3-3. Data Memory Addressing Modes (
µµµµ
PD789046)
F F F F H
Special Function Register (SFR)
256
×
8 bits
SFR Addressing
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Internal High-Speed RAM
512
×
8 bits
Short Direct Addressing
F E 2 0 H
F E 1 F H
F D 0 0 H
F C F F H
Direct Addressing
Register Indirect Addressing
Based Addressing
Unusable
4 0 0 0 H
3 F F F H
0 0 0 0 H
Internal ROM
16,384
×
8 bits
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Data Memory Addressing Modes (
µµµµ
PD78F9046)
F F F F H
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Special Function Register (SFR)
256
×
8 bits
SFR Addressing
Internal High-Speed RAM
512
×
8 bits
Short Direct Addressing
F E 2 0 H
F E 1 F H
F D 0 0 H
F C F F H
Direct Addressing
Register Indirect Addressing
Based Addressing
Unusable
4 0 0 0 H
3 F F F H
0 0 0 0 H
Flash Memory
16,384
×
8 bits
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CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
The
µ
PD789046 Subseries provide the following on-chip processor registers:
3.2.1 Control registers
The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-5. Program Counter Configuration
15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets PSW to 02H.
PSW
Figure 3-6. Program Status Word Configuration
7
IE Z 0 AC 0 0 1
0
CY
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CHAPTER 3 CPU ARCHITECTURE
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
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CHAPTER 3 CPU ARCHITECTURE
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 3-7. Stack Pointer Configuration
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.
Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before instruction execution.
SP SP _ 2
SP _ 2
SP _ 1
SP
PUSH rp
Instruction
Figure 3-8. Data to be Saved to Stack Memory
CALL, CALLT
Instructions
SP SP _ 3
SP SP _ 2 SP _ 3
Lower Half
Register Pairs
Upper Half
Register Pairs
SP _ 2
SP _ 1
PC7 to PC0
PC15 to PC8
SP _ 2
SP _ 1
SP SP
Interrupt
PC7 to PC0
PC15 to PC8
PSW
Figure 3-9. Data to be Restored from Stack Memory
POP rp
Instruction
RET Instruction RETI Instruction
SP
SP + 1
SP SP + 2
Lower Half
Register Pairs
Upper Half
Register Pairs
SP
SP + 1
SP SP + 2
PC7 to PC0
PC15 to PC8
SP
SP + 1
SP + 2
SP SP + 3
PC7 to PC0
PC15 to PC8
PSW
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CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).
In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3).
15
Figure 3-10. General-Purpose Register Configuration
(a) Absolute Names
16-Bit Processing
RP3
RP2
RP1
RP0
8-Bit Processing
R7
R6
R5
R4
R3
R2
R1
R0
0 7 0
15
16-Bit Processing
(b) Functional Names
HL
DE
BC
AX
8-Bit Processing
H
L
D
E
B
C
A
X
0 7 0
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function register (SFR)
Unlike a general-purpose register, each special function register has a special function.
It is allocated in the 256-byte area FF00H to FFFFH.
The special function register can be manipulated, like the general-purpose register, with the operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type.
Each manipulation bit unit can be specified as follows.
•
1-bit manipulation
Describes a symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address.
•
8-bit manipulation
Describes a symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address.
•
16-bit manipulation
Describes a symbol reserved with assembler for the 16-bit manipulation instruction operand. When specifying an address, describe an even address.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
•
Symbol
Indicates the addresses of the implemented special function registers. The symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called "sfrbit.h" of C compiler. Therefore, these symbols can be used as instruction operands if assembler or integrated debugger is used.
•
R/W
Indicates whether the special function register can be read or written.
R/W : Read/write
R : Read only
W : Write only
•
Number of bits manipulated simultaneously
Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.
•
After reset
Indicates the status of the special function register when the RESET signal is input.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Registers (1/2)
FF48H
FF49H
FF4AH
FF50H
FF51H
FF53H
FF70H
FF20H
FF21H
FF22H
FF23H
FF24H
FF32H
FF42H
FF00H
FF01H
FF02H
FF03H
FF04H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF1BH
Address Special Function Register (SFR) Name Symbol R/W
Port 0
Port 1
Port 2
Port 3
Port 4
16-bit compare register 90
P0
P1
P2
P3
P4
CR90
R/W
W
Number of Bits Manipulated Simultaneously After Reset
1 Bit
Ο
Ο
−
Ο
Ο
Ο
8 Bits
Ο
Ο
Ο Note 1
Ο
Ο
Ο
16 Bits
−
−
Ο Note 2
−
−
−
00H
FFFFH
FF71H
FF72H
FF73H
16-bit timer counter 90
16-bit capture register 90
Port mode register 0
Port mode register 1
Port mode register 2
Port mode register 3
Port mode register 4
Pull-up resistor option register B2
Timer clock selection register 2
TM90
TCP90
PM0
PM1
PM2
PM3
PM4
PUB2
TCL2
16-bit timer mode control register 90 TMC90
Buzzer output control register 90 BZC90
Watch timer mode control register
8-bit compare register 80
8-bit timer counter 80
8-bit timer mode control register 80
WTM
CR80
TM80
TMC80
Asynchronous serial interface mode register 20
Asynchronous serial interface status register 20
ASIM20
ASIS20
Serial operation mode register 20 CSIM20
Baud rate generator control register 20 BRGC20
R
R/W
W
R
R/W
R
R/W
−
−
Ο
Ο
Ο
Ο
Ο
Ο
−
Ο
Ο
Ο
−
−
Ο
Ο
Ο
Ο
−
Ο
Ο
Note 1
Note 1
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Note 2
Note 2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0000H
Undefined
FFH
00H
Undefined
00H
Notes 1. CR90, TM90, and TCP90 are designed only for 16-bit access. In direct addressing, however, 8-bit access can also be performed.
2. 16-bit access is allowed only in short direct addressing.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Registers (2/2)
Address Special Function Register (SFR) Name Symbol R/W Number of Bits Manipulated Simultaneously After Reset
FF74H
FFE0H
FFE1H
FFE4H
FFE5H
FFECH
FFF0H
FFF2H
FFF5H
FFF7H
FFF9H
Transmission shift register 20
Reception buffer register 20
Interrupt request flag register 0
Interrupt request flag register 1
Interrupt mask flag register 0
Interrupt mask flag register 1
External interrupt mode register 0
Suboscillation mode register
Subclock control register
Key return mode register 00
Pull-up resistor option register 0
Watchdog timer mode register
FFFAH Oscillation settling time selection register
FFFBH Processor clock control register
TXS20 SIO20
RXB20
IF0
IF1
MK0
MK1
INTM0
SCKM
CSS
KRM00
PU0
WDTM
OSTS
PCC
W
R
R/W
1 Bit
Ο
−
Ο
Ο
−
Ο
Ο
Ο
Ο
Ο
−
−
Ο
Ο
8 Bits
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
16 Bits
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FFH
Undefined
00H
FFH
00H
04H
02H
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. PC contents are normally incremented
(+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination address information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S Series User's Manual
Instruction (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) to branch. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
α
PC
+
8 7 6
S
0
... PC is the start address of
the next instruction of
a BR instruction.
0 jdisp8
PC
15
When S = 0,
α
indicates all bits "0".
When S = 1,
α
indicates all bits "1".
0
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) to branch.
This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.
CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7 0
CALL or BR
Low Addr.
High Addr.
PC
15 8 7 0
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3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.
[Illustration]
Instruction Code
7 6 5
0 1 ta
4–0
1 0
0
Effective Address
15
0
8 7
0 0 0 0 0 0 0 0
6 5
1
1 0
0
Effective Address + 1
7 Memory (Table)
Low Addr.
High Addr.
0
PC
15 8 7 0
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7 0 7 0 rp A X
PC
15 8 7 0
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3.4 Operand Address Addressing
The following methods (addressing) are available to specify the register and memory which undergo manipulation during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction Code 0 0 1 0 1 0 0 1 OP Code
0 0 0 0 0 0 0 0 00H
1 1 1 1 1 1 1 0 FEH
[Illustration]
7 0
OP Code addr16 (low) addr16 (high)
Memory
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3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal highspeed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier saddr saddrp
Description
Label or FE20H to FF1FH immediate data
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction Code 1 1 1 1 0 1 0 1 OP Code
1 0 0 1 0 0 0 0 90H (saddr-offset)
0 1 0 1 0 0 0 0 50H (immediate data)
[Illustration]
7 0
OP Code saddr-offset
Short Direct Memory
Effective
Address
15
1 1 1 1 1 1 1
8
α
When 8-bit immediate data is 20H to FFH, = 0.
α
0
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3.4.3 Special function register (SFR) addressing
[Function]
The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier sfr
Description
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction Code 1 1 1 0 0 1 1 1
0 0 1 0 0 0 0 0
[Illustration]
7 0
OP Code sfr-offset
SFR
Effective
Address
15
1 1 1 1 1 1 1 1
8 7 0
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3.4.4 Register addressing
[Function]
The general-purpose register is accessed as an operand.
The general-purpose register to be accessed is specified with register specify code and functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier r rp
X, A, C, B, E, D, L, H
AX, BC, DE, HL
Description
'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A,
C, B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction Code 0 0 0 0 1 0 1 0
0 0 1 0 0 1 0 1
Register Specify Code
INCW DE; When selecting the DE register pair for rp
Instruction Code 1 0 0 0 1 0 0 0
Register Specify Code
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CHAPTER 3 CPU ARCHITECTURE
3.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
−
[DE], [HL]
Description
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction Code 0 0 1 0 1 0 1 1
[Illustration]
DE
15 8 7
D
The contents of addressed memory are transferred
7 0
A
7
E
0
0
Memory address specified by register pair DE
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3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
−
[HL+byte]
Description
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction Code 0 0 1 0 1 1 0 1
0 0 0 1 0 0 0 0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing can be used to access the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction Code 1 0 1 0 1 0 1 0
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[MEMO]
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The
µ
PD789046 Subseries is provided with the ports shown in Figure 4-1. These ports are used to enable several types of control. Table 4-1 lists the functions of each port.
These ports, while originally designed as digital input/output ports, have alternate functions, as summarized in
Section 2.1.
Figure 4-1. Port Types
P20 P00
Port 2 Port 0
Port 3
P27
P30
P31
P40
P07
P10
Port 4 Port 1
P47 P17
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Table 4-1. Port Functions
Pin Name I/O Function
P00 to P07 I/O Port 0
8-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
P10 to P17 I/O Port 1
8-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
P20
P21
P22
P23
I/O Port 2
8-bit input/output port
Can be set to either input or output in 1-bit units
Whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register B2 (PUB2).
P24
P25
P26
P27
P30
P31
I/O Port 3
2-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
P40 to P47 I/O Port 4
8-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
After Reset Alternate Function
Input
−
Input
Input
Input
Input
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
SS20
INTP0
INTP1
INTP2/CPT90
TI80/TO80
TO90
BZO90
−
KR00 to KR07
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4.2 Port Configuration
Ports have the following hardware configuration.
Parameter
Control register
Port
Pull-up resistor
Table 4-2. Configuration of Port
Port mode registers (PMm: m = 0 to 4)
Pull-up resistor option register 0 (PU0)
Pull-up resistor option register B2 (PUB2)
Total: 34 (CMOS input/output: 34)
Total: 34 (software control: 34)
Configuration
4.2.1 Port 0
This is an 8-bit I/O port with an output latch. Port 0 can be set to input or output mode in 1-bit units by using port mode register 0 (PM0). When pins P00 to P07 are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 0 to input mode.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P07
V
DD0
WR
PU0
PU00
P-ch
RD
WR
PORT
WR
PM
Output Latch
(P00 to P07)
PM00 to PM07
PU0 : Pull-up resistor option register 0
PM : Port mode register
RD : Port 0 read signal
WR : Port 0 write signal
P00 to P07
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4.2.2 Port 1
This is an 8-bit I/O port with an output latch. Port 1 can be set to input or output mode in 1-bit units by using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 1 to input mode.
Figure 4-3 shows a block diagram of port 1.
Figure 4-3. Block Diagram of P10 to P17
V
DD0
WR
PU0
PU01
P-ch
RD
WR
PORT
WR
PM
Output Latch
(P10 to P17)
PM10 to PM17
PU0 : Pull-up resistor option register 0
PM : Port mode register
RD : Port 1 read signal
WR : Port 1 write signal
P10 to P17
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CHAPTER 4 PORT FUNCTIONS
4.2.3 Port 2
This is an 8-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). For pins P20 to P27, on-chip pull-up resistors can be connected in 1-bit units by using pullup resistor option register B2 (PUB2).
The port is also used as a data I/O and clock I/O to and from the serial interface, timer I/O, and external interrupt input.
RESET input sets port 2 to input mode.
Figures 4-4 through 4-8 show block diagrams of port 2.
Caution When using the pins of port 2 as the serial interface, the I/O and output latches must be set according to the function to be used. For details of the settings, see Table 10-2.
Figure 4-4. Block Diagram of P20
V
DD0
WR
PUB2
PUB20
Alternate
Function
P-ch
RD
WR
PORT
WR
PM
Output Latch
(P20)
PM20
Alternate
Function
PUB2 : Pull-up resistor option register B2
PM : Port mode register
RD : Port 2 read signal
WR : Port 2 write signal
P20/ASCK20/
SCK20
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WR
PUB2
RD
PUB21
CHAPTER 4 PORT FUNCTIONS
Figure 4-5. Block Diagram of P21
V
DD0
P-ch
WR
PORT
WR
PM
Output Latch
(P21)
PM21
Alternate
Function
SS20 Chip Select
Input Signal
PUB2 : Pull-up resistor option register B2
PM : Port mode register
RD : Port 2 read signal
WR : Port 2 write signal
P21/TxD20/
SO20
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WR
PUB2
CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P22 and P24 to P26
V
DD0
PUB22,
PUB24 to PUB26
Alternate
Function
P-ch
RD
WR
PORT
WR
PM
Output Latch
(P22, P24 to P26)
PM22,
PM24 to PM26
P22/RxD20/SI20
P24/INTP0
P25/INTP1
P26/INTP2/CPT90
PUB2 : Pull-up resistor option register B2
PM : Port mode register
RD : Port 2 read signal
WR : Port 2 write signal
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WR
PUB2
PUB23
Alternate
Function
RD
WR
PORT
WR
PM
Output Latch
(P23)
PM23
CHAPTER 4 PORT FUNCTIONS
Figure 4-7. Block Diagram of P23
V
DD0
P-ch
P23/SS20
PUB2 : Pull-up resistor option register B2
PM : Port mode register
RD : Port 2 read signal
WR : Port 2 write signal
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WR
PUB2
RD
PUB27
Alternate
Function
CHAPTER 4 PORT FUNCTIONS
Figure 4-8. Block Diagram of P27
V
DD0
P-ch
WR
PORT
WR
PM
Output Latch
(P27)
PM27
Alternate
Function
PUB2 : Pull-up resistor option register B2
PM : Port mode register
RD : Port 2 read signal
WR : Port 2 write signal
P27/TO80/TI80
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4.2.4 Port 3
This is a 2-bit I/O port with output latches. Port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (PM3). When P30 and P31 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0).
The port is also used as timer output and buzzer output.
RESET input sets port 3 to input mode.
Figure 4-9 shows a block diagram of port 3.
Figure 4-9. Block Diagram of P30 and P31
V
DD0
WR
PU0
PU03
P-ch
RD
WR
PORT
Output Latch
(P30, P31)
WR
PM
PM30, PM31
Alternate
Function
PU0 : Pull-up resistor option register 0
PM : Port mode register
RD : Port 3 read signal
WR : Port 3 write signal
P30/TO90
P31/BZO90
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4.2.5 Port 4
This is an 8-bit I/O port with output latches. Port 4 can be set to input or output mode in 1-bit units by using port mode register 4 (PM4). When P40 to P47 are used as input port pins, on-chip pull-up resistors can be connected in
8-bit units by using the pull-up resistor option register 0 (PU0).
The port is also used as the key return input.
RESET input sets port 4 to input mode.
Figure 4-10 shows a block diagram of port 4.
Caution When using port 4 for the key return function, it is necessary to set key return mode register 00
(KRM00). For details of the settings, see Section 11.3 (5).
Figure 4-10. Block Diagram of P40 to P47
V
DD0
WR
PU0
PU04
RD
P-ch
WR
KRM00
WR
PORT
WR
PM
KRM000 to
KRM007
Output Latch
(P40 to P47)
PM40 to PM47
Alternate
Function
KRM00 : Key return mode register 00
PU0 : Pull-up resistor option register 0
PM
RD
WR
: Port mode register
: Port 4 read signal
: Port 4 write signal
P40/KR00 to
P47/KR07
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CHAPTER 4 PORT FUNCTIONS
4.3 Port Function Control Registers
The following two types of registers are used to control the ports.
• Port mode registers (PM0 to PM4)
• Pull-up resistor option registers (PU0 and PUB2)
(1) Port mode registers (PM0 to PM4)
The port mode registers separately set each port bit to either input or output.
Each port mode register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input writes FFH into the port mode registers.
When port pins are used for alternate functions, the corresponding port mode register and output latch must be set or reset as described in Table 4-3.
Caution When port 2 is acting as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as the input for an external interrupt. To use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
P24
P25
P26
Table 4-3. Port Mode Register and Output Latch Settings for Using Alternate Functions
Pin Name PM
××
P
××
P27
P30
P31
P40 to P47
Note
Name
Alternate Function
Input/Output
INTP0
INTP1
INTP2
CPT90
TI80
TO80
TO90
BZO90
KR00 to KR07
Input
Input
Input
Input
Input
Output
Output
Output
Input
1
1
0
1
1
1
0
0
1
0
0
×
×
×
×
×
×
0
Note When an alternate function is used, set key return mode register 00 (KRM00) to 1 (see Section 11.3
(5)).
Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set according to the function to be used. For details of the settings, see Table 10-2.
Remark
×
: Don't care
PM
××
: Port mode register
P
××
: Port output latch
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CHAPTER 4 PORT FUNCTIONS
Symbol
PM0
7
PM07
6
PM06
5
PM05
Figure 4-11. Format of Port Mode Register
4
PM04
3
PM03
2
PM02
1
PM01
0
PM00
Address After Reset R/W
FF20H FFH R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H
PM3 1 1 1 1 1 1 PM31 PM30 FF23H
FFH
FFH
R/W
R/W
FFH R/W
PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H
PMmn
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
Pmn Pin Input/Output Mode Selection
m = 0 to 2, 4 : n = 0 to 7
m = 3 : n = 0, 1
FFH R/W
(2) Pull-up resistor option register 0 (PU0)
Pull-up resistor option register 0 (PU0) sets whether an on-chip pull-up resistor on port 0, 1, 3, or 4 is used.
On the port which is specified to use the on-chip pull-up resistor in PU0, the pull-up resistor can be internally used only for the bits set to input mode. No on-chip pull-up resistors can be used for the bits set to output mode regardless of the setting of PU0. On-chip pull-up resistors cannot be used even when the pins are used as the alternate-function output pins.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H.
Symbol
PU0
7
0
6
0
Figure 4-12. Format of Pull-Up Resistor Option Register 0
5
0
<4>
PU04
<3>
PU03
2
0
<1>
PU01
<0>
PU00
Address After Reset
FFF7H 00H
R/W
R/W
PU0m
0
1
Pm On-Chip Pull-Up Resistor Selection (m = 0, 1, 3, 4)
On-chip pull-up resistor not used
On-chip pull-up resistor used
Caution Bits 2 and 5 to 7 must all be set to 0.
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(3) Pull-up resistor option register B2 (PUB2)
This register specifies whether an on-chip pull-up resistor connected to each pin of port 2 is used. The pin for which use of an on-chip pull-up resistor is specified by PUB2 can use a pull-up register internally, regardless of the setting of the port mode register.
PUB2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 4-13. Format of Pull-Up Resistor Option Register B2
Symbol
PUB2
<7> <6>
PUB27 PUB26
<5> <4> <3>
PUB25 PUB24 PUB23
<2>
PUB22
<1> <0>
PUB21 PUB20
Address After Reset
FF32H 00H
R/W
R/W
PUB2n
0
1
P2n On-Chip Pull-Up Resistor Selection (n = 0 to 7)
On-chip pull-up resistor not used
On-chip pull-up resistor used
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4.4 Operation of Port Functions
The operation of a port differs depending on whether the port is set to input or output mode, as described below.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
The data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF.
The data once written to the output latch is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined.
4.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed.
4.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed with the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins.
The data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF.
Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined.
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[MEMO]
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CHAPTER 5 CLOCK GENERATION CIRCUIT
5.1 Clock Generation Circuit Functions
The clock generation circuit generates the clock to be supplied to the CPU and peripheral hardware.
The following two types of system clock oscillators are used.
••••
Main system clock oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
••••
Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by setting the subclock control register (CSS).
5.2 Clock Generation Circuit Configuration
The clock generation circuit consists of the following items of hardware.
Item
Control register
Oscillator
Table 5-1. Configuration of Clock Generation Circuit
Configuration
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Main system clock oscillator
Subsystem clock oscillator
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Internal Bus
CHAPTER 5 CLOCK GENERATION CIRCUIT
Figure 5-1. Block Diagram of Clock Generation Circuit
FRC SCC Suboscillation Mode Register
(SCKM)
XT1
XT2
Subsystem
Clock Oscillator f
XT
X1
X2
Main System
Clock Oscillator
16-Bit Timer 90
Watch Timer
Prescaler f
X
Prescaler f
X
2 2
1/2 f
XT
2
Clock for
Peripheral
Hardware
Standby
Controller
Wait
Controller
CPU Clock
(f
CPU
)
STOP
Processor Clock
MCC PCC1
Control Register (PCC)
CLS CSS0
Subclock Control
Register (CSS)
Internal Bus
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5.3 Registers Controlling Clock Generation Circuit
The clock generation circuit is controlled by the following registers:
•
Processor clock control register (PCC)
•
Suboscillation mode register (SCKM)
•
Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC selects the CPU clock and the ratio of division.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Symbol
PCC
7
MCC
6
0
Figure 5-2. Format of Processor Clock Control Register
5
0
4
0
3
0
2
0
1
PCC1
0
0
Address After Reset R/W
FFFBH 02H R/W
MCC
0
1
Operation enabled
Operation disabled
Control of Main System Clock Oscillator Operation
CSS0
0
0
1
1
PCC1
0
1
0
1 f
X
(0.2 s) f
X
/2 2 (0.8 s) f
XT
/2 (61 s)
CPU Clock (f
CPU
) Selection Note
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register (PCC) and the CSS0 flag in the subclock control register (CSS). See Section 5.3
(3).
Cautions 1. Bits 0 and 2 to 6 must all be set to 0.
2. MCC can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
4. Minimum instruction execution time: 2f
CPU
•
f
CPU
= 0.2
µ s: 0.4
µ s
•
f
CPU
= 0.8
µ s: 1.6
µ s
•
f
CPU
= 61
µ s: 122
µ s
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(2) Suboscillation mode register (SCKM)
SCKM specifies whether to use a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SCKM to 00H.
Symbol
SCKM
7
0
6
0
Figure 5-3. Format of Suboscillation Mode Register
5
0
4
0
3
0
2
0
1
FRC
0
SCC
Address After Reset
FFF0H 00H
R/W
R/W
FRC
0
1
On-chip feedback resistor used
On-chip feedback resistor not used
Use of Feedback Resistor
SCC
0
1
Operation enabled
Operation disabled
Control of Subsystem Clock Oscillator Operation
Caution Bits 2 to 7 must all be set to 0.
(3) Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be used. It also specifies how the CPU clock operates.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSS to 00H.
Symbol
CSS
7
0
6
0
Figure 5-4. Format of Subclock Control Register
5
CLS
4
CSS0
3
0
2
0
1
0
0
0
Address After Reset
FFF2H 00H
R/W
R/W Note
CLS
0
1
CPU Clock Operation Status
Operation based on the (divided) main system clock
Operation based on the subsystem clock
CSS0
0
1
Selection of Main System or Subsystem Clock Oscillator
(Divided) output from the main system clock oscillator
Output form the subsystem clock oscillator
Note Bit 5 is read-only.
Caution Bits 0 to 3, 6, and 7 must all be set to 0.
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5.4 System Clock Oscillators
5.4.1 Main system clock oscillator
The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the reversed signal to the X2 pin.
Figure 5-5 shows the external circuit of the main system clock oscillator.
Figure 5-5. External Circuit of Main System Clock Oscillator
(a) Crystal or ceramic oscillation (b) External clock
V
SS0
, V
SS1
X1
External
Clock
X1
Crystal or
Ceramic Resonator
X2
X2
5.4.2 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the
XT1 and XT2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the reversed signal to the XT2 pin.
Figure 5-6 shows the external circuit of the subsystem clock oscillator.
Figure 5-6. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation (b) External clock
External
Clock
XT1 V
SS0
, V
SS1
XT1
32.768
kHz
XT2
XT2
Cautions 1. When using the main system or subsystem clock oscillator, to avoid influence of wiring capacity, etc., wire the portion enclosed by the broken line in Figures 5-5 and 5-6 as follows:
••••
Keep the wiring length as short as possible.
••••
Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows.
••••
Always keep the ground of the capacitor of the oscillator at the same potential as V
SS
. Do not ground the capacitor to a ground pattern through which a high current flows.
••••
Do not extract signals from the oscillator.
When using the subsystem clock, pay special attention because the subsystem clock oscillator has low amplification to minimize current consumption.
Figure 5-7 shows unacceptable resonator connections.
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CHAPTER 5 CLOCK GENERATION CIRCUIT
Figure 5-7. Unacceptable Resonator Connections (1/2)
(a) Wiring too long (b) Crossed signal line
PORTn
(n = 0 to 4)
V
SS0
,
V
SS1
X1 X2
V
SS0
,
V
SS1
X1 X2
(c) Wiring near high alternating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
DD0
V
SS0
,
V
SS1
X1 X2
V
SS0
,
V
SS1
X1
P mn
X2
High Current
A B
High Current
C
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 pin in series.
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Figure 5-7. Unacceptable Resonator Connections (2/2)
(e) Signal is extracted (f) Signal conductors of the main and subsystem clocks are parallel and near to each other
V
SS0
,
V
SS1
X1 X2
V
SS0
,
V
SS1
X2 X1 XT2 XT1
XT2 and X1 wiring in parallel
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 pin in series.
Cautions 2. If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between X1 and
XT2, resulting in a malfunction.
To avoid this, do not lay the X1 and XT2 wires in parallel.
5.4.3 Scaler
The scaler divides the main system clock oscillator output (f
X
) and generates clocks.
5.4.4 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows.
XT1: Connect to V
SS0
or V
SS1
XT2: Open
In this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator when the main system clock stops. To minimize the leakage current, the on-chip feedback resistor can be removed by setting bit 1 (FRC) of the suboscillation mode register (SCKM). In this case, also connect the XT1 and XT2 pins as described above.
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5.5 Clock Generation Circuit Operation
The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as standby mode:
•
Main system clock f
X
•
Subsystem clock f
XT
•
CPU clock f
CPU
•
Clock to peripheral hardware
The operation of the clock generation circuit is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows:
(a) The slow mode 2f
CPU
(1.6
µ s: at 5.0-MHz operation) of the main system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the main system clock is stopped.
(b) Three types of CPU clocks f
CPU
(0.2
µ s and 0.8
µ s: main system clock (at 5.0-MHz operation), 61
µ s: subsystem clock (at 32.768-kHz operation)) can be selected by the PCC, SCKM, and CSS settings.
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the on-chip feedback resistor cannot be used reduces current drain during STOP mode. In a system where a subsystem clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current drain operation is used
(122
µ s: at 32.768-kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by using bit 7 (MCC) of PCC. HALT mode can be used, but STOP mode cannot.
(f) The clock for the peripheral hardware is generated by dividing the frequency of the main system clock. The subsystem clock is supplied to 16-bit timer and the watch timer only. So, even in standby mode, 16-bit timer and the watch function can keep running. The other hardware stops when the main system clock stops, because it runs based on the main system clock (except for an external input clock).
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5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 5-2).
0 0
Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value before Switching
CSS0 PCC1 CSS0
0
PCC1
0
Set Value after Switching
CSS0
0
PCC1
1
4 clocks
1 2 clocks
CSS0
1
2f
X
/f
XT
clocks
(306 clocks) f
X
/2f
XT
clocks
(76 clocks)
PCC1
×
1
×
2 clocks 2 clocks
Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
3.
×
: Don't care
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5.6.2 Switching between system clock and CPU clock
The following figure illustrates how the system clock and CPU clock switch.
Figure 5-8. Switching between System Clock and CPU Clock
V
DD
RESET
Interrupt Request Signal
System Clock
CPU Clock f
Slow
X
Operation f
X
Fast Operation f
XT
Subsystem Clock
Operation
Wait (6.55 ms: at 5.0-MHz operation)
Internal Reset Operation f
X
Fast Operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the time during which oscillation settles (2
15
/f
X
) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6
µ s: at
5.0-MHz operation).
<2> After the time required for the V
DD
voltage to rise to the level at which the CPU can operate at the high speed has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS) are rewritten so that the high-speed operation can be selected.
<3> When a drop of the V
DD
voltage is detected with an interrupt request signal, the clock is switched to the subsystem clock. (At this moment, the subsystem clock must be in the oscillation settling status.)
<4> When a recover of the V
DD
voltage is detected with an interrupt request signal, bit 7 (MCC) of PCC is set to
0 to make the main system clock start oscillating. After the time required for the oscillation to settle has elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution When the main system clock is stopped and the subsystem clock is operating, allow sufficient time for the oscillation to settle by coding the program before switching again from the subsystem clock to the main system clock.
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6.1 16-Bit Timer Functions
The 16-bit timer has the following functions.
•
Timer interrupt
•
Timer output
•
Buzzer output
•
Count value capture
(1) Timer interrupt
An interrupt is generated when a count value and compare value match.
(2) Timer output
Timer output can be controlled when a count value and compare value match.
(3) Buzzer output
Buzzer output can be controlled by software.
(4) Count value capture
A count value of 16-bit timer counter 90 (TM90) is latched into a capture register synchronizing with the capture trigger and retained.
6.2 16-Bit Timer Configuration
The 16-bit timer consists of the following items of hardware.
Item
Timer counter
Register
Timer output
Buzzer output
Control register
Table 6-1. Configuration of 16-Bit Timer
Configuration
16 bits
×
1 (TM90)
Compare register : 16 bits
×
1 (CR90)
Capture register : 16 bits
×
1 (TCP90)
1 (TO90)
1 (BZO90)
16-bit timer mode control register 90 (TMC90)
Buzzer output control register 90 (BZC90)
Port mode register 3 (PM3)
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Figure 6-1. Block Diagram of 16-Bit Timer
Internal Bus
16-Bit Timer Mode Control
Register 90 (TMC90)
TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
P30
Output Latch
PM30
TO90/P30 f
X f
XT
16-Bit Compare Register
90 (CR90)
Flip-Flop TOD90 f
X
/2 2 f
X
/2 4 f
X
/2 6
Match
Sync Circuit
16-Bit Timer Counter
90 (TM90)
OVF
CTP90/INTP2/
P26
Edge Detection
Circuit
16-Bit Capture
Register 90 (TCP90) f
X
/2
Write Control Circuit
/ 3
16-Bit Counter
Read Buffer
Write Control Circuit
CPU Clock
Internal Bus
BCS902 BCS901 BCS900 BZOE90
Buzzer Output Control
Register 90 (BZC90)
P31
Output Latch
PM31
INTTM90
BZO90/P31
CHAPTER 6 16-BIT TIMER
(1) 16-bit compare register 90 (CR90)
A value specified in CR90 is compared with the count in 16-bit timer counter 90 (TM90). If they match, an interrupt request (INTTM90) is issued by CR90.
CR90 is set with an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH can be set.
RESET input sets CR90 to FFFFH.
Cautions 1. CR90 is designed to be manipulated with a 16-bit memory manipulation instruction. It can also be manipulated with 8-bit memory manipulation instructions, however. When an 8-bit memory manipulation instruction is used to set CR90, it must be accessed in direct addressing.
2. To re-set CR90 during count operation, it is necessary to disable interrupts in advance, using interrupt mask flag register 1 (MK1). It is also necessary to disable inversion of the timer output data, using 16-bit timer mode control register 90 (TMC90).
If CR90 is rewritten with the interrupt enabled, an interrupt request may be issued immediately.
(2) 16-bit timer counter 90 (TM90)
TM90 is used to count the number of pulses.
The contents of TM90 are read with an 8-bit or 16-bit memory manipulation instruction.
RESET input clears TM90 to 0000H.
Cautions 1. The count becomes undefined when STOP mode is deselected, because the count operation is performed before oscillation settles.
2. TM90 is designed to be manipulated with a 16-bit memory manipulation instruction. It can also be manipulated with 8-bit memory manipulation instructions, however. When an 8-bit memory instruction is used to manipulate TM90, it must be accessed in direct addressing.
3. When an 8-bit memory manipulation instruction is used to manipulate TM90, the lower and upper bytes must be read as a pair, in this order.
(3) 16-bit capture register 90 (TCP90)
TCP90 captures the contents of 16-bit timer counter 90 (TM90).
It is set with an 8-bit or 16-bit memory manipulation instruction.
RESET input makes TCP90 undefined.
Caution TCP90 is designed to be manipulated with a 16-bit memory manipulation instruction. It can also be manipulated with 8-bit memory manipulation instructions, however. When an
8-bit memory manipulation instruction is used to manipulate TCP90, it must be accessed in direct addressing.
(4) 16-bit counter read buffer 90
This buffer is used to latch and hold the count for 16-bit timer counter 90 (TM90).
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6.3 Registers Controlling 16-Bit Timer
The following three types of registers control the 16-bit timer.
•
16-bit timer mode control register 90 (TMC90)
•
Buzzer output control register 90 (BZC90)
•
Port mode register 3 (PM3)
(1) 16-bit timer mode control register 90 (TMC90)
16-bit timer mode control register 90 (TMC90) controls the setting of a count clock, capture edge, etc.
TMC90 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC90 to 00H.
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Figure 6-2. Format of 16-Bit Timer Mode Control Register 90
Symbol 7 <6> 5 4 3 2 1 <0>
TMC90 TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
Address After Reset R/W
FF48H 00H R/W Note
TOD90
0
1
Timer output of 0
Timer output of 1
Timer Output Data
TOF90
0 Reset or cleared by software
1 Set when the 16-bit timer overflows
Overflow Flag Control
CPT901 CPT900
0 0
0
1
1
0
Capture Edge Selection
Capture operation disabled
Captured at the rising edge at the CPT90 pin
1 1
Captured at the falling edge at the CPT90 pin
Captured at both the rising and falling edges at the CPT90 pin
TOC90
0
1
Inversion disabled
Inversion enabled
TCL901 TCL900
0 0
0
1
1
1
0
1 f
X
/2 2 (1.25 MHz) f
X
/2 6 (78.125 kHz) f
X
/2 4 (31.1 kHz) f
XT
(32.768 kHz)
TOE90
0
1
Output disabled (port mode)
Output enabled
Timer Output Data Inversion Control
16-Bit Timer Counter 90 Count Clock Selection
16-Bit Timer Output Control
Note Bit 7 is read-only.
Caution Disable the interrupt in advance by using the interrupt mask flag register 1 (MK1) to change the data of TCL901 and TCL900. Also, prevent the timer output data from being inverted by setting TOE90 to 1.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
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(2) Buzzer output control register 90 (BZC90)
This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and
TCL900), and controls the output of a square wave.
BZC90 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears BZC90 to 00H.
Symbol
BZC90
7
0
6
0
Figure 6-3. Format of Buzzer Output Control Register 90
5
0
4
0
3 2 1 <0>
BCS902 BCS901 BCS900 BZOE90
Address After Reset R/W
FF49H 00H R/W
BZOE90
0
1
Disables buzzer port output.
Enables buzzer port output.
Buzzer Port Output Control
BCS902 BCS901 BCS900
0
0
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1 fcl = f
X
/2 2 fcl/2 4 (78.125 kHz) fcl/2 5 (39.063 kHz) fcl/2 8 (4.88 kHz) fcl/2 9 (2.44 kHz) fcl/2 10 (1.22 kHz) fcl/2 11 (610 Hz) fcl/2 12 (305 Hz) fcl/2 13 (153 Hz)
Buzzer Frequency fcl = f
X
/2 6 fcl/2 4 (4.88 kHz) fcl/2 5 (2.44 kHz) fcl/2 fcl/2
4
5 fcl = f
X
/2 4
(19.5 kHz)
(9.77 kHz) fcl/2 8 (305 Hz) fcl/2 9 (153 Hz) fcl/2 10 (76 Hz) fcl/2 fcl/2 fcl/2
8
9
(1.22 kHz)
(610 Hz)
10 (305 Hz) fcl/2 11 (38 Hz) fcl/2 12 (19 Hz) fcl/2 13 (10 Hz) fcl/2 11 (153 Hz) fcl/2 12 (76.3 Hz) fcl/2 13 (38.1 Hz) fcl = f
XT fcl/2 4 (2.05 kHz) fcl/2 5 (1.02 kHz) fcl/2 8 (128 Hz) fcl/2 9 (64 Hz) fcl/2 10 (32 Hz) fcl/2 11 (16 Hz) fcl/2 12 (8 Hz) fcl/2 13 (4 Hz)
Cautions 1. Bits 4 to 7 must all be set to 0.
2. If the subclock is selected as the count clock (TCL901 = 1, TCL900 = 1: see Figure 6-2), the subclock is not synchronized when buzzer port output is enabled. In this case, the capture function and TM90 register read function are disabled. In addition, the count value of the TM90 register is undefined.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
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(3) Port mode register 3 (PM3)
PM3 is used to set each bit of port 3 to input or output.
When pin P30/TO90 is used for timer output, reset the output latch of P30 and PM30 to 0; when pin
P31/BZO90 is used for buzzer output, reset the output latch of P31 and PM31 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Symbol
PM3
7
1
6
1
5
1
Figure 6-4. Format of Port Mode Register 3
4
1
3
1
2
1
1
PM31
0
PM30
Address After Reset R/W
FF23H FFH R/W
PM3n
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
P3n Pin I/O Mode (n = 0, 1)
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6.4 16-Bit Timer Operation
6.4.1 Operation as timer interrupt
In the timer interrupt function, interrupts are repeatedly generated at the count value set in 16-bit compare register 90 (CR90) in advance based on the intervals of the value set in TCL901 and TCL900.
To operate 16-bit timer as a timer interrupt, the following settings are required.
•
Set count values in CR90
•
Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-5.
Figure 6-5. Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation
TMC90
TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
−
0/1 0/1 0/1 0/1 0/1 0/1 0/1
Setting of count clock (see Table 6-2)
Caution If 0 is set both for CPT901 and CPT900 flags, capture operation becomes prohibited.
When the count value of 16-bit timer counter 90 (TM90) coincides with the value set in CR90, counting of TM90 continues and an interrupt request signal (INTTM90) is generated.
Table 6-2 shows interval time, and Figure 6-6 shows timing of timer interrupt operation.
Caution Perform the following processing when rewriting CR90 during count operation.
<1> Disable the interrupt (TMMK90 (bit 7 of the interrupt mask flag register 0 (MK0)) = 1).
<2> Disable inversion control of timer output data (TOC90 = 0).
If CR90 is rewritten with the interrupt enabled, an interrupt request may be issued immediately.
TCL901
0
0
1
1
TCL900
0
1
0
1
2 2 /f
X
(0.8
µ s)
2
6
/f
X
(12.8
µ s)
2
4
/f
X
(3.2
µ s)
1/f
XT
(30.5
µ s)
Table 6-2. Interval Time of 16-Bit Timer
Count Clock
2 18 /f
X
(52.4 ms)
2
22
/f
X
(838.9 ms)
2
20
/f
X
(210.0 ms)
2 16 /f
XT
(2.0 s)
Interval Time
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
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Figure 6-6. Timing of Timer Interrupt Operation t
Count Clock
TM90 Count Value
CR90
INTTM90
0000H 0001H
N
N
N
FFFFH 0000H 0001H
N
Interrupt Accept
TO90
TOF90
Overflow Flag Set
N
N
FFFFH
N
Interrupt Accept
Remark N = 0000H to FFFFH
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6.4.2 Operation as timer output
Timer outputs are repeatedly generated at the count value set in 16-bit compare register 90 (CR90) in advance based on the intervals of the value set in TCL901 and TCL900.
To operate 16-bit timer as a timer output, the following settings are required.
•
Set P30 to output mode (PM30 = 0).
•
Reset the output latch of P30 to 0.
•
Set the count value in CR90.
•
Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-7.
Figure 6-7. Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation
TMC90
TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
−
0/1 0/1 0/1 1 0/1 0/1 1
TO90 output enable
Setting of count clock (see Table 6-2)
Inverse enable of timer output data
Caution If both CPT901 flag and CPT900 flag are set to 0, capture operation becomes prohibited.
When the count value of 16-bit timer counter 90 (TM90) matches the value set in CR90, the output status of the
TO90/P30 pin is inverted. This enables timer output. At that time, TM90 count is continued and an interrupt request signal (INTTM90) is generated.
Figure 6-8 shows the timing of timer output (see Table 6-2 for the interval time of the 16-bit timer).
Figure 6-8. Timer Output Timing t
Count Clock
TM90 Count Value
CR90
INTTM90
0000H 0001H
N
N
N
FFFFH 0000H 0001H
N
N
N
FFFFH
N
Interrupt Accept Interrupt Accept
TO90 Note
TOF90
Overflow Flag Set
Note The TO90 initial value becomes low level during output enable (TOE90 = 1).
Remark N = 0000H to FFFFH
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6.4.3 Capture operation
The capture operation consists of latching the count value of 16-bit timer counter 90 (TM90) into a capture register synchronizing with a capture trigger, and retaining the count value.
Set TMC90 as shown in Figure 6-9 to allow 16-bit timer to start the capture operation.
Figure 6-9. Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation
TMC90
TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
−
0/1 0/1 0/1 0/1 0/1 0/1 0/1
Count clock selection
Capture edge selection (see Table 6-3)
16-bit capture register 90 (TCP90) starts capture operation after a CPT90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer counter 90. TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection.
Table 6-3 and Figure 6-10 shows the settings of capture edge and capture operation timing, respectively.
CPT901
0
0
1
1
CPT900
0
1
0
1
Table 6-3. Settings of Capture Edge
Capture Edge Selection
Capture operation prohibited
CPT90 pin rising edge
CPT90 pin falling edge
CPT90 pin both edges
Caution Because TCP90 is rewritten when a capture trigger edge is detected during TCP90 read, disable the capture trigger edge detection during TCP90 read.
Figure 6-10. Capture Operation Timing (Both Edges of CPT90 Pin Are Specified)
Count Clock
TM90
Count Read Buffer
TCP90
0000H 0001H
0000H 0001H
Undefined
N
N
N
M – 1
Capture Start
M
M
M
Capture Start
CPT90
Capture Edge Detection Capture Edge Detection
Remark N = 0000H to FFFFH
M = 0000H to FFFFH
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6.4.4 16-bit timer counter 90 readout
The count value of 16-bit timer counter 90 (TM90) is read out with a 16-bit manipulation instruction.
TM90 readout is performed through a counter read buffer. The counter read buffer latches the TM90 count value. And buffer operation is pended at the CPU clock falling edge after the read signal of the TM90 lower byte rises and the count value is retained. The counter read buffer value at the retention state can be read out as the count value.
Cancellation of pending is performed at the CPU clock falling edge after the read signal of the TM90 higher byte falls.
RESET input clears TM90 to 0000H and TM90 starts freerunning.
Figure 6-11 shows the timing of 16-bit timer counter 90 readout.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during oscillation settling time.
2. Though TM90 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can also be used.
When using the 8-bit transfer instruction, execute it in direct addressing.
3. When using the 8-bit transfer instruction, execute in the order from the lower byte to the higher byte in pairs. If only the lower byte is read, the pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined count value is read.
Figure 6-11. 16-Bit Timer Counter 90 Readout Timing
CPU Clock
Count Clock
TM90
Count Read Buffer
TM90 Read Signal
0000H
0000H
0001H
0001H
N
N
N + 1
Read Signal Latch
Prohibited Period
Remark N = 0000H to FFFFH
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6.4.5 Buzzer output operation
The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output.
Table 6-4 shows the buzzer frequency.
Set the 16-bit timer counter as follows to use it for buzzer output:
•
Set P31 to output mode (PM31 = 0).
•
Reset output latch of P31 to 0.
•
Set a count clock by using TCL901 and TCL900.
•
Set BZC90 as shown in Figure 6-12.
Figure 6-12. Settings of Buzzer Output Control Register 90 for Buzzer Output Operation
BZC90 0 0 0 0
BCS902 BCS901 BCS900 BZOE90
0/1 0/1 0/1 1
Enables buzzer output
Setting of buzzer frequency (see Table 6-4)
BCS902 BCS901 BCS900
0
0
1
0
0
1
1
1
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
Table 6-4. Buzzer Frequency of 16-Bit Timer fcl = f
X
/2
2 fcl/2
4
(78.1 kHz) fcl/2 5 (39.1 kHz) fcl/2
8
(4.88 kHz) fcl/2
9
(2.44 kHz) fcl/2 10 (1.22 kHz) fcl/2
11
(610 Hz) fcl/2 12 (305 Hz) fcl/2
13
(153 Hz)
Buzzer Frequency fcl = f
X
/2
6 fcl = f
X
/2
4 fcl/2
4
(4.88 kHz) fcl/2 5 (2.44 kHz) fcl/2
8
(305 Hz) fcl/2
9
(153 Hz) fcl/2 fcl/2 fcl/2 fcl/2
4
5
8
9
(19.5 kHz)
(9.77 kHz)
(1.22 kHz)
(610 Hz) fcl/2 10 (76 Hz) fcl/2
11
(38 Hz) fcl/2 12 (19 Hz) fcl/2
13
(10 Hz) fcl/2 fcl/2 fcl/2 fcl/2
10
11
12
13
(305 Hz)
(153 Hz)
(76.3 Hz)
(38.1 Hz) fcl = f
XT fcl/2
4
(2.05 kHz) fcl/2 5 (1.02 kHz) fcl/2
8
(128 Hz) fcl/2
9
(64 Hz) fcl/2 10 (32 Hz) fcl/2
11
(16 Hz) fcl/2 12 (8 Hz) fcl/2
13
(4 Hz)
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
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6.5 Notes on 16-Bit Timer
The functions of the 16-bit timer that can be used differ depending on the selection of a count clock, operation of the CPU clock, oscillation status of the system clock, and the setting of BZOE90 (bit 0 of the buzzer output control register 90 (BZC90)).
Count
Clock f
X
/2 2 , f
X
/2 4 , f
X
/2 6 f
XT
CPU
Clock
Main
Sub
Main
Sub
Table 6-5. Operating Status of 16-Bit Timer under Each Condition
System Clock
Main Clock Subclock
Oscillation
Stop
Oscillation/ stop
Oscillation
Stop
Oscillation
Oscillation Oscillation
BZOE90
1/0
Stop
(STOP mode)
Stop
Oscillation
Oscillation
Stop
Oscillation
Stop
1
1/0
0
1
0
1
1/0
0
0
1
Capture
Ο
×
×
×
×
×
×
×
Ο
×
Ο
×
Ο
×
TM90
Read
Ο Note 1
×
×
×
×
×
Ο
×
×
×
×
×
Ο
×
Buzzer
Output
Note 2
×
Note 2
×
×
×
Ο
Ο
×
×
×
Ο
×
Ο
Timer
Output
Ο
Ο
Ο
×
×
Ο
×
×
Ο
Ο
Ο
×
Ο
×
Timer
Interrupt
Ο
Ο
Ο
×
×
Ο
×
×
Ο
Ο
Ο
×
Ο
×
Notes 1. Possible only when the CPU clock is in high-speed mode
2. Can be output when BZOE90 = 1
Cautions 1. The capture function uses f
X
/2 for control (see Figure 6-1). Therefore, the capture function cannot be used when the main system clock is stopped.
2. The read function of TM90 uses the CPU clock for control (see Figure 6-1), and reads an undefined status if the CPU clock is slower than the count clock (the value cannot be guaranteed). To read TM90, check that the count clock is the same as the CPU clock (use high-speed mode if the CPU clock is the main system clock), or select a count clock slower than the CPU clock.
3. If the subsystem clock is selected as the count clock and if BZOE90 is cleared to 0, the subsystem clock synchronized with the main system clock is selected as the count clock of
TM90 (see Figure 6-1). If oscillation of the main system clock is stopped at this time, therefore, the clock supplied to the 16-bit timer is stopped and thus the timer itself is stopped (the timer interrupt does not occur).
If the subsystem clock is selected as the count clock and if BZOE90 is set to 1, the captured value and TM90 read value are not guaranteed because the subsystem clock is not synchronized. To use the capture and TM90 read functions, therefore, clear BZOE90 to 0 (if the subsystem clock is selected as the count clock, the buzzer output, capture, and TM90 read functions cannot be used at the same time).
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To stop oscillation of the main system clock to reduce the current consumption and release HALT mode by using the timer interrupt, make the following settings:
Count clock
CPU clock
: Subsystem clock
: Subsystem clock
Main system clock : Stop oscillation
BZOE90 : 1 (buzzer output enabled)
If the setting of P31, multiplexed with the buzzer output, is "PM31 = 0, P31 = 0" at this time, the square wave of the buzzer frequency is output from P31. To disable the output of the buzzer frequency:
• Set P31 in input mode (PM31 = 1).
• If P31 cannot be set in input mode, set the value of the port latch of P31 to 1 (P31 = 1).
(In this case, a high level is output from P31.)
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[MEMO]
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7.1 Functions of 8-Bit Timer/Event Counter
The 8-bit timer/event counter has the following functions:
•
Interval timer
•
External event counter
•
Square wave output
•
PWM output
(1) 8-bit interval timer
When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any time intervals set in advance.
Table 7-1. Interval Time of 8-Bit Timer/Event Counter
Minimum Interval Time
1/f
X
(200 ns)
2 8 /f
X
(51.2
µ s)
Maximum Interval Time
2
8
/f
X
(51.2
µ s)
2 16 /f
X
(13.1 ms)
Resolution
1/f
X
(200 ns)
2 8 /f
X
(51.2
µ s)
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
(2) External event counter
The number of pulses of an externally input signal can be counted.
(3) Square wave output
A square wave of arbitrary frequency can be output.
Table 7-2. Square Wave Output Range of 8-Bit Timer/Event Counter
Minimum Pulse Width
1/f
X
(200 ns)
2
8
/f
X
(51.2
µ s)
Maximum Pulse Width
2 8 /f
X
(51.2
µ s)
2
16
/f
X
(13.1 ms)
Resolution
1/f
X
(200 ns)
2
8
/f
X
(51.2
µ s)
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
(4) PWM output
8-bit resolution PWM output can be produced.
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7.2 8-Bit Timer/Event Counter Configuration
The 8-bit timer/event counter consists of the following items of hardware.
Item
Timer counter
Register
Timer output
Control register
Table 7-3. 8-Bit Timer/Event Counter Configuration
Configuration
8 bits
×
1 (TM80)
Compare register: 8 bits
×
1 (CR80)
1 (TO80)
8-bit timer mode control register 80 (TMC80)
Port mode register 2 (PM2)
Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter
Internal Bus
TI80/P27/
TO80 f
X f
X
/2
8
8-Bit Compare
Register 80 (CR80)
Match
8-Bit Timer Counter
80 (TM80)
CLEAR
OVF
R
INV Q
S
Q
TCE80 PWME80 TCL801 TCL800TOE80
8-Bit Timer Mode Control Register 80 (TMC80)
P27
Output
Latch
Internal Bus
INTTM80
PM27
TO80/P27/TI80
(1) 8-bit compare register 80 (CR80)
A value specified in CR80 is compared with the count in 8-bit timer counter 80 (TM80). If they match, an interrupt request (INTTM80) is issued.
CR80 is set with an 8-bit memory manipulation instruction. Any value from 00H to FFH can be set.
RESET input makes CR80 undefined.
Cautions 1. Before rewriting CR80, stop the timer operation. If CR80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately.
2. Do not clear CR80 to 00H in PWM output mode (when PWME80 = 1: bit 6 of 8-bit timer mode control register 80 (TMC80)); otherwise, PWM output may not be produced normally.
(2) 8-bit timer counter 80 (TM80)
TM80 is used to count the number of pulses.
Its contents are read with an 8-bit memory manipulation instruction.
RESET input clears TM80 to 00H.
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7.3 8-Bit Timer/Event Counter Control Registers
The following two types of registers are used to control the 8-bit timer/event counter.
• 8-bit timer mode control register 80 (TMC80)
• Port mode register 2 (PM2)
(1) 8-bit timer mode control register 80 (TMC80)
TMC80 determines whether to enable or disable 8-bit timer counter 80 (TM80), specifies the count clock for
TM80, and controls the operation of the output control circuit of 8-bit timer/event counter.
TMC80 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC80 to 00H.
Figure 7-2. Format of 8-Bit Timer Mode Control Register 80
Symbol <7> <6> 5
TMC80 TCE80PWME80 0
4
0
3 2 1 <0>
0 TCL801TCL800 TOE80
Address After Reset R/W
FF53H 00H R/W
TCE80
0
1
8-Bit Timer Counter 80 Operation Control
Operation disabled (TM80 is cleared to 0.)
Operation enabled
PWME80
0 Interval timer operation mode
1 PWM output mode
Operation Mode Selection
TCL801 TCL800
0 0 f
X
(5.0 MHz)
0
1
1
1
0
1 f
X
(19.5 kHz)
Rising edge of TI80
Note
Falling edge of TI80
Note
8-Bit Timer Counter 80 Count Clock Selection
TOE80
0 Output disabled (port mode)
1 Output enabled
8-Bit Timer/Event Counter Output Control
Note When inputting a clock signal externally, timer output cannot be used.
Cautions 1. Always stop the timer before setting TMC80.
2. For PWM mode operation, TMMK80 (bit 0 of interrupt mask flag register 1 (MK1)) must be set.
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
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(2) Port mode register 2 (PM2)
PM2 specifies whether each bit of port 2 is used for input or output.
To use the TO80/P27/TI80 pin for timer output, the PM27 and P27 output latch must be reset to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Symbol
PM2
7
PM27
6
PM26
5
PM25
Figure 7-3. Format of Port Mode Register 2
4
PM24
3
PM23
2
PM22
1
PM21
0
PM20
Address After Reset
FF22H FFH
R/W
R/W
PM27
0
1
Output mode (output buffer ON)
P27 Pin Input/Output Mode Selection
Input mode (output buffer OFF)
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7.4 Operation of 8-Bit Timer/Event Counter
7.4.1 Operation as interval timer
The interval timer repeatedly generates an interrupt at time intervals specified by the count value set in 8-bit compare register 80 (CR80) in advance.
To operate the 8-bit timer/event counter as an interval timer, the settings are required in the following sequence.
<1> Disable the operation of the 8-bit timer counter 80 (TM80) (TCE80 (bit 7 of the 8-bit timer mode control register 80 (TMC80)) = 0).
<2> Set the count clock of the 8-bit timer/event counter (see Table 7-4).
<3> Set a count value in CR80.
<4> Enable the operation of TM80 (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, TM80 is cleared to 0 and continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Table 7-4 shows interval time, and Figure 7-4 shows the timing of interval timer operation.
Cautions 1. Stop the timer operation before rewriting CR80. If CR80 is rewritten while timer operation is enabled, a coincidence signal may be generated on the spot (an interrupt request will be generated if the interrupt is enabled).
2. If setting of the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use the 8-bit timer/event counter as an interval timer, therefore, perform the setting in the above sequence.
Table 7-4. Interval Time of 8-Bit Timer/Event Counter
TCL801
0
0
1
1
TCL800
0
1
0
1
Minimum Interval Time
1/f
X
(200 ns)
2
8
/f
X
(51.2
µ s)
TI80 input cycle
TI80 input cycle
Maximum Interval Time
2 8 /f
X
(51.2
µ s)
2
16
/f
X
(13.1 ms)
2
8 ×
TI80 input cycle
2 8 ×
TI80 input cycle
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
Resolution
1/f
X
(200 ns)
2
8
/f
X
(51.2
µ s)
TI80 input edge cycle
TI80 input edge cycle
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t
Count Clock
TM80 Count Value 00H 01H
CHAPTER 7 8-BIT TIMER/EVENT COUNTER
Figure 7-4. Interval Timer Operation Timing
N 00H 01H
Clear
N
N 00H 01H
Clear
N CR80 N
TCE80
Count Start
INTTM80
Interrupt Accept Interrupt Accept
TO80
Interval Time
Remark Interval time = (N + 1)
×
t
N = 00H to FFH
Interval Time Interval Time
N
N
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7.4.2 Operation as external event counter
The external event counter counts the number of external clock pulses input to the TI80/P27/TO80 pin by using
8-bit timer counter 80 (TM80).
To operate the 8-bit timer/event counter as an external event counter, the settings are required in the following sequence.
<1> Set P27 to input mode (PM27 = 1).
<2> Disable the operation of the 8-bit timer counter 80 (TM80) (TCE80 (bit 7 of the 8-bit timer mode control register 80 (TMC80)) = 0).
<3> Specify the rising or falling edge of TI80 (see Table 7-4). Disable output of TO80 (TOE80 (bit 0 of TMC80)
= 0) and PWM output (PWME80 (bit 6 of TMC80) = 0).
<4> Set a count value in CR80.
<5> Enable the operation of TM80 (TCE80 = 1).
Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80
(TM80) is incremented.
When the count value of TM80 matches the value set in CR80, TM80 is cleared to 0 and continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Figure 7-5 shows the timing of the external event counter operation (with rising edge specified).
Cautions 1. Before rewriting CR80, stop the timer operation. If CR80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately.
2. If setting of the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use the 8-bit timer/event counter as an external event counter, therefore, perform the setting in the above sequence.
Figure 7-5. External Event Counter Operation Timing (with Rising Edge Specified)
TI80 Pin Input
TM80 Count Value 00H 01H 02H 03H 04H 05H
CR80 N
TCE80
INTTM80
Remark N = 00H to FFH
N – 1 N 00H 01H 02H 03H
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7.4.3 Operation as square wave output
The 8-bit timer/event counter can generate output square waves of an arbitrary frequency at intervals specified by the count value set in 8-bit compare register 80 (CR80) in advance.
To operate 8-bit timer/event counter 80 for square wave output, the settings are required in the following sequence.
<1> Set P27 to output mode (PM27 = 0). Set 0 for the output latch of P27.
<2> Disable the operation of 8-bit timer counter 80 (TM80) (TCE80 = 0).
<3> Set a count clock for 8-bit timer/event counter (see Table 7-5), enable output of TO80 (TOE80 = 1), and disable PWM output (PWME80 = 0).
<4> Set a count value in CR80.
<5> Enable the operation of TM80 (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, the TO80 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TM80 will be cleared to 0 and resumes to count, generating an interrupt request signal (INTTM80).
Setting 0 for bit 7 (TCE80) of TMC80 clears the square-wave output to 0.
Table 7-5 shows square wave output range, and Figure 7-6 shows timing of square wave output.
Cautions 1. Before rewriting CR80, stop the timer operation. If CR80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately.
2. If setting of the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use the 8-bit timer/event counter as a square wave output, therefore, perform the setting in the above sequence.
Table 7-5. Square Wave Output Range of 8-Bit Timer/Event Counter
TCL801
0
0
TCL800
0
1
Minimum Pulse Width
1/f
X
(200 ns)
2 8 /f
X
(51.2
µ s)
Maximum Pulse Width
2
8
/f
X
(51.2
µ s)
2 16 /f
X
(13.1 ms)
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
Resolution
1/f
X
(200 ns)
2 8 /f
X
(51.2
µ s)
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Figure 7-6. Square Wave Output Timing
Count Clock
TM80 Count Value 00H 01H
CR80 N
N 00H 01H
Clear
N
TCE80
Count Start
INTTM80
Interrupt Accept
TO80 Note
Note The initial value of TO80 is low for output enable (TOE80 = 1).
N 00H
Clear
01H
N
Interrupt Accept
N
N
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7.4.4 PWM output operation
PWM output enables an interrupt to be generated repeatedly at intervals specified by the count value set in 8-bit compare register 80 (CR80) in advance.
To use the 8-bit timer/event counter for PWM output, the following settings are required.
<1> Set P27 to output mode (PM27 = 0). Set 0 for the output latch of P27.
<2> Disable the operation of 8-bit timer counter 80 (TM80) (TCE80 = 0).
<3> Set a count clock for 8-bit timer/event counter (see Table 7-4), and enable output of TO80 (TOE80 = 1) and
PWM output (PWME80 = 1).
<4> Set a count value in CR80.
<5> Enable the operation of TM80 (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, TM80 continues counting, and an interrupt request signal (INTTM80) is generated.
Cautions 1. If CR80 is rewritten during timer operation, the pulse of the first cycle may not be generated immediately after CR80 has been rewritten.
2. If setting of the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use the 8-bit timer/event counter as a
PWM output, therefore, perform the setting in the above sequence.
Figure 7-7. PWM Output Timing
Count Clock
TM80 00H 01H
• • •
M
• • •
FFH 00H 01H 02H
• • •
N N + 1 N + 2
• • •
FFH 00H 01H
• • •
N
• • • • • •
CR80 M N
TCE80
OVF
INTTM80
TO80 Note
N = 01H to FFH, M = 01H to FFH
Note The initial value of TO80 is low for output enable (TOE80 = 1).
Caution Do not set CR80 to 00H in PWM output mode. Otherwise, PWM may not be output normally.
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7.5 Notes on Using 8-Bit Timer/Event Counter
(1) Error on starting timer
An error of up to 1 clock is included in the time between the timer being started and a coincidence signal being generated. This is because 8-bit timer counter 80 (TM80) is started asynchronously to the count pulse.
Figure 7-8. Start Timing of 8-Bit Timer Counter 80
Count Pulse
TM80
Count Value
00H 01H 02H 03H 04H
Timer Start
(2) Setting of 8-bit compare register 80
8-bit compare register 80 (CR80) can be set to 00H.
Therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter.
Figure 7-9. External Event Counter Operation Timing
Tl80 Input
00H CR80
TM80
Count Value
Interrupt Request Flag
00H 00H 00H 00H
Cautions 1. Before rewriting CR80 in timer counter operation mode (PWME80 (bit 6 of the 8-bit timer mode control register 80 (TMC80) = 0), stop the timer operation. If CR80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately.
2. If CR80 is rewritten during timer operation in the PWM output operation mode
(PWME80 = 1), an illegal pulse may be generated. To rewrite CR80, therefore, stop the timer operation.
3. Do not set CR80 to 00H in PWM operation mode (when PWME80 = 1: bit 6 of 8-bit timer mode control register 80 (TMC80)); otherwise, PWM may not be output normally.
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CHAPTER 8 WATCH TIMER
8.1 Watch Timer Functions
The watch timer has the following functions:
•
Watch timer
•
Interval timer
The watch and interval timers can be used at the same time.
Figure 8-1 is a block diagram of the watch timer.
Figure 8-1. Block Diagram of Watch Timer f
X f
XT f
W f
W
2 4
Clear
9-Bit Prescaler f
W
2 5 f
W
2 6 f
2
W
7 f
W
2 8 f
W
2 9
5-Bit Counter
Clear
INTWT
INTWTI
WTM7 WTM6 WTM5 WTM4
Watch Timer Mode
Control Register (WTM)
Internal Bus
0 WTM1 WTM0
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(1) Watch timer
The 4.19-MHz main system clock or 32.768-kHz subsystem clock is used to issue an interrupt request
(INTWT) at 0.5-second intervals.
Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used instead.
(2) Interval timer
The interval timer is used to generate an interrupt request (INTWTI) at specified intervals.
2
4 ×
1/f
W
2 5 ×
1/f
W
2
6 ×
1/f
W
2
7 ×
1/f
W
2 8 ×
1/f
W
2
9 ×
1/f
W
Interval
Table 8-1. Interval Generated Using Interval Timer
At f
X
= 5.0 MHz
409.6
µ s
819.2
µ s
1.64 ms
3.28 ms
6.55 ms
13.1 ms
At f
X
= 4.19 MHz
489
µ s
978
µ s
1.96 ms
3.91 ms
7.82 ms
15.6 ms
At f
XT
= 32.768 kHz
488
µ s
977
µ s
1.95 ms
3.91 ms
7.81 ms
15.6 ms
Remarks 1. f
W
: Watch timer clock frequency (f
X
/2
7
or f
XT
)
2. f
X
: Main system clock oscillation frequency
3. f
XT
: Subsystem clock oscillation frequency
8.2 Watch Timer Configuration
The watch timer consists of the following items of hardware.
Item
Counter
Prescaler
Control register
Table 8-2. Watch Timer Configuration
Configuration
5 bits
×
1
9 bits
×
1
Watch timer mode control register (WTM)
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CHAPTER 8 WATCH TIMER
8.3 Watch Timer Control Register
The watch timer mode control register (WTM) is used to control the watch timer.
• Watch timer mode control register (WTM)
WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled.
WTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WTM to 00H.
Figure 8-2. Format of Watch Timer Mode Control Register
Symbol
WTM
7
WTM7
6
WTM6
5
WTM5
4
WTM4
3
0
2
0
1
WTM1
0
WTM0
Address After Reset R/W
FF4AH 00H R/W
WTM7
0
1 f
X
/2
7 (39.1 kHz) f
XT
(32.768 kHz)
Watch Timer Count Clock Selection
WTM6
0
0
0
WTM5
0
0
1
0
1
1
0
1 0
Other than above
1
1
0
WTM4
0
1
0
Prescaler Interval Selection
2 4 /f
W
2 5 /f
W
2 6 /f
W
2 7 /f
W
2 8 /f
W
2 9 /f
W
Not to be set
WTM1
0
1
Cleared after stop
Started
Control of 5-Bit Counter Operation
WTM0
0
1
Watch Timer Operation
Operation disabled (both prescaler and timer cleared)
Operation enabled
Remarks 1. f
W
: Watch timer clock frequency (f
X
/2
7
or f
XT
)
2. f
X
: Main system clock oscillation frequency
3. f
XT
: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
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8.4 Watch Timer Operation
8.4.1 Operation as watch timer
The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals.
The watch timer is used to generate an interrupt request at specified intervals.
By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.
Only the watch timer can be started form zero seconds by clearing WTM1 to 0 when the interval timer and watch timer operate at the same time. In this case, however, an error of up to 2
9 ×
1/f
W
seconds may occur in the overflow
(INTWT) after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0.
8.4.2 Operation as interval timer
The interval timer is used to repeatedly generate an interrupt request at the interval specified by a count value set in advance.
The interval can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).
Table 8-3. Interval Generated Using Interval Timer
WTM6 WTM5 WTM4
0 0 0
0
0
0
0
1
1
1
0
1
1
1
0
0
Other than above
0
1
Interval
2
4 ×
1/f
W
2
5 ×
1/f
W
2 6 ×
1/f
W
2
7 ×
1/f
W
2
8 ×
1/f
W
2 9 ×
1/f
W
Not to be set
At f
X
= 5.0 MHz
409.6
µ s
819.2
µ s
1.64 ms
3.28 ms
6.55 ms
13.1 ms
At f
XT
= 32.768 kHz
488
µ s
977
µ s
1.95 ms
3.91 ms
7.81 ms
15.6 ms
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. f
W
: Watch timer clock frequency (f
X
/2
7
or f
XT
)
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Figure 8-3. Watch Timer/Interval Timer Operation Timing
5-Bit Counter
0H
Start
Overflow Overflow
Count Clock f
W
/2 9
Watch Timer
Interrupt
INTWT
Interval Timer
Interrupt
INTWTI
Watch Timer Interrupt Time (0.5 s) Watch Timer Interrupt Time (0.5 s)
Interval
Timer (T)
T
Remarks 1. f
W
: Watch timer clock frequency
2. The parenthesized values apply to operation at f
W
= 32.768 kHz.
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CHAPTER 9 WATCHDOG TIMER
9.1 Watchdog Timer Functions
The watchdog timer has the following functions:
•
Watchdog timer
•
Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a non-maskable interrupt or a RESET signal can be generated.
Table 9-1. Inadvertent Loop Detection Time of Watchdog Timer
At f
X
= 5.0 MHz Inadvertent Loop Detection Time
2
11 ×
1/f
X
2
13 ×
1/f
X
2 15 ×
1/f
X
2
17 ×
1/f
X
410
µ s
1.64 ms
6.55 ms
26.2 ms f
X
: Main system clock oscillation frequency
(2) Interval timer
The interval timer generates an interrupt at an arbitrary interval set in advance.
Table 9-2. Interval Time
At f
X
= 5.0 MHz Interval
2 11 ×
1/f
X
2
13 ×
1/f
X
2
15 ×
1/f
X
2 17 ×
1/f
X
410
µ s
1.64 ms
6.55 ms
26.2 ms f
X
: Main system clock oscillation frequency
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CHAPTER 9 WATCHDOG TIMER
9.2 Watchdog Timer Configuration
The watchdog timer consists of the following items of hardware.
Item
Control register
Table 9-3. Configuration of Watchdog Timer
Configuration
Timer clock selection register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 9-1. Block Diagram of Watchdog Timer
Internal Bus f
X
2 4 f
X
2 6
Prescaler f
X
2 8 2 f
X
10
7-Bit Counter
Clear
Control
Circuit
TMIF4
TMMK4
3
INTWDT
Maskable
Interrupt Request
RESET
INTWDT
Non-Maskable
Interrupt Request
TCL22 TCL21 TCL20
Timer Clock Selection Register 2
(TCL2)
RUN WDTM4 WDTM3
Watchdog Timer Mode Register (WDTM)
Internal Bus
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CHAPTER 9 WATCHDOG TIMER
9.3 Watchdog Timer Control Registers
The following two types of registers are used to control the watchdog timer.
• Timer clock selection register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock selection register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Symbol
TCL2
7
0
6
0
Figure 9-2. Format of Timer Clock Selection Register 2
5
0
4
0
3
0
2
TCL22
1 0
TCL21 TCL20
Address After Reset R/W
FF42H 00H R/W
TCL22
0
0
1
TCL21
0
1
0
TCL20
0
0
0
1 1
Other than above
0
Watchdog Timer Count Clock Selection f
X
/2
4
(312.5 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
10
(4.88 kHz)
Not to be set
2
11
/f
X
2
13
/f
X
(1.64 ms)
2
15
/f
X
(6.55 ms)
2
17
/f
X
(26.2 ms)
Interval
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
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(2) Watchdog timer mode register (WDTM)
This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Symbol
WDTM
<7>
RUN
6
0
Figure 9-3. Format of Watchdog Timer Mode Register
5
0
4 3
WDTM4 WDTM3
2
0
1
0
0
0
Address After Reset R/W
FFF9H 00H R/W
RUN
0
1
Watchdog Timer Operation Selection Note 1
Stops counting.
Clears counter and starts counting.
WDTM4 WDTM3
0 0
0
1
1
0
1 1
Operation stop
Watchdog Timer Operation Mode Selection
Note 2
Interval timer mode (Generates a maskable interrupt upon overflow occurrence.) Note 3
Watchdog timer mode 1 (Generates a non-maskable interrupt upon overflow occurrence.)
Watchdog timer mode 2 (Starts reset operation upon overflow occurrence.)
Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.
3. The watchdog timer starts operations as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock selection register 2 (TCL2).
2. To set watchdog timer mode 1 or 2, set TMMK4 (bit 0 of interrupt mask flag register 0
(MK0)) to 1 after confirming TMIF4 (bit 0 of interrupt request flag register 0 (IF0)) being set to 0. When watchdog timer mode 1 or 2 is selected with TMIF4 set to 1, a nonmaskable interrupt is generated upon the completion of rewriting WDTM.
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9.4 Watchdog Timer Operation
9.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1.
The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2
(TCL20 to TCL22) of timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the inadvertent loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the watchdog timer before executing the STOP instruction.
Cautions 1. The actual inadvertent loop detection time may be up to 0.8% shorter than the set time.
2. When the subsystem clock is selected as the CPU clock, watchdog timer count operation is stopped.
Table 9-4. Inadvertent Loop Detection Time of Watchdog Timer
TCL22 TCL21 TCL20 Inadvertent Loop Detection Time
0
0
1
1
0
1
0
1
0
0
0
0
2
11 ×
1/f
X
2
13 ×
1/f
X
2 15 ×
1/f
X
2
17 ×
1/f
X f
X
: Main system clock oscillation frequency
410
µ s
At f
X
= 5.0 MHz
1.64 ms
6.55 ms
26.2 ms
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CHAPTER 9 WATCHDOG TIMER
9.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance.
Select a count clock (or interval) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2
(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.
In interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the interval timer before executing the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval timer mode is not set, unless a RESET signal is input.
2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set.
Table 9-5. Interval Generated Using Interval Timer
TCL22 TCL21 TCL20 Interval
0
0
1
1
0
1
0
1
0
0
0
0
2
11 ×
1/f
X
2
13 ×
1/f
X
2 15 ×
1/f
X
2
17 ×
1/f
X f
X
: Main system clock oscillation frequency
410
µ s
At f
X
= 5.0 MHz
1.64 ms
6.55 ms
26.2 ms
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CHAPTER 10 SERIAL INTERFACE 20
10.1 Serial Interface 20 Functions
Serial interface 20 has the following three modes.
•
Operation stop mode
•
Asynchronous serial interface (UART) mode
•
3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.
(2) Asynchronous serial interface (UART) mode
This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex communication.
Serial interface 20 contains a UART-dedicated baud rate generator, enabling communication over a wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the clock input to the ASCK20 pin.
(3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data lines (SI20 and SO20).
As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time for data transmission than asynchronous serial interface mode.
Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the
MSB or LSB, serial interface 20 can be connected to any device regardless of whether that device is designed for MSB-first or LSB-first transmission.
3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75X/XL, 78K, and 17K Series devices.
10.2 Serial Interface 20 Configuration
Serial interface 20 consists of the following items of hardware.
Register
Item
Control register
Table 10-1. Configuration of Serial Interface 20
Configuration
Transmission shift register 20 (TXS20)
Reception shift register 20 (RXS20)
Reception buffer register 20 (RXB20)
Serial operation mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
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SI20/P22/
RxD20
SO20/P21/
TxD20
SS20/P23
SCK20/P20/
ASCK20
Figure 10-1. Block Diagram of Serial Interface 20
Serial Operation Mode
Register 20 (CSIM20)
CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20
Reception Buffer
Register 20 (RXB20)
Internal Bus
Asynchronous Serial Interface
Status Register 20 (ASIS20)
PE20 FE20 OVE20
Asynchronous Serial Interface
Mode Register 20 (ASIM20)
TXE20 RXE20 PS201 PS200 CL20 SL20
Switching of the First Bit
Transmission Shift
Register 20 (TXS20) Transmission
Shift Clock
Reception Shift
Register 20 (RXS20)
Selector
Port Mode
Register (PM21)
Reception
Shift Clock
Data Phase
Control
Parity Operation
Stop Bit Addition
4
Transmission Data Counter
Parity Operation
Stop Bit Addition
SL20, CL20, PS200, PS201
Reception Data Counter
Reception Enabled
Reception Clock
Start Bit
Detection
Detection Clock
Reception Detected
Transmission and Reception
Clock Control Baud Rate
Generator Note
4
CSIE20
DAP20
CSIE20
CSCK20 f
X
/2 to f
X
/2
8
CSIE20
Clock Phase
Control
CSCK20
TPS203 TPS202 TPS201 TPS200
Internal Clock Output
Baud Rate Generator
Control Register 20 (BRGC20)
External Clock Input
Internal Bus
INTST20
INTSR20/INTCSI20
Note See Figure 10-2 for the configuration of the baud rate generator.
Reception Detection Clock
Transmission Shift Clock
Figure 10-2. Block Diagram of Baud Rate Generator 20
1/2
Transmission
Clock Counter
1/2 Reception Shift Clock
TXE20
RXE20
CSIE20
Reception Detected
Reception
Clock Counter f
X
/2 f
X
/2 2 f
X
/2
3 f
X
/2 4 f
X
/2 5 f
X
/2
6 f
X
/2 7 f
X
/2 8
SCK20/ASCK20/P20
4
TPS203 TPS202 TPS201 TPS200
Baud Rate Generator Control
Register 20 (BRGC20)
Internal Bus
CHAPTER 10 SERIAL INTERFACE 20
(1) Transmission shift register 20 (TXS20)
TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data to TXS20 triggers transmission.
TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS20 to FFH.
Caution Do not write to TXS20 during transmission.
TXS20 and reception buffer register 20 (RXB20) are mapped at the same address, such that any attempt to read from TXS20 results in a value being read from RXB20.
(2) Reception shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one entire byte has been received, RXS20 feeds the reception data to reception buffer register 20 (RXB20).
RXS20 cannot be manipulated directly by a program.
(3) Reception buffer register 20 (RXB20)
RXB20 holds a reception data. A new reception data is transferred from reception shift register 20 (RXS20) every 1-byte data reception.
When the data length is seven bits, the reception data is sent to bits 0 to 6 of RXB20, in which the MSB is always fixed to 0.
RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written.
RESET input makes RXB20 undefined.
Caution RXB20 and transmission shift register 20 (TXS20) are mapped at the same address, such that any attempt to write to RXB20 results in a value being written to TXS20.
(4) Transmission control circuit
The transmission control circuit controls transmission. For example, it adds start, parity, and stop bits to the data in transmission shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20 (ASIM20).
(5) Reception control circuit
The reception control circuit controls reception according to the setting of asynchronous serial interface mode register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected, asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error.
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10.3 Serial Interface 20 Control Registers
Serial interface 20 is controlled by the following registers.
•
Serial operation mode register 20 (CSIM20)
•
Asynchronous serial interface mode register 20 (ASIM20)
•
Asynchronous serial interface status register 20 (ASIS20)
•
Baud rate generator control register 20 (BRGC20)
(1) Serial operation mode register 20 (CSIM20)
CSIM20 is set when serial interface 20 is used in 3-wire serial I/O mode.
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Figure 10-3. Format of Serial Operation Mode Register 20
Symbol <7> 6 5
CSIM20 CSIE20 SSE20 0
4 3 2 1 0
0 DAP20 DIR20 CSCK20 CKP20
Address After Reset
FF72H 00H
R/W
R/W
CSIE20
0
1
Operation disabled
Operation enabled
3-Wire Serial I/O Mode Operation Control
SSE20
0
1
SS20 Pin Selection
Not used
Used
Function of SS20/P23 Pin
Port function
0
1
Communication Status
Communication enabled
Communication enabled
Communication disabled
DAP20
0
1
3-Wire Serial I/O Mode Data Phase Selection
Outputs at the falling edge of SCK20.
Outputs at the rising edge of SCK20.
DIR20
0 MSB
1 LSB
First-Bit Specification
CSCK20
0
3-Wire Serial I/O Mode Clock Selection
External clock input to the SCK20 pin
1 Output of the dedicated baud rate generator
CKP20
0
3-Wire Serial I/O Mode Clock Phase Selection
Clock is low active, and SCK20 is at high level in the idle state.
1 Clock is high active, and SCK20 is at low level in the idle state.
Cautions 1. Bits 4 and 5 must all be set to 0.
2. CSIM20 must be cleared to 00H, if UART mode is selected.
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CHAPTER 10 SERIAL INTERFACE 20
(2) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set when serial interface 20 is used in asynchronous serial interface mode.
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Figure 10-4. Format of Asynchronous Serial Interface Mode Register 20
Symbol <7> <6> 5 4 3 2
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
1
0
0
0
Address After Reset R/W
FF70H 00H R/W
TXE20
0 Transmit operation stop
1 Transmit operation enable
Transmit Operation Control
RXE20
0
1
Receive operation stop
Receive operation enable
Receive Operation Control
PS201 PS200
0
0
0
1
1
1
0
1
Parity Bit Specification
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (No parity error is generated).
Odd parity
Even parity
CL20
0
1
7 bits
8 bits
Transmit Data Character Length Specification
SL20
0
1
1 bit
2 bits
Transmit Data Stop Bit Length
Cautions 1. Bits 0 and 1 must all be set to 0.
2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switch operating modes after halting serial transmit/receive operation.
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Table 10-2. Serial Interface 20 Operating Mode Settings
(1) Operation stop mode
TXE20 RXE20 CSIE20 DIR20 CSCK20
0
ASIM20
0 0
CSIM20
× ×
PM22
×
Note 1
P22
×
Other than above
Note 1
PM21
×
Note 1
P21
×
Note 1
PM20
×
Note 1
P20
×
Note 1
First
Bit
Shift
Clock
P22/SI20/
RxD20 Pin
Function
− −
Not to be set
P22
P21/SO20/
TxD20 Pin
Function
P21
P20/SCK20/
ASCK20 Pin
Function
P20
(2) 3-wire serial I/O mode
ASIM20 CSIM20
TXE20 RXE20 CSIE20 DIR20 CSCK20
0 0 1 0 0
PM22
×
Note 2
P22
×
Note 2
PM21
0
P21
1
PM20
1
P20
×
First
Bit
Shift
Clock
P22/SI20/
RxD20 Pin
Function
MSB
External
SI20 Note 2 clock
P21/SO20/
TxD20 Pin
Function
P20/SCK20/
ASCK20 Pin
Function
SO20
(CMOS output)
SCK20 input
1 0 1 Internal clock
1 1 0
1
Other than above
1
0
×
1
LSB External clock
Internal clock
Not to be set
SCK20 output
SCK20 input
SCK20 output
(3) Asynchronous serial interface mode
1
ASIM20
0 0
CSIM20
TXE20 RXE20 CSIE20 DIR20 CSCK20
0 0
PM22
×
Note 1
P22
×
Note 1
PM21
0
P21
1
PM20
1
P20
×
First
Bit
Shift
Clock
P22/SI20/
RxD20 Pin
Function
LSB
External
P22 clock
×
Note 1
×
Note 1
Internal clock
0 1 0 0 0 1
× × Note 1 × Note 1
×
1
Note 1
×
×
Note 1
External clock
Internal clock
RxD20
P21/SO20/
TxD20 Pin
Function
P20/SCK20/
ASCK20 Pin
Function
TxD20
(CMOS output)
ASCK20 input
P20
P21 ASCK20 input
P20
1 1 0 0 0 1
×
0 1 1
×
External clock
TxD20
(CMOS output)
ASCK20 input
× Note 1 × Note 1
P20
Other than above
Internal clock
Not to be set
Notes 1. These pins can be used for port functions.
2. When only transmission is used, this pin can be used as P22 (CMOS input/output).
Remark
×
: Don't care.
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(3) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set.
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS20 are undefined in 3-wire serial I/O mode.
RESET input clears ASIS20 to 00H.
Symbol
ASIS20
7
0
Figure 10-5. Format of Asynchronous Serial Interface Status Register 20
6
0
5
0
4
0
3
0
2 1 0
PE20 FE20 OVE20
Address After Reset R/W
FF71H 00H R
PE20
0 No parity error has occurred.
1
Parity Error Flag
A parity error has occurred (parity mismatch in transmission data).
FE20
0
1
Flaming Error Flag
No framing error has occurred.
A framing error has occurred (no stop bit detected).
Note 1
OVE20
0
1
Overrun Error Flag
No overrun error has occurred.
An overrun error has occurred.
Note 2
(Before data was read from the reception buffer register, the subsequent receive operation was completed.)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit.
2. Be sure to read reception buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error is generated.
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(4) Baud rate generator control register 20 (BRGC20)
BRGC20 is used to specify the serial clock for serial interface 20.
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Figure 10-6. Format of Baud Rate Generator Control Register 20
Symbol
BRGC20
7 6 5 4 3
TPS203 TPS202 TPS201 TPS200 0
2
0
1
0
0
0
Address After Reset R/W
FF73H 00H R/W
TPS203 TPS202 TPS201 TPS200
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 0
Other than above
0
1
0
1
0
1
0
1
0
3-Bit Counter Source Clock Selection f
X
/2 (2.5 MHz) f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz)
External clock input to the ASCK20 pin Note
Not to be set
Note An external clock can be used only in UART mode.
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 during operation at f
X
= 5.0 MHz because the resulting baud rate exceeds the rated range.
3. When the external input clock is selected, set P20 to input mode (PM20 (bit 0 of port mode register 2 (PM2)) = 1).
Remarks 1. f
X
: Main system clock oscillation frequency
2. n : Value determined by setting TPS200 through TPS203 (1
≤
n
≤
8)
3. The parenthesized values apply to operation at f
X
= 5.0 MHz.
7
8
5
6
n
3
4
1
2
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The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK20 pin.
(a) Generation of baud rate transmit/receive clock form system clock
The transmit/receive clock is generated by scaling the system clock. The baud rate of a clock generated from the system clock is estimated by using the following expression.
f
X
[Baud rate] = [Hz]
2 n + 1 ×
8 f
X
: System clock oscillation frequency n : Value determined by values of TPS200 through TPS203 as shown in Figure 10-6 (2 ≤ n ≤ 8)
Table 10-3. Example of Relationships between System Clock and Baud Rate
Baud Rate (bps) n BRGC20 Set Value Error (%) f
X
= 5.0 MHz
1.73
f
X
= 4.9152 MHz
0 1,200
2,400
4,800
9,600
19,200
38,400
76,800
6
5
4
3
2
8
7
70H
60H
50H
40H
30H
20H
10H
Caution Do not select n = 1 during operation at f
X
= 5.0 MHz because the resulting baud rate exceeds the rated range.
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(b) Generation of baud rate transmit/receive clock from external clock input from ASCK20 pin
The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input from the ASCK20 pin is estimated by using the following expression.
f
ASCK
[Baud rate] = [Hz]
16 f
ASCK
: Frequency of clock input from the ASCK20 pin
Table 10-4. Relationships between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
150
300
600
1,200
2,400
4,800
9,600
19,200
31,250
38,400
ASCK20 Pin Input Frequency (kHz)
1.2
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
500.0
614.4
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10.4 Serial Interface 20 Operation
Serial interface 20 provides the following three types of modes.
•
Operation stop mode
•
Asynchronous serial interface (UART) mode
•
3-wire serial I/O mode
10.4.1 Operation stop mode
In operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The
P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode is set by serial operation mode register 20 (CSIM20) and asynchronous serial interface mode register 20 (ASIM20).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Symbol
CSIM20
<7> 6
CSIE20 SSE20
5
0
4
0
3
DAP20
2 1 0
DIR20 CSCK20 CKP20
Address After Reset R/W
FF72H 00H R/W
CSIE20
0
1
Operation disabled
Operation enabled
3-Wire Serial I/O Mode Operation Control
Caution Bits 4 and 5 must all be set to 0.
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Symbol
ASIM20
<7> <6>
TXE20 RXE20
5
PS201
4
PS200
3
CL20
2
SL20
1
0
0
0
Address After Reset R/W
FF70H 00H R/W
TXE20
0
1
Transmit operation stop
Transmit operation enable
Transmit Operation Control
RXE20
0
1
Receive operation stop
Receive operation enable
Receive Operation Control
Caution Bits 0 and 1 must all be set to 0.
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10.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible.
This device incorporates a UART-dedicated baud rate generator that enables communications at a desired baud rate from many options. In addition, the baud rate can also be defined by dividing the clock input to the ASCK20 pin.
The UART-dedicated baud rate generator also can output the 31.25-kbps baud rate that complies with the MIDI standard.
(1) Register setting
UART mode is set by serial operation mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), and baud rate generator control register 20 (BRGC20).
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(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Set CSIM20 to 00H when UART mode is selected.
Symbol <7> 6 5
CSIM20 CSIE20 SSE20 0
4 3 2 1 0
0 DAP20 DIR20 CSCK20 CKP20
Address After Reset
FF72H 00H
R/W
R/W
CSIE20
0
1
Operation disabled
Operation enabled
3-Wire Serial I/O Mode Operation Control
SSE20
0
1
SS20 Pin Selection
Not used
Used
Function of SS20/P23 Pin
Port function
0
1
Communication Status
Communication enabled
Communication enabled
Communication disabled
DAP20
0
1
3-Wire Serial I/O Mode Data Phase Selection
Outputs at the falling edge of SCK20.
Outputs at the rising edge of SCK20.
DIR20
0 MSB
1 LSB
First-Bit Specification
CSCK20
0
3-Wire Serial I/O Mode Clock Selection
External clock input to the SCK20 pin
1 Output of the dedicated baud rate generator
CKP20
0
3-Wire Serial I/O Mode Clock Phase Selection
Clock is low active, and SCK20 is high level in the idle state.
1 Clock is high active, and SCK20 is low level in the idle state.
Caution Bits 4 and 5 must all be set to 0.
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(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Symbol
ASIM20
<7> <6>
TXE20 RXE20
5
PS201
4
PS200
3
CL20
2
SL20
1
0
0
0
Address After Reset R/W
FF70H 00H R/W
TXE20
0
1
Transmit operation stop
Transmit operation enable
RXE20
0
1
Receive operation stop
Receive operation enable
Transmit Operation Control
Receive Operation Control
PS201
0
0
1
1
PS200
0
1
0
1
Parity Bit Specification
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception. (No parity error is generated.)
Odd parity
Even parity
CL20
0
1
7 bits
8 bits
Character Length Specification
SL20
0
1
1 bit
2 bits
Transmit Data Stop Bit Length Specification
Cautions 1.
Bits 0 and 1 must all be set to 0.
2.
Switch operating modes after halting serial transmit/receive operation.
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Symbol
ASIS20
(c) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS20 to 00H.
7
0
6
0
5
0
4
0
3
0
2
PE20
1
FE20
0
OVE20
Address After Reset R/W
FF71H 00H R
PE20
0
1
Parity Error Flag
Parity error not generated
Parity error generated (when the parity of transmit data does not match)
FE20
0
1
Flaming Error Flag
Framing error not generated
Framing error generated (when stop bit is not detected) Note 1
OVE20
0
1
Overrun Error Flag
Overrun error not generated
Overrun error generated Note 2
(when the next receive operation is completed before the data is read from the reception buffer register)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit.
2. Be sure to read reception buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error is generated.
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(d) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Symbol
BRGC20
7 6 5 4
TPS203 TPS202 TPS201 TPS200
3
0
2
0
1
0
0
0
Address After Reset
FF73H 00H
R/W
R/W
0
0
0
0
TPS203
0
0
0
0
1
TPS202 TPS201 TPS200
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
Other than above
0
1
0
1
0
1
0
3-Bit Counter Source Clock Selection f
X
/2 (2.5 MHz) f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz)
External clock input to ASCK20 pin
Not to be set n
7
8
-
5
6
3
4
1
2
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during communication operation.
2.
Be sure not to select n = 1 during an operation at f
X
= 5.0 MHz because the resulting baud rate exceeds the rated range.
3.
When the external input clock is selected, set port mode register 2 (PM2) to input mode.
Remarks 1. f
X
: Main system clock oscillation frequency
2. n : Value determined by setting TPS200 through TPS203 (1
≤
n
≤
8)
3. The parenthesized values apply to operation at f
X
= 5.0 MHz.
The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK20 pin.
(i) Generation of baud rate transmit/receive clock from system clock
The transmit/receive clock is generated by scaling the system clock. The baud rate of a clock generated from the system clock is estimated by using the following expression.
f
X
[Baud rate] = [Hz]
2 n + 1 ×
8 f
X
: Main system clock oscillation frequency n : Value determined by setting TPS200 through TPS203 as shown in the above table (2
≤
n
≤
8)
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Table 10-5. Example of Relationships between System Clock and Baud Rate
Baud Rate (bps) n BRGC20 Set Value Error (%) f
X
= 5.0 MHz
1.73
f
X
= 4.9152 MHz
0 1,200
2,400
4,800
9,600
19,200
38,400
76,800
3
2
5
4
8
7
6
70H
60H
50H
40H
30H
20H
10H
Caution Do not select n = 1 during operation at f
X
= 5.0 MHz because the resulting baud rate exceeds the rated range.
(ii) Generation of baud rate transmit/receive clock from external clock input from ASCK20 pin
The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input from the ASCK20 pin is estimated by using the following expression.
f
ASCK
[Baud rate] = [Hz]
16 f
ASCK
: Frequency of clock input from the ASCK20 pin
Table 10-6. Relationships between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
150
300
600
1,200
2,400
4,800
9,600
19,200
31,250
38,400
ASCK20 Pin Input Frequency (kHz)
76.8
153.6
307.2
500.0
614.4
1.2
2.4
4.8
9.6
19.2
38.4
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(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 10-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s).
The specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out with asynchronous serial interface mode register 20 (ASIM20).
Figure 10-7. Asynchronous Serial Interface Transmit/Receive Data Format
One Data Frame
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Stop Bit
•
Start bits ................... 1 bit
•
Character bits............ 7 bits/8 bits
•
Parity bits .................. Even parity/odd parity/0 parity/no parity
•
Stop bit(s).................. 1 bit/2 bits
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0".
The serial transfer rate is selected by ASIM20 and baud rate generator control register 20 (BRGC20).
If a serial data receive error is generated, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (ASIS20).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit
(odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
••••
At transmission
The parity bit is determined so that the number of bits with a value of "1" in the transmit data including the parity bit may be even. The parity bit value should be as follows.
The number of bits with a value of "1" is an odd number in transmit data : 1
The number of bits with a value of "1" is an even number in transmit data : 0
••••
At reception
The number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is odd, a parity error is generated.
(ii) Odd parity
••••
At transmission
Conversely to the even parity, the parity bit is determined so that the number of bits with a value of "1" in the transmit data including the parity bit may be odd. The parity bit value should be as follows.
The number of bits with a value of "1" is an odd number in transmit data : 0
The number of bits with a value of "1" is an even number in transmit data : 1
••••
At reception
The number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is even, a parity error is generated.
(iii) 0 parity
When transmitting, the parity bit is set to "0" irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective of whether the parity bit is set to "0" or "1".
(iv) No parity
A parity bit is not added to the transmit data.
At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error is not generated.
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(c) Transmission
A transmit operation is started by writing transmit data to transmission shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated.
Figure 10-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
TxD20 (Output) D0 D1 D2 D6 D7 Parity
STOP
START
INTST20
TxD20 (Output)
(b) Stop bit length: 2
START
D0 D1 D2 D6 D7 Parity STOP
INTST20
Caution Do not rewrite to asynchronous serial interface mode register 20 (ASIM20) during a transmit operation. If the ASIM20 register is rewritten to during transmission, subsequent transmission may not be performed (the normal state is restored by
RESET input).
It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by INTST20.
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(d) Reception
When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set to 1, a receive operation is enabled and sampling of the RxD20 pin input is performed.
RxD20 pin input sampling is performed using the serial clock specified by ASIM20.
When the RxD20 pin input becomes low, the 3-bit counter starts counting, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
If the RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to reception buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated.
If an error is generated, the receive data in which the error was generated is still transferred to RXB20, and INTSR20 is generated.
If the RXE20 bit is reset to 0 during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are not changed, and INTSR20 is not generated.
Figure 10-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
RxD20 (Input) D0 D1 D2 D6 D7 Parity
STOP
START
INTSR20
Caution Be sure to read reception buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely.
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(e) Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register
20 (ASIS20). Receive error causes are shown in Table 10-7.
It is possible to determine what kind of error was generated during reception by reading the contents of
ASIS20 in the reception error interrupt servicing (see Figures 10-9 and 10-10).
The contents of ASIS20 are reset to 0 by reading reception buffer register 20 (RXB20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set).
Receive Errors
Parity error
Framing error
Overrun error
Table 10-7. Receive Error Causes
Cause
Transmission-time parity and reception data parity do not match.
Stop bit not detected
Reception of next data is completed before data is read from reception buffer register.
RxD20 (Input)
START
Figure 10-10. Receive Error Timing
(a) Parity error generated
D0 D1 D2 D6 D7 Parity
STOP
INTSR20
RxD20 (Input)
(b) Framing error or overrun error generated
D0 D1 D2 D6 D7 Parity
STOP
START
INTSR20
Cautions 1. The contents of the ASIS20 register are reset to 0 by reading reception buffer register 20 (RXB20) or receiving the next data. To ascertain the error contents, read ASIS20 before reading RXB20.
2. Be sure to read reception buffer register 20 (RXB20) even if a receive error is generated. If RXB20 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely.
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(3) Cautions related to UART mode
(a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmission shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission.
(b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during reception, reception buffer register 20 (RXB20) and the receive completion interrupt (INTSR20) are as follows.
RxD20 Pin Parity
RXB20
INTSR20
<1> <3>
<2>
When RXE20 is set to 0 at a time indicated by <1>, RXB20 holds the previous data and INTSR20 is not generated.
When RXE20 is set to 0 at a time indicated by <2>, RXB20 renews the data and INTSR20 is not generated.
When RXE20 is set to 0 at a time indicated by <3>, RXB20 renews the data and INTSR20 is generated.
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10.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc.
Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input
(SI20).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), and baud rate generator control register 20
(BRGC20).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Symbol <7> 6 5
CSIM20 CSIE20 SSE20 0
4 3 2 1 0
0 DAP20 DIR20 CSCK20 CKP20
Address After Reset
FF72H 00H
R/W
R/W
CSIE20
0 Operation disabled
1 Operation enabled
3-Wire Serial I/O Mode Operation Control
SSE20
0
1
Not used
Used
SS20 Pin Selection Function of SS20/P23 Pin
Port function
0
1
Communication Status
Communication enabled
Communication enabled
Communication disabled
DAP20
0
3-Wire Serial I/O Mode Data Phase Selection
Outputs at the falling edge of SCK20.
1 Outputs at the rising edge of SCK20.
DIR20
0
1
MSB
LSB
First-Bit Specification
CSCK20
0
3-Wire Serial I/O Mode Clock Selection
External clock input to the SCK20 pin
1 Output of the dedicated baud rate generator
CKP20
0
1
3-Wire Serial I/O Mode Clock Phase Selection
Clock is low active, and SCK20 is at high level in the idle state.
Clock is high active, and SCK20 is at low level in the idle state.
Caution Bits 4 and 5 must all be set to 0.
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(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H.
Symbol
ASIM20
<7> <6>
TXE20 RXE20
5
PS201
4
PS200
3
CL20
2
SL20
1
0
0
0
Address After Reset R/W
FF70H 00H R/W
TXE20
0
1
Transmit operation stop
Transmit operation enable
RXE20
0
1
Receive operation stop
Receive operation enable
Transmit Operation Control
Receive Operation Control
PS201
0
0
1
1
PS200
0
1
0
1
Parity Bit Specification
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception. (No parity error is generated.)
Odd parity
Even parity
CL20
0
1
7 bits
8 bits
Character Length Specification
SL20
0
1
1 bit
2 bits
Transmit Data Stop Bit Length Specification
Cautions 1. Bits 0 and 1 must all be set to 0.
2. Switch operating modes after halting serial transmit/receive operation.
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(c) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Symbol
BRGC20
7 6 5 4
TPS203 TPS202 TPS201 TPS200
3
0
2
0
1
0
0
0
Address After Reset R/W
FF73H 00H R/W
0
0
0
0
TPS203
0
0
0
0
TPS202
0
0
0
0
1
1
1
1
TPS201 TPS200
0
0
1
1
0
0
1
1
Other than above
0
1
0
1
0
1
0
1
3-Bit Counter Source Clock Selection f
X
/2 (2.5 MHz) f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz)
Not to be set n
5
6
7
3
4
1
2
8
Cautions 1. When writing to BRGC20 is performed during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during communication operation.
2. Be sure not to select n = 1 during an operation at f
X
= 5.0 MHz because the resulting baud rate exceeds the rated range.
3. When the external input clock is selected, set port mode register 2 (PM2) to input mode.
Remarks 1. f
X
: Main system clock oscillation frequency
2. n : Value determined by setting TPS200 through TPS203 (1
≤
n
≤
8)
3. The parenthesized values apply to operation at f
X
= 5.0 MHz.
If the internal clock is used as the serial clock for 3-wire serial I/O mode, set bits TPS200 to TPS203 to set the frequency of the serial clock. To obtain the frequency to be set, use the following expression.
When an external serial clock is used, setting BRGC20 is not necessary.
f
X
Serial clock frequency = [Hz]
2 n + 1 f
X
: Main system clock oscillation frequency n : Value determined by setting TPS200 through TPS203 as shown in the above table (1
≤
n
≤
8)
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(2) Communication operation
In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock.
Transmission shift register 20 (TXS20/SIO20) and reception shift register 20 (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the
SO20 latch and output from the SO20 pin. Also, receive data input to the SI20 pin is latched in reception buffer register 20 (RXB20/SIO20) on the rise of SCK20.
At the end of an 8-bit transfer, the operation of TXS20/SIO20 and RXS20 stops automatically, and the interrupt request signal (INTCSI20) is generated.
Figure 10-11. 3-Wire Serial I/O Mode Timing (1/7)
(i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
SIO20
Write
SCK20
SO20 Note
1 2 3 4 5 6 7 8
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
INTCSI20
Note The value of the last bit previously output is output.
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Figure 10-11. 3-Wire Serial I/O Mode Timing (2/7)
(ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
SIO20
Write
SCK20
SI20
1 2 3 4 5 6 7 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI20
SS20
SIO20
Write
Note The value of the last bit previously output is output.
(iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1)
SCK20 1 2 3 4 5 6 7 8
SI20
SO20
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
Hi-Z
Note 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2
Hi-Z
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
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Figure 10-11. 3-Wire Serial I/O Mode Timing (3/7)
(iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20 1 2 3 4 5 6 7 8
SO20
SI20
INTCSI20
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
(v) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20
SIO20 Write (master)
Note
SI20
1 2 3 4 5 6 7 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI20
Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20.
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Figure 10-11. 3-Wire Serial I/O Mode Timing (4/7)
(vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1)
SS20
SIO20
Write
SCK20
SIO20 Write (master) Note 1
SI20
SO20
Hi-Z
1 2 3 4 5 6 7 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Note 2
Hi-Z
INTCSI20
Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state.
(vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
SIO20
Write
SCK20
SO20
1 2 3 4 5 6 7 8
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI20
INTCSI20
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SIO20
Write
SCK20
SIO20 Write (master) Note
SI20
CHAPTER 10 SERIAL INTERFACE 20
Figure 10-11. 3-Wire Serial I/O Mode Timing (5/7)
(viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
1 2 3 4 5 6 7 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI20
Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20.
(ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1)
SS20
SIO20
Write
SCK20
SIO20 Write (master) Note 1
SI20
1 2 3 4 5 6 7 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO20
Hi-Z
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2
Hi-Z
INTCSI20
Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state.
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Figure 10-11. 3-Wire Serial I/O Mode Timing (6/7)
(x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20
SO20 Note
1 2
DO7
3
DO6 DO5
4 5 6 7 8
DO4 DO3 DO2 DO1 DO0
SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
INTCSI20
Note The value of the last bit previously output is output.
(xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20 1 2 3 4 5 6 7 8
SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI20
Note The value of the last bit previously output is output.
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Figure 10-11. 3-Wire Serial I/O Mode Timing (7/7)
(xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1)
SS20
SIO20
Write
SCK20 1 2 3 4 5 6 7 8
SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO20
Hi-Z
Note 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2
Hi-Z
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
(3) Transfer start
Serial transfer is started by setting transfer data to the transmission shift register (TXS20/SIO20) when the following two conditions are satisfied.
•
Serial operation mode register 20 (CSIM20) bit 7 (CSIE20) = 1
•
Internal serial clock is stopped or SCK20 is high after 8-bit serial transfer.
Caution If CSIE20 is set to "1" after data is written to TXS20/SIO20, transfer does not start.
A termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (INTCSI20).
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11.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt priority control and is given top priority over all other interrupt requests.
A standby release signal is generated.
The non-maskable interrupt has one source of interrupt from the watchdog timer.
(2) Maskable interrupt
These interrupts undergo mask control. If two or more interrupts are simultaneously generated, each interrupt has a predetermined priority as shown in Table 11-1.
A standby release signal is generated.
The maskable interrupt has four sources of external interrupts and seven sources of internal interrupts.
11.2 Interrupt Sources and Configuration
There are total of 12 non-maskable and maskable interrupts in the interrupt sources (see Table 11-1).
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Interrupt Type Priority Note 1
Non-maskable interrupt
−
Name
INTWDT
Maskable interrupt
0
5
6
7
8
1
2
3
4
9
10
INTWDT
INTP0
INTP1
INTP2
INTSR20
INTCSI20
INTST20
INTWT
INTWTI
INTTM80
INTTM90
INTKR00
Table 11-1. Interrupt Sources
Interrupt Source
Trigger
Internal/External Vector Table
Address
Internal 0004H
Basic
Configuration
Type Note 2
(A) Watchdog timer overflow
(when watchdog timer mode 1 is selected)
Watchdog timer overflow
(when interval timer mode is selected)
Pin input edge detection External
(B)
(C) 0006H
0008H
000AH
000CH (B) End of UART reception on serial interface 20
End of three-wire SIO transfer reception on serial interface 20
End of UART transmission on serial interface 20
Watch timer interrupt
Interval timer interrupt
Generation of match signal for
8-bit timer/event counter 80
Generation of match signal for
16-bit timer 90
Key return signal detection
Internal
External
000EH
0010H
0012H
0014H
0016H
0018H (C)
Notes 1. The priority regulates which maskable interrupt is higher, when two or more maskable interrupts are requested simultaneously. Zero signifies the highest priority, while 10 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 11-1, respectively.
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Figure 11-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal Bus
Interrupt Request
Vector Table
Address Generator
Standby Release Signal
(B) Internal maskable interrupt
Internal Bus
MK IE
Interrupt Request IF
Vector Table
Address Generator
Standby Release Signal
(C) External maskable interrupt
INTM0, KRM00 MK
Internal Bus
IE
Interrupt
Request
Edge
Detector
IF
Vector Table
Address Generator
Standby
Release Signal
INTM0 : External interrupt mode register 0
KRM00 : Key return mode register 00
IF
IE
MK
: Interrupt request flag
: Interrupt enable flag
: Interrupt mask flag
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11.3 Interrupt Function Control Registers
The interrupt functions are controlled by the following five registers:
• Interrupt request flag registers 0 and 1 (IF0 and IF1)
• Interrupt mask flag registers 0 and 1 (MK0 and MK1)
• External interrupt mode register 0 (INTM0)
• Program status word (PSW)
• Key return mode register 00 (KRM00)
Table 11-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.
Table 11-2. Interrupt Request Signals and Corresponding Flags
Interrupt Request Flag Interrupt Mask Flag Interrupt Request Signal
INTWDT
INTP0
INTP1
INTP2
INTSR20/INTCSI20
INTST20
INTWT
INTWTI
INTTM80
INTTM90
INTKR00
TMIF4
PIF0
PIF1
PIF2
SRIF20
STIF20
WTIF
WTIIF
TMIF80
TMIF90
KRIF00
TMMK4
PMK0
PMK1
PMK2
SRMK20
STMK20
WTMK
WTIMK
TMMK80
TMMK90
KRMK00
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(1) Interrupt request flag registers 0 and 1 (IF0 and IF1)
An interrupt request flag is set to 1, when the corresponding interrupt request is issued, or when the related instruction is executed. It is cleared to 0, when the interrupt request is accepted, when a RESET signal is input, or when a related instruction is executed.
IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF0 and IF1 to 00H.
Figure 11-2. Format of Interrupt Request Flag Register
Symbol <7>
IF0
7
<6>
6
<5>
5
<4>
4
<3>
WTIIF WTIF STIF20SRIF20 PIF2
3
<2>
PIF1
<1> <0>
PIF0 TMIF4
<2> <1> <0>
IF1 0 0 0 0 0 KRIF00 TMIF90TMIF80
Address After Reset R/W
FFE0H 00H R/W
FFE1H 00H R/W
××
IF
×
0
Interrupt Request Flag
No interrupt request signal has been issued.
1 An interrupt request signal has been issued; an interrupt request has been made.
Cautions 1. Bits 3 to 7 of IF1 must all be set to 0.
2. The TMIF4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2.
3. When port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. To use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
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(2) Interrupt mask flag registers 0 and 1 (MK0 and MK1)
The interrupt mask flags are used to enable and disable the corresponding maskable interrupts.
MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 and MK1 to FFH.
Figure 11-3. Format of Interrupt Mask Flag Register
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0 WTIMK WTMK STMK20 SRMK20 PMK2 PMK1 PMK0 TMMK4
7 6 5 4 3 <2> <1> <0>
MK1 1 1 1 1 1 KRMK00 TMMK90 TMMK80
Address After Reset R/W
FFE4H FFH R/W
FFE5H FFH R/W
××
MK
×
0 Enable interrupt handling.
1 Disable interrupt handling.
Interrupt Handling Control
Cautions 1. Bits 3 to 7 of MK1 must all be set to 1.
2. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read TMMK4 flag results in an undefined value being detected.
3. When port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. To use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
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(3) External interrupt mode register 0 (INTM0)
INTM0 is used to specify an effective edge for INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Figure 11-4. Format of External Interrupt Mode Register 0
Symbol
INTM0
7 6 5 4 3 2 1
ES21 ES20 ES11 ES10 ES01 ES00 0
0
0
Address After Reset R/W
FFECH 00H R/W
ES21 ES20
0 0
0
1
1
0
Falling edge
Rising edge
1 1
Not to be set
Both rising and falling edges
INTP2 Effective Edge Selection
ES11 ES10
0 0
0 1
Falling edge
Rising edge
1
1
0
1
Not to be set
Both rising and falling edges
INTP1 Effective Edge Selection
ES01 ES00
0 0
0
1
1
0
Falling edge
Rising edge
1 1
Not to be set
Both rising and falling edges
INTP0 Effective Edge Selection
Cautions 1. Bits 0 and 1 must all be set to 0.
2. Before setting INTM0, set the corresponding interrupt mask flag to 1 to disable interrupts.
To enable interrupts, clear to 0 the corresponding interrupt request flag, then the corresponding interrupt mask flag.
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(4) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (EI and DI). When a vector interrupt is accepted, PSW is automatically saved to a stack, and the IE flag is reset to 0.
RESET input sets PSW to 02H.
Symbol
PSW
7
IE
6
Z
5
0
Figure 11-5. Program Status Word Configuration
4
AC
3
0
2
0
1
1
0
CY
After Reset
02H
Used in the execution of ordinary instructions
Whether to Enable/Disable Interrupt Acceptance IE
0
1
Disable
Enable
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(5) Key return mode register 00 (KRM00)
KRM00 is used to specify pins for which the key return signals are detected.
KRM00 is set with a 1-bit or 8-bit memory manipulation instruction.
Bit 0 (KRM000) specifies whether the detection is performed for four pins from KR00/P40 to KR03/P43 together. Bits 4 to 7 (KRM004 to KRM007) specify whether the detection is performed for the KR04/P44 to
KR07/P47 pins individually.
RESET input clears KRM00 to 00H.
Figure 11-6. Format of Key Return Mode Register 00
Symbol 7 6 5 4 3
KRM00 KRM007 KRM006 KRM005 KRM004 0
2
0
1 0
0 KRM000
Address
FFF5H
After Reset
00H
R/W
R/W
KRM00n
0 Not detected
1 Detected (Falling edges of port 4)
Key Return Signal Detection Selection
Cautions 1. Bits 1 to 3 must all be set to 0.
2. When a bit of KRM00 is set to 1, the pull-up resistor is forcibly connected to the corresponding pin. If the pin is set to output mode, however, the pull-up resistor is left disconnected.
3. Before setting KRM00, set bit 2 of MK1 to 1 (KRMK00 = 1) to disable interrupts. After
KRM00 is set, clear bit 2 of IF1 (KRIF = 0), then clear KRMK00 (KRMK00 = 0) to enable interrupts.
P40/KR00
P41/KR01
P42/KR02
P43/KR03
P44/KR04
P45/KR05
P46/KR06
P47/KR07
Remark n = 0, 4 to 7
Figure 11-7. Block Diagram of Falling Edge Detection Circuit
Key Return Mode Register 00 (KRM00)
Note
Falling Edge
Detection Circuit
KRMK00
KRIF00 Setting Signal
Standby Release Signal
Note This selector selects pins to be used for falling-edge inputs.
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11.4 Interrupt Processing Operation
11.4.1 Non-maskable interrupt request acceptance operation
The non-maskable interrupt request is unconditionally accepted even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 11-8 shows the flowchart from non-maskable interrupt request generation to acceptance. Figure 11-9 shows the timing of non-maskable interrupt request acceptance. Figure 11-10 shows the acceptance operation if multiple non-maskable interrupts are generated.
Caution During a non-maskable interrupt service program execution, do not input another nonmaskable interrupt request; if it is input, the service program will be interrupted and the new interrupt request will be acknowledged.
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Figure 11-8. Flowchart from Non-Maskable Interrupt Request Generation to Acceptance
Start
WDTM4 = 1
(watchdog timer mode is selected)
Yes
No
Interval Timer
WDT
Overflows
No
Yes
WDTM3 = 0
(non-maskable interrupt is selected)
Yes
Interrupt request is generated
No
Interrupt processing is started
WDTM : Watchdog timer mode register
WDT : Watchdog timer
Reset Processing
Figure 11-9. Timing of Non-Maskable Interrupt Request Acceptance
Instruction Instruction
Saving PSW and PC, and
Jump to Interrupt Processing
Interrupt Processing
Program
CPU Processing
TMIF4
NMI Request
(first)
Figure 11-10. Accepting Non-Maskable Interrupt Request
Main Routine
First Interrupt Processing
NMI Request
(second)
Second Interrupt Processing
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11.4.2 Maskable interrupt request acceptance operation
A maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is accepted in the interrupt enabled status (when the
IE flag is set to 1).
The time required to start the interrupt processing after a maskable interrupt request has been generated is shown in Table 11-3.
See Figures 11-11 and 11-12 for the interrupt request acceptance timing.
Table 11-3. Time from Generation of Maskable Interrupt Request to Processing
Minimum Time
9 clocks
Maximum Time
Note
19 clocks
Note The wait time is maximum when an interrupt request is generated immediately before BT and
BF instruction.
1
Remark 1 clock: (f
CPU
: CPU clock) f
CPU
When two or more maskable interrupt requests are generated at the same time, they are accepted starting from the interrupt request assigned the highest priority.
A pending interrupt is accepted when the status where it can be accepted is set.
Figure 11-11 shows the algorithm of accepting interrupt requests.
When a maskable interrupt request is accepted, the contents of PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the
PC, and execution branches.
To return from interrupt processing, use the RETI instruction.
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Figure 11-11. Interrupt Request Acceptance Processing Algorithm
Start
No
××
IF = 1 ?
Yes (Interrupt request generated)
No
××
MK = 0 ?
Yes
Interrupt Request Pending
No
IE = 1 ?
Yes
Vectored Interrupt
Processing
Interrupt Request Pending
××
IF : Interrupt request flag
××
MK : Interrupt mask flag
IE : Flag to control maskable interrupt request acceptance (1 = enable, 0 = disable)
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Clock
Figure 11-12. Interrupt Request Acceptance Timing (Example of MOV A,r)
8 Clocks
CPU MOV A,r
Saving PSW and PC, Jump to Interrupt Processing
Interrupt Processing Program
Interrupt
If an interrupt request flag (
××
IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n
−
1, the interrupt is accepted after the instruction under execution completes. Figure 11-12 shows an example of the interrupt request acceptance timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acceptance processing is performed after the MOV A,r instruction is completed.
Figure 11-13. Interrupt Request Acceptance Timing (When Interrupt Request Flag Is Set at the Last
Clock During Instruction Execution)
8 Clocks
Clock
CPU NOP MOV A,r
Saving PSW and PC, Jump to Interrupt Processing
Interrupt
Processing
Program
Interrupt
If an interrupt request flag (
××
IF) is set at the last clock of the instruction, the interrupt acceptance processing starts after the next instruction is executed. Figure 11-13 shows an example of the interrupt acceptance timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is executed, and then the interrupt acceptance processing is performed.
Caution Interrupt requests are reserved while interrupt request flag register 0 or 1 (IF0 or IF1) or interrupt mask flag register 0 or 1 (MK0 or MK1) is being accessed.
11.4.3 Multiplexed interrupt processing
Multiplexed interrupt processing in which another interrupt is accepted while an interrupt is processed can be processed by priority. When two or more interrupts are generated at once, interrupt processing is performed according to the priority assigned to each interrupt request in advance (see Table 11-1).
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INTxx
CHAPTER 11 INTERRUPT FUNCTIONS
Main Processing
Figure 11-14. Example of Multiple Interrupt
Example 1. A multiple interrupt is accepted
INTxx Processing INTyy Processing
EI
IE = 0
EI
IE = 0
INTyy
RETI RETI
During interrupt INTxx servicing, interrupt request INTyy is accepted, and a multiple interrupt is generated. An EI instruction is issued before each interrupt request acceptance, and the interrupt request acceptance enable state is set.
Example 2. A multiple interrupt is not generated because interrupts are not enabled
Main Processing INTxx Processing INTyy Processing
EI
IE = 0
INTyy INTyy is kept pending
RETI
INTxx
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx processing (an EI instruction is not issued), interrupt request INTyy is not accepted, and a multiple interrupt is not generated. The INTyy request is reserved and accepted after the INTxx processing is performed.
IE = 0: Interrupt request acceptance disabled
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11.4.4 Interrupt request reserve
Some instructions may reserve the acceptance of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. The following shows such instructions (interrupt request reserve instruction).
•
Manipulation instruction for interrupt request flag registers 0 and 1 (IF0 and IF1)
•
Manipulation instruction for interrupt mask flag registers 0 and 1 (MK0 and MK1)
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CHAPTER 12 STANDBY FUNCTION
12.1 Standby Function and Configuration
12.1.1 Standby function
The standby function is to reduce the power dissipation of the system and can be effected in the following two modes:
(1) HALT mode
This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU.
The system clock oscillation circuit continues oscillating. This mode does not reduce the current drain as much as STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. STOP mode stops the main system clock oscillation circuit and stops the entire system. The current drain of the CPU can be substantially reduced in this mode.
The low voltage (V
DD
= 1.8 V min.) of the data memory can be retained. Therefore, this mode is useful for retaining the contents of the data memory at an extremely low current drain.
STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillation circuit settles after STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.
Caution To set STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction.
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12.1.2 Standby function control register
The wait time after STOP mode is released upon interrupt request until the oscillation settles is controlled with the oscillation settling time selection register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, the oscillation settling time after RESET input is 2
15
/f
X
, instead of
2
17
/f
X
.
Symbol
OSTS
7
0
Figure 12-1. Format of Oscillation Settling Time Selection Register
6
0
5
0
4
0
3
0
2
OSTS2
1
OSTS1
0
OSTS0
Address After Reset R/W
FFFAH 04H R/W
OSTS2
0
0
OSTS1
0
1
OSTS0
0
0
1 0
Other than above
0
2
12
/f
X
µ
2
15
/f
X
(6.55 ms)
2
17
/f
X
(26.2 ms)
Not to be set
Oscillation Settling Time Selection
Caution The wait time after STOP mode is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of release by RESET input or by interrupt generation.
STOP Mode Release
X1 Pin Voltage
Waveform
V
SS0
,
V
SS1 a
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
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12.2 Operation of Standby Function
12.2.1 HALT mode
(1) HALT mode
HALT mode is set by executing the HALT instruction.
The operation status in HALT mode is shown in the following table.
Item
Table 12-1. Operation Statuses in HALT Mode
HALT Mode Operation Status While the Main
System Clock Is Running
While the Subsystem
Clock Is Running
Oscillation enabled
While the Subsystem
Clock Is Not Running
HALT Mode Operation Status While the
Subsystem Clock Is Running
While the Main System
Clock Is Running
While the Main System
Clock Is Not Running
Oscillation disabled Main system clock generation circuit
CPU
Port (output latch)
16-bit timer counter
8-bit timer/event counter
Watch timer
Watchdog timer
Serial interface
External interrupt
Operation disabled
Remains in the state existing before the selection of HALT mode
Operation enabled Operation enabled
Note 1
Operation enabled
Operation enabled
Operation enabled
Operation enabled
Operation enabled
Operation enabled Note 5
Operation enabled Note 1 Operation enabled
Operation disabled
Operation enabled
Note 2
Operation enabled
Note 3
Operation enabled Note 2
Operation enabled
Note 4
Notes 1. Operation is enabled while the main system clock is selected.
2. Operation is enabled while the subsystem clock is selected.
3. Operation is enabled only when TI80 is selected as the count clock.
4. Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used.
5. Maskable interrupt that is not masked
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CHAPTER 12 STANDBY FUNCTION
(2) Releasing HALT mode
HALT mode can be released by the following three types of sources:
(a) Releasing by unmasked interrupt request
HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is enabled to be accepted, vectored interrupt processing is performed. If the interrupt acceptance is disabled, the instruction at the next address is executed.
Figure 12-2. Releasing HALT Mode by Interrupt
HALT
Instruction Wait
Standby
Release Signal
Operating
Mode
HALT Mode Wait
Oscillation
Operating Mode
Clock
Remarks 1. The broken line indicates the case where the interrupt request that has released standby mode is accepted.
2. The wait time is as follows:
•
When vectored interrupt processing is performed : 9 to 10 clocks
•
When vectored interrupt processing is not performed : 1 to 2 clocks
(b) Releasing by non-maskable interrupt request
HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed.
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(c) Releasing by RESET input
When HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started.
Figure 12-3. Releasing HALT Mode by RESET Input
HALT
Instruction
Wait
(2 15 /f
X
: 6.55 ms)
RESET
Signal
Clock
Operating
Mode
HALT Mode
Oscillation
Reset
Period
Oscillation
Stop
Oscillation
Settling
Wait Status
Oscillation
Operating
Mode
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
Releasing Source
Maskable interrupt request
Non-maskable interrupt request
RESET input
×
: Don't care
Table 12-2. Operation after Release of HALT Mode
MK
××
0
0
1
−
−
IE
0
1
×
×
−
Operation
Executes next address instruction.
Executes interrupt processing.
Retains HALT mode.
Executes interrupt processing.
Reset processing
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12.2.2 STOP mode
(1) Setting and operation status of STOP mode
STOP mode is set by executing the STOP instruction.
Caution Because standby mode can be released by an interrupt request signal, standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation settling time selection register (OSTS) elapses, and then operating mode is set.
The operation status in STOP mode is shown in the following table.
Item
Table 12-3. Operation Statuses in STOP Mode
STOP Mode Operation Status While the Main System Clock Is Running
While the Subsystem Clock Is Running While the Subsystem Clock Is Not Running
Oscillation stopped Main system clock generation circuit
CPU
Port (output latch)
16-bit timer
8-bit timer/event counter
Watch timer
Watchdog timer
Serial interface
External interrupt
Operation disabled
Remains in the state existing before the selection of STOP mode
Operation enabled
Note 1
Operation disabled
Operation enabled Note 2
Operation enabled
Note 1
Operation disabled
Operation disabled
Operation enabled Note 3
Operation enabled
Note 4
Notes 1. Operation is enabled while the subsystem clock is selected.
2. Operation is enabled only when TI80 is selected as the count clock.
3. Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used.
4. Maskable interrupt that is not masked
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(2) Releasing STOP mode
STOP mode can be released by the following two types of sources:
(a) Releasing by unmasked interrupt request
STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be accepted, vectored interrupt processing is performed, after the oscillation settling time has elapsed. If the interrupt acceptance is disabled, the instruction at the next address is executed.
Figure 12-4. Releasing STOP Mode by Interrupt
STOP
Instruction
Wait
(set time by OSTS)
Standby
Release Signal
Operating
Mode
Clock
Oscillation
STOP Mode
Oscillation
Stop
Oscillation Settling
Wait Status
Oscillation
Operating
Mode
Remark The broken line indicates the case where the interrupt request that has released standby mode is accepted.
(b) Releasing by RESET input
When STOP mode is released by the RESET signal, the reset operation is performed after the oscillation settling time has elapsed.
RESET
Signal
Operating
Mode
Clock
Oscillation
Figure 12-5. Releasing STOP Mode by RESET Input
STOP
Instruction
Wait
(2 15 /f
X
: 6.55 ms)
STOP Mode
Oscillation
Stop
Reset
Period
Oscillation
Settling
Wait Status
Oscillation
Operating
Mode
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
Releasing Source
Maskable interrupt request
RESET input
×
: Don't care
Table 12-4. Operation after Release of STOP Mode
MK
××
0
0
1
−
IE
0
1
×
−
Operation
Executes next address instruction.
Executes interrupt processing.
Retains STOP mode.
Reset processing
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CHAPTER 13 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input with RESET pin
(2) Internal reset by program run-away time detected with watchdog timer
External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by reset signal input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in Table 13-1. Each pin has a high impedance during reset input or during oscillation settling time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation settling time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation settling time has elapsed (see Figures 13-2 through
13-4).
Cautions 1. For an external reset, input a low level for 10
µµµµ s or more to the RESET pin.
2. When STOP mode is cleared by reset, STOP mode contents are held during reset input.
However, the port pins become high impedance.
Figure 13-1. Block Diagram of Reset Function
RESET
Reset Control Circuit
Reset Signal
Count Clock Watchdog Timer
Overflow
Stop
Interrupt Function
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Figure 13-2. Reset Timing by RESET Input
X1
Normal Operation
Reset Period
(oscillation
stops)
Oscillation
Settling
Time Wait
Normal Operation
(reset processing)
RESET
Internal
Reset Signal
Delay Delay
Hi-Z
Port Pin
Figure 13-3. Reset Timing by Overflow in Watchdog Timer
X1
Overflow in
Watchdog Timer
Internal
Reset Signal
Normal Operation
Reset Period
(oscillation
continues)
Oscillation
Settling
Time Wait
Normal Operation
(reset processing)
Hi-Z
Port Pin
Figure 13-4. Reset Timing by RESET Input in STOP Mode
X1
STOP Instruction Execution
Normal Operation
Stop Status
(oscillation
stops)
RESET
Reset Period
(oscillation
stops)
Oscillation
Settling
Time Wait
Internal
Reset Signal
Delay Delay
Hi-Z
Port Pin
Normal Operation
(reset processing)
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Table 13-1. State of the Hardware after a Reset
Hardware
Program counter (PC)
Note 1
Stack pointer (SP)
Program status word (PSW)
RAM Data memory
General-purpose register
Ports (P0 to P4) (output latch)
Port mode registers (PM0 to PM4)
Pull-up resistor option registers (PU0, PUB2)
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillation settling time selection register (OSTS)
16-bit timer Timer counter (TM90)
Compare register (CR90)
Capture register (TCP90)
Mode control register (TMC90)
8-bit timer/event counter
Watch timer
Watchdog timer
Serial interface 20
Interrupts
Buzzer output control register (BZC90)
Timer counter (TM80)
Compare register (CR80)
Mode control register (TMC80)
Mode control register (WTM)
Timer clock selection register (TCL2)
Mode register (WDTM)
Mode register (CSIM20)
Asynchronous serial interface mode register (ASIM20)
Asynchronous serial interface status register (ASIS20)
Baud rate generator control register (BRGC20)
Transmission shift register (TXS20)
Reception buffer register (RXB20)
Request flag registers (IF0, IF1)
Mask flag registers (MK0, MK1)
External interrupt mode register (INTM0)
Key return mode register (KRM00)
Notes 1. While a reset signal is being input, and during the oscillation settling period, the contents of the PC will be undefined, while the remainder of the hardware will be the same as after the reset.
2. In standby mode, the RAM enters the hold state after a reset.
00H
00H
00H
00H
00H
00H
FFH
Undefined
00H
FFH
00H
00H
00H
02H
00H
00H
04H
0000H
FFFFH
Undefined
00H
00H
00H
Undefined
00H
00H
State after Reset
Loaded with the contents of the reset vector table
(0000H, 0001H)
Undefined
02H
Undefined
Note 2
Undefined Note 2
00H
FFH
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CHAPTER 14
µµµµ
PD78F9046
The
µ
PD78F9046 replaces the internal masked ROM of the
µ
PD789046 with flash memory. The differences between the flash memory and the masked ROM versions are shown in Table 14-1.
Table 14-1. Differences between Flash Memory and Masked ROM Versions
Item
Internal memory
IC0 pin
V
PP
pin
Electric characteristics
ROM
High-speed RAM
Flash Memory
µ
PD78F9046
16 Kbytes (flash memory)
Masked ROM
µ
PD789046
16 Kbytes
512 bytes
Not provided Provided
Provided Not provided
Varies depending on flash memory or masked ROM version.
Caution The flash memory and masked ROM versions have different noise immunity and noise radiation characteristics. Do not use ES versions for evaluation when considering switching from flash memory versions to those using masked ROM upon the transition from preproduction to mass-production. CS versions (masked ROM versions) should be used in this case.
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µµµµ
PD78F9046
14.1 Flash Memory Programming
The on-chip program memory in the
µ
PD78F9046 is a flash memory.
The flash memory can be written with the
µ
PD78F9046 mounted on the target system (on-board). Connect the dedicated flash writer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory.
Remark FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd.
14.1.1 Selecting communication mode
The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 14-2. To select a communication mode, the format shown in Figure
14-1 is used. Each communication mode is selected by the number of V
PP
pulses shown in Table 14-2.
Communication Mode
3-wire serial I/O
UART
Pseudo 3-wire mode
Note
Table 14-2. Communication Mode
Pins Used
SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
TxD20/SO20/P21
RxD20/SI20/P22
P00 (Serial clock input)
P01 (Serial data output)
P02 (Serial data input)
0
8
12
Number of V
PP
Pulses
Note Serial transfer is performed by controlling a port by software.
Caution Be sure to select a communication mode depending on the number of V
PP
pulses shown in
Table 14-2.
Figure 14-1. Format of Communication Mode Selection
V
PP
10 V
V
DD
V
SS
1 2 n
RESET
V
DD
V
SS
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µµµµ
PD78F9046
14.1.2 Function of flash memory programming
By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 14-3 shows the major functions of flash memory programming.
Function
Batch erase
Batch blank check
Data write
Batch verify
Table 14-3. Major Functions of Flash Memory Programming
Description
Erases all contents of memory.
Checks erased state of entire memory.
Writes to flash memory based on write start address and number of data written (number of bytes).
Compares all contents of memory with input data.
14.1.3 Flashpro III connection
Connection between the Flashpro III and the
µ
PD78F9046 differs depending on the communication mode (3-wire serial I/O, UART, or pseudo 3-wire mode). Figures 14-2 to 14-4 show the connection in the respective modes.
Figure 14-2. Flashpro III Connection Example in 3-Wire Serial I/O Mode
Flashpro III
µ
PD78F9046
V
PP n Note
V
DD
RESET
SCK
SO
SI
GND
V
PP
V
DD0
, V
DD1
RESET
SCK20
SI20
SO20
V
SS0
, V
SS1
Note n = 1, 2
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µµµµ
PD78F9046
Figure 14-3. Flashpro III Connection Example in UART Mode
Flashpro III
µ
PD78F9046
V
PP n Note
V
DD
RESET
SO
SI
GND
V
PP
V
DD0
, V
DD1
RESET
RxD20
TxD20
V
SS0
, V
SS1
Note n = 1, 2
Figure 14-4. Flashpro III Connection Example in Pseudo 3-Wire Mode (When P0 Is Used)
Flashpro III
V
PP n Note
V
DD
RESET
SCK
SO
SI
GND
µ
PD78F9046
V
PP
V
DD0
, V
DD1
RESET
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)
V
SS0
, V
SS1
Note n = 1, 2
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µµµµ
PD78F9046
14.1.4 Setting Example with Flashpro III (PG-FP3)
When writing data to the flash memory by using the Flashpro III (PG-FP3), set as follows.
<1> Load the parameter file.
<2> Select a serial mode and serial clock by using the type command.
<3> An example of setting PG-FP3 is shown below.
Communication Mode
3-wire serial I/O
UART
Pseudo 3-wire mode
Table 14-4. Setting Example with PG-FP3
COMM PORT
CPU CLK
On Target Board
SIO CLK
In Flashpro
SIO CLK
COMM PORT
CPU CLK
On Target Board
UART BPS
COMM PORT
CPU CLK
On Target Board
SIO CLK
In Flashpro
SIO CLK
Setting Example with PG-FP3
SIO-ch0
On Target Board
In Flashpro
4.1943 MHz
1.0 MHz
4.0 MHz
1.0 MHz
UART-ch0
On Target Board
4.1943 MHz
9,600 bps
Note 2
Port A
On Target Board
In Flashpro
4.1943 MHz
1 kHz
4.0 MHz
1 kHz
0
V
PP
Pulse Count
Note 1
8
12
Notes 1. The number of V
PP
pulses supplied from the Flashpro III when serial communication is initialized.
These pulse counts determine the pins used for communication.
2. Select 9,600 bps, 19,200 bps, 38,400 bps, or 76,800 bps.
Remark COMM PORT : Selects serial port.
SIO CLK : Selects serial clock frequency.
CPU CLK : Selects source of CPU clock to be input.
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CHAPTER 15 INSTRUCTION SET
This chapter lists the instruction set of the
µ
PD789046 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User's Manual
Instruction (U11047E).
15.1 Operation
15.1.1 Operand identifiers and description methods
Operands are described in "Operands" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. Each symbol has the following meaning.
•
# : Immediate data specification
•
!
: Absolute address specification
•
$ : Relative address specification
•
[ ] : Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit
Table 15-1. Operand Identifiers and Description Methods
Description Method
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even addresses only)
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark See Table 3-3 for symbols of special function registers.
User's Manual U13600EJ2V0UM00
193
CHAPTER 15 INSTRUCTION SET
15.1.2 Description of "Operation" column
D
E
H
L
A
X
B
C
AX
BC
: A register; 8-bit accumulator
: X register
: B register
: C register
: D register
: E register
: H register
: L register
: AX register pair; 16-bit accumulator
: BC register pair
DE
HL
PC
SP
: DE register pair
: HL register pair
: Program counter
: Stack pointer
PSW : Program status word
CY : Carry flag
AC
Z
: Auxiliary carry flag
: Zero flag
IE : Interrupt request enable flag
NMIS : Flag indicating non-maskable interrupt servicing in progress
( ) : Memory contents indicated by address or register contents in parentheses
∨
∨
×
H
,
×
L
: Higher 8 bits and lower 8 bits of 16-bit register
∧
: Logical product (AND)
: Logical sum (OR)
: Exclusive logical sum (exclusive OR)
: Inverted data addr16 : 16-bit immediate data or label jdisp8 : Signed 8-bit data (displacement value)
15.1.3 Description of "Flag" column
(Blank) : Unchanged
0 : Cleared to 0
1
×
R
: Set to 1
: Set/cleared according to the result
: Previously saved value is stored
194
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CHAPTER 15 INSTRUCTION SET
15.2 Operation List
Mnemonic Operands Byte Clock Operation Flag
Z AC CY
MOV
XCH
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, X
A, r Note 2
A, saddr
A, sfr
A, [DE]
A, [HL]
A, [HL, byte] r, #byte saddr, #byte sfr, #byte
A, r Note 1 r, A
Note 1
A, saddr saddr, A
A, sfr sfr, A
A, !addr16
!addr16, A
PSW, #byte
2
2
2
2
2
1
1
1
2
1
1
1
2
2
1
3
3
3
2
2
2
2
2
2
3
3
3
6
6
6
6
6
4
8
8
8
6
6
6
4
4
6
8
8
6
4
4
4
4
4
4
6
6
6
PSW
←
A
A
←
(DE)
(DE)
←
A
A
←
(HL)
(HL)
←
A
A
←
(HL + byte)
(HL + byte)
←
A
A
↔
X
A
↔
r
A
↔
(saddr)
A
↔
sfr
A
↔
(DE)
A
↔
(HL)
A
↔
(HL + byte) r
←
byte
(saddr)
←
byte sfr
←
byte
A
←
r r
←
A
A
←
(saddr)
(saddr)
←
A
A
←
sfr sfr
←
A
A
←
(addr16)
(addr16)
←
A
PSW
←
byte
A
←
PSW
× × ×
× × ×
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by processor clock control register
(PCC).
User's Manual U13600EJ2V0UM00
195
CHAPTER 15 INSTRUCTION SET
Mnemonic Operands Byte Clock Operation Flag
Z AC CY
MOVW
XCHW
ADD
ADDC
SUB
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte] rp, #word
AX, saddrp saddrp, AX
AX, rp Note rp, AX
Note
AX, rp
Note
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
1
2
2
3
2
3
2
3
1
2
2
2
2
2
3
2
3
1
2
3
2
1
1
1
3
2
2
6
6
4
8
4
6
4
8
6
4
4
6
6
4
6
4
8
6
4
6
4
4
4
8
6
6
8 rp
←
word
AX
←
(saddrp)
(saddrp)
←
AX
AX
←
rp rp
←
AX
AX
↔
rp
A, CY
←
A + byte
(saddr), CY
←
(saddr) + byte
A, CY
←
A + r
A, CY
←
A + (saddr)
A, CY
←
A + (addr16)
A, CY
←
A + (HL)
A, CY
←
A + (HL + byte)
A, CY
←
A + byte + CY
(saddr), CY
←
(saddr) + byte + CY
A, CY
←
A + r + CY
A, CY
←
A + (saddr) + CY
A, CY
←
A + (addr16) + CY
A, CY
←
A + (HL) + CY
A, CY
←
A + (HL + byte) + CY
A, CY
←
A
−
byte
(saddr), CY
←
(saddr)
−
byte
A, CY
←
A
−
r
A, CY
←
A
−
(saddr)
A, CY
←
A
−
(addr16)
A, CY
←
A
−
(HL)
A, CY
←
A
−
(HL + byte)
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by processor clock control register
(PCC).
196
User's Manual U13600EJ2V0UM00
CHAPTER 15 INSTRUCTION SET
Mnemonic
SUBC
AND
OR
XOR
Operands
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
Byte Clock
2
2
3
1
2
2
2
3
2
3
3
2
1
1
2
2
2
2
3
2
2
3
2
3
1
2
3
2
Operation
4
4
8
6
6
6
4
6
4
8
6
4
6
6
6
4
4
4
8
6
4
6
4
8
6
4
6
4
A, CY
←
A
−
byte
−
CY
(saddr), CY
←
(saddr)
−
byte
−
CY
A, CY
←
A
−
r
−
CY
A, CY
←
A
−
(saddr)
−
CY
A, CY
←
A
−
(addr16)
−
CY
A, CY
←
A
−
(HL)
−
CY
A, CY
←
A
−
(HL + byte)
−
CY
A
←
A
∧
byte
(saddr)
←
(saddr)
∧
byte
A
←
A
∧
r
A
←
A
∧
(saddr)
A
←
A
∧
(addr16)
A
←
A
∧
(HL)
A
←
A
∧
(HL + byte)
A
←
A
∨
byte
(saddr)
←
(saddr)
∨
byte
A
←
A
∨
r
A
←
A
∨
(saddr)
A
←
A
∨
(addr16)
A
←
A
∨
(HL)
A
←
A
∨
(HL + byte)
A
←
A
∨
byte
(saddr)
←
(saddr)
∨
byte
A
←
A
∨
r
A
←
A
∨
(saddr)
A
←
A
∨
(addr16)
A
←
A
∨
(HL)
A
←
A
∨
(HL + byte)
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
Remark One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by processor clock control register
(PCC).
User's Manual U13600EJ2V0UM00
197
CHAPTER 15 INSTRUCTION SET
Mnemonic
CMP
ADDW
SUBW
CMPW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
SET1
CLR1
SET1
CLR1
NOT1
Operands Byte Clock
3
2
3
3
3
2
1
1
1
1
1
2
2
1
1
1
2
1
3
2
3
3
2
2
2
3
3
2
3
1
2
3
2 r saddr rp rp
A, 1
A, 1
A, 1
A, 1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word r
AX, #word saddr
Operation
6
10
6
6
6
4
2
2
4
2
2
4
4
4
10
2
2
2
6
4
6
6
4
4
6
6
6
4
8
6
4
6
4
A
−
byte
(saddr)
−
byte
A
−
r
A
−
(saddr)
A
−
(addr16)
A
−
(HL)
A
−
(HL + byte)
AX, CY
←
AX + word
AX, CY
←
AX
−
word
AX
−
word r
←
r + 1
(saddr)
←
(saddr) + 1 r
←
r + 1
(saddr)
←
(saddr)
−
1 rp
←
rp + 1 rp
←
rp
−
1
(CY, A
7
←
A
0
, A m
−
1
←
A m
)
×
1
(CY, A
0
←
A
7
, A m+1
←
A m
)
×
1
(CY
←
A
0
, A
7
←
CY, A m
−
1
←
A m
)
×
1
(CY
←
A
7
, A
0
←
CY, A m+1
←
A m
)
×
1
(saddr.bit)
←
1 sfr.bit
←
1
A.bit
←
1
PSW.bit
←
1
(HL).bit
←
1
(saddr.bit)
←
0 sfr.bit
←
0
A.bit
←
0
PSW.bit
←
0
(HL).bit
←
0
CY
←
1
CY
←
0
CY
←
CY
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× ×
× ×
× ×
× ×
×
×
×
×
× × ×
× × ×
1
0
×
Remark One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by processor clock control register
(PCC).
198
User's Manual U13600EJ2V0UM00
CHAPTER 15 INSTRUCTION SET
Mnemonic Operands Byte Clock Operation Flag
Z AC CY
CALL
CALLT
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
!addr16
[addr5]
PSW rp
PSW rp
SP, AX
AX, SP
!addr16
$addr16
AX
$saddr16
$saddr16
$saddr16
$saddr16 saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16 saddr, $addr16
4
3
2
4
1
2
2
2
3
2
2
2
1
1
1
1
2
3
4
2
4
3
4
4
1
1
3
1
1
1
3
3
1
6
2
2
2
6
6
8
6
8
6
10
10
8
6
6
6
6
6
6
8
6
4
6
2
4
10
6
6
8
10
10
10
8
(SP
−
1)
←
(PC + 3)
H
, (SP
−
2)
←
(PC + 3)
L
,
PC
←
addr16, SP
←
SP
−
2
(SP
−
1)
←
(PC + 1)
H
, (SP
−
2)
←
(PC + 1)
L
,
PC
H
←
(00000000, addr5 + 1),
PC
L
←
(00000000, addr5), SP
←
SP
−
2
PC
H
←
(SP + 1), PC
L
←
(SP), SP
←
SP + 2
PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3, NMIS
←
0
(SP
−
1)
←
PSW, SP
←
SP
−
1
(SP
−
1)
←
rp
H
, (SP
−
2)
←
rp
L
, SP
←
SP
−
2
PSW
←
(SP), SP
←
SP + 1 rp
H
←
(SP + 1), rp
L
←
(SP), SP
←
SP + 2
SP
←
AX
AX
←
SP
PC
←
addr16
PC
←
PC + 2 + jdisp8
PC
H
←
A, PC
L
←
X
PC
←
PC + 2 + jdisp8 if CY = 1
PC
←
PC + 2 + jdisp8 if CY = 0
PC
←
PC + 2 + jdisp8 if Z = 1
PC
←
PC + 2 + jdisp8 if Z = 0
PC
←
PC + 4 + jdisp8 if (saddr.bit) = 1
PC
←
PC + 4 + jdisp8 if sfr.bit = 1
PC
←
PC + 3 + jdisp8 if A.bit = 1
PC
←
PC + 4 + jdisp8 if PSW.bit = 1
PC
←
PC + 4 + jdisp8 if (saddr.bit) = 0
PC
←
PC + 4 + jdisp8 if sfr.bit = 0
PC
←
PC + 3 + jdisp8 if A.bit = 0
PC
←
PC + 4 + jdisp8 if PSW.bit = 0
B
←
B
−
1, then PC
←
PC + 2 + jdisp8 if B
≠
0
C
←
C
−
1, then PC
←
PC + 2 + jdisp8 if C
≠
0
(saddr)
←
(saddr)
−
1, then
PC
←
PC + 3 + jdisp8 if (saddr)
≠
0
No Operation
IE
←
1 (Enable Interrupt)
IE
←
0 (Disable Interrupt)
Set HALT Mode
Set STOP Mode
R R R
R R R
Remark One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by processor clock control register
(PCC).
User's Manual U13600EJ2V0UM00
199
CHAPTER 15 INSTRUCTION SET
15.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ r
2nd Operand
1st Operand
#byte
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
A r sfr saddr !addr16
PSW [DE] [HL]
[HL + byte]
$addr16 1
MOV
Note
XCH
Note
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
MOV MOV
None
INC
DEC
B, C sfr saddr
DBNZ
DBNZ INC
DEC
!addr16
PSW
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
MOV
MOV
MOV PUSH
POP
[DE]
[HL]
[HL + byte]
MOV
MOV
MOV
Note Except r = A.
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CHAPTER 15 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
AX rp
Note saddrp 2nd Operand
1st Operand
AX rp
#word
ADDW
SUBW
CMPW
MOVW MOVW Note
MOVW
XCHW
MOVW
SP
MOVW
None
INCW
DECW
PUSH
POP saddrp sp
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
BT
BF
BT
BF
BT
BF
BT
BF
$addr16
[HL].bit
CY
None
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
User's Manual U13600EJ2V0UM00
201
CHAPTER 15 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
Basic instructions BR
AX !addr16
CALL
BR
[addr5]
CALLT
$addr16
BR
BC
BNC
BZ
BNZ
DBNZ Compound instructions
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
202
User's Manual U13600EJ2V0UM00
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the
µ
PD789046 Subseries.
Figure A-1 shows development tools.
•
Compatibility with PC98-NX Series
Unless stated otherwise, products which are supported for the IBM PC/AT
TM
and compatibles can also be used with the PC98-NX Series. When using the PC98-NX Series, therefore, refer to the explanations for the IBM
PC/AT and compatibles.
•
Windows
Unless stated otherwise, "Windows" refers to the following operating systems.
• Windows 3.1
•
Windows 95
•
Windows NT
TM
Ver. 4.0
User's Manual U13600EJ2V0UM00
203
204
APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools
Language Processing Software
• Assembler Package
• C Compiler Package
• System Simulator
• Device File
• C Compiler Source File
• Integrated Debugger
Embedded Software
• OS
Host Machine
(PC or EWS)
Interface Adapter
Flash Memory
Writing Tools
Flash Writer
Flash Memory
Writing Adapter
Flash Memory
In-Circuit Emulator
Emulation Board
Emulation Probe
Power Supply Unit
Conversion Adapter
Conversion Socket
Target System
User's Manual U13600EJ2V0UM00
APPENDIX A DEVELOPMENT TOOLS
A.1 Language Processing Software
RA78K0S
Assembler package
CC78K0S
C compiler package
DF789046
Device file
Note
CC78K0S-L
C compiler source file
Program that converts program written in mnemonic into object code that can be executed by microcontroller.
In addition, automatic functions to generate symbol table and optimize branch instructions are also provided.
Used in combination with optional device file (DF789046).
<Caution when used under PC environment>
The assembler package is a DOS-based application but may be used under the Windows environment by using Project Manager of Windows (included in the package).
Part number:
µ
S
××××
RA78K0S
Program that converts program written in C language into object codes that can be executed by microcontroller.
Used in combination with optional assembler package (RA78K0S) and device file (DF789046).
<Caution when used under PC environment>
The C compiler package is a DOS-based application but may be used under the Windows environment by using Project Manager of Windows (included in the assembler package).
Part number:
µ
S
××××
CC78K0S
File containing the information inherent to the device.
Used in combination with other optional tools (RA78K0S, CC78K0S, SM78K0S).
Part number:
µ
S
××××
DF789046
Source file of functions constituting object library included in C compiler package.
Necessary for changing object library included in C compiler package according to customer's specifications.
Since this is the source file, its working environment does not depend on any particular operating system.
Part number:
µ
S
××××
CC78K0S-L
Note DF789046 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S.
Remark
××××
in the part number differs depending on the host machines and operating systems to be used.
µ
S
××××
RA78K0S
µ
S
××××
CC78K0S
µ
S
××××
DF789046
µ
S
××××
CC78K0S-L
××××
AA13
AB13
3P16
3K13
3K15
3R13
Host Machine
PC-9800 series
IBM PC/AT and compatibles
HP9000 series 700 TM
SPARCstation
TM
NEWS TM (RISC)
OS
Japanese Windows
Note
Japanese Windows
Note
HP-UX TM (Rel.10.10)
SunOS
TM
(Rel.4.1.4),
Solaris
TM
(Rel.2.5.1)
NEWS-OS TM (Rel.6.1)
Supply Media
3.5" 2HD FD
3.5" 2HC FD
DAT (DDS)
3.5" 2HC FD
1/4" CGMT
3.5" 2HC FD
Note Also operates under the DOS environment.
User's Manual U13600EJ2V0UM00
205
APPENDIX A DEVELOPMENT TOOLS
A.2 Flash Memory Writing Tools
Flash writer dedicated to the microcontrollers incorporating a flash memory.
Flashpro III
(part number: FL-PR3, PG-FP3)
Flash writer
FA-44GB-8ES
Flash memory writing adapter
Flash memory writing adapter. Used in connection with Flashpro III.
•
FA-44GB-8ES: For 44-pin plastic LQFP (GB-8ES type)
Remark FL-PR3 and FA-44GB-8ES are products of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (044-822-3813)
A.3 Debugging Tools
A.3.1 Hardware
IE-78K0S-NS
In-circuit emulator
In-circuit emulator for debugging hardware and software of application system using 78K/0S
Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine.
This is the adapter for supplying power from 100 to 240 VAC outlet.
IE-70000-MC-PS-B
AC adapter
IE-70000-98-IF-C
Interface adapter
IE-70000-CD-IF-A
PC card interface
IE-70000-PC-IF-C
Interface adapter
IE-70000-PCI-IF
Interface adapter
IE-789046-NS-EM1
Emulation board
NP-44GB
EV-9200G-44
Conversion socket
NP-44GB-TQ
TGB-044SAP
Conversion adapter
This adapter is needed when PC-9800 series (excluding a notebook-type personal computer) is used as a host machine of IE-78K0S-NS (C bus compatible).
This PC card and interface cable are needed when a notebook-type personal computer is used as a host machine of IE-78K0S-NS (PCMICA socket compatible).
This adapter is needed when IBM PC/AT and compatibles are used as a host machine of
IE-78K0S-NS (ISA bus compatible).
This adapter is needed when a personal computer incorporating the PCI bus is used as a host machine of IE-78K0S-NS.
Emulation board for emulating the peripheral hardware inherent to the device.
Used in combination with in-circuit emulator.
This is the board for connecting the in-circuit emulator and target system.
Used in combination with the EV-9200G-44.
This conversion socket is used to connect a target system board designed to allow mounting of the 44-pin plastic LQFP and the NP-44GB.
This is the board for connecting the in-circuit emulator and target system.
Used in combination with the TGB-044SAP.
This conversion adapter is used to connect a target system board designed to allow mounting of the 44-pin plastic LQFP and the NP-44GB-TQ.
Remarks 1. NP-44GB and NP-44GB-TQ are products of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (044-822-3813)
2. TGB-044SAP is a product of TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kougyou, Ltd.
Tokyo Electronics Division (03-3820-7112)
Osaka Electronics Division (06-6244-6672)
206
User's Manual U13600EJ2V0UM00
APPENDIX A DEVELOPMENT TOOLS
A.3.2 Software
ID78K0S-NS
Integrated debugger
(Supports in-circuit emulator
IE-78K0S-NS)
Control program for debugging the 78K/0S Series.
This program provides a graphical user interface. It runs on Windows for personal computer users and on OSF/Motif TM for engineering work station users, and has visual designs and operability that comply with these operating systems. In addition, it has a powerful debug function that supports C language. Therefore, trace results can be displayed at a C language level by the window integration function that links source program, disassembled display, and memory display, to the trace result. This software also allows users to add other function extension modules such as task debugger and system performance analyzer to improve the debug efficiency for programs using a real-time operating system.
Used in combination with optional device file (DF789046).
Part number:
µ
S
××××
ID78K0S-NS
Remark
××××
in the part number differs depending on the host machines and operating system to be used.
µ
S
××××
ID78K0S-NS
××××
AA13
AB13
BB13
Host Machine
PC-9800 series
IBM PC/AT and compatibles
OS
Japanese Windows
Note
Japanese Windows
Note
English Windows Note
Supply Media
3.5" 2HD FD
3.5" 2HC FD
SM78K0S
System simulator
DF789046
Note
Device file
Note Also operates under the DOS environment.
Debugs program at C source level or assembler level while simulating operation of target system on host machine.
SM78K0S runs on Windows.
By using SM78K0S, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. This enhances development efficiency and improves software quality.
Used in combination with optional device file (DF789046).
Part number:
µ
S
××××
SM78K0S
File containing the information inherent to the device.
Used in combination with other optional tools (RA78K0S, CC78K0S, SM78K0S).
Part number:
µ
S
××××
DF789046
Note DF789046 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S.
Remark
××××
in the part number differs depending on the host machines and operating system to be used.
µ
S
××××
SM78K0S
××××
AA13
AB13
BB13
Host Machine
PC-9800 series
IBM PC/AT and compatibles
OS
Japanese Windows
Note
Japanese Windows Note
English Windows
Note
Supply Media
3.5" 2HD FD
3.5" 2HC FD
Note Also operates under the DOS environment.
User's Manual U13600EJ2V0UM00
207
APPENDIX A DEVELOPMENT TOOLS
A.4 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint
Figure A-2. EV-9200G-44 Package Drawing (Reference) (unit: mm)
Based on EV-9200G-44
(1) Package drawing (in mm)
E
A
B
EV-9200G-44
F
M
N O
No.1 pin index
1
208
G
H
I
Q
R
O
P
M
N
K
L
F
G
D
E
ITEM
A
B
C
H
I
J
5.0
12.0
14.7
5.0
12.0
14.7
8.0
7.8
MILLIMETERS
15.0
10.3
10.3
15.0
4-C 3.0
0.8
2.0
1.35
0.35±0.1
EV-9200G-44-G0E
INCHES
0.591
0.406
0.406
0.591
4-C 0.118
0.031
0.197
0.472
0.579
0.197
0.472
0.579
0.315
0.307
0.079
0.053
0.014
+0.004
–0.005
User's Manual U13600EJ2V0UM00
APPENDIX A DEVELOPMENT TOOLS
Figure A-3. EV-9200G-44 Footprints (Reference) (unit: mm)
Based on EV-9200G-44
(2) Pad drawing (in mm)
G
J
K
L
C
B
A
F
G
D
E
ITEM
A
B
C
J
K
H
I
L
MILLIMETERS
15.7
15.7
5.00±0.08
5.00±0.08
0.5±0.02
EV-9200G-44-P1E
INCHES
0.618
11.0
0.8±0.02
×
10=8.0±0.05
0.8±0.02
×
10=8.0±0.05
11.0
0.433
0.031
×
0.394=0.315
+0.002
–0.002
0.031
×
0.394=0.315
+0.002
–0.002
0.433
0.618
0.197
+0.003
–0.004
0.197
+0.003
–0.004
0.02
+0.001
–0.002
+0.001
–0.002
+0.004
–0.005
+0.001
–0.002
Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).
User's Manual U13600EJ2V0UM00
209
APPENDIX A DEVELOPMENT TOOLS
A.5 Conversion Adapter (TGB-044SAP) Drawing
Figure A-4. TGB-044SAP Package Drawing (Reference) (unit: mm)
Reference diagram: TGB-044SAP (TQPACK044SA+TQSOCKET044SAP)
Package dimension (unit: mm)
H
C
A
B
P
D E F G N O
Protrusion height Q
S
J K
T
I
L
M
X
R g f
U W
V a
Y
Z b d c e
note: Product by TOKYO ELETECH CORPORATION.
T
U
V
W
X
Y
Z
N
O
P
K
L
M
Q
R
S
G
H
I
J
ITEM MILLIMETERS
A 10.12
B
C
D
0.8x10=8.0
0.8
E
F
16.65
8.4
10.8
13.2
C 2.0
9.35
1.325
1.325
12.0
16.65
8.5
13.15
5.0
1.8
φ
φ
(16.95)
7.35
1.2
6.0
1.85
3.5
(0.667)
0.289
0.047
0.236
0.073
0.138
0.052
0.472
0.656
0.335
0.518
0.197
0.071
INCHES
0.398
0.031x0.394=0.315
0.031
0.656
0.331
0.425
0.520
C 0.079
0.368
0.052
ITEM MILLIMETERS a 2.0
b c d
0.25
9.6
1.2
e f g
1.2
2.4
2.7
INCHES
0.079
0.010
0.378
0.047
0.047
0.094
0.106
TGB-044SAP-G0E
210
User's Manual U13600EJ2V0UM00
APPENDIX B EMBEDDED SOFTWARE
The following embedded software products are available for efficient program development and maintenance of the
µ
PD789046 Subseries.
MX78K0S
OS
MX78K0S is a subset OS that is based on the
µ
ITRON specification. Supplied with the
MX78K0S nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the
MX78K0S OS controls task execution order, and performs the switching process to a task to be executed.
<Caution when used under the PC environment>
MX78K0S is a DOS-based application. Use this software in the DOS pane when running it on
Windows.
µ
S
××××
MX78K0S
××××
AA13
AB13
BB13
Host Machine
PC-9800 series
IBM PC/AT compatibles
OS
Japanese Windows
Note
Japanese Windows
Note
English Windows Note
Supply Media
3.5" 2HD FD
3.5" 2HC FD
Note Also operates under the DOS environment.
User's Manual U13600EJ2V0UM00
211
[MEMO]
212
User's Manual U13600EJ2V0UM00
APPENDIX C REGISTER INDEX
C.1 Register Name Index (Alphabetic Order)
16-bit capture register 90 (TCP90) ........................................................................................................................ 87
16-bit compare register 90 (CR90) ........................................................................................................................ 87
16-bit timer counter 90 (TM90) .............................................................................................................................. 87
16-bit timer mode control register 90 (TMC90)...................................................................................................... 88
8-bit compare register 80 (CR80) ........................................................................................................................ 102
8-bit timer counter 80 (TM80) .............................................................................................................................. 102
8-bit timer mode control register 80 (TMC80)...................................................................................................... 103
[A]
Asynchronous serial interface mode register 20 (ASIM20) ......................................................... 130, 136, 139, 150
Asynchronous serial interface status register 20 (ASIS20) ......................................................................... 132, 140
[B]
Baud rate generator control register 20 (BRGC20) ............................................................................. 133, 141, 151
Buzzer output control register 90 (BZC90) ............................................................................................................ 90
[E]
External interrupt mode register 0 (INTM0) ......................................................................................................... 165
[I]
Interrupt mask flag register 0 (MK0) .................................................................................................................... 164
Interrupt mask flag register 1 (MK1) .................................................................................................................... 164
Interrupt request flag register 0 (IF0)................................................................................................................... 163
Interrupt request flag register 1 (IF1)................................................................................................................... 163
[K]
Key return mode register 00 (KRM00)................................................................................................................. 167
[O]
Oscillation settling time selection register (OSTS) .............................................................................................. 176
[P]
Port 0 (P0) ........................................................................................................................................................... 61
Port 1 (P1) ........................................................................................................................................................... 62
Port 2 (P2) ........................................................................................................................................................... 63
Port 3 (P3) ........................................................................................................................................................... 68
Port 4 (P4) ........................................................................................................................................................... 69
Port mode register 0 (PM0) ................................................................................................................................... 70
Port mode register 1 (PM1) ................................................................................................................................... 70
Port mode register 2 (PM2) ........................................................................................................................... 70, 104
Port mode register 3 (PM3) ............................................................................................................................. 70, 91
User's Manual U13600EJ2V0UM00
213
APPENDIX C REGISTER INDEX
Port mode register 4 (PM4) ....................................................................................................................................70
Processor clock control register (PCC) ..................................................................................................................77
Pull-up resistor option register 0 (PU0) ..................................................................................................................71
Pull-up resistor option register B2 (PUB2)..............................................................................................................72
[R]
Reception buffer register 20 (RXB20) ..................................................................................................................128
[S]
Serial operation mode register 20 (CSIM20) ................................................................................129, 136, 138, 149
Subclock control register (CSS) .............................................................................................................................78
Suboscillation mode register (SCKM).....................................................................................................................78
[T]
Timer clock selection register 2 (TCL2)................................................................................................................121
Transmission shift register 20 (TXS20) ................................................................................................................128
[W]
Watch timer mode control register (WTM)............................................................................................................115
Watchdog timer mode register (WDTM) ...............................................................................................................122
214
User's Manual U13600EJ2V0UM00
APPENDIX C REGISTER INDEX
C.2 Register Symbol Index (Alphabetic Order)
[M]
MK0
MK1
[O]
OSTS
[P]
P0
P1
P2
P3
P4
PCC
PM0
PM1
PM2
PM3
PM4
PU0
PUB2
[R]
RXB20
[A]
ASIM20 : Asynchronous serial interface mode register 20................................................... 130, 136, 139, 150
ASIS20 : Asynchronous serial interface status register 20 .................................................................. 132, 140
[B]
BRGC20 : Baud rate generator control register 20 ........................................................................ 133, 141, 151
BZC90 : Buzzer output control register 90.................................................................................................... 90
[C]
CR80
CR90
: 8-bit compare register 80 .............................................................................................................. 102
: 16-bit compare register 90 .............................................................................................................. 87
CSIM20 : Serial operation mode register 20......................................................................... 129, 136, 138, 149
CSS : Subclock control register ................................................................................................................ 78
[I]
IF0
IF1
INTM0
: Interrupt request flag register 0..................................................................................................... 163
: Interrupt request flag register 1..................................................................................................... 163
: External interrupt mode register 0 ................................................................................................ 165
[K]
KRM00 : Key return mode register 00 ......................................................................................................... 167
: Interrupt mask flag register 0 ........................................................................................................ 164
: Interrupt mask flag register 1 ........................................................................................................ 164
: Oscillation settling time selection register..................................................................................... 176
: Port 0 ........................................................................................................................................... 61
: Port 1 .............................................................................................................................................. 62
: Port 2 .............................................................................................................................................. 63
: Port 3 .............................................................................................................................................. 68
: Port 4 .............................................................................................................................................. 69
: Processor clock control register...................................................................................................... 77
: Port mode register 0 ....................................................................................................................... 70
: Port mode register 1 ....................................................................................................................... 70
: Port mode register 2 ............................................................................................................... 70, 104
: Port mode register 3 ................................................................................................................. 70, 91
: Port mode register 4 ....................................................................................................................... 70
: Pull-up resistor option register 0 ..................................................................................................... 71
: Pull-up resistor option register B2................................................................................................... 72
: Reception buffer register 20 ......................................................................................................... 128
User's Manual U13600EJ2V0UM00
215
APPENDIX C REGISTER INDEX
[S]
SCKM
[T]
TCL2
TCP90
TM80
TM90
TMC80
TMC90
TXS20
[W]
WDTM
WTM
: Suboscillation mode register............................................................................................................78
: Timer clock selection register 2 .....................................................................................................121
: 16-bit capture register 90.................................................................................................................87
: 8-bit timer counter 80.....................................................................................................................102
: 16-bit timer counter 90.....................................................................................................................87
: 8-bit timer mode control register 80 ...............................................................................................103
: 16-bit timer mode control register 90 ...............................................................................................88
: Transmission shift register 20........................................................................................................128
: Watchdog timer mode register.......................................................................................................122
: Watch timer mode control register.................................................................................................115
216
User's Manual U13600EJ2V0UM00
APPENDIX D REVISION HISTORY
The revision history for this manual is detailed below. "Chapter" indicates the chapter of the edition.
Edition
Second edition
Revision from Previous Edition
Completion of development of
µ
PD789046 and
µ
PD78F9046
Change of recommended connection of unused pins in processing of input/output circuit type of each pin and unused pins
Correction of 16-bit timer block diagram
Addition of cautions on rewriting CR90
Addition of cautions on 16-bit timer to Section 6.5
Addition of cautions on rewriting CR80
Addition of description of operation to operation as interval timer
Addition of description of operation to operation as external event counter
Addition of description of operation to operation as square wave output
Addition of description of operation to operation as PWM output
Correction of pins used in pseudo 3-wire mode in communication modes
Change of connection of P01 and P02 pins in example of connection of
Flashpro III in pseudo 3-wire mode (when P0 is used)
Addition of setting example of Flashpro III (PG-FP3)
Correction of product name of flash memory writing adapter in flash memory writing tools
Addition of NP-44GB-TQ as emulation probe to hardware
Addition of package drawing of conversion adapter (TBG-044SAP)
Addition of part number of MX78K0S
Chapter
Throughout
CHAPTER 2 PIN FUNCTIONS
CHAPTER 6 16-BIT TIMER
CHAPTER 7 8-BIT
TIMER/EVENT COUNTER
CHAPTER 14
µµµµ
PD78F9046
APPENDIX A
DEVELOPMENT TOOLS
APPENDIX B EMBEDDED
SOFTWARE
User's Manual U13600EJ2V0UM00
217
[MEMO]
218
User's Manual U13600EJ2V0UM00
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Key features
- 8-bit CPU
- 16-bit timer
- 8-bit timer/event counter
- Watch timer
- Watchdog timer
- Serial I/O
- Internal RAM
- Internal ROM
- Flash memory
- Low power consumption
