WM8958 Product Datasheet

w WM8958

Multi-Channel Audio Hub CODEC for Smartphones

DESCRIPTION FEATURES

The WM8958 [1] is a highly integrated ultra-low power hi-fi

CODEC designed for smartphones and other portable devices rich in multimedia features.

An integrated stereo class D/AB speaker driver and class W headphone driver minimize power consumption during audio playback.

The device requires only two voltage supplies, with all other internal supply rails generated from integrated LDOs.

Stereo full duplex asynchronous sample rate conversion and multi-channel digital mixing combined with powerful analogue mixing allow the device to support a huge range of different architectures and use cases.

A multiband compressor and programmable parametric EQ provide volume maximisation and speaker compensation in the digital playback paths. The dynamic range controller can be used in record or playback paths for maintaining a constant signal level, maximizing loudness and protecting speakers against overloading and clipping.

A smart digital microphone interface provides power regulation, a low jitter clock output and decimation filters for up to four digital microphones. Microphone activity detection with interrupt is available. Impedance sensing and measurement is provided for external accessory / push-button detection.

 24-bit 4-channel hi-fi DAC and 2-channel hi-fi ADC

 100dB SNR during DAC playback (‘A’ weighted)

 Smart MIC interface

- Power, clocking and data input for up to four digital MICs

- High performance analogue MIC interface

- MIC activity detect & interrupt allows processor to sleep

- Impedance sensing for accessory / push-button detection

 2W stereo (2 x 2W) class D/AB speaker driver

 Capless Class W headphone drivers

- Integrated charge pump

- 5.3mW total power for DAC playback to headphones

 4 Line outputs (single-ended or differential)

 BTL Earpiece driver

 Digital audio interfaces for multi-processor architecture

- Asynchronous stereo duplex sample rate conversion

- Powerful mixing and digital loopback functions

 ReTune TM Mobile 5-band, 6-channel parametric EQ

 Multiband compressor and dynamic range controller

 Dual FLL provides all necessary clocks

- Self-clocking modes allow processor to sleep

- All standard sample rates from 8kHz to 96kHz

 Active noise reduction circuits

- DC offset correction removes pops and clicks

- Ground loop noise cancellation

 Integrated LDO regulators

 72-ball W-CSP package (4.516 x 4.258 x 0.698mm)

APPLICATIONS Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. Active ground loop noise rejection and DC offset correction help prevent pop noise and suppress ground noise on the headphone outputs.

 Smartphones and music phones navigation

 Tablets

 eBooks

 Portable Media Players

WOLFSON MICROELECTRONICS plc

[1] This product is protected by Patents US 7,622,984, US 7,626,445,US 7,765,019 and GB 2,432,765

Pre-Production, August 2012, Rev 3.4

WM8958

Pre-Production

TABLE OF CONTENTS

DESCRIPTION ....................................................................................................... 1

FEATURES ............................................................................................................ 1

APPLICATIONS ..................................................................................................... 1

TABLE OF CONTENTS ......................................................................................... 2

BLOCK DIAGRAM ................................................................................................ 7

PIN CONFIGURATION .......................................................................................... 8

ORDERING INFORMATION .................................................................................. 8

PIN DESCRIPTION ................................................................................................ 9

ABSOLUTE MAXIMUM RATINGS ...................................................................... 12

RECOMMENDED OPERATING CONDITIONS ................................................... 13

THERMAL PERFORMANCE ............................................................................... 14

ELECTRICAL CHARACTERISTICS ................................................................... 15

INPUT SIGNAL LEVEL .................................................................................................. 15

INPUT PIN RESISTANCE .............................................................................................. 16

PROGRAMMABLE GAINS ............................................................................................. 18

OUTPUT DRIVER CHARACTERISTICS ....................................................................... 19

ADC INPUT PATH PERFORMANCE ............................................................................. 20

DAC OUTPUT PATH PERFORMANCE ......................................................................... 21

BYPASS PATH PERFORMANCE .................................................................................. 24

MULTI-PATH CROSSTALK ........................................................................................... 26

DIGITAL INPUT / OUTPUT ............................................................................................ 28

DIGITAL FILTER CHARACTERISTICS ......................................................................... 28

MICROPHONE BIAS CHARACTERISTICS ................................................................... 29

MISCELLANEOUS CHARACTERISTICS ...................................................................... 30

TERMINOLOGY ............................................................................................................. 31

TYPICAL PERFORMANCE ................................................................................. 32

TYPICAL POWER CONSUMPTION .............................................................................. 32

TYPICAL SIGNAL LATENCY ......................................................................................... 33

SPEAKER DRIVER PERFORMANCE ........................................................................... 34

SIGNAL TIMING REQUIREMENTS .................................................................... 35

SYSTEM CLOCKS & FREQUENCY LOCKED LOOP (FLL) .......................................... 35

AUDIO INTERFACE TIMING ......................................................................................... 36

DIGITAL MICROPHONE (DMIC) INTERFACE TIMING .................................................................................................. 36

DIGITAL AUDIO INTERFACE - MASTER MODE ........................................................................................................... 37

DIGITAL AUDIO INTERFACE - SLAVE MODE ............................................................................................................... 38

DIGITAL AUDIO INTERFACE - TDM MODE .................................................................................................................. 39

CONTROL INTERFACE TIMING ................................................................................... 40

DEVICE DESCRIPTION ...................................................................................... 41

INTRODUCTION ............................................................................................................ 41

ANALOGUE INPUT SIGNAL PATH ............................................................................... 43

MICROPHONE INPUTS .................................................................................................................................................. 44

MICROPHONE BIAS CONTROL .................................................................................................................................... 44

MICROPHONE ACCESSORY DETECT ......................................................................................................................... 46

LINE AND VOICE CODEC INPUTS ................................................................................................................................ 46

INPUT PGA ENABLE ...................................................................................................................................................... 47

INPUT PGA CONFIGURATION ...................................................................................................................................... 48

INPUT PGA VOLUME CONTROL ................................................................................................................................... 49

INPUT MIXER ENABLE ................................................................................................................................................... 52

INPUT MIXER CONFIGURATION AND VOLUME CONTROL ....................................................................................... 52

DIGITAL MICROPHONE INTERFACE .......................................................................... 56

DIGITAL PULL-UP AND PULL-DOWN ............................................................................................................................ 59

PP, August 2012, Rev 3.4

w

2

Pre-Production

WM8958

ANALOGUE TO DIGITAL CONVERTER (ADC) ............................................................ 59

ADC CLOCKING CONTROL ........................................................................................................................................... 60

DIGITAL CORE ARCHITECTURE ................................................................................. 61

DIGITAL MIXING ............................................................................................................ 63

AUDIO INTERFACE 1 (AIF1) OUTPUT MIXING ............................................................................................................. 64

DIGITAL SIDETONE MIXING .......................................................................................................................................... 65

DIGITAL SIDETONE VOLUME AND FILTER CONTROL ............................................................................................... 65

DAC OUTPUT DIGITAL MIXING ..................................................................................................................................... 67

AUDIO INTERFACE 2 (AIF2) DIGITAL MIXING ............................................................................................................. 68

ULTRASONIC (4FS) AIF OUTPUT MODE ...................................................................................................................... 69

MULTIBAND COMPRESSOR (MBC) ............................................................................ 70

RMS LIMITER .................................................................................................................................................................. 71

MBC CLOCKING CONTROL ........................................................................................................................................... 71

MBC CONTROL SEQUENCES ....................................................................................................................................... 72

DYNAMIC RANGE CONTROL (DRC) ........................................................................... 75

DRC COMPRESSION / EXPANSION / LIMITING ........................................................................................................... 76

GAIN LIMITS .................................................................................................................................................................... 78

DYNAMIC CHARACTERISTICS ..................................................................................................................................... 79

ANTI-CLIP CONTROL ..................................................................................................................................................... 79

QUICK RELEASE CONTROL ......................................................................................................................................... 79

SIGNAL ACTIVITY DETECT ........................................................................................................................................... 79

DRC REGISTER CONTROLS ......................................................................................................................................... 80

RETUNE TM MOBILE PARAMETRIC EQUALIZER (EQ) ................................................ 89

DEFAULT MODE (5-BAND PARAMETRIC EQ) ............................................................................................................. 90

RETUNE TM MOBILE MODE............................................................................................................................................. 92

EQ FILTER CHARACTERISTICS ................................................................................................................................... 93

3D STEREO EXPANSION ............................................................................................. 94

DIGITAL VOLUME AND FILTER CONTROL ................................................................. 95

AIF1 - OUTPUT PATH VOLUME CONTROL .................................................................................................................. 95

AIF1 - OUTPUT PATH HIGH PASS FILTER ................................................................................................................... 97

AIF1 - INPUT PATH VOLUME CONTROL ...................................................................................................................... 99

AIF1 - INPUT PATH SOFT MUTE CONTROL .............................................................................................................. 102

AIF1 - INPUT PATH NOISE GATE CONTROL ............................................................................................................. 103

AIF1 - INPUT PATH MONO MIX CONTROL ................................................................................................................. 104

AIF2 - OUTPUT PATH VOLUME CONTROL ................................................................................................................ 104

AIF2 - OUTPUT PATH HIGH PASS FILTER ................................................................................................................. 105

AIF2 - INPUT PATH VOLUME CONTROL .................................................................................................................... 106

AIF2 - INPUT PATH SOFT MUTE CONTROL .............................................................................................................. 106

AIF2 - INPUT PATH NOISE GATE CONTROL ............................................................................................................. 107

AIF2 - INPUT PATH MONO MIX CONTROL ................................................................................................................. 108

DIGITAL TO ANALOGUE CONVERTER (DAC) .......................................................... 109

DAC CLOCKING CONTROL ......................................................................................................................................... 109

DAC DIGITAL VOLUME ................................................................................................................................................ 111

DAC SOFT MUTE AND SOFT UN-MUTE ..................................................................................................................... 114

ANALOGUE OUTPUT SIGNAL PATH ......................................................................... 116

OUTPUT SIGNAL PATHS ENABLE .............................................................................................................................. 117

HEADPHONE SIGNAL PATHS ENABLE ...................................................................................................................... 119

OUTPUT MIXER CONTROL ......................................................................................................................................... 121

SPEAKER MIXER CONTROL ....................................................................................................................................... 125

OUTPUT SIGNAL PATH VOLUME CONTROL ............................................................................................................. 128

SPEAKER BOOST MIXER ............................................................................................................................................ 133

EARPIECE DRIVER MIXER .......................................................................................................................................... 133

LINE OUTPUT MIXERS ................................................................................................................................................ 134 w PP, August 2012, Rev 3.4

3

WM8958

Pre-Production

CHARGE PUMP ........................................................................................................... 138

DC SERVO ................................................................................................................... 140

DC SERVO ENABLE AND START-UP ......................................................................................................................... 140

DC SERVO ACTIVE MODES ........................................................................................................................................ 142

GPIO / INTERRUPT OUTPUTS FROM DC SERVO ..................................................................................................... 143

ANALOGUE OUTPUTS ............................................................................................... 144

SPEAKER OUTPUT CONFIGURATIONS ..................................................................................................................... 144

HEADPHONE OUTPUT CONFIGURATIONS ............................................................................................................... 147

EARPIECE DRIVER OUTPUT CONFIGURATIONS ..................................................................................................... 148

LINE OUTPUT CONFIGURATIONS .............................................................................................................................. 148

EXTERNAL ACCESSORY DETECTION ..................................................................... 151

ACCESSORY DETECTION WITH LOW FREQUENCY SYSCLK ................................................................................. 155

GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 156

GPIO CONTROL ........................................................................................................................................................... 156

GPIO FUNCTION SELECT ........................................................................................................................................... 157

BUTTON DETECT (GPIO INPUT) ................................................................................................................................. 159

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT) .................................................................................................. 159

INTERRUPT (IRQ) STATUS OUTPUT .......................................................................................................................... 159

OVER-TEMPERATURE DETECTION ........................................................................................................................... 159

MICROPHONE ACCESSORY STATUS DETECTION .................................................................................................. 160

FREQUENCY LOCKED LOOP (FLL) LOCK STATUS OUTPUT .................................................................................. 160

SAMPLE RATE CONVERTER (SRC) LOCK STATUS OUTPUT ................................................................................. 160

DYNAMIC RANGE CONTROL (DRC) SIGNAL ACTIVITY DETECTION ...................................................................... 161

CONTROL WRITE SEQUENCER STATUS DETECTION ............................................................................................ 163

DIGITAL CORE FIFO ERROR STATUS DETECTION.................................................................................................. 163

OPCLK CLOCK OUTPUT .............................................................................................................................................. 163

FLL CLOCK OUTPUT .................................................................................................................................................... 164

INTERRUPTS .............................................................................................................. 165

DIGITAL AUDIO INTERFACE ...................................................................................... 170

MASTER AND SLAVE MODE OPERATION ................................................................................................................. 171

OPERATION WITH TDM ............................................................................................................................................... 171

AUDIO DATA FORMATS (NORMAL MODE) ................................................................................................................ 172

AUDIO DATA FORMATS (TDM MODE) ....................................................................................................................... 175

DIGITAL AUDIO INTERFACE CONTROL ................................................................... 178

AIF1 - MASTER / SLAVE AND TRI-STATE CONTROL ................................................................................................ 178

AIF1 - SIGNAL PATH ENABLE ..................................................................................................................................... 179

AIF1 - BCLK AND LRCLK CONTROL ........................................................................................................................... 179

AIF1 - DIGITAL AUDIO DATA CONTROL ..................................................................................................................... 182

AIF1 - MONO MODE ..................................................................................................................................................... 183

AIF1 - COMPANDING ................................................................................................................................................... 184

AIF1 - LOOPBACK ........................................................................................................................................................ 186

AIF1 - DIGITAL PULL-UP AND PULL-DOWN ............................................................................................................... 186

AIF2 - MASTER / SLAVE AND TRI-STATE CONTROL ................................................................................................ 187

AIF2 - SIGNAL PATH ENABLE ..................................................................................................................................... 188



AIF2 - MONO MODE ..................................................................................................................................................... 193

AIF2 - COMPANDING ................................................................................................................................................... 193

AIF2 - LOOPBACK ........................................................................................................................................................ 193

AIF2 - DIGITAL PULL-UP AND PULL-DOWN ............................................................................................................... 194

AIF3 - SIGNAL PATH CONFIGURATION AND TRI-STATE CONTROL ....................................................................... 195



AIF3 - COMPANDING ................................................................................................................................................... 199

AIF3 - LOOPBACK ........................................................................................................................................................ 199 w PP, August 2012, Rev 3.4

4

Pre-Production

WM8958

CLOCKING AND SAMPLE RATES .............................................................................. 200

AIF1CLK ENABLE ......................................................................................................................................................... 201

AIF1 CLOCKING CONFIGURATION ............................................................................................................................ 202

AIF2CLK ENABLE ......................................................................................................................................................... 204

AIF2 CLOCKING CONFIGURATION ............................................................................................................................ 204

MISCELLANEOUS CLOCK CONTROLS ...................................................................................................................... 206

BCLK AND LRCLK CONTROL ...................................................................................................................................... 209

CONTROL INTERFACE CLOCKING ............................................................................................................................ 211

FREQUENCY LOCKED LOOP (FLL) ............................................................................................................................ 211

FREE-RUNNING FLL CLOCK ....................................................................................................................................... 217

GPIO OUTPUTS FROM FLL ......................................................................................................................................... 218

EXAMPLE FLL CALCULATION ..................................................................................................................................... 219

EXAMPLE FLL SETTINGS ............................................................................................................................................ 220

SAMPLE RATE CONVERSION ................................................................................... 221

SAMPLE RATE CONVERTER 1 (SRC1) ...................................................................................................................... 221

SAMPLE RATE CONVERTER 2 (SRC2) ...................................................................................................................... 221

SAMPLE RATE CONVERTER RESTRICTIONS .......................................................................................................... 221

SAMPLE RATE CONVERTER CONFIGURATION ERROR INDICATION ................................................................... 222

CONTROL INTERFACE ............................................................................................... 224

CONTROL WRITE SEQUENCER ................................................................................ 227

INITIATING A SEQUENCE ............................................................................................................................................ 227

PROGRAMMING A SEQUENCE .................................................................................................................................. 228

DEFAULT SEQUENCES ............................................................................................................................................... 230

POP SUPPRESSION CONTROL ................................................................................ 237

DISABLED LINE OUTPUT CONTROL .......................................................................................................................... 237

LINE OUTPUT DISCHARGE CONTROL ...................................................................................................................... 238

VMID REFERENCE DISCHARGE CONTROL .............................................................................................................. 238

INPUT VMID CLAMPS .................................................................................................................................................. 238

LDO REGULATORS .................................................................................................... 239

REFERENCE VOLTAGES AND MASTER BIAS ......................................................... 241

POWER MANAGEMENT ............................................................................................. 243

THERMAL SHUTDOWN .............................................................................................. 248

POWER ON RESET..................................................................................................... 249

QUICK START-UP AND SHUTDOWN ........................................................................ 251

SOFTWARE RESET AND DEVICE ID ......................................................................... 252

REGISTER MAP ................................................................................................ 253

REGISTER BITS BY ADDRESS .................................................................................. 265

APPLICATIONS INFORMATION ...................................................................... 360

RECOMMENDED EXTERNAL COMPONENTS .......................................................... 360

AUDIO INPUT PATHS ................................................................................................................................................... 360

HEADPHONE OUTPUT PATH ...................................................................................................................................... 361

EARPIECE DRIVER OUTPUT PATH ............................................................................................................................ 362

LINE OUTPUT PATHS .................................................................................................................................................. 362

POWER SUPPLY DECOUPLING ................................................................................................................................. 363

CHARGE PUMP COMPONENTS ................................................................................................................................. 364

MICROPHONE BIAS CIRCUIT ..................................................................................................................................... 364

EXTERNAL ACCESSORY DETECTION COMPONENTS ............................................................................................ 366

CLASS D SPEAKER CONNECTIONS .......................................................................................................................... 367

RECOMMENDED EXTERNAL COMPONENTS DIAGRAM ......................................................................................... 368

DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS ................................. 370

PCB LAYOUT CONSIDERATIONS ............................................................................. 373

CLASS D LOUDSPEAKER CONNECTION .................................................................................................................. 373 w PP, August 2012, Rev 3.4

5

WM8958

Pre-Production

PACKAGE DIMENSIONS .................................................................................. 374

IMPORTANT NOTICE ....................................................................................... 375

ADDRESS: ................................................................................................................... 375

REVISION HISTORY ......................................................................................... 376

w PP, August 2012, Rev 3.4

6

Pre-Production

BLOCK DIAGRAM w

DMICDAT2

DMICDAT1

WM8958

V

VS, NG

VS, NG

V

CPVDD

CPGND

LINEOUTFB

HPOUT1FB

SPKMODE

ADDR

SDA

SCLK

BCLK2

BCLK1

LRCLK2

LRCLK1

GPIO11/BCLK3

GPIO10/LRCLK3

GPIO8/DACDAT3

GPIO9/ADCDAT3

ADCDAT2

GPIO6/ADCLRCLK2

DACDAT2

LRCLK2

BCLK2

GPIO1/ADCLRCLK1

ADCDAT1

DACDAT1

LRCLK1

BCLK1

MCLK1

MCLK2

AVDD1

VMIDC

AGND

REFGND

LDO2ENA

LDO1ENA

VREFC


7

WM8958

PIN CONFIGURATION

Pre-Production

ORDERING INFORMATION

ORDER CODE

WM8958ECS/R

TEMPERATURE RANGE PACKAGE MOISTURE

SENSITIVITY LEVEL

-40 C to +85C 72-ball

(Pb-free, Tape and reel)

PEAK SOLDERING

TEMPERATURE

MSL1 260 C

Note:

Reel quantity = 5000 w PP, August 2012, Rev 3.4

8

Pre-Production

WM8958

PIN DESCRIPTION

A description of each pin on the WM8958 is provided below.

Note that a table detailing the associated power domain for every input and output pin is provided on the following page.

Note that, where multiple pins share a common name, these pins should be tied together on the PCB.

PIN NO NAME TYPE DESCRIPTION

Audio interface 1 ADC digital audio data

Audio interface 2 ADC digital audio data

2-wire (I2C) address select

D7, E6 AGND Supply Analogue ground (Return path for AVDD1, AVDD2 and LDO1VDD)

Analogue core supply / LDO1 Output

Output

Bandgap reference, analogue class D and FLL supply

F2 BCLK1 Audio interface 1 bit clock

G3 BCLK2 Audio interface 2 bit clock

Charge pump fly-back capacitor pin

Charge pump fly-back capacitor pin

Charge pump ground (Return path for CPVDD)

Charge pump supply

Charge pump negative supply decoupling pin (HPOUT1L, HPOUT1R)

Charge pump positive supply decoupling pin (HPOUT1L, HPOUT1R)

Audio interface 1 DAC digital audio data

Audio interface 2 DAC digital audio data

Digital buffer (I/O) supply (core functions and Audio Interface 1)

Digital buffer (I/O) supply (for Audio Interface 2)

Digital buffer (I/O) supply (for Audio Interface 3)

Digital core supply / LDO2 output

Output

Digital ground (Return path for DCVDD, DBVDD1, DBVDD2, DBVDD3)

Digital MIC clock output

H1 GPIO1/ General Purpose pin GPIO 1 /

ADCLRCLK1 Audio interface 1 ADC left / right clock

F5 GPIO10/ General Purpose pin GPIO 10 /

LRCLK3 Audio interface 3 left / right clock

E5 GPIO11/ General Purpose pin GPIO 11 /

BCLK3 Audio interface 3 bit clock


ADCLRCLK2 Audio interface 2 ADC left / right clock

G4 GPIO8/ General Purpose pin GPIO 8 /

DACDAT3 Audio interface 3 DAC digital audio data


ADCDAT3 Audio interface 3 ADC digital audio data

HPOUT1L and HPOUT1R ground loop noise rejection feedback

Left headphone output

Right headphone output

Earpiece speaker inverted output

Earpiece speaker non-inverted output

Left channel single-ended MIC input /

Left channel negative differential MIC input

Left channel line input /

Left channel positive differential MIC input w PP, August 2012, Rev 3.4

9

WM8958

Pre-Production

PIN NO NAME

DMICDAT1

DMICDAT2

TYPE

Digital Input

Digital Input

DESCRIPTION

Right channel single-ended MIC input /

Right channel negative differential MIC input

Right channel line input /

Right channel positive differential MIC input


Left channel negative differential MIC input /

Digital MIC data input 1


Left channel positive differential MIC input /

Mono differential negative input (RXVOICE -)

Right channel line input /

Right channel negative differential MIC input /

Digital MIC data input 2


Left channel positive differential MIC input /

Mono differential positive input (RXVOICE +)

Enable pin for LDO1

Supply for LDO1

Enable pin for LDO2

Negative mono line output / Positive left or right line output

Positive mono line output / Positive left line output

Negative mono line output / Positive left or right line output

Positive mono line output / Positive left line output

Line output ground loop noise rejection feedback

D4 LRCLK1 Audio interface 1 left / right clock

H2 LRCLK2 Audio interface 2 left / right clock

Master clock 1

Master clock 2

Microphone bias 1

Microphone bias 2

Microphone & accessory sense input

Analogue ground

Control interface clock input

G2 SDA Control interface data input and output / acknowledge output

Ground for speaker driver (Return path for SPKVDD1)

Ground for speaker driver (Return path for SPKVDD2)

Mono / Stereo speaker mode select

Left speaker negative output

Left speaker positive output

Right speaker negative output

Right speaker positive output

Supply for speaker driver 1 (Left channel)

Supply for speaker driver 2 (Right channel)

Midrail voltage decoupling capacitor

Bandgap reference decoupling capacitor w PP, August 2012, Rev 3.4

10

Pre-Production

The following table identifies the power domain and ground reference associated with each of the input / output pins.

PIN NO NAME POWER DOMAIN GROUND DOMAIN

WM8958

CPGND

CPGND

MICBIAS1 (DMICDAT1)

MICBIAS1 (DMICDAT2)

AGND

AGND (IN2RN) or

DGND (DMICDAT2) w PP, August 2012, Rev 3.4

11

WM8958

Pre-Production

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30 C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30 C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30 C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

Supply voltages (AVDD1, DBVDD2, DBVDD3)

Supply voltages (AVDD2, DCVDD, DBVDD1)

Supply voltages (CPVDD)

Supply voltages (SPKVDD1, SPKVDD2, LDO1VDD)

Voltage range digital inputs (DBVDD1 domain)



Voltage range digital inputs (DMICDATn)

Voltage range analogue inputs (AVDD1 domain)

Voltage range analogue inputs (MICDET, LINEOUTFB)

Voltage range analogue inputs (HPOUT1FB)

Ground (DGND, CPGND, SPKGND1, SPKGND2, REFGND, HP2GND)

Operating temperature range, T

A

Junction temperature, T

JMAX

Storage temperature after soldering

-0.3V +4.5V

-0.3V +2.5V

-0.3V +2.2V

-0.3V +7.0V

AGND - 0.3V

AGND - 0.3V

DBVDD1 + 0.3V

DBVDD2 + 0.3V

AGND - 0.3V

AGND - 0.3V

AGND - 0.3V

AGND - 0.3V

AGND - 0.3V

DBVDD3 + 0.3V

AVDD1 + 0.3V

AVDD1 + 0.3V

AVDD1 + 0.3V

AGND + 0.3V

AGND - 0.3V AGND + 0.3V

-40ºC +85ºC

-40ºC +150ºC

-65ºC +150ºC w PP, August 2012, Rev 3.4

12

Pre-Production

RECOMMENDED OPERATING CONDITIONS

WM8958

Digital supply range (Core)

See notes 7, 8

Digital supply range (I/O)

Digital supply range (I/O)

Analogue supply 1 range

See notes 3, 4, 5, 6

Analogue supply 2 range

Charge Pump supply range

Speaker supply range

LDO1 supply range

Ground

DBVDD2, DBVDD3

AVDD1

1.62 1.8 3.6 V

2.4 3.0 3.3 V

LDO1VDD 2.7 5.0 5.5 V

DGND, AGND, CPGND,

SPKGND1, SPKGND2,

REFGND, HP2GND

0 V

All supplies 1 s Power supply rise time

See notes 9, 10, 11

Operating temperature range T

A

-40

Notes:

1. Analogue, digital and speaker grounds must always be within 0.3V of AGND.

2. There is no power sequencing requirement; the supplies may be enabled in any order.

3. AVDD1 must be less than or equal to SPKVDD1 and SPKVDD2.

4. An internal LDO (powered by LDO1VDD) can be used to provide the AVDD1 supply.

5. When AVDD1 is supplied externally (not from LDO1), the LDO1VDD voltage must be greater than or equal to AVDD1.

6. The WM8958 can operate with AVDD1 tied to 0V; power consumption may be reduced, but the analogue audio functions will not be supported.

7. An internal LDO (powered by DBVDD1) can be used to provide the DCVDD supply.

8. When DCVDD is supplied externally (not from LDO2), the DBVDD1 voltage must be greater than or equal to DCVDD.

9. DCVDD and AVDD1 minimum rise times do not apply when these domains are powered using the internal LDOs.

10. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin.

However, Wolfson strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed (see “Applications Information” section).

11. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin. w PP, August 2012, Rev 3.4

13

WM8958

Pre-Production

THERMAL PERFORMANCE

Thermal analysis should be performed in the intended application to prevent the WM8958 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the GND balls through thermal vias and into a large ground plane will aid heat extraction.

Three main heat transfer paths exist to surrounding air as illustrated below in Figure 1:

- Package top to air (radiation).

- Package bottom to PCB (radiation).

- Package balls to PCB (conduction).

Figure 1 Heat Transfer Paths

The temperature rise T

R

is given by T

R

= P

D

* Ө

JA

- P

D

is the power dissipated in the device.

- Ө

JA

is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. Ө

JA

is determined with reference to JEDEC standard JESD51-9.

The junction temperature T

J

is given by T

J

= T

A

+T

R

, where T

A

is the ambient temperature.

Operating temperature range

Operating junction temperature

Thermal Resistance

T

A

-40

T

J

-40

Ө

JA

Note:

Junction temperature is a function of ambient temperature and of the device operating conditions. The ambient temperature limits and junction temperature limits must both be observed. w PP, August 2012, Rev 3.4

14

Pre-Production

WM8958

ELECTRICAL CHARACTERISTICS

INPUT SIGNAL LEVEL

Test Conditions

AVDD1 = 3.0V.

With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions.

A1 Full-Scale PGA Input

Signal Level

See notes 1, 2, 3 and 4

Single-ended PGA input 1.0 Vrms

0 dBV

Differential PGA input 1.0 Vrms

0 dBV

A2 Full-Scale Line Input

Signal Level

See notes 1, 2, 3 and 4

Single-ended Line input to

MIXINL/R, SPKMIXL/R or

MIXOUTL/R mixers

1.0

0

Vrms dBV

Differential mono line input on VRXP/VRXN to

RXVOICE or Direct Voice paths to speaker outputs or earpiece output

1.0

0

Notes:

1. The full-scale input signal level changes in proportion with AVDD1. It is calculated as AVDD1/3.0.

2. When mixing line inputs, input PGA outputs and DAC outputs the total signal must not exceed 1.0Vrms (0dBV).

3. A 1.0Vrms differential signal equates to 0.5Vrms/-6dBV per input.

4. A sinusoidal input signal is assumed.

Vrms dBV w PP, August 2012, Rev 3.4

15

WM8958

Pre-Production

INPUT PIN RESISTANCE

Test Conditions

T

A

= +25 o C.


B1

B2

B3

PGA Input Resistance

Differential Mode

See note 5

See “Applications

Information” for details of

Input resistance at all

PGA Gain settings.

PGA Input Resistance

Single-Ended Mode

See note 5

See “Applications

Information” for details of

Input resistance at all

PGA Gain settings.

Line Input Resistance

See note 5

Gain = -16.5dB

(INnx_VOL=00h)

Gain = 0dB

(INnx_VOL=0Bh)

Gain = +30dB

(INnx_VOL=1Fh)

Gain = -16.5dB

(INnx_VOL=00h)

Gain = 0dB

(INnx_VOL=0Bh)

Gain = +30dB

(INnx_VOL=1Fh)

IN1LP to MIXINL, or

IN1RP to MIXINR

Gain = -12dB

(IN1xP_MIXINx_VOL=001)

IN1LP to MIXINL, or

IN1RP to MIXINR

Gain = 0dB


IN1LP to MIXINL, or

IN1RP to MIXINR

Gain = +6dB


IN1LP to MIXINL, or

IN1RP to MIXINR

Gain = +15dB

(IN1xP_MIXINx_VOL=111,

IN1xP_MIXINx_BOOST=1)

IN1LP to SPKMIXL, or

IN1RP to SPKMIXR

(SPKATTN = -12dB)

IN1LP to SPKMIXL, or

IN1RP to SPKMIXR

(SPKATTN = 0dB)

IN2LN, IN2RN, IN2LP or

IN2RP to MIXOUTL or

MIXOUTR

Gain = -9dB

(*MIXOUTx_VOL=011)

IN2LN, IN2RN, IN2LP or

IN2RP to MIXOUTL or

MIXOUTR

Gain = 0dB

(*MIXOUTx_VOL=000) w

53 k 

25 k 

1.3 k 

58 k 

36 k 

2.5 k 

56 k 

17 k 

9.8 k 

3.7 k 

89 k 

27 k 

43 k 

18 k 


16

Pre-Production

WM8958

Test Conditions

T

A

= +25 o C.


RXVOICE to MIXINL or

MIXINR

Gain = -12dB

(IN2LRP_MIXINx_VOL=001)


MIXINR

Gain = 0dB



MIXINR

Gain = +6dB


Direct Voice to Earpiece

Gain = -6dB

(HPOUT2_VOL=1)

Direct Voice to Earpiece

Gain = 0dB

(HPOUT2_VOL=0)

Direct Voice to Speaker

Gain = 0dB

(SPKOUTx_BOOST=000)


Gain = +6dB

(SPKOUTx_BOOST=100)


Gain = +9dB

(SPKOUTx_BOOST=110)


Gain = +12dB

(SPKOUTx_BOOST=111)

48 k

12 k

6.0 k

20 kΩ

10 kΩ

170 kΩ

85 kΩ

60 kΩ

43 kΩ

Note 5: Input resistance will be seen in parallel with the resistance of other enabled input paths from the same pins





 w PP, August 2012, Rev 3.4

17

WM8958

Pre-Production

PROGRAMMABLE GAINS

Test Conditions

The following electrical characteristics are valid across the full range of recommended operating conditions.

Input PGAs (IN1L, IN2L, IN1R and IN2R)

C1 Minimum Programmable Gain

C2

C3

Maximum Programmable Gain

Programmable Gain Step Size

Input Mixers (MIXINL and MIXINR)


C7 Maximum Programmable Gain

C8

C9


Minimum Programmable Gain


C11 Programmable Gain Step Size


Maximum Programmable Gain

Guaranteed monotonic

Input PGA signal paths

Direct IN1xP input signal paths

(Note the available gain settings are

-12, -9, -6, -3, 0, +3, +6, +15dB)

MIXOUTx Record signal paths

-16.5

+30 dB

1.5 dB

0 dB dB

+30 dB

30 dB

-12 dB

+15 dB

3 dB

-12 dB

+6 dB

C12





Output Mixers (MIXOUTL and MIXOUTR)


RXVOICE (VRXP-VRXN) signal paths

3 dB

-12 dB

+6 dB

3 dB



Speaker Mixers (SPKMIXL and SPKMIXR)



0 dB

3 dB



Line Output Drivers (LINEOUT1NMIX, LINEOUT1PMIX, LINEOUT2NMIX and LINEOUT2PMIX)

0 dB

3 dB

Output PGAs (HPOUT1LVOL, HPOUT1RVOL, MIXOUTLVOL, MIXOUTRVOL, SPKLVOL and SPKRVOL)



Guaranteed monotonic -57 dB

+6 dB

1 dB




0 dB

6 dB

Earpiece Driver (HPOUT2MIX)


C34 Maximum Programmable Gain 0 dB

6 dB C35 Programmable Gain Step Size

Speaker Output Drivers (SPKOUTLBOOST and SPKOUTRBOOST)



(Note the available gain settings are

0, +1.5, +3, +4.5, +6, +7.5, +9, +12dB)


0 dB

+12 dB

1.5 dB w PP, August 2012, Rev 3.4

18

Pre-Production

OUTPUT DRIVER CHARACTERISTICS

Test Conditions


WM8958

Line Output Driver (LINEOUT1P, LINEOUT1N, LINEOUT2P, LINEOUT2N)

Output discharge resistance

Direct connection

Connection via 1kΩ series resistor

LINEOUTn_DISCH=1, VROI=0

LINEOUTn_DISCH=1, VROI=1,

LINEOUTn_ENA=0

Headphone Output Driver (HPOUT1L, HPOUT1R)

Normal operation

DC offset across load

Earpiece Output Driver (HPOUT2L, HPOUT2R)

Device survival with load applied indefinitely

(see note 6)

DC Servo complete

500 Ω

15

100

8

100

2000 pF kΩ

Ω mΩ

2 nF

TBD mV

Direct connection


Speaker Output Driver (SPKOUTLP, SPKOUTLN, SPKOUTRP, SPKOUTRN)

Stereo Mode (SPKMODE=0), Class AB


SPKVDD leakage current

Stereo Mode (SPKMODE=0), Class D

Mono Mode (SPKMODE=1)

Sum of I

SPKVDD1

+ I

SPKVDD2

8

4

4

200 pF

±5 mV

Ω

TBD pF

±5 mV

1 µA

Note 6: In typical applications, the PCB trace resistance, jack contact resistance and ESR of any series passive components

(eg. inductor or ferrite bead) are sufficient to provide this minimum resistance; additional series components are not required. w PP, August 2012, Rev 3.4

19

WM8958

Pre-Production

ADC INPUT PATH PERFORMANCE

Test Conditions

AVDD1=3.0V (powered from LDO1), DCVDD=1.2V (powered from LDO2), AVDD2=DBVDD1=DBVDD2=DBVDD3=CPVDD=1.8V,

LDO1VDD=SPKVDD1=SPKVDD2=5V, DGND=AGND=CPGND=SPKGND1=SPKGND2=HP2GND=0V,

T

A

= +25 o C, 1kHz sinusoidal signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.

D1

D2

D3

D4

Line Inputs to ADC via MIXINL and MIXINR

SNR

THD

THD+N

A-weighted

-1dBV input

-1dBV input

Channel Separation

(L/R)

PSRR (all supplies) 100mV (pk-pk)

217Hz

Record Path (DACs to ADCs via MIXINL and MIXINR)

SNR

THD

THD+N

Channel Separation

(L/R)

A-weighted

-1dBFS input

-1dBFS input

Input PGAs to ADC via MIXINL or MIXINR

SNR A-weighted

THD

THD+N

-1dBV input

-1dBV input

Channel Separation

(L/R)

PSRR (AVDD1) 100mV (pk-pk)

217Hz

RXVOICE to ADCL or ADCR

SNR

THD

THD+N

A-weighted

-1dBV input

-1dBV input

94 dB

-83 dB

-81 dB

73 dB

92 dB

-74 dB

-72 dB

84 95 dB

-82 -72 dB

-80 -70 dB

97 dB

94 dB

-84 dB

-82 dB w PP, August 2012, Rev 3.4

20

Pre-Production

WM8958

DAC OUTPUT PATH PERFORMANCE

Test Conditions



T

A


E1

E2

E5

E6

DAC to Single-Ended Line Output (Load = 10k  // 50pF)

SNR A-weighted

THD

THD+N

0dBFS input

0dBFS input

Channel Separation

(L/R)


217Hz

LINEOUTFB rejection LINEOUTn_FB=1,

100mV (pk-pk)

217Hz

DAC to Differential Line Output (Load = 10k  // 50pF)

SNR A-weighted

THD

THD+N

0dBFS input

0dBFS input

Channel Separation

(L/R)


217Hz

DAC to Headphone on HPOUT1L or HPOUT1R (Load = 32 )

SNR (A-weighted) DAC_OSR128=1

DAC_OSR128=0

THD P

O

=20mW

THD+N P

O

=20mW

THD P

O

=5mW

THD+N P

O

=5mW

Channel Separation

(L/R)


217Hz

HPOUT1FB rejection 100mV (pk-pk)

217Hz

DAC to Headphone on HPOUT1L or HPOUT1R (Load = 16 )

SNR (A-weighted) DAC_OSR128=1

DAC_OSR128=0

THD P

O

=20mW

THD+N P

O

=20mW

THD P

O

=5mW

THD+N P

O

=5mW

Channel Separation

(L/R)

PSRR (all supplies)

HPOUT1FB rejection

100mV (pk-pk)

217Hz

100mV (pk-pk)

217Hz

93 dB

-75

-73 dB dB

36 dB

38 dB

97 dB

-76 dB

-75 dB

51 dB

100 dB

97 dB

-72 dB

-76 dB

-74 dB

95 dB

51 dB

29 dB

90 100 dB

97 dB

-82 dB

-80 dB

95 dB

51 dB

29 dB w PP, August 2012, Rev 3.4

21

WM8958

Pre-Production

Test Conditions



T

A


E9 DAC to Earpiece Driver (Load = 16  BTL)

SNR A-weighted

THD P

O

=50mW

THD+N P

O

=50mW


217Hz

97 dB

-71 dB

-69 dB

51 dB

E12 DAC to Speaker Outputs (Load = 8  + 22H BTL, Stereo Mode)

Class D Mode, +12dB boost (SPKOUTx_BOOST = 111)

SNR A-weighted

THD P

O

=0.5W

THD+N P

O

=0.5W

THD P

O

=1.0W

THD+N P

O

=1.0W


217Hz

Channel Separation

(L/R)

DAC to Speaker Outputs (Load = 8  + 22H BTL, Stereo Mode)

Class AB Mode, +12dB boost (SPKOUTx_BOOST = 111)

SNR A-weighted

THD P

O

=0.5W

THD+N P

O

=0.5W

THD P

O

=1.0W

THD+N P

O

=1.0W


217Hz

Channel Separation

(L/R)

DAC to Speaker Outputs (Load = 4  + 22H BTL, Stereo Mode)


SNR A-weighted

THD P

O

=0.5W

THD+N P

O

=0.5W

THD P

O

=1.0W

THD+N P

O

=1.0W

THD P

O

=2.0W

THD+N P

O

=2.0W

PSRR (all supplies)

Channel Separation

(L/R)

100mV (pk-pk)

217Hz

85 94 dB

-65 dB

-70 dB

-68 dB

43 dB

80 dB

96 dB

-67 dB

-65 dB

-64 dB

-62 dB

43 dB

80 dB

93 dB

dB

-63 dB

dB

-63 dB

dB

-66 dB

dB

dB w PP, August 2012, Rev 3.4

22

Pre-Production

WM8958

Test Conditions



T

A


E13 Speaker Output Power (Load = 8  + 22H BTL, Stereo Mode)

Output Power SPKVDD1=

SPKVDD2=5.0V

THD+N ≤ 1%

SPKVDD1=

SPKVDD2=4.2V

THD+N ≤ 1%

Class AB

Class D

Class AB

Class D

SPKVDD1=

SPKVDD2=3.7V

THD+N ≤ 1%

Class AB

Class D

Note that the maximum recommended speaker output power is 1W per channel into 8Ω.

Output levels that exceed this limit are not guaranteed and may cause damage to the WM8958.

Speaker Output Power (Load = 4  + 22H BTL, Stereo Mode)

1

1

0.95

0.95

0.75

0.75

W

W

W 



Output Power SPKVDD1=

SPKVDD2=5.0V

THD+N ≤ 1%

SPKVDD1=

SPKVDD2=4.2V

THD+N ≤ 1%

Class D

(see note below)

Class D

2.3 W

1.6 W 

SPKVDD1=

SPKVDD2=3.7V

THD+N ≤ 1%

Speaker Output Power (Load = 4  + 22H BTL, Mono Mode)

Output Power

Class D

SPKVDD1=

SPKVDD2=5.0V

THD+N ≤ 1%

Class AB

(see note below)

Class D

(see note below)

Note that the maximum recommended speaker output power is 2W per channel into 4Ω.

Output levels that exceed this limit are not guaranteed and may cause damage to the WM8958.

1.2 W 

2.7 W

2.7 w PP, August 2012, Rev 3.4

23

WM8958

Pre-Production

BYPASS PATH PERFORMANCE

Test Conditions



T

A


F1 Input PGA to Differential Line Output (Load = 10k  // 50pF)

SNR A-weighted 100 dB

-90 dB

-87 dB

F3

F2

F4

Input PGA to Headphone via MIXOUTL or MIXOUTR (Load = 16 )

SNR

THD

THD+N

THD

THD+N

A-weighted

P

P

O

P

O

O

P

O


217Hz

Channel Separation

(L/R)

Line Input (IN2LP or IN2RP) to Headphone via MIXOUTL or MIXOUTR (Load = 16 )

SNR A-weighted

THD P

O

=20mW

THD+N P

O

=20mW

THD P

O

=5mW

THD+N P

O

=5mW


217Hz

Line Input (IN2LN or IN2RN) to Headphone via MIXOUTL or MIXOUTR (Load = 16 )

SNR

THD

THD+N

THD

A-weighted

P

P

O

P

O

O

THD+N

PSRR (all supplies)

P

O

100mV (pk-pk)

217Hz

Channel Separation

(L/R)

98 dB

49 dB

100 dB

-86 dB

-84 dB

-84 dB

-82 dB

49 dB

100 dB


24

Pre-Production

WM8958

Test Conditions



T

A


F5

F6

F7

Direct Voice Path to Earpiece Driver (Load = 16  BTL)

SNR A-weighted

THD P

O

=50mW

THD+N P

O

=50mW


217Hz

90 104 dB

-70 dB

91 dB

Direct Voice Path to Speaker Outputs (Load = 8  + 22H BTL, Stereo Mode)


SNR A-weighted

THD P

THD+N P

O

O

=0.5W

=0.5W

THD P

O

=1.0W

THD+N P

O

=1.0W


217Hz

Direct Voice Path to Speaker Outputs (Load = 8  + 22H BTL, Stereo Mode)


SNR A-weighted

97 dB

-62 dB

-60 dB

-67 dB

-65 dB

63 dB

103 dB

THD P

THD+N P

O

O

=0.5W

=0.5W

-62 dB

-60 dB

THD P

O

=1.0W

THD+N P

O

=1.0W


217Hz

-64 dB

-62 dB

67 dB

Line Input to Speaker Outputs via SPKMIXL or SPKMIXR (Load = 8  + 22H BTL, Stereo Mode)



THD P

O

=0.5W

THD+N P

O

=0.5W

-62 dB

-60 dB

THD P

O

=1.0W

THD+N P

O

=1.0W

-67 dB

-65 dB


217Hz

47 dB

Line Input to Speaker Outputs via SPKMIXL or SPKMIXR (Load = 8  + 22H BTL, Stereo Mode)



THD P

O

=0.5W

THD+N P

O

=0.5W

THD P

O

=1.0W

THD+N P

O

=1.0W


217Hz

-72 dB

-68 dB

-64 dB

-62 dB


25

WM8958

Pre-Production

MULTI-PATH CROSSTALK

Test Conditions



T

A


85 dB G1

G2

Headset Voice Call:

DAC/Headset to Tx Voice

Separation

1kHz 0dBFS DAC playback direct to HPOUT1L and HPOUT1R;

Quiescent input on IN1LN/P or

IN1RN/P (Gain=+12dB), differential line output; Measure crosstalk at differential line output

Speakerphone Voice Call:

DAC/Speaker to Tx Voice

Separation

1kHz 0dBFS DAC playback to speakers, 1W/chan output;



CR

OS

ST

AL

K

100 dB

G3

G4

G5

Earpiece PCM Voice Call:

RXVOICE to Tx Voice Separation fs=8kHz for ADC and DAC,

DAC_SB_FILT=1; -5dBFS, DAC output to HPOUT2P-HPOUT2N;

Quiescent input on input PGA

(Gain=+12dB) to ADC via MIXINL or MIXINR; Measure crosstalk at

ADC output

Speakerphone PCM Voice Call:

DAC/Speaker to ADC Separation fs=8kHz for ADC and DAC,

DAC_SB_FILT=1; 0dBFS DAC output to speaker (1W output);

ADC record from input PGA

(Gain=+30dB); Measure crosstalk on ADC output

Speakerphone PCM Voice Call:

ADC to DAC/Speaker Separation fs=8kHz for ADC and DAC,

DAC_SB_FILT=1; Quiescent DAC output to speaker; ADC record from input PGA (Gain=+30dB +

30dB boost); Measure crosstalk on speaker output

110 dB

90 dB


26

Pre-Production

WM8958

Test Conditions



T

A


G6

G7

G8

Earpiece Speaker Voice Call:

Tx Voice and RXVOICE

Separation

1kHz Full scale differential input on VRXP-VRXN, output to

HPOUT2P-HPOUT2N; Quiescent input on IN1LN/P or IN1RN/P

(Gain=+12dB), differential line output; Measure crosstalk at differential line output

Headset Voice Call:

Tx Voice and RXVOICE

Separation

1kHz full scale differential input on

VRXP-VRXN via RXVOICE to

MIXOUTL and MIXOUTR, output to HPOUT1L and HPOUT1R;



Stereo Line Record and Playback:

DAC/Headset to ADC Separation

-5dBFS input to DACs, playback to

HPOUT1L and HPOUT1R; ADC record from line input; Measure crosstalk on ADC output

IN1LN or

IN1RN

IN1LP or

IN1RP

-

+12dB

+

Quiescent input

IN1L or IN1R

(Single-ended or differential mode)

VRXN

Full scale input

VRXP

-

+

RXVOICE

(MIXINL or

MIXINR)

IN1LP or

IN1RP

Quiescent input

CROSSTALK

LINEOUT1NMIX or

LINEOUT2NMIX

LINEOUT1PMIX or

LINEOUT2PMIX

MIXINL or

MIXINR

+

DACL

MIXOUTL

+

0dB

HPOUT1LVOL

0dB

+

MIXOUTR HPOUT1RVOL

ADCL or

ADCR

0dB

0dB

0dB

0dB

LINEOUT1N or

LINEOUT2N

LINEOUT1P or

LINEOUT2P

HPOUT1LVOL

HPOUT1L

HPOUT1R

HPOUT1L

HPOUT1R

DACR

HPOUT1RVOL

100 dB

90 dB


27

WM8958

Pre-Production

DIGITAL INPUT / OUTPUT

Test Conditions


Digital Input / Output (except DMICDATn and DMICCLK)

Digital I/O is referenced to DBVDD1, DBVDD2 or DBVDD3. See “Pin Description” for the domain applicable to each pin.

H16 Input HIGH Level, V

IH

V

DBVDDn

H17 Input LOW Level, V

IL

DBVDDn

Note that digital input pins should not be left unconnected / floating.

H18 Output HIGH Level, V

OH

I

OH



DBVDDn

V

H19 Output LOW Level, V

OL

I

OL

=-1mA

DBVDDn

-0.9

Digital Microphone Input / Output (DMICDATn and DMICCLK)

H22 DMICDATn input HIGH Level, V

IH

MICBIAS1

H23 DMICDATn input LOW Level, V

IL

MICBIAS1

H24

H25

DMICCLK output HIGH Level, V

DMICCLK output LOW Level, V

OH

OL

I

OH



MICBIAS1

I

OL

=-1mA

MICBIAS1

-0.9

V

V

DIGITAL FILTER CHARACTERISTICS

Test Conditions


ADC Decimation Filter

Passband +/- 0.05dB

-6dB

0 0.454 fs

Stopband f > 0.546 fs -85 dB

DAC Interpolation Filter

Passband

Stopband

+/- 0.05dB

-6dB

0.454 fs f > 0.546 fs

0

-85

0.454 fs

+/- 0.05 dB dB w PP, August 2012, Rev 3.4

28

Pre-Production

WM8958

MICROPHONE BIAS CHARACTERISTICS

Test Conditions



T

A

= +25 o C, unless otherwise stated.

Microphone Bias (MICBIAS1 and MICBIAS2)

Note - No capacitor on MICBIASn

Note - In regulator mode, it is required that AVDD1 - V

MICBIASn

> 200mV

MICBn_LVL = 000

Regulator mode (MICBn_MODE=0)

Load current ≤ 1.0mA

MICBn_LVL = 001

MICBn_LVL = 010

MICBn_LVL = 011

MICBn_LVL = 100

MICBn_LVL = 101

MICBn_LVL = 110

MICBn_LVL = 111

Bias Voltage

Bypass mode (MICBn_MODE=1)

Load current ≤ 3.6mA

H4

H5

Output Noise Density

Integrated Noise Voltage

Output discharge resistance

Regulator mode

(MICBn_MODE=0)

Bypass mode

(MICBn_MODE=1)

Regulator mode

(MICBn_MODE=0),

MICBn_LVL = 100,

Load current = 1mA,

Measured at 1kHz

Regulator mode

(MICBn_MODE=0),

MICBn_LVL = 100,

Load current = 1mA,

100Hz to 7kHz, A-weighted

100mV (pk-pk) 217Hz

100mV (pk-pk) 10kHz

Regulator mode

(MICBn_MODE=0)

MICBn_ENA=0,

MICBn_DISCH=1

-5%

-5%

-5%

-5%

-5%

-5%

-5%

-5%

80mV

1.5

1.8

1.9

2.0

2.2

2.4

2.5

2.6

100

80

+5%

+5%

+5%

+5%

+5%

+5%

+5%

+5%

V

3.6

µV

RMS dB w PP, August 2012, Rev 3.4

29

WM8958

Pre-Production

MISCELLANEOUS CHARACTERISTICS

Test Conditions



T

A


Analogue Reference Levels

H1 VMID Midrail Reference Voltage

VMID Start-Up time

VMID_SEL = 01,

4.7

F capacitor on VMIDC

VMID_SEL = 01,

VMID_RAMP = 11,

4.7

F capacitor on VMIDC

External Accessory Detection

Load impedance detection range

(MICDET)

2.2kΩ (2%) MICBIAS2 resistor.

Note these characteristics assume no other component is connected to

MICDET. See “Applications Information” for recommended external components when a typical microphone is present. for MICD_LVL[0] = 1 for MICD_LVL[1] = 1 for MICD_LVL[2] = 1 for MICD_LVL[3] = 1 for MICD_LVL[4] = 1 for MICD_LVL[5] = 1 for MICD_LVL[6] = 1 for MICD_LVL[7] = 1

Frequency Locked Loops (FLLs)

H30 Free-running mode start-up time

H31 Free-running mode frequency accuracy

F

REF

=32kHz,

F

OUT

=12.288MHz

F

REF

=12MHz,

F

OUT

=12.288MHz

Reference supplied initially

No reference provided

LDO Regulators

H38 LDO1 Start-Up Time 4.7

F capacitor on AVDD1

1 F capacitor on VREFC

LDO1 Drop-Out voltage

(LDO1VDD - AVDD1)

LDO1 PSRR (LDO1VDD)

H42 LDO2 Start-Up Time

LDO2 PSRR (DBVDD1)

100mV (pk-pk) 217Hz

2.2

F capacitor on DCVDD

1 F capacitor on VREFC

100mV (pk-pk) 217Hz

-3% AVDD1/2 +3% V

0

13.33

27.16

42.48

65

114

191

475

+/-10

+/-30

TBD

TBD

3

15.27

30.96

49.47

85

155.24

329.87

30000

Ω

%

% dB dB w PP, August 2012, Rev 3.4

30

Pre-Production

WM8958

TERMINOLOGY

1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal and the output with no input signal applied.

2. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal.

3. Total Harmonic Distortion plus Noise (dB) – THD+N is the level of the rms value of the sum of harmonic distortion products plus noise in the specified bandwidth relative to the amplitude of the measured output signal.

4. Power Supply Rejection Ratio (dB) - PSRR is the ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured under quiescent signal path conditions.

5. Common Mode Rejection Ratio (dB) – CMRR is the ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that results from it.

6. Channel Separation (L/R) (dB) – left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel.

7. Multi-Path Crosstalk (dB) – is the difference in level between the output of the active path and the measured signal level in the idle path at the test signal frequency. The active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path.

8. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied.

9. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. w PP, August 2012, Rev 3.4

31

WM8958

Pre-Production

TYPICAL PERFORMANCE

TYPICAL POWER CONSUMPTION

OPERATING MODE TEST CONDITIONS SPKVDD

(Note 3)

LDO1VDD AVDD2 CPVDD DBVDD

(Note 4)

TOTAL

Off (Battery Leakage only)

LDO1 disabled, LDO2 disabled

Standby

LDO1 disabled, LDO2 enabled

Standby

LDO1 enabled, LDO2 enabled

All supplies present,

No clocks,

Default register settings

Music playback to Headphone (32ohm load)

AIF1 to DAC to

HPOUT1 (stereo)

All supplies present,

No clocks,

Default register settings

AIF1 to DAC to

HPOUT1 (stereo)

LDOs disabled,

See Note 7 fs=44.1kHz,

Clocking rate=256fs,

24-bit I2S, Slave mode fs=44.1kHz,


24-bit I2S, Slave mode,

Class W

4.2V

1.1

A

4.2V

1.8

A

4.2V

1.8

A

4.2V

0.0mA

4.2V

0.4

4.2V

1

4.2V

89

A

A

A

4.2V

2.05mA

0.0V

5.5

1.8V

60

1.8V

65

A

A

A

1.8V

0.32mA

0.0V

5 A

1.8V

5 A

1.8V

5 A

1.8V

0.48mA

0.0V

9.5

1.8V

62

72

A

A

1.8V

A

1.8V

1.13mA

3.6V

0.0mA

AVDD1=

2.4V

1.43mA

1.8V

0.21mA

1.8V

0.21mA

DBVDD=

1.8V

0.01mA

DCVDD=

1.2V

0.94mA

Music playback to Class D speaker output (8ohm, 22 H load)

AIF1 to DAC to

SPKOUT (stereo) fs=44.1kHz,



4.2V

1.65mA

+7.5dB Class D boost

AIF1 to DAC to

SPKOUT (Left) fs=44.1kHz,



+0.0dB Class D boost

4.2V

0.74mA

AIF1 to AIF3 Mono Digital Bypass (eg. Bluetooth video call)

AIF1(L) to AIF3(L),

AIF3(L) to AIF1(L) fs=8kHz,


24-bit I2S, Slave mode

4.2V

0.0mA

AIF2 to AIF3 Mono Digital Bypass (eg. Bluetooth voice call)

AIF2(L) to AIF3(L),

AIF3(L) to AIF2(L) fs=8kHz,


24-bit I2S, Slave mode

4.2V

0.002mA

4.2V

2.36mA

4.2V

2.34mA

4.2V

0.09mA

4.2V

0.089mA

1.8V

1.24mA

1.8V

0.79mA

1.8V

0.07mA

1.8V

0.065mA

1.8V

0.01mA

1.8V

0.01mA

1.8V

0.01mA

1.8V

0.003mA

1.8V

1.13mA

1.8V

1.13mA

1.8V

0.41mA

1.8V

0.311mA

Notes:

1. AVDD1 = 3.0V, generated by LDO1.

2. DCVDD = 1.2V, generated by LDO2.

3. SPKVDD = SPKVDD1 = SPKVDD2.

4. DBVDD = DBVDD1 = DBVDD2 = DBVDD3.

5. I

SPKVDD

= I

SPKVDD1

+ I

SPKVDD2

.

6. I

DBVDD

= I

DBVDD1

+ I

DBVDD2

+ I

DBVDD3

.

7. Power consumption for music playback with LDOs disabled requires an external supply for AVDD1 and DCVDD

0.01mW

0.2mW

0.6mW

12.1mW

5.34mW

21.1mW

16.4mW

1.2mW

1.1mW w PP, August 2012, Rev 3.4

32

Pre-Production

TYPICAL SIGNAL LATENCY

OPERATING MODE

WM8958

TEST CONDITIONS LATENCY

AIF2 to DAC Stereo Path

AIF2 EQ enabled,

AIF2 3D enabled,

AIF2 DRC enabled,

SRC enabled fs=8kHz,

Clock rate = 256fs fs=48kHz,







Clock rate = 256fs

SYSCLK=AIF1CLK 1.4ms




ADC to AIF2 Stereo Path

Digital Sidetone HPF enabled,

AIF2 DRC enabled,

AIF2 HPF enabled,

SRC enabled

Digital Sidetone HPF disabled,

AIF2 DRC disabled,

AIF2 HPF disabled,

SRC disabled

Digital Sidetone HPF disabled,

AIF2 DRC disabled,

AIF2 HPF disabled,

SRC enabled fs=8kHz,





Clock rate = 256fs


Clock rate = 1536fs




Notes:

1. These figures are relevant to typical voice call modes, assuming AIF2 is connected to the baseband processor

2. The SRC (Sample Rate Converter) is enabled automatically whenever required w PP, August 2012, Rev 3.4

33

WM8958

Pre-Production

SPEAKER DRIVER PERFORMANCE

Typical speaker driver THD+N performance is shown below for Class D and Class AB modes. Curves are shown for typical

SPKVDD supply voltage, gain and load conditions.

10

THD+N vs. Output Power

Class D, Mono (SPKMODE=1), 8Ω + 10µH

SPKVDD = 3.3V

10


Class D, Mono (SPKMODE=1), 4Ω + 10µH

SPKVDD = 3.3V

SPKVDD = 3.7V

1

SPKVDD = 5.0V

1

SPKVDD = 3.7V

SPKVDD = 4.2V

SPKVDD = 4.5V

SPKVDD = 5.0V

0.1

0.1

SPKVDD = 4.2V

0.01

0

10

0.2

0.4

0.6

0.8

1 1.2

Output Power (W)

1.4


Class AB, Mono (SPKMODE=1), 8Ω + 10µH

SPKVDD = 3.3V

1.6

1.8

2

0.01

0

10

SPKVDD = 4.5V

0.5

1 1.5

Output Power (W)

2


Class AB, Mono (SPKMODE=1), 4Ω + 10µH

SPKVDD = 3.3V

2.5

3

SPKVDD = 3.7V

SPKVDD = 5.0V

1 1 SPKVDD = 3.7V

SPKVDD = 5.0V

SPKVDD = 4.5V

0.1

0.1

SPKVDD = 4.2V

0.01

0

10

0.2

0.4

0.6

0.8

1 1.2

Output Power (W)

1.4


Class D, Stereo (SPKMODE=0), 8Ω + 10µH

SPKVDD = 3.3V

1.6

1.8

2

0.01

0

10

SPKVDD = 4.2V

SPKVDD = 4.5V

0.5

1 1.5

Output Power (W)

2


Class D, Stereo (SPKMODE=0), Load = 4Ω + 10µH

SPKVDD = 3.3V

2.5

3

SPKVDD = 3.7V

1 SPKVDD = 3.7V

0.1

SPKVDD = 5.0V

SPKVDD = 4.5V

SPKVDD = 4.2V

1

0.1

SPKVDD = 5.0V

SPKVDD = 4.5V

0.01

0

10

0.2

0.4

0.6

0.8

1 1.2

Output Power (W)

1.4


Class AB, Stereo (SPKMODE=0), 8Ω + 10µH

SPKVDD = 3.3V

1.6

1.8

2

0.01

0 0.5

1 1.5

Output Power (W)

2

SPKVDD = 4.2V

2.5

3

1

SPKVDD = 3.7V

SPKVDD = 5.0V

SPKVDD = 4.5V

0.1

SPKVDD = 4.2V

0.01

0 0.2

0.4

0.6

0.8

1 1.2

Output Power (W)

1.4

1.6

1.8

2 w PP, August 2012, Rev 3.4

34

Pre-Production

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCKS & FREQUENCY LOCKED LOOP (FLL)

WM8958

Figure 2 Master Clock Timing

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER SYMBOL CONDITIONS MIN

Master Clock Timing (MCLK1 and MCLK2)

MCLK as input to FLL,

FLLn_REFCLK_DIV = 01, 10, 11

37 ns

MCLK cycle time T

MCLKY

74

MCLK duty cycle

(= T

MCLKH

: T

MCLKL

)

Frequency Locked Loops (FLL1 and FLL2)

FLL Input Frequency

MCLK as input to FLL,

FLLn_REFCLK_DIV = 00

FLL not used, AIFnCLK_DIV = 1

FLL not used, AIFnCLK_DIV = 0

40

80

60:40 40:60

MHz FLLn_REFCLK_DIV = 00




0.032

0.064

0.128

0.256

13.5

27

27

27

Internal Clocking

SYSCLK frequency

AIF1CLK frequency

AIF2CLK frequency

DSP2CLK frequency w PP, August 2012, Rev 3.4

35

WM8958

Pre-Production

AUDIO INTERFACE TIMING

DIGITAL MICROPHONE (DMIC) INTERFACE TIMING

Figure 3 Digital Microphone Interface Timing

Test Conditions


Digital Microphone Interface Timing

DMICCLK cycle time

DMICCLK duty cycle

DMICDAT (Left) setup time to falling DMICCLK edge

DMICDAT (Left) hold time from falling DMICCLK edge

DMICDAT (Right) setup time to rising DMICCLK edge

DMICDAT (Right) hold time from rising DMICCLK edge t t

CY

ns

LSU

45:55 55:45 %

15 ns ns t

RSU

15 ns t t

LH

0

RH

0 ns w PP, August 2012, Rev 3.4

36

Pre-Production

DIGITAL AUDIO INTERFACE - MASTER MODE

WM8958

BCLK

(output)

V

OH

V

OL t

BCY

LRCLK

(output)

V

OH

V

OL t

DL

ADCDAT

(output)

V

OH

V

OL t

DDA

DACDAT

(input)

V

IH

V

IL t

DST t

DHT

Figure 4 Audio Interface Timing - Master Mode

Note that BCLK and LRCLK outputs can be inverted if required; Figure 4 shows the default, noninverted polarity of these signals.

Test Conditions


Audio Interface Timing - Master Mode

BCLK cycle time

LRCLK propagation delay from BCLK falling edge

ADCDAT propagation delay from BCLK falling edge

DACDAT setup time to BCLK rising edge

DACDAT hold time from BCLK rising edge

Audio Interface Timing - Ultrasonic (4FS) Master Mode t t t t t

BCY

DL

DDA

DST

DHT

BCLK cycle time

ADCDAT propagation delay from BCLK falling edge t

BCY t

DDA

Note that the descriptions above assume non-inverted polarity of BCLK and LRCLK. w PP, August 2012, Rev 3.4

37

WM8958

Pre-Production

DIGITAL AUDIO INTERFACE - SLAVE MODE

Figure 5 Audio Interface Timing - Slave Mode

Note that BCLK and LRCLK inputs can be inverted if required; Figure 5 shows the default, noninverted polarity.

Test Conditions


Audio Interface Timing - Slave Mode

BCLK cycle time

BCLK pulse width high

BCLK pulse width low

LRCLK set-up time to BCLK rising edge

LRCLK hold time from BCLK rising edge

DACDAT hold time from BCLK rising edge

ADCDAT propagation delay from BCLK falling edge

DACDAT set-up time to BCLK rising edge t

BCY

160 t

BCH

64 t

BCL

64 t

LRSU

10 t

LRH

10 t

DH

10 t

DD t

DS

32

Note that the descriptions above assume non-inverted polarity of BCLK and LRCLK. ns ns ns ns ns ns ns w PP, August 2012, Rev 3.4

38

Pre-Production

WM8958

DIGITAL AUDIO INTERFACE - TDM MODE

When TDM operation is used on the ADCDATn pins, it is important that two devices do not attempt to drive the ADCDATn pin simultaneously. To support this requirement, the ADCDATn pins can be configured to be tri-stated when not outputting data.

The timing of the WM8958 ADCDATn tri-stating at the start and end of the data transmission is described in Figure 6 below.

Figure 6 Audio Interface Timing - TDM Mode

Test Conditions


TDM Timing - Master Mode

ADCDAT setup time from BCLK falling edge

ADCDAT release time from BCLK falling edge

TDM Timing - Slave Mode

ADCDAT setup time from BCLK falling edge

ADCDAT release time from BCLK falling edge

0 ns

5 ns w PP, August 2012, Rev 3.4

39

WM8958

CONTROL INTERFACE TIMING

Pre-Production

Figure 7 Control Interface Timing

Test Conditions


SCLK Frequency

SCLK Low Pulse-Width

SCLK High Pulse-Width

Hold Time (Start Condition)

Setup Time (Start Condition)

Data Setup Time

SDA, SCLK Rise Time

SDA, SCLK Fall Time

Setup Time (Stop Condition)

Data Hold Time

Pulse width of spikes that will be suppressed t t t t

1 t

2

3 t

4

600 t

5

100 t

6 t

7 t

8

9 ps

1300

600

600

600

0 ns ns ns ns ns ns w PP, August 2012, Rev 3.4

40

Pre-Production

WM8958

DEVICE DESCRIPTION

INTRODUCTION

The WM8958 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a very small footprint makes it ideal for portable applications such as mobile phones. Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity.

Three sets of audio interface pins are available in order to provide independent and fully asynchronous connections to multiple processors, typically an application processor, baseband processor and wireless transceiver. Any two of these interfaces can operate totally independently and asynchronously while the third interface can be synchronised to either of the other two and can also provide ultra low power loopback modes to support, for example, wireless headset voice calls.

Four digital microphone input channels are available to support advanced multi-microphone applications such as noise cancellation. An integrated microphone activity monitor is available to enable the processor to sleep during periods of microphone inactivity, saving power.

Four DAC channels are available to support use cases requiring up to four simultaneous digital audio streams to the output drivers.

Eight highly flexible analogue inputs allow interfacing to up to four microphone inputs (single-ended or differential), plus multiple stereo or mono line inputs. Connections to an external voice CODEC, FM radio, line input, handset MIC and headset MIC are all fully supported. Signal routing to the output mixers and within the CODEC has been designed for maximum flexibility to support a wide variety of usage modes. A ‘Direct Voice’ path from a voice CODEC directly to the Speaker or Earpiece output drivers is included.

Impedance sensing and measurement for external accessories is provided, for detection of the insertion or removal of microphones and other accessories. Push-button detection of up to 7 inputs can be supported using this feature.

Nine analogue output drivers are integrated, including a stereo pair of high power, high quality

Class D/AB switchable speaker drivers; these can support 2W each in stereo mode. It is also possible to configure the speaker drivers as a mono output, giving enhanced performance. A mono earpiece driver is provided, providing output from the output mixers or from the low-power differential ‘Direct

Voice’ path.

One pair of ground-referenced headphone outputs is provided; these are powered from an integrated

Charge Pump, enabling high quality, power efficient headphone playback without any requirement for

DC blocking capacitors. A DC Servo circuit is available for DC offset correction, thereby suppressing pops and reducing power consumption. Four line outputs are provided, with multiple configuration options including 4 x single-ended output or 2 x differential outputs. The line outputs are suitable for output to a voice CODEC, an external speaker driver or line output connector. Ground loop feedback is available on the headphone outputs and the line outputs, providing rejection of noise on the ground connections. All outputs have integrated pop and click suppression features.

Internal differential signal routing and amplifier configurations have been optimised to provide the highest performance and lowest possible power consumption for a wide range of usage scenarios, including voice calls and music playback. The speaker drivers offer low leakage and high PSRR; this enables direct connection to a Lithium battery. The speaker drivers provide eight levels of AC and DC gain to allow output signal levels to be maximised for many commonly-used SPKVDD/AVDD1 combinations.

The ADCs and DACs are of hi-fi quality, using a 24-bit low-order oversampling architecture to deliver optimum performance. A flexible clocking arrangement supports mixed sample rates, whilst integrated ultra-low power dual FLLs provide additional flexibility. A high pass filter is available in all ADC and digital MIC paths for removing DC offsets and suppressing low frequency noise such as mechanical vibration and wind noise. A digital mixing path from the ADC or digital MICs to the DAC provides a sidetone of enhanced quality during voice calls. DAC soft mute and un-mute is available for pop-free music playback. w PP, August 2012, Rev 3.4

41

WM8958

Pre-Production

The integrated Multiband Compressors (MBC), Dynamic Range Controllers (DRC) and ReTune TM

Mobile 5-band parametric equaliser (EQ) provide further processing capability of the digital audio paths. The MBC enables the loudness of the digital playback path to be maximised without overdriving the loudspeakers. The RMS Limiter within the MBC function enables the maximum signal level to be matched to the application requirements and/or power rating of the loudspeaker. The DRC provides compression and signal level control to improve the handling of unpredictable signal levels.

‘Anti-clip’ and ‘quick release’ algorithms improve intelligibility in the presence of transients and impulsive noises. The EQ provides the capability to tailor the audio path according to the frequency characteristics of an earpiece or loudspeaker, and/or according to user preferences.

I

The WM8958 has highly flexible digital audio interfaces, supporting a number of protocols, including

2 S, DSP, MSB-first left/right justified, and can operate in master or slave modes. PCM operation is supported in the DSP mode. A-law and -law companding are also supported. Time division multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. The four digital MIC and ADC channels and four DAC channels are available via four TDM channels on Digital Audio Interface 1 (AIF1).

A powerful digital mixing core allows data from each TDM channel of each audio interface and from the ADCs and digital MICs to be mixed and re-routed back to a different audio interface and to the 4

DAC output channels. The digital mixing core can operate synchronously with either Audio Interface 1 or Audio Interface 2, with asynchronous stereo full duplex sample rate conversion performed on the other audio interface as required.

The system clock (SYSCLK) provides clocking for the ADCs, DACs, DSP core, digital audio interface and other circuits. SYSCLK can be derived directly from one of the MCLK1 or MCLK2 pins or via one of two integrated FLLs, providing flexibility to support a wide range of clocking schemes, including self-clocking FLL modes. Typical portable system MCLK frequencies, and sample rates from 8kHz to

96kHz are all supported. A low frequency (eg. 32.768kHz) clock can be used as the input reference to the FLLs, providing further flexibility. Automatic configuration of the clocking circuits is available, derived from the sample rate and from the MCLK / SYSCLK ratio.

The WM8958 uses a standard 2-wire control interface, providing full software control of all features, together with device register readback. An integrated Control Write Sequencer enables automatic scheduling of control sequences; commonly-used signal configurations may be selected using readyprogrammed sequences, including time-optimised control of the WM8958 pop suppression features. It is an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs.

Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications.

Versatile GPIO functionality is provided, with support for button/accessory detect inputs, or for clock, system status, or programmable logic level output for control of additional external circuitry. Interrupt logic, status readback and de-bouncing options are supported within this functionality. w PP, August 2012, Rev 3.4

42

Pre-Production

WM8958

ANALOGUE INPUT SIGNAL PATH

The WM8958 has eight highly flexible analogue input channels, configurable in a large number of combinations:

1. Up to four fully differential or single-ended microphone inputs

2. Up to eight mono line inputs or 4 stereo line inputs

3. A dedicated mono differential input from external voice CODEC

These inputs may be mixed together or independently routed to different combinations of output drivers. An internal record path is provided at the input mixers to allow DAC output to be mixed with the input signal path (e.g. for voice call recording).

The WM8958 input signal paths and control registers are illustrated in Figure 8.

Figure 8 Control Registers for Input Signal Path w PP, August 2012, Rev 3.4

43

WM8958

Pre-Production

MICROPHONE INPUTS

Up to four analogue microphones can be connected to the WM8958, either in single-ended or differential mode. A dedicated PGA is provided for each microphone input. Two low noise microphone bias circuits are provided, reducing the need for external components.

For single-ended microphone inputs, the microphone signal is connected to the inverting input of the

PGAs (IN1LN, IN2LN, IN1RN or IN2RN). The non-inverting inputs of the PGAs are internally connected to VMID in this configuration. The non-inverting input pins IN1LP, IN2LP, IN1RP and

IN2RP are free to be used as line connections to the input or output mixers in this configuration.

For differential microphone inputs, the non-inverted microphone signal is connected to the noninverting input of the PGAs (IN1LP, IN2LP, IN1RP or IN2RP), whilst the inverted (or ‘noisy ground’) signal is connected to the inverting input pins (IN1LN, IN2LN, IN1RN and IN2RN).

The gain of the input PGAs is controlled via register settings, as defined in Table 4. Note that the input impedance of both inverting and non-inverting inputs changes with the input PGA gain setting, as described under “Electrical Characteristics”. See also the “Applications Information” for details of input resistance at all PGA Gain settings.

The microphone input configurations are illustrated in Figure 9 and Figure 10. Note that any PGA input pin that is used in either microphone configuration is not available for use as a line input path at the same time.

Figure 9 Single-Ended Microphone Input Figure 10 Differential Microphone Input w

MICROPHONE BIAS CONTROL

There are two MICBIAS generators which provide low noise reference voltages suitable for powering silicon (MEMS) microphones or biasing electret condenser (ECM) type microphones via an external resistor. Refer to the “Applications Information” section for recommended external components.

The MICBIAS outputs can be independently enabled using the MICB1_ENA and MICB2_ENA register bits. Under default conditions, a smooth pop-free profile of the MICBIAS outputs is implemented when MICB1_ENA or MICB2_ENA is enabled or disabled; a faster transition can be selected by setting the MICB1_RATE and MICB2_RATE registers as described in Table 1.

When a MICBIAS output is disabled, the output pin can be configured to be floating or to be actively discharged. This is selected using the MICB1_DISCH and MICB2_DISCH register bits.

The MICBIAS generators can each operate as a voltage regulator or in bypass mode.

In Regulator mode, the output voltage is selected using the MICB1_LVL and MICB2_LVL register bits. In this mode, AVDD1 must be at least 200mV greater than the required MICBIAS output voltages. The MICBIAS outputs are powered from the AVDD1 supply pin, and use the internal bandgap circuit as a reference.

Note that, in Regulator mode, the MICBIAS regulators are designed to operate without external decoupling capacitors. It is important that parasitic capacitances on the MICBIAS1 or MICBIAS2 pins do not exceed the specified limit in Regulator mode (see “Electrical Characteristics”).

In Bypass mode, the output pin (MICBIAS1 or MICBIAS2) is connected directly to AVDD1. This enables a low power operating state. Note that, if a capacitive load is connected to MICBIAS1 or

MICBIAS2 (eg. for a digital microphone supply), then the respective MICBIAS generator must be configured in Bypass mode.


44

Pre-Production

The MICBIAS configuration is illustrated in Figure 11.

WM8958 w

Figure 11 MICBIAS Generator

REGISTER

ADDRESS

R1

(0001h)

Power

Managem ent (1)

5 MICB2_ENA

4 MICB1_ENA

R61

(003Dh)

MICBIAS

1

5 MICB1_RATE

0

0

1

4 MICB1_MODE 1

0 MICB1_DISCH 1

R62

(003Eh)

MICBIAS

2

5 MICB2_RATE 1

4 MICB2_MODE 1

DESCRIPTION

Microphone Bias 2 Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Microphone Bias 1 Rate

0 = Fast start-up / shut-down

1 = Pop-free start-up / shut-down

Microphone Bias 1 Mode

0 = Regulator mode

1 = Bypass mode

Microphone Bias 1 Voltage Control

(when MICB1_MODE = 0)

000 = 1.5V

001 = 1.8V

010 = 1.9V

011 = 2.0V

100 = 2.2V

101 = 2.4V

110 = 2.5V

111 = 2.6V

Microphone Bias 1 Discharge

0 = MICBIAS1 floating when disabled

1 = MICBIAS1 discharged when disabled

Microphone Bias 2 Rate



Microphone Bias 2 Mode

0 = Regulator mode

1 = Bypass mode


45

WM8958 w

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

0 MICB2_DISCH 1

Microphone Bias 2 Voltage Control


000 = 1.5V

001 = 1.8V

010 = 1.9V

011 = 2.0V

100 = 2.2V

101 = 2.4V

110 = 2.5V

111 = 2.6V

Microphone Bias 2 Discharge



Table 1 Microphone Bias Control

Note that the maximum source current capability for MICBIAS1 and MICBIAS2 is 2.4mA each in

Regulator mode. The external biasing resistance must be large enough to limit each MICBIAS current to 2.4mA across the full microphone impedance range. The maximum source current for MICBIAS1 and MICBIAS2 is 3.6mA each in Bypass mode, as described in the “Electrical Characteristics”.

MICROPHONE ACCESSORY DETECT

The WM8958 provides a microphone detection function, which uses impedance measurement to detect one or more different external accessory connections. This feature is described in the “External

Accessory Detection” section.

LINE AND VOICE CODEC INPUTS

All eight analogue input pins may be used as line inputs. Each line input has different signal path options, providing flexibility, high performance and low power consumption for many different usage modes.

IN1LN and IN1RN can operate as single-ended line inputs to the input PGAs IN1L and IN1R respectively. These inputs provide a high gain path if required for low input signal levels.

IN2LN and IN2RN can operate as single-ended line inputs to the input PGAs IN2L and IN2R respectively, providing further high gain signal paths. These pins can also be connected to either of the output mixers MIXOUTL and MIXOUTR.

IN1LP and IN1RP can operate as single-ended line inputs to the input mixers MIXINL and MIXINR, or to the speaker mixers SPKMIXL and SPKMIXR. These signal paths enable power consumption to be reduced, by allowing the input PGAs and other circuits to be disabled if not required.

IN2LP/VRXN and IN2RP/VRXP can operate in three different ways:

 Mono differential ’RXVOICE’ input (e.g. from an external voice CODEC) to the input mixers

MIXINL and MIXINR.

 Single-ended line inputs to either of the output mixers MIXOUTL and MIXOUTR.

 Ultra-low power mono differential ‘Direct Voice’ input (e.g. from an external voice CODEC) to the ear speaker driver on HPOUT2, or to either of the speaker drivers on SPKOUTL and

SPKOUTR.

Signal path configuration to the input PGAs and input mixers is detailed later in this section. Signal path configuration to the output mixers and speaker mixers is described in “Analogue Output Signal

Path”.


46

Pre-Production

WM8958

The line input and voice CODEC input configurations are illustrated in Figure 12 through to Figure 15.

MIXOUTL/R

Line Input

IN2LN,

IN2RN

-

+

PGA

MIXINL/R

Figure 12 IN1LN or IN1RN as Line Inputs

VMID

Figure 13 IN2LN or IN2RN as Line Inputs w

Figure 14 IN1LP or IN1RP as Line Inputs Figure 15 IN2LP or IN2RP as Line Inputs

INPUT PGA ENABLE

The Input PGAs are enabled using register bits IN1L_ENA, IN2L_ENA, IN1R_ENA and IN2R_ENA, as described in Table 2. The Input PGAs must be enabled for microphone input on the respective input pins, or for line input on the inverting input pins IN1LN, IN1RN, IN2LN, IN2RN.

REGISTER

ADDRESS

DESCRIPTION

R2 (0002h)

Power

Management

(2)

7

6

5

4

IN2L_ENA

IN1L_ENA

IN2R_ENA

IN1R_ENA

0

0

0

0

IN2L Input PGA Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

IN2R Input PGA Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Table 2 Input PGA Enable

For normal operation of the input PGAs, the reference voltage VMID and the bias current must also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls

VMID_SEL and BIAS_ENA.


47

WM8958 w

Pre-Production

INPUT PGA CONFIGURATION

Each of the Input PGAs can operate in a single-ended or differential mode. In differential mode, both inputs to the PGA are connected to the input source. In single-ended mode, the non-inverting input to the PGA must be connected to VMID. Configuration of the PGA inputs to the WM8958 input pins is controlled using the register bits shown in Table 3.

Single-ended microphone operation is configured by connecting the input source to the inverting input of the applicable PGA. The non-inverting input of the PGA must be connected to the buffered VMID reference. Note that the buffered VMID reference must be enabled, using the VMID_BUF_ENA register, as described in “Reference Voltages and Master Bias”.

Differential microphone operation is configured by connecting the input source to both inputs of the applicable PGA.

Line inputs to the input pins IN1LN, IN2LN, IN1RN and IN2RN must be connected to the applicable

PGA. The non-inverting input of the PGA must be connected to VMID.

Line inputs to the input pins IN1LP, IN2LP, IN1RP or IN2RP do not connect to the input PGAs. The non-inverting inputs of the associated PGAs must be connected to VMID. The inverting inputs of the associated PGAs may be used as separate mic/line inputs if required.

The maximum available attenuation on any of these input paths is achieved by using register bits shown in Table 3 to disconnect the input pins from the applicable PGA.

BIT LABEL DEFAULT DESCRIPTION REGISTER

ADDRESS

R40 (0028h)

Input Mixer

(2)

7

6

5

4

3

2

1

0

IN2LP_TO_IN2L

IN2LN_TO_IN2L

IN1LP_TO_IN1L

IN1LN_TO_IN1L

IN2RP_TO_IN2R

IN2RN_TO_IN2R

IN1RP_TO_IN1R

IN1RN_TO_IN1R

0

0

0

0

0

0

0

0

IN2L PGA Non-Inverting Input Select

0 = Connected to VMID

1 = Connected to IN2LP

Note that VMID_BUF_ENA must be set when using IN2L connected to

VMID.

IN2L PGA Inverting Input Select

0 = Not connected

1 = Connected to IN2LN




Note that VMID_BUF_ENA must be set when using IN1L connected to

VMID.


0 = Not connected


IN2R PGA Non-Inverting Input Select


1 = Connected to IN2RP

Note that VMID_BUF_ENA must be set when using IN2R connected to

VMID.

IN2R PGA Inverting Input Select

0 = Not connected

1 = Connected to IN2RN




Note that VMID_BUF_ENA must be set when using IN1R connected to

VMID.


0 = Not connected


Table 3 Input PGA Configuration


48

Pre-Production

WM8958

INPUT PGA VOLUME CONTROL

Each of the four Input PGAs has an independently controlled gain range of -16.5dB to +30dB in 1.5dB steps. The gains on the inverting and non-inverting inputs to the PGAs are always equal. Each Input

PGA can be independently muted using the PGA mute bits as described in Table 4, with maximum mute attenuation achieved by simultaneously disconnecting the corresponding inputs described in

Table 3.

Note that, under default conditions (following power-up or software reset), the PGA mute register bits are set to ‘1’, but the mute functions will only become effective after the respective bit has been toggled to ‘0’ and then back to ‘1’. The Input PGAs will be un-muted (Mute disabled) after power-up or software reset, regardless of the readback value of the respective PGA mute bits.

To prevent "zipper noise", a zero-cross function is provided on the input PGAs. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long period without zero-crossings, a timeout function is provided. When the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout clock is enabled using TOCLK_ENA, the timeout period is set by TOCLK_DIV. See “Clocking and Sample Rates” for more information on these fields.

The IN1_VU and IN2_VU bits control the loading of the input PGA volume data. When IN1_VU and

IN2_VU are set to 0, the PGA volume data will be loaded into the respective control register, but will not actually change the gain setting. The IN1L and IN1R volume settings are both updated when a 1 is written to IN1_VU; the IN2L and IN2R volume settings are both updated when a 1 is written to

IN2_VU. This makes it possible to update the gain of the left and right signal paths simultaneously. w PP, August 2012, Rev 3.4

49

WM8958 w

Pre-Production

The Input PGA Volume Control register fields are described in Table 4 and Table 5.

REGISTER

ADDRESS

R24 (0018h)

Left Line Input

1&2 Volume

R25 (0019h)

Left Line Input

3&4 Volume

R26 (001Ah)

Right Line

Input 1&2

Volume

R27 (001Bh)

Right Line

Input 3&4

Volume

BIT LABEL DEFAULT

8

7

6

4:0

8

7

6

4:0

8

7

6

4:0

8

7

6

4:0

IN1_VU

IN1L_MUTE

IN1L_ZC

IN1L_VOL

[4:0]

IN2_VU

IN2L_MUTE

IN2L_ZC

IN2L_VOL

[4:0]

IN1_VU

IN1R_MUTE

IN1R_ZC

IN1R_VOL

[4:0]

IN2_VU

IN2R_MUTE

IN2R_ZC

IN2R_VOL

[4:0]

N/A

1

0

01011

(0dB)

N/A

1

0

01011

(0dB)

N/A

1

0

01011

(0dB)

N/A

1

0

01011

(0dB)

DESCRIPTION

Input PGA Volume Update

Writing a 1 to this bit will cause IN1L and

IN1R input PGA volumes to be updated simultaneously

IN1L PGA Mute

0 = Disable Mute

1 = Enable Mute

IN1L PGA Zero Cross Detector

0 = Change gain immediately

1 = Change gain on zero cross only

IN1L Volume

-16.5dB to +30dB in 1.5dB steps

(See Table 5 for volume range)




IN2L PGA Mute

0 = Disable Mute

1 = Enable Mute

IN2L PGA Zero Cross Detector



IN2L Volume






IN1R PGA Mute

0 = Disable Mute

1 = Enable Mute

IN1R PGA Zero Cross Detector



IN1R Volume






IN2R PGA Mute

0 = Disable Mute

1 = Enable Mute

IN2R PGA Zero Cross Detector



IN2R Volume



Table 4 Input PGA Volume Control


50

Pre-Production

IN1L_VOL[4:0], IN2L_VOL[4:0],

IN1R_VOL[4:0], IN2R_VOL[4:0]

VOLUME

(dB)

00000 -16.5

00001 -15.0

00010 -13.5

00011 -12.0

00100 -10.5

00101 -9.0

00110 -7.5

00111 -6.0

01000 -4.5

01001 -3.0

01010 -1.5

01011 0

01100 +1.5

01101 +3.0

01110 +4.5

01111 +6.0

10000 +7.5

10001 +9.0

10010 +10.5

10011 +12.0

10100 +13.5

10101 +15.0

10110 +16.5

10111 +18.0

11000 +19.5

11001 +21.0

11010 +22.5

11011 +24.0

11100 +25.5

11101 +27.0

11110 +28.5

11111 +30.0

Table 5 Input PGA Volume Range

WM8958 w PP, August 2012, Rev 3.4

51

WM8958 w

Pre-Production

INPUT MIXER ENABLE

The WM8958 has two analogue input mixers which allow the Input PGAs and Line Inputs to be combined in a number of ways and output to the ADCs, Output Mixers, or directly to the output drivers via bypass paths.

The input mixers MIXINL and MIXINR are enabled by the MIXINL_ENA and MIXINR_ENA register bits, as described in Table 6. These control bits also enable the RXVOICE input path, described in the following section.

For normal operation of the input mixers, the reference voltage VMID and the bias current must also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls



ADDRESS

R2 (0002h)

Power

Management

(2)

9

8

MIXINL_ENA

MIXINR_ENA

0

0

Left Input Mixer Enable

(Enables MIXINL and RXVOICE input to

MIXINL)

0 = Disabled

1 = Enabled

Right Input Mixer Enable

(Enables MIXINR and RXVOICE input to

MIXINR)

0 = Disabled

1 = Enabled

Table 6 Input Mixer Enable

INPUT MIXER CONFIGURATION AND VOLUME CONTROL

The left and right channel input mixers MIXINL and MIXINR can be configured to take input from up to five sources:

1. IN1L or IN1R Input PGA

2. IN2L or IN2R Input PGA

3. IN1LP or IN1RP pin (PGA bypass)

4. RXVOICE mono differential input from IN2LP/VRXN and IN2RP/VRXP

5. MIXOUTL or MIXOUTR Output Mixer (Record path)

The Input Mixer configuration and volume controls are described in Table 7 for the Left input mixer

(MIXINL) and Table 8 for the Right input mixer (MIXINR). The signal levels from the Input PGAs may be set to Mute, 0dB or 30dB boost. Gain controls for the PGA bypass, RXVOICE and Record paths provide adjustment from -12dB to +6dB in 3dB steps.

When using the IN1LP or IN1RP signal paths direct to the input mixers (PGA bypass paths), a signal gain of +15dB can be selected using the IN1RP_MIXINR_BOOST or IN1LP_MIXINL_BOOST register bits. See Table 7 and Table 8 for further details.

When using the IN1LP or IN1RP signal paths direct to the input mixers (PGA bypass paths), the buffered VMID reference must be enabled, using the VMID_BUF_ENA register, as described in

“Reference Voltages and Master Bias”.

To prevent pop noise, it is recommended that gain and mute controls for the input mixers are not modified while the signal paths are active. If volume control is required on these signal paths, it is recommended that this is implemented using the input PGA volume controls or the ADC volume controls. The ADC volume controls are described in the “Analogue to Digital Converter (ADC)” section.


52

Pre-Production

REGISTER

ADDRESS

R21

(0015h)

Input Mixer

(1)

R41

(0029h)

Input Mixer

(3)

R43

(002Bh)

Input Mixer

(5)

WM8958

BIT LABEL DEFAULT DESCRIPTION

7

8

7

5

4

IN1LP_MIXINL_BOOST

IN2L_TO_MIXINL

IN2L_MIXINL_VOL

IN1L_TO_MIXINL

IN1L_MIXINL_VOL

2:0 MIXOUTL_MIXINL_VOL

[2:0]

8:6 IN1LP_MIXINL_VOL

[2:0]

0

0

0

0

0

000

(Mute)

000

(Mute)

IN1LP Pin (PGA Bypass) to

MIXINL Gain Boost.

This bit selects the maximum gain setting of the IN1LP_MIXINL_VOL register.

0 = Maximum gain is +6dB


IN2L PGA Output to MIXINL Mute

0 = Mute

1 = Un-Mute

IN2L PGA Output to MIXINL Gain

0 = 0dB

1 = +30dB


0 = Mute

1 = Un-Mute


0 = 0dB

1 = +30dB

Record Path MIXOUTL to MIXINL

Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB

IN1LP Pin (PGA Bypass) to

MIXINL Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB (see note below).

When IN1LP_MIXINL_BOOST is set, then the maximum gain setting is increased to +15dB, ie.

111 = +15dB.

Note that VMID_BUF_ENA must be set when using the IN1LP (PGA

Bypass) input to MIXINL. w PP, August 2012, Rev 3.4

53

WM8958

REGISTER

ADDRESS

Pre-Production


2:0 IN2LRP_MIXINL_VOL

[2:0]

000

(Mute)

RXVOICE Differential Input

(VRXP-VRXN) to MIXINL Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB

Table 7 Left Input Mixer (MIXINL) Volume Control

REGISTER

ADDRESS

R21 (0015h)

Input Mixer

(1)

8 IN1RP_MIXINR_BOOST 0

DESCRIPTION

R42 (002A)

Input Mixer

(4)

8

7

5

4

2:0

IN2R_TO_MIXINR

IN2R_MIXINR_VOL

IN1R_TO_MIXINR

IN1R_MIXINR_VOL

MIXOUTR_MIXINR_VOL

[2:0]

0

0

0

0

000

(Mute)

IN1RP Pin (PGA Bypass) to

MIXINR Gain Boost.

This bit selects the maximum gain setting of the

IN1RP_MIXINR_VOL register.



IN2R PGA Output to MIXINR Mute

0 = Mute

1 = Un-Mute

IN2R PGA Output to MIXINR Gain

0 = 0dB

1 = +30dB


0 = Mute

1 = Un-Mute


0 = 0dB

1 = +30dB

Record Path MIXOUTR to MIXINR

Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB w PP, August 2012, Rev 3.4

54

Pre-Production

REGISTER

ADDRESS

R44

(002Ch)

Input Mixer

(6)

8:6

2:0

IN1RP_MIXINR_VOL

[2:0]

IN2LRP_MIXINR_VOL

[2:0]

Table 8 Right Input Mixer (MIXINR) Volume Control

WM8958

DESCRIPTION

000

(Mute)

000

(Mute)

IN1RP Pin (PGA Bypass) to

MIXINR Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB


When IN1RP_MIXINR_BOOST is set, then the maximum gain setting is increased to +15dB, ie.

111 = +15dB.

Note that VMID_BUF_ENA must be set when using the IN1RP

(PGA Bypass) input to MIXINR.

RXVOICE Differential Input

(VRXP-VRXN) to MIXINR Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB w PP, August 2012, Rev 3.4

55

WM8958

Pre-Production

DIGITAL MICROPHONE INTERFACE

The WM8958 supports a four-channel digital microphone interface. Two channels of audio data are multiplexed on the DMICDAT1 pin and a further two channels are multiplexed on the DMICDAT2 pin.

All four channels are clocked using the DMICCLK output pin.

The DMICDAT1 function is shared with the IN2LN pin; the analogue signal paths from IN2LN cannot be used when this pin is used for DMICDAT1 digital microphone input.

The DMICDAT2 function is shared with the IN2RN pin; the analogue signal paths from IN2RN cannot be used when this pin is used for DMICDAT2 digital microphone input.

The digital microphone interface is referenced to the MICBIAS1 voltage domain; the MICBIAS1 output must be enabled (MICB1_ENA = 1) when using the digital microphone interface.

The MICBIAS1 generator is suitable for use as a low noise supply for the digital microphones. Note that, if the capacitive load on the MICBIAS1 generator exceeds the specified limit (eg. due to a decoupling capacitor or long PCB trace), then the MICBIAS1 generator must be configured in Bypass mode. See “Analogue Input Signal Path” for details of the MICBIAS1 generator.

When digital microphone input is enabled, the WM8958 outputs a clock signal on the DMICCLK pin.

A pair of digital microphones is connected as illustrated in Figure 16. The microphones must be configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic transmits a data bit when DMICCLK is low. The WM8958 samples the digital microphone data at the end of each DMICCLK phase. Each microphone must tri-state its data output when the other microphone is transmitting. w

Figure 16 Digital Microphone Input

The DMICDAT1 digital microphone channels are enabled using DMIC1L_ENA and DMIC1R_ENA.

When these signal paths are enabled, the respective ADC path is disconnected and the digital microphone data is routed to the digital mixing input bus, as illustrated in “Digital Mixing”.

The DMICDAT2 digital microphone channels are enabled using DMIC2L_ENA and DMIC2R_ENA.

When these signal paths are enabled, the digital microphone data is routed to the digital mixing input bus, as illustrated in “Digital Mixing”.

Two microphone channels are interleaved on DMICDAT1; another two channels are interleaved on

DMICDAT2. The timing is illustrated in Figure 17. Each microphone must tri-state its data output when the other microphone is transmitting.


56

Pre-Production

WM8958 w

Figure 17 Digital Microphone Interface Timing

The four digital microphone channels can be routed to one of the four timeslots on AIF1. The

DMICDAT1 microphones, when enabled, are routed to the Left/Right channels of AIF1 Timeslot 0.

The DMICDAT2 microphones, when enabled, are routed to the Left/Right channels of AIF1 Timeslot

1.

Digital volume control of the digital microphone channels in the AIF1 signal paths is provided using the registers described in the “Digital Volume and Filter Control” section.

The digital microphone channels can be routed, in a limited number of configurations, to the digital mixing output bus, via the digital sidetone signal paths. See “Digital Mixing” for further details.

Digital volume control of the digital microphone channels in the digital sidetone signal paths is provided using the registers described in the “Digital Mixing” section.

The digital microphone interface control fields are described in Table 9.

REGISTER

ADDRESS

R4 (0004h)

Power

Management

(4)

5 DMIC2L_ENA 0

4

3

2

DMIC2R_ENA

DMIC1L_ENA

DMIC1R_ENA

0

0

0

DESCRIPTION

Digital microphone DMICDAT2

Left channel enable

0 = Disabled

1 = Enabled


Right channel enable

0 = Disabled

1 = Enabled


Left channel enable

0 = Disabled

1 = Enabled


Right channel enable

0 = Disabled

1 = Enabled

Table 9 Digital Microphone Interface Control


57

WM8958 w

Pre-Production

Clocking for the Digital Microphone interface is derived from SYSCLK. The DMICCLK frequency is configured automatically, according to the AIFn_SR, AIFnCLK_RATE and ADC_OSR128 registers.

(See “Clocking and Sample Rates” for further details of the system clocks and control registers.)

The DMICCLK is enabled whenever a digital microphone input path is enabled on the DMICDAT1 or

DMICDAT2 pin(s). Note that the SYSDSPCLK_ENA register must also be set.

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the DMICCLK frequency is controlled by the AIF1_SR and AIF1CLK_RATE registers.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the DMICCLK frequency is controlled by the AIF2_SR and AIF2CLK_RATE registers.

The DMICCLK frequency is as described in Table 10 (for ADC_OSR128=1) and Table 11 (for

ADC_OSR128=0). The ADC_OSR128 bit is set by default, giving best audio performance. Note that the only valid DMICCLK configurations are the ones listed in Table 10 and Table 11.

The applicable clocks (SYSCLK, and AIF1CLK or AIF2CLK) must be present and enabled when using the digital microphone interface.

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128 192 256 384 512 768 1024 1536

8

11.025

12

16

2.048

2.8224

3.072

2.8224

3.072

2.048 2.048

2.8224 2.8224 22.05

24

32

44.1

48

3.072 3.072

2.048

2.8224

3.072

88.2

96

Note that, when ADC_OSR128=1, digital microphone operation is only supported for the above

DMICCLK configurations.

Table 10 DMICCLK Frequency (MHz) - ADC_OSR128 = 1 (Default)

SAMPLE

RATE (kHz)


128 192 256 384 512 768 1024 1536

8

11.025

12

16

1.024 1.024

1.4112 1.4112 1.4112

1.536 1.536 1.536

1.024 1.024 1.024 1.024

1.4112 1.4112 1.4112

1.536 1.536 1.536

22.05

24

32

44.1

48

88.2

2.8224

3.072

96

Note that, when ADC_OSR128=0, digital microphone operation is only supported for the above

DMICCLK configurations.

Table 11 DMICCLK Frequency (MHz) - ADC_OSR128 = 0


58

Pre-Production

WM8958

DIGITAL PULL-UP AND PULL-DOWN

The WM8958 provides integrated pull-up and pull-down resistors on the DMICDAT1 and DMICDAT2 pins. This provides a flexible capability for interfacing with other devices. Each of the pull-up and pulldown resistors can be configured independently using the register bits described in Table 12.

Note that, if the DMICDAT1 or DMICDAT2 digital microphone channels are disabled, or if

DMICDATn_PU and DMICDATn_PD are both set, then the pull-up and pull-down will be disabled on the respective pin.

DESCRIPTION REGISTER

ADDRESS

R1824

(0720h)

Pull Control

(1)

11

10

9

8

DMICDAT2_PU

DMICDAT2_PD

DMICDAT1_PU

DMICDAT1_PD

0

0

0

0

DMICDAT2 Pull-Up enable

0 = Disabled

1 = Enabled

DMICDAT2 Pull-Down enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Table 12 Digital Pull-Up and Pull-Down Control

ANALOGUE TO DIGITAL CONVERTER (ADC)

The WM8958 uses stereo 24-bit sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The oversample rate can be adjusted, if required, to reduce power consumption - see “Clocking and Sample Rates” for details.

The ADC full scale input level is proportional to AVDD1 - see “Electrical Characteristics”. Any input signal greater than full scale may overload the ADC and cause distortion.

The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits.

REGISTER

ADDRESS

R4 (0004h)

Power

Management (4)


1

0

ADCL_ENA

ADCR_ENA

0

0

DESCRIPTION

Left ADC Enable

0 = Disabled

1 = Enabled

Right ADC Enable

0 = Disabled

1 = Enabled

Table 13 ADC Enable Control

The outputs of the ADCs can be routed to the Left/Right channels of AIF1 (Timeslot 0).

Digital volume control of the ADC outputs in the AIF1 signal paths is provided using the registers described in the “Digital Volume and Filter Control” section.

The outputs of the ADCs can be routed, in a limited number of configurations, to the digital mixing output bus, via the digital sidetone signal paths. See “Digital Mixing” for further details.

Digital volume control of the ADC outputs in the digital sidetone signal paths is provided using the registers described in the “Digital Mixing” section. w PP, August 2012, Rev 3.4

59

WM8958 w

Pre-Production

ADC CLOCKING CONTROL

Clocking for the ADCs is derived from SYSCLK. The required clock is enabled when the

SYSDSPCLK_ENA register is set.

The ADC clock rate is configured automatically, according to the AIFn_SR, AIFnCLK_RATE and

ADC_OSR128 registers. (See “Clocking and Sample Rates” for further details of the system clocks and control registers.)

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the ADC clocking is controlled by the AIF1_SR and AIF1CLK_RATE registers.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the ADC clocking is controlled by the AIF2_SR and AIF2CLK_RATE registers.

The supported ADC clocking configurations are described in Table 14 (for ADC_OSR128=1) and

Table 15 (for ADC_OSR128=0). The ADC_OSR128 bit is set by default, giving best audio performance.

SAMPLE

RATE (kHz)


128 192 256 384 512 768 1024 1536

8

11.025















12

16

22.05

24

32

44.1





























48

88.2

96

When ADC_OSR128=1, ADC operation is only supported for the configurations indicated above

Table 14 ADC Clocking - ADC_OSR128 = 1 (Default)

SAMPLE

RATE (kHz)


128 192 256 384 512 768 1024 1536

8

11.025























12

16



















22.05

24

















32

44.1

48

88.2

96





When ADC_OSR128=0, ADC operation is only supported for the configurations indicated above

Table 15 ADC Clocking - ADC_OSR128 = 0

The clocking requirements in Table 14 and Table 15 are only applicable to the AIFnCLK that is selected as the SYSCLK source. Note that both clocks (AIF1CLK and AIF2CLK) must satisfy the requirements noted in the “Clocking and Sample Rates” section.

The applicable clocks (SYSCLK, and AIF1CLK or AIF2CLK) must be present and enabled when using the Analogue to Digital Converters (ADCs).


60

Pre-Production

WM8958

DIGITAL CORE ARCHITECTURE

The WM8958 Digital Core provides an extensive set of mixing and signal processing features. The

Digital Core Architecture is illustrated in Figure 18, which also identifies the datasheet sections applicable to each portion of the Digital Core.

Audio Interface 1 (AIF1) supports audio input and output on two stereo timeslots simultaneously, making a total of four inputs and four outputs. The mixing of the four AIF1 output paths is described in

“Audio Interface 1 (AIF1) Output Mixing”.

A digital mixing path from the ADCs or Digital Microphones to the DAC output paths provides a high quality sidetone for voice calls or other applications. The sidetone configuration is described in “Digital

Sidetone Mixing”; the associated filter and volume control is described in “Digital Sidetone Volume and Filter Control”.

Each of the four hi-fi DACs has a dedicated mixer for controlling the signal paths to that DAC. The configuration of these signal paths is described in “DAC Output Digital Mixing”.

Each DAC is provided with digital volume control, soft mute / un-mute and a low pass filter. The associated controls are defined in the “Digital to Analogue Converter (DAC)” section.

Digital processing can be applied to the four input channels of AIF1 and the two input channels of

AIF2. The available features include multiband compression (MBC), 5-band equalization (EQ), 3D stereo expansion and dynamic range control (DRC).

The MBC provides a function to maximise the loudness of the audio signal, using independent compression and boost of different frequency bands without overdriving the loudspeakers. The RMS

Limiter within the MBC function enables the maximum signal level to be matched to the application requirements and/or power rating of the loudspeaker. The MBC controls are described in “Multiband

Compressor”. The EQ provides the capability to tailor the audio path according to the frequency characteristics of an earpiece or loudspeaker, and/or according to user preferences. The EQ controls are described in “ReTune TM Mobile Parametric Equalizer (EQ)”.

The DRC provides adaptive signal level control to improve the handling of unpredictable signal levels and to improve intelligibility in the presence of transients and impulsive noises. The DRC controls are described in “Dynamic Range Control (DRC)”. 3D stereo expansion provides a stereo enhancement effect; the depth of the effect is programmable, as described in “3D Stereo Expansion”.

The input channels of AIF1 and AIF2 are also equipped with digital volume control and soft mute / unmute control; see “Digital Volume and Filter Control” for details of these features.

The output channels of AIF1 and AIF2 can be configured using the digital volume control and a programmable high-pass filter (HPF). The Dynamic Range Control (DRC) circuit can also be applied here, with the restriction that a DRC cannot be enabled in the input and output path of one AIF channel at the same time. The AIF output volume and filter controls are described in “Digital Volume and Filter Control”.

The WM8958 provides an ultrasonic mode on the output paths of AIF1, allowing high frequency signals (such as ultrasonic microphone signals) to be output. See “Ultrasonic (4FS) AIF Output Mode” for further details.

The WM8958 provides two full audio interfaces, AIF1 and AIF2. Each interface supports a number of protocols, including I 2 S, DSP, MSB-first left/right justified, and can operate in master or slave modes.

PCM operation is supported in the DSP mode. A-law and -law companding are also supported. Time division multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power.

Four-channel input and output is supported using TDM on AIF1. Two-channel input and output is supported on AIF2. A third interface, AIF3, is partially supported, using multiplexers to re-configure alternate connections to AIF1 or AIF2.

Signal mixing between audio interfaces is possible. The WM8958 performs stereo full-duplex sample rate conversion between the audio interfaces as required. (Note that sample rate conversion is not supported on some signal paths, as noted in Figure 18.)

The audio interfaces AIF1, AIF2 and AIF3 are referenced to DBVDD1, DBVDD2 and DBVDD3 respectively; this provides additional capability to interface between different sub-systems within an application. w PP, August 2012, Rev 3.4

61

WM8958

DMICDAT2

DMICDAT1

ADC

L

ADC

R

Digital Sidetone

Mixing

Pre-Production

Digital Sidetone Volume and Filter Control

DAC Output

Digital Mixing

G G

G G

G G

[Code]

Gain Codes

V = Full volume control

(-71.625dB to 12dB, 0.375dB steps for DAC

-71.625dB to 17.625dB, 0.375dB steps for ADC/MICs)

S = Softmute/un-mute

NG = Digital Noise Gate

G = Fixed gain control

(-36dB to 0dB, 3dB steps)

+

+

+

+

DAC1L

Vol

VS

DAC1R

Vol

VS

DAC2L

Vol

VS

DAC2R

Vol

VS

DAC

1L

DAC

1R

DAC

2L

DAC

2R

G G

DAC Digital

Volume

Audio Interface 1

(AIF1) Output Mixing

Sample Rate

Conversion

= SRC not supported

DRC / Microphone signal activity detector (GPIO)

Ultrasonic (4FS)

AIF Output Modes

Digital Audio

Interface Control

+ + + +

DRC DRC

MBC

DRC

EQ

3D

MBC

DRC

EQ

3D

AIF1 Slot 0

AIF1 Slot 1 fs / 4fs Select

AIF1 Slot 0

AIF1 Slot 1

MBC

DRC

EQ

3D

DRC

Left / Right source select / Mono Mix control

Left / Right source select /

Mono Mix control

0R 0L 1R 1L 0R 0L 1R 1L

DIGITAL AUDIO

INTERFACE 1 (AIF1)

0R 0L 0R 0L

DIGITAL AUDIO

INTERFACE 2 (AIF2)

MONO PCM

INTERFACE

Multiband Compressor (MBC) /

Dynamic Range Control (DRC) /

Retune Mobile Parameter Equalizer (EQ) /

Stereo 3D Expansion /

Digital Volume and Filter Control

Note the Multi-band Compressor (MBC) cannot be enabled on AIF1 and AIF2 simultaneously.

Note the Dynamic Range Control (DRC) cannot be enabled in the input and output paths of any

Digital Audio Interface simultaneously.

Note -

AIF1 is referenced to the DBVDD1 power domain

AIF2 is referenced to DBVDD2

AIF3 / Mono PCM is referenced to DBVDD3

Figure 18 Digital Core Architecture w PP, August 2012, Rev 3.4

62

Pre-Production

DIGITAL MIXING

WM8958

This section describes the digital mixing functions of the WM8958.

Digital audio mixing is provided on four AIF1 output paths, two digital sidetone paths, and four Digital to Analogue converters (DACs).

Note that the two AIF2 output paths are connected to the DAC2L and DAC2R signal paths.

The digital mixing functions and associated control registers are illustrated in Figure 19. w

Figure 19 Digital Mixing Block Diagram


63

WM8958

Pre-Production

AUDIO INTERFACE 1 (AIF1) OUTPUT MIXING

There are four AIF1 digital mixers, one for each AIF1 audio channel (ie. Left/Right channels on

Timeslots 0/1). The inputs to each AIF1 mixer comprise signals from the ADC / Digital Microphone inputs and from AIF2.

Note that the Left/Right channels of AIF1 can be inverted or interchanged if required; see “Digital

Audio Interface Control”.

The AIF1 Left Timeslot 0 output channel is derived from the ADCL / DMIC1 (Left) and AIF2 (Left) inputs. The ADCL / DMIC1 (Left) path is enabled by ADC1L_TO_AIF1ADC1L, whilst the AIF2 (Left) path is enabled by AIF2DACL_TO_AIF1ADC1L.

The AIF1 Right Timeslot 0 output channel is derived from the ADCR / DMIC1 (Right) and AIF2 (Right) inputs. The ADCR / DMIC1 (Right) path is enabled by ADC1R_TO_AIF1ADC1R, whilst the AIF2

(Right) path is enabled by AIF2DACR_TO_AIF1ADC1R.

The AIF1 Left Timeslot 1 output channel is derived from the DMIC2 (Left) and AIF2 (Left) inputs. The

DMIC2 (Left) path is enabled by ADC2L_TO_AIF1ADC2L, whilst the AIF2 (Left) path is enabled by

AIF2DACL_TO_AIF1ADC2L. w

The AIF1 Right Timeslot 1 output channel is derived from the DMIC2 (Right) and AIF2 (Right) inputs.

The DMIC2 (Right) path is enabled by ADC2R_TO_AIF1ADC2R, whilst the AIF2 (Right) path is enabled by AIF2DACR_TO_AIF1ADC2R.

The AIF1 output mixer controls are defined in Table 16.

REGISTER

ADDRESS

R1542 (0606h)

AIF1 ADC1

Left Mixer

Routing

1 ADC1L_TO_AIF

1ADC1L

0

0 AIF2DACL_TO_

AIF1ADC1L

0

R1543 (0607h)

AIF1 ADC1

Right Mixer

Routing

R1544 (0608h)

AIF1 ADC2

Left Mixer

Routing

R1545 (0609h)

AIF1 ADC2

Right Mixer

Routing

1

0

1

0

1

0

ADC1R_TO_AIF

1ADC1R

AIF2DACR_TO_

AIF1ADC1R

ADC2L_TO_AIF

1ADC2L

AIF2DACL_TO_

AIF1ADC2L

ADC2R_TO_AIF

1ADC2R

AIF2DACR_TO_

AIF1ADC2R

0

0

0

0

0

0

DESCRIPTION

Enable ADCL / DMIC1 (Left) to

AIF1 (Timeslot 0, Left) output

0 = Disabled

1 = Enabled

Enable AIF2 (Left) to AIF1 (Timeslot

0, Left) output

0 = Disabled

1 = Enabled

Enable ADCR / DMIC1 (Right) to

AIF1 (Timeslot 0, Right) output

0 = Disabled

1 = Enabled

Enable AIF2 (Right) to AIF1

(Timeslot 0, Right) output

0 = Disabled

1 = Enabled

Enable DMIC2 (Left) to AIF1

(Timeslot 1, Left) output

0 = Disabled

1 = Enabled

Enable AIF2 (Left) to AIF1 (Timeslot

1, Left) output

0 = Disabled

1 = Enabled

Enable DMIC2 (Right) to AIF1


0 = Disabled

1 = Enabled

Enable AIF2 (Right) to AIF1


0 = Disabled

1 = Enabled

Table 16 AIF1 Output Mixing


64

Pre-Production

WM8958

DIGITAL SIDETONE MIXING

There are two digital sidetone signal paths, STL and STR. The sidetone sources are selectable for each path. The sidetone mixer outputs are inputs to the DAC signal mixers.

The following sources can be selected for sidetone path STL.

 ADCL or DMICDAT1 (Left) channel

 DMICDAT2 (Left) channel

The following sources can be selected for sidetone path STR.

 ADCR or DMICDAT1 (Right) channel

 DMICDAT2 (Right) channel

The sidetone signal sources are selected using STR_SEL and STL_SEL as described in Table 17.

Note that, when STR_SEL = 0 or STL_SEL = 0, and the respective ADC is enabled (for analogue inputs), then the ADC data will be selected for applicable sidetone path.


ADDRESS

R1569 (0621h)

Sidetone

1 STR_SEL 0

0 STL_SEL 0

Select source for sidetone STR path

0 = ADCR / DMICDAT1 (Right)

1 = DMICDAT2 (Right)

Select source for sidetone STL path

0 = ADCL / DMICDAT1 (Left)

1 = DMICDAT2 (Left)

Table 17 Digital Sidetone Mixing

DIGITAL SIDETONE VOLUME AND FILTER CONTROL

A digital volume control is provided for the digital sidetone paths. The associated register controls are described in Table 18.

A digital high-pass filter can be enabled in the sidetone paths to remove DC offsets. This filter is enabled using the ST_HPF register bit; the cut-off frequency is configured using ST_HPF_CUT.

When the filter is enabled, it is enabled in both digital sidetone paths.

Note that the sidetone filter cut-off frequency scales according to the sample rate of AIF1 or AIF2.

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the ST_HPF cut-off frequency is scaled according to the AIF1_SR register. When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the ST_HPF cut-off frequency is scaled according to the AIF2_SR register. See “Clocking and Sample Rates” for further details of the system clocks and control registers.


ADDRESS

R1536 (0600h)

DAC1 Mixer

Volumes

8:5 ADCR_DAC1_V

OL [3:0]

0000 Sidetone STR to DAC1L and

DAC1R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB

(see Table 19 for gain range) w PP, August 2012, Rev 3.4

65

WM8958

REGISTER

ADDRESS

R1539 (0603h)

DAC2 Mixer

Volumes

R1569 (0621h)

Sidetone

Pre-Production

DESCRIPTION

3:0

8:5

3:0

9:7

6

ADCL_DAC1_V

OL [3:0]

ADCR_DAC2_V

OL [3:0]

ADCL_DAC2_V

OL [3:0]

ST_HPF_CUT

[2:0]

ST_HPF

0000

0000

0000

000

0

Sidetone STL to DAC1L and

DAC1R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB

(see Table 19 for gain range)

Sidetone STR to DAC2L and

DAC2R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB


Sidetone STL to DAC2L and

DAC2R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB


Sidetone HPF cut-off frequency

(relative to 44.1kHz sample rate)

000 = 2.7kHz

001 = 1.35kHz

010 = 675Hz

011 = 370Hz

100 = 180Hz

101 = 90Hz

110 = 45Hz

111 = Reserved

Note - the cut-off frequencies scale with the Digital Mixing (SYSCLK) clocking rate. The quoted figures apply to 44.1kHz sample rate.

Digital Sidetone HPF Select

0 = Disabled

1 = Enabled

Table 18 Digital Sidetone Volume Control w PP, August 2012, Rev 3.4

66

Pre-Production

WM8958

ADCR_DAC1_VOL,

ADCL_DAC2_VOL,

ADCR_DAC1_VOL or

ADCL_DAC2_VOL

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

SIDETONE

GAIN (dB)

-12

-9

-6

-3

0

0

0

0

-24

-21

-18

-15

-36

-33

-30

-27

Table 19 Digital Sidetone Volume Range

DAC OUTPUT DIGITAL MIXING

There are four DAC digital mixers, one for each DAC. The inputs to each DAC mixer comprise signals from AIF1, AIF2 and the digital sidetone signals. w

Note that the Left/Right channels of the AIF1 and AIF2 inputs can be inverted or interchanged if required; see “Digital Audio Interface Control”.


ADDRESS

R1537 (0601h)

DAC1 Left

Mixer Routing

R1538 (0602h)

DAC1 Right

Mixer Routing

5

4

2

1

0

5

4

2

ADCR_TO_DAC

1L

ADCL_TO_DAC

1L

AIF2DACL_TO_

DAC1L

AIF1DAC2L_TO

_DAC1L

AIF1DAC1L_TO

_DAC1L

ADCR_TO_DAC

1R

ADCL_TO_DAC

1R

AIF2DACR_TO_

DAC1R

0

0

0

0

0

0

0

0

Enable Sidetone STR to DAC1L

0 = Disabled

1 = Enabled

Enable Sidetone STL to DAC1L

0 = Disabled

1 = Enabled

Enable AIF2 (Left) to DAC1L

0 = Disabled

1 = Enabled

Enable AIF1 (Timeslot 1, Left) to

DAC1L

0 = Disabled

1 = Enabled


DAC1L

0 = Disabled

1 = Enabled

Enable Sidetone STR to DAC1R

0 = Disabled

1 = Enabled

Enable Sidetone STL to DAC1R

0 = Disabled

1 = Enabled

Enable AIF2 (Right) to DAC1R

0 = Disabled

1 = Enabled


67

WM8958 w

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

R1540 (0604h)

DAC2 Left

Mixer Routing

R1541 (0605h)

DAC2 Right

Mixer Routing

1

0

5

4

2

1

0

5

4

2

1

0

AIF1DAC2R_TO

_DAC1R

AIF1DAC1R_TO

_DAC1R

ADCR_TO_DAC

2L

ADCL_TO_DAC

2L

AIF2DACL_TO_

DAC2L

AIF1DAC2L_TO

_DAC2L

AIF1DAC1L_TO

_DAC2L

ADCR_TO_DAC

2R

ADCL_TO_DAC

2R

AIF2DACR_TO_

DAC2R

AIF1DAC2R_TO

_DAC2R

AIF1DAC1R_TO

_DAC2R

0

0

0

0

0

0

0

0

0

0

0

0

Enable AIF1 (Timeslot 1, Right) to

DAC1R

0 = Disabled

1 = Enabled


DAC1R

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


DAC2L

0 = Disabled

1 = Enabled


DAC2L

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


DAC2R

0 = Disabled

1 = Enabled


DAC2R

0 = Disabled

1 = Enabled

Table 20 DAC Output Digital Mixing

AUDIO INTERFACE 2 (AIF2) DIGITAL MIXING

There are two output channels on AIF2. The audio source for these two channels is the same as the selected source for DAC2L and DAC2R, as described in “DAC Output Digital Mixing”.

Note that the Left/Right channels of AIF2 can be inverted or interchanged if required; see “Digital

Audio Interface Control”.


68

Pre-Production

WM8958

ULTRASONIC (4FS) AIF OUTPUT MODE

The WM8958 provides an ultrasonic mode on the output paths of the AIF1 audio interface. The ultrasonic mode enables high frequency signals (such as ultrasonic microphone signals) to be output.

Ultrasonic mode is enabled on AIF1 using the AIF1ADC_4FS register bit. When the ultrasonic mode is selected, the AIF1 output sample rate is increased by a factor of 4. For example, a 48kHz sample rate will be output at 192kHz in ultrasonic mode.

Ultrasonic mode is only supported in AIF Master mode and uses the ADCLRCLK output (not the

LRCLK). When ultrasonic mode is enabled, the AIF1 must be configured in Master mode, as described in “Digital Audio Interface Control”. See “General Purpose Input/Output” to configure the

GPIO1 pin as ADCLRCLK1. The ADCLRCLK1 rate is controlled as described in “Digital Audio

Interface Control”.

When ultrasonic mode is enabled, the audio band filtering and digital volume controls (see “Digital

Volume and Filter Control”) are bypassed on the affected output paths.

The Dynamic Range Control (DRC) function is not available on the AIF1 output signal paths in ultrasonic mode. Note, however, that the DRC is still available on the AIF input paths in this case.

The ultrasonic (4FS) signal paths are illustrated in Figure 20. The AIF1ADC_4FS register bit is defined in Table 21. w

Figure 20 Ultrasonic (4FS) Signal Paths

REGISTER

ADDRESS

R1040 (0410h)

AIF1 ADC1

Filters

15 AIF1ADC_4FS

Table 21 Ultrasonic (4FS) Mode Control

0

DESCRIPTION

Enable AIF1ADC ultrasonic mode

(4FS) output, bypassing all AIF1 baseband output filtering

0 = Disabled

1 = Enabled


69

WM8958

MULTIBAND COMPRESSOR (MBC)

Pre-Production

The Multiband Compressor (MBC) is a DSP function which can be enabled in the digital playback path of the WM8958 audio interfaces. The normal function of the MBC is to maximise the loudness of the audio signal.

The MBC uses selective processing of the received digital audio signal to control the loudness; independent gain control algorithms are applied to different audio frequency bands. The effect of this is to increase the perceived loudness of the audio path, producing an enhanced audio signal without overdriving the output transducers (eg. loudspeakers).

The MBC provides two internal signal paths, allowing low frequencies and high frequencies to be processed separately. Each signal path incorporates a programmable compressor which can be used to dynamically control the level of each frequency band.

The most significant advantage of multiband compression is that a signal peak in one frequency band will not cause gain reduction in the other frequency band. Similarly, gain can be applied to one frequency band without boosting (and potentially distorting) the other. This provides a powerful capability to maximise the loudness of the signal path.

The two signal paths are re-combined at the output of the MBC. If necessary, any difference in tonal balance between the frequency bands can be restored by changing the levels of the two signal paths relative to each other.

The MBC incorporates a high-pass and a low-pass filter, which set the lower and upper frequency limits of the MBC signal path. The crossover frequency that divides the two frequency bands can be adjusted according to the system requirements. The attack and decay times of the compressors are separately programmable on each frequency band.

An RMS Limiter is included within the MBC function. This is a signal limiter that responds to the RMS output level of the digital playback path, allowing the maximum signal level to be matched to the application requirements and/or the power rating of the loudspeaker.

The WM8958 provides one stereo Multiband Compressor (MBC). The MBC can be enabled on the input path of AIF1 timeslot 0, AIF1 timeslot 1 or on the input path of AIF2. Note that the MBC cannot be enabled on more than one of these paths simultaneously.

A Dynamic Range Control (DRC) function is also available on the digital playback paths. Note that the

DRC and MBC functions should not be enabled simultaneously on the same playback path. The DRC is enabled using the registers described in Table 28.

The MBC signal paths and control parameters are illustrated in Figure 21. w

Figure 21 Multiband Compressor


70

Pre-Production

The MBC filter cut-off frequencies are shown in Table 22.

WM8958

Low Cut-Off Frequency

Crossover Frequency

High Cut-Off Frequency

20Hz 350Hz 1kHz

500Hz 2.5kHz 7.9kHz

11kHz 12kHz 16kHz

Table 22 Multiband Compressor Cut-Off Frequencies

RMS LIMITER

An RMS Limiter is included within the MBC function. This is a signal limiter that responds to the RMS output level of the digital playback path, allowing the maximum signal level to be matched to the application requirements and/or the power rating of the loudspeaker.

The Wolfson WISCE™ software must be used to derive the register settings for the RMS Limiter. The

WISCE™ software allows users to select the desired RMS voltage level of the analogue output.

Note that the selected RMS voltage level applies to each output pin. For differential (BTL) outputs, note that a limit of 1.0Vrms on each pin equates to 2.0Vrms across the load.

The MBC operates within the digital core of the WM8958, and the playback signal may be subject to boost or attenuation in the digital and/or analogue stages of the output signal path. Therefore, the

RMS Limiter configuration must take account of the applicable gain settings of the output signal path.

The WISCE™ software allows the user to input the amount of gain (dB) applicable to the relevant output signal path. (This is the total signal gain of the applicable DACs, output/boost mixers and PGA volume controls.) Note that the register settings for the RMS Limiter will only be valid for the specified gain level.

MBC CLOCKING CONTROL

Clocking for the MBC is derived from DSP2CLK. This clock is derived from the output of the

AIF1CLK_SRC or AIF2CLK_SRC multiplexers, according to the SYSCLK_SRC register. This is illustrated in Figure 22, and described further in the “Clocking and Sample Rates” section.

Figure 22 Audio Interface Clock Control

The MBC can enabled on the AIF1 or AIF2 input paths, regardless of the SYSCLK_SRC setting, provided that the minimum clocking requirement for the MBC is satisfied. w PP, August 2012, Rev 3.4

71

WM8958 w

Pre-Production

To support the MBC function, it is required that DSP2CLK ≥ 256 x fs (where fs is the sample rate of the AIF on which the MBC is enabled). When the MBC is enabled on either of the AIF1 input paths, it is required that DSP2CLK ≥ 256 x AIF1_SR; when the MBC is enabled on the AIF2 input path, it is required that DSP2CLK ≥ 256 x AIF2_SR.

The MBC is supported in 44.1kHz and 48kHz AIF sample rate modes only; note that these modes require clocking rates of AIFnCLK = 256 x fs. (See “Digital to Analogue Converter (DAC)” for details of the valid clocking rates.)

The DSP2CLK clock for the MBC is enabled when the DSP2CLK_ENA register is set. The DSP2CLK clock is required for running the MBC function, and also for accessing any of the MBC configuration registers. Note that the applicable source clock must also be present when using DSP2CLK.

See “Clocking and Sample Rates” for details of the WM8958 clocking control registers.

MBC CONTROL SEQUENCES

Specific control sequences must be followed when enabling or configuring the MBC function; these sequences are described in Table 23 to Table 26. The associated MBC control registers are described in Table 27.

Note that the WM8958 is provided with a working set of default MBC configuration parameters, allowing the MBC feature to be enabled easily in a default operating mode. For user-specific configuration of the MBC, the Wolfson WISCE™ software must be used to derive the configuration parameters (refer to WISCE TM for further information).

The control sequence for enabling the MBC is described in Table 23 (for default MBC settings) and

Table 24 (for user-specific MBC settings). It is recommended that the applicable DAC playback path is muted during this sequence, as described below.

STEP DESCRIPTION

1 Mute the applicable DAC output(s)

NOTES

The DAC Volume and Mute controls are described in Table 58.

2

3

Set DSP2CLK_ENA = 1

Set DSP2_ENA = 1

4

5

6

Write DSP2_RUNR = 1

Set MBC_SEL as required

Set MBC_ENA = 1

Un-mute the applicable DAC output(s)

For AIF1DAC1 path, set MBC_SEL = 00.


For AIF2DAC path, set MBC_SEL = 10.

Table 23 MBC Enable Sequence (default MBC configuration)

6

7

8

9



2

3

Set DSP2CLK_ENA = 1

Set DSP2_ENA = 1

NOTES


4

5

Set Register R2568 (0A08h) = 007Bh

Set Register R2569 (0A09h) = 0007h

Set Register R2570 (0A0Ah) = 0073h

Set the configuration parameters

Write DSP2_RUNR = 1

Set MBC_SEL as required

Refer to WISCE™ for register settings.

10

Set MBC_ENA = 1





Table 24 MBC Enable Sequence (user-specific MBC configuration)


72

Pre-Production

WM8958

The control sequence for disabling the MBC is described in Table 25. It is recommended that the applicable DAC playback path is muted during this sequence, as described below.

2

3

4

5



NOTES


Set MBC_ENA = 0


Set DSP2_ENA = 0

Set DSP2CLK_ENA = 0

Table 25 MBC Disable Sequence

The control sequence for updating the MBC configuration parameters is described in Table 26. It is recommended that the applicable DAC playback paths are muted during this sequence, as described below.

The same sequence is required when reading the MBC configuration parameters; note that readback of these registers is not possible when the MBC function is active.



NOTES

The DAC Volume and Mute controls are described in Table 58. (If changing the MBC from one signal path to another, then both

DAC paths should be muted.)

2

3

4

Set MBC_ENA = 0

Write DSP2_STOP = 1


5

Readback the MBC configuration parameters

Set Register R2568 (0A08h) = 007Bh

Set Register R2569 (0A09h) = 0007h

Set Register R2570 (0A0Ah) = 0073h

Set the configuration parameters


Note that these actions are only required for user-specific MBC configuration.

6

7

8

Write DSP2_RUNR = 1

Set MBC_SEL

Set MBC_ENA = 1





Table 26 MBC Update / Readback Sequence w PP, August 2012, Rev 3.4

73

WM8958

R2305 (0901h)

DSP2_Config

R2573

(0A0Dh)

DSP2_ExecCo ntrol

Pre-Production

The MBC control registers are described in Table 27.

REGISTER

ADDRESS

R2304 (0900h)

DSP2_Progra m

0 DSP2_ENA 0

5:4

0

2

1

MBC_SEL [1:0]

MBC_ENA

DSP2_STOP

DSP2_RUNR

00

0

0

0

DESCRIPTION

DSP2 Audio Processor Enable.

0 = Disabled

1 = Enabled

This bit must be set before the MBC is enabled. It must remain set whenever the MBC is enabled.

MBC Signal Path select

00 = AIF1DAC1 input path (AIF1,

Timeslot 0)

01 = AIF1DAC2 input path (AIF1,

Timeslot 1)

10 = AIF2DAC input path

11 = Reserved

MBC Enable

0 = Disabled

1 = Enabled

Stop the DSP2 audio processor

Writing a 1 to this bit will cause the

DSP2 processor to stop processing audio data

Start the DSP2 audio processor


DSP2 processor to start processing audio data

Table 27 Multiband Compressor (MBC) Control w PP, August 2012, Rev 3.4

74

Pre-Production

WM8958

DYNAMIC RANGE CONTROL (DRC)

The Dynamic Range Control (DRC) is a circuit which can be enabled in the digital playback or digital record paths of the WM8958 audio interfaces. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system.

The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anticlip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the presence of loud impulsive noises.

The DRC also incorporates a Noise Gate function, which provides additional attenuation of very lowlevel input signals. This means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions.

The WM8958 provides three stereo Dynamic Range Controllers (DRCs); these are associated with

AIF1 timeslot 0, AIF1 timeslot 1 and AIF2 respectively. Each DRC can be enabled either in the DAC playback (AIF input) path or in the ADC record (AIF output) path, as described in the “Digital Core

Architecture” section.

The DRCs are enabled in the DAC or ADCs audio signal paths using the register bits described in

Table 28. Note that enabling any DRC in the DAC and ADC paths simultaneously is an invalid selection.

A Multiband Compressor (MBC) function is also available on the digital playback paths. Note that the

DRC and MBC functions should not be enabled simultaneously on the same playback path. The MBC control registers are described in Table 27.

When the DRC is enabled in any of the ADC (digital record) paths, the associated High Pass Filter

(HPF) must be enabled also; this ensures that DC offsets are removed prior to the DRC processing.

The output path HPF control registers are described in Table 42 (for AIF1 output paths) and Table 50

(for AIF2 output paths). These are described in the “Digital Volume and Filter Control” section.

Note that, when ultrasonic (4FS) mode is selected on AIF1, then the DRC function is bypassed on the respective ADC (output) signal paths. The DRC may still be selected on the AIF1 DAC (input) signal paths.


ADDRESS

R1088 (0440h)

AIF1 DRC1 (1)

2 AIF1DAC1_DRC

_ENA

0

R1104 (0450h)

AIF1 DRC2 (1)

1

0

2

1

0

AIF1ADC1L_DR

C_ENA

AIF1ADC1R_DR

C_ENA

AIF1DAC2_DRC

_ENA

AIF1ADC2L_DR

C_ENA

AIF1ADC2R_DR

C_ENA

0

0

0

0

0

Enable DRC in AIF1DAC1 playback path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Enable DRC in AIF1ADC1 (Left) record path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Enable DRC in AIF1ADC1 (Right) record path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Enable DRC in AIF1DAC2 playback path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

Enable DRC in AIF1ADC2 (Left) record path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

Enable DRC in AIF1ADC2 (Right) record path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled w PP, August 2012, Rev 3.4

75

WM8958

REGISTER

ADDRESS

R1344 (0540h)

AIF2 DRC (1)

Pre-Production

2

1

0

AIF2DAC_DRC_

ENA

AIF2ADCL_DRC

_ENA

AIF2ADCR_DRC

_ENA

0

0

0

DESCRIPTION

Enable DRC in AIF2DAC playback path

0 = Disabled

1 = Enabled

Enable DRC in AIF2ADC (Left) record path

0 = Disabled

1 = Enabled

Enable DRC in AIF2ADC (Right) record path

0 = Disabled

1 = Enabled

Table 28 DRC Enable

The following description of the DRC is applicable to all three DRCs. The associated register control fields are described in Table 30, Table 31 and Table 32 for the respective DRCs.

Note that, where the following description refers to register names, the generic prefix [DRC] is quoted:

 For the DRC associated with AIF1 timeslot 0, [DRC] = AIF1DRC1.

 For the DRC associated with AIF1 timeslot 1, [DRC] = AIF1DRC2.

 For the DRC associated with AIF2, [DRC] = AIF2DRC.

DRC COMPRESSION / EXPANSION / LIMITING

The DRC supports two different compression regions, separated by a “Knee” at a specific input amplitude. In the region above the knee, the compression slope [DRC]_HI_COMP applies; in the region below the knee, the compression slope [DRC]_LO_COMP applies.

The DRC also supports a noise gate region, where low-level input signals are heavily attenuated. This function can be enabled or disabled according to the application requirements. The DRC response in this region is defined by the expansion slope [DRC]_NG_EXP.

For additional attenuation of signals in the noise gate region, an additional “knee” can be defined

(shown as “Knee2” in Figure 23). When this knee is enabled, this introduces an infinitely steep dropoff in the DRC response pattern between the [DRC]_LO_COMP and [DRC]_NG_EXP regions.

The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is nearconstant) is illustrated in Figure 23. w PP, August 2012, Rev 3.4

76

Pre-Production

DRC Output Amplitude (dB)

(Y0)

[DRC]_KNEE_OP

[DRC]_KNEE2_OP

Knee2

Knee1

[DRC

]_HI_

COM

P

[DR

C]_

LO

_C

OM

P

WM8958

[DRC]_KNEE2_IP [DRC]_KNEE_IP 0dB

DRC Input Amplitude (dB)

Figure 23 DRC Response Characteristic

The slope of the DRC response is determined by register fields [DRC]_HI_COMP and

[DRC]_LO_COMP. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression.

When the noise gate is enabled, the DRC response in this region is determined by the

[DRC]_NG_EXP register. A slope of 1 indicates constant gain in this region. A slope greater than 1 represents expansion (ie. a change in input amplitude produces a larger change in output amplitude).

When the DRC_KNEE2_OP knee is enabled (“Knee2” in Figure 23), this introduces the vertical line in the response pattern illustrated, resulting in infinitely steep attenuation at this point in the response.

The DRC parameters are listed in Table 29.

4

5

6

7

REF PARAMETER

1 [DRC]_KNEE_IP

DESCRIPTION

Input level at Knee1 (dB)

2

3

[DRC]_KNEE_OP

[DRC]_HI_COMP

Output level at Knee2 (dB)

Compression ratio above Knee1

[DRC]_LO_COMP

[DRC]_KNEE2_IP

[DRC]_NG_EXP

[DRC]_KNEE2_OP

Compression ratio below Knee1

Input level at Knee2 (dB)

Expansion ratio below Knee2

Output level at Knee2 (dB)

Table 29 DRC Response Parameters

The noise gate is enabled when the [DRC]_NG_ENA register is set. When the noise gate is not enabled, parameters 5, 6, 7 above are ignored, and the [DRC]_LO_COMP slope applies to all input signal levels below Knee1.

The DRC_KNEE2_OP knee is enabled when the [DRC]_KNEE2_OP_ENA register is set. When this bit is not set, then parameter 7 above is ignored, and the Knee2 position always coincides with the low end of the [DRC]_LO_COMP region. w PP, August 2012, Rev 3.4

77

WM8958

Pre-Production

The “Knee1” point in Figure 23 is determined by register fields [DRC]_KNEE_IP and

[DRC]_KNEE_OP.

Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation:

GAIN LIMITS

The minimum and maximum gain applied by the DRC is set by register fields [DRC]_MINGAIN,

[DRC]_MAXGAIN and [DRC]_NG_MINGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 23. If the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced.

The minimum gain in the Compression regions of the DRC response is set by [DRC]_MINGAIN. The mimimum gain in the Noise Gate region is set by [DRC]_NG_MINGAIN. The minimum gain limit prevents excessive attenuation of the signal path.

The maximum gain limit set by [DRC]_MAXGAIN prevents quiet signals (or silence) from being excessively amplified. w PP, August 2012, Rev 3.4

78

Pre-Production

WM8958

DYNAMIC CHARACTERISTICS

The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period of time.

The [DRC]_ATK determines how quickly the DRC gain decreases when the signal amplitude is high.

The [DRC]_DCY determines how quickly the DRC gain increases when the signal amplitude is low.

These register fields are described in Table 30, Table 31 and Table 32. Note that the register defaults are suitable for general purpose microphone use.

ANTI-CLIP CONTROL

The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the [DRC]_ANTICLIP bit.

Note that the feed-forward processing increases the latency in the input signal path.

Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal.

Note that the Anti-Clip feature should not be enabled at the same time as the Quick Release feature

(described below) on the same DRC.

QUICK RELEASE CONTROL

The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone.

The Quick Release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of [DRC]_DCY.

The Quick-Release feature is enabled by setting the [DRC]_QR bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by [DRC]_QR_THR, then the normal decay rate ([DRC]_DCY) is ignored and a faster decay rate ([DRC]_QR_DCY) is used instead.

Note that the Quick Release feature should not be enabled at the same time as the Anti-Clip feature

(described above) on the same DRC.

SIGNAL ACTIVITY DETECT

The DRC incorporates a configurable signal detect function, allowing the signal level at the DRC input to be monitored and to be used to trigger other events. This can be used to detect the presence of a microphone signal on an ADC or digital mic channel, or can be used to detect an audio signal received over the digital audio interface.

The Peak signal level or the RMS signal level of the DRC input can be selected as the detection threshold. When the threshold condition is exceeded, an interrupt or GPIO output can be generated.

See “General Purpose Input/Output” for a full description of the applicable control fields. w PP, August 2012, Rev 3.4

79

WM8958 w

REGISTER

ADDRESS

R1088 (0440h)

AIF1 DRC1 (1)

Pre-Production

DRC REGISTER CONTROLS

The AIF1DRC1 control registers are described in Table 30. The AIF1DRC2 control registers are described in Table 31. The AIF2DRC control registers are described in Table 32.

8 AIF1DRC1_NG_

ENA

0

DESCRIPTION

R1089 (0441h)

AIF1 DRC1 (2)

5

4

3

12:9

8:5

4:2

AIF1DRC1_KNE

E2_OP_ENA

AIF1DRC1_QR

AIF1DRC1_ANTI

CLIP

AIF1DRC1_ATK

[3:0]

AIF1DRC1_DCY

[3:0]

AIF1DRC1_MIN

GAIN [2:0]

0

1

1

0100

0010

001

AIF1 DRC1 Noise Gate Enable

0 = Disabled

1 = Enabled

AIF1 DRC1 KNEE2_OP Enable

0 = Disabled

1 = Enabled

AIF1 DRC1 Quick-release Enable

0 = Disabled

1 = Enabled

AIF1 DRC1 Anti-clip Enable

0 = Disabled

1 = Enabled

AIF1 DRC1 Gain attack rate

(seconds/6dB)

0000 = Reserved

0001 = 181us

0010 = 363us

0011 = 726us

0100 = 1.45ms

0101 = 2.9ms

0110 = 5.8ms

0111 = 11.6ms

1000 = 23.2ms

1001 = 46.4ms

1010 = 92.8ms

1011 = 185.6ms

1100-1111 = Reserved

AIF1 DRC1 Gain decay rate

(seconds/6dB)

0000 = 186ms

0001 = 372ms

0010 = 743ms

0011 = 1.49s

0100 = 2.97s

0101 = 5.94s

0110 = 11.89s

0111 = 23.78s

1000 = 47.56s


AIF1 DRC1 Minimum gain to attenuate audio signals

000 = 0dB

001 = -12dB (default)

010 = -18dB

011 = -24dB

100 = -36dB

101 = Reserved

11X = Reserved


80

Pre-Production

REGISTER

ADDRESS

1:0 AIF1DRC1_MAX

GAIN [1:0]

R1090 (0442h)

AIF1 DRC1 (3)

15:12 AIF1DRC1_NG_

MINGAIN [3:0]

11:10 AIF1DRC1_NG_

EXP [1:0]

9:8 AIF1DRC1_QR_

THR [1:0]

7:6 AIF1DRC1_QR_

DCY [1:0]

5:3 AIF1DRC1_HI_C

OMP [2:0]

01

0000

00

00

00

000

WM8958

DESCRIPTION

AIF1 DRC1 Maximum gain to boost audio signals (dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 36dB

AIF1 DRC1 Minimum gain to attenuate audio signals when the noise gate is active.

0000 = -36dB

0001 = -30dB

0010 = -24dB

0011 = -18dB

0100 = -12dB

0101 = -6dB

0110 = 0dB

0111 = 6dB

1000 = 12dB

1001 = 18dB

1010 = 24dB

1011 = 30dB

1100 = 36dB

1101 to 1111 = Reserved

AIF1 DRC1 Noise Gate slope

00 = 1 (no expansion)

01 = 2

10 = 4

11 = 8

AIF1 DRC1 Quick-release threshold

(crest factor in dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF1 DRC1 Quick-release decay rate (seconds/6dB)

00 = 0.725ms

01 = 1.45ms

10 = 5.8ms

11 = Reserved

AIF1 DRC1 Compressor slope

(upper region)

000 = 1 (no compression)

001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

110 = Reserved

111 = Reserved w PP, August 2012, Rev 3.4

81

WM8958

REGISTER

ADDRESS

R1091 (0443h)

AIF1 DRC1 (4)

R1092 (0444h)

AIF1 DRC1 (5)

Pre-Production

DESCRIPTION

2:0

10:5

4:0

9:5

4:0

AIF1DRC1_LO_

COMP [2:0]

AIF1DRC1_KNE

E_IP [5:0]

AIF1DRC1_KNE

E_OP [4:0]

AIF1DRC1_KNE

E2_IP [4:0]

AIF1DRC1_KNE

E2_OP [4:0]

000

000000

00000

00000

00000


(lower region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101 = Reserved

11X = Reserved

AIF1 DRC1 Input signal level at the

Compressor ‘Knee’.

000000 = 0dB

000001 = -0.75dB

000010 = -1.5dB

… (-0.75dB steps)

111100 = -45dB

111101 = Reserved

11111X = Reserved

AIF1 DRC1 Output signal at the


00000 = 0dB

00001 = -0.75dB

00010 = -1.5dB

… (-0.75dB steps)

11110 = -22.5dB

11111 = Reserved


Noise Gate threshold ‘Knee2’.

00000 = -36dB

00001 = -37.5dB

00010 = -39dB

… (-1.5dB steps)

11110 = -81dB

11111 = -82.5dB

Only applicable when

AIF1DRC1_NG_ENA = 1.



00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB


AIF1DRC1_KNEE2_OP_ENA = 1.

Table 30 AIF1 Timeslot 0 DRC Controls w PP, August 2012, Rev 3.4

82

Pre-Production

REGISTER

ADDRESS

R1104 (0450h)

AIF1 DRC2 (1)

8

5

4

3

4:2

AIF1DRC2_NG_

ENA

AIF1DRC2_KNE

E2_OP_ENA

AIF1DRC2_QR

AIF1DRC2_ANTI

CLIP

R1105 (0451h)

AIF1 DRC2 (2)

12:9 AIF1DRC2_ATK

[3:0]

8:5 AIF1DRC2_DCY

[3:0]

AIF1DRC2_MIN

GAIN [2:0]

0

0

1

1

0100

0010

001

WM8958

DESCRIPTION


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

AIF1 DRC2 Quick-release Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

AIF1 DRC2 Gain attack rate

(seconds/6dB)

0000 = Reserved

0001 = 181us

0010 = 363us

0011 = 726us

0100 = 1.45ms

0101 = 2.9ms

0110 = 5.8ms

0111 = 11.6ms

1000 = 23.2ms

1001 = 46.4ms

1010 = 92.8ms

1011 = 185.6ms


AIF1 DRC2 Gain decay rate

(seconds/6dB)

0000 = 186ms

0001 = 372ms

0010 = 743ms

0011 = 1.49s

0100 = 2.97s

0101 = 5.94s

0110 = 11.89s

0111 = 23.78s

1000 = 47.56s



000 = 0dB


010 = -18dB

011 = -24dB

100 = -36dB

101 = Reserved

11X = Reserved w PP, August 2012, Rev 3.4

83

WM8958

REGISTER

ADDRESS

R1106 (0452h)

AIF1 DRC2 (3)

Pre-Production

DESCRIPTION

1:0

15:12

11:10

9:8

7:6

5:3

AIF1DRC2_MAX

GAIN [1:0]

AIF1DRC2_NG_

MINGAIN [3:0]

AIF1DRC2_NG_

EXP [1:0]

AIF1DRC2_QR_

THR [1:0]

AIF1DRC2_QR_

DCY [1:0]

AIF1DRC2_HI_C

OMP [2:0]

01

0000

00

00

00

000


00 = 12dB

01 = 18dB

10 = 24dB

11 = 36dB


0000 = -36dB

0001 = -30dB

0010 = -24dB

0011 = -18dB

0100 = -12dB

0101 = -6dB

0110 = 0dB

0111 = 6dB

1000 = 12dB

1001 = 18dB

1010 = 24dB

1011 = 30dB

1100 = 36dB




01 = 2

10 = 4

11 = 8

AIF1 DRC2 Quick-release threshold


00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB


00 = 0.725ms

01 = 1.45ms

10 = 5.8ms

11 = Reserved


(upper region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

110 = Reserved


84

Pre-Production

REGISTER

ADDRESS

2:0 AIF1DRC2_LO_

COMP [2:0]

R1107 (0453h)

AIF1 DRC2 (4)

10:5 AIF1DRC2_KNE

E_IP [5:0]

4:0 AIF1DRC2_KNE

E_OP [4:0]

R1108 (0454h)

AIF1 DRC2 (5)

9:5 AIF1DRC2_KNE

E2_IP [4:0]

4:0 AIF1DRC2_KNE

E2_OP [4:0]

000

000000

00000

00000

00000

WM8958

DESCRIPTION


(lower region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101 = Reserved

11X = Reserved



000000 = 0dB

000001 = -0.75dB

000010 = -1.5dB

… (-0.75dB steps)

111100 = -45dB

111101 = Reserved

11111X = Reserved



00000 = 0dB

00001 = -0.75dB

00010 = -1.5dB

… (-0.75dB steps)

11110 = -22.5dB

11111 = Reserved



00000 = -36dB

00001 = -37.5dB

00010 = -39dB

… (-1.5dB steps)

11110 = -81dB

11111 = -82.5dB


AIF1DRC2_NG_ENA = 1.



00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB


AIF1DRC2_KNEE2_OP_ENA = 1.

Table 31 AIF1 Timeslot 1 DRC Controls w PP, August 2012, Rev 3.4

85

WM8958

Pre-Production

REGISTER

ADDRESS

R1344 (0540h)

AIF2 DRC (1)

8

5

4

3 AIF2DRC_ANTI

CLIP

R1345 (0541h)

AIF2 DRC (2)

12:9 AIF2DRC_ATK

[3:0]

8:5

4:2

AIF2DRC_NG_E

NA

AIF2DRC_KNEE

2_OP_ENA

AIF2DRC_QR

AIF2DRC_DCY

[3:0]

AIF2DRC_MING

AIN [2:0]

0

0

1

1

0100

0010

001

DESCRIPTION

AIF2 DRC Noise Gate Enable

0 = Disabled

1 = Enabled

AIF2 DRC KNEE2_OP Enable

0 = Disabled

1 = Enabled

AIF2 DRC Quick-release Enable

0 = Disabled

1 = Enabled

AIF2 DRC Anti-clip Enable

0 = Disabled

1 = Enabled

AIF2 DRC Gain attack rate

(seconds/6dB)

0000 = Reserved

0001 = 181us

0010 = 363us

0011 = 726us

0100 = 1.45ms

0101 = 2.9ms

0110 = 5.8ms

0111 = 11.6ms

1000 = 23.2ms

1001 = 46.4ms

1010 = 92.8ms

1011 = 185.6ms


AIF2 DRC Gain decay rate

(seconds/6dB)

0000 = 186ms

0001 = 372ms

0010 = 743ms

0011 = 1.49s

0100 = 2.97s

0101 = 5.94s

0110 = 11.89s

0111 = 23.78s

1000 = 47.56s


AIF2 DRC Minimum gain to attenuate audio signals

000 = 0dB


010 = -18dB

011 = -24dB

100 = -36dB

101 = Reserved

11X = Reserved w PP, August 2012, Rev 3.4

86

Pre-Production

REGISTER

ADDRESS

1:0 AIF2DRC_MAX

GAIN [1:0]

R1346 (0542h)

AIF2 DRC (3)

15:12 AIF2DRC_NG_

MINGAIN [3:0]

11:10 AIF2DRC_NG_E

XP [1:0]

9:8 AIF2DRC_QR_T

HR [1:0]

7:6 AIF2DRC_QR_D

CY [1:0]

5:3 AIF2DRC_HI_C

OMP [2:0]

01

0000

00

00

00

000

WM8958

DESCRIPTION

AIF2 DRC Maximum gain to boost audio signals (dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 36dB

AIF2 DRC Minimum gain to attenuate audio signals when the noise gate is active.

0000 = -36dB

0001 = -30dB

0010 = -24dB

0011 = -18dB

0100 = -12dB

0101 = -6dB

0110 = 0dB

0111 = 6dB

1000 = 12dB

1001 = 18dB

1010 = 24dB

1011 = 30dB

1100 = 36dB


AIF2 DRC Noise Gate slope


01 = 2

10 = 4

11 = 8

AIF2 DRC Quick-release threshold


00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF2 DRC Quick-release decay rate

(seconds/6dB)

00 = 0.725ms

01 = 1.45ms

10 = 5.8ms

11 = Reserved

AIF2 DRC Compressor slope

(upper region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

110 = Reserved


87

WM8958

REGISTER

ADDRESS

R1347 (0543h)

AIF2 DRC (4)

R1348 (0544h)

AIF2 DRC (5)

Pre-Production

DESCRIPTION

2:0

10:5

4:0

9:5

4:0

AIF2DRC_LO_C

OMP [2:0]

AIF2DRC_KNEE

_IP [5:0]

AIF2DRC_KNEE

_OP [4:0]

AIF2DRC_KNEE

2_IP [4:0]

AIF2DRC_KNEE

2_OP [4:0]

000

000000

00000

00000

00000

AIF2 DRC Compressor slope (lower region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101 = Reserved

11X = Reserved

AIF2 DRC Input signal level at the


000000 = 0dB

000001 = -0.75dB

000010 = -1.5dB

… (-0.75dB steps)

111100 = -45dB

111101 = Reserved

11111X = Reserved

AIF2 DRC Output signal at the


00000 = 0dB

00001 = -0.75dB

00010 = -1.5dB

… (-0.75dB steps)

11110 = -22.5dB

11111 = Reserved

AIF2 DRC Input signal level at the


00000 = -36dB

00001 = -37.5dB

00010 = -39dB

… (-1.5dB steps)

11110 = -81dB

11111 = -82.5dB


AIF2DRC_NG_ENA = 1.

AIF2 DRC Output signal at the


00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB


AIF2DRC_KNEE2_OP_ENA = 1.

Table 32 AIF2 DRC Controls w PP, August 2012, Rev 3.4

88

Pre-Production

WM8958

RETUNE TM MOBILE PARAMETRIC EQUALIZER (EQ)

The ReTune TM Mobile Parametric EQ is a circuit which can be enabled in the digital playback path of the WM8958 audio interfaces. The function of the EQ is to adjust the frequency characteristic of the output in order to compensate for unwanted frequency characteristics in the loudspeaker (or other output transducer). It can also be used to tailor the response according to user preferences, for example to accentuate or attenuate specific frequency bands to emulate different sound profiles or environments e.g. concert hall, rock etc.

The WM8958 provides three stereo EQ circuits; these are associated with AIF1 timeslot 0, AIF1 timeslot 1 and AIF2 respectively. The EQ is enabled in these three signal paths using the register bits described in Table 33.


ADDRESS

R1152 (0480h)

AIF1 DAC1

EQ Gains (1)

R1184

(04A0h)

AIF1 DAC2

EQ Gains (1)

R1408 (0580h)

AIF2 EQ Gains

(1)

0

0

0

AIF1DAC1_EQ_E

NA

AIF1DAC2_EQ_E

NA

AIF2DAC_EQ_EN

A

0

0

0

Enable EQ in AIF1DAC1 playback path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Enable EQ in AIF1DAC2 playback path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

Enable EQ in AIF2DAC playback path

0 = Disabled

1 = Enabled

Table 33 ReTune TM Mobile Parametric EQ Enable

The following description of the EQ is applicable to all three EQ circuits. The associated register control fields are described in Table 35, Table 36 and Table 37 for the respective EQs. The EQ provides selective control of 5 frequency bands as described below.

The low frequency band (Band 1) filter can be configured either as a peak filter or a shelving filter.

When configured as a shelving filter, is provides adjustable gain below the Band 1 cut-off frequency.

As a peak filter, it provides adjustable gain within a defined frequency band that is centred on the

Band 1 frequency.

The mid frequency bands (Band 2, Band 3, Band 4) filters are peak filters, which provide adjustable gain around the respective centre frequency.

The high frequency band (Band 5) filter is a shelving filter, which provides adjustable gain above the

Band 5 cut-off frequency.

The EQ can be configured to operate in two modes - “Default” mode or “ReTune TM Mobile” mode. w PP, August 2012, Rev 3.4

89

WM8958

Pre-Production

DEFAULT MODE (5-BAND PARAMETRIC EQ)

In default mode, the cut-off / centre frequencies are fixed as per Table 34. The filter bandwidths are also fixed in default mode. The gain of the individual bands (-12dB to +12dB) can be controlled as described in Table 35.

The cut-off / centre frequencies noted in Table 34 are applicable to a sample rate of 48kHz. When using other sample rates, these frequencies will be scaled in proportion to the selected sample rate for the associated Audio Interface (AIF1 or AIF2).

If AIF1 and AIF2 are operating at different sample rates, then the cut-off / centre frequencies will be different for the two interfaces. Note that the frequencies can be set to other values by using the features described in “ReTune TM Mobile Mode”.

EQ BAND CUT-OFF/CENTRE FREQUENCY

Table 34 EQ Band Cut-off / Centre Frequencies

REGISTER

ADDRESS

R1152 (0480h)

AIF1 DAC1

EQ Gains (1)

15:11 AIF1DAC1_EQ

_B1_GAIN

[4:0]

01100

(0dB)

10:6 AIF1DAC1_EQ

_B2_GAIN

[4:0]

01100

(0dB)

01100

(0dB)

5:1 AIF1DAC1_EQ

_B3_GAIN

[4:0]

R1153 (0481h)

AIF1 DAC1

EQ Gains (2)

15:11 AIF1DAC1_EQ

_B4_GAIN

[4:0]

01100

(0dB)

10:6 AIF1DAC1_EQ

_B5_GAIN

[4:0]

0 AIF1DAC1_EQ

_MODE

01100

(0dB)

0

DESCRIPTION

AIF1DAC1 (AIF1, Timeslot 0) EQ

Band 1 Gain

-12dB to +12dB in 1dB steps



Band 2 Gain




Band 3 Gain




Band 4 Gain




Band 5 Gain




Band 1 Mode

0 = Shelving filter

1 = Peak filter

Table 35 AIF1 Timeslot 0 EQ Band Gain Control w PP, August 2012, Rev 3.4

90

Pre-Production

REGISTER

ADDRESS

R1184

(04A0h)

AIF1 DAC2

EQ Gains (1)

R1185

(04A1h)

AIF1 DAC2

EQ Gains (2)

15:11 AIF1DAC2_EQ

_B1_GAIN

[4:0]

10:6 AIF1DAC2_EQ

_B2_GAIN

[4:0]

5:1 AIF1DAC2_EQ

_B3_GAIN

[4:0]

15:11 AIF1DAC2_EQ

_B4_GAIN

[4:0]

10:6 AIF1DAC2_EQ

_B5_GAIN

[4:0]

0 AIF1DAC2_EQ

_MODE

01100

(0dB)

01100

(0dB)

01100

(0dB)

01100

(0dB)

01100

(0dB)

0

WM8958

DESCRIPTION


Band 1 Gain




Band 2 Gain




Band 3 Gain




Band 4 Gain




Band 5 Gain




Band 1 Mode

0 = Shelving filter

1 = Peak filter

Table 36 AIF1 Timeslot 1 EQ Band Gain Control

REGISTER

ADDRESS

R1408 (0580h)

AIF2 EQ Gains

(1)

R1409 (0581h)

AIF2 EQ Gains

(2)

15:11

10:6

5:1 AIF2DAC_EQ_

B3_GAIN

[4:0]

15:11 AIF2DAC_EQ_

B4_GAIN

[4:0]

10:6

0

AIF2DAC_EQ_

B1_GAIN

[4:0]

AIF2DAC_EQ_

B2_GAIN

[4:0]

AIF2DAC_EQ_

B5_GAIN

[4:0]

AIF2DAC_EQ_

MODE

01100

(0dB)

01100

(0dB)

01100

(0dB)

01100

(0dB)

01100

(0dB)

0

DESCRIPTION

AIF2 EQ Band 1 Gain



AIF2 EQ Band 2 Gain



AIF2 EQ Band 3 Gain



AIF2 EQ Band 4 Gain



AIF2 EQ Band 5 Gain



AIF2 EQ Band 1 Mode

0 = Shelving filter

1 = Peak filter

Table 37 AIF2 EQ Band Gain Control w PP, August 2012, Rev 3.4

91

WM8958

Pre-Production

EQ GAIN SETTING GAIN (dB)

00000 -12

00001 -11

00010 -10

00011 -9

00100 -8

00101 -7

00110 -6

00111 -5

01000 -4

01001 -3

01010 -2

01011 -1

01100 0

01101 +1

01110 +2

01111 +3

10000 +4

10001 +5

10010 +6

10011 +7

10100 +8

10101 +9

10110 +10

10111 +11

11000 +12

11001 to 11111 Reserved

Table 38 EQ Gain Control Range

RETUNE

TM

MOBILE MODE

ReTune TM Mobile mode provides a comprehensive facility for the user to define the cut-off/centre frequencies and filter bandwidth for each EQ band, in addition to the gain controls already described.

This enables the EQ to be accurately customised for a specific transducer characteristic or desired sound profile.

The EQ enable and EQ gain controls are the same as defined for the default mode. The additional coefficients used in ReTune TM Mobile mode are held in registers R1154 to R1172 for AIF1DAC1, registers R1186 to R1204 for AIF1DAC2 and registers R1410 to R1428 for AIF2. These coefficients are derived using tools provided in Wolfson’s WISCE™ evaluation board control software.

Please contact your local Wolfson representative for more details.

Note that the WM8958 audio interfaces may operate at different sample rates concurrently. The EQ settings for each interface must be programmed relative to the applicable sample rate of the corresponding audio interface. If the audio interface sample rate is changed, then different EQ register settings will be required to achieve a given EQ response. w PP, August 2012, Rev 3.4

92

Pre-Production

WM8958

EQ FILTER CHARACTERISTICS

The filter characteristics for each frequency band are shown in Figure 24 to Figure 28. These figures show the frequency response for all available gain settings, using default cut-off/centre frequencies and bandwidth. Note that EQ Band 1 can also be configured as a Peak Filter if required.

15

10

15

10

5 5

0

-5

0

-5

-10 -10

-15

1 10 100 1000

Frequency (Hz)

10000 100000

Figure 24 EQ Band 1 – Low Freq Shelf Filter Response

-15

1 10 100 1000

Frequency (Hz)

10000

Figure 25 EQ Band 2 – Peak Filter Response

100000

-5

-10

5

0

15

10

-15

1 10 100 1000

Frequency (Hz)

10000


15

10

5

0

-5

-10

-15

1 10 10000 100000 100 1000

Frequency (Hz)

Figure 28 EQ Band 5 – High Freq Shelf Filter Response w

15

10

5

0

-5

-10

100000

-15

1 10 100 1000

Frequency (Hz)

10000


100000


93

WM8958

3D STEREO EXPANSION

Pre-Production

The 3D Stereo Expansion is an audio enhancement feature which can be enabled in the digital playback path of the WM8958 audio interfaces. This feature uses configurable cross-talk mechanisms to adjust the depth or width of the stereo audio.

The WM8958 provides three 3D Stereo Expansion circuits; these are associated with AIF1 timeslot 0,

AIF1 timeslot 1 and AIF2 respectively. The 3D Stereo Expansion is enabled and controlled in these signal paths using the register bits described in Table 39.


ADDRESS

R1057 (0421h)

AIF1 DAC1

Filters (2)

R1059 (0423h)

AIF1 DAC2

Filters (2)

R1313 (0521h)

AIF2 DAC

Filters (2)

13:9

8

13:9

8

13:9

8

AIF1DAC1_3D_G

AIN

AIF1DAC1_3D_E

NA

AIF1DAC2_3D_G

AIN

AIF1DAC2_3D_E

NA

AIF2DAC_3D_GA

IN

AIF2DAC_3D_EN

A

00000

0

00000

0

00000

0

AIF1DAC1 playback path (AIF1,

Timeslot 0) 3D Stereo depth

00000 = Off

00001 = Minimum (-16dB)

…(0.915dB steps)

11111 = Maximum (+11.45dB)

Enable 3D Stereo in AIF1DAC1 playback path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

AIF1DAC2 playback path (AIF1,

Timeslot 1) 3D Stereo depth

00000 = Off

00001 = Minimum (-16dB)

…(0.915dB steps)

11111 = Maximum (+11.45dB)

Enable 3D Stereo in AIF1DAC2 playback path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

AIF2DAC playback path 3D Stereo depth

00000 = Off

00001 = Minimum (-16dB)

…(0.915dB steps)

11111 = Maximum (+11.45dB)

Enable 3D Stereo in AIF2DAC playback path

0 = Disabled

1 = Enabled

Table 39 3D Stereo Expansion Control w PP, August 2012, Rev 3.4

94

Pre-Production

WM8958

DIGITAL VOLUME AND FILTER CONTROL

This section describes the digital volume and filter controls of the WM8958 AIF paths.

Digital volume control and High Pass Filter (HPF) control is provided on four AIF1 output (digital record) paths and two AIF2 output (digital record) paths.

Note that, when ultrasonic (4FS) mode is selected on AIF1, then the digital volume control and high pass filter (HPF) control are bypassed on the respective ADC (output) signal paths.

Digital volume, soft-mute and mono mix control is provided on four AIF1 input (digital playback) paths and two AIF2 input (digital playback) paths. A configurable noise gate function is available on each of the digital playback paths.

AIF1 - OUTPUT PATH VOLUME CONTROL

The AIF1 interface supports up to four output channels. A digital volume control is provided on each of these output signal paths, allowing attenuation in the range -71.625dB to +17.625dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by:

0.375  (X-192) dB for 1  X  239; MUTE for X = 0 +17.625dB for 239  X  255

The AIF1ADC1_VU and AIF1ADC2_VU bits control the loading of digital volume control data. When the volume update bit is set to 0, the associated volume control data will be loaded into the respective control register, but will not actually change the digital gain setting.

The AIF1ADC1L and AIF1ADC1R gain settings are updated when a 1 is written to AIF1ADC1_VU.

The AIF1ADC2L and AIF1ADC2R gain settings are updated when a 1 is written to AIF1ADC2_VU.

This makes it possible to update the gain of left and right channels simultaneously.


ADDRESS

R1024

(0400h)

AIF1 ADC1

Left Volume

R1025

(0401h)

AIF1 ADC1

Right Volume

R1028

(0404h)

AIF1 ADC2

Left Volume

8

7:0

8

7:0

8

AIF1ADC1_

VU

AIF1ADC1L

_VOL [7:0]

AIF1ADC1_

VU

AIF1ADC1R

_VOL [7:0]

AIF1ADC2_

VU

N/A

C0h

(0dB)

N/A

C0h

(0dB)

N/A

AIF1ADC1 output path (AIF1, Timeslot 0)

Volume Update


AIF1ADC1L and AIF1ADC1R volume to be updated simultaneously

AIF1ADC1 (Left) output path (AIF1, Timeslot

0) Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB



Volume Update



AIF1ADC1 (Right) output path (AIF1, Timeslot

0) Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB



Volume Update


AIF1ADC2L and AIF1ADC2R volume to be updated simultaneously w PP, August 2012, Rev 3.4

95

WM8958

REGISTER

ADDRESS

R1029

(0405h)

AIF1 ADC2

Right Volume

7:0 AIF1ADC2L

_VOL [7:0]

8

Pre-Production

DESCRIPTION

7:0

AIF1ADC2_

VU

AIF1ADC2R

_VOL [7:0]

C0h

(0dB)

N/A

C0h

(0dB)


1) Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB



Volume Update




1) Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB


Table 40 AIF1 Output Path Volume Control w PP, August 2012, Rev 3.4

96

Pre-Production w

WM8958

6Dh

6Eh

6Fh

70h

71h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

60h

61h

62h

63h

64h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

72h

73h

74h

75h

76h

77h

78h

79h

50h

51h

52h

53h

54h

55h

56h

57h

4Bh

4Ch

4Dh

4Eh

4Fh

AIF1/AIF2

Output Volume

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

-58.125

-57.750

-57.375

-57.000

-56.625

-56.250

-55.875

-55.500

-55.125

-54.750

-54.375

-54.000

-53.625

-63.000

-62.625

-62.250

-61.875

-61.500

-61.125

-60.750

-60.375

-60.000

-59.625

-59.250

-58.875

-58.500

-53.250

-52.875

-52.500

-52.125

-51.750

-51.375

-51.000

-50.625

-50.250

-49.875

-49.500

-49.125

-48.750

-48.375

-67.875

-67.500

-67.125

-66.750

-66.375

-66.000

-65.625

-65.250

-64.875

-64.500

-64.125

-63.750

-63.375

Volume

(dB)

MUTE

-71.625

-71.250

-70.875

-70.500

-70.125

-69.750

-69.375

-69.000

-68.625

-68.250

2Dh

2Eh

2Fh

30h

31h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

20h

21h

22h

23h

24h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

32h

33h

34h

35h

36h

37h

38h

39h

10h

11h

12h

13h

14h

15h

16h

17h

Bh

Ch

Dh

Eh

Fh

AIF1/AIF2

Output Volume

0h

1h

2h

6h

7h

8h

3h

4h

5h

9h

Ah

A5h

A6h

A7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

AFh

B0h

B1h

A0h

A1h

A2h

A3h

A4h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

BAh

BBh

BCh

BDh

BEh

BFh

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

90h

91h

92h

93h

94h

95h

96h

97h

8Bh

8Ch

8Dh

8Eh

8Fh

AIF1/AIF2

Output Volume

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

-34.125

-33.750

-33.375

-33.000

-32.625

-32.250

-31.875

-31.500

-31.125

-30.750

-30.375

-30.000

-29.625

-39.000

-38.625

-38.250

-37.875

-37.500

-37.125

-36.750

-36.375

-36.000

-35.625

-35.250

-34.875

-34.500

-29.250

-28.875

-28.500

-28.125

-27.750

-27.375

-27.000

-26.625

-26.250

-25.875

-25.500

-25.125

-24.750

-24.375

-43.875

-43.500

-43.125

-42.750

-42.375

-42.000

-41.625

-41.250

-40.875

-40.500

-40.125

-39.750

-39.375

Volume

(dB)

-48.000

-47.625

-47.250

-46.875

-46.500

-46.125

-45.750

-45.375

-45.000

-44.625

-44.250

E5h

E6h

E7h

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

F0h

F1h

E0h

E1h

E2h

E3h

E4h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

FAh

FBh

FCh

FDh

FEh

FFh

F2h

F3h

F4h

F5h

F6h

F7h

F8h

F9h

CBh

CCh

CDh

CEh

CFh

D0h

D1h

D2h

D3h

D4h

D5h

D6h

D7h

AIF1/AIF2

Output Volume

C0h

C1h

C2h

C3h

C4h

C5h

C6h

C7h

C8h

C9h

CAh

-10.125

-9.750

-9.375

-9.000

-8.625

-8.250

-7.875

-7.500

-7.125

-6.750

-6.375

-6.000

-5.625

-15.000

-14.625

-14.250

-13.875

-13.500

-13.125

-12.750

-12.375

-12.000

-11.625

-11.250

-10.875

-10.500

-5.250

-4.875

-4.500

-4.125

-3.750

-3.375

-3.000

-2.625

-2.250

-1.875

-1.500

-1.125

-0.750

-0.375

-19.875

-19.500

-19.125

-18.750

-18.375

-18.000

-17.625

-17.250

-16.875

-16.500

-16.125

-15.750

-15.375

Volume

(dB)

-24.000

-23.625

-23.250

-22.875

-22.500

-22.125

-21.750

-21.375

-21.000

-20.625

-20.250

13.875

14.250

14.625

15.000

15.375

15.750

16.125

16.500

16.875

17.250

17.625

17.625

17.625

9.000

9.375

9.750

10.125

10.500

10.875

11.250

11.625

12.000

12.375

12.750

13.125

13.500

17.625

17.625

17.625

17.625

17.625

17.625

17.625

17.625

17.625

17.625

17.625

17.625

17.625

17.625

4.125

4.500

4.875

5.250

5.625

6.000

6.375

6.750

7.125

7.500

7.875

8.250

8.625

Volume

(dB)

0.000

0.375

0.750

1.125

1.500

1.875

2.250

2.625

3.000

3.375

3.750

Table 41 AIF1 Output Path Digital Volume Range

AIF1 - OUTPUT PATH HIGH PASS FILTER

A digital high-pass filter can be enabled in the AIF1 output paths to remove DC offsets. This filter is enabled independently in the four AIF1 output channels using the register bits described in Table 42.

The HPF cut-off frequency for the AIF1 Timeslot 0 channels is set using AIF1ADC1_HPF_CUT. The

HPF cut-off frequency for the AIF1 Timeslot 1 channels is set using AIF1ADC2_HPF_CUT.


97

WM8958 w

Pre-Production

In hi-fi mode, the high pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.7Hz when the sample rate (fs) = 44.1kHz.

In voice modes, the high pass filter is optimised for voice communication; it is recommended to set the cut-off frequency below 300Hz.

Note that the cut-off frequencies scale with the AIF1 sample rate. (The AIF1 sample rate is set using the AIF1_SR register, as described in the “Clocking and Sample Rates” section.) See Table 43 for the

HPF cut-off frequencies at all supported sample rates.


ADDRESS

R1040 (0410h)

AIF1 ADC1

Filters

14:13 AIF1ADC1_

HPF_CUT

[1:0]

R1041 (0411h)

AIF1 ADC2

Filters

12

11

AIF1ADC1L_

HPF

AIF1ADC1R

_HPF

14:13 AIF1ADC2_

12

11

HPF_CUT

[1:0]

AIF1ADC2L_

HPF

AIF1ADC2R

_HPF

00

0

0

00

0

0


Digital HPF cut-off frequency (fc)

00 = Hi-fi mode (fc = 4Hz at fs = 48kHz)

01 = Voice mode 1 (fc = 64Hz at fs = 8kHz)




0) Digital HPF Enable

0 = Disabled

1 = Enabled



0 = Disabled

1 = Enabled


Digital HPF cut-off frequency (fc)







0 = Disabled

1 = Enabled



0 = Disabled

1 = Enabled

Table 42 AIF1 Output Path High Pass Filter

Sample

Frequency

(kHz)

Cut-Off Frequency (Hz) for given value of AIF n ADC n _HPF_CUT

00 01 10 11

8.000 0.7 64 130 267

11.025 0.9 88 178 367

16.000 1.3 127 258 532

22.050 1.9 175 354 733

24.000 2.0 190 386 798

32.000 2.7 253 514 1063

44.100 3.7 348 707 1464

48.000 4.0 379 770 1594

88.200 7.4 696 1414 2928

96.000 8.0 758 1540 3188

Table 43 AIF1 Output Path High Pass Filter Cut-Off Frequencies


98

Pre-Production

WM8958

AIF1 - INPUT PATH VOLUME CONTROL

The AIF1 interface supports up to four input channels. A digital volume control is provided on each of these input signal paths, allowing attenuation in the range -71.625dB to 0dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by:

0.375  (X-192) dB for 1  X  192; MUTE for X = 0 0dB for 192  X  255

The AIF1DAC1_VU and AIF1DAC2_VU bits control the loading of digital volume control data. When the volume update bit is set to 0, the associated volume control data will be loaded into the respective control register, but will not actually change the digital gain setting.

The AIF1DAC1L and AIF1DAC1R gain settings are updated when a 1 is written to AIF1DAC1_VU.

The AIF1DAC2L and AIF1DAC2R gain settings are updated when a 1 is written to AIF1DAC2_VU.

This makes it possible to update the gain of left and right channels simultaneously.

Note that a digital gain function is also available at the audio interface input, to boost the DAC volume when a small signal is received on DACDAT1. See “Digital Audio Interface Control” for further details.

Digital volume control is also possible at the DAC stage of the signal path, after the audio signal has passed through the DAC digital mixers. See “Digital to Analogue Converter (DAC)” for further details.


ADDRESS

R1026

(0402h)

AIF1 DAC1

Left Volume

R1027

(0403h)

AIF1 DAC1

Right Volume

R1030

(0406h)

AIF1 DAC2

Left Volume

8

7:0

8

7:0

8

AIF1DAC1_

VU

AIF1DAC1L

_VOL [7:0]

AIF1DAC1_

VU

AIF1DAC1R

_VOL [7:0]

AIF1DAC2_

VU

N/A

C0h

(0dB)

N/A

C0h

(0dB)

N/A

AIF1DAC1 input path (AIF1, Timeslot 0)

Volume Update


AIF1DAC1L and AIF1DAC1R volume to be updated simultaneously

AIF1DAC1 (Left) input path (AIF1, Timeslot 0)

Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB



Volume Update



AIF1DAC1 (Right) input path (AIF1, Timeslot

0) Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB



Volume Update


AIF1DAC2L and AIF1DAC2R volume to be updated simultaneously w PP, August 2012, Rev 3.4

99

WM8958

REGISTER

ADDRESS

R1031

(0407h)

AIF1 DAC2

Right Volume

7:0 AIF1DAC2L

_VOL [7:0]

8

Pre-Production

DESCRIPTION

7:0

AIF1DAC2_

VU

AIF1DAC2R

_VOL [7:0]

C0h

(0dB)

N/A

C0h

(0dB)

AIF1DAC2 (Left) input path (AIF1, Timeslot 1)

Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB



Volume Update



AIF1DAC2 (Right) input path (AIF1, Timeslot

1) Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB


Table 44 AIF1 Input Path Volume Control w PP, August 2012, Rev 3.4

100

Pre-Production

WM8958

Volume

(dB)

MUTE

-58.125

-57.750

-57.375

-57.000

-56.625

-56.250

-55.875

-55.500

-55.125

-54.750

-54.375

-54.000

-53.625

-53.250

-52.875

-52.500

-52.125

-51.750

-51.375

-63.750

-63.375

-63.000

-62.625

-62.250

-61.875

-61.500

-61.125

-60.750

-60.375

-60.000

-59.625

-59.250

-58.875

-58.500

-51.000

-50.625

-50.250

-49.875

-49.500

-49.125

-48.750

-48.375

-71.625

-71.250

-70.875

-70.500

-70.125

-69.750

-69.375

-69.000

-68.625

-68.250

-67.875

-67.500

-67.125

-66.750

-66.375

-66.000

-65.625

-65.250

-64.875

-64.500

-64.125

AIF1/AIF2 Input

Volume

0h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

16h

17h

18h

19h

1Ah

Ah

Bh

Ch

6h

7h

8h

9h

1h

2h

3h

4h

5h

Dh

Eh

Fh

10h

11h

12h

13h

14h

15h

AIF1/AIF2 Input

Volume

40h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

56h

57h

58h

59h

5Ah

46h

47h

48h

49h

4Ah

4Bh

4Ch

41h

42h

43h

44h

45h

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

Volume

(dB)

-24.000

-10.125

-9.750

-9.375

-9.000

-8.625

-8.250

-7.875

-7.500

-7.125

-6.750

-6.375

-6.000

-5.625

-5.250

-4.875

-4.500

-4.125

-3.750

-3.375

-3.000

-2.625

-2.250

-1.875

-1.500

-1.125

-0.750

-0.375

-15.750

-15.375

-15.000

-14.625

-14.250

-13.875

-13.500

-13.125

-12.750

-12.375

-12.000

-11.625

-11.250

-10.875

-10.500

-23.625

-23.250

-22.875

-22.500

-22.125

-21.750

-21.375

-21.000

-20.625

-20.250

-19.875

-19.500

-19.125

-18.750

-18.375

-18.000

-17.625

-17.250

-16.875

-16.500

-16.125

AIF1/AIF2 Input

Volume

80h

A5h

A6h

A7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

AFh

B0h

B1h

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BDh

BEh

BFh

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

A1h

A2h

A3h

A4h

96h

97h

98h

99h

9Ah

86h

87h

88h

89h

8Ah

8Bh

8Ch

81h

82h

83h

84h

85h

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

Volume

(dB)

-48.000

-34.125

-33.750

-33.375

-33.000

-32.625

-32.250

-31.875

-31.500

-31.125

-30.750

-30.375

-30.000

-29.625

-29.250

-28.875

-28.500

-28.125

-27.750

-27.375

-39.750

-39.375

-39.000

-38.625

-38.250

-37.875

-37.500

-37.125

-36.750

-36.375

-36.000

-35.625

-35.250

-34.875

-34.500

-27.000

-26.625

-26.250

-25.875

-25.500

-25.125

-24.750

-24.375

-47.625

-47.250

-46.875

-46.500

-46.125

-45.750

-45.375

-45.000

-44.625

-44.250

-43.875

-43.500

-43.125

-42.750

-42.375

-42.000

-41.625

-41.250

-40.875

-40.500

-40.125

Volume

(dB)

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

0.000

AIF1/AIF2 Input

Volume

C0h

E5h

E6h

E7h

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

F0h

F1h

F2h

F3h

F4h

F5h

F6h

F7h

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

E0h

E1h

E2h

E3h

E4h

C6h

C7h

C8h

C9h

CAh

CBh

CCh

C1h

C2h

C3h

C4h

C5h

CDh

CEh

CFh

D0h

D1h

D2h

D3h

D4h

D5h

Table 45 AIF1 Input Path Digital Volume Range w PP, August 2012, Rev 3.4

101

WM8958

Pre-Production

AIF1 - INPUT PATH SOFT MUTE CONTROL

The WM8958 provides a soft mute function for each of the AIF1 interface input paths. When the softmute function is selected, the WM8958 gradually attenuates the associated signal paths until the path is entirely muted.

When the soft-mute function is de-selected, the gain will either return instantly to the digital gain setting, or will gradually ramp back to the digital gain setting, depending on the applicable

_UNMUTE_RAMP register field.

The mute and un-mute ramp rate is selectable between two different rates.

The AIF1 input paths are soft-muted by default. To play back an audio signal, the soft-mute must first be de-selected by setting the applicable Mute bit to 0.

The soft un-mute would typically be used during playback of audio data so that when the Mute is subsequently disabled, a smooth transition is scheduled to the previous volume level and pop noise is avoided. This is desirable when resuming playback after pausing during a track. w

The soft un-mute would typically not be required when un-muting at the start of a music file, in order that the first part of the music track is not attenuated. The instant un-mute behaviour is desirable in this case, when starting playback of a new track. See “DAC Soft Mute and Soft Un-Mute” (Figure 29) for an illustration of the soft mute function.


ADDRESS

R1056 (0420h)

AIF1 DAC1

Filters (1)

R1058 (0422h)

AIF1 DAC2

Filters (1)

9

5

4

9

5

4

AIF1DAC1_

MUTE

AIF1DAC1_

MUTERAT

E

AIF1DAC1_

UNMUTE_

RAMP

AIF1DAC2_

MUTE

AIF1DAC2_

MUTERAT

E

AIF1DAC2_

UNMUTE_

RAMP

1

0

0

1

0

0

AIF1DAC1 input path (AIF1, Timeslot 0) Soft

Mute Control

0 = Un-mute

1 = Mute


Mute Ramp Rate

0 = Fast ramp (fs/2, maximum ramp time is

10.7ms at fs=48k)

1 = Slow ramp (fs/32, maximum ramp time is

171ms at fs=48k)

(Note: ramp rate scales with sample rate.)


Unmute Ramp select

0 = Disabling soft-mute (AIF1DAC1_MUTE=0) will cause the volume to change immediately to

AIF1DAC1L_VOL and AIF1DAC1R_VOL settings

1 = Disabling soft-mute (AIF1DAC1_MUTE=0) will cause the DAC volume to ramp up gradually to the AIF1DAC1L_VOL and

AIF1DAC1R_VOL settings


Mute Control

0 = Un-mute

1 = Mute


Mute Ramp Rate


10.7ms at fs=48k)


171ms at fs=48k)



Unmute Ramp select



1 = Disabling soft-mute (AIF1DAC2_MUTE=0)


102

Pre-Production w

WM8958

REGISTER

ADDRESS

DESCRIPTION will cause the DAC volume to ramp up gradually to the AIF1DAC2L_VOL and

AIF1DAC2R_VOL settings

Table 46 AIF1 Input Path Soft Mute Control

AIF1 - INPUT PATH NOISE GATE CONTROL

The WM8958 provides a digital noise gate function for the AIF1 input paths. The noise gate ensures best noise performance when the signal path is idle. When the noise gate is enabled, and the signal level is below the noise gate threshold, then the noise gate is activated, causing the signal path to be muted.

The AIF1 Timeslot 0 input path noise gate is enabled using the AIF1DAC1_NG_ENA register. The

AIF1 Timeslot 1 input path noise gate is enabled using the AIF1DAC2_NG_ENA register.

The noise gate threshold (the signal level below which the noise gate is activated) is set using

AIF1DAC1_NG_THR or AIF1DAC2_NG_THR.

To prevent erroneous triggering, a time delay is applied before the gate is activated; the signal path is only muted when the signal level stays below the threshold for longer than ‘hold time’, determined by the AIF1DAC1_NG_HLD or AIF1DAC2_NG_HLD registers.

When the noise gate is activated, the WM8958 gradually attenuates the associated AIF1 input signal paths until each is entirely muted. When the signal level increases, and the noise gate is de-activated, the gain will return to the AIF1DACnL_VOL and AIF1DACnR_VOL digital gain settings (where n = 1 for AIF1 Timeslot 0, and n = 2 for AIF1 Timeslot 1). The un-mute behaviour can be immediate or gradual; this is determined by the AIF1DACn_MUTERATE and AIF1DACn_UNMUTE_RAMP registers described in Table 46.


ADDRESS

R1072 (0430h)

AIF1 DAC1

Noise Gate

6:5 AIF1DAC1_

NG_HLD

[1:0]

11

R1073 (0431h)

AIF1 DAC2

Noise Gate

3:1

0

6:5

AIF1DAC1_

NG_THR

[2:0]

AIF1DAC1_

NG_ENA

AIF1DAC2_

NG_HLD

[1:0]

100

0

11

AIF1DAC1 input path (AIF1, Timeslot 0) Noise

Gate Hold Time

(delay before noise gate is activated)

00 = 30ms

01 = 125ms

10 = 250ms

11 = 500ms


Gate Threshold

000 = -60dB

001 = -66dB

010 = -72dB

011 = -78dB

100 = -84dB

101 = -90dB

110 = -96dB

111 = -102dB


Gate Enable

0 = Disabled

1 = Enabled


Gate Hold Time


00 = 30ms

01 = 125ms

10 = 250ms

11 = 500ms


103

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

3:1 AIF1DAC2_

NG_THR

[2:0]

0 AIF1DAC2_

NG_ENA

100

0


Gate Threshold

000 = -60dB

001 = -66dB

010 = -72dB

011 = -78dB

100 = -84dB

101 = -90dB

110 = -96dB

111 = -102dB


Gate Enable

0 = Disabled

1 = Enabled

Table 47 AIF1 Input Path Noise Gate Control

AIF1 - INPUT PATH MONO MIX CONTROL

A digital mono mix can be selected on one or both pairs of AIF1 input channels. The mono mix is generated as the sum of the Left and Right AIF channel data. When the mono mix function is enabled, the combined mono signal is applied to the Left channel and the Right channel of the respective AIF1 signal processing and digital mixing paths. To prevent clipping, 6dB attenuation is applied to the mono mix.

REGISTER

ADDRESS

R1056 (0420h)

AIF1 DAC1

Filters (1)

R1058 (0422h)

AIF1 DAC2

Filters (1)

7

7

AIF1DAC1_

MONO

AIF1DAC2_

MONO

0

0

DESCRIPTION

AIF1DAC1 input path (AIF1, Timeslot 0) Mono

Mix Control

0 = Disabled

1 = Enabled

AIF1DAC2 input path (AIF1, Timeslot 1) Mono

Mix Control

0 = Disabled

1 = Enabled

Table 48 AIF1 Input Path Mono Mix Control

AIF2 - OUTPUT PATH VOLUME CONTROL

The AIF2 interface supports two output channels. A digital volume control is provided on each output signal path, allowing attenuation in the range -71.625dB to +17.625dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by:

0.375  (X-192) dB for 1  X  239; MUTE for X = 0 +17.625dB for 239  X  255

The AIF2ADC_VU bit controls the loading of digital volume control data. When AIF2ADC_VU bit is set to 0, the AIF2ADCL_VOL and AIF2ADCR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to AIF2ADC_VU. This makes it possible to update the gain of left and right channels simultaneously. w PP, August 2012, Rev 3.4

104

Pre-Production w

WM8958

REGISTER

ADDRESS

R1280

(0500h)

AIF2 ADC

Left Volume

R1281

(0501h)

AIF2 ADC

Right Volume

8

8

AIF2ADC_V

U

7:0 AIF2ADCL_

VOL [7:0]

AIF2ADC_V

U

7:0 AIF2ADCR_

VOL [7:0]

N/A

C0h

(0dB)

N/A

C0h

(0dB)

DESCRIPTION

AIF2ADC output path Volume Update

Writing a 1 to this bit will cause the AIF2ADCL and AIF2ADCR volume to be updated simultaneously

AIF2ADC (Left) output path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB


AIF2ADC output path Volume Update

Writing a 1 to this bit will cause the AIF2ADCL and AIF2ADCR volume to be updated simultaneously

AIF2ADC (Right) output path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB


Table 49 AIF2 Output Path Volume Control

AIF2 - OUTPUT PATH HIGH PASS FILTER

A digital high-pass filter can be enabled in the AIF2 output paths to remove DC offsets. This filter is enabled independently in the two AIF2 output channels using the register bits described in Table 50.

The HPF cut-off frequency for the AIF2 channels is set using AIF2ADC_HPF_CUT.

In hi-fi mode, the high pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.7Hz when the sample rate (fs) = 44.1kHz.

In voice modes, the high pass filter is optimised for voice communication; it is recommended to set the cut-off frequency below 300Hz.

Note that the cut-off frequencies scale with the AIF2 sample rate. (The AIF2 sample rate is set using the AIF2_SR register, as described in the “Clocking and Sample Rates” section.) See Table 43 for the

HPF cut-off frequencies at all supported sample rates.


ADDRESS

R1296 (0510h)

AIF2 ADC

Filters

14:13 AIF2ADC_H

PF_CUT

[1:0]

12

11

AIF2ADCL_

HPF

AIF2ADCR_

HPF

00

0

0

AIF2ADC output path Digital HPF Cut-Off

Frequency (fc)





AIF2ADC (Left) output path Digital HPF

Enable

0 = Disabled

1 = Enabled

AIF2ADC (Right) output path Digital HPF

Enable

0 = Disabled

1 = Enabled

Table 50 AIF2 Output Path High Pass Filter


105

WM8958 w

Pre-Production

AIF2 - INPUT PATH VOLUME CONTROL

The AIF2 interface supports two input channels. A digital volume control is provided on each input signal path, allowing attenuation in the range -71.625dB to 0dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by:

0.375  (X-192) dB for 1  X  192; MUTE for X = 0 0dB for 192  X  255

The AIF2DAC_VU bit controls the loading of digital volume control data. When AIF2DAC_VU bit is set to 0, the AIF2DACL_VOL and AIF2DACR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to AIF2DAC_VU. This makes it possible to update the gain of left and right channels simultaneously.

Note that a digital gain function is also available at the audio interface input, to boost the DAC volume when a small signal is received on DACDAT2. See “Digital Audio Interface Control” for further details.

Digital volume control is also possible at the DAC stage of the signal path, after the audio signal has passed through the DAC digital mixers. See “Digital to Analogue Converter (DAC)” for further details.


ADDRESS

R1282

(0502h)

AIF2 DAC

Left Volume

R1283

(0503h)

AIF2 DAC

Right Volume

8

7:0

8

7:0

AIF2DAC_V

U

AIF2DACL_

VOL [7:0]

AIF2DAC_V

U

AIF2DACR_

VOL [7:0]

N/A

C0h

(0dB)

N/A

C0h

(0dB)

AIF2DAC input path Volume Update

Writing a 1 to this bit will cause the AIF2DACL and AIF2DACR volume to be updated simultaneously

AIF2DAC (Left) input path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB


AIF2DAC input path Volume Update

Writing a 1 to this bit will cause the AIF2DACL and AIF2DACR volume to be updated simultaneously

AIF2DAC (Right) input path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB


Table 51 AIF2 Input Path Volume Control

AIF2 - INPUT PATH SOFT MUTE CONTROL

The WM8958 provides a soft mute function for each of the AIF2 interface input paths. When the softmute function is selected, the WM8958 gradually attenuates the associated signal paths until the path is entirely muted.

When the soft-mute function is de-selected, the gain will either return instantly to the digital gain setting, or will gradually ramp back to the digital gain setting, depending on the

AIF2DAC_UNMUTE_RAMP register field.

The mute and un-mute ramp rate is selectable between two different rates.

The AIF2 input paths are soft-muted by default. To play back an audio signal, the soft-mute must first be de-selected by setting AIF2DAC_MUTE = 0.


106

Pre-Production w

WM8958

The soft un-mute would typically be used during playback of audio data so that when the Mute is subsequently disabled, a smooth transition is scheduled to the previous volume level and pop noise is avoided. This is desirable when resuming playback after pausing during a track.

The soft un-mute would typically not be required when un-muting at the start of a music file, in order that the first part of the music track is not attenuated. The instant un-mute behaviour is desirable in this case, when starting playback of a new track. See “DAC Soft Mute and Soft Un-Mute” (Figure 29) for an illustration of the soft mute function.


ADDRESS

R1312 (0520h)

AIF2 DAC

Filters (1)

9

5

4

AIF2DAC_M

UTE

AIF2DAC_M

UTERATE

AIF2DAC_U

NMUTE_RA

MP

1

0

0

AIF2DAC input path Soft Mute Control

0 = Un-mute

1 = Mute

AIF2DAC input path Soft Mute Ramp Rate


10.7ms at fs=48k)


171ms at fs=48k)


AIF2DAC input path Unmute Ramp select

0 = Disabling soft-mute (AIF2DAC_MUTE=0) will cause the volume to change immediately to AIF2DACL_VOL and AIF2DACR_VOL settings

1 = Disabling soft-mute (AIF2DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the AIF2DACL_VOL and

AIF2DACR_VOL settings

Table 52 AIF2 Input Path Soft Mute Control

AIF2 - INPUT PATH NOISE GATE CONTROL

The WM8958 provides a digital noise gate function for the AIF2 input paths. The noise gate ensures best noise performance when the signal path is idle. When the noise gate is enabled, and the signal level is below the noise gate threshold, then the noise gate is activated, causing the signal path to be muted.

The AIF2 input path noise gate is enabled using the AIF2DAC_NG_ENA register.

The noise gate threshold (the signal level below which the noise gate is activated) is set using

AIF2DAC_NG_THR.

To prevent erroneous triggering, a time delay is applied before the gate is activated; the signal path is only muted when the signal level stays below the threshold for longer than ‘hold time’, determined by the AIF2DAC_NG_HLD register.

When the noise gate is activated, the WM8958 gradually attenuates the AIF2 input signal paths until each is entirely muted. When the signal level increases, and the noise gate is de-activated, the gain will return to the AIF2DACL_VOL and AIF2DACR_VOL digital gain settings. The un-mute behaviour can be immediate or gradual; this is determined by the AIF2DAC_MUTERATE and

AIF2DAC_UNMUTE_RAMP registers described in Table 52.


ADDRESS

R1328 (0530h)

AIF2 DAC

Noise Gate

6:5

3:1

AIF2DAC_

NG_HLD

[1:0]

AIF2DAC_

NG_THR

11

100

AIF2DAC input path Noise Gate Hold Time


00 = 30ms

01 = 125ms

10 = 250ms

11 = 500ms

AIF2DAC input path Noise Gate Threshold

000 = -60dB


107

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

0

[2:0]

AIF2DAC_

NG_ENA

0

001 = -66dB

010 = -72dB

011 = -78dB

100 = -84dB

101 = -90dB

110 = -96dB

111 = -102dB

AIF2DAC input path Noise Gate Enable

0 = Disabled

1 = Enabled

Table 53 AIF2 Input Path Noise Gate Control

AIF2 - INPUT PATH MONO MIX CONTROL

A digital mono mix can be selected on the AIF2 input channels. The mono mix is generated as the sum of the Left and Right AIF channel data. When the mono mix function is enabled, the combined mono signal is applied to the Left channel and the Right channel of the AIF2 signal processing and digital mixing paths. To prevent clipping, 6dB attenuation is applied to the mono mix.

REGISTER

ADDRESS

R1312 (0520h)

AIF2 DAC

Filters (1)

7 AIF2DAC_M

ONO

Table 54 AIF2 Input Path Mono Mix Control

0

DESCRIPTION

AIF2DAC input path Mono Mix Control

0 = Disabled


108

Pre-Production

WM8958

DIGITAL TO ANALOGUE CONVERTER (DAC)

The WM8958 DACs receive digital input data from the DAC mixers - see “Digital Mixing”. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters four multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion.

A high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit - see

“Clocking and Sample Rates” for details.

The analogue outputs from the DACs can be mixed with analogue line/mic inputs using the line output mixers MIXOUTL / MIXOUTR and the speaker output mixers SPKMIXL / SPKMIXR.

The DACs are enabled using the register bits defined in Table 55.

Note that the DAC clock must be enabled whenever the DACs are enabled.

REGISTER

ADDRESS

R5 (0005h)

Power

Management (5)


3

2

1

0

DAC2L_EN

A

DAC2R_EN

A

DAC1L_EN

A

DAC1R_EN

A

0

0

0

0

DESCRIPTION

Left DAC2 Enable

0 = Disabled

1 = Enabled

Right DAC2 Enable

0 = Disabled

1 = Enabled

Left DAC1 Enable

0 = Disabled

1 = Enabled

Right DAC1 Enable

0 = Disabled

1 = Enabled

Table 55 DAC Enable Control

DAC CLOCKING CONTROL

Clocking for the DACs is derived from SYSCLK. The required clock is enabled when the

SYSDSPCLK_ENA register is set.

The DAC clock rate is configured automatically, according to the AIFn_SR, AIFnCLK_RATE and

DAC_OSR128 registers. (See “Clocking and Sample Rates” for further details of the system clocks and control registers.)

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the DAC clocking is controlled by the AIF1_SR and AIF1CLK_RATE registers.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the DAC clocking is controlled by the AIF2_SR and AIF2CLK_RATE registers.

The supported DAC clocking configurations are described in Table 56 (for DAC_OSR128=0) and

Table 57 (for DAC_OSR128=1). Under default conditions, the DAC_OSR128 bit is not set. w PP, August 2012, Rev 3.4

109

WM8958 w

Pre-Production

SAMPLE

RATE (kHz)


128 192 256 384 512 768 1024 1536

8

11.025

12

16

22.05

24

32

44.1

48

88.2

Note 1

Note 1

Note 1

Note 1

Note 1 Note 1

Note 1 Note 1

Note 1 Note 1

Note 1

Note 1

























































96

When DAC_OSR128=0, DAC operation is only supported for the configurations indicated above

Table 56 DAC Clocking - DAC_OSR128 = 0 (Default)

SAMPLE

RATE (kHz)


128 192 256 384 512 768 1024 1536

8

11.025

12

16

22.05

24

32

44.1

Note 1 Note 1

Note 1 Note 1

Note 1 Note 1















































48

88.2

96

When DAC_OSR128=1, DAC operation is only supported for the configurations indicated above



Table 57 DAC Clocking - DAC_OSR128 = 1

Note 1 - These clocking rates are only supported for ‘simple’ DAC-only playback modes, under the following conditions:

 AIF input is enabled on a single interface (AIF1 or AIF2) only, or is enabled on AIF1 and

AIF2 simultaneously provided AIF1 and AIF2 are synchronised (ie. AIF1CLK_SRC =

AIF2CLK_SRC)

 All AIF output paths are disabled

 All DSP functions (ReTune™ Mobile Parametric Equaliser, 3D stereo expansion and

Dynamic Range Control) are disabled

The clocking requirements in Table 56 and Table 57 are only applicable to the AIFnCLK that is selected as the SYSCLK source. Note that both clocks (AIF1CLK and AIF2CLK) must satisfy the requirements noted in the “Clocking and Sample Rates” section.

The applicable clocks (SYSCLK, and AIF1CLK or AIF2CLK) must be present and enabled when using the Digital to Analogue Converters (DACs).

Note that the presence of a suitable clock is automatically detected by the WM8958; if the clock signal is absent, then any speaker or earpiece output driver(s) associated with the DAC signal paths will be disabled. (This is applicable to the SPKOUTL, SPKOUTR and HPOUT2 outputs only, whenever one or more DAC is routed to these output drivers.)


110

Pre-Production w

WM8958

DAC DIGITAL VOLUME

The output level of each DAC can be controlled digitally over a range from -71.625dB to +12dB in

0.375dB steps. The level of attenuation for an eight-bit code X is given by:

0.375  (X-192) dB for 1  X  224; MUTE for X = 0; 12dB to 224  X  255

Each of the DACs can be muted using the soft mute control bits described in Table 58. The WM8958 always applies a soft mute, where the volume is decreased gradually. The un-mute behaviour is configurable, as described in the “DAC Soft Mute and Soft Un-Mute” section.

The DAC1_VU and DAC2_VU bits control the loading of digital volume control data. When DAC1_VU is set to 0, the DAC1L_VOL or DAC1R_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to DAC1_VU. This makes it possible to update the gain of both channels simultaneously. A similar function for DAC2L and DAC2R is controlled by the DAC2_VU register bit.


ADDRESS

R1552 (0610h)

DAC1 Left

Volume

9 DAC1L_MU

TE

1

R1553 (0611h)

DAC1 Right

Volume

R1554 (0612h)

DAC2 Left

Volume

8

7:0

9

8

7:0

9

8

DAC1_VU

DAC1L_VO

L [7:0]

DAC1R_MU

TE

DAC1_VU

DAC1R_VO

L [7:0]

DAC2L_MU

TE

DAC2_VU

N/A

C0h

(0dB)

1

N/A

C0h

(0dB)

1

N/A

DAC1L Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute

DAC1L and DAC1R Volume Update


DAC1L and DAC1R volume to be updated simultaneously

DAC1L Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB


DAC1R Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute




DAC1R Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB


DAC2L Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute





111

WM8958

REGISTER

ADDRESS

R1555 (0613h)

DAC2 Right

Volume

Pre-Production


7:0 DAC2L_VO

L [7:0]

9

8

7:0

DAC2R_MU

TE

DAC2_VU

DAC2R_VO

L [7:0]

C0h

(0dB)

1

N/A

C0h

(0dB)

DAC2L Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB


DAC2R Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute

DAC2R and DAC2R Volume Update


DAC2R and DAC2R volume to be updated simultaneously

DAC2R Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB


Table 58 DAC Digital Volume Control w PP, August 2012, Rev 3.4

112

Pre-Production

DAC Volume

0h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

Ch

Dh

Eh

Fh

10h

8h

9h

Ah

Bh

1h

2h

3h

4h

5h

6h

7h

11h

12h

13h

14h

15h

16h

17h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

31h

32h

33h

34h

35h

36h

37h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

Volume

(dB)

MUTE

-63.000

-62.625

-62.250

-61.875

-61.500

-61.125

-60.750

-60.375

-60.000

-59.625

-59.250

-58.875

-58.500

-58.125

-57.750

-57.375

-71.625

-71.250

-70.875

-70.500

-70.125

-69.750

-69.375

-69.000

-68.625

-68.250

-67.875

-67.500

-67.125

-66.750

-66.375

-66.000

-65.625

-65.250

-64.875

-64.500

-64.125

-63.750

-63.375

-53.625

-53.250

-52.875

-52.500

-52.125

-51.750

-51.375

-51.000

-50.625

-50.250

-49.875

-49.500

-49.125

-48.750

-48.375

-57.000

-56.625

-56.250

-55.875

-55.500

-55.125

-54.750

-54.375

-54.000

DAC Volume

40h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

67h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

41h

42h

43h

44h

45h

46h

47h

51h

52h

53h

54h

55h

56h

57h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

71h

72h

73h

74h

75h

76h

77h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

Volume

(dB)

-48.000

-39.000

-38.625

-38.250

-37.875

-37.500

-37.125

-36.750

-36.375

-36.000

-35.625

-35.250

-34.875

-34.500

-34.125

-33.750

-33.375

-47.625

-47.250

-46.875

-46.500

-46.125

-45.750

-45.375

-45.000

-44.625

-44.250

-43.875

-43.500

-43.125

-42.750

-42.375

-42.000

-41.625

-41.250

-40.875

-40.500

-40.125

-39.750

-39.375

-29.625

-29.250

-28.875

-28.500

-28.125

-27.750

-27.375

-27.000

-26.625

-26.250

-25.875

-25.500

-25.125

-24.750

-24.375

-33.000

-32.625

-32.250

-31.875

-31.500

-31.125

-30.750

-30.375

-30.000

Table 59 DAC Digital Volume Range

DAC Volume

80h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

A1h

A2h

A3h

A4h

A5h

A6h

A7h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

81h

82h

83h

84h

85h

86h

87h

91h

92h

93h

94h

95h

96h

97h

B8h

B9h

BAh

BBh

BCh

BDh

BEh

BFh

B1h

B2h

B3h

B4h

B5h

B6h

B7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

AFh

B0h w

DAC Volume

C0h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

E0h

E1h

E2h

E3h

E4h

E5h

E6h

E7h

C8h

C9h

CAh

CBh

CCh

CDh

CEh

CFh

D0h

C1h

C2h

C3h

C4h

C5h

C6h

C7h

D1h

D2h

D3h

D4h

D5h

D6h

D7h

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

F1h

F2h

F3h

F4h

F5h

F6h

F7h

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

F0h

Volume

(dB)

-24.000

-15.000

-14.625

-14.250

-13.875

-13.500

-13.125

-12.750

-12.375

-12.000

-11.625

-11.250

-10.875

-10.500

-10.125

-9.750

-9.375

-23.625

-23.250

-22.875

-22.500

-22.125

-21.750

-21.375

-21.000

-20.625

-20.250

-19.875

-19.500

-19.125

-18.750

-18.375

-18.000

-17.625

-17.250

-16.875

-16.500

-16.125

-15.750

-15.375

-5.625

-5.250

-4.875

-4.500

-4.125

-3.750

-3.375

-3.000

-2.625

-2.250

-1.875

-1.500

-1.125

-0.750

-0.375

-9.000

-8.625

-8.250

-7.875

-7.500

-7.125

-6.750

-6.375

-6.000

WM8958

7.875

8.250

8.625

9.000

9.375

9.750

10.125

10.500

10.875

11.250

11.625

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

3.000

3.375

3.750

4.125

4.500

4.875

5.250

5.625

6.000

6.375

6.750

7.125

7.500

Volume

(dB)

0.000

0.375

0.750

1.125

1.500

1.875

2.250

2.625

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000

12.000


113

WM8958

Pre-Production

DAC SOFT MUTE AND SOFT UN-MUTE

The WM8958 has a soft mute function which ensures that a gradual attenuation is applied to the DAC outputs when the mute is asserted. The soft mute rate can be selected using the DAC_MUTERATE bit.

When a mute bit is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the DAC_SOFTMUTEMODE register bit. If the gradual un-mute ramp is selected (DAC_SOFTMUTEMODE = 1), then the un-mute rate is determined by the DAC_MUTERATE bit.

Note that each DAC is soft-muted by default. To play back an audio signal, the mute must first be disabled by setting the applicable mute control to 0 (see Table 58).

Soft Mute Mode would typically be enabled (DAC_SOFTMUTEMODE = 1) when using mute during playback of audio data so that when the mute is subsequently disabled, the volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track).

Soft Mute Mode would typically be disabled (DAC_SOFTMUTEMODE = 0) when un-muting at the start of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks).

The DAC soft-mute function is illustrated in Figure 29 for DAC1L and DAC1R. The same function is applicable to DAC2L and DAC2R also.

DAC1L_VOL or DAC1R_VOL = [non-zero] = 00000000 = [non-zero]

DAC muting and un-muting using volume control bits

DAC1L_VOL and DAC1R_VOL

DAC1L_MUTE = 0

DAC1R_MUTE = 0

DAC_SOFTMUTEMODE = 0

DAC1L_MUTE = 1

DAC1R_MUTE = 1

DAC1L_MUTE = 0

DAC1R_MUTE = 0

DAC muting and un-muting using soft mute bits

DAC1L_MUTE or DAC1R_MUTE

Soft mute mode not enabled (DAC_SOFTMUTEMODE = 0).

DAC muting and un-muting using soft mute bit DAC_MUTE.

Soft mute mode enabled (DAC_SOFTMUTEMODE = 1).

DAC1L_MUTE = 0

DAC1R_MUTE = 0

DAC_SOFTMUTEMODE = 1

DAC1L_MUTE = 1

DAC1R_MUTE = 1

DAC1L_MUTE = 0

DAC1R_MUTE = 0

Figure 29 DAC Soft Mute Control

The DAC Soft Mute register controls are defined in Table 60.

The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 are selectable. The ramp rate determines the rate at which the volume will be increased or decreased. Note that the actual ramp time depends on the extent of the difference between the muted and un-muted volume settings. w PP, August 2012, Rev 3.4

114

Pre-Production

REGISTER

ADDRESS

R1556 (0614h)

DAC Softmute


1

0

DAC_SOFT

MUTEMODE

DAC_MUTE

RATE

0

0

WM8958

DESCRIPTION

DAC Unmute Ramp select

0 = Disabling soft-mute

(DAC[1/2][L/R]_MUTE=0) will cause the DAC volume to change immediately to DAC[1/2][L/R]_VOL settings

1 = Disabling soft-mute

(DAC[1/2][L/R]_MUTE=0) will cause the DAC volume to ramp up gradually to the DAC[1/2][L/R]_VOL settings

DAC Soft Mute Ramp Rate

0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k)

1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k)


Table 60 DAC Soft-Mute Control w PP, August 2012, Rev 3.4

115

WM8958

Pre-Production

ANALOGUE OUTPUT SIGNAL PATH

The WM8958 output routing and mixers provide a high degree of flexibility, allowing operation of many simultaneous signal paths through the device to a variety of analogue outputs. The outputs include a ground referenced headphone driver, two switchable class D/AB loudspeaker drivers, an ear speaker driver and four highly flexible line drivers. See “Analogue Outputs” for further details of these outputs.

The WM8958 output signal paths and control registers are illustrated in Figure 30. w

Figure 30 Control Registers for Output Signal Path


116

Pre-Production w

WM8958

OUTPUT SIGNAL PATHS ENABLE

The output mixers and drivers can be independently enabled and disabled as described in Table 61.

The supply rails for headphone outputs HPOUT1L and HPOUT1R are generated using an integrated dual-mode Charge Pump, which must be enabled whenever the headphone outputs are used. See the “Charge Pump” section for details on enabling and configuring this circuit.

Note that the headphone outputs HPOUT1L and HPOUT1R have dedicated output PGAs and volume controls. As a result, a low power consumption DAC playback path can be supported without needing to enable the output mixers MIXOUTL / MIXOUTR or the mixer output PGAs MIXOUTLVOL /

MIXOUTRVOL.

Note that the Headphone Outputs are also controlled by fields located within Register R96, which provide suppression of pops & clicks when enabling and disabling the HPOUT1L and HPOUT1R signal paths. These registers are described in the following “Headphone Signal Paths Enable” section.

Under recommended usage conditions, the Headphone Pop Suppression control bits will be configured by scheduling the default Start-Up and Shutdown sequences as described in the “Control

Write Sequencer” section. In these cases, the user does not need to set the register fields in R1 and

R96 directly.

For normal operation of the output signal paths, the reference voltage VMID and the bias current must also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls



ADDRESS

R1 (0001h)

Power

Management

(1)

R3 (0003h)

Power

Management

(3)

13

12

11

9

8

13

12

SPKOUTR_ENA

SPKOUTL_ENA

HPOUT2_ENA

HPOUT1L_ENA

HPOUT1R_ENA

LINEOUT1N_ENA

LINEOUT1P_ENA

0

0

0

0

0

0

0

SPKMIXR Mixer, SPKRVOL PGA and SPKOUTR Output Enable

0 = Disabled

1 = Enabled

SPKMIXL Mixer, SPKLVOL PGA and SPKOUTL Output Enable

0 = Disabled

1 = Enabled

HPOUT2 Output Stage Enable

0 = Disabled

1 = Enabled

Enables HPOUT1L input stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set as the first step of the

HPOUT1L Enable sequence.

Enables HPOUT1R input stage

0 = Disabled

1 = Enabled


HPOUT1R Enable sequence.

LINEOUT1N Line Out and

LINEOUT1NMIX Enable

0 = Disabled

1 = Enabled

LINEOUT1P Line Out and

LINEOUT1PMIX Enable

0 = Disabled

1 = Enabled


117

WM8958

REGISTER

ADDRESS

R56 (0038h)

AntiPOP (1)

Pre-Production

DESCRIPTION

11 LINEOUT2N_ENA

10

9

8

7

6

5

4

6

LINEOUT2P_ENA

SPKRVOL_ENA

SPKLVOL_ENA

MIXOUTLVOL_ENA

MIXOUTRVOL_ENA

MIXOUTL_ENA

MIXOUTR_ENA

HPOUT2_IN_ENA

0

0

0

0

0

0

0

0

0


LINEOUT2NMIX Enable

0 = Disabled

1 = Enabled


LINEOUT2PMIX Enable

0 = Disabled

1 = Enabled

SPKMIXR Mixer and SPKRVOL

PGA Enable

0 = Disabled

1 = Enabled

Note that SPKMIXR and SPKRVOL are also enabled when

SPKOUTR_ENA is set.

SPKMIXL Mixer and SPKLVOL

PGA Enable

0 = Disabled

1 = Enabled

Note that SPKMIXL and SPKLVOL are also enabled when

SPKOUTL_ENA is set.

MIXOUTL Left Volume Control

Enable

0 = Disabled

1 = Enabled

MIXOUTR Right Volume Control

Enable

0 = Disabled

1 = Enabled

MIXOUTL Left Output Mixer Enable

0 = Disabled

1 = Enabled

MIXOUTR Right Output Mixer

Enable

0 = Disabled

1 = Enabled

HPOUT2MIX Mixer and Input Stage

Enable

0 = Disabled

1 = Enabled

Table 61 Output Signal Paths Enable w PP, August 2012, Rev 3.4

118

Pre-Production

WM8958

HEADPHONE SIGNAL PATHS ENABLE

The HPOUT1L and HPOUT1R output paths can be actively discharged to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known output stage condition prior to enabling the VMID reference voltage. This is also desirable in shutdown to prevent the external connections from being affected by the internal circuits. The HPOUT1L and HPOUT1R outputs are shorted to AGND by default; the short circuit is removed on each of these paths by setting the applicable fields HPOUT1L_RMV_SHORT or HPOUT1R_RMV_SHORT.

The ground-referenced Headphone output drivers are designed to suppress pops and clicks when enabled or disabled. However, it is necessary to control the drivers in accordance with a defined sequence in start-up and shutdown to achieve the pop suppression. It is also necessary to schedule the DC Servo offset correction at the appropriate point in the sequence (see “DC Servo”). Table 62 and Table 63 describe the recommended sequences for enabling and disabling these output drivers.

Step 1

Step 2

Step 3

HPOUT1L_ENA = 1

HPOUT1R_ENA = 1

20 s delay

HPOUT1L_DLY = 1

HPOUT1R_DLY = 1

Step 4

DC offset correction

Step 5 HPOUT1L_OUTP = 1

HPOUT1L_RMV_SHORT = 1

HPOUT1R_OUTP = 1

HPOUT1R_RMV_SHORT = 1

Table 62 Headphone Output Enable Sequence

Step 1

Step 2


HPOUT1L_DLY = 0

HPOUT1L_OUTP = 0


HPOUT1R_DLY = 0

HPOUT1R_OUTP = 0

HPOUT1L_ENA = 0

HPOUT1R_ENA = 0

Table 63 Headphone Output Disable Sequence

The register bits relating to pop suppression control are defined in Table 64. w PP, August 2012, Rev 3.4

119

WM8958 w

REGISTER

ADDRESS

R1 (0001h)

Power

Management

(1)

R96 (0060h)

Analogue HP

(1)

Pre-Production


9

8

7

6

5

3

2

1

HPOUT1L_ENA

HPOUT1R_ENA

HPOUT1L_RMV_

SHORT

HPOUT1L_OUTP

HPOUT1L_DLY

HPOUT1R_RMV_

SHORT

HPOUT1R_OUTP

HPOUT1R_DLY

0

0

0

0

0

0

0

0


0 = Disabled

1 = Enabled




0 = Disabled

1 = Enabled



Removes HPOUT1L short

0 = HPOUT1L short enabled

1 = HPOUT1L short removed

For normal operation, this bit should be set as the final step of the


Enables HPOUT1L output stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled.

Enables HPOUT1L intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1L_ENA.

Removes HPOUT1R short

0 = HPOUT1R short enabled

1 = HPOUT1R short removed

For normal operation, this bit should be set as the final step of the


Enables HPOUT1R output stage

0 = Disabled

1 = Enabled


Enables HPOUT1R intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1R_ENA.

Table 64 Headphone Output Signal Paths Control


120

Pre-Production

WM8958

OUTPUT MIXER CONTROL

The Output Mixer path select and volume controls are described in Table 65 for the Left Channel

(MIXOUTL) and Table 66 for the Right Channel (MIXOUTR). The gain of each of input path may be controlled independently in the range 0dB to -9dB.

Note that the DAC input levels may also be controlled by the DAC digital volume controls (see “Digital to Analogue Converter (DAC)”) and the Audio Interface digital volume controls (see “Digital Volume and Filter Control”).

When using the IN2LP, IN2LN, IN2RP or IN2RN signal paths to the output mixers, the buffered VMID reference must be enabled, using the VMID_BUF_ENA register, as described in “Reference Voltages and Master Bias”.


ADDRESS

R45 (002Dh)

Output Mixer

(1)

R49 (0031h)

Output Mixer

(5)

R45 (002Dh)

Output Mixer

(1)

R47 (002Fh)

Output Mixer

(3)

R45 (002Dh)

Output Mixer

(1)

R47 (002Fh)

Output Mixer

(3)

R45 (002Dh)

Output Mixer

(1)

5

8:6

4

8:6

2

2:0

3

IN2RN_TO_MIXOUTL

IN2RN_MIXOUTL_VOL

[2:0]

IN2LN_TO_MIXOUTL

IN2LN_MIXOUTL_VOL

[2:0]

IN1L_TO_MIXOUTL

IN1L_MIXOUTL_VOL

[2:0]

IN1R_TO_MIXOUTL

0

000

0

000

0

000

0

IN2RN to MIXOUTL Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN2RN input to

MIXOUTL.

IN2RN to MIXOUTL Volume

0dB to -9dB in 3dB steps

X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2LN to MIXOUTL Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN2LN input to

MIXOUTL.

IN2LN to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1L PGA Output to MIXOUTL

Mute

0 = Mute

1 = Un-mute

IN1L PGA Output to MIXOUTL

Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1R PGA Output to MIXOUTL

Mute

0 = Mute

1 = Un-mute w PP, August 2012, Rev 3.4

121

WM8958 w

Pre-Production

REGISTER

ADDRESS

R47 (002Fh)

Output Mixer

(3)

5:3 IN1R_MIXOUTL_VOL

[2:0]

R45 (002Dh)

Output Mixer

(1)

R47 (002Fh)

Output Mixer

(3)

R45 (002Dh)

Output Mixer

(1)

R49 (0031h)

Output Mixer

(5)

R45 (002Dh)

Output Mixer

(1)

R49 (0031h)

Output Mixer

(5)

R45 (002Dh)

Output Mixer

(1)

R49 (0031h)

Output Mixer

(5)

1

11:9

7

5:3

6

2:0

0

IN2LP_TO_MIXOUTL

IN2LP_MIXOUTL_VOL

[2:0]

MIXINR_TO_MIXOUTL

MIXINR_MIXOUTL_VO

L [2:0]

MIXINL_TO_MIXOUTL

MIXINL_MIXOUTL_VOL

[2:0]

DAC1L_TO_MIXOUTL

11:9 DAC1L_MIXOUTL_VOL

[2:0]

000

0

000

0

000

0

000

0

000

DESCRIPTION

IN1R PGA Output to MIXOUTL

Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2LP to MIXOUTL Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN2LP input to

MIXOUTL.

IN2LP to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

MIXINR Output (Right ADC bypass) to MIXOUTL Mute

0 = Mute

1 = Un-mute

MIXINR Output (Right ADC bypass) to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

MIXINL Output (Left ADC bypass) to MIXOUTL Mute

0 = Mute

1 = Un-mute

MIXINL Output (Left ADC bypass) to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

Left DAC1 to MIXOUTL Mute

0 = Mute

1 = Un-mute

Left DAC1 to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

Table 65 Left Output Mixer (MIXOUTL) Control


122

Pre-Production w

REGISTER

ADDRESS

R46 (002Eh)

Output Mixer

(2)

R50 (0032h)

Output Mixer

(6)

8:6 IN2LN_MIXOUTR_VOL

[2:0]

000

R46 (002Eh)

Output Mixer

(2)

R46 (002Eh)

Output Mixer

(2)

R48 (0030h)

Output Mixer

(4)

3 IN1L_TO_MIXOUTR

5:3 IN1L_MIXOUTR_VOL

[2:0]

R46 (002Eh)

Output Mixer

(2)

R48 (0030h)

Output Mixer

(4)

2 IN1R_TO_MIXOUTR

2:0 IN1R_MIXOUTR_VOL

[2:0]

R46 (002Eh)

Output Mixer

(2)

5 IN2LN_TO_MIXOUTR

4 IN2RN_TO_MIXOUTR

1 IN2RP_TO_MIXOUTR

0

0

R48 (0030h)

Output Mixer

(4)

8:6 IN2RN_MIXOUTR_VOL

[2:0]

000

0

000

0

000

0

WM8958

DESCRIPTION

IN2LN to MIXOUTR Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN2LN input to

MIXOUTR.

IN2LN to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2RN to MIXOUTR Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN2RN input to

MIXOUTR.

IN2RN to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1L PGA Output to MIXOUTR Mute

0 = Mute

1 = Un-mute

IN1L PGA Output to MIXOUTR

Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1R PGA Output to MIXOUTR

Mute

0 = Mute

1 = Un-mute

IN1R PGA Output to MIXOUTR

Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2RP to MIXOUTR Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN2RP input to

MIXOUTR.


123

WM8958

REGISTER

ADDRESS

R48 (0030h)

Output Mixer

(4)

11:9 IN2RP_MIXOUTR_VOL

[2:0]

R46 (002Eh)

Output Mixer

(2)

R50 (0032h)

Output Mixer

(6)

R46 (002Eh)

Output Mixer

(2)

R50 (0032h)

Output Mixer

(6)

R46 (002Eh)

Output Mixer

(2)

R50 (0032h)

Output Mixer

(6)

7

5:3

6

2:0

0

Pre-Production

11:9

MIXINL_TO_MIXOUTR

MIXINL_MIXOUTR_VO

L[2:0]

MIXINR_TO_MIXOUTR

MIXINR_MIXOUTR_VO

L [2:0]

DAC1R_TO_MIXOUTR

DAC1R_MIXOUTR_VO

L [2:0]

000

0

000

0

000

0

000

DESCRIPTION

IN2RP to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

MIXINL Output (Left ADC bypass) to

MIXOUTR Mute

0 = Mute

1 = Un-mute

MIXINL Output (Left ADC bypass) to

MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

MIXINR Output (Right ADC bypass) to MIXOUTR Mute

0 = Mute

1 = Un-mute

MIXINR Output (Right ADC bypass) to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

Right DAC1 to MIXOUTR Mute

0 = Mute

1 = Un-mute

Right DAC1 to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

Table 66 Right Output Mixer (MIXOUTR) Control w PP, August 2012, Rev 3.4

124

Pre-Production

WM8958

SPEAKER MIXER CONTROL

The Speaker Mixer path select and volume controls are described in Table 67 for the Left Channel

(SPKMIXL) and Table 68 for the Right Channel (SPKMIXR).

Care should be taken when enabling more than one path to a speaker mixer in order to avoid clipping. The gain of each input path is adjustable using a selectable -3dB control in each path to facilitate this. Each Speaker Mixer output is also controlled by an additional independent volume control.

Note that the DAC input levels may also be controlled by the DAC digital volume controls (see “Digital to Analogue Converter (DAC)”) and the Audio Interface digital volume controls (see “Digital Volume and Filter Control”).

When using the IN1LP or IN1RP signal paths to the speaker mixers, the buffered VMID reference must be enabled, using the VMID_BUF_ENA register, as described in “Reference Voltages and

Master Bias”. w PP, August 2012, Rev 3.4

125

WM8958

REGISTER

ADDRESS

R54 (0034h)

Speaker Mixer

9

R34 (0022h)

SPKMIXL

Attenuation

7

5

3

1

6

5

4

3

2

Pre-Production

DESCRIPTION

1:0

DAC2L_TO_SPKMIXL

MIXINL_TO_SPKMIXL

IN1LP_TO_SPKMIXL

MIXOUTL_TO_SPKMIX

L

DAC1L_TO_SPKMIXL

DAC2L_SPKMIXL_VOL

MIXINL_SPKMIXL_VOL

IN1LP_SPKMIXL_VOL

MIXOUTL_SPKMIXL_V

OL

DAC1L_SPKMIXL_VOL

SPKMIXL_VOL [1:0]

0

0

0

0

0

0

0

0

0

0

11

Left DAC2 to SPKMIXL Mute

0 = Mute

1 = Un-mute

MIXINL (Left ADC bypass) to

SPKMIXL Mute

0 = Mute

1 = Un-mute

IN1LP to SPKMIXL Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN1LP input to SPKMIXL.

Left Mixer Output to SPKMIXL

Mute

0 = Mute

1 = Un-mute


0 = Mute

1 = Un-mute

Left DAC2 to SPKMIXL Fine

Volume Control

0 = 0dB

1 = -3dB

MIXINL (Left ADC bypass) to

SPKMIXL Fine Volume Control

0 = 0dB

1 = -3dB

IN1LP to SPKMIXL Fine Volume

Control

0 = 0dB

1 = -3dB

Left Mixer Output to SPKMIXL Fine

Volume Control

0 = 0dB

1 = -3dB

Left DAC1 to SPKMIXL Fine

Volume Control

0 = 0dB

1 = -3dB

Left Speaker Mixer Volume Control

00 = 0dB

01 = -6dB

10 = -12dB

11 = Mute

Table 67 Left Speaker Mixer (SPKMIXL) Control w PP, August 2012, Rev 3.4

126

Pre-Production

REGISTER

ADDRESS

R54 (0034h)

Speaker

Mixer


8 DAC2R_TO_SPKMIXR 0

6 MIXINR_TO_SPKMIXR 0

R35 (0023h)

SPKMIXR

Attenuation

4

2

0

6

5

4

3

2

1:0

IN1RP_TO_SPKMIXR

MIXOUTR_TO_SPKMIX

R

DAC1R_TO_SPKMIXR

DAC2R_SPKMIXR_VOL

MIXINR_SPKMIXR_VOL

IN1RP_SPKMIXR_VOL

MIXOUTR_SPKMIXR_V

OL

DAC1R_SPKMIXR_VOL

SPKMIXR_VOL [1:0]

0

0

0

0

0

0

0

0

11

WM8958

DESCRIPTION

Right DAC2 to SPKMIXR Mute

0 = Mute

1 = Un-mute

MIXINR (Right ADC bypass) to

SPKMIXR Mute

0 = Mute

1 = Un-mute

IN1RP to SPKMIXR Mute

0 = Mute

1 = Un-mute

Note that VMID_BUF_ENA must be set when using the IN1RP input to SPKMIXR.

Right Mixer Output to SPKMIXR

Mute

0 = Mute

1 = Un-mute


0 = Mute

1 = Un-mute

Right DAC2 to SPKMIXR Fine

Volume Control

0 = 0dB

1 = -3dB

MIXINR (Right ADC bypass) to

SPKMIXR Fine Volume Control

0 = 0dB

1 = -3dB

IN1RP to SPKMIXR Fine Volume

Control

0 = 0dB

1 = -3dB

Right Mixer Output to SPKMIXR

Fine Volume Control

0 = 0dB

1 = -3dB

Right DAC1 to SPKMIXR Fine

Volume Control

0 = 0dB

1 = -3dB

Right Speaker Mixer Volume

Control

00 = 0dB

01 = -6dB

10 = -12dB

11 = Mute

Table 68 Right Speaker Mixer (SPKMIXR) Control w PP, August 2012, Rev 3.4

127

WM8958 w

Pre-Production

OUTPUT SIGNAL PATH VOLUME CONTROL

There are six output PGAs - MIXOUTLVOL, MIXOUTRVOL, HPOUT1LVOL, HPOUT1RVOL,

SPKLVOL and SPKRVOL. Each can be independently controlled, with MIXOUTLVOL and

MIXOUTRVOL providing volume control to both the earpiece and line drivers, HPOUT1LVOL and

HPOUT1RVOL to the headphone driver, and SPKLVOL and SPKRVOL to the speaker drivers.

The volume control of each of these output PGAs can be adjusted over a wide range of values. To minimise pop noise, it is recommended that only the MIXOUTLVOL, MIXOUTRVOL, HPOUT1LVOL,

HPOUT1RVOL, SPKLVOL and SPKRVOL are modified while the output signal path is active. Other gain controls are provided in the signal paths to provide scaling of signals from different sources, and to prevent clipping when multiple signals are mixed. However, to prevent pop noise, it is recommended that those other gain controls should not be modified while the signal path is active.

To prevent "zipper noise", a zero-cross function is provided on the output PGAs. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long period without zero-crossings, a timeout function is provided. When the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout clock is enabled using TOCLK_ENA; the timeout period is set by TOCLK_DIV. See “Clocking and Sample Rates” for more information on these fields.

The mixer output PGA controls are shown in Table 69. The MIXOUT_VU bits control the loading of the output mixer PGA volume data. When MIXOUT_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The output mixer PGA volume settings are both updated when a 1 is written to either MIXOUT_VU bit. This makes it possible to update the gain of both output paths simultaneously.


ADDRESS

R32 (0020h)

Left OPGA

Volume

8 MIXOUT_VU N/A

R33 (0021h)

Right OPGA

Volume

7

6

5:0

8

7

6

MIXOUTL_ZC

MIXOUTL_MUTE_N

MIXOUTL_VOL [5:0]

MIXOUT_VU

MIXOUTR_ZC

MIXOUTR_MUTE_N

0

1

39h

(0dB)

N/A

0

1

Mixer Output PGA Volume Update

Writing a 1 to this bit will update

MIXOUTLVOL and MIXOUTRVOL volumes simultaneously.

MIXOUTLVOL (Left Mixer Output

PGA) Zero Cross Enable

0 = Zero cross disabled

1 = Zero cross enabled


PGA) Mute

0 = Mute

1 = Un-mute


PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB

(See Table 72 for output PGA volume control range)

Mixer Output PGA Volume Update


MIXOUTLVOL and MIXOUTRVOL volumes simultaneously.

MIXOUTRVOL (Right Mixer Output




MIXOUTLVOL (Right Mixer Output

PGA) Mute

0 = Mute

1 = Un-mute


128

Pre-Production w

WM8958

REGISTER

ADDRESS

DESCRIPTION

5:0 MIXOUTR_VOL [5:0] 39h

(0dB)

MIXOUTRVOL (Right Mixer Output

PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB


Table 69 Mixer Output PGA (MIXOUTLVOL, MIXOUTRVOL) Control

The headphone output PGA is configurable between two input sources. The default input to each headphone output PGA is the respective output mixer (MIXOUTL or MIXOUTR). A direct path from the DAC1L or DAC1R can be selected using the DAC1L_TO_HPOUT1L and DAC1R_TO_HPOUT1R register bits. When these bits are selected, a DAC to Headphone playback path is possible without using the output mixers; this offers reduced power consumption by allowing the output mixers to be disabled in this typical usage case.

The headphone output PGA controls are shown in Table 70. The HPOUT1_VU bits control the loading of the headphone PGA volume data. When HPOUT1_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The headphone PGA volume settings are both updated when a 1 is written to either HPOUT1_VU bit. This makes it possible to update the gain of both output paths simultaneously.


ADDRESS

R28 (001Ch)

Left Output

Volume

8 HPOUT1_VU N/A

R45 (002Dh)

Output Mixer

(1)

R29 (001Dh)

Right Output

Volume

7

6

5:0

8

8

HPOUT1L_ZC

HPOUT1L_MUTE_N

HPOUT1L_VOL [5:0]

DAC1L_TO_HPOUT1

L

HPOUT1_VU

0

1

2Dh

(-12dB)

0

N/A

Headphone Output PGA Volume

Update


HPOUT1LVOL and HPOUT1RVOL volumes simultaneously.

HPOUT1LVOL (Left Headphone

Output PGA) Zero Cross Enable




Output PGA) Mute

0 = Mute

1 = Un-mute


Output PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB



Output PGA) Input Select

0 = MIXOUTL

1 = DAC1L

Headphone Output PGA Volume

Update


HPOUT1LVOL and HPOUT1RVOL volumes simultaneously.


129

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

R46 (002Eh)

Output Mixer

(2)

7

6

5:0

8

HPOUT1R_ZC

HPOUT1R_MUTE_N

HPOUT1R_VOL [5:0]

DAC1R_TO_HPOUT1

R

0

1

2Dh

(-12dB)

0

HPOUT1RVOL (Right Headphone

Output PGA) Zero Cross Enable




Output PGA) Mute

0 = Mute

1 = Un-mute


Output PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB



Output PGA) Input Select

0 = MIXOUTR

1 = DAC1R

Table 70 Headphone Output PGA (HPOUT1LVOL, HPOUT1RVOL) Control w PP, August 2012, Rev 3.4

130

Pre-Production

WM8958

The speaker output PGA controls are shown in Table 71.The SPKOUT_VU bits control the loading of the speaker PGA volume data. When SPKOUT_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The speaker PGA volume settings are both updated when a 1 is written to either SPKOUT_VU bit. This makes it possible to update the gain of both output paths simultaneously.

REGISTER

ADDRESS

R38 (0026h)

Speaker

Volume Left

R39 (0027h)

Speaker

Volume Right

8

7

6

5:0

8

7

6

5:0

SPKOUT_VU

SPKOUTL_ZC

SPKOUTL_MUTE_N

SPKOUTL_VOL [5:0]

SPKOUT_VU

SPKOUTR_ZC

SPKOUTR_MUTE_N

SPKOUTR_VOL [5:0]

N/A

0

1

39h

(0dB)

N/A

0

1

39h

(0dB)

DESCRIPTION

Speaker Output PGA Volume

Update


SPKLVOL and SPKRVOL volumes simultaneously.

SPKLVOL (Left Speaker Output





PGA) Mute

0 = Mute

1 = Un-mute


PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB


Speaker PGA Volume Update


SPKLVOL and SPKRVOL volumes simultaneously.

SPKRVOL (Right Speaker Output





PGA) Mute

0 = Mute

1 = Un-mute


PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB


Table 71 Speaker Output PGA (SPKLVOL, SPKRVOL) Control w PP, August 2012, Rev 3.4

131

WM8958

Pre-Production

PGA GAIN SETTING VOLUME (dB) PGA GAIN SETTING VOLUME (dB)

00h -57 20h -25

01h -56 21h -24

02h -55 22h -23

03h -54 23h -22

04h -53 24h -21

05h -52 25h -20

06h -51 26h -19

07h -50 27h -18

08h -49 28h -17

09h -48 29h -16

0Ah -47 2Ah -15

0Bh -46 2Bh -14

0Ch -45 2Ch -13

0Dh -44 2Dh -12

0Eh -43 2Eh -11

0Fh -42 2Fh -10

10h -41 30h -9

11h -40 31h -8

12h -39 32h -7

13h -38 33h -6

14h -37 34h -5

15h -36 35h -4

16h -35 36h -3

17h -34 37h -2

18h -33 38h -1

19h -32 39h 0

1Ah -31 3Ah +1

1Bh -30 3Bh +2

1Ch -29 3Ch +3

1Dh -28 3Dh +4

1Eh -27 3Eh +5

1Fh -26 3Fh +6

Table 72 Output PGA Volume Range w PP, August 2012, Rev 3.4

132

Pre-Production

WM8958

SPEAKER BOOST MIXER

Each class D/AB speaker driver has its own boost mixer which performs a dual role. It allows the output from the left speaker mixer (via SPKLVOL), right speaker mixer (via SPKRVOL), or the ‘Direct

Voice’ path to be routed to either speaker driver. The speaker boost mixers are controlled using the registers defined in Table 73 below.

The ‘Direct Voice’ path is the differential input, VRXN-VRXP, routed directly to the output drivers, providing a low power differential path from baseband voice to loudspeakers. Note that a phase inversion exists between VRXP and SPKOUTxP. The ‘Direct Voice’ path output therefore represents

V

VRXN

- V

VRXP

.

The second function of the speaker boost mixers is that they provide an additional AC gain (boost) function to shift signal levels between the AVDD1 and SPKVDD voltage domains for maximum output power. The AC gain (boost) function is described in the “Analogue Outputs” section.

REGISTER

ADDRESS

R36 (0024h)

SPKOUT

Mixers

5

4

3

2

1

0

IN2LRP_TO_SPKOUT

L

SPKMIXL_TO_SPKOU

TL

SPKMIXR_TO_SPKO

UTL

IN2LRP_TO_SPKOUT

R

SPKMIXL_TO_SPKOU

TR

SPKMIXR_TO_SPKO

UTR

0

1

0

0

0

1

DESCRIPTION

Direct Voice (VRXN-VRXP) to Left

Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXL Left Speaker Mixer to

Left Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXR Right Speaker Mixer to

Left Speaker Mute

0 = Mute

1 = Un-mute

Direct Voice (VRXN-VRXP) to Right

Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXL Left Speaker Mixer to

Right Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXR Right Speaker Mixer to

Right Speaker Mute

0 = Mute

1 = Un-mute

Table 73 Speaker Boost Mixer (SPKOUTLBOOST, SPKOUTRBOOST) Control

EARPIECE DRIVER MIXER

The earpiece driver has a dedicated mixer, HPOUT2MIX, which is controlled using the registers defined in Table 74. The earpiece driver is configurable to select output from the left output mixer (via

MIXOUTLVOL), the right output mixer (via MIXOUTRVOL), or the ‘Direct Voice’ path.

The ‘Direct Voice’ path is the differential input, VRXN-VRXP, routed directly to the output drivers, providing a low power differential path from baseband voice to earpiece. Note that a phase inversion exists between VRXP and HPOUT2P. The ‘Direct Voice’ path output therefore represents V

VRXN

-

V

VRXP

.

Care should be taken to avoid clipping when enabling more than one path to the earpiece driver. The

HPOUT2VOL volume control can be used to avoid clipping when more than one full scale signal is input to the mixer. w PP, August 2012, Rev 3.4

133

WM8958 w

REGISTER

ADDRESS

R31 (001Fh)

HPOUT2

Volume

R51 (0033h)

HPOUT2

Mixer

Pre-Production


5

4

5

4

3

HPOUT2_MUTE

HPOUT2_VOL

IN2LRP_TO_HPOUT2

MIXOUTLVOL_TO_HP

OUT2

MIXOUTRVOL_TO_HP

OUT2

1

0

0

0

0

HPOUT2 (Earpiece Driver) Mute

0 = Un-mute

1 = Mute

HPOUT2 (Earpiece Driver) Volume

0 = 0dB

1 = -6dB

Direct Voice (VRXN-VRXP) to

Earpiece Driver

0 = Mute

1 = Un-mute

MIXOUTLVOL (Left Output Mixer

PGA) to Earpiece Driver

0 = Mute

1 = Un-mute

MIXOUTRVOL (Right Output Mixer

PGA) to Earpiece Driver

0 = Mute

1 = Un-mute

Table 74 Earpiece Driver Mixer (HPOUT2MIX) Control

LINE OUTPUT MIXERS

The WM8958 provides two pairs of line outputs, both with highly configurable output mixers. The outputs LINEOUT1N and LINEOUT1P can be configured as two single-ended outputs or as a differential output. In the same manner, LINEOUT2N and LINEOUT2P can be configured either as two single-ended outputs or as a differential output. The respective line output mixers can be configured in single-ended mode or differential mode; each mode supports multiple signal path configurations.

LINEOUT1 single-ended mode is selected by setting LINEOUT1_MODE = 1. In single-ended mode, any of three possible signal paths may be enabled:

 MIXOUTL (left output mixer) to LINEOUT1P

 MIXOUTR (right output mixer) to LINEOUT1N

 MIXOUTL (left output mixer) to LINEOUT1N

LINEOUT1 differential mode is selected by setting LINEOUT1_MODE = 0. In differential mode, any of three possible signal paths may be enabled:

 MIXOUTL (left output mixer) to LINEOUT1N and LINEOUT1P

 IN1L (input PGA) to LINEOUT1N and LINEOUT1P

 IN1R (input PGA) to LINEOUT1N and LINEOUT1P

The LINEOUT1 output mixers are controlled as described in Table 75. Care should be taken to avoid clipping when enabling more than one path to the line output mixers. The LINEOUT1_VOL control can be used to provide -6dB attenuation when more than one full scale signal is applied.

When using the LINEOUT1 mixers in single-ended mode, a buffered VMID must be enabled. This is achieved by setting LINEOUT_VMID_BUF_ENA, as described in the “Analogue Outputs” section.


134

Pre-Production

REGISTER

ADDRESS

R30 (001Eh)

Line Outputs

Volume

R52 (0034h)

Line Mixer (1)


6 LINEOUT1N_MUTE 1

5

4

6

5

4

2

1

0

LINEOUT1P_MUTE

LINEOUT1_VOL

MIXOUTL_TO_LINEO

UT1N

MIXOUTR_TO_LINE

OUT1N

LINEOUT1_MODE

IN1R_TO_LINEOUT1

P

IN1L_TO_LINEOUT1

P

MIXOUTL_TO_LINEO

UT1P

1

0

0

0

0

0

0

0

WM8958

DESCRIPTION

LINEOUT1N Line Output Mute

0 = Un-mute

1 = Mute

LINEOUT1P Line Output Mute

0 = Un-mute

1 = Mute

LINEOUT1 Line Output Volume

0 = 0dB

1 = -6dB

Applies to both LINEOUT1N and

LINEOUT1P

MIXOUTL to Single-Ended Line

Output on LINEOUT1N

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 1)

MIXOUTR to Single-Ended Line

Output on LINEOUT1N

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 1)

LINEOUT1 Mode Select

0 = Differential

1 = Single-Ended

IN1R Input PGA to Differential Line

Output on LINEOUT1

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 0)

IN1L Input PGA to Differential Line

Output on LINEOUT1

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 0)

Differential Mode

(LINEOUT1_MODE = 0):

MIXOUTL to Differential Output on

LINEOUT1

0 = Mute

1 = Un-mute

Single Ended Mode



Output on LINEOUT1P

0 = Mute

1 = Un-mute

Table 75 LINEOUT1N and LINEOUT1P Control w PP, August 2012, Rev 3.4

135

WM8958

Pre-Production

LINEOUT2 single-ended mode is selected by setting LINEOUT2_MODE = 1. In single-ended mode, any of three possible signal paths may be enabled:

 MIXOUTR (right output mixer) to LINEOUT2P

 MIXOUTL (left output mixer) to LINEOUT2N

 MIXOUTR (right output mixer) to LINEOUT2N

LINEOUT2 differential mode is selected by setting LINEOUT2_MODE = 0. In differential mode, any of three possible signal paths may be enabled:

 MIXOUTR (right output mixer) to LINEOUT2N and LINEOUT2P

 IN1L (input PGA) to LINEOUT2P and LINEOUT2P

 IN1R (input PGA) to LINEOUT2N and LINEOUT2P

The LINEOUT2 output mixers are controlled as described in Table 76. Care should be taken to avoid clipping when enabling more than one path to the line output mixers. The LINEOUT2_VOL control can be used to provide -6dB attenuation when more than one full scale signal is applied.

When using the LINEOUT2 mixers in single-ended mode, a buffered VMID must be enabled. This is achieved by setting LINEOUT_VMID_BUF_ENA, as described in the “Analogue Outputs” section. w PP, August 2012, Rev 3.4

136

Pre-Production

REGISTER

ADDRESS

R30 (001Eh)

Line Outputs

Volume


2 LINEOUT2N_MUTE 1

1 LINEOUT2P_MUTE 1

R53 (0035h)

Line Mixer (2)

0

6

5

4

2

1

0

LINEOUT2_VOL

MIXOUTR_TO_LINEO

UT2N

MIXOUTL_TO_LINEO

UT2N

LINEOUT2_MODE

IN1L_TO_LINEOUT2P

IN1R_TO_LINEOUT2P

MIXOUTR_TO_LINEO

UT2P

0

0

0

0

0

0

0

WM8958

DESCRIPTION


0 = Un-mute

1 = Mute


0 = Un-mute

1 = Mute


0 = 0dB

1 = -6dB

Applies to both LINEOUT2N and

LINEOUT2P


Output on LINEOUT2N

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 1)


Output on LINEOUT2N

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 1)


0 = Differential

1 = Single-Ended

IN1L Input PGA to Differential Line

Output on LINEOUT2

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 0)

IN1R Input PGA to Differential Line

Output on LINEOUT2

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 0)

Differential Mode


MIXOUTR to Differential Output on

LINEOUT2

0 = Mute

1 = Un-mute

Single-Ended Mode



Output on LINEOUT2P

0 = Mute

1 = Un-mute

Table 76 LINEOUT2N and LINEOUT2P Control w PP, August 2012, Rev 3.4

137

WM8958

CHARGE PUMP

Pre-Production

The WM8958 incorporates a dual-mode Charge Pump which generates the supply rails for the headphone output drivers, HPOUT1L and HPOUT1R.

The Charge Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and

CPVOUTN according to the selected mode of operation.

The Charge Pump connections are illustrated in Figure 31 (see “Applications Information” for external component values). An input decoupling capacitor may also be required at CPVDD, depending upon the system configuration.

CPCA CPCB

CPVDD

Charge Pump

CPVOUTP

CPVOUTN w

CPGND

Figure 31 Charge Pump External Connections





The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to optimise the power consumption according to the operating conditions. This can take two forms, which are selected using the CP_DYN_PWR register bit.

Register control (CP_DYN_PWR = 0)

Dynamic control (CP_DYN_PWR = 1)

Under Register control, the HPOUT1L_VOL and HPOUT1R_VOL register settings are used to control the charge pump mode of operation.

Under Dynamic control, the audio signal level in the digital audio interface is used to control the charge pump mode of operation. The CP_DYN_SRC_SEL register determines which of the digital signal paths is used for this function - this may be AIF1 Timeslot 0, AIF Timeslot 1 or AIF2. The

CP_DYN_SRC_SEL should be set according to the active source for the HPOUT1L and HPOUT1R outputs.

The Dynamic Charge Pump Control mode is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised in real time, but can only be used if a single AIF source is the only signal source. The Class W mode should not be used if any of the bypass paths are used to feed analogue inputs into the output signal path, or if more than one AIF source is used to feed the headphone output via the Digital Mixers.

Under the recommended usage conditions of the WM8958, the Charge Pump will be enabled by running the default headphone Start-Up sequence as described in the “Control Write Sequencer” section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.

Note that the charge pump clock is derived from internal clock SYSCLK; either MCLK or the FLL output selectable using the SYSCLK_SRC bit. Under normal circumstances an external clock signal must be present for the charge pump to function. However, the FLL has a free-running mode that does not require an external clock but will generate an internal clock suitable for running the charge pump. The clock division from SYSCLK is handled transparently by the WM8958 without user


138

Pre-Production

WM8958 intervention, as long as SYSCLK and sample rates are set correctly. Refer to the “Clocking and

Sample Rates” section for more detail on the FLL and clocking configuration.

When the Charge Pump is disabled, the output can be left floating or can be actively discharged, depending on the CP_DISCH control bit.

If the headphone output drivers (HPOUT1L and HPOUT1R) are not used, then the Charge Pump and the associated external components are not required. The Charge Pump and Headphone drivers should not be enabled in this case (CP_ENA=0, HPOUT1L_ENA=0, HPOUT1R_ENA=0).

If the Charge Pump is not used, and the associated external components are omitted, then the CPCA and CPCB pins can be left floating; the CPVOUTP and CPVOUTN pins should be grounded as illustrated in Figure 32.

Note that, when the Charge Pump is disabled, it is still recommended that the CPVDD pin is kept within its recommended operating conditions. w

Figure 32 External Configuration when Charge Pump not used

The Charge Pump control fields are described in Table 77.

REGISTER

ADDRESS

R76 (004Ch)

Charge Pump

(1)

R77 (004Dh)

Charge Pump

(2)

15

15

CP_ENA

CP_DISCH

0

1

R81 (0051h)

Class W (1)

9:8

0

CP_DYN_SRC_SEL

CP_DYN_PWR

00

0

Enable charge-pump digits

0 = Disable

1 = Enable

Charge Pump Discharge Select

0 = Charge Pump outputs floating when disabled

1 = Charge Pump outputs discharged when disabled

Selects the digital audio source for envelope tracking

00 = AIF1, DAC Timeslot 0


10 = AIF2, DAC data

11 = Reserved

Enable dynamic charge pump power control

0 = charge pump controlled by volume register settings (Class G)

1 = charge pump controlled by real-time audio level (Class W)

Table 77 Charge Pump Control


139

WM8958

DC SERVO w

Pre-Production

The WM8958 provides a DC servo circuit on the headphone outputs HPOUT1L and HPOUT1R in order to remove DC offset from these ground-referenced outputs. When enabled, the DC servo ensures that the DC level of these outputs remains within 1mV of ground. Removal of the DC offset is important because any deviation from GND at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption. Additionally, the presence of DC offsets can result in audible pops and clicks at power up and power down.

The recommended usage of the DC Servo is initialised by running the default Start-Up sequence as described in the “Control Write Sequencer” section. The default Start-Up sequence executes a series of DC offset corrections, after which the measured offset correction is maintained on the headphone output channels. If a different usage is required, eg. if a periodic DC offset correction is required, then the default Start-Up sequence may be modified according to specific requirements. The relevant control fields are described in the following paragraphs and are defined in Table 78.

DC SERVO ENABLE AND START-UP

The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and

DCS_ENA_CHAN_1 respectively. When the DC Servo is enabled, the DC offset correction can be commanded in a number of different ways, including single-shot and periodically recurring events.

Writing a logic 1 to DCS_TRIG_STARTUP_n initiates a series of DC offset measurements and applies the necessary correction to the associated output; (‘n’ = 0 for Left channel, 1 for Right channel). On completion, the headphone output will be within 1mV of AGND. This is the DC Servo mode selected by the default Start-Up sequence. Completion of the DC offset correction triggered in this way is indicated by the DCS_STARTUP_COMPLETE field, as described in Table 78. Typically, this operation takes 86ms per channel.

For correct operation of the DC Servo Start-Up mode, it is important that there is no active audio signal present on the signal path while the mode is running. The DC Servo Start-Up mode should be scheduled at the correct position within the Headphone Output Enable sequence, as described in the

“Analogue Output Signal Path” section. All other stages of the analogue signal path should be fully enabled prior to commanding the Start-Up mode; the DAC Digital Mute function should be used, where appropriate, to ensure there is no active audio signal present during the DC Servo measurements.

Writing a logic 1 to DCS_TRIG_DAC_WR_n causes the DC offset correction to be set to the value contained in the DCS_DAC_WR_VAL_n fields in Register R87. This mode is useful if the required offset correction has already been determined and stored; it is faster than the

DCS_TRIG_STARTUP_n mode, but relies on the accuracy of the stored settings. Completion of the

DC offset correction triggered in this way is indicated by the DCS_DAC_WR_COMPLETE field, as described in Table 78. Typically, this operation takes 2ms per channel.

For pop-free operation of the DC Servo DAC Write mode, it is important that the mode is scheduled at the correct position within the Headphone Output Enable sequence, as described in the “Analogue

Output Signal Path” section.

The current DC offset value for each Headphone output channel can be read from the

DCS_DAC_WR_VAL_n fields. These values may form the basis of settings that are subsequently used by the DC Servo in DAC Write mode. Note that these fields have a different definition for Read and Write, as described in Table 78.

When using either of the DC Servo options above, the status of the DC offset correction process is indicated by the DCS_CAL_COMPLETE field; this is the logical OR of the

DCS_STARTUP_COMPLETE and DCS_DAC_WR_COMPLETE fields.

The DCS_DAC_WR_COMPLETE bits can be used as inputs to the Interrupt control circuit or used to generate an external logic signal on a GPIO pin. See “Interrupts” and “General Purpose Input/Output” for further details.

The DC Servo control fields associated with start-up operation are described in Table 78. It is important to note that, to minimise audible pops/clicks, the Start-Up and DAC Write modes of DC

Servo operation should be commanded as part of a control sequence which includes muting and shorting of the headphone outputs; a suitable sequence is defined in the default Start-Up sequence.


140

Pre-Production w

REGISTER

ADDRESS

R84 (0054h)

DC Servo (1)

R87 (0057h)

DC Servo (4)

R88 (0058h)

DC Servo

Readback

5

4

3

2

15:8

7:0

9:8

DCS_TRIG_START

UP_1

DCS_TRIG_START

UP_0

DCS_TRIG_DAC_W

R_1

DCS_TRIG_DAC_W

R_0

1 DCS_ENA_CHAN_1

0 DCS_ENA_CHAN_0

DCS_DAC_WR_VA

L_1 [7:0]

DCS_DAC_WR_VA

L_0 [7:0]

DCS_CAL_COMPL

ETE [1:0]

WM8958

0

0

0

0

0

0

00h

00h

00

Writing 1 to this bit selects Start-

Up DC Servo mode for

HPOUT1R.

In readback, a value of 1 indicates that the DC Servo

Start-Up correction is in progress.

Writing 1 to this bit selects Start-

Up DC Servo mode for

HPOUT1L.



Writing 1 to this bit selects DAC

Write DC Servo mode for

HPOUT1R.

In readback, a value of 1 indicates that the DC Servo DAC

Write correction is in progress.

Writing 1 to this bit selects DAC

Write DC Servo mode for

HPOUT1L.



DC Servo enable for HPOUT1R

0 = Disabled

1 = Enabled

DC Servo enable for HPOUT1L

0 = Disabled

1 = Enabled

Writing to this field sets the DC

Offset value for HPOUT1R in

DAC Write DC Servo mode.

Reading this field gives the current DC Offset value for

HPOUT1R.

Two’s complement format.

LSB is 0.25mV.

Range is -32mV to +31.75mV

Writing to this field sets the DC

Offset value for HPOUT1L in

DAC Write DC Servo mode.


HPOUT1L.


LSB is 0.25mV.


DC Servo Complete status

0 = DAC Write or Start-Up DC

Servo mode not completed.

1 = DAC Write or Start-Up DC

Servo mode complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L


141

WM8958

Pre-Production

REGISTER

ADDRESS

5:4

1:0

DCS_DAC_WR_CO

MPLETE [1:0]

DCS_STARTUP_C

OMPLETE [1:0]

00

00

DC Servo DAC Write status

0 = DAC Write DC Servo mode not completed.

1 = DAC Write DC Servo mode complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

DC Servo Start-Up status

0 = Start-Up DC Servo mode not completed.

1 = Start-Up DC Servo mode complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

Table 78 DC Servo Enable and Start-Up Modes

DC SERVO ACTIVE MODES

The DC Servo modes described above are suitable for initialising the DC offset correction circuit on the Headphone outputs as part of a controlled start-up sequence which is executed before the signal path is fully enabled. Additional modes are available for use whilst the signal path is active; these modes may be of benefit following a large change in signal gain, which can lead to a change in DC offset level. Periodic updates may also be desirable to remove slow drifts in DC offset caused by changes in parameters such as device temperature.

The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and

DCS_ENA_CHAN_1 respectively, as described earlier in Table 78.

Writing a logic 1 to DCS_TRIG_SINGLE_n initiates a single DC offset measurement and adjustment to the associated output; (‘n’ = 0 for Left channel, 1 for Right channel). This will adjust the DC offset correction on the selected channel by no more than 1LSB (0.25mV).

Setting DCS_TIMER_PERIOD_01 to a non-zero value will cause a single DC offset measurement and adjustment to be scheduled on a periodic basis. Periodic rates ranging from every 0.52s to in excess of 2 hours can be selected.

Writing a logic 1 to DCS_TRIG_SERIES_n initiates a series of DC offset measurements and applies the necessary correction to the associated output. The number of DC Servo operations performed is determined by DCS_SERIES_NO_01. A maximum of 128 operations may be selected, though a much lower value will be sufficient in most applications.

The DC Servo control fields associated with active modes (suitable for use on a signal path that is in active use) are described in Table 79. w PP, August 2012, Rev 3.4

142

Pre-Production w

WM8958

REGISTER

ADDRESS

R84 (0054h)

DC Servo (1)

R85 (0055h)

DC Servo (2)

13

12

9

8

DCS_TRIG_SINGLE

_1

DCS_TRIG_SINGLE

_0

DCS_TRIG_SERIES

_1

DCS_TRIG_SERIES

_0

11:5 DCS_SERIES_NO_

01 [6:0]

3:0 DCS_TIMER_PERI

OD_01 [3:0]

0

0

0

0

Writing 1 to this bit selects a single DC offset correction for

HPOUT1R.

In readback, a value of 1 indicates that the DC Servo single correction is in progress.

Writing 1 to this bit selects a single DC offset correction for

HPOUT1L.


Writing 1 to this bit selects a series of DC offset corrections for HPOUT1R.



Writing 1 to this bit selects a series of DC offset corrections for HPOUT1L.



010 1010 Number of DC Servo updates to perform in a series event.

0 = 1 update

1 = 2 updates

...

127 = 128 updates

1010 Time between periodic updates.

Time is calculated as

0.251s x (2^PERIOD), where PERIOD =

DCS_TIMER_PERIOD_01.

0000 = Off

0001 = 0.502s

….

1010 = 257s (4min 17s)

1111 = 8225s (2hr 17min)

Table 79 DC Servo Active Modes

GPIO / INTERRUPT OUTPUTS FROM DC SERVO

When using the DC Servo Start-Up or DAC Write modes, the DCS_CAL_COMPLETE register provides readback of the status of the DC offset correction. This can be read from register R88 as described in Table 78.

The DCS_CAL_COMPLETE bits can also be used as inputs to the Interrupt control circuit and used to trigger an Interrupt event - see “Interrupts”.

The DCS_CAL_COMPLETE bits can also be used as inputs to the GPIO function and used to generate external logic signals indicating the DC Servo status. See “General Purpose Input/Output” for details of how to configure a GPIO pin to output the DC Servo status.


143

WM8958

Pre-Production

ANALOGUE OUTPUTS

The speaker, headphone, earpiece and line outputs are highly configurable and may be used in many different ways.

SPEAKER OUTPUT CONFIGURATIONS

The speaker outputs SPKOUTL and SPKOUTR can be driven by either of the speaker mixers,

SPKMIXL or SPKMIXR, or by the low power, differential Direct Voice path from IN2LP/VRXN and

IN2RP/VRXP. Fine volume control is available on the speaker mixer paths using the SPKLVOL and

SPKRVOL PGAs. A boost function is available on both the speaker mixer paths and the Direct Voice path. For information on the speaker mixing options, refer to the “Analogue Output Signal Path” section.

The speaker outputs SPKOUTL and SPKOUTR operate in a BTL configuration in Class AB or Class

D amplifier modes. The default mode is class D but class AB mode can be selected by setting the

SPKOUT_CLASSAB register bit, as defined in Table 81.

The speaker outputs can be configured as a pair of stereo outputs, or as a single mono output. Note that, for applications requiring only a single speaker output, it is possible to improve the THD performance by configuring the speaker outputs in mono mode. See “Typical Performance” for further details.

The mono configuration is selected by applying a logic high input to the SPKMODE pin (A4), as described in Table 80. For Stereo mode this pin should be connected to GND. Note that SPKMODE is referenced to DBVDD1.

An internal pull-up resistor is enabled by default on the SPKMODE pin; this can be configured using the SPKMODE_PU register bit described in Table 81.

SPEAKER CONFIGURATION

Stereo Mode

Mono Mode

Table 80 SPKMODE Pin Function

SPKMODE PIN (A4)

GND

DBVDD1

In the mono configuration, the P channels, SPKOUTLP and SPKOUTRP should be connected together on the PCB, and similarly with the N channels, SPKOUTLN and SPKOUTRN, as illustrated in Figure 33. In this configuration both left and right speaker drivers should be enabled

(SPKOUTL_ENA=1 and SPKOUTR_ENA=1), but path selection and volume controls are available on left channel only (SPKMIXL, SPKLVOL and SPKOUTLBOOST).

Note that the minimum speaker load resistance and the maximum power output has a dependency on the SPKMODE output configuration, and also on the Class D/AB mode selection. See “Electrical

Characteristics” for further details. w

Stereo Mono

Figure 33 Stereo / Mono Speaker Output Configurations


144

Pre-Production

WM8958

Eight levels of AC signal boost are provided in order to deliver maximum output power for many commonly-used SPKVDD/AVDD1 combinations. (Note that SPKVDD1 powers the Left Speaker driver, and SPKVDD2 powers the Right Speaker driver; it is assumed that SPKVDD1 = SPKVDD2 =

SPKVDD.)

The signal boost options are available in both Class AB and Class D modes. The AC boost levels from 0dB to +12dB are selected using register bits SPKOUTL_BOOST and SPKOUTR_BOOST. To prevent pop noise, SPKOUTL_BOOST and SPKOUTR_BOOST should not be modified while the speaker outputs are enabled. Figure 34 illustrates the speaker outputs and the mixing and gain/boost options available.

Ultra-low leakage and high PSRR allow the speaker supply SPKVDD to be directly connected to a lithium battery. Note that an appropriate SPKVDD supply voltage must be provided to prevent waveform clipping when speaker boost is used.

DC gain is applied automatically in both class AB and class D modes with a shift from VMID to

SPKVDD/2. This provides optimum signal swing for maximum output power. In class AB mode, an ultra-high PSRR mode is available, in which the DC reference for the speaker driver is fixed at VMID.

This mode is selected by enabling the SPKAB_REF_SEL bit (see Table 81). In this mode, the output power is limited but the driver will still be capable of driving more than 500mW in 8  while maintaining excellent suppression of noise on SPKVDD (for example, TDMA noise in a GSM phone application).

The AC and DC gain functions are illustrated in Figure 34. w

Figure 34 Speaker Output Configuration and AC Boost Operation


145

WM8958

REGISTER

ADDRESS

R35 (0023h)

SPKMIXR

Attenuation

R37 (0025h)

ClassD

R34 (0022h)

SPKMIXL

Attenuation

Pre-Production

8

5:3

2:0

8

SPKOUT_CLASSAB

SPKOUTL_BOOST

[2:0]

SPKOUTR_BOOST

[2:0]

SPKAB_REF_SEL

0

000

(1.0x)

000

(1.0x)

0

DESCRIPTION

Speaker Class AB Mode Enable

0 = Class D mode

1 = Class AB mode

Left Speaker Gain Boost

000 = 1.00x boost (+0dB)

001 = 1.19x boost (+1.5dB)

010 = 1.41x boost (+3.0dB)

011 = 1.68x boost (+4.5dB)

100 = 2.00x boost (+6.0dB)

101 = 2.37x boost (+7.5dB)

110 = 2.81x boost (+9.0dB)

111 = 3.98x boost (+12.0dB)

Right Speaker Gain Boost

000 = 1.00x boost (+0dB)

001 = 1.19x boost (+1.5dB)

010 = 1.41x boost (+3.0dB)

011 = 1.68x boost (+4.5dB)

100 = 2.00x boost (+6.0dB)

101 = 2.37x boost (+7.5dB)

110 = 2.81x boost (+9.0dB)

111 = 3.98x boost (+12.0dB)

Selects Reference for Speaker in

Class AB mode

0 = SPKVDD/2

1 = VMID

SPKMODE Pull-up enable

0 = Disabled

1 = Enabled

R1825

(0721h)

Pull Control

(2)

1 SPKMODE_PU

Table 81 Speaker Mode and Boost Control

1

Clocking of the Class D output driver is derived from SYSCLK. The clocking frequency division is configured automatically, according to the AIFn_SR and AIFnCLK_RATE registers. (See “Clocking and Sample Rates” for further details of the system clocks and control registers.)

The Class D switching clock is enabled whenever SPKOUTL_ENA or SPKOUTR_ENA is set, provided also that SPKOUT_CLASSAB = 0. The frequency is as described in Table 82.

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the Class D clock frequency is controlled by the AIF1_SR and AIF1CLK_RATE registers.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the Class D clock frequency is controlled by the AIF2_SR and AIF2CLK_RATE registers.

Note that the applicable clocks (SYSCLK, AIF1CLK or AIF2CLK) must be present and enabled when using the speaker outputs in Class D mode. w PP, August 2012, Rev 3.4

146

Pre-Production

WM8958

SAMPLE

RATE (kHz)

8

11.025

12

16

22.05

24

32

44.1

48

88.2

96


128 192 256 384 512 768 1024 1536

256 256 341.3 256 341.3 256 341.3 256

352.8 352.8 352.8 352.8 352.8 352.8 352.8

384 384 384 384 384 384 384

341.3 384 341.3 384 341.3 384

352.8 352.8 352.8 352.8 352.8

384 384 384 384 384

341.3 384 341.3 384

352.8 352.8 352.8

384 384 384

352.8

384

Table 82 Class D Switching Frequency (kHz)

HEADPHONE OUTPUT CONFIGURATIONS

The headphone outputs HPOUT1L and HPOUT1R are driven by the headphone output PGAs

HPOUT1LVOL and HPOUT1RVOL. Each PGA has its own dedicated volume control, as described in the “Analogue Output Signal Path” section. The input to these PGAs can be either the output mixers

MIXOUTL and MIXOUTR or the direct DAC1 outputs DAC1L and DAC1R.

The headphone output driver is capable of driving up to 30mW into a 16Ω load or 25mW into a 32Ω load such as a stereo headset or headphones. The outputs are ground-referenced, eliminating any requirement for AC coupling capacitors. This is achieved by having separate positive and negative supply rails powered by an on-chip charge pump. A DC Servo circuit removes any DC offset from the headphone outputs, suppressing ‘pop’ noise and minimising power consumption. The Charge Pump and DC Servo are described separately (see “Charge Pump” and “DC Servo” respectively).

It is recommended to connect a zobel network to the headphone output pins HPOUT1L and

HPOUT1R for best audio performance in all applications. The components of the zobel network have the effect of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions. Possible sources of these instabilities include the inductive load of a headphone coil or an active load in the form of an external line amplifier. The capacitance of lengthy cables or PCB tracks can also lead to amplifier instability. The zobel network should comprise of a

20  resistor and 100nF capacitor in series with each other, as illustrated in Figure 35.

If any ground-referenced headphone output is not used, then the zobel network components can be omitted from the corresponding output pin, and the pin can be left floating. The respective headphone driver(s) should not be enabled in this case. w

Figure 35 Zobel Network Components for HPOUT1L and HPOUT1R


147

WM8958 w

Pre-Production

The headphone output incorporates a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. The return path is via HPOUT1FB. This pin must be connected to ground for normal operation of the headphone output. No register configuration is required.

Note that the HPOUT1FB pin should be connected to GND close to the headphone jack, as illustrated in Figure 35.

EARPIECE DRIVER OUTPUT CONFIGURATIONS

The earpiece driver outputs HPOUT2P and HPOUT2N are driven by the HPOUT2MIX output mixer, which can take inputs from the mixer output PGAs MIXOUTLVOL and MIXOUTRVOL, or from the low power, differential Direct Voice path IN2LP/VRXN and IN2RP/VRXP. Fine volume control is available on the output mixer paths using MIXOUTLVOL and MIXOUTRVOL. A selectable -6dB attenuation is available on the HPOUT2MIX output, as described in Table 74 (refer to the “Analogue Output Signal

Path” section).

The earpiece outputs are designed to operate in a BTL configuration, driving 50mW into a typical 16  ear speaker.

For suppression of pop noise there are two separate enables for the earpiece driver; HPOUT2_ENA enables the output stage and HPOUT2_IN_ENA enables the mixer and input stage.

HPOUT2_IN_ENA should be enabled a minimum of 50 s before HPOUT2_ENA – see “Control Write

Sequencer” section for an example power sequence.

LINE OUTPUT CONFIGURATIONS

The four line outputs LINEOUT1P, LINEOUT1N, LINEOUT2P and LINEOUT2N provide a highly flexible combination of differential and single-ended configurations, each driven by a dedicated output mixer. There is a selectable -6dB gain option in each mixer to avoid clipping when mixing more than one signal into a line output. Additional volume control is available at other locations within each of the supported signal paths. For more information about the line output mixing options, refer to the

“Analogue Output Signal Path” section.

Typical applications for the line outputs (single-ended or differential) are:

 Handset or headset microphone output to external voice CODEC

 Stereo line output

 Output to external speaker driver(s) to support additional loudspeakers

When single-ended mode is selected for either LINEOUT1 or LINEOUT2, a buffered VMID must be enabled as a reference for the outputs. This is enabled by setting the LINEOUT_VMID_BUF_ENA bit as defined in Table 83.


ADDRESS

R56 (0038h)

AntiPOP (1)

7 LINEOUT_VMID_BUF_E

NA

0 Enables VMID reference for line outputs in single-ended mode

0 = Disabled

1 = Enabled

Table 83 LINEOUT VMID Buffer for Single-Ended Operation

Some example line output configurations are listed and illustrated below.

 Differential line output from Mic/Line input on IN1L PGA

 Differential line output from Mic/Line input on IN1R PGA

 Stereo differential line output from output mixers MIXOUTL and MIXOUTR

 Stereo single-ended line output from output mixer to either LINEOUT1 or LINEOUT2

 Mono single-ended line output from output mixer


148

Pre-Production

WM8958

IN1L

IN1R

LINEOUT1NMIX

MIXOUTLVOL

MIXOUTRVOL

IN1R

IN1L

+

0dB or -6dB

LINEOUT1PMIX

MIXOUTLVOL

IN1L

IN1R

+

0dB or -6dB

Ground Loop

Noise Rejection

Ground Loop

Noise Rejection

LINEOUT1N

LINEOUT1P

Min = -57dB

Max = +6dB

Step = 1dB

MIXOUTLVOL

Min = -57dB

Max = +6dB

Step = 1dB

MIXOUTRVOL

LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0


LINEOUT1_MODE=0

LINEOUT2_MODE=0

IN1L_TO_LINEOUT1P=1

IN1R_TO_LINEOUT2P=1

Figure 36 Differential Line Out from input PGA

IN1L (to LINEOUT1) and IN1R (to LINEOUT2)

IN1L

IN1R

LINEOUT2NMIX

MIXOUTLVOL

MIXOUTRVOL

IN1R

+

IN1L

0dB or -6dB

LINEOUT2PMIX

MIXOUTRVOL

IN1L

IN1R

+

0dB or -6dB

Ground Loop

Noise Rejection

LINEOUT2N

LINEOUT2P

Ground Loop

Noise Rejection



LINEOUT1_MODE=0

LINEOUT2_MODE=0

IN1R_TO_LINEOUT1P=1

IN1L_TO_LINEOUT2P=1

Figure 37 Differential Line Out from input PGA

IN1R (to LINEOUT1) and IN1L (to LINEOUT2)

IN1L

IN1R

LINEOUT1NMIX

MIXOUTLVOL

MIXOUTRVOL

IN1R

+

IN1L

0dB or -6dB

LINEOUT1PMIX

MIXOUTLVOL

IN1L

IN1R

+

0dB or -6dB

Ground Loop

Noise Rejection

Ground Loop

Noise Rejection

LINEOUT1N

LINEOUT1P

Min = -57dB

Max = +6dB

Step = 1dB

MIXOUTLVOL

Min = -57dB

Max = +6dB

Step = 1dB

MIXOUTRVOL

IN1L

IN1R

LINEOUT2NMIX

MIXOUTLVOL

MIXOUTRVOL

IN1R

IN1L

+

0dB or -6dB

LINEOUT2PMIX

MIXOUTRVOL

IN1L

IN1R

+

0dB or -6dB

Ground Loop

Noise Rejection

Ground Loop

Noise Rejection



LINEOUT1_MODE=1

MIXOUTL_TO_LINEOUT1P=1

MIXOUTR_TO_LINEOUT1N=1

LINEOUT_VMID_BUF_ENA=1

LINEOUT2N

LINEOUT2P



LINEOUT1_MODE=0

LINEOUT2_MODE=0


MIXOUTR_TO_LINEOUT2P=1

Figure 38 Stereo Differential Line Out from

MIXOUTL and MIXOUTR

Figure 39 Stereo Single-Ended Line Out from

MIXOUTL and MIXOUTR to LINEOUT1 w PP, August 2012, Rev 3.4

149

WM8958

Pre-Production



LINEOUT1_MODE=1

MIXOUTL_TO_LINEOUT2N=1





LINEOUT1_MODE=1

LINEOUT2_MODE=1

MIXOUTL_TO_LINEOUT1N=1 and/or


MIXOUTR_TO_LINEOUT2N=1 and/or



Figure 40 Stereo Single-Ended Line Out from

MIXOUTL and MIXOUTR to LINEOUT2

Figure 41 Mono Line Out to LINEOUT1N,

LINEOUT1P, LINEOUT2N, LINEOUT2P

The line outputs incorporate a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. The return path, via LINEOUTFB, is enabled separately for

LINEOUT1 and LINEOUT2 using the LINEOUT1_FB and LINEOUT2_FB bits as defined in Table 84.

Ground loop feedback is a benefit to single-ended line outputs only; it is not applicable to differential outputs, which already inherently offer common mode noise rejection.


ADDRESS

R55 (0037h)

Additional

Control

7

6

LINEOUT1_FB

LINEOUT2_FB

0

0

Enable ground loop noise feedback on LINEOUT1

0 = Disabled

1 = Enabled

Enable ground loop noise feedback on LINEOUT2

0 = Disabled

1 = Enabled

Table 84 Line Output Ground Loop Feedback Enable w PP, August 2012, Rev 3.4

150

Pre-Production

WM8958

EXTERNAL ACCESSORY DETECTION

The WM8958 accessory detection circuit measures the impedance of an external load connected to the MICDET pin. This feature can be used to detect the insertion or removal of a microphone, and the status of the associated hookswitch. It can also be used to detect push-button status or the connection of other external accessories.

The microphone detection circuit measures the impedance connected to MICDET, and reports whether the measured impedance lies within one of 9 pre-defined levels (including the ‘no accessory detected’ level). This means it can detect the presence of a typical microphone and up to 7 pushbuttons. One of the impedance levels is specifically designed to detect a video accessory (typical

75Ω) load if required.

The microphone detection circuit uses the MICBIAS2 output as a reference. The WM8958 will automatically enable MICBIAS2 when required in order to perform the detection function; this allows the detection function to be supported in low-power standby operating conditions.

Microphone detection is enabled by setting the MICD_ENA register. When microphone detection is enabled, the WM8958 performs a number of measurements in order to determine the MICDET impedance. The measurement process is repeated at a cyclic rate controlled by MICD_RATE. (The

MICD_RATE register selects the delay between completion of one measurement and the start of the next.)

For best accuracy, the measured impedance is only deemed valid after more than one successive measurement has produced the same result. The MICD_DBTIME register provides control of the debounce period; this can be either 2 measurements or 4 measurements.

When the microphone detection result has settled (ie. after the applicable de-bounce period), the

WM8958 indicates valid data by setting the MICD_VALID bit. The measured impedance is indicated using the MICD_LVL and MICD_STS register bits, as described in Table 85.

The MICD_VALID bit, when set, remains asserted for as long as the microphone detection function is enabled (ie. while MICD_ENA = 1). If the detected impedance changes, then the MICD_LVL and

MICD_STS fields will change, but the MICD_VALID bit will remain set, indicating valid data at all times.

Note that the impedance levels quoted in the MICD_LVL description assume that a microphone

(475Ω to 30kΩ impedance) is also present on the MICDET pin. The limits quoted in the “Electrical

Characteristics” refer to the combined effective impedance on the MICDET pin. Typical external components are described in the “Applications Information” section.

The microphone detection reports a measurement result in one of the pre-defined impedance levels.

Each measurement level can be enabled or disabled independently; this provides flexibility according to the required thresholds, and offers a faster measurement time in some applications. The

MICD_LVL_SEL register is described in detail later in this section.

Clocking for the microphone detection function is derived from SYSCLK (defined in the “Clocking and

Sample Rates” section).

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then AIF1CLK must be present and enabled when using the accessory detect function. The AIF1_SR and AIF1CLK_RATE registers must be set to values that are consistent with the available AIF1CLK frequency.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then AIF2CLK must be present and enabled when using the accessory detect function. The AIF2_SR and AIF2CLK_RATE registers must be set to values that are consistent with the available AIF2CLK frequency.

The Frequency Locked Loop (FLL) free-running mode provides flexibility to clock the microphone detection function without any external reference clock, eg. in low-power standby operating conditions. See “Clocking and Sample Rates” for details of the WM8958 clocking options and FLL.

The accessory detection function can also be supported using a low frequency (eg. 32kHz) clock, as described later in this section, see “Accessory Detection with Low Frequency SYSCLK”.

The microphone detection function is an input to the Interrupt control circuit and can be used to trigger an Interrupt event every time an accessory insertion, removal or impedance change is detected. See

“Interrupts” for further details. w PP, August 2012, Rev 3.4

151

WM8958

Pre-Production

The microphone detection function can also generate a GPIO output, providing an external indication of the microphone detection. This GPIO output is pulsed every time an accessory insertion, removal or impedance change is detected. See “General Purpose Input/Output” for details of how to configure a GPIO pin to output the microphone detection signal.

The register fields associated with Microphone Detection (or other accessories) are described in

Table 85. The external circuit configuration is illustrated in Figure 42.


ADDRESS

R208

(00D0h)

Mic Detect 1

15:12

11:8

1

0

MICD_BIAS_STARTTI

ME [3:0]

MICD_RATE [3:0]

MICD_DBTIME

MICD_ENA

0101

0110

0

0

Mic Detect Bias Startup Delay

(If MICBIAS2 is not enabled already, this field selects the delay time allowed for MICBIAS2 to startup prior to performing the MICDET function.)

0000 = 0ms (continuous)

0001 = 0.25ms

0010 = 0.5ms

0011 = 1ms

0100 = 2ms

0101 = 4ms

0110 = 8ms

0111 = 16ms

1000 = 32ms

1001 = 64ms

1010 = 128ms

1011 = 256ms

1100 to 1111 = 512ms

Mic Detect Rate

(Selects the delay between successive Mic Detect measurements.)


0001 = 0.25ms

0010 = 0.5ms

0011 = 1ms

0100 = 2ms

0101 = 4ms

0110 = 8ms

0111 = 16ms

1000 = 32ms

1001 = 64ms

1010 = 128ms

1011 = 256ms

1100 to 1111 = 512ms

Mic Detect De-bounce

0 = 2 measurements

1 = 4 measurements

Mic Detect Enable

0 = Disabled


152

Pre-Production w

WM8958

REGISTER

ADDRESS

R209

(00D1h)

Mic Detect 2

R210

(00D2h)

Mic Detect 3

7:0

10:2

1

0

MICD_LVL_SEL [7:0]

MICD_LVL [8:0]

MICD_VALID

MICD_STS

DESCRIPTION

0111_

1111

0_0000_

0000

0

0

Mic Detect Level Select

(enables Mic Detection in specific impedance ranges)

[7] = Not used - must be set to 0

[6] = Enable >475 ohm detection

[5] = Enable 326 ohm detection



[2] = Enable 47.6 ohm detection



Note that the impedance values quoted assume that a microphone

(475ohm-30kohm) is also present on the MICDET pin.

Mic Detect Level

(indicates the measured impedance)

[8] = Not used

[7] = >475 ohm, <30k ohm

[6] = 326 ohm

[5] = 152 ohm

[4] = 77 ohm

[3] = 47.6 ohm

[2] = 29.4 ohm

[1] = 14 ohm

[0] = <3 ohm

Note that the impedance values quoted assume that a microphone

(475ohm-30kohm) is also present on the MICDET pin.

Mic Detect Data Valid

0 = Not Valid

1 = Valid

Mic Detect Status

0 = No Mic Accessory present

(impedance is >30k ohm)

1 = Mic Accessory is present

(impedance is <30k ohm)

Table 85 Microphone Detect Control

The external connections for the Microphone Detect circuit are illustrated in Figure 42. In typical applications, it can be used to detect a microphone or button press.

The microphone detection function uses MICBIAS2 as a reference. The microphone detection function will automatically enable MICBIAS2 when required for MICDET impedance measurement.

If MICBIAS2 is not already enabled (ie. if MICB2_ENA = 0), then MICBIAS2 will be enabled for short periods of time only, every time the impedance measurement is scheduled. To allow time for the

MICBIAS2 source to start-up, a time delay is applied before the measurement is performed; this is configured using the MICD_BIAS_STARTTIME register, as described in Table 85.

The MICD_BIAS_STARTTIME register should be set to 16ms or more if MICB2_RATE = 1 (pop-free start-up / shut-down). The MICD_BIAS_STARTTIME register should be set to 0.25ms or more if

MICB2_RATE = 0 (fast start-up / shut-down).

If the MICBIAS2 reference is not enabled continuously (ie. if MICB2_ENA = 0), then the MICBIAS2 discharge bit (MICB2_DISCH) should be set to 0.


153

WM8958

Pre-Production

The MICBIAS sources are configured using the registers described in Table 1, in the “Analogue Input

Signal Path” section. w

Figure 42 Microphone Detect Interface

The MICD_LVL_SEL [7:0] register bits allow each of the impedance measurement levels to be enabled or disabled independently. This allows the function to be tailored to the particular application requirements.

If one or more bits within the MICD_LVL_SEL register is set to 0, then the corresponding impedance level will be disabled. Any measured impedance which lies in a disabled level will be reported as the next lowest, enabled level.

For example, the MICD_LVL_SEL [3] bit enables the detection of impedances around 77 . If

MICD_LVL_SEL [3] = 0, then an external impedance of 77  will not be indicated as 77 but will be indicated as 47 ; this would be reported in the MICD_LVL register as MICD_LVL [3] = 1.

With all measurement levels enabled, the WM8958 can detect the presence of a typical microphone and up to 7 push-buttons. The microphone detect function is specifically designed to detect a video accessory (typical 75 ) load if required.

See “Applications Information” for typical recommended external components for microphone, video or push-button accessory detection.

The microphone detection circuit assumes that a 2.2k

 (2%) resistor is connected to MICBIAS2, as illustrated. Different resistor values will lead to inaccuracy in the impedance measurement.

The measurement accuracy of the microphone detect function is assured whenever the connected load is within the applicable limits specified in the “Electrical Characteristics”. Note that a 2.2k

 (2%) resistor must also be connected between MICDET and MICBIAS2.

Note that the connection of a microphone will change the measured impedance on the MICDET pin; see “Applications Information” for recommended components for typical applications.

The measurement time varies between 100 s and 500s according to the impedance of the external load. A high impedance will be measured faster than a low impedance.


154

Pre-Production

WM8958

The timing of the microphone detect function is illustrated in Figure 43. Two different cases are shown, according to whether MICBIAS2 is enabled periodically by the impedance measurement function (MICB2_ENA=0), or is enabled at all times (MICB2_ENA=1).

Figure 43 Microphone Detect Timing

ACCESSORY DETECTION WITH LOW FREQUENCY SYSCLK

Clocking for the microphone detection function can be derived from AIF1CLK or AIF2CLK, as described earlier.

Under normal circumstances, the AIFn_SR and AIFnCLK_RATE registers must be set to values that are consistent with the available AIFnCLK frequency. The register settings support AIFnCLK frequencies of 1.024MHz or higher.

The microphone detection function can also be supported using a low frequency (eg. 32kHz) clock. In this case, the selected SYSCLK source (AIF1CLK or AIF2CLK) should be configured with the following register settings:

 AIFnCLK_RATE = 0001 (AIFnCLK / fs = 128)

 AIFn_SR = 0000 (fs = 8kHz).

The register settings above configure the WM8958 for AIFnCLK = 1.024MHz. If the available clock is a different frequency (eg. 32kHz), then the timings set by the MICD_RATE and

MICD_BIAS_STARTUP registers will be scaled accordingly. In the case of a 32kHz clock, these times will be extended by a factor of 32 (calculated as 1024000 / 32000).

For example, under normal circumstances, setting MICD_RATE = 0011 selects a 1ms delay between successive measurements. Using a 32kHz reference clock, and the register settings above, then

MICD_RATE = 0011 will select a 32ms delay. w PP, August 2012, Rev 3.4

155

WM8958

Pre-Production

GENERAL PURPOSE INPUT/OUTPUT

The WM8958 provides a number of GPIO functions to enable interfacing and detection of external hardware and to provide logic outputs to other devices. The input functions can be polled directly or can be used to generate an Interrupt (IRQ) event. The GPIO and Interrupt circuits support the following functions:

 Alternate interface functions (AIF2, AIF3)

 Button detect (GPIO input)

 Logic ‘1’ and logic ‘0’ output (GPIO output)

 Interrupt (IRQ) status output

 Over-Temperature

 Microphone accessory status detection

 Frequency Locked Loop (FLL) Lock status output

 Sample Rate Conversion (SRC) Lock status output

 Dynamic Range Control (DRC) Signal activity detection

 Control Write Sequencer status output

 Digital Core FIFO error status output

 Clock output (SYSCLK divided by OPCLK_DIV)

 Frequency Locked Loop (FLL) Clock output

GPIO CONTROL

For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1, 6, 8, 9, 10, 11). The pin direction, set by GPn_DIR, must be set according to function selected by GPn_FN.

The alternate audio interfaces AIF2 and AIF3 are both supported using GPIO pins; the applicable pin functions are selected by setting the corresponding GPn_FN register to 00h. See Table 87 for the definition of which AIF function is available on each GPIO pin.

See “Digital Audio Interface Control” for details of AIF2 and AIF3.

When a pin is configured as a GPIO input (GPn_DIR = 1), the logic level at the pin can be read from the respective GPn_LVL bit. Note that GPn_LVL is not affected by the GPn_POL bit.

A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin by setting the respective GPn_DB bit.

When a pin is configured as a Logic Level output (GPn_DIR = 0, GPn_FN = 01h), its level can be set to logic 0 or logic 1 using the GPn_LVL field.

When a pin is configured as an output (GPn_DIR = 0), the polarity can be inverted using the

GPn_POL bit. When GPn_POL = 1, then the selected output function is inverted. In the case of Logic

Level output (GPn_FN = 01h), the external output will be the opposite logic level to GPn_LVL when

GPn_POL = 1.

A GPIO output can be either CMOS driven or Open Drain. This is selected on each pin using the respective GPn_OP_CFG bit.

Internal pull-up and pull-down resistors may be enabled using the GPn_PU and GPn_PD fields; this allows greater flexibility to interface with different signals from other devices. (Note that if GPn_PU and GPn_PD are both set for any GPIO pin, then the pull-up and pull-down will be disabled.)

Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt event. An interrupt event is triggered on the rising and falling edge of the GPIO input. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See

“Interrupts” for more details of the Interrupt event handling. w PP, August 2012, Rev 3.4

156

Pre-Production w

WM8958

The register fields that control the GPIO pins are described in Table 86.

REGISTER

ADDRESS

R1792

(0700h)

GPIO 1

R1797

(0705h)

GPIO 6

R1799

(0707h)

GPIO 8 to

R1802

(070Ah)

GPIO 11

15

14

13

10

GPn_DIR

GPn_PU

GPn_PD

GPn_POL

1

0

1

0

DESCRIPTION

GPIOn Pin Direction

0 = Output

1 = Input

GPIOn Pull-Up Enable

0 = Disabled

1 = Enabled

GPIOn Pull-Down Enable

0 = Disabled

1 = Enabled

GPIOn Polarity Select

0 = Non-inverted (Active High)

1 = Inverted (Active Low)

9

8

6

GPn_OP_CFG

GPn_DB

GPn_LVL

0

1

0

GPIOn Output Configuration

0 = CMOS

1 = Open Drain

GPIOn Input De-bounce

0 = Disabled

1 = Enabled

GPIOn level. Write to this bit to set a GPIO output. Read from this bit to read GPIO input level.

For output functions only, when

GPn_POL is set, the register contains the opposite logic level to the external pin.

4:0 GPn_FN [4:0] GPIOn Pin Function

(see Table 87 for details)

GP1_FN default = 0000






Note: n is a number (1, 6, 8, 9, 10, 11) that identifies the individual GPIO.

Table 86 GPIO1, GPIO6, GPIO8, GPIO9, GPIO10 to GPIO11 Control

GPIO FUNCTION SELECT

The available GPIO functions are described in Table 87. The function of each GPIO is set using the

GPn_FN register, where n identifies the GPIO pin (1, 6, 8, 9, 10, 11). Note that the respective

GPn_DIR must also be set according to whether the function is an input or output.

GPn_FN DESCRIPTION

00h GPIO1 - ADCLRCLK1

GPIO6 - ADCLRCLK2

GPIO8 - DACDAT3

GPIO9 - ADCDAT3

GPIO10 - LRCLK3

GPIO11 - BCLK3

COMMENTS

Alternate Audio Interface connections.

01h

02h

Button detect input /

Logic level output

GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL.

GPn_DIR = 1: Button detect or logic level input.

Reserved


157

WM8958 w

Pre-Production

GPn_FN DESCRIPTION

03h IRQ Interrupt (IRQ) output

0 = IRQ not asserted

1 = IRQ asserted

04h Temperature

(Shutdown) status output

COMMENTS

Indicates Temperature Shutdown Sensor status

0 = Temperature is below shutdown level

1 = Temperature is above shutdown level

05h

06h

07h

08h

09h

Microphone Detect Microphone Detect (MICDET accessory) IRQ output

A single 31 s pulse is output whenever an accessory insertion, removal or impedance change is detected.

Reserved

Reserved

0Ah

0Bh

Reserved

FLL1 Lock Indicates FLL1 Lock status

0 = Not locked

1 = Locked

FLL2 Lock

SRC1 Lock

Indicates FLL2 Lock status

0 = Not locked

1 = Locked

Indicates SRC1 Lock status

0 = Not locked

1 = Locked

0Ch

0Dh

0Eh

0Fh

SRC2 Lock

AIF1 DRC1 Signal

Detect

AIF1 DRC2 Signal

Detect

AIF2 DRC Signal

Detect

Indicates SRC2 Lock status

0 = Not locked

1 = Locked

Indicates AIF1 DRC1 Signal Detect status

0 = Signal threshold not exceeded

1 = Signal threshold exceeded

Indicates AIF1 DRC2 Signal Detect status



Indicates AIF2 DRC Signal Detect status



10h

11h

12h

13h

14h

Write Sequencer

Status

FIFO Error

Clock Output OPCLK

Temperature (Warning) status output

DC Servo Done

Indicates Write Sequencer status

0 = Write Sequencer Idle

1 = Write Sequence Busy

Indicates a Digital Core FIFO Error condition

0 = Normal operation

1 = FIFO Error

GPIO Clock derived from SYSCLK

Indicates Temperature Warning Sensor status

0 = Temperature is below warning level

1 = Temperature is above warning level

Indicates DC Servo status on HPOUT1L and HPOUT1R

0 = DC Servo not complete

1 = DC Servo complete

15h

16h

FLL1 Clock Output

FLL2 Clock Output

Clock output from FLL1

Clock output from FLL2

17h to 1Fh Reserved

Table 87 GPIO Function Select


158

Pre-Production

WM8958

BUTTON DETECT (GPIO INPUT)

Button detect functionality can be selected on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The same functionality can be used to support a Jack Detect input function.

It is recommended to enable the GPIO input de-bounce feature when using GPIOs as button input or

Jack Detect input.

The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable de-bounce controls. Note that GPn_LVL is not affected by the GPn_POL bit.

The de-bounced GPIO signals are also inputs to the Interrupt control circuit. An interrupt event is triggered on the rising and falling edge of the GPIO input. The associated interrupt bits are latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)

The WM8958 can be programmed to drive a logic high or logic low level on any GPIO pin by selecting the “GPIO Output” function as described in “GPIO Control”. The output logic level is selected using the respective GPn_LVL bit.

Note that the polarity of the GPIO output can be inverted using the GPn_POL registers. If GPn_POL =

1, then the external output will be the opposite logic level to GPn_LVL.

INTERRUPT (IRQ) STATUS OUTPUT

The WM8958 has an Interrupt Controller which can be used to indicate when any selected Interrupt events occur. An interrupt can be generated by any of the events described throughout the GPIO function definition above. Individual interrupts may be masked in order to configure the Interrupt as required. See “Interrupts” for further details.

The Interrupt (IRQ) status may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”.

OVER-TEMPERATURE DETECTION

The WM8958 incorporates a temperature sensor which detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition.

The Temperature status may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. Any GPIO pin can be used to indicate either a Warning

Temperature event or the Shutdown Temperature event. De-bounce can be applied to the applicable signal using the register bits described in Table 88.

The Warning Temperature and Shutdown Temperature status are inputs to the Interrupt control circuit, after the selectable de-bounce. An interrupt event may be triggered on the rising and falling edges of these signals. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

Note that the temperature sensor can be configured to automatically disable the audio outputs of the

WM8958 (see “Thermal Shutdown”). In some applications, it may be preferable to manage the temperature sensor event through GPIO or Interrupt functions, allowing a host processor to implement a controlled system response to an over-temperature condition.

The temperature sensor must be enabled by setting the TSHUT_ENA register bit. When the

TSHUT_OPDIS is also set, then a device over-temperature condition will cause the speaker outputs

(SPKOUTL and SPKOUTR) of the WM8958 to be disabled. w PP, August 2012, Rev 3.4

159

WM8958

Pre-Production

REGISTER

ADDRESS

R2 (0002h)

Power

Management

(2)

R1864

(0748h)

IRQ

Debounce


14

13

0

0

TSHUT_EN

A

TSHUT_OP

DIS

TEMP_WAR

N_DB

TEMP_SHU

T_DB

1

1

0

0

DESCRIPTION

Thermal sensor enable

0 = Disabled

1 = Enabled

Thermal shutdown control

(Causes audio outputs to be disabled if an overtemperature occurs. The thermal sensor must also be enabled.)

0 = Disabled

1 = Enabled

Thermal Warning de-bounce

0 = Disabled

1 = Enabled

Thermal shutdown de-bounce

0 = Disabled

1 = Enabled

Table 88 Temperature Sensor Enable and GPIO/Interrupt Control

MICROPHONE ACCESSORY STATUS DETECTION

The WM8958 provides an impedance measurement circuit on the MICDET pin to detect the connection of a microphone or other external accessory. See “External Accessory Detection” for further details.

A logic signal from the microphone detect circuit may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a single pulse duration of 31 s whenever an accessory insertion, removal or impedance change is detected.

The microphone detection circuit is also an input to the Interrupt control circuit. An interrupt event is triggered whenever an accessory insertion, removal or impedance change is detected. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

FREQUENCY LOCKED LOOP (FLL) LOCK STATUS OUTPUT

The WM8958 maintains a flag indicating the lock status of each of FLLs, which may be used to control other events if required. See “Clocking and Sample Rates” for more details of the FLL.

The FLL Lock signals may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”.

The FLL Lock signals are inputs to the Interrupt control circuit. An interrupt event is triggered on the rising and falling edges of the FLL Lock signals. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

SAMPLE RATE CONVERTER (SRC) LOCK STATUS OUTPUT

The WM8958 maintains a flag indicating the lock status of each of Sample Rate Converters, which may be used to control other events if required. See “Sample Rate Conversion” for more details of the

Sample Rate Converters. w

The SRC Lock signals may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”.

The SRC Lock signals are inputs to the Interrupt control circuit, after the selectable de-bounce. An interrupt event is triggered on the rising and falling edges of the SRC Lock signals. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.

See “Interrupts” for more details of the Interrupt event handling.


160

Pre-Production

WM8958

DYNAMIC RANGE CONTROL (DRC) SIGNAL ACTIVITY DETECTION

Signal activity detection is provided on each of the Dynamic Range Controllers (DRCs). These may be configured to indicate when a signal is present on the respective signal path. The signal activity status signals may be used to control other events if required. See “Digital Core Architecture” for more details of the DRCs and the available digital signal paths.

When a DRC is enabled, as described in “Dynamic Range Control (DRC)”, then signal activity detection can be enabled by setting the respective [DRC]_SIG_DET register bit. The applicable threshold can be defined either as a Peak level (Crest Factor) or an RMS level, depending on the

[DRC]_SIG_DET_MODE register bit. When Peak level is selected, the threshold is determined by

[DRC]_SIG_DET_PK, which defines the applicable Crest Factor (Peak to RMS ratio) threshold. If

RMS level is selected, then the threshold is set using [DRC]_SIG_DET_RMS. These register fields are set independently for each of the three Dynamic Range Controllers, as described in Table 89.

When the DRC is enabled in any of the ADC (digital record) paths, the associated High Pass Filter

(HPF) must be enabled also; this ensures that DC offsets are removed prior to the DRC processing.

The output path HPF control registers are described in Table 42 (for AIF1 output paths) and Table 50

(for AIF2 output paths). These are described in the “Digital Volume and Filter Control” section.

The DRC Signal Detect signals may be output directly on any GPIO pin by setting the respective

GPIO registers as described in “GPIO Control”.

The DRC Signal Detect signals are inputs to the Interrupt control circuit. An interrupt event is triggered on the rising edge of the DRC Signal Detect signals. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.


ADDRESS

R1088

(0440h)

AIF1 DRC1

(1)

15:11

10:9

7

6

AIF1DRC1_SIG_

DET_RMS [4:0]

AIF1DRC1_SIG_

DET_PK [1:0]

AIF1DRC1_SIG_

DET_MODE

AIF1DRC1_SIG_

DET

00000

00

1

0

AIF1 DRC1 Signal Detect RMS

Threshold.

This is the RMS signal level for signal detect to be indicated when

AIF1DRC1_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

AIF1 DRC1 Signal Detect Peak

Threshold.

This is the Peak/RMS ratio, or Crest

Factor, level for signal detect to be indicated when


00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF1 DRC1 Signal Detect Mode

0 = Peak threshold mode

1 = RMS threshold mode

AIF1 DRC1 Signal Detect Enable

0 = Disabled


161

WM8958 w

Pre-Production

REGISTER

ADDRESS

R1104

(0450h)

AIF1 DRC2

(1)

R1344

(0540h)

AIF2 DRC (1)


15:11

10:9

7

6

15:11

10:9

7

6

AIF1DRC2_SIG_

DET_RMS [4:0]

AIF1DRC2_SIG_

DET_PK [1:0]

AIF1DRC2_SIG_

DET_MODE

AIF1DRC2_SIG_

DET

AIF2DRC_SIG_D

ET_RMS [4:0]

AIF2DRC_SIG_D

ET_PK [1:0]

AIF2DRC_SIG_D

ET_MODE

AIF2DRC_SIG_D

ET

00000

00

1

0

00000

00

1

0

Table 89 DRC Signal Activity Detect GPIO/Interrupt Control

DESCRIPTION

AIF1 DRC2 Signal Detect RMS

Threshold.



00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

AIF1 DRC2 Signal Detect Peak

Threshold.




00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB





0 = Disabled

1 = Enabled

AIF2 DRC Signal Detect RMS

Threshold.


AIF2DRC_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

AIF2 DRC Signal Detect Peak

Threshold.




00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF2 DRC Signal Detect Mode



AIF2 DRC Signal Detect Enable

0 = Disabled

1 = Enabled


162

Pre-Production

WM8958

CONTROL WRITE SEQUENCER STATUS DETECTION

The WM8958 Control Write Sequencer (WSEQ) can be used to execute a sequence of register write operations in response to a simple trigger event. When the Control Write Sequencer is executing a sequence, normal access to the register map via the Control Interface is restricted. See “Control Write

Sequencer” for details of the Control Write Sequencer.

The WM8958 generates a signal indicating the status of the Control Write Sequencer, in order to signal to the host processor whether the Control Interface functionality is restricted due to an ongoing

Control Sequence. The WSEQ_DONE flag indicates that the sequencer has completed the commanded sequence.

The Write Sequencer status may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”.

The Write Sequencer status is an input to the Interrupt control circuit. An interrupt event is triggered on completion of a Control Sequence. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

DIGITAL CORE FIFO ERROR STATUS DETECTION

The WM8958 monitors the Digital Core for error conditions which may occur if a clock rate mismatch is detected. Under these conditions, the digital audio may become corrupted.

The most likely cause of a Digital Core FIFO Error condition is an incorrect system clocking configuration. See “Clocking and Sample Rates” for the WM8958 system clocking requirements.

The Digital Core FIFO Error function is provided in order that the system configuration can be verified during product development.

The FIFO Error signal may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”.

The FIFO Error signal is an input to the Interrupt control circuit. An interrupt event is triggered on the rising edge of the FIFO Error signal. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

OPCLK CLOCK OUTPUT

A clock output (OPCLK) derived from SYSCLK may be output on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. This clock is enabled by register bit

OPCLK_ENA, and its frequency is controlled by OPCLK_DIV. w

See “Clocking and Sample Rates” for more details of the System Clock (SYSCLK).

REGISTER

ADDRESS

R2 (0002h)

Power

Management

(2)

R521 (0209h)

Clocking 1

11 OPCLK_EN

2:0

A

OPCLK_DIV

0

000

GPIO Clock Output (OPCLK) Enable

0 = Disabled

1 = Enabled

DESCRIPTION

GPIO Output Clock (OPCLK) Divider

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

Table 90 OPCLK Control


163

WM8958

Pre-Production

FLL CLOCK OUTPUT

The FLL Clock outputs may be output directly on any GPIO pin by setting the respective GPIO registers as described in “GPIO Control”.

See “Clocking and Sample Rates” for more details of the WM8958 system clocking and for details of how to enable and configure the Frequency Locked Loops. w PP, August 2012, Rev 3.4

164

Pre-Production

INTERRUPTS

WM8958

The Interrupt Controller has multiple inputs. These include the GPIO input pins, the FLL Lock circuits,

SRC Lock circuit, Microphone activity detection, Over-temperature indication, Digital FIFO error detection and the Write Sequencer status flag. Any combination of these inputs can be used to trigger an Interrupt Request (IRQ) event.

There is an Interrupt register field associated with each of the interrupt inputs. These fields are asserted whenever a logic edge is detected on the respective input. Some inputs are triggered on rising edges only; some are triggered on both edges, as noted in Table 91. The Interrupt register fields are held in Registers R1840 and R1841. The Interrupt flags can be polled at any time from these registers, or else in response to the Interrupt Request (IRQ) output being signalled via a GPIO pin.

All of the Interrupts are edge-triggered, as noted above. Many of these are triggered on both the rising and falling edges and, therefore, the Interrupt registers cannot indicate which edge has been detected. The “Raw Status” fields in Register R1842 provide readback of the current value of selected inputs to the Interrupt Controller. Note that the logic levels of any GPIO inputs can be read using the

GPn_LVL registers, as described in Table 86.

Individual mask bits can select or deselect different functions from the Interrupt controller. These are listed within the Interrupt Status Mask registers, as described in Table 91. Note that the Interrupt register fields remain valid, even when masked, but the masked interrupts will not cause the Interrupt

Request (IRQ) output to be asserted.

The Interrupt Request (IRQ) output represents the logical ‘OR’ of all the unmasked interrupts. The

Interrupt register fields are latching fields and, once they are set, they are not reset until a ‘1’ is written to the respective register bit(s). The Interrupt Request (IRQ) output is not reset until each of the unmasked interrupts has been reset.

De-bouncing of the GPIO inputs can be enabled using the register bits described in Table 86. Debouncing is also available on the Temperature Warning and Temperature Shutdown inputs to the

Interrupt Controller, in order to avoid false detections - see Table 91 for the associated registers.

The Interrupt Request (IRQ) output can be globally masked by setting the IM_IRQ register. Under default conditions, the Interrupt Request (IRQ) is not masked.

The Interrupt Request (IRQ) flag may be output on a GPIO pin - see “General Purpose Input/Output”.

The WM8958 Interrupt Controller circuit is illustrated in Figure 44. (Note that not all interrupt inputs are shown.) The associated control fields are described in Table 91.

Figure 44 Interrupt Controller w PP, August 2012, Rev 3.4

165

WM8958 w

REGISTER

ADDRESS

R1840

(0730h)

Interrupt

Status 1

R1841

(0731h)

Interrupt

Status 2

9

8

7

5

0

9

8

7

6

5

Pre-Production

DESCRIPTION

10 GP11_EINT

15

14

13

12

11

GP10_EINT

GP9_EINT

GP8_EINT

GP6_EINT

GP1_EINT

TEMP_WAR

N_EINT

DCS_DONE

_EINT

WSEQ_DO

NE_EINT

FIFOS_ERR

_EINT

AIF2DRC_SI

G_DET_EIN

T

10 AIF1DRC2_

SIG_DET_EI

NT

AIF1DRC1_

SIG_DET_EI

NT

SRC2_LOC

K_EINT

SRC1_LOC

K_EINT

FLL2_LOCK

_EINT

FLL1_LOCK

_EINT

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

GPIO11 Interrupt

(Rising and falling edge triggered)

Note: Cleared when a ‘1’ is written.

GPIO10 Interrupt



GPIO9 Interrupt



GPIO8 Interrupt



GPIO6 Interrupt



GPIO1 Interrupt



Temperature Warning Interrupt



DC Servo Interrupt

(Rising edge triggered)


Write Sequencer Interrupt



Digital Core FIFO Error Interrupt



AIF2 DRC Activity Detect Interrupt



AIF1 DRC2 (Timeslot 1) Activity Detect

Interrupt




Interrupt



SRC2 Lock Interrupt



SRC1 Lock Interrupt



FLL2 Lock Interrupt



FLL1 Lock Interrupt




166

Pre-Production w

REGISTER

ADDRESS

1 MICD_EINT

0 TEMP_SHU

T_EINT

R1842

(0732h)

Interrupt Raw

Status 2

15 TEMP_WAR

N_STS

14 DCS_DONE

_STS

13 WSEQ_DO

NE_STS

12 FIFOS_ERR

_STS

11 AIF2DRC_SI

G_DET_ST

S

10 AIF1DRC2_

SIG_DET_S

TS

9 AIF1DRC1_

SIG_DET_S

TS

8 SRC2_LOC

K_STS

7 SRC1_LOC

K_STS

6 FLL2_LOCK

_STS

5 FLL1_LOCK

_STS

R1848

(0738h)

Interrupt

Status 1

Mask

0 TEMP_SHU

T_STS

10 IM_GP11_EI

NT

9 IM_GP10_EI

NT

8 IM_GP9_EI

NT

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

WM8958

DESCRIPTION

Microphone Detection Interrupt



Temperature Shutdown Interrupt



Temperature Warning status



DC Servo status



Write Sequencer status

0 = Sequencer Busy (sequence in progress)

1 = Sequencer Idle

Digital Core FIFO Error status


1 = FIFO Error

AIF2 DRC Signal Detect status



AIF1 DRC2 (Timeslot 1) Signal Detect status






SRC2 Lock status

0 = Not locked

1 = Locked

SRC1 Lock status

0 = Not locked

1 = Locked

FLL2 Lock status

0 = Not locked

1 = Locked

FLL1 Lock status

0 = Not locked

1 = Locked

Temperature Shutdown status



GPIO11 Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.



1 = Mask interrupt.



1 = Mask interrupt.


167

WM8958 w

REGISTER

ADDRESS

R1849

(0739h)

Interrupt

Status 2

Mask

R1856

(0740h)

Interrupt

Control

7

5

0

9

8

7

6

5

1

0

0

Pre-Production

DESCRIPTION

15

14

13

12

11

IM_GP8_EI

NT

IM_GP6_EI

NT

IM_GP1_EI

NT

IM_TEMP_

WARN_EIN

T

IM_DCS_D

ONE_EINT

IM_WSEQ_

DONE_EINT

IM_FIFOS_

ERR_EINT

IM_AIF2DR

C_SIG_DET

_EINT

10 IM_AIF1DR

C2_SIG_DE

T_EINT

IM_AIF1DR

C1_SIG_DE

T_EINT

IM_SRC2_L

OCK_EINT

IM_SRC1_L

OCK_EINT

IM_FLL2_L

OCK_EINT

IM_FLL1_L

OCK_EINT

IM_MICD_EI

NT

IM_TEMP_S

HUT_EINT

IM_IRQ

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0



1 = Mask interrupt.



1 = Mask interrupt.



1 = Mask interrupt.

Temperature Warning Interrupt mask.


1 = Mask interrupt.

DC Servo Interrupt mask.


1 = Mask interrupt.

Write Sequencer Interrupt mask.


1 = Mask interrupt.

Digital Core FIFO Error Interrupt mask.


1 = Mask interrupt.

AIF2 DRC Activity Detect Interrupt mask.


1 = Mask interrupt.


Interrupt mask.


1 = Mask interrupt.


Interrupt mask.


1 = Mask interrupt.

SRC2 Lock Interrupt mask.


1 = Mask interrupt.



1 = Mask interrupt.

FLL2 Lock Interrupt mask.


1 = Mask interrupt.



1 = Mask interrupt.

Microphone Detection Interrupt mask.


1 = Mask interrupt.

Temperature Shutdown Interrupt mask.


1 = Mask interrupt.

IRQ Output Interrupt mask.


1 = Mask interrupt.


168

Pre-Production

REGISTER

ADDRESS

R1864

(0748h)

IRQ

Debounce

5 TEMP_WAR

N_DB

0 TEMP_SHU

T_DB

Table 91 Interrupt Configuration

1

1

WM8958

DESCRIPTION

Temperature Warning de-bounce

0 = Disabled

1 = Enabled

Temperature Shutdown de-bounce

0 = Disabled


169

WM8958

Pre-Production

DIGITAL AUDIO INTERFACE

The WM8958 provides digital audio interfaces for inputting DAC data and outputting ADC or Digital

Microphone data. Flexible routing options also allow digital audio to be switched or mixed between interfaces without involving any DAC or ADC.

The WM8958 provides two full audio interfaces, AIF1 and AIF2. A third interface, AIF3, supports

Mono PCM digital audio paths to/from the AIF2 DSP functions. AIF3 can also be configured using multiplexers to provide alternate connections to AIF1 or AIF2.

The digital audio interfaces provide flexible connectivity with multiple processors (eg. Applications processor, Baseband processor and Wireless transceiver). A typical configuration is illustrated in

Figure 45.

Applications

Processor

Audio Interface 1

Baseband

Processor

Audio Interface 2

Wireless

Transceiver

Audio Interface 3

WM8958

Figure 45 Typical AIF Connections

In the general case, the digital audio interface uses four pins:

 ADCDAT: ADC data output

 DACDAT: DAC data input

 LRCLK: Left/Right data alignment clock

 BCLK: Bit clock, for synchronisation

In master interface mode, the clock signals BCLK and LRCLK are outputs from the WM8958. In slave mode, these signals are inputs, as illustrated below.

As an option, a GPIO pin can be configured as the Left/Right clock for the ADC. In this case, the

LRCLK pin is dedicated to the DAC, allowing the ADC and DAC to be clocked independently.

Four different audio data formats are supported each digital audio interface:

 I 2 S w

All four of these modes are MSB first. They are described in the following sections. Refer to the

“Signal Timing Requirements” section for timing information.


170

Pre-Production

WM8958

Time Division Multiplexing (TDM) is available in all four data format modes. On AIF1, the WM8958 can transmit and receive data on two stereo pairs of timeslots simultaneously. On AIF2, the applicable timeslot pair is selectable using register control bits.

Two variants of DSP mode are supported - ‘Mode A’ and ‘Mode B’. Mono operation can be selected on either audio interface in both DSP modes. PCM operation is supported using the DSP mode.

MASTER AND SLAVE MODE OPERATION

The WM8958 digital audio interfaces can operate as a master or slave as shown in Figure 46 and

Figure 47. The associated control bits are described in “Digital Audio Interface Control”.

Figure 46 Master Mode Figure 47 Slave Mode

OPERATION WITH TDM

Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8958 ADCs and DACs support TDM in master and slave modes for all data formats and word lengths. TDM is enabled and configured using register bits defined in the “Digital Audio Interface

Control” section.

WM8958

BCLK

LRCLK

ADCDAT

DACDAT

Processor WM8958

BCLK

LRCLK

ADCDAT

DACDAT

Processor

WM8958 or similar

CODEC

BCLK

LRCLK

ADCDAT

DACDAT

Figure 48 TDM with WM8958 as Master

WM8958 or similar

CODEC

BCLK

LRCLK

ADCDAT

DACDAT

Figure 49 TDM with Other CODEC as Master w PP, August 2012, Rev 3.4

171

WM8958

WM8958

BCLK

LRCLK

ADCDAT

DACDAT

Pre-Production

Processor

WM8958 or similar

CODEC

BCLK

LRCLK

ADCDAT

DACDAT

Figure 50 TDM with Processor as Master

Note: The WM8958 is a 24-bit device. If the user operates the WM8958 in 32-bit mode then the 8

LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if necessary to the DACDAT line and the ADCDAT line in

TDM mode.

AUDIO DATA FORMATS (NORMAL MODE)

The audio data modes supported by the WM8958 are described below. Note that the polarity of the

BCLK and LRCLK signals can be inverted if required; the following descriptions all assume the default, non-inverted polarity of these signals.

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. w

Figure 51 Right Justified Audio Interface (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.


172

Pre-Production

WM8958

Figure 52 Left Justified Audio Interface (assuming n-bit word length)

In I 2 S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.

1/fs

LEFT CHANNEL RIGHT CHANNEL

LRCLK

BCLK

DACDAT/

ADCDAT

1 BCLK

1

MSB

2 3 n-2 n-1 n

LSB

Input Word Length (WL)

1 BCLK

1 2 3 n-2 n-1 n

Figure 53 I2S Justified Audio Interface (assuming n-bit word length)

In DSP mode, the left channel MSB is available on either the 1 st (mode B) or 2 nd (mode A) rising edge of BCLK following a rising edge of LRCLK. Right channel data immediately follows left channel data.

Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

The selected mode (Mode A or Mode B) is determined by the AIFnDAC_LRCLK_INV bits for the AIFn digital input (playback) signal paths, and by the AIFnADC_LRCLK_INV bits for the AIFn digital output

(record) signal paths.

Note that the DSP Mode is selected independently for the input/output paths of each digital audio interface.

In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 54 and

Figure 55. In device slave mode, Figure 56 and Figure 57, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. w PP, August 2012, Rev 3.4

173

WM8958

Pre-Production

Figure 54 DSP Mode A (AIFnDAC_LRCLK_INV / AIFnADC_LRCLK_INV=0, Master)

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

LEFT CHANNEL

1

MSB

2 3 n-2 n-1 n

LSB

Input Word Length (WL)

1 2 3

RIGHT CHANNEL n-2 n-1 n

Figure 55 DSP B Mode (AIFnDAC_LRCLK_INV / AIFnADC_LRCLK_INV=1, Master)

Figure 56 DSP Mode A (AIFnDAC_LRCLK_INV / AIFnADC_LRCLK_INV =0, Slave) w PP, August 2012, Rev 3.4

174

Pre-Production

WM8958 w

Figure 57 DSP Mode B (AIFnDAC_LRCLK_INV / AIFnADC_LRCLK_INV =1, Slave)

Mono mode operation is available in DSP interface mode. When Mono mode is enabled, the audio data is transmitted or received starting on either the 1 st (mode B) or 2 nd (mode A) rising edge of BCLK following a rising edge of LRCLK.

PCM operation is supported in DSP interface mode. WM8958 ADC data that is output on the Left

Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the

WM8958 will be treated as Left Channel data. This data may be routed to the Left/Right DACs using the control fields described in the “Digital Mixing” and “Digital Audio Interface Control” sections.

AUDIO DATA FORMATS (TDM MODE)

TDM is supported in master and slave modes. All audio interface data formats support time division multiplexing (TDM) for ADC and DAC data.

When more than one pair of ADC or DAC data channels is enabled on AIF1, the WM8958 will transmit and receive data in both Slot 0 and Slot 1.

In the case of AIF2, the ADC or DAC data can be transmitted or received in either timeslot; the required timeslot is selected using register control bits when TDM is enabled.

When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after data transmission, to allow another ADC device to drive this signal line for the remainder of the sample period. Note that it is important that two ADC devices do not attempt to drive the data pin simultaneously. A short circuit may occur if the transmission time of the two ADC devices overlap with each other. See “Audio Interface Timing” for details of the ADCDAT output relative to BCLK signal.

Note that it is possible to ensure a gap exists between transmissions by setting the transmitted word length to a value higher than the actual length of the data. For example, if 32-bit word length is selected where only 24-bit data is available, then the WM8958 interface will tri-state after transmission of the 24-bit data, ensuring a gap after the WM8958 TDM slot.

On AIF1, TDM can be used to transmit or receive up to four signal paths. Each enabled signal path is transmitted (on ADCDAT) or received (on DACDAT) sequentially. If one or more of the signal paths is disabled, then the position of remaining data blocks within the LRCLK frame may differ from those illustrated in Figure 58 to Figure 62, as the affected channel(s) will revert to the ‘normal’ (non-TDM) format. When the AIF1ADC_TDM register is set, then the ADCDAT1 output is tri-stated when not outputting data.

On AIF2, the TDM format is enabled by register control (AIF2ADC_TDM and AIF2DAC_TDM for the output and input paths respectively). When TDM is enabled on AIF2, the data formats shown in

Figure 58 to Figure 62 are always selected, and the WM8958 transmits or receives data in one of the two available timeslots; the ADCDAT2 output is tri-stated when not outputting data.

In all cases, the BCLK frequency must be high enough to allow data from the relevant time slots to be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format; the TDM timing for four input or output channels is shown in Figure 58 to Figure 62.


175

WM8958

Pre-Production

Figure 58 TDM in Right-Justified Mode

Figure 59 TDM in Left-Justified Mode

Figure 60 TDM in I 2 S Mode w

Figure 61 TDM in DSP Mode A


176

Pre-Production

Figure 62 TDM in DSP Mode B


177

WM8958

Pre-Production

DIGITAL AUDIO INTERFACE CONTROL

This section describes the configuration of the WM8958 digital audio interface paths.

Interfaces AIF1 and AIF2 can be configured as Master or Slave, or can be tri-stated. Each input and output signal path can be independently enabled or disabled. AIF output (digital record) and AIF input

(digital playback) paths can use a common Left/Right clock, or can use separate clocks for mixed sample rates.

Interfaces AIF1 and AIF2 each support flexible formats, word-length, TDM configuration, channel swapping and input path digital boost functions. 8-bit companding modes and digital loopback is also possible.

A third interface, AIF3, supports Mono PCM digital audio paths to/from the AIF2 DSP functions. AIF3 can also be configured using multiplexers to provide alternate connections to AIF1 or AIF2. Note that

AIF3 operates in Master mode only.

AIF1 - MASTER / SLAVE AND TRI-STATE CONTROL

The Digital Audio Interface AIF1 can operate in Master or Slave modes, selected by AIF1_MSTR. In

Master mode, the BCLK1 and LRCLK1 signals are generated by the WM8958 when one or more

AIF1 channels is enabled.

When AIF1_LRCLK_FRC or AIF1_CLK_FRC is set in Master mode, then LRCLK1 and ADCLRCLK1 are output at all times, including when none of the AIF1 audio channels is enabled. Note that LRCLK1 and ADCLRCLK1 are derived from BCLK1, and either an internal or external BCLK1 signal must also be present to generate LRCLK1 or ADCLRCLK1.

When AIF1_CLK_FRC is set in Master mode, then BCLK1 is output at all times, including when none of the AIF1 audio channels is enabled.

The AIF1 interface can be tri-stated by setting the AIF1_TRI register. When this bit is set, then all of the AIF1 outputs are un-driven (high-impedance). Note that the GPIO1/ADCLRCLK1 pin is a configurable pin which may take different functions independent of AIF1. The AIF1_TRI register only controls the GPIO1/ADCLRCLK1 pin when its function is set to ADCLRCLK1. See “General Purpose

Input/Output” to configure the GPIO1 pin.


ADDRESS

R770 (0302h)

AIF1

Master/Slave

15 AIF1_TRI 0

14

13

12

AIF1_MSTR

AIF1_CLK_F

RC

AIF1_LRCL

K_FRC

0

0

0

AIF1 Audio Interface tri-state

0 = AIF1 pins operate normally

1 = Tri-state all AIF1 interface pins

Note that the GPIO1 pin is controlled by this register only when configured as

ADCLRCLK1.

AIF1 Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

Forces BCLK1, LRCLK1 and ADCLRCLK1 to be enabled when all AIF1 audio channels are disabled.

0 = Normal

1 = BCLK1, LRCLK1 and ADCLRCLK1 always enabled in Master mode

Forces LRCLK1 and ADCLRCLK1 to be enabled when all AIF1 audio channels are disabled.

0 = Normal

1 = LRCLK1 and ADCLRCLK1 always enabled in Master mode

Table 92 AIF1 Master / Slave and Tri-state Control w PP, August 2012, Rev 3.4

178

Pre-Production w

WM8958

AIF1 - SIGNAL PATH ENABLE

The AIF1 interface supports up to four input channels and up to four output channels. All enabled channels are transmitted (on ADCDAT) or received (on DACDAT) sequentially, using time division multiplexing (TDM).

Each of the available channels can be enabled or disabled using the register bits defined in Table 93.

These register controls are illustrated in Figure 67.


ADDRESS

R4 (0004h)

Power

Management

(4)

R5 (0005h)

Power

Management

(5)

11

10

9

8

11

10

9

8

AIF1ADC2L

_ENA

AIF1ADC2R

_ENA

AIF1ADC1L

_ENA

AIF1ADC1R

_ENA

AIF1DAC2L

_ENA

AIF1DAC2R

_ENA

AIF1DAC1L

_ENA

AIF1DAC1R

_ENA

0

0

0

0

0

0

0

0

Enable AIF1ADC2 (Left) output path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1ADC2 (Right) output path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1ADC1 (Left) output path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

Enable AIF1ADC1 (Right) output path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

Enable AIF1DAC2 (Left) input path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1DAC2 (Right) input path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled


Timeslot 0)

0 = Disabled

1 = Enabled

Enable AIF1DAC1 (Right) input path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

Table 93 AIF1 Signal Path Enable

AIF1 - BCLK AND LRCLK CONTROL

The BCLK1 frequency is controlled relative to AIF1CLK by the AIF1_BCLK_DIV divider. See

“Clocking and Sample Rates” for details of the AIF1 clock, AIF1CLK.

The LRCLK1 frequency is controlled relative to BCLK1 by the AIF1DAC_RATE divider.

In Master mode, the LRCLK1 output is generated by the WM8958 when any of the AIF1 channels is enabled. (Note that, when GPIO1 is configured as ADCLRCLK1, then only the AIF1 DAC channels will cause LRCLK1 to be output.)

In Slave mode, the LRCLK1 output is disabled by default to allow another digital audio interface to drive this pin. It is also possible to force the LRCLK1 signal to be output, using the

AIF1DAC_LRCLK_DIR or AIF1ADC_LRCLK_DIR register bits, allowing mixed master and slave modes. (Note that, when GPIO1 is configured as ADCLRCLK1, then only the AIF1DAC_LRCLK_DIR bit will force the LRCLK1 signal.)


179

WM8958

Pre-Production

When the GPIO1 pin is configured as ADCLRCLK1, then the ADCLRCLK1 frequency is controlled relative to BCLK1 by the AIF1ADC_RATE divider. In this case, the ADCLRCLK1 is dedicated to AIF1 output, and the LRCLK1 pin is dedicated to AIF1 input, allowing different sample rates to be supported in the two paths.

In Master mode, with GPIO1 pin configured as ADCLRCLK1, this output is enabled when any of the

AIF1 ADC channels is enabled. The ADCLRCLK1 signal can also be enabled in Slave mode, using the AIF1ADC_LRCLK_DIR bit, allowing mixed master and slave modes.

When the GPIO1 pin is not configured as ADCLRCLK1, then the LRCLK1 signal applies to the ADC and DAC channels, at a rate set by AIF1DAC_RATE.

See “General Purpose Input/Output” for the configuration of GPIO1. Note that, in Ultrasonic (4FS) mode, the GPIO1 pin must be configured as ADCLRCLK1.

The BCLK1 output can be inverted using the AIF1_BCLK_INV register bit. The LRCLK1 and

ADCLRCLK1 output (when selected) can be inverted using the AIF1DAC_LRCLK_INV and

AIF1ADC_LRCLK_INV register controls respectively.

Note that in Slave mode, when BCLK1 is an input, the AIF1_BCLK_INV register selects the polarity of the received BCLK1 signal. Under default conditions, DACDAT1 input is captured on the rising edge of BCLK1, as illustrated in Figure 5. When AIF1_BCLK_INV = 1, DACDAT1 input is captured on the falling edge of BCLK1.

The AIF1 clock generators are controlled as illustrated in Figure 63. w

Figure 63 Audio Interface 1 - BCLK and LRCLK Control


180

Pre-Production w

REGISTER

ADDRESS

R768 (0300h)

AIF1 Control

(1)

8 AIF1_BCLK

_INV

R771 (0303h)

AIF1 BCLK

8:4 AIF1_BCLK

_DIV [4:0]

R772 (0304h)

AIF1ADC

LRCLK

12 AIF1ADC_L

RCLK_INV

11 AIF1ADC_L

RCLK_DIR

10:0 AIF1ADC_R

ATE [10:0]

0

00100

0

0

040h

WM8958

DESCRIPTION

BCLK1 Invert

0 = BCLK1 not inverted

1 = BCLK1 inverted

Note that AIF1_BCLK_INV selects the BCLK1 polarity in Master mode and in Slave mode.

BCLK1 Rate

00000 = AIF1CLK

00001 = AIF1CLK / 1.5

00010 = AIF1CLK / 2

00011 = AIF1CLK / 3

00100 = AIF1CLK / 4

00101 = AIF1CLK / 5

00110 = AIF1CLK / 6

00111 = AIF1CLK / 8

01000 = AIF1CLK / 11

01001 = AIF1CLK / 12

01010 = AIF1CLK / 16

01011 = AIF1CLK / 22

01100 = AIF1CLK / 24

01101 = AIF1CLK / 32

01110 = AIF1CLK / 44

01111 = AIF1CLK / 48

10000 = AIF1CLK / 64

10001 = AIF1CLK / 88

10010 = AIF1CLK / 96

10011 = AIF1CLK / 128

10100 = AIF1CLK / 176

10101 = AIF1CLK / 192

10110 - 11111 = Reserved

Right, left and I 2 S modes – ADCLRCLK1 polarity

0 = normal ADCLRCLK1 polarity

1 = invert ADCLRCLK1 polarity

Note that AIF1ADC_LRCLK_INV selects the

ADCLRCLK1 polarity in Master mode and in

Slave mode.

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK1 rising edge after ADCLRCLK1 rising edge (mode A)

1 = MSB is available on 1st BCLK1 rising edge after ADCLRCLK1 rising edge (mode B)

Allows ADCLRCLK1 to be enabled in Slave mode

0 = Normal

1 = ADCLRCLK1 enabled in Slave mode

ADCLRCLK1 Rate

ADCLRCLK1 clock output =

BCLK1 / AIF1ADC_RATE

Integer (LSB = 1)

Valid from 8..2047


181

WM8958 w

REGISTER

ADDRESS

R773 (0305h)

AIF1DAC

LRCLK

Pre-Production

DESCRIPTION

12 AIF1DAC_L

RCLK_INV

11 AIF1DAC_L

RCLK_DIR

10:0 AIF1DAC_R

ATE [10:0]

0

0

040h

Right, left and I 2 S modes – LRCLK1 polarity

0 = normal LRCLK1 polarity

1 = invert LRCLK1 polarity

Note that AIF1DAC_LRCLK_INV selects the

LRCLK1 polarity in Master mode and in Slave mode.


0 = MSB is available on 2nd BCLK1 rising edge after LRCLK1 rising edge (mode A)

1 = MSB is available on 1st BCLK1 rising edge after LRCLK1 rising edge (mode B)

Allows LRCLK1 to be enabled in Slave mode

0 = Normal

1 = LRCLK1 enabled in Slave mode

LRCLK1 Rate

LRCLK1 clock output =

BCLK1 / AIF1DAC_RATE

Integer (LSB = 1)

Valid from 8..2047

Table 94 AIF1 BCLK and LRCLK Control

AIF1 - DIGITAL AUDIO DATA CONTROL

The register bits controlling the audio data format, word length, left/right channel selection and TDM control for AIF1 are described in Table 95.

In DSP mode, the left channel MSB is available on either the 1 st (mode B) or 2 nd (mode A) rising edge of BCLK following a rising edge of LRCLK (assuming default BCLK polarity).

When the AIF1DAC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF1 digital input (playback) signal path. When the AIF1DAC_LRCLK_INV bit is not set, then DSP Mode A is selected.

When the AIF1ADC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF1 digital output (record) signal path. When the AIF1ADC_LRCLK_INV bit is not set, then DSP Mode A is selected.

Note that the DSP Mode is selected independently for the input/output paths of each digital audio interface. Also note that the AIF1ADCLRCLK_INV bits remain valid even when the LRCLK signal is common for both paths. See Table 94 for details of the AIF1DAC_LRCLK_INV and

AIF1ADC_LRCLK_INV register fields.

A digital gain function is available at the audio interface input path to boost the DAC volume when a small signal is received on DACDAT1. This is controlled using the AIF1DAC_BOOST register. To prevent clipping, this function should not be used when the boosted data is expected to be greater than 0dBFS.


ADDRESS

R768 (0300h)

AIF1 Control

(1)

15

14

AIF1ADCL_

SRC

AIF1ADCR_

SRC

0

1

AIF1 Left Digital Audio interface source

0 = Left ADC data is output on left channel

1 = Right ADC data is output on left channel

AIF1 Right Digital Audio interface source

0 = Left ADC data is output on right channel

1 = Right ADC data is output on right channel


182

Pre-Production w

WM8958

REGISTER

ADDRESS

DESCRIPTION

R769 (0301h)

AIF1 Control

(2)

R774 (0306h)

AIF1 DAC

Data

R775 (0307h)

AIF1 ADC

Data

13 AIF1ADC_T

DM

6:5 AIF1_WL

[1:0]

4:3 AIF1_FMT

[1:0]

15 AIF1DACL_

SRC

14 AIF1DACR_

SRC

11:10 AIF1DAC_B

OOST [1:0]

1

0

1

0

AIF1DACL_

DAT_INV

AIF1DACR_

DAT_INV

AIF1ADCL_

DAT_INV

AIF1ADCR_

DAT_INV

0

10

10

0

1

00

0

0

0

0

AIF1 transmit (ADC) TDM Control

0 = ADCDAT1 drives logic ‘0’ when not transmitting data

1 = ADCDAT1 is tri-stated when not transmitting data

AIF1 Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

Note - 8-bit modes can be selected using the

“Companding” control bits.

AIF1 Digital Audio Interface Format

00 = Right justified

01 = Left justified

10 = I 2 S Format

11 = DSP Mode

AIF1 Left Receive Data Source Select

0 = Left DAC receives left interface data

1 = Left DAC receives right interface data

AIF1 Right Receive Data Source Select

0 = Right DAC receives left interface data

1 = Right DAC receives right interface data

AIF1 Input Path Boost

00 = 0dB

01 = +6dB (input must not exceed -6dBFS)



AIF1 Left Receive Data Invert

0 = Not inverted

1 = Inverted

AIF1 Right Receive Data Invert

0 = Not inverted

1 = Inverted

AIF1 Left Transmit Data Invert

0 = Not inverted

1 = Inverted

AIF1 Right Transmit Data Invert

0 = Not inverted

1 = Inverted

Table 95 AIF1 Digital Audio Data Control

AIF1 - MONO MODE

AIF1 can be configured to operate in mono DSP mode by setting AIF1_MONO = 1 as described in

Table 96. Note that mono mode is only supported in DSP mode, ie when AIF1_FMT = 11.

In mono mode, the Left channel data or the Right channel data may be selected for output on

ADCDAT1. The selected channel is determined by the AIF1ADC1L_ENA and AIF1ADC1R_ENA bits.

(If both bits are set, then the Right channel data is selected.)

In mono mode, the DACDAT1 input can be enabled on the Left and/or Right signal paths using the

AIF1DAC1L_ENA and AIF1DAC1R_ENA bits. The mono input can be enabled on both paths at the same time if required.

Note that AIF1 TDM mode and AIF1 Mono mode cannot be supported simultaneously.


183

WM8958 w

REGISTER

ADDRESS

R769 (0301h)

AIF1 Control

(2)

8

Pre-Production

DESCRIPTION

AIF1_MONO 0 AIF1 DSP Mono Mode

0 = Disabled

1 = Enabled

Note that Mono Mode is only supported when

AIF1_FMT = 11.

Table 96 AIF1 Mono Mode Control

AIF1 - COMPANDING

The WM8958 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides of AIF1. This is configured using the register bits described in Table 97.

REGISTER

ADDRESS

R769 (0301h)

AIF1 Control

(2)

4 AIF1DAC_C

OMP

0

DESCRIPTION

3

2

1

AIF1DAC_C

OMPMODE

AIF1ADC_C

OMP

AIF1ADC_C

OMPMODE

0

0

0

AIF1 Receive Companding Enable

0 = Disabled

1 = Enabled

AIF1 Receive Companding Type

0 = µ-law

1 = A-law

AIF1 Transmit Companding Enable

0 = Disabled

1 = Enabled

AIF1 Transmit Companding Type

0 = µ-law

1 = A-law

Table 97 AIF1 Companding

Companding involves using a piecewise linear approximation of the following equations (as set out by

ITU-T G.711 standard) for data compression:

-law (where =255 for the U.S. and Japan):

F(x) = ln( 1 + |x|) / ln( 1 + )

A-law (where A=87.6 for Europe):

} for -1 ≤ x ≤ 1

F(x) = A|x| / ( 1 + lnA)

F(x) = ( 1 + lnA|x|) / (1 + lnA)

 for x ≤ 1/A

 for 1/A ≤ x ≤ 1

The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of data.

Companding converts 13 bits ( -law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).

AIF1 8-bit mode is selected whenever AIF1DAC_COMP=1 or AIF1ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK1 cycles per LRCLK1 frame. When using

DSP mode B, 8-bit data words may be transferred consecutively every 8 BCLK1 cycles.

AIF1 8-bit mode (without Companding) may be enabled by setting AIF1DAC_COMPMODE=1 or

AIF1ADC_COMPMODE=1, when AIF1DAC_COMP=0 and AIF1ADC_COMP=0.

BIT7 BIT[6:4]

SIGN EXPONENT

Table 98 8-bit Companded Word Composition

BIT[3:0]

MANTISSA


184

Pre-Production

120

100

80

60

40

20

0

0 u-law Companding

120

100

80

60

40

20

0

0 0.1

0.2

0.3

0.4

0.5

0.6

Normalised Input

0.7

0.8

0.9

0.7

0.6

0.5

0.4

0.3

0.2

1

0.9

0.8

1

0.1

0

Figure 64 µ-Law Companding

WM8958

A-law Companding

0.2

0.4

0.6

Normalised Input

0.8

1

0.9

0.8

0.7

0.6

1

0

0.2

0.1

0.5

0.4

0.3

Figure 65 A-Law Companding w PP, August 2012, Rev 3.4

185

WM8958

REGISTER

ADDRESS

R769 (0301h)

AIF1 Control

(2)

0

Pre-Production

AIF1 - LOOPBACK

The AIF1 interface can provide a Loopback option. When the AIF1_LOOPBACK bit is set, then AIF1 digital audio output is routed to the AIF1 digital audio input. The normal input (DACDAT1) is not used when AIF1 Loopback is enabled.

AIF1_LOOP

BACK

0

DESCRIPTION

AIF1 Digital Loopback Function

0 = No loopback

1 = Loopback enabled (ADCDAT1 data output is directly input to DACDAT1 data input).

Table 99 AIF1 Loopback

AIF1 - DIGITAL PULL-UP AND PULL-DOWN

The WM8958 provides integrated pull-up and pull-down resistors on each of the DACDAT1, LRCLK1 and BCLK1 pins. This provides a flexible capability for interfacing with other devices.

Each of the pull-up and pull-down resistors can be configured independently using the register bits described in Table 100. Note that if the Pull-up and Pull-down are both enabled for any pin, then the pull-up and pull-down will be disabled.


ADDRESS

R1824

(0720h)

Pull Control

(1)

5

4

3

2

1

0

DACDAT1_PU

DACDAT1_PD

DACLRCLK1_

PU

DACLRCLK1_

PD

BCLK1_PU

BCLK1_PD

0

0

0

0

0

0

DACDAT1 Pull-up enable

0 = Disabled

1 = Enabled

DACDAT1 Pull-down enable

0 = Disabled

1 = Enabled

LRCLK1 Pull-up enable

0 = Disabled

1 = Enabled

LRCLK1 Pull-down enable

0 = Disabled

1 = Enabled

BCLK1 Pull-up enable

0 = Disabled

1 = Enabled

BCLK1 Pull-down enable

0 = Disabled

1 = Enabled

Table 100 AIF1 Digital Pull-Up and Pull-Down Control w PP, August 2012, Rev 3.4

186

Pre-Production

WM8958

AIF2 - MASTER / SLAVE AND TRI-STATE CONTROL

The Digital Audio Interface AIF2 can operate in Master or Slave modes, selected by AIF2_MSTR. In

Master mode, the BCLK2 and LRCLK2 signals are generated by the WM8958 when one or more

AIF2 channels is enabled.

When AIF2_LRCLK_FRC or AIF2_CLK_FRC is set in Master mode, then LRCLK2 and ADCLRCLK2 are output at all times, including when none of the AIF2 audio channels is enabled. Note that LRCLK2 and ADCLRCLK2 are derived from BCLK2, and either an internal or external BCLK2 signal must also be present to generate LRCLK2 or ADCLRCLK2.

When AIF2_CLK_FRC is set in Master mode, then BCLK2 is output at all times, including when none of the AIF2 audio channels is enabled.

Note that the ADCLRCLK2 pin is also a GPIO pin, whose function is configurable. This pin must be configured for AIF functionality when used as audio interface pin. See “General Purpose

Input/Output”.

The AIF2 interface can be tri-stated by setting the AIF2_TRI register. When this bit is set, then all of the AIF2 outputs are un-driven (high-impedance). The AIF2_TRI register only affects those pins which are configured for AIF2 functions; it does not affect pins which are configured for other functions.

REGISTER

ADDRESS

R786 (0312h)

AIF2

Master/Slave

15

14

13

12

AIF2_TRI

AIF2_MSTR

AIF2_CLK_F

RC

AIF2_LRCL

K_FRC

0

0

0

0

Table 101 AIF2 Master / Slave and Tri-state Control

DESCRIPTION




Note that pins not configured as AIF2 functions are not affected by this register.

AIF2 Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

Forces BCLK2, LRCLK2 and ADCLRCLK2 to be enabled when all AIF2 audio channels are disabled.

0 = Normal


Forces LRCLK2 and ADCLRCLK2 to be enabled when all AIF2 audio channels are disabled.

0 = Normal

1 = LRCLK2 and ADCLRCLK2 always enabled in Master mode w PP, August 2012, Rev 3.4

187

WM8958

AIF2 - SIGNAL PATH ENABLE

The AIF2 interface supports two input channels and two output channels. Each of the available channels can be enabled or disabled using the register bits defined in Table 102. These register controls are illustrated in Figure 67.

REGISTER

ADDRESS

R4 (0004h)

Power

Management

(4)

R5 (0005h)

Power

Management

(5)

R784 (0310h)

AIF2 Control

(1)

13 AIF2ADCL_

ENA

12 AIF2ADCR_

ENA

13 AIF2DACL_

ENA

12 AIF2DACR_

ENA

1

0

Pre-Production

AIF2TXL_E

NA

AIF2TXR_E

NA

0

0

0

0

1

1

DESCRIPTION

Enable AIF2ADC (Left) output path

0 = Disabled

1 = Enabled

This bit must be set for AIF2 or AIF3 output of the AIF2ADC (Left) signal.

Enable AIF2ADC (Right) output path

0 = Disabled

1 = Enabled


Enable AIF2DAC (Left) input path

0 = Disabled

1 = Enabled

Enable AIF2DAC (Right) input path

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

This bit must be set for AIF2 output of the

AIF2ADC (Left) signal. For AIF3 output only, this bit can be set to 0.


0 = Disabled

1 = Enabled

This bit must be set for AIF2 output of the

AIF2ADC (Left) signal. For AIF3 output only, this bit can be set to 0.

Table 102 AIF2 Signal Path Enable


The BCLK2 frequency is controlled relative to AIF2CLK by the AIF2_BCLK_DIV divider. See

“Clocking and Sample Rates” for details of the AIF2 clock, AIF2CLK.

The LRCLK2 frequency is controlled relative to BCLK2 by the AIF2DAC_RATE divider.

In Master mode, the LRCLK2 output is generated by the WM8958 when any of the AIF2 channels is enabled. (Note that, when GPIO6 is configured as ADCLRCLK2, then only the AIF2 DAC channels will cause LRCLK2 to be output.)

In Slave mode, the LRCLK2 output is disabled by default to allow another digital audio interface to drive this pin. It is also possible to force the LRCLK2 signal to be output, using the

AIF2DAC_LRCLK_DIR or AIF2ADC_LRCLK_DIR register bits, allowing mixed master and slave modes. (Note that, when GPIO6 is configured as ADCLRCLK2, then only the AIF2DAC_LRCLK_DIR bit will force the LRCLK2 signal.)

When the GPIO6 pin is configured as ADCLRCLK2, then the ADCLRCLK2 frequency is controlled relative to BCLK2 by the AIF2ADC_RATE divider. In this case, the ADCLRCLK2 is dedicated to AIF2 output, and the LRCLK2 pin is dedicated to AIF2 input, allowing different sample rates to be supported in the two paths. w

In Master mode, with GPIO6 pin configured as ADCLRCLK2, this output is enabled when any of the

AIF2 ADC channels is enabled. The ADCLRCLK2 signal can also be enabled in Slave mode, using the AIF2ADC_LRCLK_DIR bit, allowing mixed master and slave modes.


188

Pre-Production

WM8958

See “General Purpose Input/Output” for the configuration of GPIO6.

The BCLK2 output can be inverted using the AIF2_BCLK_INV register bit. The LRCLK2 and

ADCLRCLK2 output (when selected) can be inverted using the AIF2DAC_LRCLK_INV and

AIF2ADC_LRCLK_INV register controls respectively.

Note that in Slave mode, when BCLK2 is an input, the AIF2_BCLK_INV register selects the polarity of the received BCLK2 signal. Under default conditions, DACDAT2 input is captured on the rising edge of BCLK2, as illustrated in Figure 5. When AIF2_BCLK_INV = 1, DACDAT2 input is captured on the falling edge of BCLK2.

The AIF2 clock generators are controlled as illustrated in Figure 66. w

Figure 66 Audio Interface 2 - BCLK and LRCLK Control


189

WM8958 w

REGISTER

ADDRESS

R784 (0310h)

AIF2 Control

(1)

R787 (0313h)

AIF2 BCLK

R788 (0314h)

AIF2ADC

LRCLK

R789 (0315h)

AIF2DAC

LRCLK

8

Pre-Production

DESCRIPTION

8:4

12

11

10:0

12

AIF2_BCLK

_INV

AIF2_BCLK

_DIV [4:0]

AIF2ADC_L

RCLK_INV

AIF2ADC_L

RCLK_DIR

AIF2ADC_R

ATE [10:0]

AIF2DAC_L

RCLK_INV

0

00100

0

0

040h

0

BCLK2 Invert


1 = BCLK2 inverted


BCLK2 Rate

00000 = AIF2CLK

00001 = AIF2CLK / 1.5

00010 = AIF2CLK / 2

00011 = AIF2CLK / 3

00100 = AIF2CLK / 4

00101 = AIF2CLK / 5

00110 = AIF2CLK / 6

00111 = AIF2CLK / 8

01000 = AIF2CLK / 11

01001 = AIF2CLK / 12

01010 = AIF2CLK / 16

01011 = AIF2CLK / 22

01100 = AIF2CLK / 24

01101 = AIF2CLK / 32

01110 = AIF2CLK / 44

01111 = AIF2CLK / 48

10000 = AIF2CLK / 64

10001 = AIF2CLK / 88

10010 = AIF2CLK / 96

10011 = AIF2CLK / 128

10100 = AIF2CLK / 176

10101 = AIF2CLK / 192

10110 - 11111 = Reserved

Right, left and I 2 S modes – ADCLRCLK2 polarity




ADCLRCLK2 polarity in Master mode and in

Slave mode.


0 = MSB is available on 2nd BCLK2 rising edge after ADCLRCLK2 rising edge (mode A)

1 = MSB is available on 1st BCLK2 rising edge after ADCLRCLK2 rising edge (mode B)


0 = Normal


ADCLRCLK2 Rate



Integer (LSB = 1)

Valid from 8..2047




Note that AIF2DAC_LRCLK_INV selects the

LRCLK2 polarity in Master mode and in Slave mode.


190

Pre-Production w

WM8958

REGISTER

ADDRESS

DESCRIPTION

11 AIF2DAC_L

RCLK_DIR

10:0 AIF2DAC_R

ATE [10:0]

0

040h





0 = Normal


LRCLK2 Rate



Integer (LSB = 1)

Valid from 8..2047

Table 103 AIF2 BCLK and LRCLK Control


The register bits controlling the audio data format, word length, left/right channel selection and TDM control for AIF2 are described in Table 104.

When TDM mode is enabled on AIF2, the WM8958 can transmit and receive audio data in Slot 0 or

Slot 1. In this case, the ADCDAT2 output is tri-stated during the unused timeslot, allowing another device to transmit data on the same pin. See “Signal Timing Requirements” for the associated timing details. (Note that, when TDM is not enabled on AIF2, the ADCDAT2 output is driven logic ‘0’ during the unused timeslot.)

In DSP mode, the left channel MSB is available on either the 1 st (mode B) or 2 nd (mode A) rising edge of BCLK following a rising edge of LRCLK (assuming default BCLK polarity).

When the AIF2DAC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF2 digital input (playback) signal path. When the AIF2DAC_LRCLK_INV bit is not set, then DSP Mode A is selected.

When the AIF2ADC_LRCLK_INV bit is set in DSP mode, then DSP Mode B is selected for the AIF2 digital output (record) signal path. When the AIF2ADC_LRCLK_INV bit is not set, then DSP Mode A is selected.

Note that the DSP Mode is selected independently for the input/output paths of each digital audio interface. Also note that the AIF2ADCLRCLK_INV bits remain valid even when the LRCLK signal is common for both paths. See Table 103 for details of the AIF2DAC_LRCLK_INV and

AIF2ADC_LRCLK_INV register fields.



ADDRESS

R784 (0310h)

AIF2 Control

(1)

15

14

13

AIF2ADCL_

SRC

AIF2ADCR_

SRC

AIF2ADC_T

DM

0

1

0







AIF2 transmit (ADC) TDM Enable

0 = Normal ADCDAT2 operation

1 = TDM enabled on ADCDAT2


191

WM8958

REGISTER

ADDRESS

R785 (0311h)

AIF2 Control

(2)

R790 (0316h)

AIF2 DAC

Data

R791 (0317h)

AIF2 ADC

Data

12 AIF2ADC_T

DM_CHAN

6:5

4:3

15

14

13

12

AIF2DACL_

SRC

AIF2DACR_

SRC

11:10 AIF2DAC_B

1

0

1

0

Pre-Production

DESCRIPTION

AIF2_WL

[1:0]

AIF2_FMT

[1:0]

AIF2DAC_T

DM

AIF2DAC_T

DM_CHAN

OOST [1:0]

AIF2DACL_

DAT_INV

AIF2DACR_

DAT_INV

AIF2ADCL_

DAT_INV

AIF2ADCR_

DAT_INV

0

10

10

0

1

0

0

00

0

0

0

0

AIF2 transmit (ADC) TDM Slot Select

0 = Slot 0

1 = Slot 1


00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits



AIF2 Digital Audio Interface Format


01 = Left justified

10 = I 2 S Format

11 = DSP Mode







AIF2 receive (DAC) TDM Enable

0 = Normal DACDAT2 operation

1 = TDM enabled on DACDAT2

AIF2 receive (DAC) TDM Slot Select

0 = Slot 0

1 = Slot 1


00 = 0dB





0 = Not inverted

1 = Inverted


0 = Not inverted

1 = Inverted


0 = Not inverted

1 = Inverted


0 = Not inverted

1 = Inverted

Table 104 AIF2 Digital Audio Data Control w PP, August 2012, Rev 3.4

192

Pre-Production w

WM8958

AIF2 - MONO MODE

AIF2 can be configured to operate in mono DSP mode by setting AIF2_MONO = 1 as described in

Table 105. Note that mono mode is only supported in DSP mode, ie when AIF2_FMT = 11.

In mono mode, the Left channel data or the Right channel data may be selected for output on

ADCDAT2. The selected channel is determined by the AIF2ADCL_ENA and AIF2ADCR_ENA bits. (If both bits are set, then the Right channel data is selected.)

In mono mode, the DACDAT2 input can be enabled on the Left and/or Right signal paths using the

AIF2DACL_ENA and AIF2DACR_ENA bits. The mono input can be enabled on both paths at the same time if required.


ADDRESS

R785 (0311h)

AIF2 Control

(2)

8 AIF2_MONO 0 AIF2 DSP Mono Mode

0 = Disabled

1 = Enabled


AIF2_FMT = 11.

Table 105 AIF2 Mono Mode Control



For more details on Companding, see the Audio Interface AIF1 description above.

REGISTER

ADDRESS

R785 (0311h)

AIF2 Control

(2)

4

3

2

1

AIF2DAC_C

OMP

AIF2DAC_C

OMPMODE

AIF2ADC_C

OMP

AIF2ADC_C

OMPMODE

0

0

0

0

DESCRIPTION


0 = Disabled

1 = Enabled


0 = µ-law

1 = A-law


0 = Disabled

1 = Enabled


0 = µ-law

1 = A-law


AIF2 - LOOPBACK

The AIF2 interface can provide a Loopback option. When the AIF2_LOOPBACK bit is set, then AIF2 digital audio output is routed to the AIF2 digital audio input. The normal input (DACDAT2) is not used when AIF2 Loopback is enabled.

REGISTER

ADDRESS

R785 (0311h)

AIF2 Control

(2)

0 AIF2_LOOP

BACK

0

DESCRIPTION


0 = No loopback


Table 107 AIF2 Loopback


193

WM8958

Pre-Production

AIF2 - DIGITAL PULL-UP AND PULL-DOWN

The WM8958 provides integrated pull-up and pull-down resistors on each of the DACDAT2,

DACLRCLK2 and BCLK2 pins. This provides a flexible capability for interfacing with other devices.

Each of the pull-up and pull-down resistors can be configured independently using the register bits described in Table 108. Note that if the Pull-up and Pull-down are both enabled for any pin, then the pull-up and pull-down will be disabled.

Note that pull-up and pull-down resistors are also provided on the GPIO6/ADCLRCLK2 pin; this is described in the “General Purpose Input/Output” section.


ADDRESS

R1794

(0702h)

Pull Control

(BCLK2)

R1795

(0703h)

Pull Control

(DACLRCLK2)

R1796

(0704h)

Pull Control

(DACDAT2)

14

13

14

13

14

13

BCLK2_PU

BCLK2_PD

DACLRCLK2_

PU

DACLRCLK2_

PD

DACDAT2_PU

DACDAT2_PD

0

1

0

1

0

1

BCLK2 Pull-up enable

0 = Disabled

1 = Enabled

BCLK2 Pull-down enable

0 = Disabled

1 = Enabled

DACLRCLK2 Pull-up enable

0 = Disabled

1 = Enabled

DACLRCLK2 Pull-down enable

0 = Disabled

1 = Enabled

DACDAT2 Pull-up enable

0 = Disabled

1 = Enabled

DACDAT2 Pull-down enable

0 = Disabled

1 = Enabled

Table 108 AIF2 Digital Pull-Up and Pull-Down Control w PP, August 2012, Rev 3.4

194

Pre-Production

WM8958

AIF3 - SIGNAL PATH CONFIGURATION AND TRI-STATE CONTROL

The AIF3 interface provides Mono PCM digital audio paths to/from the AIF2 DSP functions. The AIF3 interface can also support stereo digital audio paths via multiplexers to provide alternate connections to AIF1 or AIF2. The relevant multiplexers are illustrated in Figure 67.

Left / Right source select / Mono Mix control

AIF2DAC_SRC

Left / Right source select /

Mono Mix control

AIF3ADC_SRC[1:0]

0R 0L 1R 1L 0R 0L 1R 1L

DIGITAL AUDIO

INTERFACE 1 (AIF1)

AIF1_DACDAT_SRC

0R 0L 0R 0L

DIGITAL AUDIO

INTERFACE 2 (AIF2)

MONO PCM

INTERFACE

AIF2_DACDAT_SRC

AIF3_ADCDAT_SRC[1:0]

LRCLK1 LRCLK2

AIF2_ADCDAT_SRC w

Figure 67 Audio Interface AIF3 Configuration

Note that all of the AIF3 connections are supported on pins which also provide GPIO functions. These pins must be configured as AIF functions when used as audio interface pins. See “General Purpose

Input/Output”.

The GPIO8 pin supports the DACDAT3 function, which provides the input to the AIF3 Mono PCM interface.

When AIF3 Mono PCM input is used, this must be configured as an input to the AIF2 input paths using the AIF2DAC_SRC register as described in Table 109. The AIF3 Mono input may be selected on either channel (Left or Right), with AIF2 input enabled on the opposite channel at the same time.

When AIF3 Mono PCM input is used, the AIF2 input paths must be enabled using the

AIF2DACR_ENA and AIF2DACL_ENA register bits defined in Table 102.

The DACDAT3 input pin can also be used as an input (mono or stereo) to AIF1 or AIF2. The data input source for AIF1 is selected using the AIF1_DACDAT_SRC register. The data input source for

AIF2 is selected using the AIF2_DACDAT_SRC register.

The DACDAT3 input pin can also be routed to the ADCDAT2 output. The ADCDAT2 source is selected using the AIF2_ADCDAT_SRC register.


195

WM8958 w

Pre-Production

The GPIO9 pin supports the ADCDAT3 function, which supports the output from the AIF3 Mono PCM interface. The source for the ADCDAT3 pin is selected using the AIF3_ADCDAT_SRC register.

When AIF3 Mono PCM output is used, the data source must be configured using the AIF3ADC_SRC register; this selects either the Left or Right AIF2 output paths as the data source.

When AIF3 Mono PCM output is used, the AIF2 output paths must be enabled using the

AIF2ADCR_ENA and AIF2ADCL_ENA register bits. Note that, if AIF3 Mono PCM output is required and AIF2 output is not used, then the AIF2 output can be disabled using the AIF2TXL_ENA and

AIF2TXR_ENA registers. See Table 102 for details of these registers.

The ADCDAT3 pin can also be used as an alternate data output (mono or stereo) from AIF1 or AIF2, or can be connected to the DACDAT2 data input.

The AIF3 interface can be tri-stated by setting the AIF3_TRI register. When this bit is set, then all of the AIF3 outputs are un-driven (high-impedance). The AIF3_TRI register only affects those pins which are configured for AIF3 functions; it does not affect pins which are configured for other functions.

The AIF3 control registers are described in Table 109.

REGISTER

ADDRESS

R6 (0006h)

Power

Management

(6)

10:9 AIF3ADC_S

RC [1:0]

00

8:7

5

4:3

2

1

AIF2DAC_S

RC [1:0]

AIF3_TRI

AIF3_ADCD

AT_SRC

[1:0]

AIF2_ADCD

AT_SRC

AIF2_DACD

AT_SRC

00

0

00

0

0

DESCRIPTION

AIF3 Mono PCM output source select

00 = None

01 = AIF2ADC (Left) output path

10 = AIF2ADC (Right) output path

11 = Reserved

AIF2 input path select

00 = Left and Right inputs from AIF2

01 = Left input from AIF2; Right input from

AIF3

10 = Left input from AIF3; Right input from

AIF2

11 = Reserved





GPIO9/ADCDAT3 Source select

00 = AIF1 ADCDAT1

01 = AIF2 ADCDAT2

10 = DACDAT2

11 = AIF3 Mono PCM output

Note that GPIO9 must be configured as

ADCDAT3.

ADCDAT2 Source select

0 = AIF2 ADCDAT2

1 = GPIO8/DACDAT3

For selection 1, the GPIO8 pin must also be configured as DACDAT3.

AIF2 DACDAT Source select

0 = DACDAT2

1 = GPIO8/DACDAT3



196

Pre-Production

WM8958

REGISTER

ADDRESS

DESCRIPTION

0 AIF1_DACD

AT_SRC

0 AIF1 DACDAT Source select

0 = DACDAT1

1 = GPIO8/DACDAT3

Note that, for selection 1, the GPIO8 pin must be configured as DACDAT3.

Table 109 AIF3 Signal Path Configuration


The GPIO10 pin supports the LRCLK3 function. When configured as LRCLK3, this pin outputs the

LRCLK signal from AIF1 or AIF2. The applicable AIF source is determined automatically as defined in

Table 110. Note that the LRCLK3 signal is also controlled by the logic illustrated in Figure 63 (AIF1) or Figure 66 (AIF2), depending on the selected AIF source.

The GPIO11 pin supports the BCLK3 function. When configured as BCLK3, this pin outputs the BCLK signal from AIF1 or AIF2. The applicable AIF source is determined automatically as defined in Table

110. Note that the BCLK3 signal is also controlled by the logic illustrated in Figure 63 (AIF1) or Figure

66 (AIF2), depending on the selected AIF source.

AIF1_DACDAT_SRC = 1

(DACDAT3 selected as AIF1 data input) or

CONDITION DESCRIPTION

AIF1 selected as BCLK3 / LRCLK3 source

AIF3_ADCDAT_SRC[1:0] = 00

(AIF1 data output selected on ADCDAT3)

All other conditions AIF2 selected as BCLK3 / LRCLK3 source

Table 110 BCLK3 / LRCLK3 Configuration

The LRCLK3 output can be inverted by setting the AIF3_LRCLK_INV register. Note that AIF3 operates in Master mode only.


ADDRESS

R800 (0320h)

AIF3 Control

(1)

7 AIF3_LRCL

K_INV

0 Right, left and I 2 S modes – LRCLK3 polarity






Table 111 AIF3 LRCLK Control w PP, August 2012, Rev 3.4

197

WM8958

Pre-Production


The register bits controlling the AIF3 Mono PCM interface are described in Table 112.

Note that these registers control the AIF3 Mono PCM interface only; they are not applicable to the

ADCDAT3 and DACDAT3 signal paths when these pins are selected as alternate inputs to the AIF1 or AIF2 interfaces.

The audio data format for AIF3 is set the same as AIF2; this is controlled using the AIF2_FMT register, as described in see Table 104.

In DSP mode, the AIF3 Mono channel MSB is available on either the 1 st (mode B) or 2 nd (mode A) rising edge of BCLK following a rising edge of LRCLK. The applicable DSP mode is selected using the AIF3_LRCLK_INV bit, as described in Table 111.

In Left justified, Right justified and I2S modes, the AIF3 Mono interface data is transmitted and received in the Left channel data bits of the ADCDAT3 and DACDAT3 channels.



ADDRESS

R800 (0320h)

AIF3 Control

(1)

R801 (0321h)

AIF3 Control

(2)

R802 (0322h)

AIF3DAC

Data

R803 (0323h)

AIF3ADC

Data

6:5 AIF3_WL

[1:0]

11:10 AIF3DAC_B

0

0

OOST [1:0]

AIF3DAC_D

AT_INV

AIF3ADC_D

AT_INV

10

00

0

0


00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits



Note that this controls the AIF3 Mono PCM interface path only; it does not affect AIF3 inputs/outputs routed to AIF1 or AIF2.


00 = 0dB




Note that this controls the AIF3 Mono PCM interface path only; it does not affect

DACDAT3 input to AIF1 or AIF2.

AIF3 Receive Data Invert

0 = Not inverted

1 = Inverted



AIF3 Transmit Data Invert

0 = Not inverted

1 = Inverted


ADCDAT3 output from AIF1 or AIF2.

Table 112 AIF3 Digital Audio Data Control w PP, August 2012, Rev 3.4

198

Pre-Production

WM8958



Note that these registers control the AIF3 Mono PCM interface only; they are not applicable to the

ADCDAT3 and DACDAT3 signal paths when these pins are selected as alternate inputs to the AIF1 or AIF2 interfaces.

For more details on Companding, see the Audio Interface AIF1 description above.

REGISTER

ADDRESS

R801 (0321h)

AIF3 Control

(2)

4

3

2

1

AIF3DAC_C

OMP

AIF3DAC_C

OMPMODE

AIF3ADC_C

OMP

AIF3ADC_C

OMPMODE

0

0

0

0

DESCRIPTION


0 = Disabled

1 = Enabled




0 = µ-law

1 = A-law




0 = Disabled

1 = Enabled




0 = µ-law

1 = A-law




AIF3 - LOOPBACK

The AIF3 interface can provide a Loopback option. When the AIF3_LOOPBACK bit is set, then AIF3

Mono PCM output is routed to the AIF3 Mono PCM input. The normal input (DACDAT3) is not used when AIF3 Loopback is enabled.

REGISTER

ADDRESS

R801 (0321h)

AIF3 Control

(2)

0 AIF3_LOOP

BACK

0

DESCRIPTION


0 = No loopback

1 = Loopback enabled (AIF3 Mono PCM data output is directly input to AIF3 Mono PCM data input).

Table 114 AIF3 Loopback w PP, August 2012, Rev 3.4

199

WM8958

Pre-Production

CLOCKING AND SAMPLE RATES

The WM8958 requires a clock for each of the Digital Audio Interfaces (AIF1 and AIF2). These may be derived from a common clock reference, or from independent references. Under typical clocking configurations, many commonly-used audio sample rates can be derived directly from the external reference; for additional flexibility, the WM8958 incorporates two Frequency Locked Loop (FLL) circuits to perform frequency conversion and filtering.

External clock signals may be connected via MCLK1 and MCLK2. In AIF Slave modes, the BCLK or

LRCLK signals may be used as a reference for the AIF clocks.

The WM8958 performs stereo full-duplex sample rate conversion between the audio interfaces AIF1 and AIF2, enabling digital audio to be routed between the interfaces, and asynchronous audio data to be mixed together. See “Sample Rate Conversion” for further details.

In AIF Slave modes, it is important to ensure the applicable AIF clock (AIF1CLK or AIF2CLK) is synchronised with the associated external LRCLK. This can be achieved by selecting an MCLK input that is derived from the same reference as the LRCLK, or can be achieved by selecting the external

BCLK or LRCLK signals as a reference input to one of the FLLs, as a source for the AIF clock.

If the AIF clock is not synchronised with the LRCLK, then clicks arising from dropped or repeated audio samples will occur, due to the inherent tolerances of multiple, asynchronous, system clocks.

See “Applications Information” for further details on valid clocking configurations.

Clocking for the Audio Interfaces is provided by AIF1CLK and AIF2CLK for AIF1 and AIF2 respectively. An additional internal clock, SYSCLK is derived from either AIF1CLK or AIF2CLK in order to support the DSP core functions, Charge Pump, Class D switching amplifier, DC servo control, Control Write Sequencer and other internal functions. A further clock, DSP2CLK, is derived from either AIF1CLK or AIF2CLK in order to support the Multiband Compressor (MBC) function.

The following operating limits must be observed when configuring the WM8958 clocks. Failure to observe these limits will result in degraded performance and/or incorrect system functionality. Latency in the WM8958 signal paths is reduced at high SYSCLK frequencies; power consumption is reduced at low SYSCLK frequencies.

 SYSCLK

 SYSCLK

 SYSCLK

 AIF1CLK

 AIF1CLK

 AIF2CLK

 AIF2CLK

 DSP2CLK

Note that, if DAC_OSR128 = 0 and ADC_OSR128 = 0, then a slower SYSCLK frequency is possible; in this case, the requirement is SYSCLK  2.048MHz.

Note that, under specific operating conditions, clocking ratios of 128 x fs and 192 x fs are possible; this is described in the “Digital to Analogue Converter (DAC)” section. w

The SYSCLK frequency must be  256 x fs, (where fs is the faster rate of AIF1_SR or AIF2_SR). The

SYSCLK frequency is derived from AIF1CLK or AIF2CLK, as selected by the SYSCLK_SRC register

(see Table 119).


200

Pre-Production

WM8958

Note that the bandwidth of the digital audio mixing paths will be determined by the sample rate of whichever AIF is selected as the SYSCLK source. When using only one audio interface, the active interface should be selected as the SYSCLK source. For best audio performance when using AIF1 and AIF2 simultaneously, the SYSCLK source must select the AIF with the highest sample rate

(AIFn_SR).

The AIFnCLK / fs ratio is the ratio of AIFnCLK to the AIFn sample rate, where ‘n’ identifies the applicable audio interface AIF1 or AIF2. The AIF clocking ratio and sample rate are set by the

AIFnCLK_RATE and AIFn_SR register fields, defined in Table 116 and Table 118.

Note that, in the case of mixed input/output path sample rates on either interface, then

AIFnCLK_RATE and AIFn_SR are set according to the higher of the two sample rates.

The clocking configuration for AIF1CLK, AIF2CLK, SYSCLK and DSP2CLK is illustrated in Figure 68.

The SYSCLK_SRC register is defined in Table 119.

The WM8958 provides integrated pull-up and pull-down resistors on the MCLK1 and MCLK2 pins.

This provides a flexible capability for interfacing with other devices. This is configured as described in

Table 119. Note that if the Pull-up and Pull-down are both enabled for any pin, then the pull-up and pull-down will be disabled.

Figure 68 Audio Interface Clock Control

AIF1CLK ENABLE

The AIF1CLK_SRC register is used to select the AIF1CLK source. The source may be MCLK1,

MCLK2, FLL1 or FLL2. If either of the Frequency Locked Loops is selected as the source, then the

FLL(s) must be enabled and configured as described later.

The AIF1CLK clock may be adjusted by the AIF1CLK_DIV divider, which provides a divide-by-two option. The selected source may also be inverted by setting the AIF1CLK_INV bit.

The maximum AIF1CLK frequency is specified in the “Electrical Characteristics” section. Note that, when AIF1CLK_DIV = 1, the maximum frequency limit applies to the divided-down AIF1CLK frequency.

The AIF1CLK is enabled by the register bit AIF1CLK_ENA. This bit should be set to 0 when reconfiguring the clock sources. It is not recommended to change AIF1CLK_SRC while the

AIF1CLK_ENA bit is set. w PP, August 2012, Rev 3.4

201

WM8958

REGISTER

ADDRESS

R512 (0200h)

AIF 1

Clocking (1)

Pre-Production


4:3 AIF1CLK_SR

C

2

1

0

AIF1CLK_INV

AIF1CLK_DIV

AIF1CLK_EN

A

00

0

0

0

AIF1CLK Source Select

00 = MCLK1

01 = MCLK2

10 = FLL1

11 = FLL2

AIF1CLK Invert

0 = AIF1CLK not inverted

1 = AIF1CLK inverted

AIF1CLK Divider

0 = AIF1CLK

1 = AIF1CLK / 2

AIF1CLK Enable

0 = Disabled

1 = Enabled

Table 115 AIF1CLK Enable

AIF1 CLOCKING CONFIGURATION

The WM8958 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The AIF1 clocking configuration is selected using 4 control fields, which are set according to the required AIF digital audio sample rate, and the ADC/DAC clocking rate.

The AIF1_SR register is set according to the AIF1 sample rate. Note that 88.2kHz and 96kHz modes are supported for AIF1 input (DAC playback) only.

The AIF1CLK_RATE register is set according to the ratio of AIF1CLK to the AIF1 sample rate. Note that there a some restrictions on the supported clocking ratios, depending on the selected sample rate and operating conditions. The supported configurations are detailed in the “Digital Microphone

Interface”, “Analogue to Digital Converter (ADC)” and “Digital to Analogue Converter (DAC)” sections, according to each applicable function.

The audio interface can support different sample rates for the input data (DAC path) and output data

(ADC path) simultaneously. In this case, the AIF1_SR and AIF1CLK_RATE fields should be set according to the faster of the two sample rates.

When different sample rates are used for input data (DAC path) and output data (ADC path), the clocking of the slower path is set using AIF1DAC_DIV (if the AIF input path has the slower sample rate) or AIF1ADC_DIV (if the AIF output path has the slower sample rate). The appropriate divider is set according to the ratio of the two sample rates.

For example, if AIF1 input uses 48kHz sample rate, and AIF1 output uses 8kHz, then AIF1ADC_DIV should be set to 110b (divide by 6).

Note that the audio interface cannot support every possible combination of input and output sample rate simultaneously, but only where the ratio of the sample rates matches the available AIF1ADC_DIV or AIF1DAC_DIV divider settings.

Note that the WM8958 performs sample rate conversion, where necessary, to provide digital mixing and interconnectivity between the Audio Interfaces and the DSP Core functions. One stereo Sample

Rate Converter (SRC) is provided for audio input; a second stereo SRC is provided for audio output.

Each SRC is automatically configured on AIF1 or AIF2, depending on the selected Clocking and

Sample Rate settings. The WM8958 cannot support configurations that would require SRC on the input or output paths of both interfaces simultaneously. See “Sample Rate Conversion” for further details. w PP, August 2012, Rev 3.4

202

Pre-Production w

REGISTER

ADDRESS

R513 (0201h)

AIF 1

Clocking (2)


5:3 AIF1DAC_DIV 000

R528 (0210h)

AIF1 Rate

2:0

7:4

3:0

AIF1ADC_DIV

AIF1_SR

AIF1CLK_RAT

E

000

1000

0011

WM8958

DESCRIPTION

Selects the AIF1 input path sample rate relative to the AIF1 output path sample rate.

This field should only be changed from default in modes where the AIF1 input path sample rate is slower than the AIF1 output path sample rate.

000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

Selects the AIF1 output path sample rate relative to the AIF1 input path sample rate.

This field should only be changed from default in modes where the AIF1 output path sample rate is slower than the AIF1 input path sample rate.

000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

Selects the AIF1 Sample Rate (fs)

0000 = 8kHz

0001 = 11.025kHz

0010 = 12kHz

0011 = 16kHz

0100 = 22.05kHz

0101 = 24kHz

0110 = 32kHz

0111 = 44.1kHz

1000 = 48kHz

1001 = 88.2kHz

1010 = 96kHz

All other codes = Reserved

Note that 88.2kHz and 96kHz modes are supported for AIF1 input (DAC playback) only.

Selects the AIF1CLK / fs ratio

0000 = Reserved

0001 = 128

0010 = 192

0011 = 256

0100 = 384

0101 = 512

0110 = 768

0111 = 1024

1000 = 1408

1001 = 1536


Table 116 AIF1 Clocking Configuration


203

WM8958 w

AIF2CLK ENABLE

Pre-Production

The AIF2CLK_SRC register is used to select the AIF2CLK source. The source may be MCLK1,

MCLK2, FLL1 or FLL2. If either of the Frequency Locked Loops is selected as the source, then the

FLL(s) must be enabled and configured as described later.

The AIF2CLK clock may be adjusted by the AIF2CLK_DIV divider, which provides a divide-by-two option. The selected source may also be inverted by setting the AIF2CLK_INV bit.

The maximum AIF2CLK frequency is specified in the “Electrical Characteristics” section. Note that, when AIF2CLK_DIV = 1, the maximum frequency limit applies to the divided-down AIF2CLK frequency.

The AIF2CLK is enabled by the register bit AIF2CLK_ENA. This bit should be set to 0 when reconfiguring the clock sources. It is not recommended to change AIF2CLK_SRC while the

AIF2CLK_ENA bit is set.


ADDRESS

R516 (0204h)

AIF 2

Clocking (1)

4:3

2

1

0

AIF2CLK_SR

C

AIF2CLK_INV

AIF2CLK_DIV

AIF2CLK_EN

A

00

0

0

0

AIF2CLK Source Select

00 = MCLK1

01 = MCLK2

10 = FLL1

11 = FLL2

AIF2CLK Invert



AIF2CLK Divider

0 = AIF2CLK

1 = AIF2CLK / 2

AIF2CLK Enable

0 = Disabled

1 = Enabled

Table 117 AIF2CLK Enable

AIF2 CLOCKING CONFIGURATION

The WM8958 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The AIF2 clocking configuration is selected using 4 control fields, which are set according to the required AIF digital audio sample rate, and the ADC/DAC clocking rate.

The AIF2_SR register is set according to the AIF2 sample rate. Note that 88.2kHz and 96kHz modes are supported for AIF2 input (DAC playback) only.

The AIF2CLK_RATE register is set according to the ratio of AIF2CLK to the AIF2 sample rate. Note that there a some restrictions on the supported clocking ratios, depending on the selected sample rate and operating conditions. The supported configurations are detailed in the “Digital Microphone

Interface”, “Analogue to Digital Converter (ADC)” and “Digital to Analogue Converter (DAC)” sections, according to each applicable function.

The audio interface can support different sample rates for the input data (DAC path) and output data

(ADC path) simultaneously. In this case, the AIF2_SR and AIF2CLK_RATE fields should be set according to the faster of the two sample rates.

When different sample rates are used for input data (DAC path) and output data (ADC path), the clocking of the slower path is set using AIF2DAC_DIV (if the AIF input path has the slower sample rate) or AIF2ADC_DIV (if the AIF output path has the slower sample rate). The appropriate divider is set according to the ratio of the two sample rates.

For example, if AIF2 input uses 48kHz sample rate, and AIF2 output uses 8kHz, then AIF2ADC_DIV should be set to 110b (divide by 6).

Note that the audio interface cannot support every possible combination of input and output sample rate simultaneously, but only where the ratio of the sample rates matches the available AIF2ADC_DIV or AIF2DAC_DIV divider settings.


204

Pre-Production

WM8958

Note that the WM8958 performs sample rate conversion, where necessary, to provide digital mixing and interconnectivity between the Audio Interfaces and the DSP Core functions. One stereo Sample

Rate Converter (SRC) is provided for audio input; a second stereo SRC is provided for audio output.

Each SRC is automatically configured on AIF1 or AIF2, depending on the selected Clocking and

Sample Rate settings. The WM8958 cannot support configurations that would require SRC on the input or output paths of both interfaces simultaneously. See “Sample Rate Conversion” for further details.


ADDRESS

R517

(0205h)

AIF 2

Clocking

(2)


5:3 AIF2DAC_DIV 000

R529

(0211h)

AIF2

Rate

2:0

7:4

AIF2ADC_DIV

AIF2_SR

000

1000

Selects the AIF2 input path sample rate relative to the AIF2 output path sample rate.


000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

Selects the AIF2 output path sample rate relative to the AIF2 input path sample rate.


000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

Selects the AIF2 Sample Rate (fs)

0000 = 8kHz

0001 = 11.025kHz

0010 = 12kHz

0011 = 16kHz

0100 = 22.05kHz

0101 = 24kHz

0110 = 32kHz

0111 = 44.1kHz

1000 = 48kHz

1001 = 88.2kHz

1010 = 96kHz


Note that 88.2kHz and 96kHz modes are supported for AIF2 input (DAC playback) only. w PP, August 2012, Rev 3.4

205

WM8958 w

Pre-Production

REGISTER

ADDRESS


3:0 AIF2CLK_RAT

E

0011

DESCRIPTION


0000 = Reserved

0001 = 128

0010 = 192

0011 = 256

0100 = 384

0101 = 512

0110 = 768

0111 = 1024

1000 = 1408

1001 = 1536


Table 118 AIF2 Clocking Configuration

MISCELLANEOUS CLOCK CONTROLS

SYSCLK provides clocking for many of the WM8958 functions. SYSCLK clock is required to support

DSP Core functions and also the Charge Pump, Class D switching amplifier, DC servo control,

Control Write Sequencer and other internal functions.

The SYSCLK_SRC register is used to select the SYSCLK source. The source may be AIF1CLK or

AIF2CLK, as illustrated in Figure 69. Note that the bandwidth of the digital audio mixing paths will be determined by the sample rate of whichever AIF is selected as the SYSCLK source. When using only one audio interface, the active interface should be selected as the SYSCLK source. For best audio performance when using AIF1 and AIF2 simultaneously, the SYSCLK source must select the AIF with the highest sample rate (AIFn_SR).

The SYSCLK_SRC register is also used to select the DSP2CLK source; the DSP2CLK clock is required for the Multiband Compressor (MBC) function. The MBC can enabled on the AIF1 or AIF2 input paths, regardless of the SYSCLK_SRC setting, provided that the minimum clocking requirement for the MBC is satisfied. See “Multiband Compressor” for further details.

The MBC clocking is enabled using the DSP2CLK_ENA bit, as illustrated in Figure 69. See

“Multiband Compressor” for further details of the MBC clocking requirements.

The AIF1 DSP processing clock is derived from SYSCLK, and enabled by AIF1DSPCLK_ENA.

The AIF2 DSP processing clock is derived from SYSCLK, and enabled by AIF2DSPCLK_ENA.

The clocking of the WM8958 ADC, DAC, digital mixer and digital microphone functions is enabled by setting SYSDSPCLK_ENA. See “Digital Microphone Interface” for details of the DMICCLK frequency.

Two modes of ADC / Digital Microphone operation can be selected using the ADC_OSR128 bit. This bit is enabled by default, giving best audio performance. De-selecting this bit provides a low power alternative setting.

A high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit. When the DAC_OSR128 bit is set, the audio performance is improved, but power consumption is also increased.

A clock is required for the Charge Pump circuit when the ground-referenced headphone outputs

(HPOUT1L and HPOUT1R) are enabled. The Charge Pump clock is derived from SYSCLK whenever the Charge Pump is enabled. The Charge Pump clock division is configured automatically.

A clock is required for the Class D speaker driver circuit when the speaker outputs (SPKOUTL and

SPKOUTR) are enabled. The Class D clock is derived from SYSCLK whenever these outputs are enabled in Class D mode. The Class D clock division is configured automatically. See “Analogue

Outputs” for details of the Class D switching frequency.

A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled by register big OPCLK_ENA, and its frequency of this clock is controlled by OPCLK_DIV. See General

Purpose Input/Output” to configure a GPIO pin for this function.


206

Pre-Production

WM8958

A slow clock (TOCLK) is derived internally in order to control volume update timeouts when the zerocross option is selected. This clock is enabled by register bit TOCLK_ENA, and its frequency is controlled by TOCLK_DIV.

A de-bounce control is provided for GPIO inputs and for other functions that may be selected as

GPIO outputs. The de-bounced clock frequency is controlled by DBCLK_DIV.

The WM8958 generates a 256kHz clock for internal functions; TOCLK and DBCLK are derived from this 256kHz clock. In order to generate this clock correctly when SYSCLK_SRC = 0, valid settings are required for AIF1_SR and AIF1CLK_RATE. To generate this clock correctly when SYSCLK_SRC = 1, valid settings are required for AIF2_SR and AIF2CLK_RATE.

The WM8958 Clocking is illustrated in Figure 69. w

Figure 69 System Clocking


207

WM8958

REGISTER

ADDRESS

R2 (0002h)

Power

Management

(2)

R520 (0208h)

Clocking (1)

R521 (0209h)

Clocking (2)

Pre-Production


11

14

4

3

2

1

0

10:8

6:4

OPCLK_ENA

DSP2CLK_EN

A

TOCLK_ENA

AIF1DSPCLK

_ENA

AIF2DSPCLK

_ENA

SYSDSPCLK_

ENA

SYSCLK_SRC

TOCLK_DIV

DBCLK_DIV

0

0

0

0

0

0

0

000

000


0 = Disabled

1 = Enabled

MBC Processor Clock Enable

0 = Disabled

1 = Enabled

Slow Clock (TOCLK) Enable

0 = Disabled

1 = Enabled

This clock is required for zero-cross timeout.

AIF1 Processing Clock Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Digital Mixing Processor Clock Enable

0 = Disabled

1 = Enabled

SYSCLK Source Select

0 = AIF1CLK

1 = AIF2CLK

Slow Clock (TOCLK ) Divider

(Sets TOCLK rate relative to 256kHz.)

000 = Divide by 256 (1kHz)

001 = Divide by 512 (500Hz)

010 = Divide by 1024 (250Hz)

011 = Divide by 2048 (125Hz)

100 = Divide by 4096 (62.5Hz)

101 = Divide by 8192 (31.2Hz)

110 = Divide by 16384 (15.6Hz)

111 = Divide by 32768 (7.8Hz)

De-bounce Clock (DBCLK) Divider

(Sets DBCLK rate relative to 256kHz.)


001 = Divide by 2048 (125Hz)

010 = Divide by 4096 (62.5Hz)

011 = Divide by 8192 (31.2Hz)

100 = Divide by 16384 (15.6Hz)

101 = Divide by 32768 (7.8Hz)

110 = Divide by 65536 (3.9Hz)

111 = Divide by 131072 (1.95Hz) w PP, August 2012, Rev 3.4

208

Pre-Production

WM8958

REGISTER

ADDRESS


R1568

(0620h)

Oversampling

R1793

(0701h)

Pull Control

(MCLK2)

R1824

(0720h)

Pull Control

(1)

2:0 OPCLK_DIV

1

0

14

13

7

6

ADC_OSR128

DAC_OSR128

MCLK2_PU

MCLK2_PD

MCLK1_PU

MCLK1_PD

000

1

0

0

1

0

0


0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK / 16


ADC / Digital Microphone Oversample

Rate Select

0 = Low Power

1 = High Performance

DAC Oversample Rate Select

0 = Low Power


MCLK2 Pull-up enable

0 = Disabled

1 = Enabled

MCLK2 Pull-down enable

0 = Disabled

1 = Enabled

MCLK1 Pull-up enable

0 = Disabled

1 = Enabled

MCLK1 Pull-down enable

0 = Disabled

1 = Enabled

Table 119 System Clocking

BCLK AND LRCLK CONTROL

The digital audio interfaces (AIF1 and AIF2) use BCLK and LRCLK signals for synchronisation. In master mode, these are output signals, generated by the WM8958. In slave mode, these are input signals to the WM8958. It is also possible to support mixed master/slave operation.

The BCLK and LRCLK signals are controlled as illustrated in Figure 70. See the “Digital Audio

Interface Control” section for further details of the relevant control registers. w PP, August 2012, Rev 3.4

209

WM8958

AIF1CLK

AIF2CLK

Pre-Production

AIF1_BCLK_DIV [4:0]

AIF1DAC_RATE [10:0] f/N f/N

AIF1_MSTR

AIF1ADC_RATE [10:0] MASTER

MODE

CLOCK

OUTPUTS f/N

BCLK1

LRCLK1

ADCLRCLK1/

GPIO1

AIF2_BCLK_DIV [4:0]

AIF2DAC_RATE [10:0] f/N

AIF2_MSTR f/N

AIF2ADC_RATE [10:0]

MASTER

MODE

CLOCK

OUTPUTS f/N

BCLK2

LRCLK2

GPIO6/

ADCLRCLK2

Figure 70 BCLK and LRCLK Control w PP, August 2012, Rev 3.4

210

Pre-Production

WM8958

CONTROL INTERFACE CLOCKING

Register map access is possible with or without a system clock. Clocking is provided from SYSCLK; the SYSCLK_SRC register selects either AIF1CLK or AIF2CLK as the applicable SYSCLK source.

When AIF1CLK is the SYSCLK source (ie. SYSCLK_SRC = 0), and AIF1CLK_ENA = 1, then an active clock source for AIF1CLK must be present for control interface clocking. If the AIF1CLK source is stopped, then AIF1CLK_ENA must be set to 0 for control register access.

When AIF2CLK is the SYSCLK source (ie. SYSCLK_SRC = 1), and AIF2CLK_ENA = 1, then an active clock source for AIF2CLK must be present for control interface clocking. If the AIF2CLK source is stopped, then AIF2CLK_ENA must be set to 0 for control register access.

FREQUENCY LOCKED LOOP (FLL)

Two integrated FLLs are provided to support the clocking requirements of the WM8958. These can be enabled and configured independently according to the available reference clocks and the application requirements. The reference clock may be a high frequency (eg. 12.288MHz) or low frequency (eg.

32.768kHz).

The FLL is tolerant of jitter and may be used to generate a stable AIF clock from a less stable input reference. The FLL characteristics are summarised in “Electrical Characteristics”. Note that the FLL can be used to generate a free-running clock in the absence of an external reference source. This is described in the “Free-Running FLL Clock” section below.

The input reference for FLL1 is selected using FLL1_REFCLK_SRC. The available options are

MCLK1, MCLK2, BCLK1 or LRCLK1. The input reference for FLL2 is selected using

FLL2_REFCLK_SRC. The available options are MCLK1, MCLK2, BCLK2 or LRCLK2.

The FLLs can be bypassed using the FLL1_BYP or FLL2_BYP registers. This allows the BCLKn clock to be used as the AIFnCLK reference, without enabling the respective FLL.

The FLL input reference and bypass configurations are illustrated in Figure 71. w

Figure 71 FLL Input Reference Selection

The following description is applicable to FLL1 and FLL2. The associated register control fields are described in Table 122 for FLL1 and Table 123 for FLL2.

The FLL control registers are illustrated in Figure 72.


211

WM8958

Pre-Production

Figure 72 FLL Configuration

The FLL is enabled using the FLLn_ENA register bit (where n = 1 for FLL1 and n = 2 for FLL2). Note that the other FLL registers should be configured before enabling the FLL; the FLLn_ENA register bit should be set as the final step of the FLLn enable sequence.

When changing FLL settings, it is recommended that the digital circuit be disabled via FLLn_ENA and then re-enabled after the other register settings have been updated. When changing the input reference frequency F

REF

, it is recommended that the FLL be reset by setting FLLn_ENA to 0.

The field FLLn_REFCLK_DIV provides the option to divide the input reference (MCLK, BCLK or

LRCLK) by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit - should be selected.

The FLL output frequency is directly determined from FLLn_FRATIO, FLLn_OUTDIV and the real number represented by N.K.

The integer value, N, is held in the FLLn_N register field. The fractional portion, K, is determined by the ratio FLLn_THETA / FLLn_LAMBDA.

Note that the FLLn_EFS_ENA register bit must be enabled in fractional mode (ie. whenever

FLLn_THETA > 0).

The FLL output frequency is generated according to the following equation:

F

OUT

= (F

VCO

/ FLLn_OUTDIV)

The FLL operating frequency, F

VCO

is set according to the following equation:

F

VCO

= (F

REF

x N.K x FLLn_FRATIO)

F

REF

is the input frequency, as determined by FLLn_REFCLK_DIV.

F

VCO

must be in the range 90-100 MHz. Frequencies outside this range cannot be supported.

Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating conditions. w PP, August 2012, Rev 3.4

212

Pre-Production

WM8958

In order to follow the above requirements for F

VCO

, the value of FLLn_OUTDIV should be selected according to the desired output F

OUT

. The divider, FLLn_OUTDIV, must be set so that F

VCO

is in the range 90-100MHz. The available divisions are integers from 4 to 64. Some typical settings of

FLLn_OUTDIV are noted in Table 120.

OUTPUT FREQUENCY F

OUT

FLLn_OUTDIV

1.875 MHz - 2.0833 MHz 101111 (divide by 48)

2.8125 MHz - 3.125 MHz

3.75 MHz - 4.1667 MHz

011111 (divide by 32)

010111 (divide by 24)

5.625 MHz - 6.25 MHz

11.25 MHz - 12.5 MHz

18 MHz - 20 MHz

22.5 MHz - 25 MHz

001111 (divide by 16)

000111 (divide by 8)



Table 120 Selection of FLLn_OUTDIV

The value of FLLn_FRATIO should be selected as described in Table 121.

REFERENCE FREQUENCY F

REF

FLLn_FRATIO

1MHz - 13.5MHz 0h (divide by 1)

256kHz - 1MHz

128kHz - 256kHz

64kHz - 128kHz

Less than 64kHz

1h (divide by 2)

2h (divide by 4)

3h (divide by 8)

4h (divide by 16)

Table 121 Selection of FLLn_FRATIO

In order to determine the remaining FLL parameters, the FLL operating frequency, F

VCO

, must be calculated, as given by the following equation:

F

VCO

= (F

OUT

x FLLn_OUTDIV)

The value of N.K can then be determined as follows:

N.K = F

VCO

/ (FLLn_FRATIO x F

REF

)

Note that, in the above equations:

FLLn_OUTDIV is the F

OUT

clock ratio.

F

REF

is the input frequency, after division by FLL_REFCLK_DIV, where applicable.

FLLn_FRATIO is the F

VCO

clock ratio (1, 2, 4, 8 or 16).

The value of N is held in the FLLn_N register field.

The value of K is determined by the ratio FLLn_THETA / FLLn_LAMBDA.

The FLLn_N, FLLn_THETA and FLLn_LAMBDA fields are all coded as integers (LSB = 1). w PP, August 2012, Rev 3.4

213

WM8958 w

Pre-Production

In Fractional Mode (FLLn_THETA > 0 and FLLn_EFS_ENA = 1), the register fields FLLn_THETA and

FLLn_LAMBDA can be calculated as follows:

Calculate GCD(FLL) using the ‘Greatest Common Denominator’ function:

GCD(FLL) = GCD(FLLn_FRATIO x F

REF

, F

VCO

) where GCD(x, y) is the greatest common denominator of x and y

Next, calculate FLLn_THETA and FLLn_LAMBDA using the following equations:

FLLn_THETA = (F

VCO

- (FLLn_N x FLLn_FRATIO x F

REF

)) / GCD(FLL)

FLLn_LAMBDA = (FLLn_FRATIO x F

REF

) / GCD(FLL)

Note that, in Fractional Mode, the values of FLLn_THETA and FLLn_LAMBDA must be co-prime (ie. not divisible by any common integer). The calculation above ensures that the values will be co-prime.

The value of K must be a fraction less than 1 (ie. FLLn_THETA must be less than FLLn_LAMBDA).

The FLL1 control registers are described in Table 122. The FLL2 control registers are described in

Table 123. Example settings for a variety of reference frequencies and output frequencies are shown in Table 125.


ADDRESS

R544 (0220h)

FLL1 Control (1)

0 FLL1_ENA 0

R545 (0221h)

FLL1 Control (2)

R546 (0222h)

FLL1 Control (3)

R547 (0223h)

FLL1 Control (4)

13:8

2:0

15:0

14:5

FLL1_OUTDIV

[5:0]

FLL1_FRATIO

[2:0]

FLL1_THETA

[15:0]

FLL1_N [9:0]

000000

000

0000h

000h

FLL1 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL1 enable sequence, ie. after the other FLL registers have been configured.

FLL1 F

OUT

clock divider

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(F

OUT

= F

VCO

/ FLL1_OUTDIV)

FLL1 F

VCO

clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

FLL Fractional multiply for F

REF

This field sets the numerator

(multiply) part of the FLL1_THETA /

FLL1_LAMBDA ratio.

Coded as LSB = 1.

FLL1 Integer multiply for F

REF

(LSB = 1)


214

Pre-Production

REGISTER

ADDRESS

R548 (0224h)

FLL1 Control (5)

R550 (0226h)

FLL1 EFS1

R551 (0227h)

FLL1 EFS2

15

4:3

1:0

2:1

0

FLL1_BYP

FLL1_REFCLK_

DIV [1:0]

FLL1_REFCLK_

SRC [1:0]

15:0 FLL1_LAMBDA

[15:0]

FLL1_EFS_ENA

0

00

00

0000h

11

0

WM8958

DESCRIPTION

FLL1 Bypass Select

0 = Disabled

1 = Enabled

When FLL1_BYP is set, the FLL1 output is derived directly from

BCLK1. In this case, FLL1 can be disabled.

FLL1 Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must be divided down to <=13.5MHz.

For lower power operation, the reference clock can be divided down further if desired.

FLL1 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK1

11 = BCLK1


REF

This field sets the denominator

(dividing) part of the FLL1_THETA /

FLL1_LAMBDA ratio.

Coded as LSB = 1.

Reserved - Do not change

FLL Fractional Mode EFS enable

0 = Integer Mode

1 = Fractional Mode

This bit should be set to 1 when

FLL1_THETA > 0.

Table 122 FLL1 Register Map

REGISTER

ADDRESS

R576 (0240h)

FLL2 Control (1)

0 FLL2_ENA 0

DESCRIPTION

FLL2 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL2 enable sequence, ie. after the other FLL registers have been configured. w PP, August 2012, Rev 3.4

215

WM8958 w

REGISTER

ADDRESS

R577 (0241h)

FLL2 Control (2)

R578 (0242h)

FLL2 Control (3)

R579 (0243h)

FLL2 Control (4)

R580 (0244h)

FLL2 Control (5)

R582 (0246h)

FLL2 EFS1

R583 (0247h)

Pre-Production

DESCRIPTION

13:8

2:0

15:0

14:5

15

4:3

1:0

15:0

2:1

FLL2_OUTDIV

[5:0]

FLL2_FRATIO

[2:0]

FLL2_THETA

[15:0]

FLL2_N [9:0]

FLL2_BYP

FLL2_REFCLK_

DIV [1:0]

FLL2_REFCLK_

SRC [1:0]

FLL2_LAMBDA

[15:0]

000000

000

0000h

000h

0

00

00

0000h

11

FLL2 F

OUT

clock divider

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(F

OUT

= F

VCO

/ FLL2_OUTDIV)

FLL2 F

VCO

clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16


REF

This field sets the numerator

(multiply) part of the FLL2_THETA /

FLL2_LAMBDA ratio.

Coded as LSB = 1.

FLL2 Integer multiply for F

REF

(LSB = 1)

FLL2 Bypass Select

0 = Disabled

1 = Enabled

When FLL2_BYP is set, the FLL2 output is derived directly from

BCLK2. In this case, FLL2 can be disabled.


00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8



FLL2 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK2

11 = BCLK2


REF

This field sets the denominator

(dividing) part of the FLL2_THETA /

FLL2_LAMBDA ratio.

Coded as LSB = 1.

Reserved - Do not change


216

Pre-Production

WM8958

REGISTER

ADDRESS

FLL2 EFS2

DESCRIPTION

0 FLL2_EFS_ENA 0 FLL Fractional Mode EFS enable

0 = Integer Mode

1 = Fractional Mode

This bit should be set to 1 when

FLL2_THETA > 0.

Table 123 FLL2 Register Map

FREE-RUNNING FLL CLOCK

The FLL can generate a clock signal even when no external reference is available. However, it should be noted that the accuracy of this clock is reduced, and a reference source should always be used where possible. The free-running FLL modes are not sufficiently accurate for hi-fi ADC or DAC operations, but are suitable for clocking most other functions, including the Write Sequencer, Charge

Pump, DC Servo and Class D loudspeaker driver. The free-running FLL operation is ideal for clocking the accessory detection function during low-power standby operating conditions (see “External

Accessory Detection”).

If an accurate reference clock is initially available, then the FLL should be configured as described above. The FLL will continue to generate a stable output clock after the reference input is stopped or disconnected.

If no reference clock is available at the time of starting up the FLL, then an internal clock frequency of approximately 12MHz can be generated by implementing the following sequence:

 Enable the FLL Analogue Oscillator (FLLn_OSC_ENA = 1)

 Set the F

OUT

clock divider to divide by 8 (FLLn_OUTDIV = 000111)

 Configure the oscillator frequency by setting FLLn_FRC_NCO = 1 and

FLLn_FRC_NCO_VAL = 19h

Note that the free-running FLL mode is not suitable for hi-fi CODEC applications. In the absence of any reference clock, the FLL output is subject to a very wide tolerance; see “Electrical Characteristics” for details of the FLL accuracy.

Note that the free-running FLL clock is selected as SYSCLK using the registers noted in Figure 68.

The free-running FLL clock may be used to support analogue functions, for which the digital audio interface is not used, and there is no applicable Sample Rate (fs). When SYSCLK is required for circuits such the Class D, DC Servo, Control Write Sequencer or Charge Pump, then valid Sample

Rate register settings are still required, even though the digital audio interface is not active.

For correct functionality when SYSCLK_SRC = 0, valid settings are required for AIF1_SR and

AIF1CLK_RATE. In the case where SYSCLK_SRC = 1, then valid settings are required for AIF2_SR and AIF2CLK_RATE.

The control registers applicable to FLL free-running modes are described in Table 124. w PP, August 2012, Rev 3.4

217

WM8958

REGISTER

ADDRESS

R544 (0220h)

FLL1 Control (1)

R548 (0224h)

FLL1 Control (5)

R576 (0240h)

FLL2 Control (1)

R580 (0244h)

FLL2 Control (5)

Pre-Production

DESCRIPTION

1

12:7

6

1

12:7

6

FLL1_OSC_ENA

FLL1_FRC_NCO

_VAL [5:0]

FLL1_FRC_NCO

FLL2_OSC_ENA

FLL2_FRC_NCO

_VAL [5:0]

FLL2_FRC_NCO

0

19h

0

0

19h

0

FLL1 Oscillator enable

0 = Disabled

1 = Enabled

(Note that this field is required for freerunning FLL1 modes only)

FLL1 Forced oscillator value

Valid range is 000000 to 111111

0x19h (011001) = 12MHz approx

(Note that this field is required for freerunning FLL modes only)

FLL1 Forced control select

0 = Normal

1 = FLL1 oscillator controlled by

FLL1_FRC_NCO_VAL


FLL2 Oscillator enable

0 = Disabled

1 = Enabled

(Note that this field is required for freerunning FLL2 modes only)

FLL2 Forced oscillator value


0x19h (011001) = 12MHz approx



0 = Normal

1 = FLL2 oscillator controlled by

FLL2_FRC_NCO_VAL


Table 124 FLL Free-Running Mode

GPIO OUTPUTS FROM FLL

For each FLL, the WM8958 has an internal signal which indicates whether the FLL Lock has been achieved. The FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event - see “Interrupts”.

The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See

“General Purpose Input/Output” for details of how to configure a GPIO pin to output the FLL Lock signal.

The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the

FLL Clock may be output even if the FLL is not selected as the WM8958 SYSCLK source. The FLL clocking configuration is illustrated in Figure 71. See “General Purpose Input/Output” for details of how to configure a GPIO pin to output the FLL Clock. w PP, August 2012, Rev 3.4

218

Pre-Production

WM8958

EXAMPLE FLL CALCULATION

The following example illustrates how to derive the FLL1 registers to generate 12.288 MHz output

(F

OUT

) from a 12.000 MHz reference clock (F

REF

):

 Set FLL1_REFCLK_DIV in order to generate F

REF

<=13.5MHz:

FLL1_REFCLK_DIV = 00 (divide by 1)

 Set FLL1_OUTDIV for the required output frequency as shown in Table 120:-

F

OUT

= 12.288 MHz, therefore FLL1_OUTDIV = 7h (divide by 8)

 Set FLL1_FRATIO for the given reference frequency as shown in Table 121:

F

REF

= 12MHz, therefore FLL1_FRATIO = 0h (divide by 1)

VCO

as given by F

VCO

= F

OUT

x FLL1_OUTDIV:-

F

VCO

= 12.288 x 8 = 98.304MHz

 Calculate N.K as given by N.K = F

VCO

/ (FLL1_FRATIO x F

REF

):

N.K = 98.304 / (1 x 12) = 8.192

 Set FLL1_EFS_ENA according to whether N.K is an integer.

N.K has a fractional part, therefore FLL1_EFS_ENA = 1

 Determine FLL1_N from the integer portion of N.K:-

FLL_N = 8.

 Determine GCD(FLL), as given by GCD(FLL) = GCD(FLL1_FRATIO x F

REF

, F

VCO

):

GCD(FLL) = GCD(1 x 12000000, 98304000) = 96000

 Determine FLL1_THETA, as given by

FLL1_THETA = (F

VCO

- (FLL1_N x FLL1_FRATIO x F

REF

)) / GCD(FLL):

FLL1_THETA = (98304000 - (8 x 1 x 12000000)) / 96000

FLL1_THETA = 24 (0018h)

 Determine FLL_LAMBDA, as given by

FLL1_LAMBDA = (FLL1_FRATIO x F

REF

) / GCD(FLL):

FLL1_LAMBDA = (1 x 12000000) / 96000

FLL1_LAMBDA = 125 (007Dh) w PP, August 2012, Rev 3.4

219

WM8958

Pre-Production

EXAMPLE FLL SETTINGS

Table 125 provides example FLL settings for generating common SYSCLK frequencies from a variety of low and high frequency reference inputs.

F

SOURCE

32.000 kHz

32.000 kHz

32.768 kHz

32.768 kHz

44.1 kHz

48 kHz

128 kHz

128 kHz

512 kHz

F

OUT

(MHz) F

REF

Divider

12.288

N.K FRATIO F

VCO

(MHz) OUTDIV FLLn_N FLLn_

EFS_ENA

1 192 16 98.304 8 0C0h 0

FLLn_

THETA

FLLn_

LAMBDA

11.2896

12.288

11.2896

11.2896

12.288

2.048

12.288

2.048

512 kHz 12.288

1.4112 MHz 11.2896

1 128 16

1 128 16 98.304 8 080h 0

1 96 8 98.304 48 060h 0

1 96 8 98.304 8 060h 0

1 96 2 98.304 48 060h 0

1 96 2 98.304 8 060h 0

1 64 1

2.8224 MHz 11.2896

1.536 MHz

3.072 MHz

12.288

12.288

1 32 1

1 64 1 98.304 8 040h 0

1 32 1 98.304 8 020h 0

11.2896 12.288 1 8.7075 1 98.304 8 008h 1 0068h 0093h

12.000 MHz 12.288

12.000 MHz

12.288 MHz

11.2896

12.288

12.288 MHz 11.2896

13.000 MHz 12.288

13.000 MHz 11.2896

1 7.5264 1 90.3168 8 007h 1 0149h 0271h

1 8 1

1 7.5618 1 98.304 8 007h 1 0391h 0659h

1 6.9474 1 90.3168 8 006h 1 1E12h 1FBDh

19.200 MHz 12.288

19.200 MHz 11.2896

24 MHz

24 MHz

26 MHz

26 MHz

27 MHz

12.288

11.2896

12.288

11.2896

12.288

2 7.5264 1 90.3168 8 007h 1 0149h 0271h

2 7.5618 1 98.304 8 007h 1 0391h 0659h

2 6.9474 1 90.3168 8 006h 1 1E12h 1FBDh

2 7.2818 1 98.304 8 007h 1 013Dh 0465h

27 MHz 11.2896 2 6.6901 1 90.3168 8 006h 1 050Eh 0753h

F

OUT

= (F

SOURCE

/ F

REF

Divider) * N.K * FRATIO / OUTDIV

The values of N and K are contained in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above.

See Table 122 and Table 123 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers.

Table 125 Example FLL Settings w PP, August 2012, Rev 3.4

220

Pre-Production

WM8958

SAMPLE RATE CONVERSION

The WM8958 supports two main digital audio interfaces, AIF1 and AIF2. These interfaces are configured independently and may operate entirely asynchronously to each other. The WM8958 performs stereo full-duplex sample rate conversion between the audio interfaces, allowing digital audio to be routed between the interfaces, and allowing asynchronous audio data to be mixed together.

The Sample Rate Converters (SRCs) are configured automatically within the WM8958, and no user settings are required. The SRCs are enabled automatically when required and are disabled at other times. Synchronisation between the audio interfaces is not instantaneous when the clocking or sample rate configurations are updated; the lock status of the SRCs is signalled via the GPIO or

Interrupt circuits, as described in “General Purpose Input/Output” and “Interrupts”.

Separate clocks can be used for AIF1 and AIF2, allowing asynchronous operation on these interfaces. The digital mixing core is clocked by SYSCLK, which is linked to either AIF1CLK or

AIF2CLK, as described in “Clocking and Sample Rates”. The digital mixing core is, therefore, always synchronised to AIF1, or to AIF2, or to both interfaces at once.

SAMPLE RATE CONVERTER 1 (SRC1)

SRC1 performs sample rate conversion of digital audio data input to the WM8958. Sample Rate

Conversion is required when digital audio data is received on an audio interface that is not synchronised to the digital mixing core.

SRC1 is automatically configured on AIF1 or AIF2, depending on the selected Clocking and Sample

Rate configuration. Note that SRC1 cannot convert input data on AIF1 and AIF2 simultaneously.

Sample Rate conversion on AIF1 is only supported on TDM Timeslot 0.

The SRC1 Lock status indicates when audio data can be received on the interface channel that is not synchronised to the digital mixing core. No audio will be present on this signal path until SRC1 Lock is achieved.

SAMPLE RATE CONVERTER 2 (SRC2)

SRC2 performs sample rate conversion of digital audio data output from the WM8958. Sample Rate

Conversion is required when digital audio data is transmitted on an audio interface that is not synchronised to the digital mixing core.

SRC2 is automatically configured on AIF1 or AIF2, depending on the selected Clocking and Sample

Rate configuration. Note that SRC2 cannot convert output data on AIF1 and AIF2 simultaneously.

Sample Rate conversion on AIF1 is only supported on TDM Timeslot 0.

The SRC2 Lock status indicates when audio data can be transmitted on the interface channel that is not synchronised to the digital mixing core. No audio will be present on this signal path until SRC2

Lock is achieved.

SAMPLE RATE CONVERTER RESTRICTIONS

The following restrictions apply to the configuration of the WM8958 Sample Rate Converters.

No SRC on AIF1 Timeslot 1. Sample Rate Conversion on audio interface AIF1 is not supported on the TDM Timeslot 1. Therefore, it is not possible to route digital audio between AIF1 Timeslot 1 and

AIF2, or to mix together audio from these interface paths. Note that this only applies when the SRC is applied to AIF1.

Maximum of three sample rates in the system. The audio sample rate of AIF1 input and AIF1 output may be different to each other. The audio sample rate of AIF2 input and AIF2 output may be different to each other. However, it is not possible to have four different sample rates operating simultaneously, as this would require sample rate conversion in too many paths. A maximum of three different sample rates can be supported in the system. w PP, August 2012, Rev 3.4

221

WM8958

Pre-Production

No SRC capability when using 88.2kHz or 96kHz AIF input (DAC playback). If either interface is configured for 88.2kHz or 96kHz sample rate, then the digital mixing core must also be configured for this sample rate. Sample Rate Conversion cannot be supported in this mode, therefore AIF output is not supported at any sample rate under these conditions.

Restricted Sample Rate options when AIF1 and AIF2 are synchronised. When the same clock source is used for AIF1CLK and AIF2CLK, and mixed sample rates are selected on both interfaces, then the DAC sample rate of one interface must be the same as the ADC sample rate of the other.

 If AIF1CLK_SRC = AIF2CLK_SRC

 Then the DAC sample rate of one interface must be the same as the ADC sample rate of the other.

Restricted Sample Rate options when AIF1 and AIF2 are not synchronised. When a different clock source is used for AIF1CLK and AIF2CLK, then the AIF to which the SYSCLK is synchronised cannot be mixed sample rates.

 And SYSCLK_SRC =0

 Then AIF1DAC_DIV and AIF1ADC_DIV must be set to 000 w

 And SYSCLK_SRC =1

 Then AIF2DAC_DIV and AIF2ADC_DIV must be set to 000

SAMPLE RATE CONVERTER CONFIGURATION ERROR INDICATION

The WM8958 verifies the register settings relating to Clocking, Sample Rates and Sample Rate

Conversion. If an invalid configuration is attempted, then the SR_ERROR register will indicate the error by showing a non-zero value. This read-only field may be checked to confirm that the WM8958 can support the selected Clocking and Sample Rate settings.

REGISTER

ADDRESS

R530 (0212h)

Rate Status


3:0 SR_ERROR

[3:0]

0000

DESCRIPTION

Sample Rate Configuration status

Indicates an error with the register settings related to sample rate configuration

0000 = No errors

0001 = Invalid sample rate

0010 = Invalid AIF divide

0011 = ADC and DAC divides both set in an interface

0100 = Invalid combination of AIF divides and sample-rate

0101 = Invalid set of enables for 96kHz mode

0110 = Invalid SYSCLK rate (derived from

AIF1CLK_RATE or AIF2CLK_RATE)

0111 = Mixed ADC and DAC rates in

SYSCLK AIF when AIFs are asynchronous

1000 = Invalid combination of sample rates when both AIFs are from the same clock source

1001 = Invalid combination of mixed


222

Pre-Production

WM8958

REGISTER

ADDRESS


ADC/DAC AIFs when both from the same clock source

1010 = AIF1DAC2 (Timeslot 1) ports enabled when SRCs connected to AIF1

Table 126 Sample Rate Converter Configuration Status w PP, August 2012, Rev 3.4

223

WM8958

Pre-Production

CONTROL INTERFACE

The WM8958 is controlled by writing to registers through a 2-wire serial control interface. Readback is available for all registers, including Chip ID and power management status.

Note that the Control Interface function can be supported with or without system clocking. Where possible, the register map access is synchronised with SYSCLK in order to ensure predictable operation of cross-domain functions. See “Clocking and Sample Rates” for further details of Control

Interface clocking.

The WM8958 is a slave device on the control interface; SCLK is a clock input, while SDAT is a bidirectional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8958 transmits logic 1 by tri-stating the SDAT pin, rather than pulling it high. An external pull-up resistor is required to pull the SDAT line high so that the logic 1 can be recognised by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 8-bit device ID (this is not the same as the address of each register in the WM8958). The device ID is selectable on the WM8958, using the ADDR pin as shown in Table 127. The LSB of the

Device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.

An internal pull-down resistor is enabled by default on the ADDR pin; this can be configured using the

ADDR_PD register bit described in Table 129.

Low

High

0011 0100 (34h)

0011 0110 (36h)

Table 127 Control Interface Device ID Selection

The WM8958 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDAT while SCLK remains high. This indicates that a device ID, register address and data will follow. The WM8958 responds to the start condition and shifts in the next eight bits on SDAT (8-bit device ID, including Read/Write bit, MSB first). If the device ID received matches the device ID of the WM8958, then the WM8958 responds by pulling SDAT low on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the WM8958 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8958, the data transfer continues as described below. The controller indicates the end of data transfer with a low to high transition on SDAT while

SCLK remains high. After receiving a complete address and data sequence the WM8958 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDAT changes while SCLK is high), the device returns to the idle condition.

The WM8958 supports the following read and write operations:

 Single

 Single

 Multiple write using auto-increment

 Multiple read using auto-increment

The sequence of signals associated with a single register write operation is illustrated in Figure 73.

Figure 73 Control Interface 2-wire (I2C) Register Write w PP, August 2012, Rev 3.4

224

Pre-Production

WM8958

The sequence of signals associated with a single register read operation is illustrated in Figure 74.

Figure 74 Control Interface 2-wire (I2C) Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in

Table 128.

Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.

This feature is enabled by default, as noted in Table 129.

TERMINOLOGY DESCRIPTION

A Acknowledge (SDA Low)

Not Acknowledge (SDA High)

[White field]

[Grey field]

1 = Read

Data flow from bus master to WM8958

Data flow from WM8958 to bus master

Table 128 Control Interface Terminology

Figure 75 Single Register Write to Specified Address

Figure 76 Single Register Read from Specified Address w PP, August 2012, Rev 3.4

225

WM8958

Pre-Production

Figure 77 Multiple Register Write to Specified Address using Auto-increment

Figure 78 Multiple Register Read from Specified Address using Auto-increment

Figure 79 Multiple Register Read from Last Address using Auto-increment

Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of the data in the WM8958 register map faster than is possible with single register operations. The autoincrement option is enabled when the AUTO_INC register bit is set. This bit is defined in Table 129.

Auto-increment is enabled by default.


ADDRESS

R257 (0101h)

Control Interface

2 AUTO_INC 1

R1825 (0721h)

Pull Control (2)

8 ADDR_PD 1

Enables address auto-increment

0 = Disabled

1 = Enabled

ADDR Pull-down enable

0 = Disabled

1 = Enabled

Table 129 Control Interface Configuration w PP, August 2012, Rev 3.4

226

Pre-Production

WM8958

CONTROL WRITE SEQUENCER

The Control Write Sequencer is a programmable unit that forms part of the WM8958 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently.

Default sequences for Start-Up of each output driver and Shut-Down are provided (see “Default

Sequences” section). It is recommended that these default sequences are used unless changes become necessary.

When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The host processor informs the sequencer of the start index of the required sequence within the sequencer’s memory. At each step of the sequence, the contents of the selected register fields are read from the sequencer’s memory and copied into the WM8958 control registers. This continues sequentially through the sequencer’s memory until an “End of Sequence” bit is encountered; at this point, the sequencer stops and an Interrupt status flag is asserted. For cases where the timing of the write sequence is important, a programmable delay can be set for specific steps within the sequence.

Note that the Control Write Sequencer’s internal clock is derived from the internal clock SYS_CLK which must be enabled as described in “Clocking and Sample Rates”. The clock division from

SYS_CLK is handled transparently by the WM8958 without user intervention, provided that SYS_CLK is configured as specified in “Clocking and Sample Rates”.

INITIATING A SEQUENCE

The Register fields associated with running the Control Write Sequencer are described in Table 130.

Note that the operation of the Control Write Sequencer also requires the internal clock SYS_CLK to be configured as described in “Clocking and Sample Rates”.

The Write Sequencer is enabled by setting the WSEQ_ENA bit. The start index of the required sequence must be written to the WSEQ_START_INDEX field.

The Write Sequencer stores up to 128 register write commands. These are defined in Registers

R12288 to R12799. There are 4 registers used to define each of the 128 possible commands. The value of WSEQ_START_INDEX selects the registers applicable to the first write command in the selected sequence.

Setting the WSEQ_START bit initiates the sequencer at the given start index. The Write Sequencer can be interrupted by writing a logic 1 to the WSEQ_ABORT bit.

The current status of the Write Sequencer can be read using two further register fields - when the

WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. Note that, whilst the

Control Write Sequencer is running a sequence (indicated by the WSEQ_BUSY bit), normal read/write operations to the Control Registers cannot be supported. The index of the current step in the Write Sequencer can be read from the WSEQ_CURRENT_INDEX field; this is an indicator of the sequencer’s progress. On completion of a sequence, this field holds the index of the last step within the last commanded sequence.

When the Write Sequencer reaches the end of a sequence, it asserts the WSEQ_DONE_EINT flag in

Register R1841 (see Table 91). This flag can be used to generate an Interrupt Event on completion of the sequence. Note that the WSEQ_DONE_EINT flag is asserted to indicate that the WSEQ is NOT

Busy. w PP, August 2012, Rev 3.4

227

WM8958 w

Pre-Production

REGISTER

ADDRESS

R272 (0110h)

Write

Sequencer

Ctrl (1)

R273 (0111h)

Write

Sequencer

Ctrl (2)


15

9

8

6:0

8

6:0

WSEQ_ENA

WSEQ_ABORT

WSEQ_START

WSEQ_START_

INDEX [6:0]

WSEQ_BUSY

(read only)

WSEQ_CURRE

NT_INDEX [6:0]

(read only)

DESCRIPTION

0

0

0

Write Sequencer Enable.

0 = Disabled

1 = Enabled

Writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface.

Writing a 1 to this bit starts the write sequencer at the index location selected by WSEQ_START_INDEX.

The sequence continues until it reaches an “End of sequence” flag.

At the end of the sequence, this bit will be reset by the Write Sequencer.

000_0000 Sequence Start Index. This field determines the memory location of the first command in the selected sequence. There are 127 Write

Sequencer RAM addresses:

00h = WSEQ_ADDR0 (R12288)



….

7Fh = WSEQ_ADDR127 (R12796)

0 Sequencer Busy flag (Read Only).

0 = Sequencer idle

1 = Sequencer busy

Note: it is not possible to write to control registers via the control interface while the Sequencer is

Busy.

000_0000 Sequence Current Index. This indicates the memory location of the most recently accessed command in the write sequencer memory.

Coding is the same as

WSEQ_START_INDEX.

Table 130 Write Sequencer Control - Initiating a Sequence

PROGRAMMING A SEQUENCE

A sequence consists of write operations to data bits (or groups of bits) within the control registers.

Each write operation is defined by a block of 4 registers, which contain 6 fields as described in this section.

The block of 4 registers is the same for up to 128 steps held in the sequencer memory. Multiple sequences can be held in the memory at the same time; each sequence occupies its own range within the 128 available register blocks.

The following 6 fields are replicated 128 times - one for each of the sequencer’s 128 steps. In the following descriptions, the term ‘n’ is used to denote the step number, from 0 to 127.

WSEQ_ADDRn is a 14-bit field containing the Control Register Address in which the data should be written.

WSEQ_DATAn is an 8-bit field which contains the data to be written to the selected Control Register.

The WSEQ_DATA_WIDTHn field determines how many of these bits are written to the selected register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTHn) are ignored.


228

Pre-Production

WM8958

WSEQ_DATA_STARTn is a 4-bit field which identifies the LSB position within the selected Control

Register to which the data should be written. For example, setting WSEQ_DATA_STARTn = 0100 will select bit 4 as the LSB position; in this case, 4-bit data would be written to bits 7:4.

WSEQ_DATA_WIDTHn is a 3-bit field which identifies the width of the data block to be written. This enables selected portions of a Control Register to be updated without any concern for other bits within the same register, eliminating the need for read-modify-write procedures. Values of 0 to 7 correspond to data widths of 1 to 8 respectively. For example, setting WSEQ_DATA_WIDTHn = 010 will cause a

3-bit data block to be written. Note that the maximum value of this field corresponds to an 8-bit data block; writing to register fields greater than 8 bits wide must be performed using two separate operations of the Control Write Sequencer.

WSEQ_DELAYn is a 4-bit field which controls the waiting time between the current step and the next step in the sequence i.e. the delay occurs after the write in which it was called. The total delay time per step (including execution) is defined below, giving a useful range of execution/delay times from

562 s up to 2.048s per step:

T = k × (2 WSEQ_DELAY + 8) where k = 62.5

s (under recommended operating conditions)

WSEQ_EOSn is a 1-bit field which indicates the End of Sequence. If this bit is set, then the Control

Write Sequencer will automatically stop after this step has been executed.

The register definitions for Step 0 are described in Table 131. The equivalent definitions also apply to

Step 1 through to Step 127, in the subsequent register address locations. w

REGISTER

ADDRESS

R12288

(3000h)

Write

Sequencer 0

R12289

(3001h)

Write

Sequencer 1

R12290

(3002h)

Write

Sequencer 2

R12291

(3003h)

Write

Sequencer 3


13:0

7:0

10:8

3:0

8

3:0

WSEQ_ADDR

0 [13:0]

WSEQ_DATA

0 [7:0]

WSEQ_DATA

_WIDTH0 [2:0]

WSEQ_DATA

_START0 [3:0]

WSEQ_EOS0

WSEQ_DELA

Y0 [3:0]

0000h

00h

000

0000

0

0000

DESCRIPTION

Control Register Address to be written to in this sequence step.

Data to be written in this sequence step.

When the data width is less than 8 bits, then one or more of the MSBs of

WSEQ_DATAn are ignored. It is recommended that unused bits be set to

0.

Width of the data block written in this sequence step.

000 = 1 bit

001 = 2 bits

010 = 3 bits

011 = 4 bits

100 = 5 bits

101 = 6 bits

110 = 7 bits

111 = 8 bits

Bit position of the LSB of the data block written in this sequence step.

0000 = Bit 0

…

1111 = Bit 15

End of Sequence flag. This bit indicates whether the Control Write Sequencer should stop after executing this step.

0 = Not end of sequence

1 = End of sequence (Stop the sequencer after this step).

Time delay after executing this step.

Total time per step (including execution)

= 62.5µs × (2 WSEQ_DELAY + 8)

Table 131 Write Sequencer Control - Programming a Sequence


229

WM8958

Pre-Production

Note that a ‘Dummy’ write can be inserted into a control sequence by commanding the sequencer to write a value of 0 to bit 0 of Register R255 (00FFh). This is effectively a write to a non-existent register location. This can be used in order to create placeholders ready for easy adaptation of a control sequence. For example, a sequence could be defined to power-up a mono signal path from

DACL to headphone, with a ‘dummy’ write included to leave space for easy modification to a stereo signal path configuration. Dummy writes can also be used in order to implement additional time delays between register writes. Dummy writes are included in both of the Headphone start-up sequences - see Table 132 and Table 133.

In summary, the Control Register to be written is set by the WSEQ_ADDRn field. The data bits that are written are determined by a combination of WSEQ_DATA_STARTn, WSEQ_DATA_WIDTHn and

WSEQ_DATAn. This is illustrated below for an example case of writing to the VMID_SEL field within

Register R1 (0001h).

In this example, the Start Position is bit 01 (WSEQ_DATA_STARTn = 0001b) and the Data width is 2 bits (WSEQ_DATA_WIDTHn = 0001b). With these settings, the Control Write Sequencer would update the Control Register R1 [2:1] with the contents of WSEQ_DATAn [1:0]. w

Figure 80 Control Write Sequencer Example

DEFAULT SEQUENCES

When the WM8958 is powered up, a number of Control Write Sequences are available through default settings in the sequencer memory locations. The pre-programmed default settings include

Start-Up and Shut-Down sequences for each of the output drivers. Note that the default sequences do not include audio signal path or gain setting configuration; this must be implemented prior to scheduling any of the default Start-Up sequences.

The entire sequencer memory may be programmed to users’ own settings at any time, as described in “Programming a Sequence”. Users’ own settings remain in memory regardless of WSEQ_ENA, and are not affected by software resets (i.e. writing to Register R0). However, any non-default sequences are lost when the device is powered down.

The following default control sequences are provided:

1. Headphone Cold Start-Up - This sequence powers up the headphone driver and charge pump. It commands the DC Servo to perform offset correction. It enables the master bias required for analogue functions. This sequence is intended for enabling the headphone output after initial power-on, when DC offset correction has not previously been run.


230

Pre-Production

WSEQ

INDEX

0 (00h)

REGISTER

ADDRESS

R57 (0039h)

WM8958

2. Headphone Warm Start-Up - This sequence is similar to the Headphone Cold Start-Up, but does not include the DC Servo operation. This sequence is intended for fast enabling of the headphone output when DC offset correction has previously been scheduled and provided the analogue gain settings have not been updated since scheduling the DC offset correction.

3. Speaker Start-Up - This sequence powers up the stereo speaker driver. It also enables the master bias required for analogue functions.

4. Earpiece Start-Up - This sequence powers up the earpiece driver. It also enables the master bias required for analogue functions. The soft-start VMID option is used in order to suppress pops when the driver is enabled. This sequence is intended for enabling the earpiece driver when the master bias has not previously been enabled.

5. Line Output Start-Up - This sequence powers up the line outputs. Active discharge of the line outputs is selected, followed by the soft-start VMID enable, followed by selection of the master bias and un-muting of the line outputs. This sequence is intended for enabling the line drivers when the master bias has not previously been enabled.

6. Speaker and Headphone Fast Shut-Down - This sequence implements a fast shutdown of the speaker and headphone drivers. It also disables the DC Servo and charge pump circuits, and disables the analogue bias circuits using the soft-start (ramp) feature. This sequence is intended as a shut-down sequence when only the speaker or headphone drivers are enabled.

7. Generic Shut-Down - This sequence shuts down all of the WM8958 output drivers, DC Servo, charge pump and analogue bias circuits. It is similar to the Fast Shut-Down sequence, with the additional control of the earpiece and line output drivers. Active discharge of the line outputs is included and all drivers are disabled as part of this sequence.

Specific details of each of these sequences is provided below.

Headphone Cold Start-Up

The Headphone Cold Start-Up sequence is initiated by writing 8100h to Register 272 (0110h). This single operation starts the Control Write Sequencer at Index Address 0 (00h) and executes the sequence defined in Table 132.

This sequence takes approximately 296ms to run.

WIDTH START DATA DELAY EOS DESCRIPTION

5 bits Bit 2 1Bh 0h 0b

1 (01h)

2 (02h)

3 (03h)

4 (04h)

5 (05h)

R1 (0001h)

R76 (004Ch)

R1 (0001h)

R96 (0060h)

R84 (0054h)

3 bits

1 bit

2 bits

5 bits

6 bits

Bit 0

Bit 15

Bit 8

Bit 1

Bit 0

03h

01h

03h

11h

33h

9h

6h

0h

0h

Ch

0b

0b

0b

0b

0b

STARTUP_BIAS_ENA = 1

VMID_BUF_ENA = 1

VMID_RAMP[1:0] = 11b

(delay = 0.5625ms)

BIAS_ENA = 1

VMID_SEL[1:0] = 01b

(delay = 32.5ms)

CP_ENA = 1

(delay = 4.5ms)

HPOUT1R_ENA = 1

HPOUT1L_ENA = 1

(delay = 0.5625ms)

HPOUT1R_DLY = 1

HPOUT1L_DLY = 1

(delay = 0.5625ms)

DCS_ENA_CHAN_0 = 1

DCS_ENA_CHAN_1 = 1

DCS_TRIG_STARTUP_0 = 1

DCS_TRIG_STARTUP_1 = 1

(delay = 256.5ms) w PP, August 2012, Rev 3.4

231

WM8958

WSEQ

INDEX

6 (06h)

7 (07h)

REGISTER

ADDRESS

R255

(00FFh)

R96 (0060h)

Pre-Production


1 bit

6 bits

Bit 0

Bit 2

00h

3Bh

0h

0h

0b

1b

Dummy Write for expansion

(delay = 0.5625ms)

HPOUT1R_OUTP = 1

HPOUT1R_RMV_SHORT =1

HPOUT1_DLY = 1

HPOUT1L_OUTP = 1


(delay = 0.5625ms)

Table 132 Headphone Cold Start-Up Default Sequence

WSEQ

INDEX

8 (08h)

9 (09h)

10 (0Ah)

11 (0Bh)

12 (0Ch)

13 (0Dh)

14 (0Eh)

REGISTER

ADDRESS

R57 (0039h)

Headphone Warm Start-Up

The Headphone Warm Start-Up sequence can be initiated by writing 8108h to Register 272 (0110h).

This single operation starts the Control Write Sequencer at Index Address 8 (08h) and executes the sequence defined in Table 133.




R1 (0001h)

R76 (004Ch)

R1 (0001h)

R96 (0060h)

R84 (0054h)

R255

(00FFh)

15 (0Fh) R96 (0060h)

3 bits

1 bits

2 bits

5 bits

2 bits

1 bits

6 bits

Bit 0

Bit 15

Bit 8

Bit 1

Bit 0

Bit 0

Bit 2

03h

01h

03h

11h

03h

00h

3Bh

9h

6h

0h

0h

0h

0h

0h

0b

0b

0b

0b

0b

0b

1b


VMID_BUF_ENA = 1


(delay = 0.5625ms)

BIAS_ENA = 1

VMID_SEL[1:0] = 01b

(delay = 32.5ms)

CP_ENA = 1

(delay = 4.5ms)

HPOUT1R_ENA = 1

HPOUT1L_ENA = 1

(delay = 0.5625ms)

HPOUT1R_DLY = 1

HPOUT1L_DLY = 1

(delay = 0.5625ms)

DCS_ENA_CHAN_0 = 1

DCS_ENA_CHAN_1 = 1

(delay = 0.5625ms)

Dummy Write for expansion

(delay = 0.5625ms)

HPOUT1R_OUTP = 1

HPOUT1R_RMV_SHORT =1

HPOUT1_DLY = 1

HPOUT1L_OUTP = 1


(delay = 0.5625ms)

Table 133 Headphone Warm Start-Up Default Sequence w PP, August 2012, Rev 3.4

232

Pre-Production

WSEQ

INDEX

16 (10h)

REGISTER

ADDRESS

R57 (39h)

WM8958

Speaker Start-Up

The Speaker Start-Up sequence can be initiated by writing 8110h to Register 272 (0110h). This single operation starts the Control Write Sequencer at Index Address 16 (10h) and executes the sequence defined in Table 134.




17 (11h)

18 (12h)

R1 (01h)

R1 (01h)

3 bits

2 bits

Bit 0

Bit 12

03h

03h

9h

0h

0b

1b


VMID_BUF_ENA = 1


(delay = 0.5625ms)

BIAS_ENA = 1

VMID_SEL[1:0] = 01b

(delay = 32.5ms)

SPKOUTL_ENA = 1

SPKOUTR_ENA = 1

(delay = 0.5625ms)

Table 134 Speaker Start-Up Default Sequence

WSEQ

INDEX

19 (13h)

20 (14h)

21 (15h)

22 (16h)

23 (17h)

24 (18h)

REGISTER

ADDRESS

R57 (39h)

R56 (38h)

R31 (1Fh)

R1 (01h)

R1 (01h)

R57 (39h)

Earpiece Start-Up

The Earpiece Start-Up sequence can be initiated by writing 8113h to Register 272 (0110h). This single operation starts the Control Write Sequencer at Index Address 19 (13h) and executes the sequence defined in Table 135.



6 bits

1 bit

1 bit

1 bit

3 bits

1 bit

Bit 1

Bit 6

Bit 5

Bit 11

Bit 0

Bit 1

27h

01h

00h

01h

03h

00h

0h

0h

0h

0h

Ch

0h

0b

0b

1b

0b

0b

0b

BIAS_SRC = 1


VMID_BUF_ENA = 1


(delay = 0.5625ms)

HPOUT2_IN_ENA = 1

(delay = 0.5625ms)

HPOUT2_MUTE = 0

(delay = 0.5625ms)

HPOUT2_ENA = 1

(delay = 0.5625ms)

BIAS_ENA = 1

VMID_SEL[1:0] = 01b

(delay = 256.5ms)

BIAS_SRC = 0

(delay = 0.5625ms)

Table 135 Earpiece Start-Up Default Sequence w PP, August 2012, Rev 3.4

233

WM8958

WSEQ

INDEX

25 (19h)

26 (1Ah)

27 (1Bh)

28 (1Ch)

29 (1Dh)

30 (1Eh)

31 (1Fh)

32 (20h)

33 (21h)

REGISTER

ADDRESS

R56 (38h)

Pre-Production

Line Output Start-Up

The Line Output Start-Up sequence can be initiated by writing 8119h to Register 272 (0110h). This single operation starts the Control Write Sequencer at Index Address 25 (19h) and executes the sequence defined in Table 136.



2 bits Bit 4 03h 0h 0b

R57 (39h)

R56 (38h)

R3 (03h)

R56 (38h)

R1 (01h)

R57 (39h)

R30 (1Eh)

R30 (1Eh)

6 bits

1 bit

4 bits

2 bits

3 bits

1 bit

2 bits

2 bits

Bit 1

Bit 7

Bit 10

Bit 4

Bit 0

Bit 1

Bit 5

Bit 1

27h

01h

0Fh

00h

03h

00h

00h

00h

0h

0h

0h

0h

Dh

0h

0h

0h

0b

0b

0b

0b

0b

0b

0b

1b

LINEOUT2_DISCH = 1

LINEOUT1_DISCH = 1

(delay = 0.5625ms)

BIAS_SRC = 1


VMID_BUF_ENA = 1


(delay = 0.5625ms)

LINEOUT_VMID_BUF_ENA = 1

(delay = 0.5625ms)

LINEOUT2P_ENA = 1

LINEOUT2N_ENA = 1

LINEOUT1P_ENA = 1

LINEOUT1N_ENA = 1

(delay = 0.5625ms)

LINEOUT2_DISCH = 0

LINEOUT1_DISCH = 0

(delay = 0.5625ms)

BIAS_ENA = 1

VMID_SEL = 01b

(delay = 512.5ms)

BIAS_SRC = 0

(delay = 0.5625ms)

LINEOUT1P_MUTE = 0

LINEOUT1N_MUTE = 0

(delay = 0.5625ms)

LINEOUT2P_MUTE = 0

LINEOUT2N_MUTE = 0

(delay = 0.5625ms)

Table 136 Line Output Start-Up Default Sequence w PP, August 2012, Rev 3.4

234

Pre-Production

WSEQ

INDEX

34 (22h)

REGISTER

ADDRESS

R96 (60h)

WM8958

Speaker and Headphone Fast Shut-Down

The Speaker and Headphone Fast Shut-Down sequence can be initiated by writing 8122h to Register

272 (0110h). This single operation starts the Control Write Sequencer at Index Address 34 (22h) and executes the sequence defined in Table 137.



7 bits Bit 1 00h 0h 0b

35 (23h)

36 (24h)

37 (25h)

38 (26h)

39 (27h)

40 (28h)

41 (29h)

R84 (54h)

R1 (01h)

R76 (4Ch)

R1 (01h)

R57 (39h)

R1 (01h)

R57 (39h)

2 bits

2 bits

1 bit

2 bits

6 bits

3 bits

6 bits

Bit 0

Bit 8

Bit 15

Bit 12

Bit 1

Bit 0

Bit 1

00h

00h

00h

00h

37h

00h

00h

0h

0h

0h

0h

0h

9h

0h

0b

0b

0b

0b

0b

0b

1b

HPOUT1R_DLY = 0

HPOUT1R_OUTP = 0


HPOUT1L_DLY = 0

HPOUT1L_OUTP = 0


(delay = 0.5625ms)

DCS_ENA_CHAN_0 = 0

DCS_ENA_CHAN_1 = 0

(delay = 0.5625ms)

HPOUT1R_ENA = 0

HPOUT1L_ENA = 0

(delay = 0.5625ms)

CP_ENA = 0

(delay = 0.5625ms)

SPKOUTL_ENA = 0

SPKOUTR_ENA = 0

(delay = 0.5625ms)

BIAS_SRC = 1


VMID_BUF_ENA = 1


(delay = 0.5625ms)

BIAS_ENA = 0

VMID_SEL = 00b

(delay = 32.5ms)

BIAS_SRC = 0


VMID_BUF_ENA = 0


(delay = 0.5625ms)

Table 137 Speaker and Headphone Fast Shut-Down Default Sequence w PP, August 2012, Rev 3.4

235

WM8958

WSEQ

INDEX

42 (2Ah)

REGISTER

ADDRESS

R31 (1Fh)

43 (2Bh)

44 (2Ch)

45 (2Dh)

46 (2Eh)

47 (2Fh)

48 (30h)

49 (31h)

50 (32h)

51 (33h)

52 (34h)

53 (35h)

54 (36h)

55 (37h)

R30 (1Eh)

R96 (60h)

R84 (54h)

R1 (01h)

R76 (4Ch)

R1 (01h)

R57 (39h)

R1 (01h)

R1 (01h)

R56 (38h)

R55 (37h)

R56 (38h)

R3 (03h)

Pre-Production

Generic Shut-Down

The Generic Shut-Down sequence can be initiated by writing 812Ah to Register 272 (0110h). This single operation starts the Control Write Sequencer at Index Address 42 (2Ah) and executes the sequence defined in Table 138.



1 bit

6 bits

7 bits

2 bits

2 bits

1 bit

2 bits

6 bits

3 bits

1 bit

2 bits

1 bit

1 bit

4 bits

Bit 5

Bit 1

Bit 1

Bit 0

Bit 8

Bit 15

Bit 12

Bit 1

Bit 0

Bit 11

Bit 4

Bit 0

Bit 6

Bit 10

01h

33h

00h

00h

00h

00h

00h

17h

00h

00h

03h

01h

00h

00h

0h

0h

0h

0h

0h

0h

0h

0h

Dh

0h

0h

0h

0h

0h

0b

0b

0b

0b

0b

0b

0b

0b

0b

0b

0b

0b

0b

0b

HPOUT2_MUTE = 1

(delay = 0.5625ms)

LINEOUT2P_MUTE = 1

LINEOUT2N_MUTE = 1

LINEOUT1P_MUTE = 1

LINEOUT1N_MUTE = 1

(delay = 0.5625ms)

HPOUT1R_DLY = 0

HPOUT1R_OUTP = 0


HPOUT1L_DLY = 0

HPOUT1L_OUTP = 0


(delay = 0.5625ms)

DCS_ENA_CHAN_0 = 0

DCS_ENA_CHAN_1 = 0

(delay = 0.5625ms)

HPOUT1R_ENA = 0

HPOUT1L_ENA = 0

(delay = 0.5625ms)

CP_ENA = 0

(delay = 0.5625ms)

SPKOUTL_ENA = 0

SPKOUTR_ENA = 0

(delay = 0.5625ms)

BIAS_SRC = 1


VMID_BUF_ENA = 1


(delay = 0.5625ms)

BIAS_ENA = 0

VMID_SEL = 00b

(delay = 512.5ms)

HPOUT2_ENA = 0

(delay = 0.5625ms)

LINEOUT2_DISCH = 1

LINEOUT1_DISCH = 1

(delay = 0.5625ms)

VROI = 1

(delay = 0.5625ms)

HPOUT2_IN_ENA =0

(delay = 0.5625ms)

LINEOUT2P_ENA = 0

LINEOUT2N_ENA = 0

LINEOUT1P_ENA = 0

LINEOUT1N_ENA = 0

(delay = 0.5625ms) w PP, August 2012, Rev 3.4

236

Pre-Production

WSEQ

INDEX

56 (38h)

REGISTER

ADDRESS

R56 (38h)

WIDTH START DATA DELAY

1 bit Bit 7 00h 0h

57 (39h)

58 (3Ah)

R55 (37h)

R57 (39h)

1 bit

6 bits

Bit 0

Bit 1

00h

00h

0h

0h

WM8958

DESCRIPTION EOS

0b

0b

1b

LINEOUT_VMID_BUF_ENA = 0

(delay = 0.5625ms)

VROI = 0

(delay = 0.5625ms)

BIAS_SRC = 0


VMID_BUF_ENA = 0


(delay = 0.5625ms)

Table 138 Generic Shut-Down Default Sequence

POP SUPPRESSION CONTROL

The WM8958 incorporates a number of features, including Wolfson’s SilentSwitch™ technology, designed to suppress pops normally associated with Start-Up, Shut-Down or signal path control. To achieve maximum benefit from these features, careful attention is required to the sequence and timing of these controls. Note that, under the recommended usage conditions of the WM8958, these features will be configured by running the default Start-Up and Shut-Down sequences as described in the “Control Write Sequencer” section. In these cases, the user does not need to set these register fields directly.

The Pop Suppression controls relating to the Headphone / Line Output drivers are described in the

“Analogue Output Signal Path” section.

Additional bias controls, also pre-programmed into Control Write Sequencer, are described in the

“Reference Voltages and Master Bias” section.

DISABLED LINE OUTPUT CONTROL

The line outputs are biased to VMID in normal operation. To avoid audible pops caused by a disabled signal path dropping to AGND, the WM8958 can maintain these connections at VMID when the relevant output stage is disabled. This is achieved by connecting a buffered VMID reference to the output.

The buffered VMID reference is enabled by setting VMID_BUF_ENA. The output resistance is selectable, using the VROI register bit.

Note that, if LINEOUTn_DISCH=1 (see Table 140), then the respective output will be discharged to

AGND, and will not be connected to VMID.


ADDRESS

R55 (0037h)

Additional

Control

R57 (0039h)

AntiPOP (2)

0

3

VROI

VMID_BUF

_ENA

0

0

Buffered VMID to Analogue Line Output

Resistance (Disabled Outputs)

0 = 20k  from buffered VMID to output

1 = 500  from buffered VMID to output

VMID Buffer Enable

0 = Disabled

1 = Enabled (provided VMID_SEL > 00)

Table 139 Disabled Line Output Control w PP, August 2012, Rev 3.4

237

WM8958 w

Pre-Production

LINE OUTPUT DISCHARGE CONTROL

The line output paths can be actively discharged to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known output stage condition prior to enabling the soft-start

VMID reference voltage. This is also desirable in shut-down to prevent the external connections from being affected by the internal circuits.

The line outputs LINEOUT1P and LINEOUT1N are discharged to AGND by setting

LINEOUT1_DISCH. The line outputs LINEOUT2P and LINEOUT2N are discharged to AGND by setting LINEOUT2_DISCH.

The discharge resistance is dependent upon the respective LINEOUTn_ENA bit, and also according to the VROI bit (see Table 139). The discharge resistance is noted in the “Electrical Characteristics” section.


ADDRESS

R56 (0038h)

AntiPOP (1)

5 LINEOUT1_DISC

H

0

4 LINEOUT2_DISC

H

0

Discharges LINEOUT1P and

LINEOUT1N outputs

0 = Not active

1 = Actively discharging LINEOUT1P and LINEOUT1N

Discharges LINEOUT2P and

LINEOUT2N outputs

0 = Not active


Table 140 Line Output Discharge Control

VMID REFERENCE DISCHARGE CONTROL

The VMID reference can be actively discharged to AGND through internal resistors. This is desirable at start-up in order to achieve a known initial condition prior to enabling the soft-start VMID reference; this ensures maximum suppression of audible pops associated with start-up. VMID is discharged by setting VMID_DISCH.

REGISTER

ADDRESS

R57 (0039h)

AntiPOP (2)


0 VMID_DISCH 0

DESCRIPTION

Connects VMID to ground

0 = Disabled

1 = Enabled

Table 141 VMID Reference Discharge Control

INPUT VMID CLAMPS

The analogue inputs can be clamped to Vmid using the INPUTS_CLAMP bit described below. This allows pre-charging of the input AC coupling capacitors during power-up. Note that all eight inputs are clamped using the same control bit.

Note that INPUTS_CLAMP must be set to 0 when the analogue input signal paths are in use.

REGISTER

ADDRESS

R21 (15h)

Input Mixer (1)

6 INPUTS_CLAMP 0

DESCRIPTION

Input pad VMID clamp

0 = Clamp de-activated

1 = Clamp activated

Table 142 Input VMID Clamps


238

Pre-Production

WM8958

LDO REGULATORS

The WM8958 provides two integrated Low Drop-Out Regulators (LDOs). These are provided to generate the appropriate power supplies for internal circuits, simplifying and reducing the requirements for external supplies and associated components. A reference circuit powered by

AVDD2 ensures the accuracy of the LDO regulator voltage settings.

Note that the integrated LDOs are only intended for generating the AVDD1 and DCVDD supply rails for the WM8958; they are not suitable for powering any additional or external loads.

LDO1 is intended for generating AVDD1 - the primary analogue power domain of the WM8958. LDO1 is powered by LDO1VDD and is enabled when a logic ‘1’ is applied to the LDO1ENA pin. The logic level is determined with respect to the DBVDD1 voltage domain. The LDO1 start-up time is dependent on the external AVDD1 and VREFC capacitors; the start-up time is noted in the “Electrical

Characteristics” section for the recommended external component conditions.

When LDO1 is enabled, the output voltage is controlled by the LDO1_VSEL register field. Note that the LDO1 voltage difference LDO1VDD - AVDD1 must be higher than the LDO1 Drop-Out voltage

(see “Electrical Characteristics”).

When LDO1 is disabled (by applying a logic ‘0’ to the LDO1ENA pin), the output can be left floating or can be actively discharged, depending on the LDO1_DISCH control bit.

It is possible to supply AVDD1 from an external supply. If AVDD1 is supplied externally, then LDO1 should be disabled, and the LDO1 output left floating (LDO1DISCH = 0). Note that the LDO1VDD voltage must be greater than or equal to AVDD1; this ensures that there is no leakage path through the LDO for the external supply.

Note that the WM8958 can operate with AVDD1 tied to 0V; power consumption may be reduced, but the analogue audio functions will not be supported.

LDO2 is intended for generating the DCVDD power domain which supplies the digital core functions on the WM8958. LDO2 is powered by DBVDD1 and is enabled when a logic ‘1’ is applied to the

LDO2ENA pin. The logic level is determined with respect to the DBVDD1 voltage domain. The LDO2 start-up time is dependent on the external DCVDD and VREFC capacitors; the start-up time is noted in the “Electrical Characteristics” section for the recommended external component conditions.

When LDO2 is enabled, the output voltage is controlled by the LDO2_VSEL register field.

When LDO2 is disabled (by applying a logic ‘0’ to the LDO2ENA pin), the output can be left floating or can be actively discharged, depending on the LDO2_DISCH control bit.

It is possible to supply DCVDD from an external supply. If DCVDD is supplied externally, the

LDO2ENA and LDO2DISCH bits should be set to 0. Note that the DBVDD1 voltage must be greater than or equal to DCVDD; this ensures that there is no leakage path through the LDO for the external supply.

An internal pull-down resistor is enabled by default on the LDO1ENA and LDO2ENA pins. These pulldown resistors can be configured using the register bits described in Table 143.

Decoupling capacitors should be connected to the voltage reference pin, VREFC, and also to the

LDO outputs, AVDD1 and DCVDD. See “Applications Information” for further details.

The LDO Regulator connections and controls are illustrated in Figure 81. The register controls are defined in Table 143. w PP, August 2012, Rev 3.4

239

WM8958

VREFC

Pre-Production

AVDD2

Voltage

Reference

LDO1_VSEL[2:0]

LDO1_DISCH

LDO1

Analogue Supply

LDO2_VSEL[1:0]

LDO2_DISCH

Digital Core Supply

LDO2 w

LDO1VDD LDO1ENA AVDD1

Figure 81 LDO Regulators

REGISTER

ADDRESS

R59 (003Bh)

LDO 1

3:1 LDO1_VSEL [2:0]

R60

(003Ch)

LDO 2

R1825

(0721h)

Pull Control

(2)

0

2:1

0

6

4

LDO1_DISCH

LDO2_VSEL [1:0]

LDO2_DISCH

LDO2ENA_PD

LDO1ENA_PD

DBVDD1 LDO2ENA DCVDD

110

1

10

1

1

1

DESCRIPTION

LDO1 Output Voltage Select

2.4V to 3.1V in 100mV steps

000 = 2.4V

001 = 2.5V

010 = 2.6V

011 = 2.7V

100 = 2.8V

101 = 2.9V

110 = 3.0V

111 = 3.1V

LDO1 Discharge Select

0 = LDO1 floating when disabled

1 = LDO1 discharged when disabled

LDO2 Output Voltage Select


00 = Reserved

01 = 1.1V

10 = 1.2V

11 = 1.3V

LDO2 Discharge Select



LDO2ENA Pull-down enable

0 = Disabled

1 = Enabled

LDO1ENA Pull-down enable

0 = Disabled

1 = Enabled

Table 143 LDO Regulator Control


240

Pre-Production

WM8958

REFERENCE VOLTAGES AND MASTER BIAS

This section describes the analogue reference voltage and bias current controls. It also describes the

VMID soft-start circuit for pop suppressed start-up and shut-down.

The analogue circuits in the WM8958 require a mid-rail analogue reference voltage, VMID. This reference is generated from AVDD1 via a programmable resistor chain. Together with the external

VMID decoupling capacitor, the programmable resistor chain determines the charging characteristic on VMID. This is controlled by VMID_SEL[1:0], and can be used to optimise the reference for normal operation or low power standby as described in Table 144.

A buffered mid-rail reference voltage is provided. This is required for the single-ended configuration of the Input PGAs, and also for direct signal paths from the input pins to the Input Mixers, Output Mixers or Speaker Mixers. These requirements are noted in the relevant “Analogue Input Signal Path” and

“Analogue Output Signal Path” sections. The buffered mid-rail reference is enabled by setting the

VMID_BUF_ENA register bit.

The analogue circuits in the WM8958 require a bias current. The normal bias current is enabled by setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also.

REGISTER

ADDRESS

R1 (0001h)

Power

Management

(1)

R57 (0039h)

AntiPOP (2)

2:1

0

3

VMID_SEL

[1:0]

BIAS_ENA

VMID_BUF_

ENA

00

0

0

DESCRIPTION

VMID Divider Enable and Select

00 = VMID disabled (for OFF mode)

01 = 2 x 40k  divider (for normal operation)

10 = 2 x 240k  divider (for low power standby)

11 = Reserved

Enables the Normal bias current generator (for all analogue functions)

0 = Disabled

1 = Enabled

VMID Buffer Enable

0 = Disabled


Table 144 Reference Voltages and Master Bias Enable

A pop-suppressed start-up requires VMID to be enabled smoothly, without the step change normally associated with the initial stage of the VMID capacitor charging. A pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal path prior to the VMID reference voltage being applied. The WM8958 incorporates pop-suppression circuits which address these requirements.

An alternate bias current source (Start-Up Bias) is provided for pop-free start-up; this is enabled by the STARTUP_BIAS_ENA register bit. The start-up bias is selected (in place of the normal bias) using the BIAS_SRC bit. It is recommended that the start-up bias is used during start-up, before switching back to the higher quality, normal bias.

A soft-start circuit is provided in order to control the switch-on of the VMID reference. The soft-start control circuit offers two slew rates for enabling the VMID reference; these are selected and enabled by VMID_RAMP. When the soft-start circuit is enabled prior to enabling VMID_SEL, the reference voltage rises smoothly, without the step change that would otherwise occur. It is recommended that the soft-start circuit and the output signal path be enabled before VMID is enabled by VMID_SEL.

A soft shut-down is provided, using the soft-start control circuit and the start-up bias current generator. The soft shut-down of VMID is achieved by setting VMID_RAMP, STARTUP_BIAS_ENA and BIAS_SRC to select the start-up bias current and soft-start circuit prior to setting VMID_SEL=00.

Note that, if the VMID_RAMP function is enabled for soft start-up or soft shut-down then, after setting

VMID_SEL = 00 to disable VMID, the soft-start circuit must be reset before re-enabling VMID. The soft-start circuit is reset by setting VMID_RAMP = 00. After resetting the soft-start circuit, the

VMID_RAMP register may be updated to the required setting for the next VMID transition.

The VMID soft-start register controls are defined in Table 145. w PP, August 2012, Rev 3.4

241

WM8958

REGISTER

ADDRESS

R57 (0039h)

AntiPOP (2)


6:5

2

1

Pre-Production

VMID_RAMP [1:0]

STARTUP_BIAS_

ENA

BIAS_SRC

10

0

1

DESCRIPTION

VMID soft start enable / slew rate control

00 = Normal slow start

01 = Normal fast start

10 = Soft slow start

11 = Soft fast start

If VMID_RAMP = 1X is selected for

VMID start-up or shut-down, then the soft-start circuit must be reset by setting VMID_RAMP=00 after VMID is disabled, before VMID is re-enabled.

VMID is disabled / enabled using the

VMID_SEL register.

Enables the Start-Up bias current generator

0 = Disabled

1 = Enabled

Selects the bias current source

0 = Normal bias

1 = Start-Up bias

Table 145 Soft Start Control w PP, August 2012, Rev 3.4

242

Pre-Production

WM8958

POWER MANAGEMENT

The WM8958 has control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise, it is important to enable or disable functions in the correct order. See “Control Write Sequencer” for details of recommended control sequences.

REGISTER

ADDRESS

R1 (0001h)

Power

Management

(1)

R2 (0002h)

Power

Management

(2)

13 SPKOUTR_ENA

12 SPKOUTL_ENA

11 HPOUT2_ENA

9

8

5

4

2:1 VMID_SEL

[1:0]

0

HPOUT1L_ENA

HPOUT1R_ENA

MICB2_ENA

MICB1_ENA

BIAS_ENA

14 TSHUT_ENA

13 TSHUT_OPDIS

11 OPCLK_ENA

9 MIXINL_ENA

0

0

0

0

0

0

0

00

0

1

1

0

0

DESCRIPTION

SPKMIXR Mixer, SPKRVOL PGA and

SPKOUTR Output Enable

0 = Disabled

1 = Enabled

SPKMIXL Mixer, SPKLVOL PGA and

SPKOUTL Output Enable

0 = Disabled

1 = Enabled

HPOUT2 and HPOUT2MIX Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

VMID Divider Enable and Select


01 = 2 x 40k  divider (Normal mode)

10 = 2 x 240k  divider (Standby mode)

11 = Reserved

Enables the Normal bias current generator (for all analogue functions)

0 = Disabled

1 = Enabled

Thermal Sensor Enable

0 = Disabled

1 = Enabled

Thermal Shutdown Control

(Causes audio outputs to be disabled if an over-temperature occurs. The thermal sensor must also be enabled.)

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Left Input Mixer Enable

(Enables MIXINL and RXVOICE input to

MIXINL)

0 = Disabled

1 = Enabled


w

243

WM8958 w

REGISTER

ADDRESS

R3 (0003h)

Power

Management

(3)

Pre-Production

DESCRIPTION

8

7

6

5

4

13

12

11

10

9

8

7

6

5

MIXINR_ENA

IN2L_ENA

IN1L_ENA

IN2R_ENA

IN1R_ENA

LINEOUT1N_ENA

LINEOUT1P_ENA

LINEOUT2N_ENA

LINEOUT2P_ENA

SPKRVOL_ENA

SPKLVOL_ENA

MIXOUTLVOL_E

NA

MIXOUTRVOL_E

NA

MIXOUTL_ENA

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Right Input Mixer Enable

(Enables MIXINR and RXVOICE input to

MIXINR)

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


LINEOUT1NMIX Enable

0 = Disabled

1 = Enabled


LINEOUT1PMIX Enable

0 = Disabled

1 = Enabled


LINEOUT2NMIX Enable

0 = Disabled

1 = Enabled


LINEOUT2PMIX Enable

0 = Disabled

1 = Enabled

SPKMIXR Mixer and SPKRVOL PGA

Enable

0 = Disabled

1 = Enabled

Note that SPKMIXR and SPKRVOL are also enabled when SPKOUTR_ENA is set.

SPKMIXL Mixer and SPKLVOL PGA

Enable

0 = Disabled

1 = Enabled

Note that SPKMIXL and SPKLVOL are also enabled when SPKOUTL_ENA is set.

MIXOUTL Left Volume Control Enable

0 = Disabled

1 = Enabled

MIXOUTR Right Volume Control Enable

0 = Disabled

1 = Enabled


0 = Disabled


244

Pre-Production w

REGISTER

ADDRESS

4 MIXOUTR_ENA

R4 (0004h)

Power

Management

(4)

13 AIF2ADCL_ENA

12 AIF2ADCR_ENA

11 AIF1ADC2L_ENA

9 AIF1ADC1L_ENA

8 AIF1ADC1L_ENA

5 DMIC2L_ENA

4 DMIC2R_ENA

3 DMIC1L_ENA

2 DMIC1R_ENA

1 ADCL_ENA

0 ADCR_ENA

R5 (0005h)

Power

Management

13 AIF2DACL_ENA

0

0

0

0

10 AIF1ADC2R_ENA 0

0

0

0

0

0

0

0

0

0

WM8958

DESCRIPTION

1 = Enabled

MIXOUTR Right Output Mixer Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled



0 = Disabled

1 = Enabled


Enable AIF1ADC2 (Left) output path

(AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1ADC2 (Right) output path

(AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1ADC1 (Left) output path

(AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Enable AIF1ADC1 (Right) output path

(AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Digital microphone DMICDAT2 Left channel enable

0 = Disabled

1 = Enabled

Digital microphone DMICDAT2 Right channel enable

0 = Disabled

1 = Enabled

Digital microphone DMICDAT1 Left channel enable

0 = Disabled

1 = Enabled

Digital microphone DMICDAT1 Right channel enable

0 = Disabled

1 = Enabled

Left ADC Enable

0 = ADC disabled

1 = ADC enabled

Right ADC Enable

0 = ADC disabled

1 = ADC enabled


0 = Disabled

1 = Enabled


245

WM8958 w

REGISTER

ADDRESS

(5)

R76 (004Ch)

Charge Pump

(1)

R84 (0054h)

DC Servo (1)

R272 (0110h)

Write

Sequencer

Ctrl (1)

R512 (0200h)

AIF 1 Clocking

(1)

R516 (0204h)

AIF 2 Clocking

(1)

R520 (0208h)

Clocking (1)

Pre-Production

DESCRIPTION

12 AIF2DACR_ENA 0

11

10

9

8

3

2

1

0

15

1

0

8

0

0

4

AIF1DAC2L_ENA

AIF1DAC2R_ENA

AIF1DAC1L_ENA

AIF1DAC1R_ENA

DAC2L_ENA

DAC2R_ENA

DAC1L_ENA

DAC1R_ENA

CP_ENA

DCS_ENA_CHAN

_1

DCS_ENA_CHAN

_0

WSEQ_ENA

AIF1CLK_ENA

AIF2CLK_ENA

TOCLK_ENA

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


0 = Disabled

1 = Enabled


Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1DAC2 (Right) input path

(AIF1, Timeslot 1)

0 = Disabled

1 = Enabled


Timeslot 0)

0 = Disabled

1 = Enabled

Enable AIF1DAC1 (Right) input path

(AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Left DAC2 Enable

0 = DAC disabled

1 = DAC enabled

Right DAC2 Enable

0 = DAC disabled

1 = DAC enabled

Left DAC1 Enable

0 = DAC disabled

1 = DAC enabled

Right DAC1 Enable

0 = DAC disabled

1 = DAC enabled

Enable charge-pump digits

0 = Disable

1 = Enable


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Write Sequencer Enable.

0 = Disabled

1 = Enabled

AIF1CLK Enable

0 = Disabled

1 = Enabled

AIF2CLK Enable

0 = Disabled

1 = Enabled

Slow Clock (TOCLK) Enable

0 = Disabled

1 = Enabled



246

Pre-Production

REGISTER

ADDRESS

3 AIF1DSPCLK_EN

A

2 AIF2DSPCLK_EN

A

1 SYSDSPCLK_EN

A

R544 (0220h)

FLL1 Control

(1)

0 FLL1_ENA

R576 (0240h)

FLL2 Control

(1)

0 FLL2_ENA

0

0

0

0

0

WM8958

DESCRIPTION


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

FLL1 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the

FLL1 enable sequence, ie. after the other

FLL registers have been configured.

FLL2 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the

FLL2 enable sequence, ie. after the other

FLL registers have been configured.

Table 146 Power Management w PP, August 2012, Rev 3.4

247

WM8958

Pre-Production

THERMAL SHUTDOWN

The WM8958 incorporates a temperature sensor which detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition. The temperature sensor can be configured to automatically disable the audio outputs of the WM8958 in response to an overtemperature condition (approximately 150ºC).

The temperature status can be output directly on a GPIO pin, as described in the “General Purpose

Input/Output” section. The temperature sensor can also be used to generate Interrupt events, as described in the “Interrupts” section. The GPIO and Interrupt functions can be used to indicate either a Warning Temperature event or the Shutdown Temperature event.

The temperature sensor is enabled by setting the TSHUT_ENA register bit. When the TSHUT_OPDIS is also set, then a device over-temperature condition will cause the speaker outputs (SPKOUTL and

SPKOUTR) of the WM8958 to be disabled; this response is likely to prevent any damage to the device attributable to the large currents of the output drivers.

Note that, to prevent pops and clicks, TSHUT_ENA and TSHUT_OPDIS should only be updated whilst the speaker and headphone outputs are disabled.


ADDRESS

R2 (0002h)

Power

Management

(2)

14

13

TSHUT_ENA

TSHUT_OPDIS

1

1

Thermal sensor enable

0 = Disabled

1 = Enabled

Thermal shutdown control


0 = Disabled

1 = Enabled

Table 147 Thermal Shutdown w PP, August 2012, Rev 3.4

248

Pre-Production

WM8958

POWER ON RESET

The WM8958 includes a Power-On Reset (POR) circuit, which is used to reset the digital logic into a default state after power up. The POR circuit derives its output from AVDD2 and DCVDD. The internal

The specific behaviour of the circuit will vary, depending on relative timing of the supply voltages.

Typical scenarios are illustrated in Figure 82 and Figure 83.

Figure 82 Power On Reset Timing – AVDD2 enabled/disabled first

Figure 83 Power On Reset Timing - DCVDD enabled/disabled first

¯¯¯ signal is undefined until AVDD2 has exceeded the minimum threshold, V pora

. Once this writes to the control interface are ignored. Once AVDD2 and DCVDD have reached their respective control interface may take place.

Note that a power-on reset period, T

POR

, applies after AVDD2 and DCVDD have reached their respective power on thresholds. This specification is guaranteed by design rather than test. w power-down thresholds.


249

WM8958 w

Pre-Production

Typical Power-On Reset parameters for the WM8958 are defined in Table 148.

V pora_on

V pora_off

V pord_on

V pord_off

T

POR

Power-On threshold (AVDD2)

Power-Off threshold (AVDD2)

Power-On threshold (DCVDD)

Power-Off threshold (DCVDD)

Minimum Power-On Reset period

Table 148 Typical Power-On Reset Parameters

1.15 V

1.14 V

0.56 V

0.55 V

100 ns

Table 149 describes the status of the WM8958 digital I/O pins when the Power On Reset has completed, prior to any register writes. The same conditions apply on completion of a Software Reset

(described in the “Software Reset and Device ID” section).

TYPE RESET STATUS PIN NO NAME

DBVDD1 power domain

A4

C3

SPKMODE

LDO1ENA

D3

D5

E3

G2

ADDR

LDO2ENA

SCLK

SDA

E1

D2

F2

D4

H1

G1

MCLK1

MCLK2

BCLK1

LRCLK1

GPIO1/ADCLRCLK1

DACDAT1

F1 ADCDAT1


G3 BCLK2

H2

H3

E4

F4

LRCLK2

GPIO6/ADCLRCLK2

DACDAT2

ADCDAT2


E5 GPIO11/BCLK3

F5

G4

H4

GPIO10/LRCLK3

GPIO8/DACDAT3

GPIO9/ADCDAT3

Digital Input

Digital Input

Digital Input

Digital Input

Digital Input

Digital Input/Output

Digital Input

Digital Input




Digital Input

Digital Output




Digital Input

Digital Output





Pull-up to DBVDD1

Pull-down to DGND

Pull-down to DGND

Pull-down to DGND

Digital input

Digital input

Digital input

Pull-down to DGND

Digital input

Digital input

Digital input

Digital input

Digital output

Digital input,

Pull-down to DGND

Digital input,

Pull-down to DGND

Digital input,

Pull-down to DGND

Pull-down to DGND

Digital output

Digital input,

Pull-down to DGND

Digital input,

Pull-down to DGND

Digital input,

Pull-down to DGND

Digital input,

Pull-down to DGND

MICBIAS1 power domain

D6

A8

B9

DMICCLK

IN2RN/DMICDAT2

IN2LN/DMICDAT1

Digital Output

Analogue Input/Digital Input

Analogue Input/Digital Input

Table 149 WM8958 Digital I/O Status in Reset

Digital output

Analogue input

Analogue input

Note that the dual function IN2LN/DMICDAT1 and IN2RN/DMICDAT2 pins default to IN2LN or IN2RN

(analogue input) after Power On Reset is completed. The IN2LN and IN2RN functions are referenced to the AVDD1 power domain.


250

Pre-Production

WM8958

QUICK START-UP AND SHUTDOWN

The default control sequences (see “Control Write Sequencer”) contain only the register writes necessary to enable or disable specific output drivers. It is therefore necessary to configure the signal path and gain settings before commanding any of the default start-up sequences.

This section describes minimum control sequences to configure the WM8958 for DAC to Headphone playback. Note that these sequences are provided for guidance only; application software should be verified and tailored to ensure optimum performance.

Table 150 describes an example control sequence to enable DAC playback to HPOUT1L and

HPOUT1R path. This involves DAC enable, signal path configuration and mute control, together with the default “Headphone Cold Start-Up” sequence. Table 151 describes an example control sequence to disable the direct DAC to Headphone path.

REGISTER VALUE

R5 (0005h) 0003h

DESCRIPTION

Enable DAC1L and DAC1R

R45 (002Dh)

R46 (002Eh)

R272 (0110h)

0100h

0100h

8100h

Enable path from DAC1L to HPOUT1L

Enable path from DAC1R to HPOUT1R

Initiate Control Write Sequencer at Index Address 0 (00h)

(Headphone Cold Start-Up sequence)

R1056 (0420h) 0000h

Note: Delay must be inserted in the sequence to allow the

Control Write Sequencer to finish. Any control interface writes to the CODEC will be ignored while the Control Write

Sequencer is running.

Soft un-mute DAC1L and DAC1R

Table 150 DAC to Headphone Direct Start-Up Sequence

REGISTER VALUE

R1056 (0420h) 0200h

DESCRIPTION

Soft mute DAC1L and DAC1R

R272 (0110h) 812Ah Initiate Control Write Sequencer at Index Address 42 (2Ah)

(Generic Shut-Down)

R45 (002Dh)

R46 (002Eh)

R5 (0005h)

0000h

0000h

0000h

Note: Delay must be inserted in the sequence to allow the

Control Write Sequencer to finish. Any control interface writes to the CODEC will be ignored while the Control Write

Sequencer is running.

Disable path from DAC1L to HPOUT1L

Disable path from DAC1R to HPOUT1R

Disable DAC1L and DAC1R

Table 151 DAC to Headphone Direct Shut-Down Sequence

In both cases, the WSEQ_BUSY bit (in Register R272, see Table 130) will be set to 1 while the

Control Write Sequence runs. When this bit returns to 0, the remaining steps of the sequence may be executed. w PP, August 2012, Rev 3.4

251

WM8958

Pre-Production

SOFTWARE RESET AND DEVICE ID

The device ID can be read back from register R0. Writing to this register will reset the device.

The software reset causes most control registers to be reset to their default state. Note that the

Control Write Sequencer registers R12288 (3000h) through to R12799 (31FFh) are not affected by a software reset; the Control Sequences defined in these registers are retained unchanged.

The status of the WM8958 digital I/O pins following a software reset is described in Table 149.

The device revision can be read back from register R256.

REGISTER

ADDRESS

R0 (0000h)

Software

Reset


15:0 SW_RESET

[15:0]

8958h

DESCRIPTION

Writing to this register resets all registers to their default state. (Note - Control

Write Sequencer registers are not affected by Software Reset.)

Reading from this register will indicate device ID 8958h.

Chip revision R256

(0100h)

Chip

Revision

3:0 CHIP_REV [3:0]

Table 152 Chip Reset and ID w PP, August 2012, Rev 3.4

252

Pre-Production

WM8958

REGISTER MAP

The WM8958 control registers are listed below. Note that only the register addresses described here should be accessed; writing to other addresses may result in undefined behaviour. Register bits that are not documented should not be changed from the default values.

REG NAME

R0 (0h) Software Reset

R1 (1h)

R2 (2h)

R3 (3h)

R4 (4h)

R5 (5h)

Power

Management (1)

Power

Management (2)

Power

Management (3)

Power

Management (4)

Power

Management (5)

15 14 13 12 11 10 9 8 7

SW_RESET [15:0]

6 5 4 3 2 1 0 DEFAULT

0000h

0 TSHU

T_ENA

UTR_E

NA

SPKO

UTL_E

NA

HPOU

T2_EN

A

TSHU

T_OP

DIS

UT1N_

ENA

LINEO

UT1P_

ENA

LINEO

UT2N_

ENA

LINEO

UT2P_

ENA

SPKR

VOL_E

NA

SPKLV

OL_EN

A

MIXOU

TLVOL

_ENA

MIXOU

TRVO

L_ENA

MIXOU

TL_EN

A

MIXOU

TR_EN

A

DCL_E

NA

ACL_E

NA

0 OPCL

AIF2A

DCR_

ENA

AIF2D

ACR_

ENA

K_ENA

AIF1A

DC2L_

ENA

0 HPOU

0 MIXIN

L_ENA

MIXIN

R_EN

A

AIF1A

DC2R_

ENA

T1L_E

NA

AIF1A

DC1L_

ENA

HPOU

T1R_E

NA

AIF1A

DC1R_

ENA

AIF1D

AC2L_

ENA

AIF1D

AC2R_

ENA

AIF1D

AC1L_

ENA

AIF1D

AC1R_

ENA

IN2L_

ENA

IN1L_

ENA

_ENA

IN2R_

ENA

MICB1

_ENA

IN1R_

ENA

L_ENA

DMIC2

R_EN

A

DMIC1

L_ENA

DMIC1

R_EN

A

ADCL_

ENA

ADCR

_ENA

_ENA

DAC2

R_EN

A

[1:0]

DAC1L

_ENA

ENA

DAC1

R_EN

A

0000h

0 0 0 0 6000h

0 0 0 0 0000h

0000h

0000h

R6 (6h) Power

Management (6)

R21 (15h) Input Mixer (1)

[1:0] [1:0]

_MIXI

NR_B

OOST

IN1LP

_MIXI

NL_BO

OST

INPUT

S_CLA

MP

0 AIF3_T

RI

AIF3_ADCDAT

_SRC [1:0]

AIF2_

ADCD

AT_SR

C

AIF2_

DACD

AT_SR

C

AIF1_

DACD

AT_SR

C

0000h

0 0 0 0 0 0 0000h

U

IN1L_

MUTE

IN1L_Z

C

R24 (18h) Left Line Input 1&2

Volume

R25 (19h) Left Line Input 3&4

Volume

R26 (1Ah) Right Line Input

1&2 Volume

U

IN2L_

MUTE

IN2L_Z

C

IN1R_

MUTE

IN1R_

ZC U

R27 (1Bh) Right Line Input

3&4 Volume

R29 (1Dh) Right Output

Volume

U

IN2R_

MUTE

R28 (1Ch) Left Output Volume 0 0 0 0 0 0 0

T1_VU

HPOU

T1L_Z

C

IN2R_

ZC

HPOU

T1L_M

UTE_N

R30 (1Eh) Line Outputs

Volume

R31 (1Fh) HPOUT2 Volume

HPOUT1L_VOL [5:0] 006Dh

T1_VU

HPOU

T1R_Z

C

HPOU

T1R_M

UTE_N

HPOUT1R_VOL [5:0]

UT1N_

MUTE

LINEO

UT1P_

MUTE

LINEO

UT1_V

OL

T2_MU

TE

HPOU

T2_VO

L

0 LINEO

UT2N_

MUTE

LINEO

UT2P_

MUTE

LINEO

UT2_V

OL

006Dh

0066h

0 0 0 0 0020h

MIXOUTL_VOL [5:0] 0079h R32 (20h) Left OPGA Volume 0 0 0 0 0 0 0

T_VU

MIXOU

TL_ZC

MIXOU

TL_MU

TE_N

R33 (21h) Right OPGA

Volume T_VU

MIXOU

TR_ZC

MIXOU

TR_M

UTE_N

MIXOUTR_VOL [5:0] 0079h

R34 (22h) SPKMIXL

Attenuation B_REF

_SEL

0 DAC2L

_SPK

MIXL_

VOL

MIXIN

L_SPK

MIXL_

VOL

IN1LP

_SPK

MIXL_

VOL

MIXOU

TL_SP

KMIXL

_VOL

DAC1L

_SPK

MIXL_

VOL

SPKMIXL_VOL

[1:0]

0003h w PP, August 2012, Rev 3.4

253

WM8958

REG NAME

R35 (23h) SPKMIXR

Attenuation

R36 (24h) SPKOUT Mixers

R37 (25h) ClassD

R38 (26h) Speaker Volume

Left

R39 (27h) Speaker Volume

Right



R42 (2Ah) Input Mixer (4)

R43 (2Bh) Input Mixer (5)

R44 (2Ch) Input Mixer (6)

R45 (2Dh) Output Mixer (1)

R46 (2Eh) Output Mixer (2)

R47 (2Fh) Output Mixer (3)

R48 (30h) Output Mixer (4)



R51 (33h) HPOUT2 Mixer

R52 (34h) Line Mixer (1)

15 14 13 12

Pre-Production

11 10 9 8

UT_CL

ASSA

B

7 6 5 4

0 DAC2

R_SPK

MIXR_

VOL

MIXIN

R_SPK

MIXR_

VOL

IN1RP

_SPK

MIXR_

VOL

3

MIXOU

TR_SP

KMIXR

_VOL

2

DAC1

R_SPK

MIXR_

VOL

1

SPKMIXR_VOL

[1:0]

0 DEFAULT

0003h

P_TO_

SPKO

UTL

SPKMI

XL_TO

_SPK

OUTL

SPKMI

XR_T

O_SP

KOUT

L

IN2LR

P_TO_

SPKO

UTR

SPKMI

XL_TO

_SPK

OUTR

SPKMI

XR_T

O_SP

KOUT

R

0011h

0140h

[2:0]

SPKOUTL_VOL [5:0]

[2:0]

UT_VU

SPKO

UTL_Z

C

SPKO

UTL_M

UTE_N

SPKO

UT_VU UTR_Z

C

SPKO

UTR_

MUTE

_N

SPKOUTR_VOL [5:0]

0079h

0079h

_TO_I

N2L

O_MIX

INL

IN2L_

MIXIN

L_VOL

TO_MI

XINR

IN2R_

MIXIN

R_VOL

IN2LN

_TO_I

N2L

IN1LP

_TO_I

N1L

IN1LN

_TO_I

N1L

0 IN1L_T

O_MIX

INL

IN1L_

MIXIN

L_VOL

0 IN1R_

TO_MI

XINR

IN1R_

MIXIN

R_VOL

IN2RP

_TO_I

N2R

IN2RN

_TO_I

N2R

IN1RP

_TO_I

N1R

IN1RN

_TO_I

N1R

0000h

0 MIXOUTL_MIXINL_VOL 0000h

[2:0]

0 MIXOUTR_MIXINR_VO

L [2:0]

0000h

[2:0] [2:0]

[2:0]

[2:0]

[2:0]

L [2:0]

[2:0] [2:0]

_TO_H

POUT

1L

MIXIN

R_TO_

MIXOU

TL

MIXIN

L_TO_

MIXOU

TL

IN2RN

_TO_

MIXOU

TL

IN2LN

_TO_

MIXOU

TL

IN1R_

TO_MI

XOUT

L

IN1L_T

O_MIX

OUTL

IN2LP

_TO_

MIXOU

TL

DAC1L

_TO_

MIXOU

TL

R_TO_

HPOU

T1R

MIXIN

L_TO_

MIXOU

TR

MIXIN

R_TO_

MIXOU

TR

IN2LN

_TO_

MIXOU

TR

IN2RN

_TO_

MIXOU

TR

IN1L_T

O_MIX

OUTR

IN1R_

TO_MI

XOUT

R

IN2RP

_TO_

MIXOU

TR

DAC1

R_TO_

MIXOU

TR

[2:0]

IN1R_MIXOUTL_VOL

[2:0]

IN1L_MIXOUTL_VOL

[2:0]

0000h

0000h

0000h

[2:0]

IN1L_MIXOUTR_VOL

[2:0]

IN1R_MIXOUTR_VOL

[2:0]

MIXINR_MIXOUTL_VO

L [2:0]

MIXINL_MIXOUTL_VOL

[2:0] [2:0]

IN2LN_MIXOUTR_VOL

[2:0]

MIXINL_MIXOUTR_VO

L [2:0]

MIXINR_MIXOUTR_VO

L [2:0]

0000h

0000h

0000h

P_TO_

HPOU

T2

MIXOU

TLVOL

_TO_H

POUT

2

MIXOU

TRVO

L_TO_

HPOU

T2

TL_TO

_LINE

OUT1

N

MIXOU

TR_TO

_LINE

OUT1

N

LINEO

UT1_M

ODE

0 0 0 0000h

0 IN1R_

TO_LI

NEOU

T1P

IN1L_T

O_LIN

EOUT

1P

MIXOU

TL_TO

_LINE

OUT1

P


254

Pre-Production

WM8958

REG NAME

R53 (35h) Line Mixer (2)

R54 (36h) Speaker Mixer

R55 (37h) Additional Control

R56 (38h) AntiPOP (1)

R57 (39h) AntiPOP (2)

15 14 13 12 11 10 9 8 7 6 5

TR_TO

_LINE

OUT2

N

MIXOU

TL_TO

_LINE

OUT2

N

4

LINEO

UT2_M

ODE

3 2 1

0 IN1L_T

O_LIN

EOUT

2P

IN1R_

TO_LI

NEOU

T2P

0 DEFAULT

MIXOU

TR_TO

_LINE

OUT2

P

0000h

_TO_S

PKMIX

L

DAC2

R_TO_

SPKMI

XR

MIXIN

L_TO_

SPKMI

XL

MIXIN

R_TO_

SPKMI

XR

IN1LP

_TO_S

PKMIX

L

IN1RP

_TO_S

PKMIX

R

MIXOU

TL_TO

_SPK

MIXL

MIXOU

TR_TO

_SPK

MIXR

DAC1L

_TO_S

PKMIX

L

DAC1

R_TO_

SPKMI

XR

0000h

UT1_F

B

LINEO

UT2_F

B

UT_V

MID_B

UF_EN

A

HPOU

T2_IN_

ENA

LINEO

UT1_D

ISCH

LINEO

UT2_D

ISCH

0 0 0 0 0000h

[1:0] BUF_E

NA

START

UP_BI

AS_EN

A

BIAS_

SRC

VMID_

DISCH

0180h

R59 (3Bh) LDO 1 000Dh

DISCH

R60 (3Ch) LDO 2

R61 (3Dh) MICBIAS1

R62 (3Eh) MICBIAS2

0005h

_RATE

_RATE

MICB1

_MOD

E

MICB2

_MOD

E

[1:0] DISCH

MICB1_LVL [2:0] MICB1

_DISC

H

MICB2_LVL [2:0] MICB2

_DISC

H

0039h

0039h

0 0 1 1 1 1 1 0 0 1 0 0 1 0 1 1F25h R76 (4Ch) Charge Pump (1) CP_E

NA

R77 (4Dh) Charge Pump (2) CP_DI

SCH

R81 (51h) Class W (1)

R84 (54h) DC Servo (1)



R88 (58h) DC Servo

Readback

R96 (60h) Analogue HP (1)

R208 (D0h) Mic Detect 1



R256 (100h) Chip Revision

R257 (101h) Control Interface

0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 AB19h

RIG_SI

NGLE_

1

DCS_T

RIG_SI

NGLE_

0

0 0 0 0

DCS_DAC_WR_VAL_1 [7:0]

_SEL [1:0]

RIG_S

ERIES

_1

DCS_T

RIG_S

ERIES

_0

RIG_S

TART

UP_1

DCS_T

RIG_S

TART

UP_0

DCS_T

RIG_D

AC_W

R_1

DCS_T

RIG_D

AC_W

R_0

DCS_

ENA_

CHAN

_1

YN_P

WR

DCS_

ENA_

CHAN

_0

0004h

0000h

DCS_TIMER_PERIOD_01 054Ah

DCS_DAC_WR_VAL_0 [7:0] 0000h

MPLETE [1:0]

T1L_R

MV_S

HORT

HPOU

T1L_O

UTP

_COMPLETE

[1:0]

HPOU

T1L_D

LY

P_COMPLETE

[1:0]

0 0000h 0 HPOU

T1R_R

MV_S

HORT

HPOU

T1R_O

UTP

HPOU

T1R_D

LY

[3:0] MICD_RATE MICD_

DBTIM

E

MICD_

ENA

0000h

5600h

0 0 0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

MICD_

VALID

MICD_

STS

007Fh

0000h

000Xh

0 0 8004h

_INC w PP, August 2012, Rev 3.4

255

WM8958

Pre-Production

REG NAME

R272 (110h) Write Sequencer

Ctrl (1)

15

WSEQ

_ENA

14 13 12 11 10 9

_ABO

RT

8

WSEQ

_STAR

T

7 6 5 4 3 2 1 0 DEFAULT

R273 (111h) Write Sequencer

Ctrl (2)

R512 (200h) AIF1 Clocking (1)

_BUSY

[1:0] LK_IN

V

AIF1C

LK_DI

V

AIF1C

LK_EN

A

0000h



[1:0] LK_IN

V

AIF2C

LK_DI

V

AIF2C

LK_EN

A

0000h


R520 (208h) Clocking (1) 0 DSP2

CLK_E

NA

AIF1D

K_ENA SPCLK

_ENA

AIF2D

SPCLK

_ENA

SYSD

SPCLK

_ENA

SYSCL

K_SR

C

0000h

R521 (209h) Clocking (2)

R528 (210h) AIF1 Rate

R529 (211h) AIF2 Rate

R530 (212h) Rate Status

R544 (220h) FLL1 Control (1)

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 SR_ERROR 0000h

OSC_

ENA

FLL1_

ENA

0000h





0 0

0

FLL1_

BYP

0 0

FLL1_THETA [15:0]

FLL1_

FRC_

NCO

FLL2_LAMBDA [15:0]

0 FLL1_REFCLK

_DIV [1:0]

0 FLL1_REFCLK

_SRC [1:0]

0000h

0 0 0 0 0 0000h

0C80h

R550 (226h) FLL1 EFS1

R551 (227h) FLL1 EFS2

0000h

0006h


OSC_

ENA

EFS_E

NA

FLL2_

ENA

0000h





R582 (246h) FLL2 EFS1

R583 (247h) FLL2 EFS2

R768 (300h) AIF1 Control (1)


0 0

0

FLL2_

BYP

AIF1A

DCL_S

RC

AIF1D

ACL_S

RC

0 0

AIF1A

DCR_

SRC

AIF1D

ACR_

SRC

AIF1A

DC_T

DM

FLL2_THETA [15:0] 0000h

0 0 0 0 0 0000h

FLL2_

FRC_

NCO

FLL2_LAMBDA [15:0]

0 FLL2_REFCLK

_DIV [1:0]

0 FLL2_REFCLK

_SRC [1:0]

0C80h

0000h

0006h

0 AIF1_WL [1:0] AIF1_FMT [1:0] 0 0

EFS_E

NA

0 4050h

ST [1:0]

BCLK_

INV

0 AIF1_

MONO AC_C

OMP

AIF1D

AC_C

OMPM

ODE

AIF1A

DC_C

OMP

AIF1A

DC_C

OMPM

ODE

AIF1_L

OOPB

ACK

4000h

0 0 0 0 0 0 0 0 0 0 0 0 0000h R770 (302h) AIF1 Master/Slave AIF1_T

RI

R771 (303h) AIF1 BCLK

AIF1_

MSTR

AIF1_

CLK_F

RC

AIF1_L

RCLK_

FRC

0 0 0 0 0 0 0 0 0 0 0 0040h w PP, August 2012, Rev 3.4

256

Pre-Production

WM8958

REG NAME

R772 (304h) AIF1ADC LRCLK

R773 (305h) AIF1DAC LRCLK

15 14 13 10 9 8 7 6 5 4

AIF1ADC_RATE [10:0]

AIF1DAC_RATE [10:0]

3 2 1 0 DEFAULT

0040h

0040h

R774 (306h) AIF1DAC Data

R775 (307h) AIF1ADC Data

ACL_D

AT_IN

V

AIF1D

ACR_

DAT_I

NV

DCL_D

AT_IN

V

AIF1A

DCR_

DAT_I

NV

0 AIF2_WL [1:0] AIF2_FMT [1:0] 0 AIF2T

XL_EN

A

AIF2T

XR_E

NA



R786 (312h) AIF2 Master/Slave AIF2_T

RI

R787 (313h) AIF2 BCLK

R788 (314h) AIF2ADC LRCLK

AIF2A

DCL_S

RC

AIF2D

ACL_S

RC

AIF2A

DCR_

SRC

AIF2A

DC_T

DM

AIF2A

DC_T

DM_C

HAN

BCLK_

INV

AIF2ADC_RATE [10:0]

4053h

AIF2D

ACR_

SRC

AIF2D

AC_TD

M

AIF2D

AC_TD

M_CH

AN

AIF2DAC_BOO

ST [1:0]

0 AIF2_

MONO AC_C

OMP

AIF2D

AC_C

OMPM

ODE

AIF2A

DC_C

OMP

AIF2A

DC_C

OMPM

ODE

AIF2_L

OOPB

ACK

4000h

0 0 0 0 0 0 0 0 0 0 0 0 0000h AIF2_

MSTR

AIF2_

CLK_F

RC

AIF2_L

RCLK_

FRC

0 0 0 0 0040h

0040h

R789 (315h) AIF2DAC LRCLK

0 0 0 0 0 0 0

DC_LR

CLK_I

NV

AIF2A

DC_LR

CLK_D

IR

AC_LR

CLK_I

NV

AIF2D

AC_LR

CLK_D

IR

AIF2DAC_RATE [10:0]

0000h

0000h

0040h

R790 (316h) AIF2DAC Data 0000h

R791 (317h) AIF2ADC Data

ACL_D

AT_IN

V

AIF2D

ACR_

DAT_I

NV

DCL_D

AT_IN

V

AIF2A

DCR_

DAT_I

NV

0000h


12 11

DC_LR

CLK_I

NV

AIF1A

DC_LR

CLK_D

IR

AC_LR

CLK_I

NV

AIF1D

AC_LR

CLK_D

IR

RCLK_

INV


ST [1:0] AC_C

OMP

AIF3D

AC_C

OMPM

ODE

AIF3A

DC_C

OMP

AIF3A

DC_C

OMPM

ODE

AIF3_L

OOPB

ACK

0000h

R802 (322h) AIF3DAC Data 0000h

AC_D

AT_IN

V

R803 (323h) AIF3ADC Data 0000h

DC_D

AT_IN

V

R1024 (400h) AIF1 ADC1 Left

Volume DC1_V

U

AIF1ADC1L_VOL [7:0] 00C0h w PP, August 2012, Rev 3.4

257

WM8958

Pre-Production

REG NAME

R1025 (401h) AIF1 ADC1 Right

Volume

15 14 13 12 11 10 9 8 7 6 5 4 3

AIF1ADC1R_VOL [7:0]

2 1 0 DEFAULT

00C0h

DC1_V

U

R1026 (402h) AIF1 DAC1 Left

Volume AC1_V

U

AIF1DAC1L_VOL [7:0] 00C0h

R1027 (403h) AIF1 DAC1 Right

Volume AC1_V

U

AIF1DAC1R_VOL [7:0] 00C0h


Volume DC2_V

U

AIF1ADC2L_VOL [7:0] 00C0h


Volume

AIF1ADC2R_VOL [7:0] 00C0h

R1030 (406h) AIF1 DAC2 Left

Volume

R1031 (407h) AIF1 DAC2 Right

Volume

AIF1DAC2L_VOL [7:0] 00C0h

AC2_V

U

AIF1DAC2R_VOL [7:0] 00C0h

AC2_V

U

0 0 0 0 0 0 0 0 0 0 0 0000h R1040 (410h) AIF1 ADC1 Filters AIF1A

DC_4F

S

R1041 (411h) AIF1 ADC2 Filters

AIF1ADC1_HP

F_CUT [1:0]

AIF1A

DC1L_

HPF

AIF1A

DC1R_

HPF

0 AIF1ADC2_HP

F_CUT [1:0]

AIF1A

DC2L_

HPF

AIF1A

DC2R_

HPF

R1056 (420h) AIF1 DAC1 Filters

(1)


(2)


(1)


(2)

0 0 0 0 0 0 0 0 0 0 0 0000h

AC1_

MUTE

0 AIF1D

AC1_

MONO

0 AIF1D

AC1_

MUTE

RATE

AIF1D

AC1_U

NMUT

E_RA

MP

0 0 0 0 0200h

0 0 AIF1DAC1_3D_GAIN

AC1_3

D_EN

A

AC2_

MUTE

0 0 0 1 0 0 0 0 0010h

0 AIF1D

AC2_

MONO

0 AIF1D

AC2_

MUTE

RATE

AIF1D

AC2_U

NMUT

E_RA

MP

0 0 0 0 0200h

0 0 AIF1DAC2_3D_GAIN

AC2_3

D_EN

A

0 0 0 1 0 0 0 0 0010h

R1072 (430h) AIF1 DAC1 Noise

Gate

DC2_V

U

_HLD [1:0] [2:0]

0068h

AC1_N

G_EN

A

R1073 (431h) AIF1 DAC2 Noise

Gate

0068h

R1088 (440h) AIF1 DRC1 (1)

R1089 (441h) AIF1 DRC1 (2)

R1090 (442h) AIF1 DRC1 (3)

AIF1DRC1_SIG_DET_RMS [4:0]

_HLD [1:0] [2:0] AC2_N

G_EN

A

AIF1DRC1_SIG

_DET_PK [1:0]

AIF1D

RC1_N

G_EN

A

AIF1D

RC1_S

IG_DE

T_MO

DE

AIF1D

RC1_S

IG_DE

T

AIF1D

RC1_K

NEE2_

OP_E

NA

AIF1D

RC1_

QR

AIF1D

RC1_A

NTICLI

P

AIF1D

AC1_D

RC_E

NA

AIF1A

DC1L_

DRC_

ENA

AIF1A

DC1R_

DRC_

ENA

AIF1DRC1_NG_MINGAIN [3:0] AIF1DRC1_NG

_EXP [1:0]

AIF1DRC1_DCY [3:0]

AIF1DRC1_QR

_THR [1:0]

AIF1DRC1_QR

_DCY [1:0]

AIF1DRC1_MINGAIN

[2:0]

AIF1DRC1_HI_COMP

[2:0]

AIF1DRC1_MA

XGAIN [1:0]

AIF1DRC1_LO_COMP

[2:0]

0098h

0845h

0000h


w

258

Pre-Production

WM8958

REG NAME

R1091 (443h) AIF1 DRC1 (4)

R1092 (444h) AIF1 DRC1 (5)

R1104 (450h) AIF1 DRC2 (1)

R1105 (451h) AIF1 DRC2 (2)

R1106 (452h) AIF1 DRC2 (3)

R1107 (453h) AIF1 DRC2 (4)

R1108 (454h) AIF1 DRC2 (5)

R1152 (480h) AIF1 DAC1 EQ

Gains (1)


Gains (2)


Band 1 A


Band 1 B


Band 1 PG


Band 2 A


Band 2 B


Band 2 C


Band 2 PG


Band 3 A

R1162 (48Ah) AIF1 DAC1 EQ

Band 3 B

R1163 (48Bh) AIF1 DAC1 EQ

Band 3 C

R1164 (48Ch) AIF1 DAC1 EQ

Band 3 PG

R1165 (48Dh) AIF1 DAC1 EQ

Band 4 A

R1166 (48Eh) AIF1 DAC1 EQ

Band 4 B

R1167 (48Fh) AIF1 DAC1 EQ

Band 4 C


Band 4 PG


Band 5 A


Band 5 B


Band 5 PG


Band 1 C w

15 14 13 12 11 10

0 0 0 0 0

9 8 7 6 5 4 3 2 1 0 DEFAULT

AIF1DRC1_KNEE_OP 0000h

0 0 0 0 0 0 AIF1DRC1_KNEE2_IP

AIF1DRC2_SIG_DET_RMS [4:0] AIF1DRC2_SIG

_DET_PK [1:0]

AIF1D

RC2_N

G_EN

A

AIF1D

RC2_S

IG_DE

T_MO

DE

AIF1D

RC2_S

IG_DE

T

AIF1D

RC2_K

NEE2_

OP_E

NA

AIF1D

RC2_

QR

AIF1D

RC2_A

NTICLI

P

AIF1D

AC2_D

RC_E

NA

AIF1A

DC2L_

DRC_

ENA

AIF1A

DC2R_

DRC_

ENA

0098h

AIF1DRC2_NG_MINGAIN [3:0] AIF1DRC2_NG

_EXP [1:0]

0 0 0 0 0

_THR [1:0]

AIF1DRC2_DCY [3:0]

AIF1DRC2_QR AIF1DRC2_QR

_DCY [1:0]

AIF1DRC2_MINGAIN

[2:0]

AIF1DRC2_MA

XGAIN [1:0]

0845h

AIF1DRC2_HI_COMP

[2:0]

AIF1DRC2_LO_COMP

[2:0]

0000h

AIF1DRC2_KNEE_OP 0000h

0 0 0 0 0 0 AIF1DRC2_KNEE2_IP

AIF1DAC1_EQ_B1_GAIN [4:0] AIF1DAC1_EQ_B2_GAIN [4:0] AIF1DAC1_EQ_B3_GAIN [4:0]

AIF1DAC1_EQ_B4_GAIN [4:0] 0 0 0 0 0

AC1_E

Q_MO

DE

AIF1DAC1_EQ_B1_A [15:0]

AIF1D

AC1_E

Q_EN

A

6318h

6300h

0FCAh

AIF1DAC1_EQ_B1_B [15:0]

AIF1DAC1_EQ_B1_PG [15:0]



AIF1DAC1_EQ_B2_C [15:0]














0400h

00D8h

1EB5h

F145h

0B75h

01C5h

1C58h

F373h

0A54h

0558h

168Eh

F829h

07ADh

1103h

0564h

0559h

4000h

0000h


259

WM8958

REG NAME

R1184 (4A0h) AIF1 DAC2 EQ

Gains (1)


Gains (2)


Band 1 A


Band 1 B


Band 1 PG


Band 2 A


Band 2 B


Band 2 C


Band 2 PG


Band 3 A

R1194 (4AAh) AIF1 DAC2 EQ

Band 3 B

R1195 (4ABh) AIF1 DAC2 EQ

Band 3 C

R1196 (4ACh) AIF1 DAC2 EQ

Band 3 PG

R1197 (4ADh) AIF1 DAC2 EQ

Band 4 A

R1198 (4AEh) AIF1 DAC2 EQ

Band 4 B

R1199 (4AFh) AIF1 DAC2 EQ

Band 4 C

R1200 (4B0h) AIF1 DAC2 EQ

Band 4 PG


Band 5 A


Band 5 B


Band 5 PG


Band 1 C

R1280 (500h) AIF2 ADC Left

Volume

R1281 (501h) AIF2 ADC Right

Volume

R1282 (502h) AIF2 DAC Left

Volume

R1283 (503h) AIF2 DAC Right

Volume

Pre-Production

15 14 13 12

AIF1DAC2_EQ_B1_GAIN [4:0]

11 10 9 8 7


6 5 4 3 2


1 0 DEFAULT

AIF1D

AC2_E

Q_EN

A

6318h

6300h AIF1DAC2_EQ_B4_GAIN [4:0] 0 0 0 0 0

AC2_E

Q_MO

DE

AIF1DAC2_EQ_B1_A [15:0] 0FCAh



















AIF2ADCL_VOL [7:0]

0564h

0559h

4000h

0000h

00C0h

168Eh

F829h

07ADh

1103h

0B75h

01C5h

1C58h

F373h

0A54h

0558h

0400h

00D8h

1EB5h

F145h

DC_V

U

DC_V

U

AC_V

U

AC_V

U

AIF2ADCR_VOL [7:0]

AIF2DACL_VOL [7:0]

AIF2DACR_VOL [7:0]

00C0h

00C0h

00C0h w PP, August 2012, Rev 3.4

260

Pre-Production

WM8958

REG NAME

R1296 (510h) AIF2 ADC Filters

R1312 (520h) AIF2 DAC Filters

(1)

R1313 (521h) AIF2 DAC Filters

(2)

R1328 (531h) AIF2 DAC Noise

Gate

R1344 (540h) AIF2 DRC (1)

R1345 (541h) AIF2 DRC (2)

R1346 (542h) AIF2 DRC (3)

R1347 (543h) AIF2 DRC (4)

R1348 (544h) AIF2 DRC (5)

R1408 (580h) AIF2 EQ Gains (1)

R1409 (581h) AIF2 EQ Gains (2)

R1410 (582h) AIF2 EQ Band 1 A

R1411 (583h) AIF2 EQ Band 1 B

R1412 (584h) AIF2 EQ Band 1

PG



R1415 (587h) AIF2 EQ Band 2 C


PG


R1418 (58Ah) AIF2 EQ Band 3 B

R1419 (58Bh) AIF2 EQ Band 3 C

R1420 (58Ch) AIF2 EQ Band 3

PG

R1421 (58Dh) AIF2 EQ Band 4 A

R1422 (58Eh) AIF2 EQ Band 4 B

R1423 (58Fh) AIF2 EQ Band 4 C


PG




PG

R1428 (594h) AIF2 EQ Band 1 C

15 14 13 12

0 AIF2ADC_HPF

_CUT [1:0]

AIF2A

DCL_H

PF

11

AIF2A

DCR_

HPF

10 9 8 7 6 5 4 3 2 1 0 DEFAULT

0 0 0 0 0 0 0 0 0 0 0 0000h

0 0

AIF2DRC_SIG_DET_RMS [4:0]

AC_M

UTE

0 AIF2D

AC_M

ONO

0 AIF2D

AC_M

UTER

ATE

AIF2D

AC_U

NMUT

E_RA

MP

0 0 0 0 0200h

0 0 0 1 0 0 0 0 0010h

AC_3D

_ENA

0068h

AIF2DRC_SIG_

DET_PK [1:0]

AIF2D

RC_N

G_EN

A

AIF2D

RC_SI

G_DE

T_MO

DE

HLD [1:0]

AIF2D

RC_SI

G_DE

T

AIF2D

RC_K

NEE2_

OP_E

NA

AIF2D

RC_Q

R

AIF2D

RC_A

NTICLI

P

[2:0]

AIF2D

AC_D

RC_E

NA

AIF2A

DCL_D

RC_E

NA

AC_N

G_EN

A

AIF2A

DCR_

DRC_

ENA

0098h

0 0 0 AIF2DRC_ATK

AIF2DRC_NG_MINGAIN [3:0] AIF2DRC_NG_

EXP [1:0]

0 0 0 0 0

AIF2DRC_QR_

THR [1:0]

AIF2DRC_QR_

DCY [1:0]

0845h

[2:0] GAIN [1:0]

AIF2DRC_HI_COMP

[2:0]

AIF2DRC_LO_COMP

[2:0]

0000h

AIF2DRC_KNEE_OP 0000h

0 0 0 0 0 0 AIF2DRC_KNEE2_IP

AIF2DAC_EQ_B1_GAIN [4:0] AIF2DAC_EQ_B2_GAIN [4:0]

AIF2DRC_KNEE2_OP

AIF2DAC_EQ_B3_GAIN [4:0] AIF2D

AC_E

Q_EN

A

0000h

6318h

6300h

AC_E

Q_MO

DE

AIF2DAC_EQ_B1_A [15:0]

AIF2DAC_EQ_B1_B [15:0]

AIF2DAC_EQ_B1_PG [15:0]

0FCAh

0400h

00D8h



AIF2DAC_EQ_B2_C [15:0]














1EB5h

F145h

0B75h

01C5h

1C58h

F373h

0A54h

0558h

168Eh

F829h

07ADh

1103h

0564h

0559h

4000h


261

WM8958

REG NAME

R1536 (600h) DAC1 Mixer

Volumes

R1537 (601h) DAC1 Left Mixer

Routing

15 14 13 12

Pre-Production

11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT

R1538 (602h) DAC1 Right Mixer

Routing

_TO_D

AC1L

ADCL_

TO_D

AC1L

_TO_D

AC1R

ADCL_

TO_D

AC1R

0 AIF2D

ACL_T

O_DA

C1L

AIF1D

AC2L_

TO_D

AC1L

AIF1D

AC1L_

TO_D

AC1L

0 AIF2D

ACR_T

O_DA

C1R

AIF1D

AC2R_

TO_D

AC1R

AIF1D

AC1R_

TO_D

AC1R

0000h

0000h

R1539 (603h) DAC2 Mixer

Volumes

R1540 (604h) DAC2 Left Mixer

Routing

R1541 (605h) DAC2 Right Mixer

Routing


Mixer Routing


Mixer Routing


Mixer Routing

R1545 (609h) AIF1 ADC2 Right mixer Routing

R1552 (610h) DAC1 Left Volume

_TO_D

AC2L

_TO_D

AC2R

ADCL_

TO_D

AC2L

ADCL_

TO_D

AC2R

0 AIF2D

ACL_T

O_DA

C2L

AIF1D

AC2L_

TO_D

AC2L

AIF1D

AC1L_

TO_D

AC2L

0 AIF2D

ACR_T

O_DA

C2R

AIF1D

AC2R_

TO_D

AC2R

AIF1D

AC1R_

TO_D

AC2R

_TO_A

IF1AD

C1L

AIF2D

ACL_T

O_AIF

1ADC1

L

R_TO_

AIF1A

DC1R

AIF2D

ACR_T

O_AIF

1ADC1

R

_TO_A

IF1AD

C2L

AIF2D

ACL_T

O_AIF

1ADC2

L

R_TO_

AIF1A

DC2R

AIF2D

ACR_T

O_AIF

1ADC2

R

DAC1L_VOL [7:0]

0000h

0000h

0000h

0000h

0000h

0000h

02C0h

R1553 (611h) DAC1 Right

Volume

R1554 (612h) DAC2 Left Volume

R1555 (613h) DAC2 Right

Volume

R1556 (614h) DAC Softmute

_MUT

E

_MUT

E

DAC1_

VU

R_MU

TE

DAC1_

VU

DAC2_

VU

R_MU

TE

DAC2_

VU

DAC1R_VOL [7:0]

DAC2L_VOL [7:0]

DAC2R_VOL [7:0]

02C0h

02C0h

02C0h

R1568 (620h) Oversampling

R1569 (621h) Sidetone

F

SOFT

MUTE

MODE

DAC_

MUTE

RATE

OSR12

8

DAC_

OSR12

8

EL

STL_S

EL

0000h

0002h


262

Pre-Production

WM8958

REG NAME

R1792 (700h) GPIO 1

15 14

GP1_D

IR

GP1_P

U

13

GP1_P

D

12 11 10

OL

9

GP1_

OP_C

FG

8

GP1_D

B

7 6

0 GP1_L

VL

5 4 3 2 1 0 DEFAULT

0 0 0 0 1 0 0 0 0 0 0 0 1 A101h R1793 (701h) Pull Control

(MCLK2)

R1794 (702h) Pull Control

(BCLK2)


(DACLRCLK2)


(DACDAT2)

1 MCLK

2_PU

MCLK

2_PD

1 BCLK2

_PU

BCLK2

_PD

1 DACL

RCLK2

_PU

DACL

RCLK2

_PD

1 DACD

AT2_P

U

DACD

AT2_P

D

GP6_D

IR

GP6_P

U

GP6_P

D

0 0 0 0 1 0 0 0 0 0 0 0 1 A101h

0 0 0 0 1 0 0 0 0 0 0 0 1 A101h

0 0 0 0 1 0 0 0 0 0 0 0 1 A101h

R1797 (705h) GPIO 6

R1799 (707h) GPIO 8

R1800 (708h) GPIO 9

GP8_D

IR

GP9_D

IR

GP8_P

U

GP9_P

U

GP8_P

D

GP9_P

D

OL

OL

OL

GP6_

OP_C

FG

GP8_

OP_C

FG

GP6_D

B

GP8_D

B

GP9_

OP_C

FG

GP9_D

B

0 GP6_L

VL

0 GP8_L

VL

0 GP9_L

VL

R1801 (709h) GPIO 10

R1802 (70Ah) GPIO 11

GP10_

DIR

GP11_

DIR

GP10_

PU

GP11_

PU

GP10_

PD

GP11_

PD

POL

POL

GP10_

OP_C

FG

GP10_

DB

GP11_

OP_C

FG

GP11_

DB

AT2_P

U

DMICD

AT2_P

D

DMICD

AT1_P

U

DMICD

AT1_P

D

0 GP10_

LVL

0 GP11_

LVL

R1824 (720h) Pull Control (1)

R1825 (721h) Pull Control (2)

_PD

MCLK

1_PU

MCLK

1_PD

DACD

AT1_P

U

0 LDO2E

NA_P

D

DACD

AT1_P

D

0 LDO1E

NA_P

D

DACL

RCLK1

_PU

DACL

RCLK1

_PD

BCLK1

_PU

ODE_

PU

BCLK1

_PD

0000h

0 0156h

0000h R1840 (730h) Interrupt Status 1

R1841 (731h) Interrupt Status 2

R1842 (732h) Interrupt Raw

Status 2

TEMP

_WAR

N_EIN

T

DCS_

DONE

_EINT

WSEQ

_DON

E_EIN

T

FIFOS

_ERR_

EINT

AIF2D

RC_SI

G_DE

T_EIN

T

EINT

GP10_

EINT

GP9_E

INT

GP8_E

INT

AIF1D

RC2_S

IG_DE

T_EIN

T

AIF1D

RC1_S

IG_DE

T_EIN

T

SRC2_

LOCK_

EINT

SRC1_

LOCK_

EINT

0 GP6_E

INT

FLL2_

LOCK_

EINT

FLL1_

LOCK_

EINT

TEMP

_WAR

N_STS

DCS_

DONE

_STS

WSEQ

_DON

E_STS

FIFOS

_ERR_

STS

AIF2D

RC_SI

G_DE

T_STS

AIF1D

RC2_S

IG_DE

T_STS

AIF1D

RC1_S

IG_DE

T_STS

SRC2_

LOCK_

STS

SRC1_

LOCK_

STS

FLL2_

LOCK_

STS

FLL1_

LOCK_

STS


Mask


Mask

11_EI

NT

IM_GP

10_EI

NT

IM_GP

9_EIN

T

IM_GP

8_EIN

T

IM_TE

MP_W

ARN_

EINT

IM_DC

S_DO

NE_EI

NT

IM_WS

EQ_D

ONE_

EINT

IM_FIF

OS_E

RR_EI

NT

IM_AIF

2DRC_

SIG_D

ET_EI

NT

IM_AIF

1DRC2

_SIG_

DET_E

INT

IM_AIF

1DRC1

_SIG_

DET_E

INT

IM_SR

C2_LO

CK_EI

NT

IM_SR

C1_LO

CK_EI

NT

1 IM_GP

6_EIN

T

IM_FL

L2_LO

CK_EI

NT

IM_FL

L1_LO

CK_EI

NT

EINT

CD_EI

NT

INT

TEMP

_SHUT

_EINT

_SHUT

_STS

1_EIN

T

IM_TE

MP_S

HUT_E

INT

0000h

0000h

07FFh

FFFFh

R1856 (740h) Interrupt Control 0000h

Q

R1864 (748h) IRQ Debounce 003Fh

_WAR

N_DB

_SHUT

_DB

R2304 (900h) DSP2_Program 1C00h

ENA w PP, August 2012, Rev 3.4

263

WM8958

Pre-Production

REG NAME

R2305 (901h) DSP2_Config

15 14 13

0 0

12 11 10 9 8 7 6 5 4

MBC_SEL

3 2 1 0 DEFAULT

MBC_

ENA

0000h

R2573 (A0Dh) DSP2_ExecControl 0 0 0 0 0 0 0 0 0 0 0 0 0

STOP

DSP2_

RUNR

R12288

(3000h)

Write Sequencer 0 0 0

R12289

(3001h)

Write Sequencer 1 0 0 0 0 0 0 0 0

Write Sequencer 2 R12290

(3002h)

R12291

(3003h)

R12292

(3004h)

Write Sequencer 3

Write Sequencer 4 0 0

[2:0]

_EOS0

Write Sequencer 5 0 0 0 0 0 0 0 0 R12293

(3005h)

R12294

(3006h)

Write Sequencer 6

[2:0]

Write Sequencer 7 R12295

(3007h) _EOS1

0 0000h

0039h

001Bh

0001h

0003h

004Ch

[similar for WSEQ address 2 … 126] 0001h

0006h

0000h R12796

(31FCh)

R12797

(31FDh)

R12798

(31FEh)

R12799

(31FFh)

Write Sequencer

508

Write Sequencer

509

Write Sequencer

510

Write Sequencer

511

0 0 0 0 0 0 0 0

27 [2:0]

_EOS1

27

WSEQ_DATA_START127

0000h


264

Pre-Production

REGISTER BITS BY ADDRESS

REGISTER

ADDRESS

R0 (00h)

Software

Reset

[15:0]

DESCRIPTION

_0000_000

0

Writing to this register resets all registers to their default state. (Note - Control Write Sequencer registers are not affected by Software Reset.)

Reading from this register will indicate device ID 8958h.

Register 00h Software Reset

REGISTER

ADDRESS

R1 (01h)

Power

Managemen t (1)

DESCRIPTION

13 SPKOUTR_EN

A

12 SPKOUTL_EN

A

0

0

SPKMIXR Mixer, SPKRVOL PGA and SPKOUTR

Output Enable

0 = Disabled

1 = Enabled

SPKMIXL Mixer, SPKLVOL PGA and SPKOUTL Output

Enable

0 = Disabled

1 = Enabled

11 HPOUT2_ENA 0 HPOUT2 Output Stage Enable

0 = Disabled

1 = Enabled

9 HPOUT1L_EN

A

0 Enables HPOUT1L input stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set as the first step of the HPOUT1L Enable sequence.

8 HPOUT1R_EN

A

0 Enables HPOUT1R input stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set as the first step of the HPOUT1R Enable sequence.

5 MICB2_ENA 0 Microphone Bias 2 Enable

0 = Disabled

1 = Enabled

4 MICB1_ENA 0 Microphone Bias 1 Enable

0 = Disabled

1 = Enabled

2:1 VMID_SEL

[1:0]

00 VMID Divider Enable and Select


01 = 2 x 40k divider (for normal operation)

10 = 2 x 240k divider (for low power standby)

11 = Reserved

0 BIAS_ENA 0 Enables the Normal bias current generator (for all analogue functions)

0 = Disabled

1 = Enabled

Register 01h Power Management (1)


265

WM8958

Pre-Production

REGISTER

ADDRESS

R2 (02h)

Power

Managemen t (2)

DESCRIPTION

14 TSHUT_ENA 1 Thermal sensor enable

0 = Disabled

1 = Enabled

13 TSHUT_OPDIS 1 Thermal shutdown control


0 = Disabled

1 = Enabled

11 OPCLK_ENA 0 GPIO Clock Output (OPCLK) Enable

0 = Disabled

1 = Enabled

9 MIXINL_ENA 0 Left Input Mixer Enable

(Enables MIXINL and RXVOICE input to MIXINL)

0 = Disabled

1 = Enabled

8 MIXINR_ENA 0 Right Input Mixer Enable

(Enables MIXINR and RXVOICE input to MIXINR)

0 = Disabled

1 = Enabled

7 IN2L_ENA 0 IN2L Input PGA Enable

0 = Disabled

1 = Enabled

6 IN1L_ENA 0 IN1L Input PGA Enable

0 = Disabled

1 = Enabled

5 IN2R_ENA 0 IN2R Input PGA Enable

0 = Disabled

1 = Enabled

4 IN1R_ENA 0 IN1R Input PGA Enable

0 = Disabled

1 = Enabled


REGISTER

ADDRESS

R3 (03h)

Power

Managemen t (3)

13 LINEOUT1N_E

NA

12 LINEOUT1P_E

NA

0

0

DESCRIPTION

11 LINEOUT2N_E

NA

10 LINEOUT2P_E

NA

9 SPKRVOL_EN

A w

0

0

0

LINEOUT1N Line Out and LINEOUT1NMIX Enable

0 = Disabled

1 = Enabled

LINEOUT1P Line Out and LINEOUT1PMIX Enable

0 = Disabled

1 = Enabled

LINEOUT2N Line Out and LINEOUT2NMIX Enable

0 = Disabled

1 = Enabled

LINEOUT2P Line Out and LINEOUT2PMIX Enable

0 = Disabled

1 = Enabled

SPKMIXR Mixer and SPKRVOL PGA Enable

0 = Disabled

1 = Enabled

Note that SPKMIXR and SPKRVOL are also enabled when SPKOUTR_ENA is set.


266

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

8 SPKLVOL_EN

A

7 MIXOUTLVOL_

ENA

6 MIXOUTRVOL

_ENA

5 MIXOUTL_EN

A

4 MIXOUTR_EN

A

0

0

0

0

0

SPKMIXL Mixer and SPKLVOL PGA Enable

0 = Disabled

1 = Enabled

Note that SPKMIXL and SPKLVOL are also enabled when SPKOUTL_ENA is set.

MIXOUTL Left Volume Control Enable

0 = Disabled

1 = Enabled

MIXOUTR Right Volume Control Enable

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

MIXOUTR Right Output Mixer Enable

0 = Disabled

1 = Enabled


REGISTER

ADDRESS

R4 (04h)

Power

Managemen t (4)

13 AIF2ADCL_EN

A

12 AIF2ADCR_EN

A

11 AIF1ADC2L_E

NA

10 AIF1ADC2R_E

NA

0

0

0

0

DESCRIPTION


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Enable AIF1ADC2 (Left) output path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1ADC2 (Right) output path (AIF1, Timeslot

1)

0 = Disabled

9 AIF1ADC1L_E

NA

8 AIF1ADC1R_E

NA

0

0

1 = Enabled

Enable AIF1ADC1 (Left) output path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Enable AIF1ADC1 (Right) output path (AIF1, Timeslot

0)

0 = Disabled

1 = Enabled

5 DMIC2L_ENA 0 Digital microphone DMICDAT2 Left channel enable

0 = Disabled

1 = Enabled

4 DMIC2R_ENA 0 Digital microphone DMICDAT2 Right channel enable

0 = Disabled

1 = Enabled

3 DMIC1L_ENA 0 Digital microphone DMICDAT1 Left channel enable

0 = Disabled

1 = Enabled

2 DMIC1R_ENA 0 Digital microphone DMICDAT1 Right channel enable

0 = Disabled w

WM8958


267

WM8958

Pre-Production

REGISTER

ADDRESS

1 = Enabled

1 ADCL_ENA 0 Left ADC Enable

0 = Disabled

1 = Enabled

0 ADCR_ENA 0 Right ADC Enable

0 = Disabled

1 = Enabled


DESCRIPTION

REGISTER

ADDRESS

R5 (05h)

Power

Managemen t (5)

DESCRIPTION

13 AIF2DACL_EN

A

12 AIF2DACR_EN

A

11 AIF1DAC2L_E

NA

10 AIF1DAC2R_E

NA

0

0

0

0


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Enable AIF1DAC2 (Left) input path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

Enable AIF1DAC2 (Right) input path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

9 AIF1DAC1L_E

NA

8 AIF1DAC1R_E

NA

0

0

Enable AIF1DAC1 (Left) input path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

Enable AIF1DAC1 (Right) input path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

3 DAC2L_ENA 0 Left DAC2 Enable

0 = Disabled

1 = Enabled

2 DAC2R_ENA 0 Right DAC2 Enable

0 = Disabled

1 = Enabled

1 DAC1L_ENA 0 Left DAC1 Enable

0 = Disabled

1 = Enabled

0 DAC1R_ENA 0 Right DAC1 Enable

0 = Disabled

1 = Enabled

Register 05h Power Management (5) w PP, August 2012, Rev 3.4

268

Pre-Production

REGISTER

ADDRESS

R6 (06h)

Power

Managemen t (6)

10:9 AIF3ADC_SRC

[1:0]

00

8:7 AIF2DAC_SRC

[1:0]

00

4:3 AIF3_ADCDAT

_SRC [1:0]

2 AIF2_ADCDAT

_SRC

1 AIF2_DACDAT

_SRC

0 AIF1_DACDAT

_SRC

00

0

0

0

DESCRIPTION

AIF3 Mono PCM output source select

00 = None

01 = AIF2ADC (Left) output path

10 = AIF2ADC (Right) output path

11 = Reserved

AIF2 input path select

00 = Left and Right inputs from AIF2

01 = Left input from AIF2; Right input from AIF3

10 = Left input from AIF3; Right input from AIF2

11 = Reserved




GPIO9/ADCDAT3 Source select

00 = AIF1 ADCDAT1

01 = AIF2 ADCDAT2

10 = DACDAT2

11 = AIF3 Mono PCM output

Note that GPIO9 must be configured as ADCDAT3.

ADCDAT2 Source select

0 = AIF2 ADCDAT2

1 = GPIO8/DACDAT3



0 = DACDAT2

1 = GPIO8/DACDAT3



0 = DACDAT1

1 = GPIO8/DACDAT3

Note that, for selection 1, the GPIO8 pin must be configured as DACDAT3.


REGISTER

ADDRESS

R21 (15h)

Input Mixer

(1)

8 IN1RP_MIXINR

_BOOST

7 IN1LP_MIXINL

_BOOST

0

0

DESCRIPTION

IN1RP Pin (PGA Bypass) to MIXINR Gain Boost.


IN1RP_MIXINR_VOL register.



IN1LP Pin (PGA Bypass) to MIXINL Gain Boost.


IN1LP_MIXINL_VOL register.




269

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

6 INPUTS_CLAM

P

0 Input pad VMID clamp

0 = Clamp de-activated

1 = Clamp activated

Register 15h Input Mixer (1)

REGISTER

ADDRESS

R24 (18h)

Left Line

Input 1&2

Volume

DESCRIPTION

Writing a 1 to this bit will cause IN1L and IN1R input

PGA volumes to be updated simultaneously

7 IN1L_MUTE 1 IN1L PGA Mute

0 = Disable Mute

1 = Enable Mute




Register 18h Left Line Input 1&2 Volume

REGISTER

ADDRESS

R25 (19h)

Left Line

Input 3&4

Volume

DESCRIPTION



7 IN2L_MUTE 1 IN2L PGA Mute

0 = Disable Mute

1 = Enable Mute




Register 19h Left Line Input 3&4 Volume

REGISTER

ADDRESS

R26 (1Ah)

Right Line

Input 1&2

Volume

DESCRIPTION



7 IN1R_MUTE 1 IN1R PGA Mute

0 = Disable Mute

1 = Enable Mute



4:0 IN1R_VOL 0_1011 IN1R Volume

[4:0]


Register 1Ah Right Line Input 1&2 Volume w PP, August 2012, Rev 3.4

270

Pre-Production

WM8958

REGISTER

ADDRESS

R27 (1Bh)

Right Line

Input 3&4

Volume

DESCRIPTION



7 IN2R_MUTE 1 IN2R PGA Mute

0 = Disable Mute

1 = Enable Mute



4:0 IN2R_VOL 0_1011 IN2R Volume

[4:0]


Register 1Bh Right Line Input 3&4 Volume

REGISTER

ADDRESS

R28 (1Ch)

Left Output

Volume

DESCRIPTION

8 HPOUT1_VU 0 Headphone Output PGA Volume Update

Writing a 1 to this bit will update HPOUT1LVOL and

HPOUT1RVOL volumes simultaneously.

7 HPOUT1L_ZC 0 HPOUT1LVOL (Left Headphone Output PGA) Zero

Cross Enable



6 HPOUT1L_MU

TE_N

1 HPOUT1LVOL (Left Headphone Output PGA) Mute

0 = Mute

1 = Un-mute

5:0 HPOUT1L_VO

L [5:0]

10_1101 HPOUT1LVOL (Left Headphone Output PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB

Register 1Ch Left Output Volume

REGISTER

ADDRESS

R29 (1Dh)

Right Output

Volume

DESCRIPTION

8 HPOUT1_VU 0 Headphone Output PGA Volume Update

Writing a 1 to this bit will update HPOUT1LVOL and

HPOUT1RVOL volumes simultaneously.

7 HPOUT1R_ZC 0 HPOUT1RVOL (Right Headphone Output PGA) Zero

Cross Enable



6 HPOUT1R_MU

TE_N

1 HPOUT1RVOL (Right Headphone Output PGA) Mute

0 = Mute

1 = Un-mute

5:0 HPOUT1R_VO

L [5:0]

10_1101 HPOUT1RVOL (Right Headphone Output PGA)

Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB w PP, August 2012, Rev 3.4

271

WM8958

Register 1Dh Right Output Volume

Pre-Production

REGISTER

ADDRESS

R30 (1Eh)

Line Outputs

Volume

6 LINEOUT1N_M

UTE

5 LINEOUT1P_M

UTE

4 LINEOUT1_VO

L

2 LINEOUT2N_M

UTE

1 LINEOUT2P_M

UTE

0 LINEOUT2_VO

L

1

1

0

1

1

0

DESCRIPTION


0 = Un-mute

1 = Mute


0 = Un-mute

1 = Mute


0 = 0dB

1 = -6dB

Applies to both LINEOUT1N and LINEOUT1P


0 = Un-mute

1 = Mute


0 = Un-mute

1 = Mute


0 = 0dB

1 = -6dB

Applies to both LINEOUT2N and LINEOUT2P

Register 1Eh Line Outputs Volume

REGISTER

ADDRESS

R31 (1Fh)

HPOUT2

Volume

DESCRIPTION

5 HPOUT2_MUT

E

1 HPOUT2 (Earpiece Driver) Mute

0 = Un-mute

1 = Mute

4 HPOUT2_VOL 0 HPOUT2 (Earpiece Driver) Volume

0 = 0dB

1 = -6dB

Register 1Fh HPOUT2 Volume

REGISTER

ADDRESS

R32 (20h)

Left OPGA

Volume

DESCRIPTION

8 MIXOUT_VU 0 Mixer Output PGA Volume Update

Writing a 1 to this bit will update MIXOUTLVOL and

MIXOUTRVOL volumes simultaneously.

7 MIXOUTL_ZC 0 MIXOUTLVOL (Left Mixer Output PGA) Zero Cross

Enable



6 MIXOUTL_MU

TE_N

1 MIXOUTLVOL (Left Mixer Output PGA) Mute

0 = Mute

1 = Un-mute

[5:0]


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps) w PP, August 2012, Rev 3.4

272

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

11_1111 = +6dB

Register 20h Left OPGA Volume

REGISTER

ADDRESS

R33 (21h)

Right OPGA

Volume

DESCRIPTION

8 MIXOUT_VU 0 Mixer Output PGA Volume Update

Writing a 1 to this bit will update MIXOUTLVOL and

MIXOUTRVOL volumes simultaneously.

7 MIXOUTR_ZC 0 MIXOUTRVOL (Right Mixer Output PGA) Zero Cross

Enable



6 MIXOUTR_MU

TE_N

1 MIXOUTLVOL (Right Mixer Output PGA) Mute

0 = Mute

1 = Un-mute

5:0 MIXOUTR_VO

L [5:0]

11_1001 MIXOUTRVOL (Right Mixer Output PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB

Register 21h Right OPGA Volume

REGISTER

ADDRESS

R34 (22h)

SPKMIXL

Attenuation

8 SPKAB_REF_

SEL

0

DESCRIPTION

6 DAC2L_SPKMI

XL_VOL

5 MIXINL_SPKMI

XL_VOL

4 IN1LP_SPKMI

XL_VOL

3 MIXOUTL_SPK

MIXL_VOL

2 DAC1L_SPKMI

XL_VOL

1:0 SPKMIXL_VOL

[1:0]

0

0

0

0

0

11

Selects Reference for Speaker in Class AB mode

0 = SPKVDD/2

1 = VMID

Left DAC2 to SPKMIXL Fine Volume Control

0 = 0dB

1 = -3dB

MIXINL (Left ADC bypass) to SPKMIXL Fine Volume

Control

0 = 0dB

1 = -3dB

IN1LP to SPKMIXL Fine Volume Control

0 = 0dB

1 = -3dB

Left Mixer Output to SPKMIXL Fine Volume Control

0 = 0dB

1 = -3dB

Left DAC1 to SPKMIXL Fine Volume Control

0 = 0dB

1 = -3dB

Left Speaker Mixer Volume Control

00 = 0dB

01 = -6dB

10 = -12dB

11 = Mute

Register 22h SPKMIXL Attenuation


273

WM8958

REGISTER

ADDRESS

R35 (23h)

SPKMIXR

Attenuation

8 SPKOUT_CLA

SSAB

6 DAC2R_SPKM

IXR_VOL

5 MIXINR_SPKM

IXR_VOL

4 IN1RP_SPKMI

XR_VOL

3 MIXOUTR_SP

KMIXR_VOL

2 DAC1R_SPKM

IXR_VOL

1:0 SPKMIXR_VO

L [1:0]

Pre-Production

0

0

0

0

0

0

11

DESCRIPTION

Speaker Class AB Mode Enable

0 = Class D mode

1 = Class AB mode

Right DAC2 to SPKMIXR Fine Volume Control

0 = 0dB

1 = -3dB

MIXINR (Right ADC bypass) to SPKMIXR Fine Volume

Control

0 = 0dB

1 = -3dB

IN1RP to SPKMIXR Fine Volume Control

0 = 0dB

1 = -3dB

Right Mixer Output to SPKMIXR Fine Volume Control

0 = 0dB

1 = -3dB

Right DAC1 to SPKMIXR Fine Volume Control

0 = 0dB

1 = -3dB

Right Speaker Mixer Volume Control

00 = 0dB

01 = -6dB

10 = -12dB

11 = Mute

Register 23h SPKMIXR Attenuation

REGISTER

ADDRESS

R36 (24h)

SPKOUT

Mixers

5 IN2LRP_TO_S

PKOUTL

4 SPKMIXL_TO_

SPKOUTL

3 SPKMIXR_TO_

SPKOUTL

2 IN2LRP_TO_S

PKOUTR

1 SPKMIXL_TO_

SPKOUTR

0 SPKMIXR_TO_

SPKOUTR

Register 24h SPKOUT Mixers

0

1

0

0

0

1

DESCRIPTION

Direct Voice (VRXN-VRXP) to Left Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXL Left Speaker Mixer to Left Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXR Right Speaker Mixer to Left Speaker Mute

0 = Mute

1 = Un-mute

Direct Voice (VRXN-VRXP) to Right Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXL Left Speaker Mixer to Right Speaker Mute

0 = Mute

1 = Un-mute

SPKMIXR Right Speaker Mixer to Right Speaker Mute

0 = Mute


274

Pre-Production

REGISTER

ADDRESS

R37 (25h)

ClassD

5:3 SPKOUTL_BO

OST [2:0]

DESCRIPTION

2:0 SPKOUTR_BO

OST [2:0]

000

000

Left Speaker Gain Boost

000 = 1.00x boost (+0dB)

001 = 1.19x boost (+1.5dB)

010 = 1.41x boost (+3.0dB)

011 = 1.68x boost (+4.5dB)

100 = 2.00x boost (+6.0dB)

101 = 2.37x boost (+7.5dB)

110 = 2.81x boost (+9.0dB)

111 = 3.98x boost (+12.0dB)

Right Speaker Gain Boost

000 = 1.00x boost (+0dB)

001 = 1.19x boost (+1.5dB)

010 = 1.41x boost (+3.0dB)

011 = 1.68x boost (+4.5dB)

100 = 2.00x boost (+6.0dB)

101 = 2.37x boost (+7.5dB)

110 = 2.81x boost (+9.0dB)

111 = 3.98x boost (+12.0dB)

Register 25h ClassD

REGISTER

ADDRESS

R38 (26h)

Speaker

Volume Left

DESCRIPTION

8 SPKOUT_VU 0 Speaker Output PGA Volume Update

Writing a 1 to this bit will update SPKLVOL and

SPKRVOL volumes simultaneously.

7 SPKOUTL_ZC 0 SPKLVOL (Left Speaker Output PGA) Zero Cross

Enable


6 SPKOUTL_MU

TE_N

1


SPKLVOL (Left Speaker Output PGA) Mute

0 = Mute

5:0 SPKOUTL_VO

L [5:0]

1 = Un-mute

11_1001 SPKLVOL (Left Speaker Output PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB

Register 26h Speaker Volume Left

WM8958

REGISTER

ADDRESS

R39 (27h)

Speaker

Volume

Right

DESCRIPTION

8 SPKOUT_VU 0 Speaker Output PGA Volume Update

Writing a 1 to this bit will update SPKLVOL and

SPKRVOL volumes simultaneously.

7 SPKOUTR_ZC 0 SPKRVOL (Right Speaker Output PGA) Zero Cross

Enable



6 SPKOUTR_MU

TE_N

1 SPKRVOL (Right Speaker Output PGA) Mute

0 = Mute


275

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

5:0 SPKOUTR_VO

L [5:0]

11_1001 SPKRVOL (Right Speaker Output PGA) Volume


00_0000 = -57dB

00_0001 = -56dB

… (1dB steps)

11_1111 = +6dB

Register 27h Speaker Volume Right

REGISTER

ADDRESS

R40 (28h)

Input Mixer

(2)

7 IN2LP_TO_IN2

L

0

DESCRIPTION

6 IN2LN_TO_IN2

L

5 IN1LP_TO_IN1

L

4 IN1LN_TO_IN1

L

3 IN2RP_TO_IN2

R

2 IN2RN_TO_IN2

R

1 IN1RP_TO_IN1

R

0 IN1RN_TO_IN1

R

0

0

0

0

0

0

0




Note that VMID_BUF_ENA must be set when using

IN2L connected to VMID.


0 = Not connected






IN1L connected to VMID.


0 = Not connected






IN2R connected to VMID.


0 = Not connected






IN1R connected to VMID.


0 = Not connected


Register 28h Input Mixer (2) w PP, August 2012, Rev 3.4

276

Pre-Production

REGISTER

ADDRESS

R41 (29h)

Input Mixer

(3)

8 IN2L_TO_MIXI

NL

7 IN2L_MIXINL_

VOL

5 IN1L_TO_MIXI

NL

4 IN1L_MIXINL_

VOL

2:0 MIXOUTL_MIX

INL_VOL [2:0]

Register 29h Input Mixer (3)

REGISTER

ADDRESS

R42 (2Ah)

Input Mixer

(4)

8 IN2R_TO_MIXI

NR

7 IN2R_MIXINR_

VOL

5 IN1R_TO_MIXI

NR

4 IN1R_MIXINR_

VOL

2:0 MIXOUTR_MIX

INR_VOL [2:0]

0

0

0

0

000

DESCRIPTION


0 = Mute

1 = Un-Mute


0 = 0dB

1 = +30dB


0 = Mute

1 = Un-Mute


0 = 0dB

1 = +30dB

Record Path MIXOUTR to MIXINR Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB

Register 2Ah Input Mixer (4)

0

0

0

0

000

DESCRIPTION


0 = Mute

1 = Un-Mute


0 = 0dB

1 = +30dB


0 = Mute

1 = Un-Mute


0 = 0dB

1 = +30dB

Record Path MIXOUTL to MIXINL Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB


277

WM8958

REGISTER

ADDRESS

R43 (2Bh)

Input Mixer

(5)

8:6 IN1LP_MIXINL

_VOL [2:0]

2:0 IN2LRP_MIXIN

L_VOL [2:0]

Register 2Bh Input Mixer (5)

REGISTER

ADDRESS

R44 (2Ch)

Input Mixer

(6)

8:6 IN1RP_MIXINR

_VOL [2:0]

2:0 IN2LRP_MIXIN

R_VOL [2:0]

000

000

DESCRIPTION

IN1RP Pin (PGA Bypass) to MIXINR Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB


When IN1RP_MIXINR_BOOST is set, then the maximum gain setting is increased to +15dB, ie. 111 =

+15dB.

Note that VMID_BUF_ENA must be set when using the

IN1RP (PGA Bypass) input to MIXINR.

RXVOICE Differential Input (VRXP-VRXN) to MIXINR

Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB

Register 2Ch Input Mixer (6)

000

000

Pre-Production

DESCRIPTION

IN1LP Pin (PGA Bypass) to MIXINL Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB


When IN1LP_MIXINL_BOOST is set, then the maximum gain setting is increased to +15dB, ie. 111 =

+15dB.


IN1LP (PGA Bypass) input to MIXINL.

RXVOICE Differential Input (VRXP-VRXN) to MIXINL

Gain and Mute

000 = Mute

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB w PP, August 2012, Rev 3.4

278

Pre-Production

REGISTER

ADDRESS

R45 (2Dh)

Output Mixer

(1)

8 DAC1L_TO_H

POUT1L

7 MIXINR_TO_M

IXOUTL

6 MIXINL_TO_MI

XOUTL

5 IN2RN_TO_MI

XOUTL

4 IN2LN_TO_MI

XOUTL

3 IN1R_TO_MIX

OUTL

2 IN1L_TO_MIX

OUTL

1 IN2LP_TO_MI

XOUTL

0

0

0

0

0

0

0

0

0

DESCRIPTION

HPOUT1LVOL (Left Headphone Output PGA) Input

Select

0 = MIXOUTL

1 = DAC1L

MIXINR Output (Right ADC bypass) to MIXOUTL Mute

0 = Mute

1 = Un-mute

MIXINL Output (Left ADC bypass) to MIXOUTL Mute

0 = Mute

1 = Un-mute

IN2RN to MIXOUTL Mute

0 = Mute

1 = Un-mute


IN2RN input to MIXOUTL.

IN2LN to MIXOUTL Mute

0 = Mute

1 = Un-mute


IN2LN input to MIXOUTL.

IN1R PGA Output to MIXOUTL Mute

0 = Mute

1 = Un-mute

IN1L PGA Output to MIXOUTL Mute

0 = Mute

1 = Un-mute

IN2LP to MIXOUTL Mute

0 = Mute

1 = Un-mute


IN2LP input to MIXOUTL.

Left DAC1 to MIXOUTL Mute

0 = Mute

1 = Un-mute

WM8958

0 DAC1L_TO_MI

XOUTL

Register 2Dh Output Mixer (1)

REGISTER

ADDRESS

R46 (2Eh)

Output Mixer

(2)

8 DAC1R_TO_H

POUT1R

7 MIXINL_TO_MI

XOUTR

6 MIXINR_TO_M

IXOUTR

0

0

0

DESCRIPTION

HPOUT1RVOL (Right Headphone Output PGA) Input

Select

0 = MIXOUTR

1 = DAC1R

MIXINL Output (Left ADC bypass) to MIXOUTR Mute

0 = Mute

1 = Un-mute

MIXINR Output (Right ADC bypass) to MIXOUTR Mute

0 = Mute


279

WM8958

REGISTER

ADDRESS

5 IN2LN_TO_MI

XOUTR

4 IN2RN_TO_MI

XOUTR

3 IN1L_TO_MIX

OUTR

2 IN1R_TO_MIX

OUTR

1 IN2RP_TO_MI

XOUTR

0 DAC1R_TO_MI

XOUTR

0

0

0

0

0

0

Pre-Production

DESCRIPTION

IN2LN to MIXOUTR Mute

0 = Mute

1 = Un-mute


IN2LN input to MIXOUTR.

IN2RN to MIXOUTR Mute

0 = Mute

1 = Un-mute


IN2RN input to MIXOUTR.

IN1L PGA Output to MIXOUTR Mute

0 = Mute

1 = Un-mute

IN1R PGA Output to MIXOUTR Mute

0 = Mute

1 = Un-mute

IN2RP to MIXOUTR Mute

0 = Mute

1 = Un-mute


IN2RP input to MIXOUTR.

Right DAC1 to MIXOUTR Mute

0 = Mute

1 = Un-mute

Register 2Eh Output Mixer (2)

REGISTER

ADDRESS

R47 (2Fh)

Output Mixer

(3)

11:9 IN2LP_MIXOU

TL_VOL [2:0]

8:6 IN2LN_MIXOU

TL_VOL [2:0]

5:3 IN1R_MIXOUT

L_VOL [2:0]

2:0 IN1L_MIXOUT

L_VOL [2:0]

000

000

000

000

DESCRIPTION

IN2LP to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2LN to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1R PGA Output to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1L PGA Output to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

Register 2Fh Output Mixer (3) w PP, August 2012, Rev 3.4

280

Pre-Production

REGISTER

ADDRESS

R48 (30h)

Output Mixer

(4)

11:9 IN2RP_MIXOU

TR_VOL [2:0]

8:6 IN2RN_MIXOU

TR_VOL [2:0]

5:3 IN1L_MIXOUT

R_VOL [2:0]

2:0 IN1R_MIXOUT

R_VOL [2:0]

000

000

000

000

DESCRIPTION

IN2RP to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2RN to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1L PGA Output to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN1R PGA Output to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

Register 30h Output Mixer (4)

REGISTER

ADDRESS

R49 (31h)

Output Mixer

(5)

11:9 DAC1L_MIXO

UTL_VOL [2:0]

8:6 IN2RN_MIXOU

TL_VOL [2:0]

5:3 MIXINR_MIXO

UTL_VOL [2:0]

000

000

000

DESCRIPTION

Left DAC1 to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2RN to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

MIXINR Output (Right ADC bypass) to MIXOUTL

Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB


281

WM8958

REGISTER

ADDRESS

2:0 MIXINL_MIXO

UTL_VOL [2:0]

000

Pre-Production

DESCRIPTION

MIXINL Output (Left ADC bypass) to MIXOUTL Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB


REGISTER

ADDRESS

R50 (32h)

Output Mixer

(6)

11:9 DAC1R_MIXO

UTR_VOL [2:0]

8:6 IN2LN_MIXOU

TR_VOL [2:0]

5:3 MIXINL_MIXO

UTR_VOL [2:0]

2:0 MIXINR_MIXO

UTR_VOL [2:0]

000

000

000

000

DESCRIPTION

Right DAC1 to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

IN2LN to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

MIXINL Output (Left ADC bypass) to MIXOUTR Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB

MIXINR Output (Right ADC bypass) to MIXOUTR

Volume


X00 = 0dB

X01 = -3dB

X10 = -6dB

X11 = -9dB


REGISTER

ADDRESS

R51 (33h)

HPOUT2

Mixer

5 IN2LRP_TO_H

POUT2

4 MIXOUTLVOL_

TO_HPOUT2

3 MIXOUTRVOL

_TO_HPOUT2

0

0

0

DESCRIPTION

Direct Voice (VRXN-VRXP) to Earpiece Driver

0 = Mute

1 = Un-mute

MIXOUTLVOL (Left Output Mixer PGA) to Earpiece

Driver

0 = Mute

1 = Un-mute

MIXOUTRVOL (Right Output Mixer PGA) to Earpiece

Driver

0 = Mute

1 = Un-mute

Register 33h HPOUT2 Mixer w PP, August 2012, Rev 3.4

282

Pre-Production

REGISTER

ADDRESS

R52 (34h)

Line Mixer

(1)

6 MIXOUTL_TO_

LINEOUT1N

5 MIXOUTR_TO

_LINEOUT1N

4 LINEOUT1_MO

DE

2 IN1R_TO_LINE

OUT1P

1 IN1L_TO_LINE

OUT1P

0 MIXOUTL_TO_

LINEOUT1P

0

0

0

0

0

0

DESCRIPTION

MIXOUTL to Single-Ended Line Output on LINEOUT1N

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 1)

MIXOUTR to Single-Ended Line Output on LINEOUT1N

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 1)


0 = Differential

1 = Single-Ended

IN1R Input PGA to Differential Line Output on

LINEOUT1

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 0)

IN1L Input PGA to Differential Line Output on

LINEOUT1

0 = Mute

1 = Un-mute

(LINEOUT1_MODE = 0)

Differential Mode (LINEOUT1_MODE = 0):

MIXOUTL to Differential Output on LINEOUT1

0 = Mute

1 = Un-mute

Single Ended Mode (LINEOUT1_MODE = 1):

MIXOUTL to Single-Ended Line Output on LINEOUT1P

0 = Mute

1 = Un-mute

WM8958

Register 34h Line Mixer (1)

REGISTER

ADDRESS

R53 (35h)

Line Mixer

(2)

6 MIXOUTR_TO

_LINEOUT2N

5 MIXOUTL_TO_

LINEOUT2N

4 LINEOUT2_MO

DE

2 IN1L_TO_LINE

OUT2P

0

0

0

0

DESCRIPTION

MIXOUTR to Single-Ended Line Output on LINEOUT2N

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 1)

MIXOUTL to Single-Ended Line Output on LINEOUT2N

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 1)


0 = Differential

1 = Single-Ended

IN1L Input PGA to Differential Line Output on

LINEOUT2

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 0) w PP, August 2012, Rev 3.4

283

WM8958

REGISTER

ADDRESS

1 IN1R_TO_LINE

OUT2P

0 MIXOUTR_TO

_LINEOUT2P

0

0

Pre-Production

DESCRIPTION

IN1R Input PGA to Differential Line Output on

LINEOUT2

0 = Mute

1 = Un-mute

(LINEOUT2_MODE = 0)

Differential Mode (LINEOUT2_MODE = 0):

MIXOUTR to Differential Output on LINEOUT2

0 = Mute

1 = Un-mute

Single-Ended Mode (LINEOUT2_MODE = 0):

MIXOUTR to Single-Ended Line Output on LINEOUT2P

0 = Mute

1 = Un-mute

Register 35h Line Mixer (2)

REGISTER

ADDRESS

R54 (36h)

Speaker

Mixer

9 DAC2L_TO_S

PKMIXL

8 DAC2R_TO_S

PKMIXR

7 MIXINL_TO_S

PKMIXL

6 MIXINR_TO_S

PKMIXR

5 IN1LP_TO_SP

KMIXL

4 IN1RP_TO_SP

KMIXR

3 MIXOUTL_TO_

SPKMIXL

2 MIXOUTR_TO

_SPKMIXR

1 DAC1L_TO_S

PKMIXL

0 DAC1R_TO_S

PKMIXR

Register 36h Speaker Mixer w

0

0

0

0

0

0

0

0

0

0

DESCRIPTION


0 = Mute

1 = Un-mute


0 = Mute

1 = Un-mute

MIXINL (Left ADC bypass) to SPKMIXL Mute

0 = Mute

1 = Un-mute

MIXINR (Right ADC bypass) to SPKMIXR Mute

0 = Mute

1 = Un-mute

IN1LP to SPKMIXL Mute

0 = Mute

1 = Un-mute


IN1LP input to SPKMIXL.

IN1RP to SPKMIXR Mute

0 = Mute

1 = Un-mute


IN1RP input to SPKMIXR.

Left Mixer Output to SPKMIXL Mute

0 = Mute

1 = Un-mute

Right Mixer Output to SPKMIXR Mute

0 = Mute

1 = Un-mute


0 = Mute

1 = Un-mute


0 = Mute

1 = Un-mute


284

Pre-Production

REGISTER

ADDRESS

R55 (37h)

Additional

Control

DESCRIPTION

7 LINEOUT1_FB 0 Enable ground loop noise feedback on LINEOUT1

0 = Disabled

1 = Enabled

6 LINEOUT2_FB 0 Enable ground loop noise feedback on LINEOUT2

0 = Disabled

1 = Enabled

(Disabled Outputs)

0 = 20k  from buffered VMID to output

1 = 500  from buffered VMID to output

Register 37h Additional Control

REGISTER

ADDRESS

R56 (38h)

AntiPOP (1)

7 LINEOUT_VMI

D_BUF_ENA

0

DESCRIPTION

6 HPOUT2_IN_E

NA

5 LINEOUT1_DI

SCH

4 LINEOUT2_DI

SCH

0

0

0

Enables VMID reference for line outputs in singleended mode

0 = Disabled

1 = Enabled

HPOUT2MIX Mixer and Input Stage Enable

0 = Disabled

1 = Enabled

Discharges LINEOUT1P and LINEOUT1N outputs

0 = Not active


Discharges LINEOUT2P and LINEOUT2N outputs

0 = Not active


Register 38h AntiPOP (1)

WM8958

REGISTER

ADDRESS

R57 (39h)

AntiPOP (2)

DESCRIPTION

6:5 VMID_RAMP

[1:0]

3 VMID_BUF_EN

A

2 STARTUP_BIA

S_ENA

00

0

0

VMID soft start enable / slew rate control

00 = Normal slow start

01 = Normal fast start

10 = Soft slow start

11 = Soft fast start

If VMID_RAMP = 1X is selected for VMID start-up or shut-down, then the soft-start circuit must be reset by setting VMID_RAMP=00 after VMID is disabled, before

VMID is re-enabled. VMID is disabled / enabled using the VMID_SEL register.

VMID Buffer Enable

0 = Disabled


Enables the Start-Up bias current generator

0 = Disabled

1 = Enabled

1 BIAS_SRC 0 Selects the bias current source

0 = Normal bias

1 = Start-Up bias

0 VMID_DISCH 0 Connects VMID to ground w PP, August 2012, Rev 3.4

285

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

0 = Disabled

1 = Enabled

Register 39h AntiPOP (2)

REGISTER

ADDRESS

R59 (3Bh)

LDO 1

DESCRIPTION

3:1 LDO1_VSEL

[2:0]

110 LDO1 Output Voltage Select


000 = 2.4V

001 = 2.5V

010 = 2.6V

011 = 2.7V

100 = 2.8V

101 = 2.9V

110 = 3.0V

111 = 3.1V

0 LDO1_DISCH 1 LDO1 Discharge Select



Register 3Bh LDO 1

REGISTER

ADDRESS

R60 (3Ch)

LDO 2

DESCRIPTION

2:1 LDO2_VSEL

[1:0]

10 LDO2 Output Voltage Select


00 = Reserved

01 = 1.1V

10 = 1.2V

11 = 1.3V

0 LDO2_DISCH 1 LDO2 Discharge Select



Register 3Ch LDO 2

REGISTER

ADDRESS

R61 (3Dh)

MICBIAS1

DESCRIPTION

5 MICB1_RATE 1 Microphone Bias 1 Rate



4 MICB1_MODE 1 Microphone Bias 1 Mode

0 = Regulator mode

1 = Bypass mode w PP, August 2012, Rev 3.4

286

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

3:1 MICB1_LVL

[2:0]

100 Microphone Bias 1 Voltage Control


000 = 1.5V

001 = 1.8V

010 = 1.9V

011 = 2.0V

100 = 2.2V

101 = 2.4V

110 = 2.5V

111 = 2.6V

0 MICB1_DISCH 1 Microphone Bias 1 Discharge



Register 3Dh MICBIAS1

REGISTER

ADDRESS

R62 (3Eh)

MICBIAS2

DESCRIPTION

5 MICB2_RATE 1 Microphone Bias 2 Rate



4 MICB2_MODE 1 Microphone Bias 2 Mode

0 = Regulator mode

1 = Bypass mode

3:1 MICB2_LVL

[2:0]

100 Microphone Bias 2 Voltage Control


000 = 1.5V

001 = 1.8V

010 = 1.9V

011 = 2.0V

100 = 2.2V

101 = 2.4V

110 = 2.5V

111 = 2.6V

0 MICB2_DISCH 1 Microphone Bias 2 Discharge



Register 3Eh MICBIAS2

REGISTER

ADDRESS

R76 (4Ch)

Charge

Pump (1)

DESCRIPTION

15 CP_ENA 0 Enable charge-pump digits

0 = Disable

1 = Enable

Register 4Ch Charge Pump (1)

WM8958

REGISTER

ADDRESS

R77 (4Dh)

Charge

Pump (2)

DESCRIPTION

15 CP_DISCH 1 Charge Pump Discharge Select

0 = Charge Pump outputs floating when disabled

1 = Charge Pump outputs discharged when disabled

Register 4Dh Charge Pump (2) w PP, August 2012, Rev 3.4

287

WM8958

Pre-Production

REGISTER

ADDRESS

R81 (51h)

Class W (1)

DESCRIPTION

9:8 CP_DYN_SRC

_SEL [1:0]

00 Selects the digital audio source for envelope tracking



10 = AIF2, DAC data

11 = Reserved

0 CP_DYN_PWR 0 Enable dynamic charge pump power control

0 = charge pump controlled by volume register settings

(Class G)

1 = charge pump controlled by real-time audio level

(Class W)

Register 51h Class W (1)

REGISTER

ADDRESS

R84 (54h)

DC Servo

(1)

13 DCS_TRIG_SI

NGLE_1

0

DESCRIPTION

12 DCS_TRIG_SI

NGLE_0

9 DCS_TRIG_SE

RIES_1

8 DCS_TRIG_SE

RIES_0

5 DCS_TRIG_ST

ARTUP_1

4 DCS_TRIG_ST

ARTUP_0

3 DCS_TRIG_DA

C_WR_1

2 DCS_TRIG_DA

C_WR_0

1 DCS_ENA_CH

AN_1

0 DCS_ENA_CH

AN_0

0

0

0

0

0

0

0

0

0

Writing 1 to this bit selects a single DC offset correction for HPOUT1R.


Writing 1 to this bit selects a single DC offset correction for HPOUT1L.


Writing 1 to this bit selects a series of DC offset corrections for HPOUT1R.


DAC Write correction is in progress.

Writing 1 to this bit selects a series of DC offset corrections for HPOUT1L.



Writing 1 to this bit selects Start-Up DC Servo mode for

HPOUT1R.



Writing 1 to this bit selects Start-Up DC Servo mode for

HPOUT1L.



Writing 1 to this bit selects DAC Write DC Servo mode for HPOUT1R.



Writing 1 to this bit selects DAC Write DC Servo mode for HPOUT1L.




0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Register 54h DC Servo (1) w PP, August 2012, Rev 3.4

288

Pre-Production

REGISTER

ADDRESS

R85 (55h)

DC Servo

(2)

DESCRIPTION

11:5 DCS_SERIES_

NO_01 [6:0]

3:0 DCS_TIMER_P

ERIOD_01

[3:0]

010_1010 Number of DC Servo updates to perform in a series event.

0 = 1 update

1 = 2 updates

...

127 = 128 updates

1010 Time between periodic updates. Time is calculated as

0.251s x (2^PERIOD), where PERIOD = DCS_TIMER_PERIOD_01.

0000 = Off

0001 = 0.502s

….

1010 = 257s (4min 17s)

1111 = 8225s (2hr 17min)

Register 55h DC Servo (2)

REGISTER

ADDRESS

R87 (57h)

DC Servo

(4)

DESCRIPTION

15:8 DCS_DAC_WR

_VAL_1 [7:0]

7:0 DCS_DAC_WR

_VAL_0 [7:0]

0000_0000 Writing to this field sets the DC Offset value for

HPOUT1R in DAC Write DC Servo mode.


HPOUT1R.


LSB is 0.25mV.


0000_0000 Writing to this field sets the DC Offset value for

HPOUT1L in DAC Write DC Servo mode.


HPOUT1L.


LSB is 0.25mV.


Register 57h DC Servo (4)

REGISTER

ADDRESS

R88 (58h)

DC Servo

Readback

9:8 DCS_CAL_CO

MPLETE [1:0]

00

DESCRIPTION

5:4 DCS_DAC_WR

_COMPLETE

[1:0]

1:0 DCS_STARTU

P_COMPLETE

[1:0]

00

00

DC Servo Complete status

0 = DAC Write or Start-Up DC Servo mode not completed.

1 = DAC Write or Start-Up DC Servo mode complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

DC Servo DAC Write status

0 = DAC Write DC Servo mode not completed.

1 = DAC Write DC Servo mode complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

DC Servo Start-Up status

0 = Start-Up DC Servo mode not completed.

1 = Start-Up DC Servo mode complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

Register 58h DC Servo Readback w

WM8958


289

WM8958

REGISTER

ADDRESS

R96 (60h)

Analogue

HP (1)

7 HPOUT1L_RM

V_SHORT

6 HPOUT1L_OU

TP

5 HPOUT1L_DL

Y

3 HPOUT1R_RM

V_SHORT

2 HPOUT1R_OU

TP

1 HPOUT1R_DL

Y

0

0

0

0

0

0

Pre-Production

DESCRIPTION

Removes HPOUT1L short

0 = HPOUT1L short enabled

1 = HPOUT1L short removed

For normal operation, this bit should be set as the final step of the HPOUT1L Enable sequence.

Enables HPOUT1L output stage

0 = Disabled

1 = Enabled


Enables HPOUT1L intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1 after the output signal path has been configured, and before

DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1L_ENA.

Removes HPOUT1R short

0 = HPOUT1R short enabled

1 = HPOUT1R short removed

For normal operation, this bit should be set as the final step of the HPOUT1R Enable sequence.

Enables HPOUT1R output stage

0 = Disabled

1 = Enabled


Enables HPOUT1R intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1 after the output signal path has been configured, and before

DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1R_ENA.

Register 60h Analogue HP (1)

REGISTER

ADDRESS

R208 (D0h)

Mic Detect 1

15:12 MICD_BIAS_S

TARTTIME

[3:0] w

DESCRIPTION

0101 Mic Detect Bias Startup Delay

(If MICBIAS2 is not enabled already, this field selects the delay time allowed for MICBIAS2 to startup prior to performing the MICDET function.)


0001 = 0.25ms

0010 = 0.5ms

0011 = 1ms

0100 = 2ms

0101 = 4ms

0110 = 8ms

0111 = 16ms

1000 = 32ms

1001 = 64ms

1010 = 128ms


290

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

11:8 MICD_RATE

[3:0]

0110

1011 = 256ms

1100 to 1111 = 512ms

Mic Detect Rate

(Selects the delay between successive Mic Detect measurements.)


0001 = 0.25ms

0010 = 0.5ms

0011 = 1ms

0100 = 2ms

0101 = 4ms

0110 = 8ms

0111 = 16ms

1000 = 32ms

1001 = 64ms

1010 = 128ms

1011 = 256ms

1100 to 1111 = 512ms

1 MICD_DBTIME 0 Mic Detect De-bounce

0 = 2 measurements

1 = 4 measurements

0 MICD_ENA 0 Mic Detect Enable

0 = Disabled

1 = Enabled

Register D0h Mic Detect 1

REGISTER

ADDRESS

R209 (D1h)

Mic Detect 2

DESCRIPTION

7:0 MICD_LVL_SE

L [7:0]

0111_1111 Mic Detect Level Select

(enables Mic Detection in specific impedance ranges)

[7] = Not used - must be set to 0

[6] = Enable >475 ohm detection







Note that the impedance values quoted assume that a microphone (475ohm-30kohm) is also present on the

MICDET pin.



291

WM8958

Pre-Production

REGISTER

ADDRESS

R210 (D2h)

Mic Detect 3

DESCRIPTION

[8:0] 00

Mic Detect Level

(indicates the measured impedance)

[8] = Not used

[7] = >475 ohm, <30k ohm

[6] = 326 ohm

[5] = 152 ohm

[4] = 77 ohm

[3] = 47.6 ohm

[2] = 29.4 ohm

[1] = 14 ohm

[0] = <2 ohm

Note that the impedance values quoted assume that a microphone (475ohm-30kohm) is also present on the

MICDET pin.

1 MICD_VALID 0 Mic Detect Data Valid

0 = Not Valid

1 = Valid

0 MICD_STS 0 Mic Detect Status

0 = No Mic Accessory present (impedance is >30k ohm)

1 = Mic Accessory is present (impedance is <30k ohm)


REGISTER

ADDRESS

R256

(0100h)

Chip

Revision

3:0 CHIP_REV

[3:0]

Register 0100h Chip Revision

Chip revision

DESCRIPTION

REGISTER

ADDRESS

R257

(0101h)

Control

Interface

DESCRIPTION

2 AUTO_INC 1 Enables address auto-increment

Register 0101h Control Interface

0 = Disabled

1 = Enabled

REGISTER

ADDRESS

R272

(0110h)

Write

Sequencer

Ctrl (1)

DESCRIPTION

15 WSEQ_ENA 0 Write Sequencer Enable.

0 = Disabled

1 = Enabled

9 WSEQ_ABOR

T

0 Writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface.

8 WSEQ_START 0 Writing a 1 to this bit starts the write sequencer at the index location selected by WSEQ_START_INDEX. The sequence continues until it reaches an “End of sequence” flag. At the end of the sequence, this bit will be reset by the Write Sequencer. w PP, August 2012, Rev 3.4

292

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

6:0 WSEQ_START

_INDEX [6:0]

000_0000 Sequence Start Index. This field determines the memory location of the first command in the selected sequence. There are 127 Write Sequencer RAM addresses:




….

7Fh = WSEQ_ADDR127 (R12796)

Register 0110h Write Sequencer Ctrl (1)

REGISTER

ADDRESS

R273

(0111h)

Write

Sequencer

Ctrl (2)

DESCRIPTION

8 WSEQ_BUSY 0 Sequencer Busy flag (Read Only).

0 = Sequencer idle

1 = Sequencer busy

Note: it is not possible to write to control registers via the control interface while the Sequencer is Busy.

6:0 WSEQ_CURR

ENT_INDEX

[6:0]

000_0000 Sequence Current Index. This indicates the memory location of the most recently accessed command in the write sequencer memory.

Coding is the same as WSEQ_START_INDEX.

Register 0111h Write Sequencer Ctrl (2)

REGISTER

ADDRESS

R512

(0200h)

AIF1

Clocking (1)

DESCRIPTION

4:3 AIF1CLK_SRC

[1:0]

00 AIF1CLK Source Select

00 = MCLK1

01 = MCLK2

10 = FLL1

11 = FLL2

2 AIF1CLK_INV 0 AIF1CLK Invert



1 AIF1CLK_DIV 0 AIF1CLK Divider

0 = AIF1CLK

1 = AIF1CLK / 2

0 AIF1CLK_ENA 0 AIF1CLK Enable

0 = Disabled

1 = Enabled

Register 0200h AIF1 Clocking (1)


293

WM8958

REGISTER

ADDRESS

R513

(0201h)

AIF1

Clocking (2)

5:3 AIF1DAC_DIV

[2:0]

000

2:0 AIF1ADC_DIV

[2:0]

000

Pre-Production

DESCRIPTION

Selects the AIF1 input path sample rate relative to the

AIF1 output path sample rate.


000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

Selects the AIF1 output path sample rate relative to the

AIF1 input path sample rate.


000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved


REGISTER

ADDRESS

R516

(0204h)

AIF2

Clocking (1)

DESCRIPTION

4:3 AIF2CLK_SRC

[1:0]

00 AIF2CLK Source Select

00 = MCLK1

01 = MCLK2

10 = FLL1

11 = FLL2

2 AIF2CLK_INV 0 AIF2CLK Invert



1 AIF2CLK_DIV 0 AIF2CLK Divider

0 = AIF2CLK

1 = AIF2CLK / 2

0 AIF2CLK_ENA 0 AIF2CLK Enable

0 = Disabled

1 = Enabled

Register 0204h AIF2 Clocking (1) w PP, August 2012, Rev 3.4

294

Pre-Production

REGISTER

ADDRESS

R517

(0205h)

AIF2

Clocking (2)

5:3 AIF2DAC_DIV

[2:0]

2:0 AIF2ADC_DIV

[2:0]

000

000

DESCRIPTION

Selects the AIF2 input path sample rate relative to the

AIF2 output path sample rate.


000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

Selects the AIF2 output path sample rate relative to the

AIF2 input path sample rate.


000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved


REGISTER

ADDRESS

R520

(0208h)

Clocking (1)

DESCRIPTION

14 DSP2CLK_EN

A

0 MBC Processor Clock Enable

0 = Disabled

1 = Enabled

4 TOCLK_ENA 0 Slow Clock (TOCLK) Enable

0 = Disabled

3 AIF1DSPCLK_

ENA

2 AIF2DSPCLK_

ENA

1 SYSDSPCLK_

ENA

0

0

0

1 = Enabled



0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

0 SYSCLK_SRC 0 SYSCLK Source Select

0 = AIF1CLK

1 = AIF2CLK

Register 0208h Clocking (1)


295

WM8958

REGISTER

ADDRESS

R521

(0209h)

Clocking (2)

10:8 TOCLK_DIV

[2:0]

000

6:4 DBCLK_DIV

[2:0]

000

2:0 OPCLK_DIV

[2:0]

000

Pre-Production

DESCRIPTION

Slow Clock (TOCLK ) Divider

(Sets TOCLK rate relative to 256kHz.)


001 = Divide by 512 (500Hz)

010 = Divide by 1024 (250Hz)

011 = Divide by 2048 (125Hz)

100 = Divide by 4096 (62.5Hz)

101 = Divide by 8192 (31.2Hz)

110 = Divide by 16384 (15.6Hz)

111 = Divide by 32768 (7.8Hz)

De-bounce Clock (DBCLK) Divider

(Sets DBCLK rate relative to 256kHz.)


001 = Divide by 2048 (125Hz)

010 = Divide by 4096 (62.5Hz)

011 = Divide by 8192 (31.2Hz)

100 = Divide by 16384 (15.6Hz)

101 = Divide by 32768 (7.8Hz)

110 = Divide by 65536 (3.9Hz)

111 = Divide by 131072 (1.95Hz)


000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

Register 0209h Clocking (2)

REGISTER

ADDRESS

R528

(0210h)

AIF1 Rate

DESCRIPTION

0000 = 8kHz

0001 = 11.025kHz

0010 = 12kHz

0011 = 16kHz

0100 = 22.05kHz

0101 = 24kHz

0110 = 32kHz

0111 = 44.1kHz

1000 = 48kHz

1001 = 88.2kHz

1010 = 96kHz


Note that 88.2kHz and 96kHz modes are supported for

AIF1 input (DAC playback) only. w PP, August 2012, Rev 3.4

296

Pre-Production

REGISTER

ADDRESS

3:0 AIF1CLK_RAT

E [3:0]

DESCRIPTION

0011 Selects the AIF1CLK / fs ratio

0000 = Reserved

0001 = 128

0010 = 192

0011 = 256

0100 = 384

0101 = 512

0110 = 768

0111 = 1024

1000 = 1408

1001 = 1536


Register 0210h AIF1 Rate

REGISTER

ADDRESS

R529

(0211h)

AIF2 Rate

3:0 AIF2CLK_RAT

E [3:0]

DESCRIPTION

0011

0000 = 8kHz

0001 = 11.025kHz

0010 = 12kHz

0011 = 16kHz

0100 = 22.05kHz

0101 = 24kHz

0110 = 32kHz

0111 = 44.1kHz

1000 = 48kHz

1001 = 88.2kHz

1010 = 96kHz


Note that 88.2kHz and 96kHz modes are supported for

AIF2 input (DAC playback) only.


0000 = Reserved

0001 = 128

0010 = 192

0011 = 256

0100 = 384

0101 = 512

0110 = 768

0111 = 1024

1000 = 1408

1001 = 1536


Register 0211h AIF2 Rate


297

WM8958

REGISTER

ADDRESS

R530

(0212h)

Rate Status

3:0 SR_ERROR

[3:0]

0000

Pre-Production

DESCRIPTION

Sample Rate Configuration status

Indicates an error with the register settings related to sample rate configuration

0000 = No errors

0001 = Invalid sample rate

0010 = Invalid AIF divide

0011 = ADC and DAC divides both set in an interface

0100 = Invalid combination of AIF divides and samplerate

0101 = Invalid set of enables for 96kHz mode

0110 = Invalid SYSCLK rate (derived from

AIF1CLK_RATE or AIF2CLK_RATE)

0111 = Mixed ADC and DAC rates in SYSCLK AIF when AIFs are asynchronous

1000 = Invalid combination of sample rates when both

AIFs are from the same clock source

1001 = Invalid combination of mixed ADC/DAC AIFs when both from the same clock source

1010 = AIF1DAC2 (Timeslot 1) ports enabled when

SRCs connected to AIF1

Register 0212h Rate Status

REGISTER

ADDRESS

R544

(0220h)

FLL1

Control (1)

DESCRIPTION

1 FLL1_OSC_EN

A

0 FLL1 Oscillator enable

0 = Disabled

1 = Enabled

(Note that this field is required for free-running FLL1 modes only)

0 FLL1_ENA 0 FLL1 Enable

0 = Disabled

1 = Enabled


Register 0220h FLL1 Control (1)

REGISTER

ADDRESS

R545

(0221h)

FLL1

Control (2)

13:8 FLL1_OUTDIV

[5:0]

DESCRIPTION

00_0000 FLL1 FOUT clock divider

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(FOUT = FVCO / FLL1_OUTDIV) w PP, August 2012, Rev 3.4

298

Pre-Production

REGISTER

ADDRESS

2:0 FLL1_FRATIO

[2:0]

000

DESCRIPTION

WM8958

FLL1 FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16


REGISTER

ADDRESS

R546

(0222h)

FLL1

Control (3)


REGISTER

ADDRESS

R547

(0223h)

FLL1

Control (4)


_0000_000

0

FLL1 Fractional multiply for FREF

(MSB = 0.5)

000

DESCRIPTION

DESCRIPTION

FLL1 Integer multiply for FREF

(LSB = 1)

REGISTER

ADDRESS

R548

(0224h)

FLL1

Control (5)

DESCRIPTION

15 FLL1_BYP 0 FLL1 Bypass Select

0 = Disabled

1 = Enabled

When FLL1_BYP is set, the FLL1 output is derived directly from BCLK1. In this case, FLL1 can be disabled.

12:7 FLL1_FRC_NC

O_VAL [5:0]

6 FLL1_FRC_NC

O

01_1001 FLL1 Forced oscillator value


0x19h (011001) = 12MHz approx

(Note that this field is required for free-running FLL modes only)

0 FLL1 Forced control select

0 = Normal

1 = FLL1 oscillator controlled by FLL1_FRC_NCO_VAL


4:3 FLL1_REFCLK

_DIV [1:0]

00 FLL1 Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8


For lower power operation, the reference clock can be divided down further if desired. w PP, August 2012, Rev 3.4

299

WM8958

REGISTER

ADDRESS

1:0 FLL1_REFCLK

_SRC [1:0]

Pre-Production

DESCRIPTION

00


REGISTER

ADDRESS

R550

(0226h)

FLL1 EFS 1

[15:0]

Register 0226h FLL1 EFS 1

REGISTER

ADDRESS

R550

(0226h)

FLL1 EFS 1

0 FLL1_EFS_EN

A

DESCRIPTION

_0000_000

0

FLL Fractional multiply for FREF

This field sets the denominator (dividing) part of the

FLL1_THETA / FLL1_LAMBDA ratio.

Coded as LSB = 1.

0

DESCRIPTION


0 = Integer Mode

1 = Fractional Mode

This bit should be set to 1 when FLL1_THETA > 0.


FLL1 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK1

11 = BCLK1

REGISTER

ADDRESS

R576

(0240h)

FLL2

Control (1)

DESCRIPTION

1 FLL2_OSC_EN

A

0 FLL2 Oscillator enable

0 = Disabled

1 = Enabled

(Note that this field is required for free-running FLL2 modes only)

0 FLL2_ENA 0 FLL2 Enable

0 = Disabled

1 = Enabled


Register 0240h FLL2 Control (1) w PP, August 2012, Rev 3.4

300

Pre-Production

REGISTER

ADDRESS

R577

(0241h)

FLL2

Control (2)

DESCRIPTION

13:8 FLL2_OUTDIV 00_0000 FLL2 FOUT clock divider

[5:0]

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

2:0 FLL2_FRATIO

[2:0]

000

111111 = 64

(FOUT = FVCO / FLL2_OUTDIV)

FLL2 FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16


REGISTER

ADDRESS

R578

(0242h)

FLL2

Control (3)


REGISTER

ADDRESS

R579

(0243h)

FLL2

Control (4)


_0000_000

0

000

FLL2 Fractional multiply for FREF

(MSB = 0.5)

FLL2 Integer multiply for FREF

(LSB = 1)

DESCRIPTION

DESCRIPTION

REGISTER

ADDRESS

R580

(0244h)

FLL2

Control (5)

DESCRIPTION

15 FLL2_BYP 0 FLL2 Bypass Select

0 = Disabled

1 = Enabled

12:7 FLL2_FRC_NC

O_VAL [5:0]

When FLL2_BYP is set, the FLL2 output is derived directly from BCLK2. In this case, FLL2 can be disabled.

01_1001 FLL2 Forced oscillator value


0x19h (011001) = 12MHz approx



301

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

6 FLL2_FRC_NC

4:3 FLL2_REFCLK

_DIV [1:0]

1:0 FLL2_REFCLK

_SRC [1:0]


O

0

00

00


0 = Normal

1 = FLL2 oscillator controlled by FLL2_FRC_NCO_VAL



00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8



FLL2 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK2

11 = BCLK2


REGISTER

ADDRESS

R582

(0246h)

FLL2 EFS 1

[15:0]


REGISTER

ADDRESS

R583

(0247h)

FLL2 EFS 2

0 FLL2_EFS_EN

A

DESCRIPTION

_0000_000

0

FLL Fractional multiply for FREF

This field sets the denominator (dividing) part of the

FLL2_THETA / FLL2_LAMBDA ratio.

Coded as LSB = 1.

0

DESCRIPTION


0 = Integer Mode

1 = Fractional Mode

This bit should be set to 1 when FLL2_THETA > 0.

REGISTER

ADDRESS

R768

(0300h)

AIF1 Control

(1)

15 AIF1ADCL_SR

C

14 AIF1ADCR_SR

C

0

1

DESCRIPTION






1 = Right ADC data is output on right channel w PP, August 2012, Rev 3.4

302

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

13 AIF1ADC_TDM 0 AIF1 transmit (ADC) TDM Control

0 = ADCDAT1 drives logic ‘0’ when not transmitting data

1 = ADCDAT1 is tri-stated when not transmitting data

8 AIF1_BCLK_IN

V

0 BCLK1 Invert


1 = BCLK1 inverted


00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits




01 = Left justified

10 = I2S Format

11 = DSP Mode

Register 0300h AIF1 Control (1)

REGISTER

ADDRESS

R769

(0301h)

AIF1 Control

(2)

DESCRIPTION

15 AIF1DACL_SR

C

14 AIF1DACR_SR

C

2 AIF1ADC_CO

MP

1 AIF1ADC_CO

MPMODE

0

1

11:10 AIF1DAC_BOO

ST [1:0]

00


0 = Disabled

1 = Enabled


AIF1_FMT = 11.

4 AIF1DAC_CO

MP

0


00 = 0dB




3 AIF1DAC_CO

MPMODE

0


0 = Disabled

1 = Enabled


0 = µ-law

1 = A-law

0

0








0 = Disabled

1 = Enabled


0 = µ-law

1 = A-law w

WM8958


303

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

0 AIF1_LOOPBA

CK

0 AIF1 Digital Loopback Function

0 = No loopback



REGISTER

ADDRESS

R770

(0302h)

AIF1

Master/Slav e

DESCRIPTION

15 AIF1_TRI 0 AIF1 Audio Interface tri-state



Note that the GPIO1 pin is controlled by this register only when configured as ADCLRCLK1.

14 AIF1_MSTR 0 AIF1 Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

13 AIF1_CLK_FR

C

0 Forces BCLK1, LRCLK1 and ADCLRCLK1 to be enabled when all AIF1 audio channels are disabled.

0 = Normal


12 AIF1_LRCLK_

FRC

0 Forces LRCLK1 and ADCLRCLK1 to be enabled when all AIF1 audio channels are disabled.

0 = Normal

1 = LRCLK1 and ADCLRCLK1 always enabled in

Master mode

Register 0302h AIF1 Master/Slave w PP, August 2012, Rev 3.4

304

Pre-Production

REGISTER

ADDRESS

R771

(0303h)

AIF1 BCLK

8:4 AIF1_BCLK_DI

V [4:0]

DESCRIPTION

0_0100 BCLK1 Rate

00000 = AIF1CLK

00001 = AIF1CLK / 1.5

00010 = AIF1CLK / 2

00011 = AIF1CLK / 3

00100 = AIF1CLK / 4

00101 = AIF1CLK / 5

00110 = AIF1CLK / 6

00111 = AIF1CLK / 8

01000 = AIF1CLK / 11

01001 = AIF1CLK / 12

01010 = AIF1CLK / 16

01011 = AIF1CLK / 22

01100 = AIF1CLK / 24

01101 = AIF1CLK / 32

01110 = AIF1CLK / 44

01111 = AIF1CLK / 48

10000 = AIF1CLK / 64

10001 = AIF1CLK / 88

10010 = AIF1CLK / 96

10011 = AIF1CLK / 128

10100 = AIF1CLK / 176

10101 = AIF1CLK / 192

10110 - 11111 = Reserved

Register 0303h AIF1 BCLK

REGISTER

ADDRESS

R772

(0304h)

AIF1ADC

LRCLK

DESCRIPTION

12 AIF1ADC_LRC

LK_INV

11 AIF1ADC_LRC

LK_DIR

10:0 AIF1ADC_RAT

E [10:0]

0

0

000_0100_

0000

Right, left and I2S modes – ADCLRCLK1 polarity




ADCLRCLK1 polarity in Master mode and in Slave mode.


0 = MSB is available on 2nd BCLK1 rising edge after

ADCLRCLK1 rising edge (mode A)

1 = MSB is available on 1st BCLK1 rising edge after

ADCLRCLK1 rising edge (mode B)


0 = Normal


ADCLRCLK1 Rate



Integer (LSB = 1)

Valid from 8..2047

Register 0304h AIF1ADC LRCLK w

WM8958


305

WM8958

Pre-Production

REGISTER

ADDRESS

R773

(0305h)

AIF1DAC

LRCLK

DESCRIPTION

12 AIF1DAC_LRC

LK_INV

11 AIF1DAC_LRC

LK_DIR

10:0 AIF1DAC_RAT

E [10:0]

0

0

000_0100_

0000

Right, left and I2S modes – LRCLK1 polarity



Note that AIF1DAC_LRCLK_INV selects the LRCLK1 polarity in Master mode and in Slave mode.



LRCLK1 rising edge (mode A)


LRCLK1 rising edge (mode B)


0 = Normal


LRCLK1 Rate



Integer (LSB = 1)

Valid from 8..2047

Register 0305h AIF1DAC LRCLK

REGISTER

ADDRESS

R774

(0306h)

AIF1DAC

Data

1 AIF1DACL_DA

T_INV

0 AIF1DACR_DA

T_INV

0

0

DESCRIPTION


0 = Not inverted

1 = Inverted


0 = Not inverted

1 = Inverted

Register 0306h AIF1DAC Data

REGISTER

ADDRESS

R775

(0307h)

AIF1ADC

Data

1 AIF1ADCL_DA

T_INV

0 AIF1ADCR_DA

T_INV

0

0

DESCRIPTION


0 = Not inverted

1 = Inverted


0 = Not inverted

1 = Inverted

Register 0307h AIF1ADC Data w PP, August 2012, Rev 3.4

306

Pre-Production

REGISTER

ADDRESS

R784

(0310h)

AIF2 Control

(1)

DESCRIPTION

15 AIF2ADCL_SR

C

14 AIF2ADCR_SR

C

0

1







13 AIF2ADC_TDM 0 AIF2 transmit (ADC) TDM Enable

0 = Normal ADCDAT2 operation

1 = TDM enabled on ADCDAT2

12 AIF2ADC_TDM

_CHAN

0 AIF2 transmit (ADC) TDM Slot Select

0 = Slot 0

1 = Slot 1

8 AIF2_BCLK_IN

V

0 BCLK2 Invert


1 = BCLK2 inverted


00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits




01 = Left justified

10 = I2S Format

11 = DSP Mode

1 AIF2TXL_ENA 1 Enable AIF2DAC (Left) input path

0 = Disabled

1 = Enabled

This bit must be set for AIF2 output of the AIF2ADC

(Left) signal. For AIF3 output only, this bit can be set to

0.

0 AIF2TXR_ENA 1 Enable AIF2DAC (Right) input path

0 = Disabled

1 = Enabled

This bit must be set for AIF2 output of the AIF2ADC

(Left) signal. For AIF3 output only, this bit can be set to

0.


REGISTER

ADDRESS

R785

(0311h)

AIF2 Control

(2)

15 AIF2DACL_SR

C

14 AIF2DACR_SR

C

0

1

DESCRIPTION








307

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

13 AIF2DAC_TDM 0 AIF2 receive (DAC) TDM Enable

0 = Normal DACDAT2 operation

1 = TDM enabled on DACDAT2

12 AIF2DAC_TDM

_CHAN

0 AIF2 receive (DAC) TDM Slot Select

0 = Slot 0

1 = Slot 1

11:10 AIF2DAC_BOO

ST [1:0]

00


0 = Disabled

1 = Enabled


AIF2_FMT = 11.

4 AIF2DAC_CO

MP

0


00 = 0dB




3 AIF2DAC_CO

MPMODE

0


0 = Disabled

1 = Enabled


0 = µ-law

1 = A-law

2 AIF2ADC_CO

MP

0

1 AIF2ADC_CO

MPMODE

0 AIF2_LOOPBA

CK

0

0


0 = Disabled

1 = Enabled


0 = µ-law

1 = A-law


0 = No loopback



REGISTER

ADDRESS

R786

(0312h)

AIF2

Master/Slav e

DESCRIPTION

15 AIF2_TRI 0 AIF2 Audio Interface tri-state




14 AIF2_MSTR 0 AIF2 Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

13 AIF2_CLK_FR

C

0 Forces BCLK2, LRCLK2 and ADCLRCLK2 to be enabled when all AIF2 audio channels are disabled.

0 = Normal

1 = BCLK2, LRCLK2 and ADCLRCLK2 always enabled in Master mode w PP, August 2012, Rev 3.4

308

Pre-Production

REGISTER

ADDRESS

12 AIF2_LRCLK_

FRC

DESCRIPTION

0 Forces LRCLK2 and ADCLRCLK2 to be enabled when all AIF2 audio channels are disabled.

0 = Normal

1 = LRCLK2 and ADCLRCLK2 always enabled in

Master mode

Register 0312h AIF2 Master/Slave

REGISTER

ADDRESS

R787

(0313h)

AIF2 BCLK

DESCRIPTION

8:4 AIF2_BCLK_DI

V [4:0]

0_0100 BCLK2 Rate

00000 = AIF2CLK

00001 = AIF2CLK / 1.5

00010 = AIF2CLK / 2

00011 = AIF2CLK / 3

00100 = AIF2CLK / 4

00101 = AIF2CLK / 5

00110 = AIF2CLK / 6

00111 = AIF2CLK / 8

01000 = AIF2CLK / 11

01001 = AIF2CLK / 12

01010 = AIF2CLK / 16

01011 = AIF2CLK / 22

01100 = AIF2CLK / 24

01101 = AIF2CLK / 32

01110 = AIF2CLK / 44

01111 = AIF2CLK / 48

10000 = AIF2CLK / 64

10001 = AIF2CLK / 88

10010 = AIF2CLK / 96

10011 = AIF2CLK / 128

10100 = AIF2CLK / 176

10101 = AIF2CLK / 192

10110 - 11111 = Reserved

Register 0313h AIF2 BCLK

REGISTER

ADDRESS

R788

(0314h)

AIF2ADC

LRCLK

12 AIF2ADC_LRC

LK_INV

0

DESCRIPTION

11 AIF2ADC_LRC w

LK_DIR

0

WM8958

Right, left and I2S modes – ADCLRCLK2 polarity




ADCLRCLK2 polarity in Master mode and in Slave mode.



ADCLRCLK2 rising edge (mode A)


ADCLRCLK2 rising edge (mode B)


0 = Normal



309

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

10:0 AIF2ADC_RAT

E [10:0]

000_0100_

0000

ADCLRCLK2 Rate



Integer (LSB = 1)

Valid from 8..2047

Register 0314h AIF2ADC LRCLK

REGISTER

ADDRESS

R789

(0315h)

AIF2DAC

LRCLK

DESCRIPTION

12 AIF2DAC_LRC

LK_INV

11 AIF2DAC_LRC

LK_DIR

10:0 AIF2DAC_RAT

E [10:0]

0

0

000_0100_

0000

Right, left and I2S modes – LRCLK2 polarity



Note that AIF2DAC_LRCLK_INV selects the LRCLK2 polarity in Master mode and in Slave mode.







0 = Normal


LRCLK2 Rate



Integer (LSB = 1)

Valid from 8..2047

Register 0315h AIF2DAC LRCLK

REGISTER

ADDRESS

R790

(0316h)

AIF2DAC

Data

1 AIF2DACL_DA

T_INV

0 AIF2DACR_DA

T_INV

0

0


0 = Not inverted

1 = Inverted


0 = Not inverted

1 = Inverted

DESCRIPTION


REGISTER

ADDRESS

R791

(0317h)

AIF2ADC

Data

1 AIF2ADCL_DA

T_INV

0 AIF2ADCR_DA

T_INV

0

0


0 = Not inverted

1 = Inverted


0 = Not inverted

1 = Inverted

DESCRIPTION

Register 0317h AIF2ADC Data w PP, August 2012, Rev 3.4

310

Pre-Production

REGISTER

ADDRESS

R800

(0320h)

AIF3 Control

(1)

7 AIF3_LRCLK_I

NV

0

DESCRIPTION









00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits



Note that this controls the AIF3 Mono PCM interface path only; it does not affect AIF3 inputs/outputs routed to AIF1 or AIF2.


REGISTER

ADDRESS

R801

(0321h)

AIF3 Control

(2)

11:10 AIF3DAC_BOO

ST [1:0]

4 AIF3DAC_CO

MP

3 AIF3DAC_CO

MPMODE

2 AIF3ADC_CO

MP

00

0

0

0

DESCRIPTION


00 = 0dB




Note that this controls the AIF3 Mono PCM interface path only; it does not affect DACDAT3 input to AIF1 or

AIF2.


0 = Disabled

1 = Enabled


AIF2.


0 = µ-law

1 = A-law


AIF2.


0 = Disabled

1 = Enabled

Note that this controls the AIF3 Mono PCM interface path only; it does not affect ADCDAT3 output from AIF1 or AIF2.


311

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

1 AIF3ADC_CO

MPMODE

0 AIF3_LOOPBA

CK

0

0


0 = µ-law

1 = A-law



0 = No loopback

1 = Loopback enabled (AIF3 Mono PCM data output is directly input to AIF3 Mono PCM data input).


REGISTER

ADDRESS

R802

(0322h)

AIF3DAC

Data

0 AIF3DAC_DAT

_INV

0

DESCRIPTION

AIF3 Receive Data Invert

0 = Not inverted

1 = Inverted


AIF2.


REGISTER

ADDRESS

R803

(0323h)

AIF3ADC

Data

0 AIF3ADC_DAT

_INV

0

DESCRIPTION

AIF3 Transmit Data Invert

0 = Not inverted

1 = Inverted


Register 0323h AIF3ADC Data

REGISTER

ADDRESS

R1024

(0400h)

AIF1 ADC1

Left Volume

DESCRIPTION

8 AIF1ADC1_VU 0 AIF1ADC1 output path (AIF1, Timeslot 0) Volume

Update

Writing a 1 to this bit will cause the AIF1ADC1L and

AIF1ADC1R volume to be updated simultaneously

7:0 AIF1ADC1L_V

OL [7:0]

1100_0000 AIF1ADC1 (Left) output path (AIF1, Timeslot 0) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB

Register 0400h AIF1 ADC1 Left Volume w PP, August 2012, Rev 3.4

312

Pre-Production

REGISTER

ADDRESS

R1025

(0401h)

AIF1 ADC1

Right

Volume

DESCRIPTION


Update



7:0 AIF1ADC1R_V

OL [7:0]

1100_0000 AIF1ADC1 (Right) output path (AIF1, Timeslot 0) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB

Register 0401h AIF1 ADC1 Right Volume

REGISTER

ADDRESS

R1026

(0402h)

AIF1 DAC1

Left Volume

DESCRIPTION

8 AIF1DAC1_VU 0 AIF1DAC1 input path (AIF1, Timeslot 0) Volume

Update

Writing a 1 to this bit will cause the AIF1DAC1L and

AIF1DAC1R volume to be updated simultaneously

7:0 AIF1DAC1L_V

OL [7:0]

1100_0000 AIF1DAC1 (Left) input path (AIF1, Timeslot 0) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB

Register 0402h AIF1 DAC1 Left Volume

REGISTER

ADDRESS

R1027

(0403h)

AIF1 DAC1

Right

Volume

DESCRIPTION


Update



7:0 AIF1DAC1R_V

OL [7:0]

1100_0000 AIF1DAC1 (Right) input path (AIF1, Timeslot 0) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB

Register 0403h AIF1 DAC1 Right Volume


313

WM8958

Pre-Production

REGISTER

ADDRESS

R1028

(0404h)

AIF1 ADC2

Left Volume

DESCRIPTION


Update



7:0 AIF1ADC2L_V

OL [7:0]

1100_0000 AIF1ADC2 (Left) output path (AIF1, Timeslot 1) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB

Register 0404h AIF1 ADC2 Left Volume

REGISTER

ADDRESS

R1029

(0405h)

AIF1 ADC2

Right

Volume

DESCRIPTION


Update



7:0 AIF1ADC2R_V

OL [7:0]

1100_0000 AIF1ADC2 (Right) output path (AIF1, Timeslot 1) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB

Register 0405h AIF1 ADC2 Right Volume

REGISTER

ADDRESS

R1030

(0406h)

AIF1 DAC2

Left Volume

DESCRIPTION


Update



7:0 AIF1DAC2L_V

OL [7:0]

1100_0000 AIF1DAC2 (Left) input path (AIF1, Timeslot 1) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB

Register 0406h AIF1 DAC2 Left Volume w PP, August 2012, Rev 3.4

314

Pre-Production

REGISTER

ADDRESS

R1031

(0407h)

AIF1 DAC2

Right

Volume

DESCRIPTION


Update



7:0 AIF1DAC2R_V

OL [7:0]

1100_0000 AIF1DAC2 (Right) input path (AIF1, Timeslot 1) Digital

Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB

Register 0407h AIF1 DAC2 Right Volume

WM8958

REGISTER

ADDRESS

R1040

(0410h)

AIF1 ADC1

Filters

DESCRIPTION

15 AIF1ADC_4FS 0 Enable AIF1ADC ultrasonic mode (4FS) output, bypassing all AIF1 baseband output filtering

0 = Disabled

1 = Enabled

14:13 AIF1ADC1_HP

F_CUT [1:0]

00 AIF1ADC1 output path (AIF1, Timeslot 0) Digital HPF cut-off frequency (fc)





12 AIF1ADC1L_H

PF

0

11 AIF1ADC1R_H

PF

0

AIF1ADC1 (Left) output path (AIF1, Timeslot 0) Digital

HPF Enable

0 = Disabled

1 = Enabled

AIF1ADC1 (Right) output path (AIF1, Timeslot 0) Digital

HPF Enable

0 = Disabled

1 = Enabled

Register 0410h AIF1 ADC1 Filters

REGISTER

ADDRESS

R1041

(0411h)

AIF1 ADC2

Filters

14:13 AIF1ADC2_HP

F_CUT [1:0]

12 AIF1ADC2L_H

PF

11 AIF1ADC2R_H

PF

00

0

0

DESCRIPTION

AIF1ADC2 output path (AIF1, Timeslot 1) Digital HPF cut-off frequency (fc)





AIF1ADC2 (Left) output path (AIF1, Timeslot 1) Digital

HPF Enable

0 = Disabled

1 = Enabled

AIF1ADC2 (Right) output path (AIF1, Timeslot 1) Digital

HPF Enable

0 = Disabled

1 = Enabled

Register 0411h AIF1 ADC2 Filters w PP, August 2012, Rev 3.4

315

WM8958

REGISTER

ADDRESS

R1056

(0420h)

AIF1 DAC1

Filters (1)

9 AIF1DAC1_MU

TE

7 AIF1DAC1_MO

NO

5 AIF1DAC1_MU

TERATE

4 AIF1DAC1_UN

MUTE_RAMP

1

0

0

0

Pre-Production

DESCRIPTION

AIF1DAC1 input path (AIF1, Timeslot 0) Soft Mute

Control

0 = Un-mute

1 = Mute

AIF1DAC1 input path (AIF1, Timeslot 0) Mono Mix

Control

0 = Disabled

1 = Enabled


Ramp Rate




AIF1DAC1 input path (AIF1, Timeslot 0) Unmute Ramp select



1 = Disabling soft-mute (AIF1DAC1_MUTE=0) will cause the DAC volume to ramp up gradually to the


Register 0420h AIF1 DAC1 Filters (1)

REGISTER

ADDRESS

R1057

(0421h)

AIF1 DAC1

Filters (2)

13:9 AIF1DAC1_3D

_GAIN [4:0]

8 AIF1DAC1_3D

_ENA

DESCRIPTION

0_0000 AIF1DAC1 playback path (AIF1, Timeslot 0) 3D Stereo depth

00000 = Off

00001 = Minimum (-16dB)

…(0.915dB steps)

11111 = Maximum (+11.45dB)

0 Enable 3D Stereo in AIF1DAC1 playback path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled


REGISTER

ADDRESS

R1058

(0422h)

AIF1 DAC2

Filters (1)

9 AIF1DAC2_MU

TE

7 AIF1DAC2_MO

NO

1

0

Control

0 = Un-mute

1 = Mute

DESCRIPTION


AIF1DAC2 input path (AIF1, Timeslot 1) Mono Mix

Control

0 = Disabled


316

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

5 AIF1DAC2_MU

TERATE

4 AIF1DAC2_UN

MUTE_RAMP


REGISTER

ADDRESS

R1059

(0423h)

AIF1 DAC2

Filters (2)

13:9 AIF1DAC2_3D

_GAIN [4:0]

8 AIF1DAC2_3D

_ENA

DESCRIPTION

0_0000 AIF1DAC2 playback path (AIF1, Timeslot 1) 3D Stereo depth

00000 = Off

00001 = Minimum (-16dB)

…(0.915dB steps)

11111 = Maximum (+11.45dB)

0 Enable 3D Stereo in AIF1DAC2 playback path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled


REGISTER

ADDRESS

R1072

(0430h)

AIF1 DAC1

Noise Gate

6:5 AIF1DAC1_NG

_HLD [1:0]

0

0

11


Ramp Rate




AIF1DAC2 input path (AIF1, Timeslot 1) Unmute Ramp select



1 = Disabling soft-mute (AIF1DAC2_MUTE=0) will cause the DAC volume to ramp up gradually to the


DESCRIPTION

3:1 AIF1DAC1_NG

_THR [2:0]

0 AIF1DAC1_NG

_ENA

100

0

AIF1DAC1 input path (AIF1, Timeslot 0) Noise Gate

Hold Time


00 = 30ms

01 = 125ms

10 = 250ms

11 = 500ms


Threshold

000 = -60dB

001 = -66dB

010 = -72dB

011 = -78dB

100 = -84dB

101 = -90dB

110 = -96dB

111 = -102dB


Enable

0 = Disabled

1 = Enabled

Register 0430h AIF1 DAC1 Noise Gate w

WM8958


317

WM8958

REGISTER

ADDRESS

R1073

(0431h)

AIF1 DAC2

Noise Gate

6:5 AIF1DAC2_NG

_HLD [1:0]

3:1 AIF1DAC2_NG

_THR [2:0]

0 AIF1DAC2_NG

_ENA

11

100

0

Pre-Production

DESCRIPTION


Hold Time


00 = 30ms

01 = 125ms

10 = 250ms

11 = 500ms


Threshold

000 = -60dB

001 = -66dB

010 = -72dB

011 = -78dB

100 = -84dB

101 = -90dB

110 = -96dB

111 = -102dB


Enable

0 = Disabled

1 = Enabled

Register 0431h AIF1 DAC2 Noise Gate

REGISTER

ADDRESS

R1088

(0440h)

AIF1 DRC1

(1)

15:11 AIF1DRC1_SI

G_DET_RMS

[4:0]

10:9 AIF1DRC1_SI

G_DET_PK

[1:0]

8 AIF1DRC1_NG

_ENA

7 AIF1DRC1_SI

G_DET_MODE

6 AIF1DRC1_SI

G_DET

DESCRIPTION

0_0000 AIF1 DRC1 Signal Detect RMS Threshold.

This is the RMS signal level for signal detect to be indicated when AIF1DRC1_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

00 AIF1 DRC1 Signal Detect Peak Threshold.

This is the Peak/RMS ratio, or Crest Factor, level for signal detect to be indicated when


00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

0

1

0


0 = Disabled

1 = Enabled





0 = Disabled


318

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

5 AIF1DRC1_KN

EE2_OP_ENA

3 AIF1DRC1_AN

TICLIP

0 AIF1 DRC1 KNEE2_OP Enable

0 = Disabled

1 = Enabled

4 AIF1DRC1_QR 1 AIF1 DRC1 Quick-release Enable

0 = Disabled

1 = Enabled

1 AIF1 DRC1 Anti-clip Enable

0 = Disabled

1 = Enabled

2 AIF1DAC1_DR

C_ENA

0

1 AIF1ADC1L_D

RC_ENA

0

Enable DRC in AIF1DAC1 playback path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

Enable DRC in AIF1ADC1 (Left) record path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

0 AIF1ADC1R_D

RC_ENA

0 Enable DRC in AIF1ADC1 (Right) record path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

Register 0440h AIF1 DRC1 (1)

REGISTER

ADDRESS

R1089

(0441h)

AIF1 DRC1

(2)

12:9 AIF1DRC1_AT

K [3:0]

DESCRIPTION

8:5 AIF1DRC1_DC

Y [3:0]

0100

0010

AIF1 DRC1 Gain attack rate (seconds/6dB)

0000 = Reserved

0001 = 181us

0010 = 363us

0011 = 726us

0100 = 1.45ms

0101 = 2.9ms

0110 = 5.8ms

0111 = 11.6ms

1000 = 23.2ms

1001 = 46.4ms

1010 = 92.8ms

1011 = 185.6ms


AIF1 DRC1 Gain decay rate (seconds/6dB)

0000 = 186ms

0001 = 372ms

0010 = 743ms

0011 = 1.49s

0100 = 2.97s

0101 = 5.94s

0110 = 11.89s

0111 = 23.78s

1000 = 47.56s



319

WM8958

REGISTER

ADDRESS

4:2 AIF1DRC1_MI

NGAIN [2:0]

1:0 AIF1DRC1_MA

XGAIN [1:0]

001

01

Pre-Production

DESCRIPTION


000 = 0dB


010 = -18dB

011 = -24dB

100 = -36dB

101 = Reserved

11X = Reserved


00 = 12dB

01 = 18dB

10 = 24dB

11 = 36dB


REGISTER

ADDRESS

R1090

(0442h)

AIF1 DRC1

(3)

15:12 AIF1DRC1_NG

_MINGAIN

[3:0]

11:10 AIF1DRC1_NG

_EXP [1:0]

9:8 AIF1DRC1_QR

_THR [1:0]

7:6 AIF1DRC1_QR

_DCY [1:0]

DESCRIPTION

0000

00

00

00


0000 = -36dB

0001 = -30dB

0010 = -24dB

0011 = -18dB

0100 = -12dB

0101 = -6dB

0110 = 0dB

0111 = 6dB

1000 = 12dB

1001 = 18dB

1010 = 24dB

1011 = 30dB

1100 = 36dB




01 = 2

10 = 4

11 = 8

AIF1 DRC1 Quick-release threshold (crest factor in dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB


00 = 0.725ms

01 = 1.45ms

10 = 5.8ms


320

Pre-Production

REGISTER

ADDRESS

5:3 AIF1DRC1_HI_

COMP [2:0]

DESCRIPTION

2:0 AIF1DRC1_LO

_COMP [2:0]

000

000

AIF1 DRC1 Compressor slope (upper region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

110 = Reserved

111 = Reserved

AIF1 DRC1 Compressor slope (lower region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101 = Reserved

11X = Reserved


REGISTER

ADDRESS

R1091

(0443h)

AIF1 DRC1

(4)

DESCRIPTION

10:5 AIF1DRC1_KN

EE_IP [5:0]

4:0 AIF1DRC1_KN

EE_OP [4:0]

00_0000 AIF1 DRC1 Input signal level at the Compressor ‘Knee’.

000000 = 0dB

000001 = -0.75dB

000010 = -1.5dB

… (-0.75dB steps)

111100 = -45dB

111101 = Reserved

11111X = Reserved

0_0000 AIF1 DRC1 Output signal at the Compressor ‘Knee’.

00000 = 0dB

00001 = -0.75dB

00010 = -1.5dB

… (-0.75dB steps)

11110 = -22.5dB

11111 = Reserved


REGISTER

ADDRESS

R1092

(0444h)

AIF1 DRC1

(5)

DESCRIPTION

9:5 AIF1DRC1_KN

EE2_IP [4:0]

0_0000 AIF1 DRC1 Input signal level at the Noise Gate threshold ‘Knee2’.

00000 = -36dB

00001 = -37.5dB

00010 = -39dB

… (-1.5dB steps)

11110 = -81dB

11111 = -82.5dB

Only applicable when AIF1DRC1_NG_ENA = 1.


321

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

4:0 AIF1DRC1_KN

EE2_OP [4:0]

0_0000 AIF1 DRC1 Output signal at the Noise Gate threshold

‘Knee2’.

00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB

Only applicable when AIF1DRC1_KNEE2_OP_ENA =

1.


REGISTER

ADDRESS

R1104

(0450h)

AIF1 DRC2

(1)

DESCRIPTION

15:11 AIF1DRC2_SI

G_DET_RMS

[4:0]

10:9 AIF1DRC2_SI

G_DET_PK

[1:0]

0_0000 AIF1 DRC2 Signal Detect RMS Threshold.

This is the RMS signal level for signal detect to be indicated when AIF1DRC2_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

00 AIF1 DRC2 Signal Detect Peak Threshold.



00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

8 AIF1DRC2_NG

_ENA

7 AIF1DRC2_SI

G_DET_MODE

6 AIF1DRC2_SI

G_DET

5 AIF1DRC2_KN

EE2_OP_ENA

0

1

0

0


0 = Disabled

1 = Enabled





0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

4 AIF1DRC2_QR 1 AIF1 DRC2 Quick-release Enable

0 = Disabled

3 AIF1DRC2_AN

TICLIP

1

1 = Enabled


0 = Disabled

1 = Enabled

2 AIF1DAC2_DR

C_ENA

0 Enable DRC in AIF1DAC2 playback path (AIF1,

Timeslot 1)

0 = Disabled


322

Pre-Production

REGISTER

ADDRESS

1 AIF1ADC2L_D

RC_ENA

0 AIF1ADC2R_D

RC_ENA

0

0


REGISTER

ADDRESS

R1105

(0451h)

AIF1 DRC2

(2)

12:9 AIF1DRC2_AT

K [3:0]

8:5 AIF1DRC2_DC

Y [3:0]

4:2 AIF1DRC2_MI

NGAIN [2:0]

1:0 AIF1DRC2_MA

XGAIN [1:0]

DESCRIPTION

0100

0010

001

01

AIF1 DRC2 Gain attack rate (seconds/6dB)

0000 = Reserved

0001 = 181us

0010 = 363us

0011 = 726us

0100 = 1.45ms

0101 = 2.9ms

0110 = 5.8ms

0111 = 11.6ms

1000 = 23.2ms

1001 = 46.4ms

1010 = 92.8ms

1011 = 185.6ms


AIF1 DRC2 Gain decay rate (seconds/6dB)

0000 = 186ms

0001 = 372ms

0010 = 743ms

0011 = 1.49s

0100 = 2.97s

0101 = 5.94s

0110 = 11.89s

0111 = 23.78s

1000 = 47.56s



000 = 0dB


010 = -18dB

011 = -24dB

100 = -36dB

101 = Reserved

11X = Reserved


00 = 12dB

01 = 18dB

10 = 24dB

11 = 36dB


DESCRIPTION

Enable DRC in AIF1ADC2 (Left) record path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

Enable DRC in AIF1ADC2 (Right) record path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled


323

WM8958

REGISTER

ADDRESS

R1106

(0452h)

AIF1 DRC2

(3)

15:12 AIF1DRC2_NG

_MINGAIN

[3:0]

11:10 AIF1DRC2_NG

_EXP [1:0]

9:8 AIF1DRC2_QR

_THR [1:0]

7:6 AIF1DRC2_QR

_DCY [1:0]

5:3 AIF1DRC2_HI_

COMP [2:0]

2:0 AIF1DRC2_LO

_COMP [2:0]

Pre-Production

DESCRIPTION

0000

00

00

00

000

000


0000 = -36dB

0001 = -30dB

0010 = -24dB

0011 = -18dB

0100 = -12dB

0101 = -6dB

0110 = 0dB

0111 = 6dB

1000 = 12dB

1001 = 18dB

1010 = 24dB

1011 = 30dB

1100 = 36dB




01 = 2

10 = 4

11 = 8

AIF1 DRC2 Quick-release threshold (crest factor in dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB


00 = 0.725ms

01 = 1.45ms

10 = 5.8ms

11 = Reserved

AIF1 DRC2 Compressor slope (upper region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

110 = Reserved

111 = Reserved

AIF1 DRC2 Compressor slope (lower region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101 = Reserved

11X = Reserved

Register 0452h AIF1 DRC2 (3) w PP, August 2012, Rev 3.4

324

Pre-Production

REGISTER

ADDRESS

R1107

(0453h)

AIF1 DRC2

(4)

10:5 AIF1DRC2_KN

EE_IP [5:0]

4:0 AIF1DRC2_KN

EE_OP [4:0]

DESCRIPTION

00_0000 AIF1 DRC2 Input signal level at the Compressor ‘Knee’.

000000 = 0dB

000001 = -0.75dB

000010 = -1.5dB

… (-0.75dB steps)

111100 = -45dB

111101 = Reserved

11111X = Reserved

0_0000 AIF1 DRC2 Output signal at the Compressor ‘Knee’.

00000 = 0dB

00001 = -0.75dB

00010 = -1.5dB

… (-0.75dB steps)

11110 = -22.5dB

11111 = Reserved


REGISTER

ADDRESS

R1108

(0454h)

AIF1 DRC2

(5)

9:5 AIF1DRC2_KN

EE2_IP [4:0]

4:0 AIF1DRC2_KN

EE2_OP [4:0]

DESCRIPTION

0_0000 AIF1 DRC2 Input signal level at the Noise Gate threshold ‘Knee2’.

00000 = -36dB

00001 = -37.5dB

00010 = -39dB

… (-1.5dB steps)

11110 = -81dB

11111 = -82.5dB

Only applicable when AIF1DRC2_NG_ENA = 1.

0_0000 AIF1 DRC2 Output signal at the Noise Gate threshold

‘Knee2’.

00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB

Only applicable when AIF1DRC2_KNEE2_OP_ENA =

1.


REGISTER

ADDRESS

R1152

(0480h)

AIF1 DAC1

EQ Gains

(1)

15:11 AIF1DAC1_EQ

_B1_GAIN [4:0]

10:6 AIF1DAC1_EQ

_B2_GAIN [4:0]

5:1 AIF1DAC1_EQ

_B3_GAIN [4:0]

0 AIF1DAC1_EQ

_ENA

Register 0480h AIF1 DAC1 EQ Gains (1)

DESCRIPTION

0_1100 AIF1DAC1 (AIF1, Timeslot 0) EQ Band 1 Gain






0 Enable EQ in AIF1DAC1 playback path (AIF1, Timeslot

0)

0 = Disabled

1 = Enabled w

WM8958


325

WM8958

REGISTER

ADDRESS

R1153

(0481h)

AIF1 DAC1

EQ Gains

(2)

15:11 AIF1DAC1_EQ

_B4_GAIN [4:0]

10:6 AIF1DAC1_EQ

_B5_GAIN [4:0]

0 AIF1DAC1_EQ

_MODE

Register 0481h AIF1 DAC1 EQ Gains (2)

Pre-Production

DESCRIPTION





0 AIF1DAC1 (AIF1, Timeslot 0) EQ Band 1 Mode

0 = Shelving filter

1 = Peak filter

REGISTER

ADDRESS

R1154

(0482h)

AIF1 DAC1

EQ Band 1

A

15:0 AIF1DAC1_EQ

_B1_A [15:0]

Register 0482h AIF1 DAC1 EQ Band 1 A

DESCRIPTION

0000_1111

_1100_101

0

EQ Band 1 Coefficient A

REGISTER

ADDRESS

R1155

(0483h)

AIF1 DAC1

EQ Band 1

B

15:0 AIF1DAC1_EQ

_B1_B [15:0]

Register 0483h AIF1 DAC1 EQ Band 1 B

DESCRIPTION

0000_0100

_0000_000

0

EQ Band 1 Coefficient B

REGISTER

ADDRESS

R1156

(0484h)

AIF1 DAC1

EQ Band 1

PG

15:0 AIF1DAC1_EQ

_B1_PG [15:0]

0000_0000

_1101_100

Register 0484h AIF1 DAC1 EQ Band 1 PG

0

DESCRIPTION

EQ Band 1 Coefficient PG

REGISTER

ADDRESS

R1157

(0485h)

AIF1 DAC1

EQ Band 2

A

15:0 AIF1DAC1_EQ

_B2_A [15:0]


DESCRIPTION

0001_1110

_1011_010

1

EQ Band 2 Coefficient A w PP, August 2012, Rev 3.4

326

Pre-Production

REGISTER

ADDRESS

R1158

(0486h)

AIF1 DAC1

EQ Band 2

B

15:0 AIF1DAC1_EQ

_B2_B [15:0]


DESCRIPTION

1111_0001

_0100_010

1


REGISTER

ADDRESS

R1159

(0487h)

AIF1 DAC1

EQ Band 2

C

15:0 AIF1DAC1_EQ

_B2_C [15:0]

Register 0487h AIF1 DAC1 EQ Band 2 C

DESCRIPTION

0000_1011

_0111_010

1

EQ Band 2 Coefficient C

REGISTER

ADDRESS

R1160

(0488h)

AIF1 DAC1

EQ Band 2

PG

15:0 AIF1DAC1_EQ

_B2_PG [15:0]

0000_0001

_1100_010


1

DESCRIPTION


REGISTER

ADDRESS

R1161

(0489h)

AIF1 DAC1

EQ Band 3

A

15:0 AIF1DAC1_EQ

_B3_A [15:0]


DESCRIPTION

0001_1100

_0101_100

0


REGISTER

ADDRESS

R1162

(048Ah)

AIF1 DAC1

EQ Band 3

B

15:0 AIF1DAC1_EQ

_B3_B [15:0]

Register 048Ah AIF1 DAC1 EQ Band 3 B

DESCRIPTION

1111_0011

_0111_001

1


REGISTER

ADDRESS

R1163

(048Bh)

AIF1 DAC1

EQ Band 3

C

15:0 AIF1DAC1_EQ

_B3_C [15:0]

Register 048Bh AIF1 DAC1 EQ Band 3 C

DESCRIPTION

0000_1010

_0101_010

0

EQ Band 3 Coefficient C w

WM8958


327

WM8958

Pre-Production

REGISTER

ADDRESS

R1164

(048Ch)

AIF1 DAC1

EQ Band 3

PG

15:0 AIF1DAC1_EQ

_B3_PG [15:0]

0000_0101

_0101_100

Register 048Ch AIF1 DAC1 EQ Band 3 PG

0

DESCRIPTION


REGISTER

ADDRESS

R1165

(048Dh)

AIF1 DAC1

EQ Band 4

A

15:0 AIF1DAC1_EQ

_B4_A [15:0]

Register 048Dh AIF1 DAC1 EQ Band 4 A

DESCRIPTION

0001_0110

_1000_111

0


REGISTER

ADDRESS

R1166

(048Eh)

AIF1 DAC1

EQ Band 4

B

15:0 AIF1DAC1_EQ

_B4_B [15:0]

Register 048Eh AIF1 DAC1 EQ Band 4 B

DESCRIPTION

1111_1000

_0010_100

1


REGISTER

ADDRESS

R1167

(048Fh)

AIF1 DAC1

EQ Band 4

C

15:0 AIF1DAC1_EQ

_B4_C [15:0]

Register 048Fh AIF1 DAC1 EQ Band 4 C

DESCRIPTION

0000_0111

_1010_110

1


REGISTER

ADDRESS

R1168

(0490h)

AIF1 DAC1

EQ Band 4

PG

15:0 AIF1DAC1_EQ

_B4_PG [15:0]

0001_0001

_0000_001


1

DESCRIPTION


REGISTER

ADDRESS

R1169

(0491h)

AIF1 DAC1

EQ Band 5

A

15:0 AIF1DAC1_EQ

_B5_A [15:0]


DESCRIPTION

0000_0101

_0110_010

0

EQ Band 5 Coefficient A w PP, August 2012, Rev 3.4

328

Pre-Production

REGISTER

ADDRESS

R1170

(0492h)

AIF1 DAC1

EQ Band 5

B

15:0 AIF1DAC1_EQ

_B5_B [15:0]


DESCRIPTION

0000_0101

_0101_100

1


REGISTER

ADDRESS

R1171

(0493h)

AIF1 DAC1

EQ Band 5

PG

15:0 AIF1DAC1_EQ

_B5_PG [15:0]

0100_0000

_0000_000


0

DESCRIPTION


REGISTER

ADDRESS

R1184

(04A0h)

AIF1 DAC2

EQ Gains

(1)

15:11 AIF1DAC2_EQ

_B1_GAIN [4:0]

10:6 AIF1DAC2_EQ

_B2_GAIN [4:0]

5:1 AIF1DAC2_EQ

_B3_GAIN [4:0]

0 AIF1DAC2_EQ

_ENA

Register 04A0h AIF1 DAC2 EQ Gains (1)

DESCRIPTION







0 Enable EQ in AIF1DAC2 playback path (AIF1, Timeslot

1)

0 = Disabled

1 = Enabled

REGISTER

ADDRESS

R1185

(04A1h)

AIF1 DAC2

EQ Gains

(2)

15:11 AIF1DAC2_EQ

_B4_GAIN [4:0]

10:6 AIF1DAC2_EQ

_B5_GAIN [4:0]

0 AIF1DAC2_EQ

_MODE

Register 04A1h AIF1 DAC2 EQ Gains (2)

DESCRIPTION





0 AIF1DAC2 (AIF1, Timeslot 1) EQ Band 1 Mode

0 = Shelving filter

1 = Peak filter

REGISTER

ADDRESS

R1186

(04A2h)

AIF1 DAC2

EQ Band 1

A

15:0 AIF1DAC2_EQ

_B1_A [15:0]

Register 04A2h AIF1 DAC2 EQ Band 1 A

DESCRIPTION

0000_1111

_1100_101

0



329

WM8958

Pre-Production

REGISTER

ADDRESS

R1187

(04A3h)

AIF1 DAC2

EQ Band 1

B

15:0 AIF1DAC2_EQ

_B1_B [15:0]

Register 04A3h AIF1 DAC2 EQ Band 1 B

DESCRIPTION

0000_0100

_0000_000

0


REGISTER

ADDRESS

R1188

(04A4h)

AIF1 DAC2

EQ Band 1

PG

15:0 AIF1DAC2_EQ

_B1_PG [15:0]

0000_0000

_1101_100

Register 04A4h AIF1 DAC2 EQ Band 1 PG

0

DESCRIPTION


REGISTER

ADDRESS

R1189

(04A5h)

AIF1 DAC2

EQ Band 2

A

15:0 AIF1DAC2_EQ

_B2_A [15:0]


DESCRIPTION

0001_1110

_1011_010

1


REGISTER

ADDRESS

R1190

(04A6h)

AIF1 DAC2

EQ Band 2

B

15:0 AIF1DAC2_EQ

_B2_B [15:0]

Register 04A6h AIF1 DAC2 EQ Band 2 B

DESCRIPTION

1111_0001

_0100_010

1


REGISTER

ADDRESS

R1191

(04A7h)

AIF1 DAC2

EQ Band 2

C

15:0 AIF1DAC2_EQ

_B2_C [15:0]

DESCRIPTION

0000_1011

_0111_010

1


Register 04A7h AIF1 DAC2 EQ Band 2 C

REGISTER

ADDRESS

R1192

(04A8h)

AIF1 DAC2

EQ Band 2

PG

15:0 AIF1DAC2_EQ

_B2_PG [15:0]

0000_0001

_1100_010

Register 04A8h AIF1 DAC2 EQ Band 2 PG

1

DESCRIPTION

EQ Band 2 Coefficient PG w PP, August 2012, Rev 3.4

330

Pre-Production

REGISTER

ADDRESS

R1193

(04A9h)

AIF1 DAC2

EQ Band 3

A

15:0 AIF1DAC2_EQ

_B3_A [15:0]


DESCRIPTION

0001_1100

_0101_100

0


REGISTER

ADDRESS

R1194

(04AAh)

AIF1 DAC2

EQ Band 3

B

15:0 AIF1DAC2_EQ

_B3_B [15:0]

Register 04AAh AIF1 DAC2 EQ Band 3 B

DESCRIPTION

1111_0011

_0111_001

1


REGISTER

ADDRESS

R1195

(04ABh)

AIF1 DAC2

EQ Band 3

C

15:0 AIF1DAC2_EQ

_B3_C [15:0]

Register 04ABh AIF1 DAC2 EQ Band 3 C

DESCRIPTION

0000_1010

_0101_010

0


REGISTER

ADDRESS

R1196

(04ACh)

AIF1 DAC2

EQ Band 3

PG

15:0 AIF1DAC2_EQ

_B3_PG [15:0]

0000_0101

_0101_100

Register 04ACh AIF1 DAC2 EQ Band 3 PG

0

DESCRIPTION


REGISTER

ADDRESS

R1197

(04ADh)

AIF1 DAC2

EQ Band 4

A

15:0 AIF1DAC2_EQ

_B4_A [15:0]

Register 04ADh AIF1 DAC2 EQ Band 4 A

DESCRIPTION

0001_0110

_1000_111

0


REGISTER

ADDRESS

R1198

(04AEh)

AIF1 DAC2

EQ Band 4

B

15:0 AIF1DAC2_EQ

_B4_B [15:0]

Register 04AEh AIF1 DAC2 EQ Band 4 B

DESCRIPTION

1111_1000

_0010_100

1

EQ Band 4 Coefficient B w

WM8958


331

WM8958

Pre-Production

REGISTER

ADDRESS

R1199

(04AFh)

AIF1 DAC2

EQ Band 4

C

15:0 AIF1DAC2_EQ

_B4_C [15:0]

Register 04AFh AIF1 DAC2 EQ Band 4 C

DESCRIPTION

0000_0111

_1010_110

1


REGISTER

ADDRESS

R1200

(04B0h)

AIF1 DAC2

EQ Band 4

PG

15:0 AIF1DAC2_EQ

_B4_PG [15:0]

0001_0001

_0000_001

Register 04B0h AIF1 DAC2 EQ Band 4 PG

1

DESCRIPTION


REGISTER

ADDRESS

R1201

(04B1h)

AIF1 DAC2

EQ Band 5

A

15:0 AIF1DAC2_EQ

_B5_A [15:0]

Register 04B1h AIF1 DAC2 EQ Band 5 A

DESCRIPTION

0000_0101

_0110_010

0


REGISTER

ADDRESS

R1202

(04B2h)

AIF1 DAC2

EQ Band 5

B

15:0 AIF1DAC2_EQ

_B5_B [15:0]

Register 04B2h AIF1 DAC2 EQ Band 5 B

DESCRIPTION

0000_0101

_0101_100

1


REGISTER

ADDRESS

R1203

(04B3h)

AIF1 DAC2

EQ Band 5

PG

15:0 AIF1DAC2_EQ

_B5_PG [15:0]

0100_0000

_0000_000

Register 04B3h AIF1 DAC2 EQ Band 5 PG

0

DESCRIPTION


332

Pre-Production

REGISTER

ADDRESS

R1280

(0500h)

AIF2 ADC

Left Volume

DESCRIPTION

8 AIF2ADC_VU 0 AIF2ADC output path Volume Update

Writing a 1 to this bit will cause the AIF2ADCL and

AIF2ADCR volume to be updated simultaneously

7:0 AIF2ADCL_VO

L [7:0]

1100_0000 AIF2ADC (Left) output path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB

Register 0500h AIF2 ADC Left Volume

REGISTER

ADDRESS

R1281

(0501h)

AIF2 ADC

Right

Volume

DESCRIPTION

8 AIF2ADC_VU 0 AIF2ADC output path Volume Update

Writing a 1 to this bit will cause the AIF2ADCL and

AIF2ADCR volume to be updated simultaneously

7:0 AIF2ADCR_VO

L [7:0]

1100_0000 AIF2ADC (Right) output path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

EFh = +17.625dB

Register 0501h AIF2 ADC Right Volume

REGISTER

ADDRESS

R1282

(0502h)

AIF2 DAC

Left Volume

DESCRIPTION

8 AIF2DAC_VU 0 AIF2DAC input path Volume Update

Writing a 1 to this bit will cause the AIF2DACL and

AIF2DACR volume to be updated simultaneously

7:0 AIF2DACL_VO

L [7:0]

1100_0000 AIF2DAC (Left) input path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB

Register 0502h AIF2 DAC Left Volume

REGISTER

ADDRESS

R1283

(0503h)

AIF2 DAC

Right

Volume

DESCRIPTION

8 AIF2DAC_VU 0 AIF2DAC input path Volume Update

Writing a 1 to this bit will cause the AIF2DACL and

AIF2DACR volume to be updated simultaneously

7:0 AIF2DACR_VO

L [7:0]

1100_0000 AIF2DAC (Right) input path Digital Volume

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

FFh = 0dB

Register 0503h AIF2 DAC Right Volume


333

WM8958

REGISTER

ADDRESS

R1296

(0510h)

AIF2 ADC

Filters

14:13 AIF2ADC_HPF

_CUT [1:0]

12 AIF2ADCL_HP

F

11 AIF2ADCR_HP

F

00

0

0

Pre-Production

DESCRIPTION

AIF2ADC output path Digital HPF Cut-Off Frequency

(fc)





AIF2ADC (Left) output path Digital HPF Enable

0 = Disabled

1 = Enabled

AIF2ADC (Right) output path Digital HPF Enable

0 = Disabled

1 = Enabled

Register 0510h AIF2 ADC Filters

REGISTER

ADDRESS

R1312

(0520h)

AIF2 DAC

Filters (1)

9 AIF2DAC_MUT

E

7 AIF2DAC_MO

NO

5 AIF2DAC_MUT

ERATE

4 AIF2DAC_UN

MUTE_RAMP

1

0

0

0

DESCRIPTION

AIF2DAC input path Soft Mute Control

0 = Un-mute

1 = Mute

AIF2DAC input path Mono Mix Control

0 = Disabled

1 = Enabled

AIF2DAC input path Soft Mute Ramp Rate




AIF2DAC input path Unmute Ramp select

0 = Disabling soft-mute (AIF2DAC_MUTE=0) will cause the volume to change immediately to AIF2DACL_VOL and AIF2DACR_VOL settings

1 = Disabling soft-mute (AIF2DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the

AIF2DACL_VOL and AIF2DACR_VOL settings

Register 0520h AIF2 DAC Filters (1)

REGISTER

ADDRESS

R1313

(0521h)

AIF2 DAC

Filters (2)

13:9 AIF2DAC_3D_

GAIN [4:0]

8 AIF2DAC_3D_

ENA

DESCRIPTION

0_0000 AIF2DAC playback path 3D Stereo depth

00000 = Off

00001 = Minimum (-16dB)

…(0.915dB steps)

11111 = Maximum (+11.45dB)

0 Enable 3D Stereo in AIF2DAC playback path

0 = Disabled

1 = Enabled

Register 0521h AIF2 DAC Filters (2) w PP, August 2012, Rev 3.4

334

Pre-Production

REGISTER

ADDRESS

R1328

(0430h)

AIF2 DAC

Noise Gate

6:5 AIF2DAC_NG_

HLD [1:0]

3:1 AIF2DAC_NG_

THR [2:0]

0 AIF2DAC_NG_

ENA

11

100

0

DESCRIPTION

AIF2DAC input path Noise Gate Hold Time


00 = 30ms

01 = 125ms

10 = 250ms

11 = 500ms

AIF2DAC input path Noise Gate Threshold

000 = -60dB

001 = -66dB

010 = -72dB

011 = -78dB

100 = -84dB

101 = -90dB

110 = -96dB

111 = -102dB

AIF2DAC input path Noise Gate Enable

0 = Disabled

1 = Enabled

WM8958

Register 0530h AIF2 DAC Noise Gate

REGISTER

ADDRESS

R1344

(0540h)

AIF2 DRC

(1)

DESCRIPTION

15:11 AIF2DRC_SIG

_DET_RMS

[4:0]

10:9 AIF2DRC_SIG

_DET_PK [1:0]

0_0000 AIF2 DRC Signal Detect RMS Threshold.

This is the RMS signal level for signal detect to be indicated when AIF2DRC_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

00

11110 = -75dB

11111 = -76.5dB

AIF2 DRC Signal Detect Peak Threshold.



00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

8 AIF2DRC_NG_

ENA

7 AIF2DRC_SIG

_DET_MODE

6 AIF2DRC_SIG

_DET

5 AIF2DRC_KNE

E2_OP_ENA

0

1

0

0

AIF2 DRC Noise Gate Enable

0 = Disabled

1 = Enabled

AIF2 DRC Signal Detect Mode



AIF2 DRC Signal Detect Enable

0 = Disabled

1 = Enabled

AIF2 DRC KNEE2_OP Enable

0 = Disabled

1 = Enabled

4 AIF2DRC_QR 1 AIF2 DRC Quick-release Enable

0 = Disabled


335

WM8958

REGISTER

ADDRESS

Pre-Production

DESCRIPTION

3 AIF2DRC_ANT

ICLIP

2 AIF2DAC_DRC

_ENA

1 AIF2ADCL_DR

C_ENA

0 AIF2ADCR_DR

C_ENA

1

0

0

0

AIF2 DRC Anti-clip Enable

0 = Disabled

1 = Enabled

Enable DRC in AIF2DAC playback path

0 = Disabled

1 = Enabled

Enable DRC in AIF2ADC (Left) record path

0 = Disabled

1 = Enabled

Enable DRC in AIF2ADC (Right) record path

0 = Disabled

1 = Enabled

Register 0540h AIF2 DRC (1)

REGISTER

ADDRESS

R1345

(0541h)

AIF2 DRC

(2)

12:9 AIF2DRC_ATK

[3:0]

4:2 AIF2DRC_MIN

GAIN [2:0]

1:0 AIF2DRC_MAX

GAIN [1:0]

0100

8:5 AIF2DRC_DCY

[3:0]

0010

001

01

DESCRIPTION

AIF2 DRC Gain attack rate (seconds/6dB)

0000 = Reserved

0001 = 181us

0010 = 363us

0011 = 726us

0100 = 1.45ms

0101 = 2.9ms

0110 = 5.8ms

0111 = 11.6ms

1000 = 23.2ms

1001 = 46.4ms

1010 = 92.8ms

1011 = 185.6ms


AIF2 DRC Gain decay rate (seconds/6dB)

0000 = 186ms

0001 = 372ms

0010 = 743ms

0011 = 1.49s

0100 = 2.97s

0101 = 5.94s

0110 = 11.89s

0111 = 23.78s

1000 = 47.56s


AIF2 DRC Minimum gain to attenuate audio signals

000 = 0dB


010 = -18dB

011 = -24dB

100 = -36dB

101 = Reserved

11X = Reserved

AIF2 DRC Maximum gain to boost audio signals (dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 36dB

Register 0541h AIF2 DRC (2) w PP, August 2012, Rev 3.4

336

Pre-Production

REGISTER

ADDRESS

R1346

(0542h)

AIF2 DRC

(3)

15:12 AIF2DRC_NG_

MINGAIN [3:0]

11:10 AIF2DRC_NG_

EXP [1:0]

9:8 AIF2DRC_QR_

THR [1:0]

7:6 AIF2DRC_QR_

DCY [1:0]

5:3 AIF2DRC_HI_

COMP [2:0]

2:0 AIF2DRC_LO_

COMP [2:0]

DESCRIPTION

0000

00

00

00

000

000

AIF2 DRC Minimum gain to attenuate audio signals when the noise gate is active.

0000 = -36dB

0001 = -30dB

0010 = -24dB

0011 = -18dB

0100 = -12dB

0101 = -6dB

0110 = 0dB

0111 = 6dB

1000 = 12dB

1001 = 18dB

1010 = 24dB

1011 = 30dB

1100 = 36dB


AIF2 DRC Noise Gate slope


01 = 2

10 = 4

11 = 8

AIF2 DRC Quick-release threshold (crest factor in dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF2 DRC Quick-release decay rate (seconds/6dB)

00 = 0.725ms

01 = 1.45ms

10 = 5.8ms

11 = Reserved

AIF2 DRC Compressor slope (upper region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

110 = Reserved

111 = Reserved

AIF2 DRC Compressor slope (lower region)


001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101 = Reserved

11X = Reserved



337

WM8958

REGISTER

ADDRESS

R1347

(0543h)

AIF2 DRC

(4)

10:5 AIF2DRC_KNE

E_IP [5:0]

4:0 AIF2DRC_KNE

E_OP [4:0]

Pre-Production

DESCRIPTION

00_0000 AIF2 DRC Input signal level at the Compressor ‘Knee’.

000000 = 0dB

000001 = -0.75dB

000010 = -1.5dB

… (-0.75dB steps)

111100 = -45dB

111101 = Reserved

11111X = Reserved

0_0000 AIF2 DRC Output signal at the Compressor ‘Knee’.

00000 = 0dB

00001 = -0.75dB

00010 = -1.5dB

… (-0.75dB steps)

11110 = -22.5dB

11111 = Reserved


REGISTER

ADDRESS

R1348

(0544h)

AIF2 DRC

(5)

DESCRIPTION

9:5 AIF2DRC_KNE

E2_IP [4:0]

4:0 AIF2DRC_KNE

E2_OP [4:0]

0_0000 AIF2 DRC Input signal level at the Noise Gate threshold

‘Knee2’.

00000 = -36dB

00001 = -37.5dB

00010 = -39dB

… (-1.5dB steps)

11110 = -81dB

11111 = -82.5dB

Only applicable when AIF2DRC_NG_ENA = 1.

0_0000 AIF2 DRC Output signal at the Noise Gate threshold

‘Knee2’.

00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB

Only applicable when AIF2DRC_KNEE2_OP_ENA = 1.


REGISTER

ADDRESS

R1408

(0580h)

AIF2 EQ

Gains (1)

15:11 AIF2DAC_EQ_

B1_GAIN [4:0]

10:6 AIF2DAC_EQ_

B2_GAIN [4:0]

5:1 AIF2DAC_EQ_

B3_GAIN [4:0]

0 AIF2DAC_EQ_

ENA

DESCRIPTION

0_1100 AIF2 EQ Band 1 Gain






0 Enable EQ in AIF2DAC playback path

0 = Disabled

1 = Enabled

Register 0580h AIF2 EQ Gains (1) w PP, August 2012, Rev 3.4

338

Pre-Production

REGISTER

ADDRESS

R1409

(0581h)

AIF2 EQ

Gains (2)

15:11 AIF2DAC_EQ_

B4_GAIN [4:0]

10:6 AIF2DAC_EQ_

B5_GAIN [4:0]

0 AIF2DAC_EQ_

MODE

DESCRIPTION





0 AIF2 EQ Band 1 Mode

0 = Shelving filter

1 = Peak filter

Register 0581h AIF2 EQ Gains (2)

REGISTER

ADDRESS

R1410

(0582h)

AIF2 EQ

Band 1 A

15:0 AIF2DAC_EQ_

B1_A [15:0]

Register 0582h AIF2 EQ Band 1 A

DESCRIPTION

0000_1111

_1100_101

0


REGISTER

ADDRESS

R1411

(0583h)

AIF2 EQ

Band 1 B

15:0 AIF2DAC_EQ_

B1_B [15:0]

Register 0583h AIF2 EQ Band 1 B

DESCRIPTION

0000_0100

_0000_000

0


REGISTER

ADDRESS

R1412

(0584h)

AIF2 EQ

Band 1 PG

15:0 AIF2DAC_EQ_

B1_PG [15:0]

Register 0584h AIF2 EQ Band 1 PG

DESCRIPTION

0000_0000

_1101_100

0


REGISTER

ADDRESS

R1413

(0585h)

AIF2 EQ

Band 2 A

15:0 AIF2DAC_EQ_

B2_A [15:0]


DESCRIPTION

0001_1110

_1011_010

1


REGISTER

ADDRESS

R1414

(0586h)

AIF2 EQ

Band 2 B

15:0 AIF2DAC_EQ_

B2_B [15:0]


DESCRIPTION

1111_0001

_0100_010

1


WM8958


339

WM8958

Pre-Production

REGISTER

ADDRESS

R1415

(0587h)

AIF2 EQ

Band 2 C

15:0 AIF2DAC_EQ_

B2_C [15:0]

Register 0587h AIF2 EQ Band 2 C

DESCRIPTION

0000_1011

_0111_010

1


REGISTER

ADDRESS

R1416

(0588h)

AIF2 EQ

Band 2 PG

15:0 AIF2DAC_EQ_

B2_PG [15:0]


DESCRIPTION

0000_0001

_1100_010

1


REGISTER

ADDRESS

R1417

(0589h)

AIF2 EQ

Band 3 A

15:0 AIF2DAC_EQ_

B3_A [15:0]


DESCRIPTION

0001_1100

_0101_100

0


REGISTER

ADDRESS

R1418

(058Ah)

AIF2 EQ

Band 3 B

15:0 AIF2DAC_EQ_

B3_B [15:0]

Register 058Ah AIF2 EQ Band 3 B

DESCRIPTION

1111_0011

_0111_001

1


REGISTER

ADDRESS

R1419

(058Bh)

AIF2 EQ

Band 3 C

15:0 AIF2DAC_EQ_

B3_C [15:0]

Register 058Bh AIF2 EQ Band 3 C

DESCRIPTION

0000_1010

_0101_010

0


REGISTER

ADDRESS

R1420

(058Ch)

AIF2 EQ

Band 3 PG

15:0 AIF2DAC_EQ_

B3_PG [15:0]

Register 058Ch AIF2 EQ Band 3 PG

DESCRIPTION

0000_0101

_0101_100

0


340

Pre-Production

REGISTER

ADDRESS

R1421

(058Dh)

AIF2 EQ

Band 4 A

15:0 AIF2DAC_EQ_

B4_A [15:0]

Register 058Dh AIF2 EQ Band 4 A

DESCRIPTION

0001_0110

_1000_111

0


REGISTER

ADDRESS

R1422

(058Eh)

AIF2 EQ

Band 4 B

15:0 AIF2DAC_EQ_

B4_B [15:0]

Register 058Eh AIF2 EQ Band 4 B

DESCRIPTION

1111_1000

_0010_100

1


REGISTER

ADDRESS

R1423

(058Fh)

AIF2 EQ

Band 4 C

15:0 AIF2DAC_EQ_

B4_C [15:0]

Register 058Fh AIF2 EQ Band 4 C

DESCRIPTION

0000_0111

_1010_110

1


REGISTER

ADDRESS

R1424

(0590h)

AIF2 EQ

Band 4 PG

15:0 AIF2DAC_EQ_

B4_PG [15:0]


DESCRIPTION

0001_0001

_0000_001

1


REGISTER

ADDRESS

R1425

(0591h)

AIF2 EQ

Band 5 A

15:0 AIF2DAC_EQ_

B5_A [15:0]


DESCRIPTION

0000_0101

_0110_010

0


REGISTER

ADDRESS

R1426

(0592h)

AIF2 EQ

Band 5 B

15:0 AIF2DAC_EQ_

B5_B [15:0]


DESCRIPTION

0000_0101

_0101_100

1


WM8958


341

WM8958

Pre-Production

REGISTER

ADDRESS

R1427

(0593h)

AIF2 EQ

Band 5 PG

15:0 AIF2DAC_EQ_

B5_PG [15:0]


DESCRIPTION

0100_0000

_0000_000

0


REGISTER

ADDRESS

R1536

(0600h)

DAC1 Mixer

Volumes

8:5 ADCR_DAC1_

VOL [3:0]

DESCRIPTION

3:0 ADCL_DAC1_

VOL [3:0]

0000

0000

Sidetone STR to DAC1L and DAC1R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB

Sidetone STL to DAC1L and DAC1R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB

Register 0600h DAC1 Mixer Volumes

REGISTER

ADDRESS

R1537

(0601h)

DAC1 Left

Mixer

Routing

5 ADCR_TO_DA

C1L

4 ADCL_TO_DA

C1L

2 AIF2DACL_TO

_DAC1L

1 AIF1DAC2L_T

O_DAC1L

0 AIF1DAC1L_T

O_DAC1L

0

0

0

0

0

DESCRIPTION


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Enable AIF1 (Timeslot 1, Left) to DAC1L

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Register 0601h DAC1 Left Mixer Routing

REGISTER

ADDRESS

R1538

(0602h)

DAC1 Right

Mixer

Routing

5 ADCR_TO_DA

C1R

4 ADCL_TO_DA

C1R

0

0

DESCRIPTION


0 = Disabled

1 = Enabled


0 = Disabled


342

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

2 AIF2DACR_TO

_DAC1R

1 AIF1DAC2R_T

O_DAC1R

0 AIF1DAC1R_T

O_DAC1R

Register 0602h DAC1 Right Mixer Routing

REGISTER

ADDRESS

R1539

(0603h)

DAC2 Mixer

Volumes

8:5 ADCR_DAC2_

VOL [3:0]

3:0 ADCL_DAC2_

VOL [3:0]

DESCRIPTION

0000

0000

Sidetone STR to DAC2L and DAC2R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB

Sidetone STL to DAC2L and DAC2R Volume

0000 = -36dB

0001 = -33dB

…. (3dB steps)

1011 = -3dB

1100 = 0dB

Register 0603h DAC2 Mixer Volumes

REGISTER

ADDRESS

R1540

(0604h)

DAC2 Left

Mixer

Routing

5 ADCR_TO_DA

C2L

4 ADCL_TO_DA

C2L

2 AIF2DACL_TO

_DAC2L

1 AIF1DAC2L_T

O_DAC2L

0 AIF1DAC1L_T

O_DAC2L

0

0

0

0

0

0

0

0


0 = Disabled

1 = Enabled

Enable AIF1 (Timeslot 1, Right) to DAC1R

0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

DESCRIPTION


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Register 0604h DAC2 Left Mixer Routing


343

WM8958

REGISTER

ADDRESS

R1541

(0605h)

DAC2 Right

Mixer

Routing

5 ADCR_TO_DA

C2R

4 ADCL_TO_DA

C2R

2 AIF2DACR_TO

_DAC2R

1 AIF1DAC2R_T

O_DAC2R

0 AIF1DAC1R_T

O_DAC2R

Register 0605h DAC2 Right Mixer Routing

REGISTER

ADDRESS

R1542

(0606h)

AIF1 ADC1

Left Mixer

Routing

1 ADC1L_TO_AI

F1ADC1L

0 AIF2DACL_TO

_AIF1ADC1L

0

0

0

0

0

0

0

Pre-Production

DESCRIPTION


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

Enable ADCL / DMIC1 (Left) to AIF1 (Timeslot 0, Left) output

0 = Disabled

1 = Enabled

Enable AIF2 (Left) to AIF1 (Timeslot 0, Left) output

0 = Disabled

1 = Enabled

DESCRIPTION

Register 0606h AIF1 ADC1 Left Mixer Routing

REGISTER

ADDRESS

R1543

(0607h)

AIF1 ADC1

Right Mixer

Routing

1 ADC1R_TO_AI

F1ADC1R

0 AIF2DACR_TO

_AIF1ADC1R

0

0

DESCRIPTION

Enable ADCR / DMIC1 (Right) to AIF1 (Timeslot 0,

Right) output

0 = Disabled

1 = Enabled

Enable AIF2 (Right) to AIF1 (Timeslot 0, Right) output

0 = Disabled

1 = Enabled

Register 0607h AIF1 ADC1 Right Mixer Routing

REGISTER

ADDRESS

R1544

(0608h)

AIF1 ADC2

Left Mixer

Routing

1 ADC2L_TO_AI

F1ADC2L

0 AIF2DACL_TO

_AIF1ADC2L

0

0

DESCRIPTION

Enable DMIC2 (Left) to AIF1 (Timeslot 1, Left) output

0 = Disabled

1 = Enabled

Enable AIF2 (Left) to AIF1 (Timeslot 1, Left) output

0 = Disabled

1 = Enabled

Register 0608h AIF1 ADC2 Left Mixer Routing w PP, August 2012, Rev 3.4

344

Pre-Production

REGISTER

ADDRESS

R1545

(0609h)

AIF1 ADC2

Right mixer

Routing

1 ADC2R_TO_AI

F1ADC2R

0 AIF2DACR_TO

_AIF1ADC2R

0

0

DESCRIPTION

Enable DMIC2 (Right) to AIF1 (Timeslot 1, Right) output

0 = Disabled

1 = Enabled

Enable AIF2 (Right) to AIF1 (Timeslot 1, Right) output

0 = Disabled

1 = Enabled

Register 0609h AIF1 ADC2 Right mixer Routing

REGISTER

ADDRESS

R1552

(0610h)

DAC1 Left

Volume

DESCRIPTION

9 DAC1L_MUTE 1 DAC1L Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute

8 DAC1_VU 0 DAC1L and DAC1R Volume Update

Writing a 1 to this bit will cause the DAC1L and DAC1R volume to be updated simultaneously

[7:0] 00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB

Register 0610h DAC1 Left Volume

REGISTER

ADDRESS

R1553

(0611h)

DAC1 Right

Volume

DESCRIPTION

9 DAC1R_MUTE 1 DAC1R Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute



[7:0]

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB

Register 0611h DAC1 Right Volume


345

WM8958

Pre-Production

REGISTER

ADDRESS

R1554

(0612h)

DAC2 Left

Volume

DESCRIPTION

9 DAC2L_MUTE 1 DAC2L Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute



[7:0]

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB

Register 0612h DAC2 Left Volume

REGISTER

ADDRESS

R1555

(0613h)

DAC2 Right

Volume

DESCRIPTION

9 DAC2R_MUTE 1 DAC2R Soft Mute Control

0 = DAC Un-mute

1 = DAC Mute



[7:0]

00h = MUTE

01h = -71.625dB

… (0.375dB steps)

C0h = 0dB

… (0.375dB steps)

E0h = 12dB

FFh = 12dB

Register 0613h DAC2 Right Volume

REGISTER

ADDRESS

R1556

(0614h)

DAC

Softmute

1 DAC_SOFTMU

TEMODE

0

DESCRIPTION

0 DAC_MUTERA

TE

0

DAC Unmute Ramp select

0 = Disabling soft-mute (DAC [1/2] [L/R]_MUTE=0) will cause the DAC volume to change immediately to DAC

[1/2] [L/R]_VOL settings

1 = Disabling soft-mute (DAC [1/2] [L/R]_MUTE=0) will cause the DAC volume to ramp up gradually to the DAC

[1/2] [L/R]_VOL settings

DAC Soft Mute Ramp Rate




Register 0614h DAC Softmute w PP, August 2012, Rev 3.4

346

Pre-Production

REGISTER

ADDRESS

R1568

(0620h)

Oversamplin g

DESCRIPTION

1 ADC_OSR128 1 ADC / Digital Microphone Oversample Rate Select

0 = Low Power


0 DAC_OSR128 0 DAC Oversample Rate Select

0 = Low Power


Register 0620h Oversampling

REGISTER

ADDRESS

R1569

(0621h)

Sidetone

9:7 ST_HPF_CUT

[2:0]

000

DESCRIPTION

Sidetone HPF cut-off frequency (relative to 44.1kHz sample rate)

000 = 2.7kHz

001 = 1.35kHz

010 = 675Hz

011 = 370Hz

100 = 180Hz

101 = 90Hz

110 = 45Hz

111 = Reserved

Note - the cut-off frequencies scale with the Digital

Mixing (SYSCLK) clocking rate. The quoted figures apply to 44.1kHz sample rate.

0 = Disabled

1 = Enabled

1 STR_SEL 0 Select source for sidetone STR path

0 = ADCR / DMICDAT1 (Right)

1 = DMICDAT2 (Right)

0 = ADCL / DMICDAT1 (Left)

1 = DMICDAT2 (Left)

Register 0621h Sidetone

REGISTER

ADDRESS

R1792

(0700h)

GPIO 1

DESCRIPTION

15 GP1_DIR 1 GPIO1 Pin Direction

0 = Output

1 = Input

14 GP1_PU 0 GPIO1 Pull-Up Enable

0 = Disabled

1 = Enabled

13 GP1_PD 0 GPIO1 Pull-Down Enable

0 = Disabled

1 = Enabled

10 GP1_POL 0 GPIO1 Polarity Select



9 GP1_OP_CFG 0 GPIO1 Output Configuration

0 = CMOS

1 = Open Drain w

WM8958


347

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

0 = Disabled

1 = Enabled

6 GP1_LVL 0 GPIO1 level. Write to this bit to set a GPIO output.

Read from this bit to read GPIO input level.

For output functions only, when GP1_POL is set, the register contains the opposite logic level to the external pin.

00h = ADCLRCLK1

01h = GPIO

02h = Reserved

03h = IRQ

04h = Temperature (Shutdown) status

05h = MICDET status

06h = Reserved

07h = Reserved

08h = Reserved

09h = FLL1 Lock

0Ah = FLL2 Lock

0Bh = SRC1 Lock

0Ch = SRC2 Lock

0Dh = AIF1 DRC1 Signal Detect

0Eh = AIF1 DRC2 Signal Detect

0Fh = AIF2 DRC Signal Detect

10h = Write Sequencer Status

11h = FIFO Error

12h = OPCLK Clock output

13h = Temperature (Warning) status

14h = DC Servo Done

15h = FLL1 Clock output


17h to 1Fh = Reserved

Register 0700h GPIO 1

REGISTER

ADDRESS

R1793

(0701h) Pull

Control

(MCLK2)

DESCRIPTION

14 MCLK2_PU 0 MCLK2 Pull-up enable

0 = Disabled

1 = Enabled

13 MCLK2_PD 1 MCLK2 Pull-down enable

0 = Disabled

1 = Enabled

Register 0701h Pull Control (MCLK2) w PP, August 2012, Rev 3.4

348

Pre-Production

REGISTER

ADDRESS

R1794

(0702h) Pull

Control

(BCLK2)

DESCRIPTION

14 BCLK2_PU 0 BCLK2 Pull-up enable

0 = Disabled

1 = Enabled

13 BCLK2_PD 1 BCLK2 Pull-down enable

0 = Disabled

1 = Enabled

Register 0702h Pull Control (BCLK2)

REGISTER

ADDRESS

R1795

(0703h) Pull

Control

(DACLRCLK

2)

14 DACLRCLK2_

PU

13 DACLRCLK2_

PD

0

1

DESCRIPTION

DACLRCLK2 Pull-up enable

0 = Disabled

1 = Enabled

DACLRCLK2 Pull-down enable

0 = Disabled

1 = Enabled

Register 0703h Pull Control (DACLRCLK2)

REGISTER

ADDRESS

R1796

(0704h) Pull

Control

(DACDAT2)

DESCRIPTION

14 DACDAT2_PU 0 DACDAT2 Pull-up enable

0 = Disabled

1 = Enabled

13 DACDAT2_PD 1 DACDAT2 Pull-down enable

0 = Disabled

1 = Enabled

Register 0704h Pull Control (DACDAT2)

REGISTER

ADDRESS

R1797

(0705h)

GPIO 6

DESCRIPTION


0 = Output

1 = Input


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled





0 = CMOS

1 = Open Drain

0 = Disabled

1 = Enabled w

WM8958


349

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION




00h = ADCLRCLK2

01h = GPIO

02h = Reserved

03h = IRQ


05h = MICDET status

06h = Reserved

07h = Reserved

08h = Reserved

09h = FLL1 Lock

0Ah = FLL2 Lock

0Bh = SRC1 Lock

0Ch = SRC2 Lock





11h = FIFO Error



14h = DC Servo Done





REGISTER

ADDRESS

R1799

(0707h)

GPIO 8

DESCRIPTION


0 = Output

1 = Input


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled





0 = CMOS

1 = Open Drain

0 = Disabled

1 = Enabled



w

350

Pre-Production

REGISTER

ADDRESS

DESCRIPTION



00h = DACDAT3

01h = GPIO

02h = Reserved

03h = IRQ


05h = MICDET status

06h = Reserved

07h = Reserved

08h = Reserved

09h = FLL1 Lock

0Ah = FLL2 Lock

0Bh = SRC1 Lock

0Ch = SRC2 Lock





11h = FIFO Error



14h = DC Servo Done





REGISTER

ADDRESS

R1800

(0708h)

GPIO 9

DESCRIPTION


0 = Output

1 = Input


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled





0 = CMOS

1 = Open Drain

0 = Disabled

1 = Enabled


351

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION




00h = ADCDAT3

01h = GPIO

02h = Reserved

03h = IRQ


05h = MICDET status

06h = Reserved

07h = Reserved

08h = Reserved

09h = FLL1 Lock

0Ah = FLL2 Lock

0Bh = SRC1 Lock

0Ch = SRC2 Lock





11h = FIFO Error



14h = DC Servo Done





REGISTER

ADDRESS

R1801

(0709h)

GPIO 10

DESCRIPTION


0 = Output

1 = Input


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled




9 GP10_OP_CF

G

0 GPIO10 Output Configuration

0 = CMOS

1 = Open Drain

8 GP10_DB 1 GPIO10 Input De-bounce

0 = Disabled


352

Pre-Production

REGISTER

ADDRESS

DESCRIPTION




00h = LRCLK3

01h = GPIO

02h = Reserved

03h = IRQ


05h = MICDET status

06h = Reserved

07h = Reserved

08h = Reserved

09h = FLL1 Lock

0Ah = FLL2 Lock

0Bh = SRC1 Lock

0Ch = SRC2 Lock





11h = FIFO Error



14h = DC Servo Done





REGISTER

ADDRESS

R1802

(070Ah)

GPIO 11

DESCRIPTION


0 = Output

1 = Input


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled




9 GP11_OP_CF

G

0 GPIO11 Output Configuration

0 = CMOS

1 = Open Drain

8 GP11_DB 1 GPIO11 Input De-bounce

0 = Disabled

1 = Enabled w

WM8958


353

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION




00h = BCLK3

01h = GPIO

02h = Reserved

03h = IRQ


05h = MICDET status

06h = Reserved

07h = Reserved

08h = Reserved

09h = FLL1 Lock

0Ah = FLL2 Lock

0Bh = SRC1 Lock

0Ch = SRC2 Lock





11h = FIFO Error



14h = DC Servo Done




Register 070Ah GPIO 11

REGISTER

ADDRESS

R1824

(0720h) Pull

Control (1)

DESCRIPTION

11 DMICDAT2_P

U

10 DMICDAT2_P

D

9 DMICDAT1_P

U

8 DMICDAT1_P

D

0

0

0

0


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled


0 = Disabled

1 = Enabled

7 MCLK1_PU 0 MCLK1 Pull-up enable

0 = Disabled

1 = Enabled

6 MCLK1_PD 0 MCLK1 Pull-down enable

0 = Disabled


354

Pre-Production

REGISTER

ADDRESS

DESCRIPTION

5 DACDAT1_PU 0 DACDAT1 Pull-up enable

0 = Disabled

1 = Enabled

4 DACDAT1_PD 0 DACDAT1 Pull-down enable

0 = Disabled

1 = Enabled

3 DACLRCLK1_

PU

0 LRCLK1 Pull-up enable

0 = Disabled

1 = Enabled

2 DACLRCLK1_

PD

0 LRCLK1 Pull-down enable

0 = Disabled

1 = Enabled

1 BCLK1_PU 0 BCLK1 Pull-up enable

0 = Disabled

1 = Enabled

0 BCLK1_PD 0 BCLK1 Pull-down enable

0 = Disabled

1 = Enabled

Register 0720h Pull Control (1)

REGISTER

ADDRESS

R1825

(0721h) Pull

Control (2)

DESCRIPTION

8 ADDR_PD 1 ADDR Pull-down enable

0 = Disabled

1 = Enabled

6 LDO2ENA_PD 1 LDO2ENA Pull-down enable

0 = Disabled

1 = Enabled

4 LDO1ENA_PD 1 LDO1ENA Pull-down enable

0 = Disabled

1 = Enabled

1 SPKMODE_PU 1 SPKMODE Pull-up enable

0 = Disabled

1 = Enabled

Register 0721h Pull Control (2)

REGISTER

ADDRESS

R1840

(0730h)

Interrupt

Status 1

DESCRIPTION

10 GP11_EINT 0 GPIO11 Interrupt











Note: Cleared when a ‘1’ is written. w

WM8958


355

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION







Register 0730h Interrupt Status 1

REGISTER

ADDRESS

R1841

(0731h)

Interrupt

Status 2

DESCRIPTION

15 TEMP_WARN_

EINT

14 DCS_DONE_E

INT

13 WSEQ_DONE

_EINT

12 FIFOS_ERR_E

INT

11 AIF2DRC_SIG

_DET_EINT

10 AIF1DRC2_SI

G_DET_EINT

9 AIF1DRC1_SI

G_DET_EINT

8 SRC2_LOCK_

EINT

0

0

0

0

0

0

0

0

Temperature Warning Interrupt



DC Servo Interrupt



Write Sequencer Interrupt



Digital Core FIFO Error Interrupt



AIF2 DRC Activity Detect Interrupt



AIF1 DRC2 (Timeslot 1) Activity Detect Interrupt



AIF1 DRC1 (Timeslot 0) Activity Detect Interrupt



SRC2 Lock Interrupt



7 SRC1_LOCK_

EINT

6 FLL2_LOCK_E

INT

0

0

SRC1 Lock Interrupt



FLL2 Lock Interrupt



5 FLL1_LOCK_E

INT

0 TEMP_SHUT_

EINT

0 FLL1 Lock Interrupt



1 MICD_EINT 0 Microphone Detection Interrupt



0 Temperature Shutdown Interrupt



Register 0731h Interrupt Status 2 w PP, August 2012, Rev 3.4

356

Pre-Production

REGISTER

ADDRESS

R1842

(0732h)

Interrupt

Raw Status

2

15 TEMP_WARN_

STS

14 DCS_DONE_S

TS

13 WSEQ_DONE

_STS

12 FIFOS_ERR_S

TS

11 AIF2DRC_SIG

_DET_STS

10 AIF1DRC2_SI

G_DET_STS

9 AIF1DRC1_SI

G_DET_STS

8 SRC2_LOCK_

STS

7 SRC1_LOCK_

STS

6 FLL2_LOCK_S

TS

5 FLL1_LOCK_S

TS

0 TEMP_SHUT_

STS

0

0

0

0

0

0

0

0

0

0

0

0

DESCRIPTION

Temperature Warning status



DC Servo status



Write Sequencer status

0 = Sequencer Busy (sequence in progress)

1 = Sequencer Idle

Digital Core FIFO Error status


1 = FIFO Error

AIF2 DRC Signal Detect status









SRC2 Lock status

0 = Not locked

1 = Locked

SRC1 Lock status

0 = Not locked

1 = Locked

FLL2 Lock status

0 = Not locked

1 = Locked

FLL1 Lock status

0 = Not locked

1 = Locked

Temperature Shutdown status



Register 0732h Interrupt Raw Status 2

REGISTER

ADDRESS

R1848

(0738h)

Interrupt

Status 1

Mask

DESCRIPTION

10 IM_GP11_EIN

T

9 IM_GP10_EIN

T

1

1



1 = Mask interrupt.



1 = Mask interrupt.

8 IM_GP9_EINT 1 GPIO9 Interrupt mask.


1 = Mask interrupt.



1 = Mask interrupt. w

WM8958


357

WM8958

Pre-Production

REGISTER

ADDRESS

DESCRIPTION



1 = Mask interrupt.



1 = Mask interrupt.

Register 0738h Interrupt Status 1 Mask

REGISTER

ADDRESS

R1849

(0739h)

Interrupt

Status 2

Mask

15 IM_TEMP_WA

RN_EINT

14 IM_DCS_DON

E_EINT

1

1

DESCRIPTION

13 IM_WSEQ_DO

NE_EINT

12 IM_FIFOS_ER

R_EINT

11 IM_AIF2DRC_

SIG_DET_EIN

T

10 IM_AIF1DRC2

_SIG_DET_EI

NT

9 IM_AIF1DRC1

_SIG_DET_EI

NT

8 IM_SRC2_LOC

K_EINT

7 IM_SRC1_LOC

K_EINT

6 IM_FLL2_LOC

K_EINT

5 IM_FLL1_LOC

K_EINT

1 IM_MICD_EIN

T

0 IM_TEMP_SH

UT_EINT

1

1

1

1

1

1

1

1

1

1

1

Temperature Warning Interrupt mask.


1 = Mask interrupt.

DC Servo Interrupt mask.


1 = Mask interrupt.

Write Sequencer Interrupt mask.


1 = Mask interrupt.

Digital Core FIFO Error Interrupt mask.


1 = Mask interrupt.

AIF2 DRC Activity Detect Interrupt mask.


1 = Mask interrupt.

AIF1 DRC2 (Timeslot 1) Activity Detect Interrupt mask.


1 = Mask interrupt.

AIF1 DRC1 (Timeslot 0) Activity Detect Interrupt mask.


1 = Mask interrupt.



1 = Mask interrupt.



1 = Mask interrupt.



1 = Mask interrupt.



1 = Mask interrupt.

Microphone Detection Interrupt mask.


1 = Mask interrupt.

Temperature Shutdown Interrupt mask.


1 = Mask interrupt.

Register 0739h Interrupt Status 2 Mask w PP, August 2012, Rev 3.4

358

Pre-Production

REGISTER

ADDRESS

R1856

(0740h)

Interrupt

Control

Register 0740h Interrupt Control

DESCRIPTION


1 = Mask interrupt.

REGISTER

ADDRESS

R1864

(0748h) IRQ

Debounce

5 TEMP_WARN_

DB

0 TEMP_SHUT_

DB

1

1

DESCRIPTION

Temperature Warning de-bounce

0 = Disabled

1 = Enabled

Thermal shutdown de-bounce

0 = Disabled

1 = Enabled

Register 0748h IRQ Debounce

REGISTER

ADDRESS

R2304

(0900h)

DSP2_Progr am

DESCRIPTION

0 DSP2_ENA 0 DSP2 Audio Processor Enable.

0 = Disabled

1 = Enabled

This bit must be set before the MBC is enabled. It must remain set whenever the MBC is enabled.

Register 0900h DSP2_Program

REGISTER

ADDRESS

R2305

(0901h)

DSP2_Confi g

DESCRIPTION

00 = AIF1DAC1 input path (AIF1, Timeslot 0)

01 = AIF1DAC2 input path (AIF1, Timeslot 1)

10 = AIF2DAC input path

11 = Reserved

0 MBC_ENA 0 MBC Enable

0 = Disabled

1 = Enabled

Register 0901h DSP2_Config

REGISTER

ADDRESS

R2573

(0A0Dh)

DSP2_Exec

Control

2

1

DSP2_STOP

DSP2_RUNR

0

0

DESCRIPTION

Stop the DSP2 audio processor

Writing a 1 to this bit will cause the DSP2 processor to stop processing audio data

Start the DSP2 audio processor

Writing a 1 to this bit will cause the DSP2 processor to start processing audio data

Register 0A0Dh DSP2_ExecControl w

WM8958


359

WM8958

APPLICATIONS INFORMATION

Pre-Production

RECOMMENDED EXTERNAL COMPONENTS

AUDIO INPUT PATHS

The WM8958 provides 8 analogue audio inputs. Each of these inputs is referenced to the internal DC reference, VMID. A DC blocking capacitor is required for each input pin used in the target application.

The choice of capacitor is determined by the filter that is formed between that capacitor and the input impedance of the input pin. The circuit is illustrated in Figure 84. w

Figure 84 Audio Input Path DC Blocking Capacitor

If the input impedance is known, and the cut-off frequency is known, then the minimum capacitor value may be derived easily. However, it can be seen from the representation in Figure 84 that the input impedance is not fixed in all applications but can vary with gain and boost amplifier settings.

The PGA input resistance for every gain setting is detailed in Table 153.

IN1L_VOL[4:0],

IN2L_VOL[4:0],

IN1R_VOL[4:0],

IN2R_VOL[4:0]

VOLUME

(dB)

INPUT RESISTANCE

(kΩ)

SINGLE-ENDED

MODE

DIFFERENTIAL

MODE

00000 -16.5 58 52.5

00001 -15.0 56.9 50.6

00010 -13.5 55.6 48.6

00011 -12.0 54.1 46.4

00100 -10.5 52.5 44.1

00101 -9.0 50.7 41.5

00110 -7.5 48.6 38.9

00111 -6.0 46.5 36.2

01000 -4.5 44.1 33.4

01001 -3.0 41.6 30.6

01010 -1.5 38.9 27.8

01100 +1.5 33.4 22.5

01101 +3.0 30.6 20.0

01110 +4.5 27.8 17.7

01111 +6.0 25.1 15.6

10000 +7.5 22.5 13.6

10001 +9.0 20.1 11.9

10010 +10.5 17.8 10.3

10011 +12.0 15.6 8.9

10100 +13.5 13.7 7.6

10101 +15.0 11.9 6.5


360

Pre-Production w

WM8958

IN1L_VOL[4:0],

IN2L_VOL[4:0],

IN1R_VOL[4:0],

IN2R_VOL[4:0]

VOLUME

(dB)

INPUT RESISTANCE

(kΩ)

SINGLE-ENDED

MODE

DIFFERENTIAL

MODE

10110 +16.5 10.3 5.6

10111 +18.0 8.9 4.8

11000 +19.5 7.7 4.1

11001 +21.0 6.6 3.5

11010 +22.5 5.6 2.9

11011 +24.0 4.8 2.5

11100 +25.5 4.1 2.1

11101 +27.0 3.5 1.8

11110 +28.5 2.9 1.5

11111 +30.0 2.5 1.3

Table 153 PGA Input Pin Resistance

The appropriate input capacitor may be selected using the PGA input resistance data provided in

Table 153, depending on the required PGA gain setting(s).

The choice of capacitor for a 20Hz cut-off frequency is shown in Table 154 for a selection of typical input impedance conditions.

INPUT IMPEDANCE MINIMUM CAPACITANCE

FOR 20HZ PASS BAND

2k  4

15k  0.5

30k  0.27

60k  0.13

Table 154 Audio Input DC Blocking Capacitors

Using the figures in Table 154, it follows that a 1 F capacitance for all input connections will give good results in most cases. Tantalum electrolytic capacitors are particularly suitable as they offer high stability in a small package size.

Ceramic equivalents are a cost effective alternative to the superior tantalum packages, but care must be taken to ensure the desired capacitance is maintained at the AVDD1 operating voltage. Also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to electrical signals. This is particularly problematic for microphone input paths where a large signal gain is required.

A single capacitor is required for a line input or single-ended microphone connection. In the case of a differential microphone connection, a DC blocking capacitor is required on both input pins.

HEADPHONE OUTPUT PATH

The headphone output on WM8958 is ground referenced and therefore does not require the large, expensive capacitors necessary for VMID reference solutions. For best audio performance, it is recommended to connect a zobel network to the audio output pins. This network should comprise of a

100nF capacitor and 20ohm resistor in series with each other (see “Analogue Outputs” section).

These components have the effect of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions. Possible sources of these instabilities include the inductive load of a headphone coil or an active load in the form of an external line amplifier.


361

WM8958

Pre-Production

EARPIECE DRIVER OUTPUT PATH

The earpiece driver on HPOUT2P and HPOUT2N is designed as a 32ohm BTL speaker driver. The outputs are referenced to the internal DC reference VMID, but direct connection to the speaker is possible because of the BTL configuration. There is no requirement for DC blocking capacitors.

LINE OUTPUT PATHS

The WM8958 provides four line outputs (LINEOUT1P, LINEOUT1N, LINEOUT2P and LINEOUT2N).

Each of these outputs is referenced to the internal DC reference, VMID. In any case where a line output is used in a single-ended configuration (i.e. referenced to AGND), a DC blocking capacitor will be required in order to remove the DC bias. In the case where a pair of line outputs is configured as a

BTL differential pair, then the DC blocking capacitor should be omitted.

The choice of capacitor is determined from the filter that is formed between the capacitor and the load impedance – see Figure 85.

Figure 85 Line Output Path Components

LOAD IMPEDANCE MINIMUM CAPACITANCE

FOR 20HZ PASS BAND

10k  0.8

47k  0.17

Table 155 Line Output Frequency Cut-Off

Using the figures in Table 155, it follows that that a 1 F capacitance would be a suitable choice for a line load. Tantalum electrolytic capacitors are again particularly suitable but ceramic equivalents are a cost effective alternative. Care must be taken to ensure the desired capacitance is maintained at the appropriate operating voltage. w PP, August 2012, Rev 3.4

362

Pre-Production

WM8958

POWER SUPPLY DECOUPLING

Electrical coupling exists particularly in digital logic systems where switching in one sub-system causes fluctuations on the power supply. This effect occurs because the inductance of the power supply acts in opposition to the changes in current flow that are caused by the logic switching. The resultant variations (or ‘spikes’) in the power supply voltage can cause malfunctions and unintentional behavior in other components. A decoupling (or ‘bypass’) capacitor can be used as an energy storage component which will provide power to the decoupled circuit for the duration of these power supply variations, protecting it from malfunctions that could otherwise arise.

Coupling also occurs in a lower frequency form when ripple is present on the power supply rail caused by changes in the load current or by limitations of the power supply regulation method. In audio components such as the WM8958, these variations can alter the performance of the signal path, leading to degradation in signal quality. A decoupling (or ‘bypass’) capacitor can be used to filter these effects, by presenting the ripple voltage with a low impedance path that does not affect the circuit to be decoupled.

These coupling effects are addressed by placing a capacitor between the supply rail and the corresponding ground reference. In the case of systems comprising multiple power supply rails, decoupling should be provided on each rail.

The recommended power supply decoupling capacitors for WM8958 are listed below in Table 156.

POWER SUPPLY

LDO1VDD, DBVDD1, DBVDD2, DBVDD3,

AVDD2

0.1

DECOUPLING CAPACITOR

F ceramic (see Note)

SPKVDD1, SPKVDD2 4.7

F ceramic

AVDD1 4.7

F ceramic

DCVDD 2.2

F ceramic

CPVDD 4.7

F ceramic

VMIDC 4.7

F ceramic

VREFC 1.0

F ceramic

Table 156 Power Supply Decoupling Capacitors

Note: 0.1

F is required with 4.7F a guide to the total required power rail capacitance, including that at the regulator output.

All decoupling capacitors should be placed as close as possible to the WM8958 device. The connection between AGND, the AVDD1 decoupling capacitor and the main system ground should be made at a single point as close as possible to the AGND ball of the WM8958.

The VMID capacitor is not, technically, a decoupling capacitor. However, it does serve a similar purpose in filtering noise on the VMID reference. The connection between AGND, the VMID decoupling capacitor and the main system ground should be made at a single point as close as possible to the AGND ball of the WM8958.

Due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. For most applications, the use of ceramic capacitors with capacitor dielectric X5R is recommended. w PP, August 2012, Rev 3.4

363

WM8958

Pre-Production

CHARGE PUMP COMPONENTS

A fly-back capacitor is required between the CPCA and CPCB pins. The required capacitance is

2.2µF at 2V.

A decoupling capacitor is required on CPVOUTP and CPVOUTN; the recommended value is 2.2µF at

2V.

The positioning of the Charge Pump capacitors is important, particularly the fly-back capacitor. These capacitors should be placed as close as possible to the WM8958.

Due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. For most applications, the use of ceramic capacitors with capacitor dielectric X5R is recommended.

MICROPHONE BIAS CIRCUIT

The WM8958 is designed to interface easily with up to four analogue microphones. These may be connected in single-ended or differential configurations, as illustrated in Figure 86. The single-ended method allows greater capability for the connection of multiple audio sources simultaneously, whilst the differential method provides better performance due to its rejection of common-mode noise.

In either configuration, the analogue microphone requires a bias current (electret condenser microphones) or voltage supply (silicon microphones), which can be provided by MICBIAS1 or

MICBIAS2.

A current-limiting resistor is required when using an electret condenser microphone (ECM). The resistance should be chosen according to the minimum operating impedance of the microphone and

MICBIAS voltage so that the maximum bias current of the WM8958 is not exceeded. Wolfson recommends a 2.2k

 current limiting resistor as it provides compatibility with a wide range of microphone models.

MIC

AGND

C

IN1LN,

IN2LN,

IN1RN,

IN2RN

IN1LP,

IN2LP,

IN1RP,

IN2RP

2k2

VMID

Line Input

MICBIAS1/2

-

+

PGA

To input mixers

AGND

2k2

MIC

C

IN1LN,

IN2LN,

IN1RN,

IN2RN

C

IN1LP,

IN2LP,

IN1RP,

IN2RP

2k2

VMID

Line Input

MICBIAS1/2

-

+

PGA

To input mixers

Figure 86 Single-Ended and Differential Analogue Microphone Connections

The WM8958 also supports up to four digital microphone inputs. The MICBIAS1 generator is suitable for use as a low noise supply for digital microphones, as shown in Figure 87. w PP, August 2012, Rev 3.4

364

Pre-Production

WM8958

Figure 87 Digital Microphone Connection

The MICBIAS generators can each operate as a voltage regulator or in bypass mode. See “Analogue

Input Signal Path” for details of the MICBIAS generators.

In Regulator mode, the MICBIAS regulators are designed to operate without external decoupling capacitors. It is important that parasitic capacitances on the MICBIAS1 or MICBIAS2 pins do not exceed the specified limit in Regulator mode (see “Electrical Characteristics”).

If the capacitive load on MICBIAS1 or MICBIAS2 exceeds the specified limit (eg. due to a decoupling capacitor or long PCB trace), then the respective generator must be configured in Bypass mode.

The maximum output current is noted in the “Electrical Characteristics”. This limit must be observed on each MICBIAS output, especially if more than one microphone is connected to a single MICBIAS pin. Note that the maximum output current differs between Regulator mode and Bypass mode. The

MICBIAS output voltage can be adjusted using register control in Regulator mode. w PP, August 2012, Rev 3.4

365

WM8958

Pre-Production

EXTERNAL ACCESSORY DETECTION COMPONENTS

The accessory detection circuit measures the impedance of an external load connected to the

MICDET pin.

This function uses the MICBIAS2 output as a reference, as shown in Figure 88. Note that the

WM8958 will automatically enable MICBIAS2 when required in order to perform the detection function.

The WM8958 can detect the presence of a typical microphone and up to 7 push-buttons, using the components shown. When the microphone detection circuit is enabled, then each of the push-buttons shown will cause a different bit within the MICD_LVL register to be set.

The microphone detect function is specifically designed to detect a video accessory (typical 75 ) load if required. A measured external impedance of 75  will cause the MICD_LVL [4] bit to be set.

Figure 88 External Accessory Detect Connection w PP, August 2012, Rev 3.4

366

Pre-Production

WM8958

CLASS D SPEAKER CONNECTIONS

The WM8958 incorporates two Class D/AB speaker drivers. By default, the speaker drivers operate in

Class D mode, which offers high amplifier efficiency at large signal levels. As the Class D output is a pulse width modulated signal, the choice of speakers and tracking of signals is critical for ensuring good performance and reducing EMI in this mode.

The efficiency of the speaker drivers is affected by the series resistance between the WM8958 and the speaker (e.g. PCB track loss and inductor ESR) as shown in Figure 89. This resistance should be as low as possible to maximise efficiency.

Figure 89 Speaker Connection Losses

The Class D output requires external filtering in order to recreate the audio signal. This may be implemented using a 2 nd order LC or 1 st order RC filter, or else may be achieved by using a loudspeaker whose internal inductance provides the required filter response. An LC or RC filter should be used if the loudspeaker characteristics are unknown or unsuitable, or if the length of the loudspeaker connection is likely to lead to EMI problems.

In applications where it is necessary to provide Class D filter components, a 2 nd order LC filter is the recommended solution as it provides more attenuation at higher frequencies and minimises power dissipated in the filter when compared to a first order RC filter (lower ESR). This maximises both rejection of unwanted switching frequencies and overall speaker efficiency. A suitable implementation is illustrated in Figure 90. w

Figure 90 Class D Output Filter Components


367

WM8958

Pre-Production

A simple equivalent circuit of a loudspeaker consists of a serially connected resistor and inductor, as shown in Figure 91. This circuit provides a low pass filter for the speaker output. If the loudspeaker characteristics are suitable, then the loudspeaker itself can be used in place of the filter components described earlier. This is known as ‘filterless’ operation.

Figure 91 Speaker Equivalent Circuit for Filterless Operation

For filterless Class D operation, it is important to ensure that a speaker with suitable inductance is chosen. For example, if we know the speaker impedance is 8Ω and the desired cut-off frequency is

20kHz, then the optimum speaker inductance may be calculated as:

8  loudspeakers typically have an inductance in the range 20H to 100H, however, it should be noted that a loudspeaker inductance will not be constant across the relevant frequencies for Class D operation (up to and beyond the Class D switching frequency). Care should be taken to ensure that the cut-off frequency of the loudspeaker’s filtering is low enough to suppress the high frequency energy of the Class D switching and, in so doing, to prevent speaker damage. The Class D outputs of the WM8958 operate at much higher frequencies than is recommended for most speakers and it must be ensured that the cut-off frequency is low enough to protect the speaker.

RECOMMENDED EXTERNAL COMPONENTS DIAGRAM

Figure 92 provides a summary of recommended external components for WM8958. Note that this diagram does not include any components that are specific to the end application e.g. it does not include filtering on the speaker outputs (assume filterless class D operation), RF decoupling, or RF filtering for pins which connect to the external world i.e. headphone or speaker outputs. w PP, August 2012, Rev 3.4

368

Pre-Production

WM8958

Figure 92 Recommended External Components Diagram w PP, August 2012, Rev 3.4

369

WM8958

Pre-Production

DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS

The WM8958 provides 3 digital audio interfaces and supports many different clocking configurations.

The asynchronous sample rate converter enables more than one digital audio interface to be supported simultaneously, even when there is no synchronisation between these interfaces. In a typical application, this enables audio mixing between a multimedia applications processor and a baseband voice call processor, for example.

The AIF1 and AIF2 audio interfaces can be configured in Master or Slave modes, and can also support defined combinations of mixed sample rates. In all applications, it is important that the system clocking configuration is correctly designed. Incorrect clock configurations will lead to audible clicks arising from dropped or repeated audio samples; this is caused by the inherent tolerances of multiple asynchronous system clocks.

To ensure reliable clocking of the audio interface functions, it is a requirement that, for each audio interface, the external interface clocks (eg. BCLK, LRCLK) are derived from the same clock source as the respective AIF clock (AIFnCLK).

In AIF Master mode, the external BCLK and LRCLK signals are generated by the WM8958 and synchronisation of these signals with AIFnCLK is guaranteed. In this case, clocking of the AIF is derived from the MCLK1 or MCLK2 inputs, either directly or via one of the Frequency Locked Loop

(FLL) circuits.

In AIF Slave mode, the external BCLK and LRCLK signals are generated by another device, as inputs to the WM8958. In this case, it must be ensured that the respective AIF clock is generated from a source that is synchronised to the external BCLK and LRCLK inputs. In a typical Slave mode application, the BCLK input is selected as the clock reference, using the FLL to perform frequency shifting. It is also possible to use the MCLK1 or MCLK2 inputs, but only if the selected clock is synchronised externally to the BCLK and LRCLK inputs.

The valid AIF clocking configurations are listed in Table 157 for AIF Master and AIF Slave modes.

AUDIO INTERFACE MODE

AIF Master Mode

AIF Slave Mode

CLOCKING CONFIGURATION

AIFnCLK_SRC selects FLL1 or FLL2 as AIFnCLK source;

FLLn_REFCLK_SRC selects MCLK1 or MCLK2 as FLLn source.

AIFnCLK_SRC selects MCLK1 or MCLK2 as AIFnCLK source.


FLLn_REFCLK_SRC selects BCLKn as FLLn source.

AIFnCLK_SRC selects MCLK1 or MCLK2 as AIFnCLK source, provided MCLK is externally synchronised to the BCLKn input.


FLLn_REFCLK_SRC selects MCLK1 or MCLK2 as FLLn source, provided MCLK is externally synchronised to the BCLKn input.

Table 157 Audio Interface Clocking Confgurations

In each case, the AIFnCLK frequency must be a valid ratio to the LRCLKn frequency; the supported clocking ratios are defined by the AIFnCLK_RATE register.

The valid AIF clocking configurations are illustrated in Figure 93 to Figure 97 below. Note that, where

MCLK1 is illustrated as the clock source, it is equally possible to select MCLK2 as the clock source.

Similarly, in cases where FLL1 is illustrated, it is equally possible to select the FLL2. w PP, August 2012, Rev 3.4

370

Pre-Production

WM8958

Figure 93 AIF Master Mode, using MCLK as reference

WM8958

FLL1_REFCLK_SRC

FLL1

AIFnCLK

AIFn

(Master Mode)

AIFnCLK_SRC

BCLKn

LRCLKn

DACDATn

ADCDATn

Processor

Oscillator

Figure 94 AIF Master Mode, using MCLK and FLL as reference

WM8958

FLL1_REFCLK_SRC

FLL1

AIFnCLK_SRC

AIFnCLK

AIFn

(Slave Mode)

Figure 95 AIF Slave Mode, using BCLK and FLL as reference

BCLKn

LRCLKn

DACDATn

ADCDATn

Processor w PP, August 2012, Rev 3.4

371

WM8958

Pre-Production

Figure 96 AIF Slave Mode, using MCLK as reference

Figure 97 AIF Slave Mode, using MCLK and FLL as reference w PP, August 2012, Rev 3.4

372

Pre-Production

WM8958

PCB LAYOUT CONSIDERATIONS

Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce and resistive voltage losses. All external components should be placed as close to the WM8958 device as possible, with current loop areas kept as small as possible. Specific factors relating to

Class D loudspeaker connection are detailed below.

CLASS D LOUDSPEAKER CONNECTION

Long, exposed PCB tracks or connection wires will emit EMI. The distance between the WM8958 and the loudspeaker should therefore be kept as short as possible. Where speakers are connected to the

PCB via a cable form, it is recommended that a shielded twisted pair cable is used. The shield should be connected to the main system, with care taken to ensure ground loops are avoided.

Further reduction in EMI can be achieved using PCB ground (or VDD) planes and also by using passive LC components to filter the Class D switching waveform. When passive filtering is used, low

ESR components should be chosen in order to minimise the series resistance between the WM8958 and the speaker, maximising the power efficiency.

LC passive filtering will usually be effective at reducing EMI at frequencies up to around 30MHz. To reduce emissions at higher frequencies, ferrite beads can also be used. These should be positioned as close to the device as possible.

These techniques for EMI reduction are illustrated in Figure 98.

SPKP

SPKN

EMI

Long, exposed tracks emit EMI

SPKP

SPKN Short connection wires will reduce EMI emission

SPKP

SPKN

Shielding using PCB ground (or VDD) planes will reduce EMI emission

SPKP

LOW ESR

SPKN

LOW ESR

LC filtering will reduce EMI emission up to around 30MHz

SPKP

SPKN w

Figure 98 EMI Reduction Techniques

Ferrite beads will reduce EMI emission at frequencies above 30MHz.


373

WM8958

PACKAGE DIMENSIONS

Pre-Production

B: 72 BALL W-CSP PACKAGE 4.516 X 4.258 X 0.698 mm BODY, 0.50 mm BALL PITCH

DETAIL 1 g A2

2

A

9 8 7 6 5 4 3 2 1

A

B

C

4

A1

CORNER

D

E

F

G e

5

E1

H

DETAIL 2 e ddd

M

Z A B

D1

BOTTOM VIEW

2 X

2 X aaa B aaa A f1

6

D

TOP VIEW

SOLDER BALL

DM119.A

A

E

B bbb Z h f2

1

Z ccc Z

A1

DETAIL 2

Symbols

E

E1 e f1

A

A1

A2

D

D1 f2

MIN

0.658

0.206

0.418

4.491

4.233

0.246

0.367

Dimensions (mm)

NOM

0.698

0.242

0.434

4.516

4.00 BSC

4.258

3.50 BSC

0.50 BSC

MAX

0.738

0.278

0.450

4.541

4.283

NOTE

5

8

9 g h aaa

0.264

0.022

0.314

0.025

0.060

0.364

bbb ccc ddd

0.030

0.015

NOTES:

1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING.

3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE.

4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.

5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH.

6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C.

8. f1 = NOMINAL DISTANCE OF BALL CENTRE TO DIE EDGE X AXIS (AS PER POD) – APPLICABLE TO ALL CORNERS OF DIE.

9. f2 = NOMINAL DISTANCE OF DIE CENTRE TO DIE EDGE IN Y AXIS (AS PER POD) – APPLICABLE TO ALL CORNERS OF DIE.


374

Pre-Production

WM8958

IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.

Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.

ADDRESS:

Wolfson Microelectronics plc

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: [email protected]


375

WM8958

Pre-Production

REVISION HISTORY

DATE REV

16/11/10 2.2

4/1/11

24/1/11

2.2

2.2

28/1/11 2.2

24/03/11 3.0

DESCRIPTION OF CHANGES

DRC Signal Detect registers DRC_SIG_DET_RMS, DRC_SIG_DET_PK and

DRC_SIG_DET_MODE updated.

Additional details provided on pull-up / pull-down functions.

Added notes that DRC and MBC must not be enabled simultaneously on the same playback path.

Added notes that the Output Path HPF should be enabled when DRC is used on a record (ADC) path.

Power domains and Ground references listed for each input/output.

MICD_BIAS_STARTTIME and MICD_RATE descriptions updated, and associated text / recommended settings.

Noted that DRC Anti-Clip and Quick Release features should not be used at the same time.

VMID soft-start descriptions updated, including requirement to reset soft-start circuit before re-enabling VMID.

Speaker driver performance graphs added.

SPKAB_REF_SEL added to ‘Registers By Address’ section.

Added note that LDOs are not suitable for external loads.

Noted RF suppression on analogue inputs.

Noise Gate function defined for AIF1 and AIF2 input paths.

DAC Volume registers updated to support values up to +12dB.

EQ Band 1 now configurable as Shelf or Peak filter.

DSP2CLK_SRC register deleted.

MBC Control sequences updated.

EFS modes described for FLL1 and FLL2.

Decoupling capacitor removed from DMIC connection drawing.

Additional register writes added to the MBC enable sequence.

Pin description list re-sorted by Name, in order to draw attention to any multiple pins with a common name.

Updates noting that Ultrasonic (4FS) mode uses ADCLRCLK (not LRCLK).

GPIO1/GPIO6 must be configured for AIF1/AIF2 respectively.

Input Path drawing updated, showing VMID as PGA reference.

Accessory detection / impedance sensing added to Introduction section and on front page.

Updated electrical characteristics to reflect 4 ohm mono mode THD performance.

Restriction on MICBIAS capacitance clarified - 50pF limit is only applicable in Normal

(regulator) mode.

Applications Information (MICBIAS) enhanced to incorporate Digital Microphone connections.

Interrupts section updated to improve clarity.

Corrections to the FLL Example settings

LDO2 output voltage updated (1.1V to 1.3V)

Updated speaker inductive load conditions in electrical characteristics to 22uH.

Updated LDO2 output voltage in electrical characteristics.

Added max/min limits to electrical characteristics.

CHANGED BY

PH

PH

PH

KOL

KOL w PP, August 2012, Rev 3.4

376

Pre-Production

DATE REV

14/02/11 3.0

04/04/11 3.1

18/05/11 3.3

24/11/11 3.3

03/01/12 3.3

25/05/12 3.4

WM8958

DESCRIPTION OF CHANGES

Updated speaker inductive load in electrical characteristics to 22uH.

Updated LDO2 output voltage in electrical characteristics.

Notes added requiring VMID_BUF_ENA is enabled for direct signal paths from input pins to Input Mixers, Output Mixers or Speaker Mixers. Descriptions of affected register bits updated.

Reel order quantity updated

MICBIAS modes clarified as “Regulator” mode and “Bypass” mode.

Ultrasonic (4FS) mode deleted on AIF2.

External Accessory Detect description & characteristics updated; Recommended

External Components added in Applications Information section.

Block diagram updated (input digital mixing paths and MICBIAS references)

Updated ADC Path characteristics - input is -1dBV, not -1dBFS.

Clarification of DAC_OSR128 modes in DAC playback path Electrical Characteristics.

Input PGA Mute behaviour description updated.

Noted that HPF is required when using DRC Signal Activity Detect.

Updates to FLL Input Frequency range.

Minimum headphone load resistance updated.

Clarifications and formatting updates to Electrical Characteristics and Recommended

Operating Conditions.

Noted phase inversion in ‘Direct Voice’ paths.

Clarification to the usage of the INPUTS_CLAMP register.

PSRR specifications added for LDO1 and LDO2.

Drop-out voltage specification added for LDO1.

RMS Limiter function added within the MBC description.

TSHUT_ENA default corrected in Power Management section (default is 1).

Absolute Maximum Ratings updated: (AVDD1 domain) added to Voltage range analogue inputs.

Maximum MICBIASn load capacitance noted in Electrical Characteristics.

Specifications added for LINEOUTFB and HPOUT1FB ground noise rejection.

System clocking updated - DBCLK is derived independently of TOCLK_ENA.

Additional details in Absolute Maximum Ratings.

Clarification of Line Output discharge functions and associated Electrical

Characteristics.

Package diagram changed to DM119.A

CHANGED BY

PH

PH

PH

PH

JMacD w PP, August 2012, Rev 3.4

377

WM8958 Product Datasheet

Multi-Channel Audio Hub CODEC for Smartphones

Related manuals

Table of contents

WM8958 Product Datasheet

Multi-Channel Audio Hub CODEC for Smartphones

Related manuals

Cirrus Logic

WM8958

Cirrus Logic

WM8994

Cirrus Logic

WM8281

Cirrus Logic

CS47L85

Cirrus Logic

WM8998

Cirrus Logic

CS47L90

Table of contents