special edition of IEEE Solid-State Circuits Magazine

special edition of IEEE Solid-State Circuits Magazine
FALL 2012
VOL. 4 • NO. 4
www.ieee.org/sscs-news
features
8
INTRODUCTION TO
SYSTEMS
CARVER MEAD • LYNN CONWAY
Reminiscences of the VLSI Revolution
How a series of failures triggered
a paradigm shift in digital design.
By Lynn Conway
32 A Paradigm Shift Was
Happening All Around Us
By Chuck House
36
Witnessing the Birth of VLSI Design
40
“Covering”
By Carlo H. Séquin
How we missed the inside-story
of the VLSI revolution.
By Ken Shepard
tutorial
43
On the Other Applications
of Organic Electronics on Foil
By Hagen Marien, Michel S.J. Steyaert,
Erik van Veenendaal, and Paul L. Heremans
about this image:
This book helped start a revolution; read
all about it starting on p. 8.
columns/
departments
3Contributors
4 Editor’s Note
5 President’s Corner
6 associate editor’s view
50people
54Chapters
61 society News
62IEEE news
64 Conference Reports
71Conference Calendar
CVR 3footer
Digital Object Identifier 10.1109/MSSC.2012.2214274
IEEE SOLID-STATE CIRCUITS MAGAZINE
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IEEE solid-state
circuits magazine
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Digital Object Identifier 10.1109/MSSC.2012.2214275
about the cover:
Lynn Conway conceived of and became the
principal author of the famous Mead-Conway
text, thereby launching a worldwide revolution
in VLSI system design in the late 1970s.
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IEEE SOLID-STATE CIRCUITS MAGAZINE
Contributors
Lynn Conway in­vented scalable MOS
design rules and
highly
simplified
methods for ­silicon
chip design, conceived of and became the principal
author of the famous Mead-Conway
text, and pioneered the intensive
course at MIT that taught these
methods, thereby launching a
worldwide revolution in VLSI system
design in the late 1970s.
Chuck House was
most recently chancellor of Cogswell
College, Sunnyvale,
California, and executive director of
Media X @ Stanford University after
a long career at Hewlett-Packard
and Intel.
Digital Object Identifier 10.1109/MSSC.2012.2215750
Date of publication: 24 December 2012
Carlo H. Séquin
is a professor of
computer
science
at the University of
California, Berkeley.
After working with
integrated circuits for two decades,
he now works on three-dimensional
designs, ranging from architectural
building models to abstract geometrical sculptures.
Ken Shepard has
been influenced by
Lynn Conway’s work
for more than 25
years. He is a professor of electrical
engineering at Columbia University.
Marien
Hagen
was a research assistant in the ESATMICAS
Laboratory
of the Katholieke
Universiteit Leuven.
After finishing his Ph.D., he joined
the design house AnSem as a senior
design engineer.
Michel S.J. Stey­
aert is a full professor at the Katholieke
Universiteit Leuven
and chair of the
Electrical Engineering Department.
Erik van Veenen­
daal is a principal
scientist at Polymer
Vision BV.
Paul L. Heremans
is an imec fellow,
director of imec’s
Large Area Electronics Department, and
part-time
professor in the Electrical
Engineering Department of the University of Leuven.
IEEE SOLID-STATE CIRCUITS MAGAZINE
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3
editor’s note
Mary Lanzerotti
Welcome to the Fall 2012 Issue
of IEEE Solid-State Circuits Magazine!
T
This Fall 2012 issue marks the fourth
issue of the fourth year of IEEE SolidState Circuits Magazine. In this issue,
we are fortunate to feature Lynn Conway, professor of Electrical Engineering and Computer Science Emerita at
the University of Michigan. This special issue is titled “Lynn Conway: VLSI
Reminiscences.” We are delighted to
be able to present the achievements
in this special issue in honor of Prof.
Conway.
In this issue, we present Prof.
Conway’s feature article, “Reminiscences of the VLSI Revolution:
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Date of publication: 24 December 2012
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How a Series of Failures Triggered
a Paradigm Shift in Digital Design,”
and three expert articles in honor
of Prof. Conway that describe the
impact of her research:
■■ Chuck House, “A Paradigm Shift
Was Happening All Around Us”
■■ Carlo Séquin, “Witnessing the Birth
of VLSI Design”
■■ Kenneth
Shepard, “‘Covering’:
How We Missed the Inside-Story
of the VLSI Revolution.”
We are very fortunate for the support of our Executive Director Michael
Kelly, who joined the IEEE Solid-State
Circuits Society in April 2012, and for
our Tutorials Editor Willy Sansen and
Technology Editor Jake Baker. We are
IEEE SOLID-STATE CIRCUITS MAGAZINE
grateful for the work of our continuing
News Editor Katherine Olstein and for
the columns of PengFei Zhang, associate editor of Asia, and Tom Lee, contributing editor.
The goal of each issue of IEEE SolidState Circuits Magazine continues to
be to create a series of self-contained
resources, with original sources and
new contributions by experts describing the current state of affairs in technology in view of the influence of the
original papers and/or patents.
Thank you very much for reading
IEEE Solid-State Circuits Magazine.
Please send comments and “Letters
to the Editor” to [email protected]
post.harvard.edu.
By Lynn Conway
Reminiscences of
the VLSI Revolution:
How a series of failures triggered
a paradigm shift in digital design
Preface
I
nnovations in science and engineering
have excited me for a lifetime, as they
have for many friends and colleagues.
Unfortunately, our wider culture often
imagines the engineering life to be one of
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Date of publication: 24 December 2012
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IEEE SOLID-STATE CIRCUITS MAGAZINE
tedium and technical drudgery, seldom witnessing the
joys of such creativity.
If only I could wave a wand, I’ve often wished, and
say “YOU CAN DO IT” to inspire young folks to dedicate
their lives to such adventures. But then various friends
asked me to write about my own career – a tale wherein
travails, setbacks, dark days and obscurity at times
seemed the theme – and I wondered who’d be inspired
1943-0582/12/$31.00©2012IEEE
by such a journey, so often apparently lonely, difficult
and discouraging?
However, after deeper contemplation and review, I
realized that each setback in my story, each hardship,
actually strengthened my skills, my perspectives, and
my resolve. And when colleagues began reading the
early drafts, they reacted similarly: “Wow, this is really
something!” The story was authentic, real – maybe even
surreal – and it actually happened.
The child who once dreamed of “making a difference,”
indeed made a difference after all. And with that, I’d like
to inspire YOU to imagine how you too can positively
impact our world. Be assured, it won’t be easy, and fame
may never come your way, but the satisfaction gained
from a life of creative work will be immense. Trust me
on this!
Childhood Fascinations
© 2012, Lynn Conway. All Rights Reserved.
I loved listening to the radio
as a child during WWII, especially to BBC broadcasts from
London. Thrilled by hearing
people speak from far away,
I wondered how this mysterious machine worked, with all
the glowing tubes and strangelooking parts inside.
My father was a chemical
engineer, and he gave me The
Wonder Book of Knowledge as
one of my first ‘big books.’
From it I learned not only how
to read, but also how electricity was tamed and radios were
created, and that engineers did
these things.
Becoming fascinated by
astronomy, math, physics and
electronics, and encouraged to
build things that worked, I was
channeled to become an engineer. Among my heroes were
Charles Steinmetz and Edwin
Armstrong; I knew their stories well and dreamed of doing
such things.
Steinmetz pioneered methods for calculating alternating
current phenomena using complex numbers, complex
exponentials and vector diagrams, simplifying a highly
arcane field. His books and passionate teaching launched
the AC revolution, and his story carried an embedded
message: Someone who faced physical challenges (he
was afflicted with hunchback and hip dysplasia) or who
was somehow perceived as different might become liked,
even honored, if they made valuable contributions.
Edwin Armstrong pioneered the regenerative and
super-regenerative circuits, the super-heterodyne radio
receiver and FM radio. His visionary inventions involved
elegant arrangements of simple electronic components,
and helped launch a revolution in radio.
Time and Place Are Everything
Just as Steinmetz had with electrification and Armstrong
with wireless communication, I found myself a student
at the beginning of a technological revolution: digital
computing in the early 1960s. And, I was at the right
place: Columbia University’s School of Engineering and
Applied Science, with its close ties to IBM, then a leading
force in the emerging industry.
Along with delving into every relevant course
in math, physics, electrical engineering, and computing, I also did an independent study there with
Dr. Herb Schorr, just prior to his joining IBM. I must have
made a good impression, for I was quickly recruited
by IBM Research and in 1965 found myself at the T. J.
Watson Research Center at Yorktown Heights, working on a highly proprietary and secretive supercomputer project, a project unknown even to many within
the company.
The Advanced Computing Systems (ACS) project had
been personally launched by IBM’s then-CEO Thomas.
J. Watson, Jr., and given the mission to “go for broke”
to create the most powerful scientific computer in the
world. Staffed with pre-eminent IBM computing experts
of the time including the legendary John Cocke, the
project soon moved to what would become Silicon Valley
[1], [2].
Herb Schorr led ACS’s architecture department, where
I worked on an architectural simulation model of the
evolving hardware design. The initial design for the
ACS-1 exploited cache memory, instruction pre-fetch,
multiple pipelined functional units, and an innovative
instruction set and branch hardware for anticipating
and minimizing branch disruptions in instruction flow.
There was a bottleneck in instruction issuance, however,
and functional units often stood idle as stalled instructions awaited results.
Gene Amdahl, already famous inside IBM for his work
on System 360, along with other prominent computer
architects of the day, presumed that no single-stream
architecture could be found that issued, on average,
more than one instruction per machine cycle [3]. Cocke
questioned this presumption, but no way had been found
around the bottleneck – as yet.
Unaware that this was an open research question,
I took it on as a design challenge and obsessed on it for
over a month. I explored varying ways to represent and
issue instructions, mentally juggling all aspects of the
problem simultaneously – everything from mathematical
abstractions, to architectural structures, to circuit-level
implementations, but to no avail.
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Source Matrix
Cycle (n):
1 2 3 4 5 6 7 8
R3 + R4
R7
R7 * R2
R4
1
R1 + R2
R5
1 1
R8 ' R1
R8
1
Cycle (n+1):
1 1
1
1
R7
R7 * R2
R4
R6 - R3
R3
71, R1; R2 = 0
1
1
1
1 2 3 4 5 6 7 8
1
1
1
1
1
1
1
Destination Matrix
1 2 3 4 5 6 7 8 # ' !
1
1
1
1
1 1
1
Busy Vector Branch
1 2 3 4 5 6 7 8 # ' !
1
1
Source Matrix
R3 + R4
Destination Matrix
1 2 3 4 5 6 7 8 # ' !
1
Busy Vector Branch
1 2 3 4 5 6 7 8 # '
1
1 1
1
1
1
1
1
1 1
FIGURE 1: DIS functional diagrams, showing multiple out-of-order issuance of instructions per machine cycle.
My First Invention
In the fall of 1965, however, it suddenly beamed down to me: By holding pending instructions in a queue,
and representing source and destination registers and functional
units in unary positional form
rather than in binary, I determined
that it would be possible to scan
the queue, resolve dependencies,
and issue multiple instructions outof-order (OOO), even when various
entries were stalled [3].
The scheme involved not only
mathematical and micro-architectural ideas, but also tricks at the
logic and circuit levels, using arrays
of ACS high-speed emitter-coupled
logic (ECL) integrated circuits and
exploiting their ‘wired-OR’ connections to scan queue-columns within
machine cycle-time constraints. An
ACS colleague at the time, Brian Randell, coined a perfect name for the
scheme, Dynamic Instruction Scheduling (DIS). It was quickly incorporated into the ACS-1 design [3],
[4], [5].
DIS provides a sort of ‘turbocharger’ for pushing more instructions through a processor during
each machine cycle than would otherwise be possible. Although huge
regular arrays of ECL circuits were
required to implement that ‘turbocharger’ for the ACS-1 (a moderate
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fraction of the main processor’s
total circuitry), the scheme proved
simple and elegant in both function
and structure, and more than doubled the machine’s performance.
This was a personal Edwin Armstrong moment for me. I now knew
what it felt like to invent something
cool. In fact, DIS proved to be a
fundamental advance in computer
architecture and by a circuitous
route has since become a standard
fixture in modern high-performance
microprocessors.
Lessons Learned
One might ask how could a shy,
naïve, freshly-minted MSEE be the
one to invent multiple-OOO DIS? The
problem had been clear to others;
why hadn’t they found a solution?
The belief that it couldn’t be done
undoubtedly held back progress,
while ethnographic observations
reveal further problems: By the
mid-1960s, chasms had developed
between the various specialized
groups working on computer architecture, logic design, circuit design,
and packaging – with each specialty
optimizing their work at a particular
level of abstraction, and then tossing it over the wall to the next.
As a result, most computer architects lacked knowledge about the
rapidly advancing ECL integrated
IEEE SOLID-STATE CIRCUITS MAGAZINE
circuitry, and couldn’t envision
how to reach down into and more
fully exploit it. Nor could expert
ECL circuit designers provide architects with the necessary circuit
level hooks to resolve intractable
computer architecture problems. DIS
revealed that only a rethinking of the
basics across all levels of abstraction
could break the logjam – a lesson
that deeply affected my later work in
VLSI [3].
Another problem inhibiting progress was the complexity of the ACS-1’s
design. I realized that a rigorous overall system design methodology was
required – based on a coordinated,
hierarchical, multi-level computer
simulation of formalized design partitions – for there to be any hope of
collective group activity to generate
the sequences of internal subsysteminterface test patterns for debugging,
bringing up and maintaining such a
complex machine.
These realizations, along with
many insights into interpersonal
team behavior that I had gained
from the then-recent ethnomethological work of Harold Garfinkel,
led me to design and propose a formalized design of the ACS design
process, a proposal which was wellreceived and also strongly impacted
my later thinking on VLSI design
methods [3], [5], [6], [7].
My First Failed Project
In hindsight, it is now recognized
that had the ACS-1 been built, it
would likely have been the premier
supercomputer of the era, eclipsing both the CDC 7600 and the IBM
Model 91 [1]. But, that was not to be.
Instead, in 1968 Gene Amdahl
proposed that the ACS-1 be replaced
with a S360-compatible supercomputer, and the ACS project fell victim
to the ensuing political confrontation. Declared “a failure” by IBM
executive B. O. Evans, the ACS project was disbanded [8]. Apparently,
neither Amdahl nor Evans nor other
key IBM people had a clue about
the novel DIS architectural innovations that had been made within the
secretive project; the invention was
shelved away and apparently lost in
dusty technical reports.
Fired by IBM
At that same time in 1968, I was pioneering along another path, as well.
I alerted HR at IBM that I was undertaking a gender transition to resolve
a terrible existential situation I had
faced since childhood. I was hoping to quietly maintain employment
during that difficult period. However, the news escalated to IBM’s
Corporate Executive Committee
(including CEO T.J. Watson, Jr.), and
I was summarily fired [3].
Finding myself unemployed and
in the midst of transition, I watched
my contributions to ACS go down
the tubes as the failed project
simultaneously imploded. I grieved
over this misfortune, but there was
nothing I could do about it. And not
surprisingly, given ACS-1’s stained
image within IBM, little curiosity
ever arose at the company about
what developments had occurred
there. The DIS concepts eventually
leaked out, however, and began
propagating through the architecture community, the full story only
beginning to emerge in recent years.
Starting All Over Again
I completed my transition and started
my career all over again in early 1969,
remaining right in the Bay Area. A
gritty survivor, I began at the bottom
of the ladder as a contract programmer, with a new identity that allowed
me to work in “stealth mode”. Nonetheless, it was a terrifying time. Any
public outing would have killed my
new career and I could have ended up
unemployed, a social outcast, living
on the streets.
Fortunately, after a series of
rapid upward moves I was hired as
a systems programmer at Memorex
Corporation. On joining Memorex,
I described the general nature of
my computer design work at IBM to
the HR department. When Memorex
entered the computer business I was
given responsibility for CPU architecture and design for the Memorex
30 System (MRX30), an entry-level
competitor to IBM’s System 3. It was
now mid-1971.
Creating a TTL micro-programmed
minicomputer from a blank sheet of
paper, under tight time and cost constraints, was a tremendous hands-on
experience. I loved the intense teamwork and gained confidence as an
enthusiastic thought leader on the
project. Using methods I’d developed
at ACS, I quickly built a register transfer level simulator to coordinate the
overall design effort. When first powered up in early 1972, the ‘Memorex
7100’ processor (the MRX30 manufacturing prototype, shown in Figure 2)
came up smoothly and ran code with
just two minor wiring errors. It was
a triumph.
Explosive News
Then in November 1971, Intel
announced the 4004 microprocessor, followed by the 8008 in
April 1972. These were blockbuster
events for digital system designers
and seriously grabbed my attention.
I attended several intensive short
courses to learn about the chips.
They proved architecturally simple
and easy to use.
Detailed knowledge about the
underlying MOS (metal-oxide-semiconductor) digital circuitry about
which I was so curious, however,
FIGURE 2: The Memorex 7100.
was still inaccessible outside Intel
(except for knowledge about the rapidly emerging application of MOSFET’s in dynamic memories [9]). Did
architects have to understand MOS
circuits and devices to design such
microprocessor chips? Did folks
outside semiconductor houses have
futures in computer architecture?
The future of digital design
seemed to be in MOS, but I had no
clue how to get into it.
My Second Failed Project
Just as we completed the MRX30
manufacturing prototype, Memorex
left the computer business – a victim
of monopolistic pricing moves by
IBM. I was crushed and no longer
saw a future there. Not only had IBM
fired me, it was now stamping out
many competitors that I might possibly work for!
Nonetheless, in late 1972 I asked
my headhunter to open a job search
and received two excellent offers: to
be the architect of Fairchild Semiconductor’s next microprocessor or
to join Xerox at the new Palo Alto
Research Center (PARC).
The Fairchild opening seemed a
great opportunity, but I felt uneasy.
Knowing nothing about MOS circuitry, I hesitated at the prospect of
merely blocking out simple architectures that others would implement.
I also had doubts about fitting into
the semiconductor industry, with its
famously macho disdain of women.
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Xerox was different, however.
A movement was underway there
that promised to revolutionize computing by creating a new world of
interactive personal computers and
related storage devices, scanners,
copiers, laser-printers and network
communications. PARC was recruiting the best and brightest young
talent from across the U.S. to join
the effort, including a number of
women scientists. A diverse and
eclectic group, I’d heard of many of
the ‘names’ already working there. I
took the job at PARC in 1973.
My project was a tough one: create a compound OCR/FAX system
that compressed office documents
for efficient communication. It took
two years of work on characterrecognition algorithms, as well as
the architecture, logic design, and
packaging of a novel image processing system, to create the TTL prototype. The Xerox Sierra filled a full
rack of circuit boards, and there was
no way to then reduce it to a few LSI
chips. It was clearly doomed.
My Third Failed Project
The end came in 1975 when William
R. (Bert) Sutherland joined PARC as
manager of the Systems Sciences
Lab (SSL). Bert had led the Computer
Science Division at Bolt, Beranek
and Newman (BBN) and knew where
he wanted his new lab to focus. He
began vetting staff and projects,
bringing in Wesley (Wes) Clark of
LINC fame to advise him.
By then I had told Bert in confidence about my IBM work, and in
an intense follow-on interview, I
presented the details of Sierra and
my ACS-1 innovations to both Wes
and Bert. Afterwards, Wes told Bert,
“This is the real thing!”
I was able to keep my job, but
Sierra had to go. I was severely disheartened over yet another failed
project. There was no way to know
at the time, of course, that all of
those failed projects had prepared
and positioned me to launch a revolution in what would become known
as ‘VLSI design’.
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Concurrent Events at Fairchild,
Intel, IBM and Caltech
In 1970, Carver Mead at Caltech
had coined the term “Moore’s Law”
for Gordon Moore’s 1965 prediction
[10] that chip device counts would
double every two years. A specialist in device physics in addition to
his teaching duties at Caltech, Mead
became a high-level consultant at
Intel, gaining access to vital projects
and know-how there. Around this
same time Mead reportedly independently invented a metal-gate
PMOS circuit design for PLA-based
finite-state machines, realizing
that it would be easier to code
logic than to draw it [11].
In 1972, Bruce Hoeneisen and
Mead described MOS device scaling
principles in a widely read paper,
predicting that MOS field-effecttransistors (MOSFETs) would function properly at gate lengths as small
as 0.25 micron, far smaller than the
10 micron gates of the time [12].
Motivated by the possibilities of
scaling, Mead began teaching MOS
integrated circuit design courses at
Caltech, based on the dynamic-logic
design methods that were rapidly
evolving within several semiconductor firms to exploit the new
technology – from the early work
of Frank Wanlass at General Microelectronics, to that of Bob Booher at
Autonetics, to that of Lee Boysel and
his teams at Fairchild Semiconductor and then at Four Phase Systems,
to that of Federico Faggin and others at Intel on the Intel 4004, 8008
and other early microprocessors
[13], [14], [15], [16].
The latest Intel circuit design
methods well exploited the new
self-aligned silicon-gate fabrication
technology, a concept invented in
1966 by Bower and Dill at Hughes
Research [17] and by Kerwin, Klein,
and Sarace at Bell Labs, and first
commercialized by Faggin while
at Fairchild [16]. Bright Caltech
students studying these methods
under Mead’s guidance had no difficulty applying them to basic digital
circuit design.
IEEE SOLID-STATE CIRCUITS MAGAZINE
In 1974, IBM’s Robert Dennard,
inventor of the single transistor
DRAM, showed that when MOSFET
geometries, voltages and dopings
were scaled down, gate transit times
also scaled down and performance
thus improved by the same factor
[18]. Taken together, the density
improvements predicted by Moore’s
Law and the performance improvements predicted by Dennard signaled a coming explosive growth in
chip processing power.
Bert’s brother Ivan Sutherland
joined Caltech in 1974 as founding Chair of the new Computer Science Department there. Famous for
his pioneering work in computer
graphics, Ivan was excited about
the potential for microelectronics.
He recruited Mead to join his new
department, bringing in Mead’s
expertise in device physics and circuit design and his many connections in industry.
In ‘75 Ivan Sutherland, Carver
Mead and Tom Everhart (then
chair of EECS at U.C. Berkeley) conducted a major ARPA study of the
basic limitations of microelectronics fabrication. Their ARPA report
(published in ‘76) urgently recommended research into the system
design implications of “very-largescale integrated circuits” in light of
coming advances in scaling – pointing out that no methods existed for
coping with such complexity and
no approaches then underway held
promise of solutions [19].
Bert introduced me to Carver and
Ivan that fall, and I began studying
their recent work – having no idea
what adventures lay ahead. Ivan soon
wrote a letter to his brother Bert – a
letter that has since proven to be
historic – proposing that PARC and
Caltech work together to attack the
system complexity problem [20], [21].
The PARC/Caltech Collaboration
In early ‘76, the Sutherland brothers
formalized a collaborative research
project between Xerox PARC and
Caltech. The mission: to explore
ways to more easily create systems
in silicon, and apply the emerging
personal computing technology at
PARC to the task.
At Caltech, Ivan Sutherland asked
Carver Mead, and his students Jim
Rowson and Dave Johannsen, to
be part of the team. At PARC, Bert
asked two researchers to join the
team: one was Doug Fairbairn, a
brilliant young computer engineer
then designing Xerox’s NoteTaker,
the world’s first portable personal
computer. Bert’s other invitation
was to me.
Personally, I could hardly believe
this reversal in fortune! I was being
propelled into MOS-LSI, and was
confident my experiences at ACS
would give clues on how to proceed.
By now it was clear that commercially viable chips would inevitably
contain several million transistors
by the early 1990s. By scaling supply voltages and exploiting the coming CMOS technology, MOS circuits
would become as fast as ECL but with
far lower power dissipation. The
capabilities of an entire ACS-1 processor could eventually be ‘printed’
on a single chip, and personal computers like those emerging at PARC
were destined to have the power of
current-day supercomputers. It also
meant that my DIS invention would
inevitably come to life. These electrifying possibilities launched me
into hyperdrive.
Exploration Begins
Our work began with concentrated
studies, including taking a number
of short intensive courses on the
very latest relevant technologies
in Silicon Valley. And, while Mead
taught us about NMOS device physics, circuit design and fabrication
processes, I shared my knowledge
of computer architecture, and of
multiple-abstraction-level computerdesign-process design, with him.
We then waded in by building hands-on prototype chip subsystems, learning as we went
along. Fairbairn and Rowson created an interactive layout system called “ICARUS” on the Xerox
Alto computers, which we all used
to gain design experience. Mike
Tolle, Chris Carrol, Rod Masumoto,
Ivan Sutherland, Dave Johannsen
and Carver Mead worked on the
“OM” microprocessor data path at
Caltech, using symbolic layout software (ICL/ICLIC) by Ron Ayres. Ron
and Ivan crafted a graphical interchange format (Caltech Intermediate Form, CIF), to circumvent the n2
translation problem that arose when
converting each design tool’s output
to one of many mask specs.
Our tool building and design
work in that early period went well,
but chip prototyping proved difficult. We could obtain masks from
Silicon Valley mask makers of the
time, using reticle pattern-generator code produced by ICARUS. However, wafer fabrication was quite
another matter.
Engineers within semiconductor
firms could get small lots of prototype chips via regular fab runs
– either by stepping reticles of prototypes into a few die locations on
production masks, or by substituting masks containing multiple prototype designs as one particular
boatload of wafers transited the fab
line. However, it was nearly impossible for outsiders to access such
prototyping. Only ‘writers’ working
for the ‘printing plant’ could become
‘published’; i.e., only designers
working for the semiconductor firms
could get their chips manufactured.
Mead’s contacts occasionally provided access to MOS fab for Caltech
circuit designs, and he worked to
gain similar access for our PARC/
Caltech project. This involved extensive coordination during design and
mask-making in order to meet the
many requirements of the target fab
line. Each line had different layout
design rules, mask polarities, alignment marks, process test patterns,
scribe lines and more – with all of
that data communicated via detailed
paperwork unique to each company.
We sometimes obtained prototype
chips for our project this way. However it was a daunting activity, full
of easily-derailed arcane practices,
and turnaround times spanned
many months.
Even so, we made great progress in 1976 as we cranked up our
knowledge in MOS design and tool
building – although learning more
than we wished to know about
what can go wrong in prototype
implementation.
Meanwhile, Ivan Sutherland
prepared an article for Scientific
American about the challenge
microelectronics posed to computing theory and practice. Since most
of a chip’s surface was occupied
by ‘wires’ (conducting pathways
on the various levels) rather than
‘components’ (transistors), decades
of minimization theory in logic
design had become irrelevant. And
by co-mingling logic and memory
within regular lateral arrays of
small processing structures in silicon, it was possible to save both
time and energy in internal onchip communications.
The resulting article, co-authored
by Carver Mead, was a powerful
statement of the challenges we faced
as 1976 drew to a close [22]. The
bottom line: A huge and previouslyunknown territory for creative architectural innovation had opened up,
and as yet there were no theories or
methods to guide those explorations.
Simplification and Convergence
By late 1976, I sensed in our work
a parallel to Steinmetz’s time – a
time when DC technology was well
established but was running out of
steam – while the emerging AC concepts seemed mysterious, even to
expert practitioners, who as yet had
no formal theories to develop AC
technology.
Steinmetz had broken the logjam by coalescing mathematical
methods and design examples that
enabled practicing engineers to
routinely design AC electrical systems with predictable results. This
starter set of knowledge was sufficient to launch the AC revolution.
By applying Steinmetz’s principles,
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13
FIGURE 3: Lynn Conway at Xerox PARC in 1977.
practicing engineers spawned a
whole new industry.
Similarly, this seemed the right
way to attack the VLSI complexity problem. Instead of visualizing an ever more complex future
into which all current and evolving
developments were projected, why
not begin by simplifying, simplifying, simplifying? Would that not
spawn something starkly simple
and eminently practical instead?
This wasn’t about engineering
new things; it was about the engineering of new knowledge. My
key idea was to sidestep tons of
accumulated vestigial practices in
system architecture, logic design,
circuit design and circuit layout,
and replace them with a coherent but minimalist set of methods sufficient to do any digital
design – restructuring the levels of
abstraction themselves to be appropriate for MOS-LSI.
I theorized that if such a starter
set could be composed, it would
enable thousands of system designers to quickly migrate from TTL
into MOS-LSI – just as I had. Most of
what was needed was all around us,
including the latest Intel’s MOS-LSI
design lore. The challenge was to
make wise decisions about what to
keep, and what to toss.
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Structuring a Design Methodology
With this theory in mind, I convinced
Mead we should set a far more ambitious goal for the work. We should
move to create a simplified methodology for designing whole systems
in silicon, not just circuits – and aim
it specifically at computer architects
and system designers. He agreed,
and in an incredibly intense period
in the spring of 1977 we formulated
the basics of the new methods.
Happily, NMOS was perfect for this
simplification.
Seen from an architect’s perspective, an NMOS chip could be visualized as a miniature 3-layer printed
circuit board, with wires printed on
the metal (MET), polysilicon (POLY)
and diffusion (DIFF) levels, and with
vias (i.e., “contacts”) connecting wiring levels where needed. As a result
of the new self-aligned silicon-gate
fabrication process, a MOSFET transistor was formed (and easily conceptualized) wherever a path on the
POLY level crossed over a path on
the DIFF level.
But there was more. The resistance of wires was small compared to
on-transistors, while off-transistors
had extremely high resistance. Thus
an NMOS FET could be abstracted
as an almost perfect ‘bi-directional
switch’ with its control gate on POLY
IEEE SOLID-STATE CIRCUITS MAGAZINE
and switch contacts on DIFF. Additionally, wiring and stray capacitances were often modest compared
to gate capacitances. Thus turning a transistor on for a sufficient
time and then off could charge (or
discharge) the gate-capacitance of
a subsequent transistor and then
isolate it – dynamically storing the
on (or off) state as in a Dennard
dynamic RAM cell [18].
At the top level, architects composed digital systems as arrangements of interconnected registers
and intervening logic, with data
movement and logical sequencing
controlled by state machines. Registers could now be built in NMOS as
arrays of inverters, each composed
as a simple pull-up/pull-down transistor pair using depletion-mode
MOSFETs as loads. Data movement
between registers could be controlled by pass transistors, using
two-phase non-overlapping clocks to
isolate the dynamically stored data.
Clocking times could be calculated
as simple multiples of minimum
FET-gate delays. Logic functions
could be crafted using simple NMOS
structures placed between successive register stages. State-machines
could be built using NMOS programmable logic arrays (PLAs), with registers holding state to feedback to
inputs at successive machine cycles.
All this could be done using simple
rules of thumb for gate geometries,
pullup/pulldown ratios, fan-outs,
power distribution and timing.
By routing control lines perpendicular to data lines, important
subsystems could be woven as
regular arrays of cleverly designed
NMOS cells – resurrecting long-lost
non-gate-logic methods, as in symmetric networks of relay contact
switches, and elevating the bidirectional ‘switch’ as a basic level
of abstraction. We sketched cell
topologies as stick diagrams, using
blue, red and green pencils to indicate cell wiring on the MET, POLY
and DIFF levels – and wherever a
‘red wire’ crossed a ‘green wire’
an FET ‘switch’ was created. Cell
topologies were then geometrically
expanded to form cell layouts, compacted to the degree possible under
the target fab line design rules for
spacings and widths.
When implemented, such designs
often required far less area, time
and energy to perform functions
than those produced using traditional abstraction-levels and optimizations at each level – shattering
years of established academic theory and industry practice – and they
were often dramatically simpler
to design.
Layout design rules:
The Fly in the Ointment
The stick diagrams of cell topologies contained all information necessary for laying out functionally
unique cells. The layout design
rules merely said what was prohibited during the compaction of geometrically expanded cell topologies
towards minimal areas.
Unfortunately, MOS fabrication
engineers produced large books of
layout design rules unique to each
new process, often running 40 pages
or more. In efforts to increase
yields, layout designers valiantly
applied these rules, including those
enabling only tiny compactions,
often using arbitrary angles and
curvatures to scrunch on-chip features down in size. Just imagine the
complexity of the layouts, hand-cut
into rubylith patterns for maskmaking, that resulted from such efforts!
To ease the burden for students
in his earlier circuit-design classes,
Mead crafted ad-hoc rules having
reduced complexity by tossing lowreturn constraints and formulating
‘covering’ sets of rules – using linewidths, separations, extensions and
overlaps somewhat larger than the
minimums required for target processes. Such rules were easier to
teach, apply and check, and were far
better for prototype design where
extreme compaction was not needed.
However, such rule-crafting required
expertise, judgment and close coordination with fab lines. The resulting
layouts were also tied to particular
processes, and had to be redone as
new processes came online.
In contrast to our other successes,
circuit layout seemed an intractable
level of design abstraction. Questions of computational complexity also loomed: How could such
complex, rapidly changing geometric layout rules be encoded, applied,
and checked – given the increases
in circuit density anticipated in the
coming years?
Invention of Scalable Design Rules
In early 1977, I began asking myself:
What is the simplest possible set
of layout design rules? I found the
answer in a different question:
What is the maximum from among
the minimum lateral line widths,
separations, extensions and overlaps at all levels for a given process?
Once found, I knew this one measure of process resolution could be
used to limit minimum sizes for all
layout features.
The resulting, minimalist covering
rules were crude and non-optimal,
but they fit onto a single page – that in
itself, a breakthrough. I also noticed
something else: The minimalist-rules
generated layouts having a timeless
quality. They remained unchanged,
even as the process scaled down.
Suddenly it beamed down to me:
MOS design rules should not be
framed as sets of lengths but as sets
of ratios of lengths. Such dimensionless rules could then be scaled
to any process as multiples of a
basic length unit in microns, a unit I
called Lambda (m).
I quickly crafted an NMOS rule
set to explore this idea, setting m at
one-half the maximum of minimum
line-widths, separations, extensions, and overlaps. The resultant
rule set was less toy-like than the
minimalist rule set, and revealed
the full potential of the idea.
I vividly recall seeing Mead’s jaw
drop that spring morning in 1977
as I presented my strategy for m
-based rules on my whiteboard at
PARC. This was it! We now had a
‘structured’ design methodology (as
Mead called it) from top-to-bottom.
Of course the rules needed
tweaking to gain compactions and
to better anticipate scaling effects.
For example, we set line widths and
separations on the MET layer to 3m,
while keeping those on the POLY and
DIFF layers at 2m. Still, the rule set
remained small at only two pages in
length, easy to teach, learn, apply,
and check (see Fig. 4).
These simplified scalable design
rules had many implications. With
circuit density doubling roughly
every two years, why spend time
on intense layout compaction? Why
not compress design times by using
these simpler rules, and race to the
next smaller process that much
sooner? Even more importantly, scalable rules allowed cell topologies
to be laid out in a timeless form –
opening the door to widely-sharable,
time-durable MOS cell libraries.
Adjacent subsystems could also
often be abutted by designing their
cells at the same pitch (extending some cells’ lateral dimensions,
where needed), saving space and
improving performance by eliminating wiring channels. EDA tools
for generating and checking layouts
were also greatly simplified and
speeded-up by using rectilinear wiring on a Lambda-based integer grid,
rather than at arbitrary angles and
dimensions as in earlier practices.
Thus the Lambda-based design
rules played a similarly simplifying,
empowering and unifying role at the
knowledge-interface between VLSI
designs and EDA tools, as had the
self-aligned MOS gate at the knowledge-interface between LSI designs
and semiconductor fabrication.
The scalable design rules opened
another door, as well. Suddenly a
clean separation between chip design
and fabrication was possible, with
extremely simple rules providing
the interface.
The “Tall Thin Man”
The transparency of the new methods enabled architects to design
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fa l l 2 0 12
15
3m
2m
(a)
(b)
m
m
2m
m
m
2m
2m
2m
(i)
(d)
(c)
(j)
6m
2m
2m
m
Cover
2m
4m
2m
(e)
m
(f)
(k)
2m
4m
(l)
1½m
m
3m
2m
m
m
3m
1½m
(g)
1½m
(h)
(m)
(n)
FIGURE 4: The m-based scalable NMOS design rules [23], [24]. (a) W d /m H 2. (b) S dd /m H 3. (c) W p /m H 2. (d) S pp /m H 2. (e) S pd /m H 1. (f) E pd /m H 2.
(g) Example of several rules. (h) S ig /m H 1 12 ; E ig /m H 1 12 . (i) W c /m H 2 ; E dc /m H 1. (j) E pc /m H 1. (k) S cc /m H 2; S cg /m H 2. (l) O pd /m = 1, and details
of butting contact. (m) W m /m H 3; S mm /m H 3. (n) E mc /m H 1.
systems from top-to-bottom, as
they had in the days of relay contact
switches and vacuum tubes in the
1950’s, when I was a student.
Now once again, digital circuitry could be easily envisioned
and crafted, using simple rules
of thumb. No longer were extensive calculations and circuit simulations needed as in bipolar IC
design. While such efforts were
still needed during process development to ensure circuit function
and performance, they were not
needed when designing prototype
circuits and layouts. So long as onchip test patterns found that electrical parameters were within spec,
our design rules of thumb worked
perfectly well.
For years, ECL and TTL had
imposed logic-gate and clockedge-triggered flip-flop register
abstractions onto system design –
impeding top-down visualizations
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fa l l 2 0 12
of alternatives for expressing
architectures in silicon. Using our
methods, architects could clearly
visualize and instantiate their
creations all the way down to the
switches in silicon. It was a tremendous breakthrough!
A new world of architectural
exploration opened up before us, a
world I had peered into twelve years
before, when inventing DIS at ACS. I
sensed that thousands of engineers
could now have similar experiences
as system architects by exploiting
our new methods. At least, that was
my theory at the time.
Meanwhile, Fairbairn’s and Rowson’s ICARUS software and Ayres’
ICL/ICLIC enabled us to input, edit,
print, and visually inspect our layouts. However, these were only the
beginning of a parallel revolution
in EDA, as new tools evolved to support work across the restructured
levels of abstraction. The scalable
IEEE SOLID-STATE CIRCUITS MAGAZINE
design rules in particular had dramatic implications for tool-building
and chip prototyping.
By this time, however, signs of
resistance were emerging at PARC,
as critics in the competing Computer
Science Lab (CSL) looked askance at
what they saw as our “toy” designs
and “toy” design tools. Not surprisingly, they questioned what our tiny
effort could possibly bring to the
huge semiconductor industry.
What we clearly needed were
classy tutorial design examples,
and in June 1977 Dave Johannsen
set out to rigorously apply the new
methods to the design of a followon data path chip at Caltech. The
OM2 would be completed by yearend, yielding excellent examples
of subsystem design using the new
methods. Unlike the OM1, the OM2
actually worked.
Early in our work Mead had
coined a term – The “Tall Thin
Man” – to describe system designers like Johannsen who used our
exploratory methods, and the term
eventually took its place in the
lexicon of Silicon Valley. Although
women engineers (including me)
were excluded by Mead’s imagery,
the phrase stuck, for a time.
What to do with
the New Knowledge?
The rush of ideas in early 1977 led
to a host of challenges. Most especially, what were we to do with
the new knowledge? In response, I
began evolving a tutorial to unfold
and explain it all, honing a minimalist sequence of ideas sufficient
for architects to visualize what
a chip is and how it now might
be designed.
The task was akin to revealing
a medieval cathedral as composed
of pointed arches, ribbed vaulting,
thin walls and flying buttresses,
showing how a set of basic principles were sufficient to raise such
a complex structure. While doing
this work, I began realizing that
launching such an abstract system
of knowledge by publishing bits and
pieces here and there in traditional
journals would be inadequate, especially when it challenged so much
established practice. What to do?
The Idea of “The Book”
The die was cast in early June 1977,
during a relaxed, evening team-brainstorming meeting at PARC. Thinking
out loud, I launched the idea: Why
not write a book about our work, and
self-publish it using PARC’s Alto systems and laser printers?
If the book were comprehensive,
well-written, and filled with good
design examples, it would appear
to reflect years of mature practice.
In yet another echo of the Steinmetz story, I theorized that such a
book would be taken seriously and
could launch the new methods we
were proposing. Mead let out a big,
“Yeah!”, and Fairbairn was excited
as well. So that was it. The decision
had been made, and off we went.
The
sophisticated
computing environment at PARC gave us
uncommon confidence. We could
interactively create documents and
designs using our Alto systems, collaborating locally via e-mail and filesharing, and interacting remotely
with colleagues at leading universities by using the new ARPANET.
Swept along by PARC’s movement to
bring computer power to the individual, we had intellectual powertools at our disposal that provided
the means and the wherewithal to
do unprecedented things.
As I began writing the book, my
Alto became the integrating node
and control-center for a wildlyexpanding project and community of
contributors. While I drafted explanations of the structured design
methods, Mead provided input on
NMOS fabrication and mask-making,
Fairbairn and Rowson crafted an ICARUS tutorial, and Johannsen began
documenting OM2 design examples
to round out the text.
We introduced the first three
chapters in the fall of 1977, interjecting them into MOS circuit design
courses taught by Mead at Caltech
and by Carlo Séquin at U.C. Berkeley. (Séquin had recently joined
our team as a consultant at PARC).
We titled those preliminary chapters Introduction to LSI Systems, but
then paused at how to acknowledge
authorship. Mead was a well-connected full professor at the time,
while I was virtually unknown outside of our group. Thus even though
I was the architect and principal
author of the book, we listed Mead
as first author – to enhance the
book’s credibility [23].
Building on the feedback that
came in, I prepared five full chapters
for courses set to be taught the next
spring. Dick Lyon, a brilliant Caltech
grad and signal processing expert
joined our team at PARC. (Lyon went
on to invent the optical mouse,
among other things.) The winter
of 1977–78, Lyon and Carlo Séquin
worked with computer graphics
expert Robert (Bob) Sproull to refine
and produce a formal description of
the CIF language (CIF2.0). Johannsen
also completed the OM2 in December 1977, in a much-needed early
validation of the new methods.
By February 1978, I had incorporated the ICARUS tutorial, the
CIF2.0 specification, and the OM2
design examples into a draft of the
first five chapters, just in time for
spring semester courses taught by
Bob Sproull at CMU and Fred Rosenberger at Washington University.
This version of the book included
many color plates I had made on the
new color copiers at PARC, enabling
easier teaching and better mastery
of the new methods [23].
Then one day, in a rush of enthusiasm, I changed the title to Introduction to VLSI Systems.
Bert’s Challenge
By this time, Bert Sutherland had
joined the EECS Department advisory
committee at M.I.T., and soon after
offered me a challenge: Go to M.I.T.
in the fall, he said, and introduce a
senior/masters-level course on this
stuff. I was thrilled. We’d been testing
portions of the book in various MOS
circuit design courses, but this was
the chance to pioneer a completely
new full-fledged system design
course based solely on the book.
I was also terrified. A bit shy
among strangers and fearful of public speaking, I also lived in dread
of being outed about my past. Up
to now, I had been sheltered as a
researcher in the laboratory environment at PARC, and had only
recently begun to flourish as a
research manager there. Teaching
at M.I.T. would be quite a different
matter, involving much more public visibility. It seemed beyond my
reach and in my anxiety I wavered.
But Bert insisted: “Lynn, you’ve got
to do this!”
Shortly afterward, while glancing
at Steinmetz’s photo on my office
wall, his story came back to mind,
especially the impact of his teaching at Union College. It was one of
the great turning points in my life:
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17
labs joined in the effort; in fact, the
whole team pitched in to help compile the new guidebook [25].
Summer passed in a whirlwind
of preparations. Before long I was
packing-up boxes of freshly-minted
texts and course handouts – and
heading out on my 3000-mile road
trip to M.I.T.
Launching the Course
FIGURE 5: Students at DEC-20 terminals in the MIT ‘78 VLSI design lab.
I threw caution to the wind, and
went for it.
Planning the M.I.T. Course
The spring of 1978, I immersed
myself in finishing the book. While
I drafted Chapter 6 on the architectural level of abstraction, Charles
(Chuck) Seitz at Caltech drafted
Chapter 7 on self-timed systems, H.
T. Kung at CMU provided material
on concurrent processing for Chapter 8, and Mead drafted Chapter 9 on
the physics of computation. A full
draft would be ready by summer,
just in time for the course [23].
I also got an important idea: If I
could compress teaching of the new
methods into the first half semester, students could launch design
projects during the second half. If
I could then organize quick-turnaround (QTA) implementation of the
student projects – including layout
file merging, mask file formatting
and generation, mask-making, wafer
fabrication, dicing, packaging and
wire-bonding – I might be able to
get packaged chips back to students
shortly after the course ended.
I felt that the unprecedented
opportunity to design your own chip
would attract very bright students to
the course. And their projects would,
in turn, heavily test the design methods, design tools, book, course, and
18
fa l l 2 0 12
quick-turnaround
implementation
methods. As the summer of 1978
progressed, I based the whole course
plan around these ideas.
With Bert’s support, I also
launched a summer program for the
VLSI Systems Area (my new research
department at PARC), recruiting
Steve Trimberger of Caltech and Rob
Hon of CMU as research interns.
Trimberger worked with Fairbairn on
design tool development, while Hon
organized mask-making and fabrication of a set of PARC designs as a
multi-project chip (MPC), enhancing
our experience in quick turnaround
implementation during the run-up
to the course.
Building on that experience, Hon
and Séquin compiled The Guide to
LSI Implementation, as a guidebook
to our innovative clean interface
between chip design and chip fabrication and to the logistical details of
implementation. Dick Lyon created a
library of critically important cells
(input pads with ‘lightning arrestors’
for electrostatic protection, output pads with tri-state drivers, PLA
cells, etc.), contributing CIF code and
color plots of the cells to the guidebook. Lyon also updated ICARUS to
accept and manipulate oversized CIF
code files as outlines and produce
a merged MPC CIF file. Rick Davies
and Maureen Stone from other Xerox
IEEE SOLID-STATE CIRCUITS MAGAZINE
Launching the course was a formidable experience, in particular
because I was terrified of becoming
tongue-tied in front of the students.
My solution was to be massively
over-prepared.
I wrote out each lecture in complete detail, including every instructional point, every drawing and
every calculation. Along the way, I
unfolded the fundamental concepts
of electric circuit theory, electronic
design, switching theory, digital
logic design, and computer system design, to ensure that all students were well-grounded in every
level of abstraction, independent of
their background upon entering the
course. I didn’t see it coming at the
time, but this work to avoid gaps in
student comprehension would have
unforeseen, far-reaching effects.
Jonathan (Jon) Allen was my
faculty host for the course, and
his student Glen Miranker was my
TA. The class included 32 students
and 9 faculty/staff auditors. Staff
researcher Bill Henke built CIFTRAN,
a symbolic layout tool for encoding
CIF specifications, while Miranker
set up a lab where students could
access CIFTRAN via DEC20 terminals and plot their layouts using HP
pen plotters. Meanwhile, I kept in
close contact with my team at PARC,
using a portable, acoustic-coupled,
TI printer-terminal to transmit
e-mails via the ARPANET.
Contrary to my apprehensions,
the students became tremendously
excited by my teaching. They seized
the opportunity to learn by doing
and ran with the new knowledge.
Many ambitious projects got underway and I began holding my breath,
realizing if things went well,
Problems Arise,
Pushback Begins
this could be a huge win.
Mead and I had contracted
By now, Alan Bell of BBN
with Addison-Wesley to pubhad joined my team at PARC.
lish the book, and in early
He and Dick Lyon began
1979 I began the tedious
preparations for the QTA
task of coordinating the
implementation of the projcopy-editing, hoping to have
ects, and everyone pulled
it ready for courses slated
together at both ends to coorfor that fall.
dinate things as the design
Word spread quickly on
cut-off date approached.
the ARPANET about the M.I.T.
I sent the final student
course, especially the news
design files to PARC via the
about Steele’s LISP microARPANET on December 6,
processor. Many professors
1978. Lyon and Bell then
asked how to offer similar
merged the 19 projects into
courses, and how to lead
a multi-project-chip CIF file,
ambitious design projects. In
converted it to Mann PG forresponse, my group at PARC
mat, and had masks made by FIGURE 6: Students Jim Cherry and Gerald Roylance and TA Glen
began to train instructors in
Micro Mask using their new Miranker study a checkplot, MIT ‘78.
the new methods of teaching
electron beam system. In
VLSI design.
this first phase of an imporDoug Fairbairn and Dick Lyon
tant collaboration with Pat Castro
sensed where it might lead. I had also
ran an intensive short course for
at Hewlett-Packard, wafers were
gained real confidence as a research
PARC researchers during the spring
fabricated at her Integrated Circuit
team leader, and itched to do more. I
of 1979, which was videotaped. We
Processing Lab (ICPL) at nearby
drove on, rock music blaring on the
began using those tapes as the basis
HP Research using a 6-micron
radio, my head in the clouds, savoring
for short, intensive courses at PARC
(m = 3 nm) silicon-gate NMOS prothe moment.
cess. Everything went off without a
for university faculty members in
Something powerful rode along on
hitch, and the packaged chips were
the summer of 1979. With the help
that trip – an instructor’s guidebook
shipped back to M.I.T. on January 18,
of the PARC tapes, Mead and Ted
on how to teach such a course, in the
1979 (see Fig. 7).
Kehl also ran a course at the Univerform of hundreds of pages of careAlthough my students had
sity of Washington that summer.
fully handwritten lecture notes [26]
only primitive EDA tools, and had
resorted to hand-checking of design
rules, the new methods so simplified the design work that not many
errors were made, and the course led
to a very exciting group of projects.
Jim Cherry, for example, designed
a transformational memory system
for mirroring and rotating bit-map
image data, and his project worked
completely correctly. Guy Steele,
in an even more ambitious project,
designed a complete LISP microprocessor. The processor almost
worked on this first try, except for
three small wiring errors. As such, it
set a high mark for others to follow.
After finishing the semester at
M.I.T., I took a leisurely route back
(a)
to California, traveling through the
South and Southwest. I knew something profound had happened in
FIGURE 7: Photo of the MIT ‘78 chip set. (Melgar Photography)
the M.I.T. course, but I only vaguely
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19
ARPANET Geographic Map, October 1980
MIT44
MOFFETT
LINCOLN
LBL
AMES15 AMES16 LLL
SRI2
UTAH
SRI51
XEROX
STANFORD TYMSHARE
NPS
SUMEX
HAWAII
ACCAT NOSC
DOCB
STLA
UCLA
AFSD
ISI27
RAND
ISI52
CIT
USC
ANL
GWC
DTI
SCOTT
AFWL
YUMA
ISI22
WSMR
Satellite Circuit
IMP
TIP
Pluribus IMP
Pluribus TIP
C30
COLLINS
GUNTER
MIT6
CCA
RCC5
AFGL
NYU
RCC49
DEC
CORADCOM
BBN40 RCC71
RADC
BBN63
CMU
BBN72
HARVARD
WPAFB
ABERDEEN
DARCOM
ANDRW
NRL
NBS
NSA
DCEC
NORSAR
SDAC
MITRE
PENTAGON
ARPA
EGLIN
BRAGG
ROBINS
LONDON
TEXAS
(Note: This Map Does Not Show ARPA’S Experimental Satellite Connections)
Names Shown are IMP Names, Not (Necessarily) Host Names
FIGURE 8: Map of the Arpanet, circa 1980.
I also organized my M.I.T. lecture
notes to create the Instructor’s Guide
to VLSI System Design and began
printing copies for all those interested in teaching the course [26]. It
was these notes, rather than the textbook alone, that for the first time contained the full exposition of the new
design methods – unfolding a teachable, accessible, minimalist, covering
set of knowledge that enabled students to quickly learn how to competently do VLSI system design.
However, we had a big problem:
there was no way to implement
design projects from so many universities, other than for each to
arrange for their own mask and fab.
We had defined a clean interface
between design and fab at the layout design-file level, but the logistics of implementation were far too
complex for isolated departments or
design groups to handle.
I felt that unless students could
learn by doing, and make things
that worked, they would have
merely learned a theory of design.
Attacking this problem head-on, I
launched work to further simplify
and document the logistics in a new
20
fa l l 2 0 12
edition of Hon & Sequin’s Guide to
LSI Implementation, hoping to help
more instructors implement their
students’ projects in the fall 1979
semester [25].
Mead coined the name “foundry”
for any semiconductor firm that
could ‘print’ externally generated
designs created using the scalable
design rules, and he began popularizing the term to lure firms into
providing this type of service. Given
Mead’s high-level business connections, it wasn’t long before folks
across the industry were buzzing
about his provocative term, wondering what it meant for them.
As noise spread about Mead and
Conway, signals of serious resistance began to arise. Experts at
various levels of abstraction began
having allergic reactions: when seen
from the viewpoint of each narrow
abstraction our stuff looked far too
crude and naive to possibly work.
Trouble also arose within PARC.
My new research department in SSL
came under increasing attack from
the leaders of the Computer Science Lab (CSL), who wondered why
budget and headcount were being
IEEE SOLID-STATE CIRCUITS MAGAZINE
devoted to such questionable work.
They didn’t seem to grasp why the
freedom to improvise and playfully
create things was so important when
working in a new medium – whether
in art or music or engineering –
especially when exploring what it is
possible to do.
Some in academe even began to
wonder if we were nuts. “Who are
these people?” they asked. To them,
Mead was a device physicist making
wild pronouncements on computer
design, while Conway seemed some
totally unknown woman tagging
along as Mead’s ‘assistant.’ Such reactions to appearances were totally
understandable. Something had
to be done to turn things around,
but what?
Necessity is the Mother of Invention
It began as a daydream that spring
of 1979, as I fantasized about the
impact of large numbers of M.I.T.
type VLSI design courses.
I could feel the powerful energy
out there: the young faculty members hoping to stand out and
get tenure, the students seeking
careers in a frontier area, the folks
To ARPANET
(User MSGS, System MSGS, Operator MSGS,
System Library Files, User Design Files)
User Message and Design File
Processing Subsystem
(Control Info)
Die-Layout Planning
and
Design File Merging
Subsystem
File Storage
System
(Control Info)
Operator
Terminal
CIF to MEBES Conversion
Subsystem
(Mask, Fab, Packaging
Schedules and Constraints)
(MEBES Mask Specification Files)
(Control Info, Bonding Diagrams,
Implementation Documentation)
FIGURE 9: MPC79 implementation system: overview of the software.
who wanted to start companies and
make their fortunes. Imagine how
they’d rush to participate in the new
courses, get into VLSI and design
their own chips!
Back in reality: My group had
maxed out our capability when handling projects from just one school.
How on earth could I scale up chipprototyping to handle ten or more
such courses?
I began doodling on my whiteboard, searching for ways to simplify
the implementation process, shorten
its turnaround time, and scale it
up. Although we’d documented static
technical interfaces in the Guide to
LSI Implementation, many procedures
needed to be charted and many questions remained about who should
do what, and when. Plus we had no
means to handle information flow
and coordinate interactions on such
a large scale.
Suddenly it struck me: What if we
positioned an interactive messagehandling and file-handling server
that orchestrated interactions over
the ARPANET? That would streamline everything, eliminate the need
for constant human interactions,
and bring the needed scalability.
What I envisioned was an early
form of Internet commerce system,
where design files could be sent to a
server and packaged chips returned
after implementation. From an
information management point of
view, it would be analogous to sending many separate magazine articles to a remote server, where they’d
be coalesced into a printable mosaic
and queued for magazine printing.
With such a system, we could
send messages to the chip ‘authors’,
coordinate all activity, do CIFsyntax checking and space requirement checking, and then at the design
cut-off time, reel in the final projects’
design files. It was clear that such a
“VLSI implementation system”, as we
called it, could then under operator
control plan die layouts for multiple
multi-project chips (MPCs), merge
the design files into those MPCs, and
generate MEBES (Manufacturing Electron Beam Exposure System) files for
mask generation.
When I excitedly revealed this
idea to Mead, he went cold and said
“Don’t do it.”
Mead worried that the event
would appear to be orchestrated
by DARPA and they would “take all
the credit”. I understood, for DARPA
had ended up gaining much of the
visible credit for Stoner’s M16 rifle
after simply running field trials and
promoting the weapon, but so what?
That’s the way the world worked.
Why let concerns about credit interfere with doing something cool?
IEEE SOLID-STATE CIRCUITS MAGAZINE
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21
Mead also felt that each school
should connect directly with mask
and fab services on its own, just as
he’d been doing at Caltech, rather
than fall under the control of a
centralized service. I disagreed, for
I thought his notion of foundry as
yet undeveloped, in that it relied too
much on undocumented personal
expertise, lacked methods for information management, and hence
lacked scalability. More importantly,
it could not be widely implemented
in time for courses in the fall of
1979. Uneasy collaborators from the
start, these sharp differences pretty
much ended our interactions.
Fortunately
Bert
Sutherland
remained enthusiastic, and I forged
ahead. We ramped up work on the
implementation system, with Alan
Bell and graphics expert Martin
Newell developing the software.
Although the software itself was
conceptually straightforward, the
space of possible user interactions
was highly complex. It took great
effort to anticipate all such interactions and formulate specially constrained key-worded messages to
handle them all; Bell began making
critical innovations in this area.
As summer approached, it seemed
we just might be able to pull it off. By
now faculty members at many universities were planning to offer the
course, but we hadn’t yet announced
INTRODUCTION TO
SYSTEMS
CARVER MEAD • LYNN CONWAY
FIGURE 10: The Mead-Conway text.
22
fa l l 2 0 12
the chip implementation service.
Time was running short and I had to
make a decision.
With just a tinge of fear, I drafted
an e-mail, complete with a huge
promise to the many faculty members and many, many students out
there: We at PARC would implement
the chip designs from all MeadConway courses offered that fall,
in an ARPANET happening called
“MPC79”. I knew if what I was offering didn’t work, I would have to go
into hiding. I hesitated, suspended
in the moment, then pulled the trigger and pushed “SEND”.
MPC79: The Network Adventure
The summer passed in a rush.
Alan Bell and Martin Newell
readied the implementation system
software, while Bell, Rob Hon and I
carefully crafted e-mails to send at
intervals during the fall – establishing
a strict timeline to coordinate activities. Hon and Séquin completed the
second edition Guide to LSI Implementation, which included the definition of CIF2.0 by Bob Sproull and
Dick Lyon, an expanded set of PLA
cells and I/O pads created by Lyon
for all designers to use, along with
a lot more information about implementation procedures [25].
All sort of wild things happened
as we went along – some serendipitous, some funny, some scary. A
young Stanford professor named
Jim Clark asked if he could hang
out at PARC, learn the basics of chip
design and do a project for MPC79.
I said sure, and helped him with
some basic instruction. An expert
in system architecture and computer graphics, Clark seemed a perfect adventurer to launch into VLSI.
After taking Fairbairn and Lyon’s
PARC videocourse, Stanford professor Forest Baskett and his Ph.D. student Andreas Bechtolsheim also did
projects for MPC79; they would later
become famous as architects of the
SUN workstation and more.
A crisis then developed. A senior
academic of impeccable standing
called an urgent meeting with George
IEEE SOLID-STATE CIRCUITS MAGAZINE
Pake, Director of PARC. Apparently
my announcement of MPC79 seemed
incomprehensible to the establishment at the time, and the academic’s
school was among those threatened
by the perceived infection. His message: Conway is “crazy”, the MCP79
project is unsound, and Xerox will
suffer huge embarrassment unless
it’s cancelled.
I could feel the apprehension in
Bert’s voice as we hurried to Pake’s
office, and I nearly panicked when
they told me what happened. We
knew the concerns were truly justified. Although the new methods had
worked at M.I.T. and our computers
provided powers outsiders couldn’t
imagine, MPC79 was a huge gamble.
However, Bert stood by me and the
cloud lifted. Pake said “Not to worry.
Just do it.”
The vibrant counter culture
within PARC helped brace us
against all doubts; it seemed everyone there was reaching for dreams.
On the outside people saw a prestigious corporate lab housed in a
castle-like building, high on a hill
overlooking Palo Alto. It was a dignified image much like that of IBM’s
lab at Yorktown Heights, i.e., one
that established folks took very
seriously. How could they possibly imagine what went on within
PARC’s walls?
This contrast came home to roost
one weekend evening, as I passed by
a young Rob Hon at his Alto. In T-shirt
and jeans, feet propped on a chair,
using his Alto to send an important
MPC79 message to the universities:
“If only they knew who’s doing this,”
he quipped.
Primed and bonded by our
experiences during the 1978 M.I.T.
course, the team was really on a
roll, and an atmosphere of excitement and fun permeated our work.
Everyone seemed to know what to
do, no matter how novel the situation. Individuals jumped in and out,
taking on creative improvisational
roles as opportunities arose, much
as seasoned musicians would in a
fine blues and jazz band.
MPC79 Flowchart:
User Community
~ 100 Designers at:
MIT, Caltech, Carnegie-Mellon Univ., Stanford,
Univ. of Illinois, U.C. Berkeley, Univ. of Wash., …
(Using AIDS/LAP/ICARUS/etc.)
DS 12; 9 PlaCell;
(5 Items);
LNM; BL 4000 W 1000 C 2000, -750;
...
L NP; BL 500 W 4000 C 2500. -2000;
DF;
(MSGS, Design Files)
Project Lab Coordinators at Each School Use Local Electronic
Mail and File Transfer Facilities to Interact with the Designers
and Use the ARPANET to Interact with MPC79
(MSGS, CIF2.0 Design Files)
Data Comm. Facility
To: [email protected]
From: [email protected]
Subject: IMPLEMENT PROJ.CIF
ARPANET
(MSG, FTP, TELNET)
(MSGS, CIF2.0 Design Files)
IMPL Facility
Info. Mgmt System: Xerox PARC/SSL
Checking, Planning, Merging of Designs into Starting Frames
Meeting of Constraints, Coordination, Logistics
(Design Files, Merged
into Starting Frames)
(Constraints, Logistics,
Control Info.)
“The Foundry”
Maskmaking: Micro Mask, Inc.
Data Format: MEBES; ETEC Electron-Beam System
(Masks)
Wafer Fabrication: H-P/ICPL
NMOS Silicon Gate
Lambda = 2.5 Microns
(Wafers)
Packaging
(Bonding Maps) (Packaged Chips)
(Elect. Params)
(Plots)
Packaged Chips, Customs Wire-Bonded Per Project, Along with
Plots, Wire-Bonding Maps, and Results of Electrical Testing,
to Send Back to the Designers for Functional Testing
FIGURE 11: Flowchart of events for MPC79.
A huge phenomenon unfolded that
fall as our coordinating messages
and files surged across the ARPANET.
Twelve universities participated, with
courses given by Jon Allen and Lance
Glasser at M.I.T., Chuck Seitz and
Carver Mead at Caltech, John Newkirk
and Rob Mathews at Stanford, Richard
Newton and Carlo Séquin at Berkeley,
Bob Sproull at CMU, John Murray at
University of Colorado, Jacob Abraham at University of Illinois, Ted Kehl
at University of Washington, Edward
Kinnen and Gershon Kedem at University of Rochester, Vance Tyree at
UCLA, Fred Rosenberger at Washington University, St. Louis, and John
Nelson at USC.
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23
All courses used the
and diced them, mounted
new Mead-Conway text
die into 40-pin packages
(see Fig. 10), published
(enough for three per projjust in time by Addisonect), and wire-bonded to the
Wesley [24], while faculty
individual projects within
and TAs had access to the
each die (see, for example,
new Instructors Guidebook
Figs. 14, 15, 16). Packaged
and the latest edition of
chips were shipped, along
the Guide to LSI Implemenwith chip photos and docutation, which I’d printedmentation, to students and
up in large numbers at
researchers at the 12 uniPARC [25], [26].
versities on Jan. 2, 1980
All courses were syn[27], [28].
chronized with the MPC79
We’d done the impossiFIGURE 12: Alan Bell at PARC, completing the design-file merge for
schedule (see Fig. 11), and
ble: demonstrating that sysMPC79.
most students completed
tem designers could work
projects for inclusion in
directly in VLSI and quickly
MPC79. This was remarkable, as
obtain prototypes at a cost in time
mask-making was again done by
many schools were offering the
and money equivalent to using offMicro Mask, pipelined with wafer
course for the very first time,
the-shelf TTL.
fabrication to reduce time to comand design tools were being proThe MPC79 chip set contained
pletion. With the support of Merrill
grammed as they went along. These
82 design projects from 124 designBrooksby and Pat Castro at HP, fabevents in the fall of 1979 escalated
ers, spread across 12 die-types on
rication was again provided by HP’s
into a giant network adventure that
two wafer sets. Astoundingly, turnICPL using a 5-micron (m = 2.5 nm)
silicon-gate NMOS process.
climaxed as the design-cutoff time
around time from design cutoff to
Meanwhile, Dick Lyon, Alan
approached, and as the final rush
distribution of packaged chips was
Bell, Martin Newell and I readied
of design files flowed through the
only 29 days [27].
“Implementation Documentation” for
ARPANET to PARC.
Importantly, these weren’t just
designers, including lists of projects,
At 5:00 pm sharp on December 4,
any designs, for many pushed the
die-maps, wire-bonding maps, elec1979, Alan Bell closed external interenvelope of system architecture.
trical process test data, chip photos
actions and began die-layout planJim Clark, for instance, prototyped
by Melgar Photographers and more.
ning, file merging (see Fig. 12), and
the Geometry Engine and went on to
When the wafers arrived, we scribed
MEBES format conversions. E-beam
launch Silicon Graphics Incorporated
FIGURE 13: Lynn Conway, Alan Bell, Martin Newell and Dick
Lyon complete the final packaging of MPC79 chips for distribution to designers.
24
fa l l 2 0 12
IEEE SOLID-STATE CIRCUITS MAGAZINE
FIGURE 14 (a, b): MPC79 wafer, die and packaged chip.
Design Methodology
Text, Instructors’ Guide, and Other Documents
Courses
Design Environments
Student Design Projects
Implementation Methodology & Systems
FIGURE 15: Photo of MPC79 die type BK,
from Stanford University. (Melgar
Photography)
FIGURE 16: “Geometry Engine” prototype by Jim Clark of Stanford (a project on
MPC79 die-type BK). (Melgar Photography)
based on that work (see Fig. 16).
Guy Steele, Gerry Sussman, Jack
Holloway and Alan Bell created the
follow-on ‘Scheme’ (a dialect of LISP)
microprocessor, another stunning
design. Along with scores of other
innovative projects, these designs
signaled that an architectural gold
rush was underway.
New Media Proclaim Revolution
As engineers, our ideas are often
tested by primal forces, and in the
end what works, works. No matter
how unknown the designer or how
controversial the design, if a bridge
stands, it stands.
MPC79 stood, and with it, the
design methods, the instructor’s
guide, the book, the implementation
guide, the course, and many innovative EDA tools and chip designs (see
Fig. 17). To most participants it had
Design Prototypes
FIGURE 17: The evolution of a multi-level system of knowledge: design projects provide
feedback for debugging at all levels [28].
all seemed pretty straightforward.
Taking the courses for granted, most
must have thought “I guess this is
the way things are done in Silicon
Valley.” They had passed through
a huge paradigm shift [29] without even knowing it, never having
designed or implemented prototype
chips “the old-fashioned way” – and
the entire system of methods had
been proven sound by the success
of MPC79.
But what about the rest of the
world? MPC79 hardly seemed believable unless you were there. Like the
Impressionist Movement in France,
we needed our own “Salon” – a separate place for showing our works
where people could stand back,
grasp the thing in its entirety, and
see that the new methods stood.
Badly needed, that level of success
wasn’t long in coming.
Chuck Seitz had organized the
first VLSI Conference at Caltech in
January 1979, to provide a forum for
the new VLSI systems researchers. In
January 1980, a second conference
was held at M.I.T., quickly bringing
news of the success of MPC79 to an
influential audience.
Meanwhile, during the exciting
summer of 1979, Doug Fairbairn and
Jim Rowson had had the idea of publishing a magazine for the emerging community of VLSI designers
and tool builders, and began working on it in parallel with our work
on MPC79. The first issue appeared
in January 1980 (see Fig. 18), and
Lambda (later known as VLSI Design,
then Integrated System Design Magazine) soon attracted scores of technical articles about VLSI architectures,
design tools and implementation
methods [30]. Those articles, along
with the many Melgar chip photographs it featured, made Lambda
a potent medium for spreading the
revolution [27], [28].
In another exciting move, Fairbairn left PARC to become a founding member of VLSI Technology,
Inc. (VTI), a company that pioneered VLSI ASIC design. Working
with Merrill Brooksby (Manager of
Corporate Design Aids at HP and by
then a strong advocate of our new
methods), Fairbairn also organized
FIGURE 18: The premiere issue of Lambda,
the Magazine of VLSI Design (1st Qtr, 1980).
IEEE SOLID-STATE CIRCUITS MAGAZINE
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25
the videotaping of a short intensive
VLSI Design Course. Fairbairn and
Stanford professors Newkirk and
Mathews gave the primary lectures,
with guest lectures given by Mead,
Lyon, Rowson, Johannsen, Seitz and
myself – along with Richard Newton of U.C. Berkeley, Jack Holloway
of M.I.T and Jim Clark of Stanford.
In addition to wide use within HP,
the VTI videotaped courses were
run at other places to ramp up
their ASIC business. Meanwhile,
Jon Allen ran intensive VLSI design
summer courses at M.I.T., impacting
design practices at DEC and other
East-coast high-tech firms. Carlo
Sequin also began offering intensive courses in VLSI design, as part
of the Hellman Associates Tutorial
Series, at many locations around
the country.
Mead also began exploring opportunities to capitalize on the work.
Always a charismatic personality,
he generated lots of buzz among
Silicon Valley venture capitalists.
In 1981 Mead, along with Dave
Johannsen and Ed Cheng, founded
Silicon Compilers Inc. to commercialize Johannsen’s work. Mead went
on to start even more companies as
time went by.
Perhaps the most powerful
medium for spreading the new
methods, however, was the ARPANET, as messages told the story of
MPC79. Before long, many more
schools around the country began
offering Mead-Conway courses, and
design tools and design files rocketed across the ARPANET into a
growing community of participants,
in a huge wave of disruptive technology and innovation.
Struggling to cope with these
fast-moving
developments,
we
planned yet another MPC system
run in the spring of 1980. Led by
Ted Strollo at PARC, the ‘MPC580’
project implemented 171 VLSI system design projects from 15 different universities and research
organizations. It was another crashing success and a further validation of our methods and teachings.
26
fa l l 2 0 12
These courses generated vast numbers of large check-plots – many
appearing in the hallways of EECS
departments around the country – and these amazing artifacts
attracted even more students to the
new movement. VLSI adventurers
were the new gang in town, and our
graffiti were on all the walls [28]!
As courses spread to major universities all around the world, I struggled
to supply startup ‘care-packages’ of
Instructor’s Guides, Implementation
Guides, and Implementation Documentation from MPC79 and MPC580.
But a bigger question began to loom:
How to institutionalize the MPC
implementation service, and keep
it going?
The DARPA VLSI Program
Robert (Bob) Kahn and Duane Adams
at DARPA had provided funding for
Ivan Sutherland’s Silicon Structures
Project at Caltech, and with Ivan’s
guidance had closely followed the
subsequent events. The success of
the M.I.T. course in the fall of 1978
convinced them that the new MeadConway VLSI methods were sound.
The publication of the book and success of MPC79 sealed the deal.
Kahn and Adams quickly convinced DARPA’s leadership to
launch a VLSI Research Program
to build on the new methods, and
major funding soon flowed into
research on new VLSI architectures
and EDA tools. Managed initially by
Adams in 1980 then by Paul Losleben in 1981 and beyond, the program sponsored tens of millions of
dollars in VLSI research. With this
level of support, a rush of intellectual adventurers jumped into the
movement.
DARPA sponsors MOSIS
to Institutionalize MPC79
With DARPA support behind him,
Bert Sutherland then solved another
big problem: He found a home for
the MPC79 technology and implementation service. In the spring of
1980 Bert, Alan Bell, Ted Strollo and I
met with Keith Uncapher and Danny
IEEE SOLID-STATE CIRCUITS MAGAZINE
Cohen of USC-ISI (a major DARPA
software contractor), and arranged
a rapid transfer of the PARC MPC
system technology and methods of
operation to ISI.
ISI soon announced the new
“MOSIS” service, and it began operations in early 1981. Prominent
Caltech researcher Chuck Seitz later
reflected that “MOSIS represented
the first period since the pioneering
work of Eckert and Mauchly on the
ENIAC in the late 1940s that universities and small companies had access
to state-of-the-art digital technology.”
What began in MPC79 as revolutionary technology to advance the
VLSI design movement became one
of the earliest examples of automated internet commerce. Operating to this day, MOSIS is still housed
at the USC facility in Marina del Rey,
California [31].
The Paradigm Shifts
That same year, Electronics Magazine awarded their Award for
Achievement jointly to Mead and
me. The magazine’s feature article
about the VLSI methods, the book
and the successes of M.I.T.’78 and
MPC79 put the engineering community on high alert that a revolution
was at hand [32].
I had now experienced my “Steinmetz moment”, for within two years,
120 universities around the world
were offering Mead-Conway VLSI
courses, with the book translated
into Japanese, Italian, French, and
Russian (this last, an “unauthorized” government edition distributed among many Soviet engineers).
Introduction to VLSI Systems eventually sold around 70,000 copies.
To provide further Mead-Conwaycompatible books on key topics,
Chuck Seitz and I served as serieseditors of Addison-Wesley’s new VLSI
Systems Series – one of the first being
Principles of CMOS VLSI Design by
Neil Weste and Kamran Eshraghian.
The design-tool building to support early project labs at M.I.T.,
U.C. Berkeley and Caltech led to
rapid evolution of tools for the
Mead-Conway
methods,
triggering an explosion
in EDA innovations. This
earthquake of innovation,
where teams across the
globe built on each other’s
ideas, sharing libraries and
tools, presaged and helped
lay groundwork for the
modern open-source software revolution.
In 1979 two M.I.T. graduate students, Chris Terman
and Clark Baker, developed
a pioneering set of tools,
including a design rule
checker, circuit extractor
and static checker by Baker,
and a switch-level simulator by Terman. The tools
provided direct support
for ‘Mead-Conway design’.
They immediately received
widespread
distribution,
and began to change the
way people thought about
FIGURE 19: Conway and Mead receive the 1981 Electronics
doing their design work. In
Award for Achievement.
particular, Baker’s circuit
extractor was the first time
anyone had “closed the
loop,” making sure that the actual
in the movement went on to play
circuit layout implemented the
key roles in creating field programintended circuit – and circuit extracmable gate array (FPGA) technology
tion went on to become a mandatory
and tools, such as Steve Trimberger
part of most IC design processes.
at Xilinx.
During his M.I.T. Ph.D. work in
The architectural work of Jim
1979–1980, Randy Bryant originated
Clark on the Geometry Engine, and
new methods for switch-level simuof Steele, Sussman, Holloway and
lation, and he went on to place a
Bell on the M.I.T. Scheme micropromuch-needed mathematical foundacessor gained high visibility through
tion under switch-level design. By
Lambda and the VLSI conferences,
1983, the MOSSIM-II simulator that
triggering a rush of additional brilBryant and his students developed
liant young computer scientists and
(then at Caltech) was in use at Intel.
architects into the movement.
At Caltech, Dave Johannsen also
After attending Jon Allen’s
pioneered work on “silicon compilcourse at M.I.T. in the fall of 1979,
ers” which he later commercialized
Ron Rivest, Adi Shamir and Leonwith Mead. John Ousterhout and his
ard Adelman implemented their
students at U.C. Berkeley developed
recently invented “RSA Cipher” in
IC layout tools CAESAR and MAGIC,
VLSI using MPC79. At U.C. Berkeley,
establishing an architectural founDave Patterson and Carlo Séquin led
dation for many later EDA software
a team that created the RISC-I and
systems – including those comRISC-II architectures in VLSI. Carlo
mercialized by VLSI Technology,
reports that this work was inspired
Cadence, Valid Logic, Daisy, Menin part by a private communication
tor Graphics and Viewlogic. Others
with John Cocke, concerning work
on the 801 at IBM—another
pioneering IBM project that
was “moth-balled” and only
published many years later.
Similarly, at Stanford,
John
Hennessey,
Norm
Jouppi, Forest Baskett and
John Gill developed the RISCbased MIPS architecture
and prototyped VLSI implementations using MOSIS. At
UNC, Henry Fuchs and John
Poulton developed the PixelPlanes VLSI raster graphics engine, with assistance
from Al Paeth and Alan Bell
at PARC.
Dick Lyon at PARC pioneered smart VLSI digital
sensors based on lateral inhibition, inventing the optical
mouse and implementing
a VLSI prototype, and then
helped Martin Haeberli and
Robert Garner design a chip
for Xerox’s production Xerox
optical mouse. Lyon also
demonstrated how to create
VLSI architectural methodologies for special applications, using digital signal processing
as an example. Lyon and Gaetano
Borriello went on to create the first
single-chip Ethernet driver-receiverencoder-decoder, exploiting Lyon’s
new semi-digital methods.
The collaborations between PARC
and HP, Caltech and Intel, and MIT
and DEC led to rapid infusions of the
Mead-Conway methods into those
various firms. VLSI architectural
research also led to parallel VLSI
processors such as the Connection
Machine by Danny Hillis at M.I.T.,
the Cosmic Cube by Chuck Seitz at
Caltech and the WARP Processor
by H. T. Kung at CMU. Such research
was increasingly funded by DARPA
and led to many important startups,
including Silicon Graphics, MIPS
and Sun.
MOSIS was initially closed to
those outside the U.S., triggering the
launch of similar systems in other
countries. DEC computer architect
Craig Mudge returned to his native
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27
Australia to found the CSIRO
of those artifacts (and
VLSI program and AUSMPC
with them the new knowlservice, and my team at PARC
edge) through cleverly augassisted in those efforts.
mented diffusion channels,
Reiner Hartenstein, a profesand the provision of means
sor at Technische Universität
for immediate exploitaKaiserslautern then visittion of the knowledge via
ing U.C. Berkeley, returned
the new QTA implementato Germany, began teaching
tion service – all leading
the course, and spearheaded
to more artifacts and thus
Germany’s E.I.S. service –
‘gain’ in the knowledge
and he and Klaus Wölcken
propagation process.
also began advocating for a
The emerging internet
larger European-wide serand PC technology enabled
vice. Ole Olesen from Denme to operate in wholly
mark and Christer Svensson
new ways as an architect of
from Sweden formed the
disruptive change. Almost
Nordic Multi-Project Chip
no one at the time could
FIGURE 20: Lynn Conway in her office at PARC in 1983. (Photo
organization and Francois
visualize what I was actuby Margaret Moulton, Palo Alto Weekly)
Anceau founded the Circuits
ally doing, thus I needed no
Multi-Projets (CMP) service in
‘permission’ to do it and no
France, led in later years by
one was power-positioned
Bernard Courtois. Roger Van Overto stop it. As a corollary, few folks
and foundry services – triggering
straeten and Hugo De Man founded
later understood what had really
the rapid evolution of what is now
IMEC in Belgium, which provided
happened – much less who had done
called the “fabless/foundry” busia similar service (The ‘EUROCHIP’
it. Participants simply slid through
ness model, as a growing fraction of
service, formed in 1989, built upon
the resulting paradigm shift, and
the semiconductor industry.
these earlier efforts.)
ran with the results.
Some Reflections at the time
With many researchers exploitA concise history of these unfoldReflecting on all this at the time, I
ing MPC79, MPC580 and then MOSIS,
ing events is given in the book Fundthought back to my years at Columbia
and with hundreds of bright stuing a Revolution, published by the
where I had minored and read widely
dents emerging from universities
National Academy Press in 1999,
in cultural anthropology – being
and expecting access to silicon as
revealing the impact in academia
particularly intrigued by processes
they had experienced in school,
and industry of the Mead-Conway
underlying the diffusion of innocommercial “foundries” of varidesign methods, the textbook, the
vations. I realized that somewhere
ous forms started up to meet the
VLSI design courses and the MOSIS
along the way, having recalled Everitt
demand for manufacturing of indeinfrastructure [34].
Rogers’ early book on the topic [33],
pendently designed chips.
Ivan Sutherland’s challenge had
I had mounted a meta-level exploraThe first was SynMOS, founded
been met, inventive simplifications
tion in ‘applied anthropology’ that
by Larry Matheny and Bob Smith
being the key to success. Along the
ran in parallel with and guided my
in September 1980, serving as
way we’d secured “freedom of the
design of the VLSI design methods.
an agent/broker between design
silicon press,” and great novels were
In my early VLSI work this involved
groups and mask and fab firms.
now being written.
the deliberate selection, structuring
Building on the knowledge generAlong with the thrusts in perand encoding of the knowledge so
ated by MCP79 and MPC580, VTI
sonal computing at PARC and in
as to have a good ‘impedance match’
soon offered similar services, and
the Valley beyond, and the vigorwith the culture of the targeted
by mid 1982 a special issue of VLSI
ous entrepreneurial engineering
recipient communities, and with the
Design Magazine identified 38 such
culture they propagated, these
simplification of that knowledge by
companies; some were fabless firms
collective events within ten years
creation and adoption of unifying
such as SynMOS and VTI, while
spelled doom for the domineering
open standards.
others were front-offices to existing
IBM of old. What a dramatic reverBy the time of MPC79, this metafab firms.
sal of our mutual fortunes since
level thrust shifted into enhancing
Everything really took off as venthat terrible time in 1968 when
the noticeability of the significance
ture capital firms funded scores of
I was fired by IBM – a firing that
of the new knowledge via dramatic
entrepreneurial startups of VLSI
could have shattered my life back
visible artifacts, the rapid diffusion
design companies, EDA companies
in those days.
28
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IEEE SOLID-STATE CIRCUITS MAGAZINE
On to New Things
By 1981, the VLSI work was well on
its way. Bert thought it time to move
on, and I founded the Knowledge
Systems Area at PARC to explore
artificial intelligence and collaboration technology.
Even so, I was often asked to
speak about VLSI. I gave the opening
talk at the 2nd Caltech Conference
on VLSI in 1981, describing the interactive meta-level research methods
I had used to generate, test, validate
and propagate the Mead-Conway
methods [28], [35], [36]. I also keynoted IEEE Compcon Spring 1983
and the ACM/IEEE Design Automation Conference in 1984. Although
reported to have given outstanding
talks, as a still somewhat-reserved
person I found these experiences
a bit intimidating, and as the VLSI
revolution went viral I pulled back
from additional public exposure.
In contrast, Mead was now in his
element. Armed with top-level connections and an outgoing personality, he soared toward fame as one
of the “founding fathers” of Silicon
Valley [37].
In 1983, Bob Cooper, Director of
DARPA, asked me to lead the planning of a new program called Strategic Computing. The agency wanted
to organize a coordinated research
program in artificial intelligence,
computer architecture, VLSI design
and QTA prototyping to create a
rich technology base for intelligent
weapons systems. Reflecting on my
father’s leadership role in the WWII
synthetic rubber program, I took the
mission, planning to return to PARC
after my tour. My secretive past was
never an issue; I was granted a Top
Secret clearance.
I’m proud of the resulting
Strategic Computing Plan, for it
quickly triggered over $100 million in funding for important computing research. I imagine it also
discouraged the Soviets, as they
watched brilliant U.S. researchers
reach far beyond what they could
hope to achieve behind the Iron
Curtain [38].
FIGURE 21: Mead and Conway receiving the Wetherill Medal at the Franklin Institute in 1985.
While at DARPA, I got a call from
Jim Duderstadt, Dean of Engineering at the University of Michigan,
asking if I’d consider a faculty
position along with a position in
his office as Associate Dean. I had
served on the Engineering College’s
National Advisory Committee, and
realized that it was a time of exciting expansion at the College. The
Valley had also become so career
and money obsessed I found it hard
to form good relationships there. In
1985, I took the job at Michigan and
“got a life”.
Confronting the Past,
Coming Out, Moving On
Thirteen years later, in late 1998, I
casually typed the word “superscalar” into an internet search and up
popped: “ACS—The first superscalar computer?”
Professor Mark Smotherman at
Clemson University had stumbled
onto information about the old project, and theorized in his website
that ACS was indeed the first. This
had become a question of historical
interest, because of the success of
the Intel Pentiums and other superscalar microprocessors. Stunned,
I realized the story of my involvement would come out, and that I
needed to get out ahead of it.
I contacted Mark and gradually
revealed my role in the project. Fortunately, I had saved all my ACS documentation including the original
DIS report. I shared these with Mark
and pointed him to other project
veterans who might be able to find
additional documents; in July 1999
Mark organized an ACS reunion at
IBM Research, in Yorktown Heights,
to encourage this effort (see Fig. 22).
I also began posting information on
my website to quietly explain my
long-ago transition to my colleagues,
hoping times had changed and some
would understand.
Michael Hiltzik of the L. A. Times
had earlier interviewed me while
writing Dealers of Lightning, his
definitive book about Xerox PARC.
He became eager to report this further story, and his article “Through
the Gender Labyrinth” ran on
November 19, 2000 [39]. Since then
I have interacted with thousands of
other gender transitioners via the
internet – expanding my website’s
informational support as time went
along. My website, lynnconway.com,
has served as a beacon of hope for
transitioners all around the world,
and this work has given further
meaning to my life.
During the early 2000’s, Smotherman compiled a comprehensive
history of IBM-ACS in his website
with the help of many ACS vets [2].
In February 2010, the Computer
History Museum in Mountain view,
California, hosted a special event
to honor surviving veterans of the
forgotten project. Around that same
time I also received the IEEE Computer Society’s Computer Pioneer
Award, based in part on my work
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29
outfits in computing: IBM Advanced
Computing Systems in the 1960s
and Xerox PARC in the 1970s. Undeniably cool ideas beamed down to
researchers at those places, and
creative people pulled together to
really make things happen based on
those ideas.
Along the way, ACS pioneered the
superscalar computer architecture
so important today, and the PARC/
Caltech collaboration launched the
VLSI Revolution. What a thrill it has
been to watch our ideas become
reality, ideas that have changed the
world forever.
I’ve also experienced a very special personal closure: The VLSI revolution enabled my DIS invention
to finally come to life, to be implemented in silicon – and while I was
still around to see it happen.
What a ride it’s been!
Acknowledgements
FIGURE 22: ACS Reunion, July 29, 1999: (L-R) John Cocke, Fran Allen, Herb Schorr, and Lynn
Conway. (Photo by Mark Smotherman)
The VLSI Archive
When reflecting on the past with friends and family, we often use
photo albums to trigger shared memories – memories that bind us
together and reveal how we got to where we are.
However, what of our careers? Although the final products of our
work may remain, mementos of our adventures along the way are
often lost in the rush of events. Only too late we realize what we
should have saved.
But it was different for the VLSI revolution. Perhaps it was the
exciting visual artifacts, or the shared-sense that we were breaking
new ground. Whatever the reasons, many participants saved original treasures from that era – research notes, chips and chip photos,
even huge color check plots – storing them away for decades.
During the past few years members of the VLSI research team,
along with colleagues in academia and industry, have gathered up,
scanned and photographed many of those artifacts and posted them
online. A work in progress, the ‘VLSI Archive’ helps bring those
exciting days back to life [21], [43].
on dynamic instruction scheduling
(DIS) [40]. It felt wonderful to see
that work, done and then lost so
long ago, finally acknowledged.
30
fa l l 2 0 12
References
QR Code for the
“VLSI Archive”
QR Code for Lynn
Conway’s website
Finding Closure
In reviewing my story I am struck by
my good fortune of having worked
at two of the greatest research
IEEE SOLID-STATE CIRCUITS MAGAZINE
Many people named in these reflections played vital roles in the VLSI
design revolution; it was a thrill to
join them on this great adventure.
I especially want to acknowledge
and thank W. R. (Bert) Sutherland
[41], [42]. Without Bert’s wisdom and
guidance, the Mead-Conway revolution would never have happened.
[1] M. Smotherman and D. Spicer, “Historical
Reflections:
IBM’s
Single-Processor
Supercomputer Efforts – Insights on the
pioneering IBM Stretch and ACS projects”,
Communications of the ACM, vol. 53,
no. 12, pp.28–30, December 2010.
[2] M. Smotherman, “IBM Advanced Computing
Systems (ACS) — 1961 – 1969”, historical
reconstruction website, Clemson University. http://www.cs.clemson.edu/~mark/
acs.html
[3] L. Conway, “IBM-ACS: Reminiscences and
Lessons Learned from a 1960’s Supercomputer Project”; in: C. B. Jones, J. L.
Lloyd, (Eds.), Dependable and Historic
Computing: Essays Dedicated to Brian
Randell on the Occasion of his 75th
Birthday, Springer-Verlag, Berlin, 2011,
pp.185–224.
[4] L. Conway, B. Randell, D. Rozenberg, D.
Senzig, “Dynamic Instruction Scheduling,” ACS Memorandum, IBM-ACS, February 23, 1966.
[5] L. Conway, “Lynn Conway’s IBM-ACS
Archive”, lynnconway.com. http://ai.eecs.
umich.edu/people/conway/ACS/Archive/
ACSarchive.html
[6] H. Garfinkel, Studies in Ethnomethodology,
Prentice Hall, Englewood Cliffs, N.J., 1967.
[7] L. Conway, “The Computer Design Process:
A Proposed Plan for ACS”, ACS Memorandum, IBM-ACS, August 6, 1968.
[8] B. O. Evans, “The Ill Fated ACS Project”:
pages 27-28 in Evans’ memoir The Genesis
of the Mainframe, Wilhelm G. Spruth, ed.,
University of Leipzig, Department of computer science, June 2010.
[9] L. M. Terman, “MOSFET Memory Circuits”,
Invited Paper, Proceedings of the IEEE, vol.
59, no. 7, pp. 1044–1058, July 1971.
[10] G. E. Moore, “Cramming more components
onto integrated circuits”, Electronics, vol.
38, no. 5, pp. 114–117, April 19, 1965.
[11] R.F. Lyon, p.e.c., March 29, 2012.
[12] B. Hoeneisen and C. Mead, “Fundamental Limitations in Microelectronics-I.
MOS Technology,” Solid State Electronics,
vol. 15, pp. 819–829, 1972.
[13] R. Bassett, To the Digital Age: Research
Labs, Start-up Companies, and the Rise of
MOS Technology, Johns Hopkins University Press, Baltimore, 2002.
[14] R. K. Booher, “MOS GP Computer,” Proceedings of the Fall Joint Computer Conference,
AFIPS ‘68 (Fall, part I), San Francisco,
December 9-11, 1968, pp.877–889.
[15] L. Boysel and J. Murphy, “Four-phase LSI
logic offers new approach to computer
designer”, Computer Design, pp. 141–146,
April, 1970.
[16] F. Faggin, “The Making of the First
Microprocessor”, IEEE Solid-State Circuits
Magazine, vol. 1, no. 1, pp. 8–21, Winter
2009.
[17] R. Bower and R. Dill, “Insulated gate field
effect transistors fabricated using the
gate as source-drain mask”, Proceedings
of the Electron Devices Meeting 1966 International, Washington, DC, October 26–28,
1966, pp. 102–104.
[18] R. H. Dennard, F. H. Gaensslen, H. N.
Yu, L. Rideout, E. Bassous and A. R.
LeBlanc, “Design of Ion-Implanted MOSFET’S with Very Small Physical Dimensions”, IEEE Journal of Solid-State Circuits,
vol. SC-9, no. 5, pp. 256–268, October
1974.
[19] I. Sutherland, C. Mead and T. E. Everhart,
“Basic Limitations in Microcircuit Fabrication Technology”, ARPA Report R-1956ARPA, Published by Rand Corporation,
Santa Monica, CA, November 1976.
[20] I. Sutherland, “The Problem: How to build
digital electronic circuits from now to
1985”, Letter to W. R. Sutherland describing the challenges presented by advances
in microelectronics and proposing the
Xerox-PARC/Caltech collaboration, January 26, 1976.
[21] L. Conway, Ed., “The VLSI Archive: An online
archive of documents and artifacts from
the Mead-Conway VLSI design revolution”,
lynnconway.com. http://ai.eecs.umich.edu/
people/conway/VLSI/VLSIarchive.html
[22] I. Sutherland and C. Mead, “Microelectronics and Computer Science”, Scientific
American, pp. 210-228, November 1977.
[23] C. Mead and L. Conway, Introduction to
VLSI Systems, Xerox PARC, laser-printed
prepublication versions: Chapters 1–3,
October 1977; Chapters 1–5, February
1978; Chapters 1–9, July 1978.
[24] C. Mead and L. Conway, Introduction to
VLSI Systems, Addison-Wesley, Reading,
MA, 1980.
[25] R. Hon and C. Sequin, A Guide to LSI Implementation, Xerox PARC Technical Report,
1st Ed., September 1978; 2nd Ed., January
1980.
[26] L. Conway, The M.I.T.’78 VLSI System
Design Course: A Guidebook for the
Instructor of VLSI System Design, Xerox
PARC, August 12, 1979.
[27] L. Conway, A. Bell and M.E. Newell, “MPC79:
The Large-Scale Demonstration of a New
Way to Create Systems in Silicon”, Lambda,
the Magazine of VLSI Design, vol.1, no. 2,
pp. 10-19, Second Quarter 1980.
[28] L. Conway, “The MPC Adventures: Experiences with the Generation of VLSI Design
and Implementation Methodologies”,
Xerox PARC Technical Report VLSI-81-2,
January 1981.
[29] T. Kuhn, The Structure of Scientific Revolutions, 2nd Ed., University of Chicago
Press, Chicago, 1970.
[30] D. Fairbairn and J. Rowson, “From the
Editors”, Lambda, the Magazine of VLSI
Design, vol. 1, no. 1, pp. 2–3, First Quarter, 1980.
[31] MOSIS, “The MOSIS Service – More than
50,000 designs in over 25 years of operation”, mosis.com.
[32] M. Marshall, L. Waller, and H. Wolff,
“The 1981 Achievement Award: For optimal VLSI design efforts, Mead and Conway have fused device fabrication and
system-level architecture”, Electronics,
vol. 54, no. 21, pp. 102–105, October 20,
1981.
[33] E. M. Rogers, Diffusion of innovations, Free
Press, New York, 1962.
[34] Computer Science and Telecommunications Board, National Research Council,
Funding a Revolution: Government Support for Computing Research, National
Academy Press, Washington, DC, 1999,
pp. 113–122.
[35] M. Stefik and L. Conway, “Towards the
Principled Engineering of Knowledge”,
AI Magazine, vol. 3:3, pp. 4–16, Summer
1982.
[36] L. Conway, “The Design of VLSI Design
Methods”, Proc. of ESSCIRC’82: Eighth
European Solid-State Circuits Conference, Brussels, September 22-24, 1982,
pp. 106–117.
[37] M. Cassidy, “Chip inventors getting their
due at Hall of Fame induction”, San Jose
Mercury, April 30, 2009.
[38] D. B. Davis, “Assessing the Strategic Computing Initiative”, High Technology, vol.5,
no.4, pp. 41–49, April 1985
[39] M. A. Hiltzik, “Through the Gender Labyrinth: How a bright boy with a penchant
for tinkering grew up to be one of the top
women in her high-tech field”, Los Angeles
Times Magazine (Cover Story), pp. 12–17,
Sunday, November 19, 2000.
[40] IEEE Computer Society, “Lynn Conway,
2009 Computer Pioneer Award Recipient,”
January, 2010. http://www.computer.org/
portal/web/awards/conway
[41] W. R. (Bert) Sutherland, “Management
of Industrial Research: Exploring the
Unknown Technical Future”, Perspective
Series 2008-7, Sun Labs, July 2008.
[42] W. R. (Bert) Sutherland, “Faith, Funds, &
Fate: Prerequisites for the development
and transfer of new technology”, Presentation at the celebration of the 40th
anniversary of USC-ISI, Marina del Rey,
California, April 26, 2012.
[43] L. Conway, “The VLSI Archive”, Electronic
Design News, June 3, 2009. http://edagraffiti.com/?p=101
About the Author
Lynn Conway ([email protected]) is
Professor of Electrical Engineering
and Computer Science, Emerita, at
the University of Michigan.
After earning her B.S. and M.S.E.E.
from Columbia University’s School
of Engineering and Applied Science
in 1962 and 1963, Lynn joined IBM
Research. There she made foundational contributions to computer
architecture, including the invention
of multiple-out-of-order dynamic
instruction scheduling (DIS). Fired
by IBM as she underwent her gender
transition in 1968, Lynn started her
career over again in a new identity,
soon becoming a computer architect
at Memorex Corporation.
Joining Xerox’s Palo Alto Research
Center in 1973, she invented scalable MOS design rules and highly
simplified methods for silicon chip
design, conceived of and became
principal author of the famous MeadConway text, and pioneered at M.I.T.
the intensive university course that
taught these methods – thereby
launching a world-wide revolution in
VLSI system design in the late 1970’s.
Lynn also invented the internet-based, rapid-chip-prototyping
infrastructure institutionalized by
DARPA as the MOSIS system – supporting the rapid development of
thousands of chip designs, and
leading to many Silicon Valley startups in the 1980’s.
After serving as Assistant Director for Strategic Computing at DARPA
from 1983-85, Lynn joined the University of Michigan as Professor of
EECS and Associate Dean of Engineering, where she continued her
distinguished career. Now retired,
she lives with her engineer husband
Charlie on their 23 acre homestead
in rural Michigan. They’ve been
together for 25 years.
An IEEE Fellow, Lynn holds five
U.S. Patents and has received a
number of professional honors for
her work, including the Electronics
Award for Achievement (1981), the
Pender Award, University of Pennsylvania (1984), the Wetherill Medal
of the Franklin Institute (1985), election to the National Academy of
Engineering (1989), and the Computer Pioneer Award of the IEEE
Computer Society (2009).
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31
A Paradigm Shift Was
Happening All Around Us
T
Chuck House
hankfully, Ridley Scott’s brilliant Super Bowl ad, proclaiming that 1984 won’t
be like 1984, heralded a Golden Age of Electronics instead of George Orwell’s
dyspeptic scenario. Apple’s Macintosh debuted, Hewlett-Packard and its new
LaserJet printer set record sales and profits for Silicon Valley companies, and
I met Lynn Conway when we both joined the IEEE Spectrum Advisory Board.
Although Conway was a bit shy and had held back from the limelight, I already “knew”
her. As HP’s Corporate Engineering Director, my job was to “know” the Valley. Operating
a prototype Macintosh six months prior to introduction, I’d sparked Tom Whitney’s Summerhill Partners’ angel round that was the initial funding for Aldus Corporation and Pagemaker. I‘d compared views with Xerox PARC’s Warren Teitleman, both a Caltech classmate
and a neighbor (with an Alto and then a Dorado by his home swimming pool). Warren and I
had both known Carver Mead for 25 years. Mead was my senior advisor, urging me to join
HP in 1962. By 1975, Mead and Conway were collaborating at PARC.
But I really knew Conway because of “the book” and the subsequent Electronics cover
Award of Achievement in October 1981 [1]. Electronics, perhaps the most prestigious trade
magazine at that time, had honored Intel’s founders, Bob Noyce and Gordon Moore, in their
inaugural award in 1974; they’d singled out my Logic State Analyzers in 1977 (Figure 1) [2].
I’d joked with Mead that this was the first time I’d beaten him; he reminded me that he’d
done the calculations for Gordon and even facetiously said the name “Moore’s Law” could
Digital Object Identifier 10.1109/MSSC.2012.2215759
Date of publication: 24 December 2012
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have been “Mead’s Law”—he winked
that he’d “won twice.”
The book—Introduction to VLSI
Systems [3]—was a landmark. Simplistic histories of Silicon Valley and the
Personal Computer Revolution focus
on the hobbyist Homebrew Computer Club, the youthful Steves (Jobs
and Wozniak), with a Gary Kildall
vs. Bill Gates footnote. But the paradigm shift that enabled Apple’s and
Microsoft’s emergence had vital antecedents that have largely remained
obscure. Conway’s role there, while
crucial, has often seemed “behind
the scenes” to outside observers.
The second annual IEEE Workshop on Microprocessors (now
called the Asilomar Microcomputer Workshop, or AMW) was held
Wednesday–Friday, April 28-30,
1976, near Monterey, California
[4]. Arriving the night before from
HP Colorado Springs, I knew few
of the ninety-four attendees. Espying Carver Mead, my college senior
advisor, across the room in the buffet line, I joined him and six other
ex-students at a dinner table. With a
glazed look, Carver intoned that he
recalled each of us.
AMW was the most successful of four private invitation IEEE
design workshops that arose to discuss these presumptuously named
‘microcomputer’ integrated circuits.
Authoring the Electronics May, 1975
article: “Engineering in the Data
Domain Calls for a New Kind of
Digital Instrument” got me invited
to AMW’s 2nd workshop to describe
the philosophy behind HP’s new
Logic State Analyzers, which were
tools analogous to oscilloscopes to
give digital designers insight for
using these complicated chips [5].
My Wednesday evening talk
described tools that enabled a very
different design methodology—
Algorithmic State Machine design
(ASM)—using Lyapunov state-variable mathematics, and derivative
techniques pioneered at HP by Chris
Clare and Dave Cochran for the
spectacularly successful handheld
scientific calculators (e.g., HP 35) [6].
My point: circuit design was no
longer an element-by-element issue,
but a question of “state flow” at lots
of nodes—the sequential “words” of
registers rather than the voltages of
device pins. In effect, it argued that
electronic voltages, whether analogic
or switched, would “lose out” to software instructions, and “data states.”
Systems would be designed and analyzed for proper state sequencing
rather than analogic signal distortion or digital switching times.
I’d have done fine if I had left
the See’s Candy POS terminal example out of the discussion, but I got
carried away with case studies we
knew from selling Logic Analyzers
that were alien to this sophisticated
assemblage. Four-bit microprocessors—the Intel 4040, for example—
were “toys” to this group, and I
didn’t know any better. In response
to questions, though, I was able to
describe our dedicated 8080 “personality module” for a forthcoming
logic analyzer, just as an HP colleague tried to “shush” me.
When I finished, Carver was the
first person to the podium, exclaiming, “NOW I REMEMBER YOU.”
He excitedly explained that our
concepts of data domain (versus
the traditional time domain or frequency domain methods taught to
all electronic engineers) fit perfectly
with some work he was doing. He
asked to borrow my transparency
foils, and proceeded to sketch something he called “the tall thin man”
methodology for transistor layout.
The room was mesmerized.
I’d been lucky at CalTech to be in
Richard Feynman’s first freshman
lectures with handwritten notes; this
scene repeated at AMW2 as people
asked how they could get copies of
these new ideas. Mead said that he
and Lynn Conway over at Xerox PARC
were preparing some notes, which he
might send electronically. Electronically? Yes, he said, if you have access
to an ARPANET node. Some in the
room nodded; others looked quizzical. The electric atmosphere of the
evening is still etched in memory.
FIGURE 1: Electronics 1977 cover, with the
Award of Achievement for Logic Analyzers.
(Courtesy of Chuck House.)
I’d already seen the power
of pre-publication books. Clare’s
insightful ASM methodology text,
Designing Logic Systems Using State
Machines, swept through the HP
design community (Figure 2) [7].
Stanford’s electrical engineering
department was not so sanguine,
however, canceling Clare’s course
in 1974, saying that “it is a little bit
too unconventional” [8]. Stanford
preferred Quine-McCluskey minimization techniques. Fittingly, Mead’s
FIGURE 2: Chris Clare’s book: ­designing
logic systems using state machines.
(Courtesy of Chuck House.)
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FIGURE 3: Computer-controlled plasma
system at HP’s ICPL. (Courtesy of HewlettPackard [12].)
Caltech colleague Ivan Sutherland
prepared a Scientific American article (1977) [9] about the challenge
microelectronics posed to computing theory and practice, noting
that since most of a chip’s surface
was occupied by “wires” (conducting pathways) rather than “components” (transistors), decades of
minimization theory in logic design
had become irrelevant [10].
AMW would “make history”—as
industry veteran Ted Laliotis noted
thirty years later: “the intentional
lack of written proceedings and the
exclusion of general press representatives was perhaps the most distinctive characteristic of AMW that
made it so special and successful.
This encouraged the scientists and
engineers who were at the cutting
edge of the technology, the movers
and shakers that shaped Silicon Valley, the designers of the next generation microprocessors, to discuss
and debate freely the various issues
facing microprocessors. In fact,
many features, or lack of, were born
during the discussions and debates
at AMW. We often referred to AMW
FIGURE 4: Fabrication processing line at
HP’s ICPL. (Courtesy of Pat Castro.)
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and its attendees as the bowels of
Silicon Valley...” [11].
AMW would feature many key
contributors to this new paradigm
during the first six years. Intel’s
Sterling Hou extolled the Intellec 8
for developing 4004 and 8008 code
at AMW1; he shared the stage with
me at AMW2, describing the Intellec
MDS to assist Intel 8080 microcomputer designers. The “toy” Intel 4004
had 2,300 transistors and a clock
speed less than 1 MHz—its largest usage by 1976 was in a grocery
clerking tool built by MSI Data of
Costa Mesa for Alpha Beta Grocery
Stores on a whim.
Moore’s Law from 1965 predicted
a bright future, but in spring 1976,
this august body was still profoundly skeptical. No one would
have believed that a Pentium 4
chip with a billion transistors and
a gigahertz clock speed would exist
twenty-five years later, let alone sell
for a thousand dollars.
An uneventful AMW3 was followed by AMW4 in 1978, which
featured Charlie Bass, Dave Farber, Gary Kildall, Bernie Peuto, Ken
Bowles and Len Shustek among others. A strong Berkeley contingent
showed up for AMW5, with Alvin
Despain as Chair, and Dave Patterson, Carlo Séquin and Dave Hodges
presenting alongside Nick Treddennick (Motorola 68000), and Intel’s
Ted Hoff.
The real excitement at AMW5,
however, was the last session on
Friday, May 25, 1979, entitled “New
Directions and Architectures.” Forest Baskett, newly arriving at Stanford from Xerox PARC, reviewed the
extraordinary results of nineteen
projects in Lynn Conway’s MPC78
course at MIT. Conway had written
that: “I sent the final student design
files to PARC via the ARPANET on
December 6, 1978. Lyon and Bell
then merged the 19 projects into a
single multi-project chip CIF file,
converted it to Mann PG format and
had masks made by Micro Mask….
In this first phase of an important
collaboration with Pat Castro at
IEEE SOLID-STATE CIRCUITS MAGAZINE
Hewlett-Packard, wafers were fabricated at her Integrated Circuit
Processing Lab (ICPL) at nearby
HP Research using a 6-micron
(m = 3 nm) silicon-gate NMOS process (Figures 3, 4). Everything went
off without a hitch, and the packaged chips were shipped back to
M.I.T. on January 18, 1979” [13]. I’ve
wondered why Conway hadn’t presented the work; colleagues recall
just that AMW “was invite only.”
Conway next fashioned an even
more ambitious multi-university
program—MPC79. The first session
of AMW6 featured her bold initiative as “Special Purpose Building
Blocks,” chaired Wednesday April
23, 1980 by Carlo Séquin, described
by Carver Mead, Jim Clark, Glenn
Krasner and Dick Lyon. The MPC79
chip set contained 82 design projects from 124 designers at 12 universities, spread across 12 die-types
on two wafer sets. Astoundingly,
turnaround time from design cutoff to distribution of packaged
chips was only 29 days, again using
Hewlett-Packard’s Palo Alto research
fabrication facility. Conway’s proud
assessment: “We’d done the impossible: demonstrating that system
designers could work directly in
VLSI and quickly obtain prototypes
at a cost in time and money equivalent to using off-the-shelf TTL” [14].
Significant chips were built in the
MPC79 “run,” including Jim Clark’s
Geometry Engine that spawned Silicon Graphics Corporation. Substantial interest surfaced at Caltech, MIT,
Berkeley, and Stanford—enough
that Pat Castro and her colleagues at
HP reluctantly had to “pull the plug”
on opening their facility to universities, citing their industrial priority.
Castro says today: “Jim Gibbons at
Stanford was really offended when
I told him ‘no’.” Gibbons acknowledges that this action stimulated
his decision to build Stanford’s CIS
(Computer Integrated Systems) lab;
he further states that Lynn Conway,
from his perspective, was the singular force behind the entire foundry
development that emerged.
FIGURE 5: Merrill Brooksby, HP Corporate
Design Aids Center director. (Courtesy of
Hewlett-Packard [15].)
Clearly a new design paradigm
had emerged—rendering discrete
circuit design as irrelevant as QuineMcCluskey
minimization
rules.
Importantly, imaginative support
in terms of infrastructure and idea
dissemination proved as valuable as
the concepts, tools, and chips. “The
electronic book” and the “foundry”
were both prescient and necessary,
providing momentum and proof
points.
FIGURE 6: Patricia Castro, HP ICPL director,
in 1977. (Courtesy of Hewlett-Packard [16].)
Castro, the first woman engineer
hired by Fairchild Semiconductor,
built the world’s first three-inch
wafer fab facility for HP in 1975, pioneering a way to prototype multiple
processes and designs. Her supervisor, Merrill Brooksby (Figure 5), who
had built HP’s first IC fabrication
facility in 1967, supported Castro’s
leadership for this shop because of
the breadth of HP’s scientific instrumentation requirements. The dedication and willingness of Castro
(Figure 6) to work with universities
was vital to produce the resultant
student-designed wire-bonded chips
in Conway’s MPC program.
The resultant methods would
convulse an industry—but fame
would accrue to the people who
built the products using the chips,
rather than to those who did the
incredible breakthroughs to create the methods and even the chips
themselves.
Paradigm shifts seem to be universally resisted—this one was no
different. Virtually all mainframe
and
minicomputer
companies
(ironically, even Intel leadership),
struggled to comprehend. HewlettPackard’s
wildly
decentralized
organization allowed some individuals—Merrill Brooksby and Pat
Castro in the IC lab; Chris Clare in
calculators; and my team in the logic
test business—to chase the new paradigm. But even at HP, conventional
wisdom prevailed in most divisions.
Moreover, Castro’s lab was “taken
out of commission” for such industry-university experiments, when
the volume of processing requests
from Stanford, CalTech, and Berkeley among others escalated on the
heels of MPC 79.
It took nearly another decade
before commercialized EDA design
tools and silicon foundries emerged
to support industrial designers
in the way that Conway’s MPC79
sponsored. In retrospect, Conway’s
dedication and insights irrevocably
altered extant companies while fueling a worldwide digital electronics
cornucopia. We are all beneficiaries.
References
[1] Waller, Marshall L., and H. Wolff, “The 1981
Achievement Award: For optimal VLSI design
efforts, Mead and Conway have fused device
fabrication and system-level architecture”,
Electronics, (54:21), October 20, 1981, cover
and pp. 102–105.
[2] The 1977 Electronics Award of Achievement,”
Electronics, (50:22), October 27, 1977.
[3] Mead, Carver and Lynn Conway, “Introduction
to VLSI Systems,” Addison-Wesley, Reading, MA,
1980.
[4] Agendas for the first thirty years are at
http://www.bswd.com/AMW-35thWorkshop
Booklet-SingleSidedVersion.pdf.
[5] House, Charles H., “Engineering in the
Data Domain calls for a new kind of digital
instrument,” Electronics, (48:9), May 1, 1975,
pp. 75–81.
[6] On April 14, 2009, the IEEE Milestone in
Electrical Engineering award for the HP 35
was presented by the outgoing president
of IEEE, Dr. Lewis Terman. Terman was one
of Mead’s seven ex-students at the 1976
Asilomar dinner table.
[7] C. Clare, Designing Logic Systems Using
State Machines, McGraw-Hill, NY, 1973.
[8] C. House and R. Price, The HP Phenomenon,
Stanford University Press, 2009, p. 260.
[9] Sutherland, Ivan and Carver Mead,
“Microelectronics and Computer Science”,
Scientific American, November 1977,
pp. 210–228.
[10] Conway, Lynn, “IBM-ACS: Reminiscences
and Lessons Learned from a 1960’s
Supercomputer Project”; in: C. B. Jones,
J. L. Lloyd, (Eds.), Dependable and Historic
Computing: Essays Dedicated to Brian
Randell on the Occasion of his 75th Birthday,
Springer-Verlag, Berlin, 2011, pp.185–224.
[11] T. Laliotis, Commemorative Booklet
for the 35th Asilomar Microcomputer
Workshop, April 15–17, 2009.
[12] Hewlett-Packard Journal, June 1981,
32:6, p. 30.
[13] Conway, Ibid.
[14] Conway, Ibid.
[15] Hewlett-Packard Journal, Ibid.
[16] Hewlett-Packard Reporter, November
1977, p. 34
About the Author
Chuck House, an IEEE and ACM
Fellow, Director of InnovaScapes
Institute, was recently Chancellor
of Cogswell College, Sunnyvale, CA,
and Executive Director of Media X
@ Stanford University after a long
career at Hewlett-Packard and Intel.
Author of The HP Phenomenon, his
work has been honored by CNN
(Top 25 products of past 25 years),
Smithsonian (200 Wizards of Computing), Electronics Design (Top 50
products of 20th century), and the
HP Medal of Defiance. A past vice
president of IEEE, he also was an
ACM president.
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35
Carlo H. Séquin
Witnessing
the Birth of
VLSI Design
I
have had several lucky breaks in my
career. One of them was the opportunity to be immersed in the emergence of
VLSI technology and its associated design
methodology. I got my Ph.D. in Experimental Physics from the University of Basel, Switzerland,
in 1969. My first job was with Bell Telephone Laboratories in Murray Hill, New Jersey. Because of my thesis,
in which I studied the behavior of Interface States in
Metal-Oxide-Semiconductor Field-Effect Transistors, I
was placed into Lab 225, which was engaged in building
solid state imaging devices based on the brand new CCD
(Charge-Coupled Device) technology, which had been
conceived there a few months earlier. When I arrived,
the group with Mike Tompsett and Gil Amelio had just
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demonstrated a CCD sensor array with 8 by 8 pixels.
Since I have been enamored with geometry ever since
high-school, I jumped to the opportunity to design the
layouts of much larger imaging arrays, first with 128 by
128 pixels, and eventually (in 1973) with two interlaced
fields of 256 scan lines, which was compatible with the
American broadcast TV format. The latter device was
way larger than any other IC chips of that time: It had ¾
of a million MOS electrodes placed in a rectangle measuring ½ inch by 5/8 of an inch (Figure 1).
The success of this chip brought me a job offer from
the University of California. In 1976 I went to Berkeley as
visiting lecturer, and in 1977 I became a tenured faculty
member in the Computer Science Division in the EECS
department. Although my background was mostly on the
EE side, I was hired into the CS Division because there
was an urgent need for expansion. Tom Everhart, then
chair of EECS, explained to me that this would put me in
1943-0582/12/$31.00©2012IEEE
graphics-oriented computer stations were readily used
by everybody; prototypes of powerful bit-mapped display panels implied a technological revolution just
around the corner; lively discussions were taking place
all day long in lounge-like settings furnished with beanbags. Overall it felt like I could obtain a glimpse of what
the future would soon bring. But most of all, it was the
charisma and enthusiasm of Lynn Conway that drew
me into this environment. I was excited by the visionary plan of establishing some simple and logical ground
rules for the design of integrated circuits, which could
readily be taught to a whole class of smart students.
Up to this point, my experience with the design of IC
chips was more like a magical art—learned by osmosis, slowly transcending from a few old masters to their
devoted pupils, who would gradually absorb the mysterious ways in which these devices were brought to
life. (I am exaggerating only a little bit.)
The new approach was to extend the system of
nested abstractions that was already used in the
design of binary logic circuits (e.g., using TTL logic
gates) upwards and downwards, so that the abstractions would cover the whole range from the architectural systems level down to the layout of the
gates of individual transistors. The technology
of choice was the rapidly growing n-MOS process that had become stable and well controlled
in the early 1970s. The devices were in principle
quite simple: a source and a drain region in the
silicon layer, separated by a channel that could be
turned on and off by the voltage of a metal gate placed
on top of the thin isolating oxide layer. This geometry
could be represented succinctly by a red line (representing the gate electrode) crossing a green line (representing the silicon channel). Suddenly the layout of
an integrated circuit was captured by simple and clean
a unique and
important position. While
I already had several acquaintances and friends
on the EE side, it would be important for my career to
establish close working relations with my CS colleagues.
Having good connections in both Divisions should then
allow me to help meld together those
two Divisions, which at that time
were not very congenial competitors. Naïvely I accepted this mission
to bring those two factions together.
Fortunately I got some unexpected
help in this audacious task.
As soon as I was an official faculty
member at Berkeley, and no longer a
Bell Labs employee, I was contacted
by Lynn Conway at Xerox PARC. She
invited me to be a consultant in a
project to develop a new methodology for the design of large and
complex integrated circuits. After a
single visit to Xerox PARC, I enthusiastically accepted this additional job
offer. The decision was made easy FIGURE 1: The first solid-state image sensor compatible with the American broadcast TV
by what I saw at that Lab: Interactive format.
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Most of all, though, it was the charisma
and enthusiasm of Lynn Conway that drew
me into this environment.
geometrical diagrams. This had
tremendous appeal for me!
Of course, the method was a little more complicated than outlined
above. To make it useful, quite a few
details had to be figured out. But
these challenges were exactly of the
nature that had rendered geometry
my favorite subject in high school.
So for the next several years I routinely spent one day of every week
at Xerox PARC; and this was typically the highlight of the week. It
was wonderful to have “one day off,”
or at least one day that was quite
different from an ordinary “school
day.” I worked with Lynn Conway
and her team to put together concrete guidelines for the new way of
thinking about integrated systems.
At several occasions during my consulting days at Xerox PARC, I also met
Carver Mead and often engaged in
heated discussions of what it really
meant “to map the systems architecture onto the 2-dimensional space
of a chip” or how to unambiguously
specify “a linear array of n cells,
of size s, separated by distance d.”
At other times I would engage in
brain-storming sessions of how to
use a computer program to turn
the Boolean specifications of a programmable logic array (PLA) into
an array of green and red line elements crossing at right angles, thus
capturing the basic arrangements
of a compact n-MOS realization of
circuitry that would perform the
specified function.
However, for small PLAs with
only a handful of inputs and outputs, the generated layouts were not
competitive in compactness with
the beautiful, handcrafted layouts
done by expert IC layout designers. Therefore many engineers in
Silicon Valley, as well as some of my
colleagues in academia, dismissed
those early results as “toy examples” of no real significance. Also,
the sometimes overly enthusiastic
statements by Carver Mead, claiming that a proper mapping of the
FIGURE 2: The first functional RISC chip, built by graduate students at U.C. Berkeley.
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system architecture onto the surface
of a silicon wafer would improve
layout density by one or two orders
of magnitude, gave ammunition to
people who were skeptical of those
early efforts. But neither Carver nor
Lynn let themselves be discouraged
by such negative evaluations. They
responded by decisively moving
along the envisioned path, clarifying one issue after another, and
solving problems one at a time as
they arose.
Carver Mead saw clearly that
Moore’s Law, which predicted a doubling of chip complexity every 18
to 24 months, would soon allow us
to place systems on a single chip
with tens or hundreds of thousands
of individual switching elements;
those systems could no longer be
designed, drawn, and checked by
the traditional “manual” methods.
Thus we were rapidly approaching
a “complexity barrier” in the design
of integrated circuits. And indeed, it
was not too long before some computer chips had logic arrays with
several dozens of inputs, on the
order of a hundred outputs, and
more than 200 min-terms. Now the
computer generated layouts could
produce working solutions that
could no longer be obtained with
manual layout.
I eagerly absorbed those ideas
and developments and brought
them back to Berkeley. My personal, special graduate course, CS
248, was aimed at Modular MOS LSI
Design. This gave me an opportunity to try out emerging new ideas
and carry that feedback back to
Xerox PARC. By 1978 Lynn Conway
had launched a full-blown effort to
capture all the new design concepts
in a textbook, and she was making available emerging chapters to
whoever was willing to teach such a
design course. So this was different
of the normal model of developing a
text book, where notes accumulated
over several offerings of a particular course eventually got distilled
into a refined text that documented
all the good ideas that had survived
world-wide
this evolutionary process. In this
case, ideas developed in brainstorming sessions at Xerox PARC
were used to define various lectures
and set the overall itinerary of my
LSI Design course.
In addition the new methods were
also applied in joint research with
Dave Patterson. Realizing that the
real estate on an IC chip was a limited, precious resource, we carefully
evaluated what circuitry and what
functions would deliver the most
“bang” per square millimeter for
making a powerful, general-purpose
microprocessor. We then applied the
new structured layout methodology
for n-MOS circuitry. The result was
the RISC (Reduced Instruction Set
Computer) principle, and by 1981
our students had realized the first
working single-chip RISC (Figure 2).
Gradually the LSI chip-building
activities at Berkeley expanded. For
the more ambitious follow-on projects, SOAR (Smalltalk On A RISC) and
SPUR (Symbolic Processing Using
RISCs), we needed the help and
expertise of our colleagues on the
EE side, in particular, David Hodges,
Alberto Sangiovanni, and Richard
Newton. We also needed better and
easier-to-use CAD tools to lay out
those complicated chips in symbolic sticks format, convert them
into compact layouts without design
rule violations, and finally verify
the proper logic operation and
timing behavior of those circuits.
John Ousterhout in the CS Division
played a major role in this domain;
he made a personal commitment to
develop a new IC-CAD tool for every
new computer chip that this EECSteam designed.
This activity attracted a lot of
attention and drew in ever bigger
groups of students. Doing IC layout with a user-friendly CAD tool
was a lot of fun (almost like today’s
video games) and it gave the students a true sense of achievement.
By the early 1980s seven faculty and
more than 30 students from both
EE and CS were working together
to develop new powerful IC CAD
The IC-CAD effort at UC Berkeley was the best one
in academia orld-wide; this was brought about
by a close collaboration of research groups from
both EE and CS.
tools and designing computer chips
that gained attention and appreciation in Silicon Valley as well as in
academia. Very soon there was no
doubt that the IC-CAD effort at UC
Berkeley was the best one in academia world-wide, and that this was
mostly brought about by a close
collaboration of research groups
from both EE and CS. Before too
long, other schools, like MIT and
Stanford, took notice and started to
emulate the Berkeley EE+CS collaborative model.
In summary, thanks to the outreach of Lynn Conway, thanks to
her enthusiasm and support, and
thanks to the exciting ideas emerging in VLSI Design, I was able to
start an activity at Berkeley that
brought together EE and CS and thus
allowed me to make good on the
mission originally assigned to me
by Tom Everhart. By the early 1980s
the harsh boundaries between the
two Divisions had mostly disappeared,
many
interdisciplinary
research groups had formed, and
students were freely transitioning
from one side to the other. As an
example, Manolis Katevenis first did
his MS degree under David Sakrison
on the EE side and then came to CS
Division to do his Ph.D. with me and
Dave Patterson; he became the key
designer of the successful RISC chip.
About the Author
Carlo H. Séquin is a professor of
Computer Science at the University
of California, Berkeley. He received
his Ph.D. degree in experimental
physics from the University of Basel,
Switzerland, in 1969. From 1970 till
1976 he worked at Bell Telephone
Laboratories, Murray Hill, NJ, on the
design and investigation of ChargeCoupled Devices for imaging and
signal processing applications. In
1977 he joined the faculty in the
EECS Department at Berkeley. He
started out by teaching courses on
the subject of very large-scale integrated (VLSI) circuits, thereby trying to build a bridge between the CS
division and the EE faculty. In the
early 1980’s, jointly with D. Patterson he introduced the “RISC” concept
to the world of microcomputers. He
was head of the Computer Science
Division from 1980 till 1983. During his tenure at Berkeley Séquin has
directed the research of 26 Ph.D. students and has supervised 77 graduate students in the completion their
Masters Theses.
For the last two decades Séquin’s
work has been focused on computer graphics, geometric modeling,
mathematical visualizations, and
on the development of computer
aided design (CAD) tools for circuit
designers, architects, mechanical
engineers, and more recently also
for artists creating abstract geometric art. His collaboration with sculptor Brent Collins of Gower, MO, and
with bronze artist Steve Reinmuth
of Eugene, OR, has resulted in largescale bronze sculptures that are
installed in the lobby of Sutardja
Dai Hall at U.C. Berkeley and in the
courtyard of the H&R Block headquarters building in Kansas City.
Dr. Séquin is a Fellow of the
ACM, a Fellow of the IEEE, and has
been elected to the Swiss Academy
of Engineering Sciences. He has
received the IEEE Technical Achievement Award for contributions to
the development of computer-aided
design tools, the Diane S. McEntyre
Award for Excellence in Teaching,
and an Outstanding Service Award
from the University of California for
Exceptional Leadership in the Conception, Design and Realization of
Soda Hall.
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39
“Covering”:
How we missed the inside-story
of the VLSI revolution.
Ken Shepard
I
’m delighted to comment on Lynn Conway’s outstanding piece “Reminiscences
of the VLSI Revolution: How a series of
failures triggered a paradigm shift in digital design.” What we often forget in engineering and science is that innovation and technological
progress happen because of actions of people, people
who have personalities, lives, and life stories that influence them and are influenced by those around them.
Lynn’s story provides a case in point.
I’m writing this from a “younger” perspective having known Lynn personally for only about five years
(but having been influenced by her work for more
than 25 years). Lynn’s story and work have touched me
personally on many levels, as a student, as a Columbia
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faculty member, as a VLSI educator, as a former IBM
employee (I worked for five years at IBM Research after
completing my Ph.D., many years after Lynn left), and as
a gay man. I’d like to provide commentary from each of
these perspectives.
As an electrical engineering student at Princeton from
1984–1987, I was first influenced by Lynn through the
famous Mead and Conway text book. I graduated from
Princeton in three years (a deal with my parents—they
would pay for me to go to Princeton if I worked hard
and completed my degree in three years—a good deal,
indeed) but this left me “skipping” a lot of courses that
I knew I could teach myself and signing up for the more
advanced courses.
This trick worked well for me except when I wanted
to sign up for EECS 420 (VLSI Systems) in my senior
year, a new course based on the new Mead and Conway
textbook. I had skipped the required course in digital
1943-0582/12/$31.00©2012IEEE
logic because I knew that I could
just teach myself the material over
the summer, and the professor who
taught the course at the time would
not let me in because I did not have
the prerequisite. I was determined
to learn the material myself, which
I did by reading the Mead and Conway text cover-to-cover. I feel a certain vindication since I now teach
VLSI Circuits at Columbia to over
45 students every fall. Wow, that
was a good book.
As a Columbia faculty member, I am very proud to count Lynn
among our great alumnae. Columbia’s engineering school and electrical engineering program have a
very influential history and Columbia’s faculty continue to innovate
and train outstanding students. The
size of our program is small and I
often feel that we are really underappreciated when compared with
larger schools such as MIT, Stanford,
or Cornell. Columbia’s engineering
program also leverages the incredible strengths of the larger university with strong science departments
and a culture of out-of-the-box thinking. Columbia provides an intellectual culture to prepare students to
do great things. There is no greater
testament to that than the life and
career of Lynn Conway.
As a VLSI educator, I sense that
few students today recognize the
impact of the Mead-Conway text
and how it led to the “VLSI revolution.” In my own classes, I always
make sure to mention the impact
Mead and Conway had on creating the “culture of circuit design”
now embodied in our electrical
engineering program, including
a emphasis on hands-on design
projects. Lynn’s contribution to
making this happen, it seems, has
not been fully appreciated. From
that first course in the fall of 1978
that Lynn taught at MIT, things had
already exploded to 113 universities worldwide by 1982 (just four
short years!). Today, virtually every
electrical program in the world has
a course in modern VLSI design.
As a former IBM employee, Lynn’s
story touches me in two important
ways. First, IBM Research was and
still is (despite the many changes
at IBM and the industry these last
15 years) an amazing place with
many amazing people, my husband
among them. The time I spent there
was very influential on my future
career and I still have many productive interactions with IBM—it’s
a great place and a great company
and I think Lynn would agree.
That being said, the history of
what IBM did to Lynn in the 1960s
surrounding her gender transition
is unconscionable. Fortunately, this
is a different time now and IBM has
done a 180-degree turn in recognizing and valuing LGBT persons. For
those who aren’t in the know, this
brings. We know about the influence of the “Mead-Conway” book,
but no one seemed able to explain
what had actually happened.
Untold went Lynn’s story as the hidden hand that innovated, shaped
and guided the VLSI paradigm-shift
through the book, the courses and
the MPC79/MOSIS-infrastructure.
It is now becoming clearer why
this story was missed. Lynn’s
accomplishments as an engineer
are remarkable, but when placed in
the context of the discrimination
and personal struggle she faced as
a transgender woman, they are epic
and inspirational.
In a time when gender transitioners were pathologized, stigmatized,
socially ostracized and virtually
unemployable, Lynn found herself
As a VLSI educator, I sense that few
students today recognize the impact of the
Mead-Conway text and how it led to the
“VLSI revolution.”
stands for “lesbian, gay, bisexual,
and transgender” and refers to
people whose diversity is manifest
through sexual orientation or gender identity.
IBM adopted a policy of nondiscrimination on the basis of sexual
orientation in 1984 and added
“gender identity and expression”
in 2002. After 40 years, it is finally
recognized that companies cannot afford to do without some of
their best talent in the interests of
archaic prejudices. Over 50 major
companies now have policies of
nondiscrimination on gender identity and expression, including tech
giants like Apple, Hewlett-Packard,
Cisco, Intel, and Oracle.
Last but certainly not least,
from my perspective as a gay man,
Lynn’s story demonstrates the discrimination that LGBT people have
faced (and continue to face) in
this society and the negatives this
the innovator at the center of the
VLSI revolution. Constantly fearing
an “outing,” she worked passionately inside the laboratories of Xerox
PARC to orchestrate events while
minimizing external exposures—
thereby remaining a mystery-person
to those outside.
Kenji Yoshino, noted law professor at NYU, in his book Covering: The Hidden Assault on our Civil
Rights talks about the hidden cost of
hiding one’s identity, or “covering,”
for LGBT persons. As we see from
Lynn’s story, this “covering” not
only consumes tremendous time
and energy, but the actual contributions of such persons can also go
unrecognized, hidden away in the
background.
This year would have been the
100th birthday of another computer science pioneer, Alan Turing, who committed suicide at
age 41 after being persecuted for his
IEEE SOLID-STATE CIRCUITS MAGAZINE
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41
homosexuality. Imagine how many
more contributions he would have
made to our field had he lived longer. While Corporate America and
diversity discussion, there is still
a long way to go; meanwhile many
continue to remain in the closet out
of intense fear.
Lynn’s amazing story of accomplishment
and personal triumph in the face of personal
adversity and overt discrimination should serve
as an inspiration to all young e
­ ngineers.
most universities have come a long
way in recognizing the important
role that LGBT people play in the
Lynn’s amazing story of accomplishment and personal triumph in
the face of personal adversity and
Columbia’s new Northwest Corner Building, location of Prof. Shepard’s research laboratory.
42
fa l l 2 0 12
IEEE SOLID-STATE CIRCUITS MAGAZINE
overt discrimination should serve
as an inspiration to all young engineers. We are thankful that she has
shared these memorable reminiscences with us.
About the Author
Kenneth L. Shepard received the
B.S.E. degree from Princeton University, New Jersey, in 1987 and
the M.S. and Ph.D. degrees in electrical engineering from Stanford
University, California, in 1988 and
1992, respectively. From 1992 to
1997, he was a research staff member and manager with the VLSI
Design Department, IBM T.J. Watson
Research Center, Yorktown Heights,
New York, where he was responsible for the design methodology for
IBM’s G4 S/390 microprocessors.
Since 1997, he has been with Columbia University, New York, where he
is a professor of electrical engineering and biomedical engineering. He
also was chief technology officer
of CadMOS Design Technology, San
Jose, California, until its acquisition by Cadence Design Systems in
2001. His current research interests
include carbon electronics, power
electronics, and CMOS mixed-signal
design for biological applications.
He was technical program chair and
general chair for the 2002 and 2003
International Conference on Computer Design, respectively. He has
served on the Program Committees
for ISSCC, VLSI Symposium, ICCAD,
DAC, ISCAS, ISQED, GLS-VLSI, TAU,
and ICCD. He received the Fannie
and John Hertz Foundation Doctoral
Thesis Prize in 1992, a National Science Foundation CAREER Award in
1998, and the 1999 Distinguished
Faculty Teaching Award from Columbia. He has been an associate editor
of IEEE Transactions on Very LargeScale Integration (VLSI) Systems and
is currently an associate editor for
IEEE Journal of Solid-State Circuits
and IEEE Transactions on Biomedical
Circuits and Systems. He is a Fellow
of the IEEE.
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