mirrorbit reset an

mirrorbit reset an

Reset Voltage and Timing Requirements for MirrorBit

®

Flash

Application Note

Synopsis

MirrorBit NOR flash has several unique reset control signal timing requirements. Timing requirements vary by

MirrorBit process and family (110 nm, 90 nm, 65 nm, GLxxxN, WSxxxP, etc…). System designers must accommodate these requirements for reliable operation.

Applicable Device Families

110 nm MirrorBit Process: S29GLxxxN, S29PLxxxN, S29WSxxxN, S29NSxxxN

90 nm MirrorBit Process: S29GLxxxP, S29NSxxxP, S29WSxxxP

65 nm MirrorBit Process: S29GLxxxR, S29WSxxxR, S29NSxxxR, S29VS/XSxxxR

65 nm MirrorBit

®

Eclipse

Process: S29GLxxxS (

1 GBit), S70GL02GS

Publication Number

mirrorbit_reset_an

Revision

02

Issue Date

October 4, 2010

2

A p p l i c a t i o n N o t e

1.

Parameters of Interest

V

LKO t

VCS t

VIOS t

RP t

RH t

READY t

RB

Low V

CC

Lock-Out Voltage

V

CC

> V

CC-MIN

setup requirement prior to RESET# negation

V

IO

> V

IO-MIN

setup requirement prior to RESET# negation

RESET# pulse width (assertion period)

RESET# high requirement prior to CE# assertion

Period from RESET# assertion to RY/BY# negation

PERIOD from RY/BY# negation to CE# assertion

2.

Reset Requirements - 110 nm Process Node Products

The second generation MirrorBit devices have reset timing similar to the first generation of MirrorBit devices.

The power and timing requirements for Power-On-Reset and Warm-RESET (also known as Hard Reset) of the 110 nm process node products are reviewed in this section.

2.1

2.1.1

Power-On-Reset Requirements

During Power-On, V

CC

should rise monotonically and must remain greater than V

Voltage) during all reset operations. V

IO

can either be tied to V

CC

LKO

(Low V

CC

Lock-Out

or can be driven to a different voltage level

(see

Figure 2.1

). In the latter case, V

IO

must exceed V

IO_MIN

before RESET# is negated and must be maintained between V

IO_MIN

and V

CC

+100 mV.

During V

CC

ramp-up, RESET# must be asserted (low). From the period in time when V

CC

exceeds V

CC_MIN

,

RESET# must remain asserted for a period of t

VCS

prior to negation (see Figure 2.1

). Control signal

transitions can be initiated t

RH

following RESET# negation.

Power-On-Reset Timing

Table 2.1

110 nm Process Node Products - Power-On-Reset Timing

Parameter Description S29WSxxxN S29NSxxxN S29GLxxxN

t

VCS t

VIOS t

RH

V

V

CC

IO

Setup Time to RESET# negation (min)

Setup Time to RESET# negation (min)

RESET# high prior to CE# assertion (min)

1 ms

1 ms

200 ns

1 ms

1 ms

10 µs

50 µs

50 µs

50 ns

Notes:

1. For S29WSxxxN and S29NSxxxN, V

CC

ramp rate must exceed 1V/100 µs otherwise a hardware reset would be required.

2. For S29PLxxxN, V

CC

ramp rate must exceed 1V/400 µs otherwise a hardware reset would be required.

3. For S29PLxxxN and S29WSxxxN, V

IO

is internally connected to V

CC

.

4. For S29NSxxxN, V

IO

pin is named V

CC

Q.

S29PLxxxN

250 µs

250 µs

200 ns

VCC

VIO

Figure 2.1

110 nm Process Node Products- Power-On Reset Timing

V

CC_MIN

V

IO_MIN

V

IO

V

CC

+ 200 mV t

RH

CE# t

VIO S t

VC S

RE S ET#

MirrorBit Reset mirrorbit_reset_an_02 October 4, 2010

2.2

2.2.1

A p p l i c a t i o n N o t e

Warm-Reset Requirements

Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. Timing requirements vary by the state of the device prior to RESET# assertion, specifically whether or not the device is performing an embedded operation (program or erase operation in progress).

Warm-Reset Timing While Embedded Operation Not In Progress

In the event of the Warm-Reset being initiated when an embedded operation is not in progress (see

Figure 2.2

), the internal reset operation requires t

RP

to be completed. Control signal transitions can be initiated t

RH

following internal reset operation completion. RY/BY# will stay in the ready state as the device operates during non-embedded operations.

The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions.

Table 2.2

110 nm Process Node Products - Warm Reset Timing - Embedded Operation Not in Progress

Parameter

t

RP t

RH

Description

RESET# Pulse Width (min)

RESET# high prior to CE# assertion (min)

S29WSxxxN

30 µs

200 ns

S29NSxxxN

200 ns

10 µs

S29GLxxxN

500 ns

50 ns

S29PLxxxN

30 µs

200 ns

2.2.2

Figure 2.2

110 nm Process Node Products- Warm Reset Timing – Embedded Operation Not In Progress

CE# t

RH t

RP

RE S ET#

Warm-Reset Timing While Embedded Operation In Progress

In the event of the Warm-Reset being initiated when an embedded operation is in progress (see Figure 2.3

),

the internal reset operation requires t

READY

to be completed. t

READY

is comprised of the time required to gracefully exit an embedded programming operation, followed by the standard internal reset operation and the set-up time from reset operation completion until a control signal transition detection can be guaranteed.

The complete reset operation is triggered by the falling edge of RESET#. RESET# must remain asserted for a period of t

RP

. Control signals transition can be initiated t

READY

after the falling edge of RESET#.

Table 2.3

110 nm Process Node Products - Warm Reset Timing - Embedded Operation in Progress

Parameter

t

READY t

RB t

RP t

RH

Description

RESET# assertion to RY/BY# negation (min)

RY/BY# high to CE# assertion (min)

RESET# Pulse Width (min)

RESET# high prior to CE# assertion (min)

S29WSxxxN

30.2 µs

0 ns

30 µs

200 ns

S29NSxxxN

10.2 µs

0 ns

200 ns

10 µs

Notes:

1. For S29WSxxxN, S29NSxxxN and S29PLxxxN, t

READY

= t

RP

+ t

RH

. No additional waiting time is required.

2. For GLxxxN, The sum of t

RP

and t

RH

must be equal to or greater than t

READY

.

S29GLxxxN

20 µs

0 ns

500 ns

50 ns

S29PLxxxN

30.2 µs

0 ns

30 µs

200 ns

A typical implementation would have RESET# asserted a period of t

READY

with a short delay from RESET# negation before asserting CE# and initiating a read operation.

An alternate implementation is asserting RESET# for a shorter period of t

RP

and employing a delay loop to prevent flash control signal accesses for t

READY

from the assertion of RESET#.

An additional option is to monitor RY/BY# following the rising edge of a RESET# pulse at least t

RP

in duration.

When RY/BY# is detected high, control signal transitions can be initiated.

October 4, 2010 mirrorbit_reset_an_02 MirrorBit Reset 3

4

A p p l i c a t i o n N o t e

Figure 2.3

110 nm Process Node Products - Warm Reset Timing – Embedded Operation In Progress t

READY

RY/BY# t

RB

CE#, OE# t

RH

RE S ET# t

RP

3.

Reset Requirements - 90 nm Process Node Products

New reset conditions are required for the 90 nm MirrorBit devices because of circuit changes implemented to reduce die size and to improve endurance of Advanced Sector Protection PPB bits. The Power-On-Reset and

Warm Reset requirements for these new device families are reviewed in this section.

3.1

3.1.1

Power-On-Reset Requirements

During Power-On, V

CC

should rise monotonically and must remain greater than V

LKO

during all reset operations. V

IO must exceed V

can either be tied to V

CC

or can be driven to a different voltage level. In the latter case, V

IO_MIN

before RESET# is negated and must be maintained between V

IO_MIN

and

IO

V

CC

+100 mV.

During V

CC

ramp-up, RESET# must be asserted (low). From the period in time when V

CC

exceeds V

CC_MIN

,

RESET# must remain asserted for a period of t

VCS

) prior to negation (see

Figure 3.1

). Control signal transitions can be initiated t

RH

following RESET# negation.

Power-On-Reset Timing

Table 3.1

90 nm Process Node Products - Power-On-Reset Timing

Parameter Description S29WSxxxP S29NSxxxP S29GLxxxP

t

VCS t

VIOS t

RH

V

CC

V

IO

Setup Time to RESET# negation (min)

Setup Time to RESET# negation (min)

RESET# high prior to CE# assertion (min)

30 µs

30 µs

200 ns

30 µs

30 µs

200 ns

35 µs

35 µs

200 ns

Notes:

1. For S29WSxxxP, V

CC

ramp rate must exceed 1V/400 µs otherwise a hardware reset would be required.

2. For S29WSxxxP and S29NSxxxP, V

IO

pin is named V

CC

Q.

3. V

CC

and V

IO

(resp. V

CC

Q) must be ramped up simultaneously for proper power-up.

4. If RESET# is not stable for t

VCS

or t

VIOS

: The device does not permit any read and write operations, a valid read operation returns FFh and a hardware reset is required.

VCC

VIO

Figure 3.1

90 nm Process Node Products- Power-On Reset Timing

V

CC_MIN

V

CC

V

LKO

V

IO_MIN

V

IO

V

CC

+ 200 mV t

RH

CE#, OE# t

VIO S t

VC S

RE S ET# t

VC S

: V

CC

S et u p Time t

VIO S

: V

IO

S et u p Time

MirrorBit Reset mirrorbit_reset_an_02 October 4, 2010

A p p l i c a t i o n N o t e

3.2

3.2.1

Warm-Reset Requirements

Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. Timing requirements vary by the state of the device prior to RESET# assertion, specifically whether or not the device is performing an embedded operation (program or erase operation in progress).

During Warm-Reset operations, V

CC

must be maintained greater than V

LKO

.

Warm-Reset Timing While Embedded Operation Not In Progress

In the event of the Warm-Reset being initiated when an embedded operation is not in progress (see

Figure 3.2

), the internal reset operation requires t

RP

to be completed. Control signal transitions can be initiated t

RH

following internal reset operation completion. RY/BY# will stay in the ready state as the device operates during non-embedded operations.

The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions.

Table 3.2

90 nm Process Node Products - Warm Reset Timing - Embedded Operation Not in Progress

Parameter

t

RP t

RH

Description

RESET# Pulse Width (min)

RESET# high prior to CE# assertion (min)

S29WSxxxP

30 µs

200 ns

S29NSxxxP

50 ns

200 ns

S29GLxxxP

35 µs

200 ns

Figure 3.2

90 nm Process Node Products– Warm Reset Timing – Embedded Operation Not In Progress

VCC

V

CC

V

LKO

RY/BY# t

RH

CE#, OE# t

RP

RE S ET#

October 4, 2010 mirrorbit_reset_an_02 MirrorBit Reset 5

6

3.2.2

A p p l i c a t i o n N o t e

Warm-Reset Timing While Embedded Operation In Progress

In the event of the Warm-Reset being initiated when an embedded operation is in progress (see Figure 3.3

),

the internal reset operation requires t

READY

to be completed. t

READY

is comprised of the time required to gracefully exit an embedded programming operation, followed by the standard internal reset operation and the set-up time from reset operation completion until a control signal transition detection can be guaranteed.

The complete reset operation is triggered by the falling edge of RESET#. RESET# must remain asserted for a period of t

RP

. Control signals transition can be initiated by t

READY

after the falling edge of RESET#.

Table 3.3

90 nm Process Node Products - Warm Reset Timing - Embedded Operation in Progress

Parameter

t

READY t

RB t

RP t

RH

Description

RESET# assertion to RY/BY# negation (min)

RY/BY# high to CE# assertion (min)

RESET# Pulse Width (min)

RESET# high prior to CE# assertion (min)

S29WSxxxP

30.2 µs

0 ns

30 µs

200 ns

Notes:

1. For S29WSxxxP and S29GLxxxP, t

READY

= t

RP

+ t

RH

. No additional waiting time is required.

2. For NSxxxP, The sum of t

RP

and t

RH

must be equal to or greater than t

READY

.

S29NSxxxP

10 µs

0 ns

50 ns

200 ns

S29GLxxxP

35.2 µs

0 ns

35 µs

200 ns

A typical implementation would have RESET# asserted a period of t

READY

with a short delay from RESET# negation before asserting CE# and initiating a read operation.

An alternate implementation is asserting RESET# for a shorter period of t

RP

and employing a delay loop to prevent flash control signal accesses for t

READY

from the assertion of RESET#.

An additional option is to monitor RY/BY# following the rising edge of a RESET# pulse at least t

RP

in duration.

When RY/BY# is detected high, control signal transitions can be initiated.

Figure 3.3

90 nm Process Node Products - Warm Reset Timing – Embedded Operation In Progress t

READY

RY/BY# t

RB

CE#, OE# t

RH

RE S ET# t

RP

MirrorBit Reset mirrorbit_reset_an_02 October 4, 2010

A p p l i c a t i o n N o t e

4.

Reset Requirements - 65 nm Process Node Products

New reset conditions are required for the 65 nm MirrorBit devices because of circuit changes implemented to reduce die size. The Power-On-Reset and Warm Reset requirements for these new device families are reviewed in this section.

4.1

4.1.1

Power-On-Reset Requirements

During Power-On, the V

CC

and V

IO

ramp rate could be non-linear. However, V

CC

and V

IO

must remain greater than V

LKO

during all reset operations. It is also recommended to ramp up those two signals simultaneously.

Power-On-Reset Timing

Table 4.1

65 nm Process Node Products - Power-On-Reset Timing

Parameter Description S29WSxxxR

t

VCS t

VIOS t

RH t

RP t

RPH

V

V

CC

IO

Setup Time to RESET# negation (min)

Setup Time to RESET# negation (min)

RESET# high prior to CE# assertion (min)

RESET# Pulse Width (min)

RESET# Low to CE# Low (min)

300 µs

300 µs

200 ns

50 ns

10 µs

Notes:

1. V

CC

and V

IO

ramp rate could be non-linear.

2. RESET# must be high after V

CC

and V

IO

are higher than V

CC

minimum.

3. The sum of t

RP

and t

RH

must be equal to or greater than t

RPH

.

S29NSxxxR

300 µs

300 µs

200 ns

50 ns

10 µs

S29GLxxxR

300 µs

300 µs

150 ns

200 ns

35 µs

S29VS/XSxxxR

300 µs

300 µs

200 ns

50 ns

10 µs

Figure 4.1

65 nm Process Node Products - Power-On Reset Timing

VCC

VIO t

VIO S t

VC S

RE S ET# t

RP t

RPH t

RH

CE#

October 4, 2010 mirrorbit_reset_an_02 MirrorBit Reset 7

4.2

A p p l i c a t i o n N o t e

Warm-Reset Requirements

Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. Starting from the

65 nm MirrorBit products, the warm reset timing requirements will be totally independent from the state of the device prior to RESET# assertion, namely whether an embedded operation was in progress or not.

During Warm-Reset operations, V

CC

must be maintained greater than V

LKO

.

During Warm-Reset (see

Figure 4.2

), the internal reset operation requires t

RP

to be completed. Control signal transitions may be initiated t

RH

following RESET# negation.

4.2.1

Warm-Reset Timing

Table 4.2

65 nm Process Node Products - Warm Reset Timing

Parameter Description

t

RPH t

RP

RESET# Low to CE# Low (min)

RESET# Pulse Width (min) t

RH

RESET# high prior to CE# assertion (min)

Notes:

1. The sum of t

RP

and t

RH

must be equal to or greater than t

RPH

.

2. CE#, OE# and WE# must be at logic high during Reset Time.

S29WSxxxR

10 µs

50 ns

200 ns

S29NSxxxR

10 µs

50 ns

200 ns

S29GLxxxR

35 µs

200 ns

150 ns

S29VS/XSxxxR

10 µs

50 ns

200 ns

The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions.

An equally effective and alternate implementation for the 65 nm MirrorBit devices is asserting RESET# for a short period followed by a long delay to allow the completion of the internal reset operation prior to initiating control signal transitions.

RE S ET#

Figure 4.2

65 nm Process Node Products – Warm Reset Timing t

RP t

RH t

RPH

CE#

8 MirrorBit Reset mirrorbit_reset_an_02 October 4, 2010

A p p l i c a t i o n N o t e

5.

Reset Requirements - 65 nm Eclipse MirrorBit Products

New reset conditions are required for the 65 nm Eclipse MirrorBit devices because of circuit changes implemented to reduce die size. The Power-On-Reset and Warm Reset requirements for these new device families are reviewed in this section.

5.1

5.1.1

Power-On-Reset Requirements

During Power-On, V

CC

and V

IO

ramp rate could be non-linear. However, V

CC

and V

IO

must remain greater than V

LKO

during all reset operations. It is also recommended to ramp up those two signals simultaneously.

Power-Up Sequencing

V

CC

must always be greater than or equal to V

IO

(V

CC

V

IO

). V

IO

200 mV (V

IO

V

CC

- 200 mV) when V

IO

is below the V

IO

must track the rise and fall of V

minimum.

CC

within

The device ignores all inputs until a time delay of t

VCS

has elapsed after the moment that V

CC

and V

IO

both rise above, and stay above, the minimum V

CC

and V

IO

thresholds. During t

VCS

the device is performing power on reset operations.

Parameter

t

VCS t

VIOS

Table 5.1

65 nm Eclipse Products - Power-Up Timing

Description

V

CC

Setup Time to RESET# negation (min)

V

IO

Setup Time to RESET# negation (min)

S29GLxxxS

300 µs

300 µs

S70GL02GS

600 µs

600 µs

Figure 5.1

65 nm Eclipse Products - Power-up Timing

October 4, 2010 mirrorbit_reset_an_02 MirrorBit Reset 9

5.1.2

A p p l i c a t i o n N o t e

Power-On-Reset Timing

Table 5.2

65 nm Eclipse Products - Power-On-Reset Timing

Parameter

t

VCS t

VIOS t

RH t

RP t

RPH

V

CC

V

IO

Description

Setup Time to RESET# negation (min)

Setup Time to RESET# negation (min)

RESET# high prior to CE# assertion (min)

RESET# Pulse Width (min)

RESET# Low to CE# Low (min)

S29GLxxxS

Gbit

300 µs

300 µs

50 ns

200 ns

35 µs

S70GL02GS

600 µs

600 µs

50 ns

200 ns

70 µs

Notes:

1. V

CC

and V

IO

ramp rate could be non-linear.

2. RESET# Low is optional during POR. If RESET# is asserted during POR, the later of t

RPH

, t

VIOS

, or t

VCS will determine when CE# may go

Low. If RESET# remains low after t

VIOS

, or t

VCS

is satisfied, t

RPH

is measured from the end of t

VIOS

, or t

VCS

. RESET# must also be high t

RH

before CE# goes low.

3. The sum of t

RP

and t

RH

must be equal to or greater than t

RPH

.

4. RY/BY# pin is low during power-up.

Figure 5.2

65 nm Eclipse Products - Power On Reset Timing

VCC

VIO t

VIO S t

VC S

RE S ET# t

RP t

RPH t

RH

CE#

5.2

5.2.1

Warm-Reset Requirements

Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. For the 65 nm

MirrorBit Eclipse products, the warm reset timing requirements will be also totally independent from the state of the device prior to RESET# assertion, namely whether an embedded operation was in progress or not.

During Warm-Reset operations, V

CC

must be maintained greater than V

LKO

.

During Warm-Reset (see

Figure 5.3

), the internal reset operation requires t

RP

to be completed. Control signal transitions may be initiated t

RH

following RESET# negation.

Warm-Reset Timing

Table 5.3

65 nm Eclipse Products - Warm Reset Timing

Parameter Description

t

RPH t

RP t

RH

RESET# Low to CE# Low (min)

RESET# Pulse Width (min)

RESET# high prior to CE# assertion (min)

Notes:

1. The sum of t

RP

and t

RH

must be equal to or greater than t

RPH

.

2. CE#, OE# and WE# are recommended to be at logic high during Reset Time.

S29GLxxxS

1 Gbit

35 µs

200 ns

50 ns

S70GL02GS

70 µs

200 ns

50 ns

10 MirrorBit Reset mirrorbit_reset_an_02 October 4, 2010

A p p l i c a t i o n N o t e

The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions.

An equally effective and alternate implementation for the 65 nm MirrorBit Eclipse devices is asserting

RESET# for a short period followed by a long delay to allow the completion of the internal reset operation prior to initiating control signal transitions.

RE S ET#

Figure 5.3

65 nm Eclipse Products - Warm Reset Timing t

RP t

RH t

RPH

CE#

October 4, 2010 mirrorbit_reset_an_02 MirrorBit Reset 11

A p p l i c a t i o n N o t e

6.

Revision History

Section

Revision 01 (November 14, 2006)

Revision 02 (October 4, 2010)

Description

Initial release

Updated document format

Removed all references to AM29LVxxxM, MBM29PLxxxM, S29GLxxxM, S29PLxxxP and

S29GLxxxA

Added POR and Reset requirements for 90 nm, 65 nm and 65 nm Eclipse products

12 MirrorBit Reset mirrorbit_reset_an_02 October 4, 2010

A p p l i c a t i o n N o t e

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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document.

Copyright © 2006-2010 Spansion Inc. All rights reserved. Spansion

®

, the Spansion logo, MirrorBit

®

, MirrorBit

®

Eclipse™, ORNAND™,

EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.

Other names used are for informational purposes only and may be trademarks of their respective owners.

October 4, 2010 mirrorbit_reset_an_02 MirrorBit Reset 13

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