TSIU03, SYSTEM DESIGN LECTURE 4 LINKÖPING UNIVERSITY

TSIU03, SYSTEM DESIGN  LECTURE 4 LINKÖPING UNIVERSITY
LINKÖPING UNIVERSITY
Department of Electrical
Engineering
TSIU03, SYSTEM DESIGN
LECTURE 4
Kent Palmkvist ([email protected])
Based on slides by Mario Garrido Gálvez ([email protected])
Linköping, 2015
1
Deadline reminder
 Lab 1 deadline Wednesday 9 September (everyone
already passed?)
 Assignment 2 deadline Friday 11 September 10.15
2
TODAY
 More information about test bench VHDL: wait, assert,
instantiating a design
 Data types
 Memories
 FIFO/Buffer.
 Description of the Project (development part).
3
WHICH IS THE DIFFERENCE?
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
entity and1 is
entity and2 is
port (a,b: in std_logic;
port (a,b: in std_logic;
z : out std_logic);
z : out std_logic);
end and1;
end and2;
architecture arch of and1 is
architecture arch of and2 is
signal p: std_logic;
begin
signal p: std_logic;
begin
p <= a AND b;
z <= p;
z <= p;
p <= a AND b;
end arch;
end arch;
4
PROCESS
process (<sensitivity_list>) –- triggers for the process
<variable_declaration> -- only if the process has variables
begin
if reset = '1' then
<initialization>
-- asynchronous reset (also:
='0')
-- initialize signals and variables
elsif rising_edge (clk) then
<statements>
-- behavior of the circuit
-- These statements are executed
-- one by one (sequential)
end if;
end if;
end process;
5
LAB 2 TEST BENCH
 In lab 2 notes there is a new command presented
assert HEX0 = “0011001” report “HEX0 failed” severity error;
 Print out a message if HEX0 is the wrong value, also indicating how
important this is (can be note, warning, error or failure)
 Works on all VHDL simulators (not only Modelsim)
 Not possible to synthesize (can not create corresponding hardware) =>
Only for testbench design.
 wait statement at the end of a process used to limit the process to run
only once (all processes are started at simulation start)
 signal assignment with delay (from testbench example)
PS_DAT <= ‘0’; -- start bit
PS2_CLK <= ‘0’ after 10 us, ‘1’ after 35 us;
wait for 100 us;
6
LAB 2 TEST BENCH
 Instantiating of another design. Another design can then be included in
the architecture and connected to the rest of the architecture. Declare first
the design to test before the begin statement in the architecture
component mydesign is
Port(a,b: in std_logic; z: out std_logic);
end component;
 Connect the design to the signals in the architecture by instantiating it
after the begin in the architecture
Unit1 : mydesign
port map (a => asignal, b => bsignal, z => result);
 asignal etc above must be declared as signals in the testbench
architecture.
 The component part may be excluded if new release of VHDL is used.
7
TEST BENCH EXAMPLE
...
constant clk_period : time := 10 ns; -- Clock period.
signal rstn, clk : std_logic;
signal counter : std_logic_vector(3 downto 0);
component controlBlock is
port (rstn : in std_logic; clk : in std_logic; counter :
std_logic_vector(3 downto 0));
end component;
begin
rstn <= '1', '0' after 10 ns, '1' after 25 ns; -- Reset.
-- Instantiation of the component to simulate.
ctnrlBlock: controlBlock
port map( rstn => rstn, clk => clk, counter => counter);
...
8
TEST BENCH ALTERNATIVE
...
constant clk_period : time := 10 ns; -- Clock period.
signal rstn, clk : std_logic;
signal counter : std_logic_vector(3 downto 0);
begin
rstn <= '1', '0' after 10 ns, '1' after 25 ns; -- Reset.
-- Instantiation of the component to simulate.
ctnrlBlock: entity work.controlBlock
port map( rstn => rstn, clk => clk, counter => counter);
...
9
DATA TYPES
 VHDL is strongly typed: The type of each signal must always be
clear.
 Operators depend on the type. Example: the operator < gives a
different result for signed and unsigned, and cannot be used with
std_logic_vector.
 Some standard types (predefined in VHDL):
type boolean is (true, false);
type integer is range -2147483648 to +2147483647;
type real -- real value
type time – integer number plus unit (ns, ms,...)
 Some types are synthesizable, such as boolean or integer and
some types are not, such as real or time.
 Good description and further information on data types: [R4].
10
TYPES OF TYPES
 Integer types:
type integer is range -2147483648 to +2147483647;
type short is range -128 to 127;
 Subtypes:
subtype natural is integer range 0 to integer'high;
 Enumeration:
type std_logic is ('U','X','0','1','Z','W','L','H','-');
type bit is ('0','1')
type boolean is (false, true);
 Array:
type memory is array (0 to 2**bitsAddr -1) of
std_logic_vector (WL -1 downto 0);
11
MEMORY
 Circuit used for storage.
 It is an array of 2n locations, each
of which stores m bits of
information.
WL
1
EN ABLE
 Each of the locations has one
address that ranges from 0 to 2n -1.
Therefore, the address of the
memory is represented by n bits.
 We can read a memory location
by selecting its address.
0
1
1
WR
2
n
ADDRESS
WL
WL
D A T A IN
DATA OUT
n
2 -1
 In some memories we can also
write in the memory locations.
12
TYPES OF MEMORY
 Internal memory (we can create them in the FPGA):
- RAM: Random Access Memory (we can read and write to it).
- ROM: Read Only Memory (fixed values that we cannot modify).
 External memory (outside the FPGA):
- RAM and ROM: They can be external as well.
- SRAM: Static RAM (static = does not need refresh).
- SDRAM: Synchronous Dynamic RAM (dynamic = needs refresh).
- DDR SDRAM: Double Data Rate SDRAM (upper and lower edge).
- FLASH (non volatile = the content is not erased without power).
 The DE2 board includes an 8 MB SDRAM, a 512 kB
SRAM and a 4 MB FLASH.
13
ROM IN VHDL
 Example of a ROM of 8 addresses and 4 bits in each address:
...
type ROM_mem is array (0 to 7) of
std_logic_vector (3 downto 0);
constant ROM_content: ROM_mem := (0 => "0001",
1 => "0101",
2 => "0000",
3 => "0111",
4 => "0001",
5 to 7 => "1111");
signal Addr: std_logic_vector (2 downto 0);
begin
z <= ROM_content(to_integer(unsigned(Addr)));
...
14
RAM IN VHDL
type RAM_mem is array (0 to 2**bitsAddr -1)
of std_logic_vector (WL -1 downto 0);
signal RAM_content: RAM_mem;
signal Addr: std_logic_vector (bitsAddr -1 downto 0);
begin
process (clk)
begin
if rising_edge (clk) then
if we = '1' then
-- Write enable signal
RAM_content (to_integer(unsigned(Addr))) <= data_in;
end if;
end if;
end process;
data_out <= RAM_content (to_integer(unsigned(Addr)));
15
DUAL-PORT RAM
 Dual-Port: memory in which it is possible to write on a memory location
and read from another one. Obviously, it uses more resources (more
area) than a single-port memory.
 wAddr: write address; rAddr: read address.
process (clk)
begin
if rising_edge (clk) then
if we = '1' then
RAM_content (to_integer(unsigned(wAddr))) <= data_in;
end if;
data_out_reg <= data_out; -- If we want to register the output
end if;
end process;
data_out <= RAM_content (to_integer(unsigned(rAddr)));
16
FIFO or BUFFER
a
L
c lk
z
z n   a n  L 
 FIFO = First-In First-Out.
 It simply delays the inputs L clock cycles. The wordlength of the
input and output is WL:
type FIFO is array (0 to L-1)
of std_logic_vector (WL -1 downto 0);
 The buffer can be implemented in a similar way as a shift register,
i.e., moving each word to the next position every clock cycle
(preferable for small L) or by using a memory (preferable for large L).
17
TRISTATE BUFFERS
 Common to use a shared bus for data in external SRAMs
 Avoid using tristate buffers inside the design, only to connect to
outside units such as memories
 Use entity port direction INOUT
 Must be able to turn one of the connected signals to inactive
(TRISTATE) using assignment with ‘Z’
 Requires use of the std_logic datatype
 Important: Assigning ‘1’ and ‘0’ from two different entities to the
same signal corresponds to a short-circuit
 May destroy circuit in practice
18
PROJECT
 Aim: Develop a complete functional system using the DE2
board and the FPGA included in it.
 Task: Use the DE2 board to modify/analyze a sound signal
(in stereo) that is generated by a CD player. The input sound
signal shall be converted into digital form and modified on the
FPGA. The output sound shall be sent to the loudspeakers.
Information related to the signal will be displayed graphically
on a VGA attached to the board. The red and green LEDs and
7-segment displays on the DE2 board can also be used for this
purpose. Everything can be controlled using the push buttons
and switches on the board, or from an attached keyboard.
19
GENERAL REQUIREMENTS
 It has to fit in the DE2 board and in the FPGA.
 All the hardware on the board can be used: push
buttons, displays, switches, memories (SRAM and
FLASH), etc.
 All groups must implement a digital volume control and
balance for the incoming sound signal. The volume shall
have at leas 10 levels of resolution, and the balance shall
also have at least 10 levels.
 Apart from these general requirements, each project
group has to choose an alternative task.
20
ALTERNATIVE TASKS
1) Digital Oscilloscope.
2) Signal level indicator.
3) Echo.
4) Suppression of the mono sound and bass/tremble
amplification.
5) Equalizer.
6) Task proposed by the students.
Together with the specific task, each project group has to
propose a small “improvement” or distinctive feature that makes
their system different to any other project.
21
PHASES OF THE PROJECT
 Create the project groups.
 Define the requirements of the system:
- Write the Requirement Specification document.
 Hardware design:
- Do the hardware design of the system.
- Write the Design Specification and the Project Plan documents.
- First Presentation.
 Description in VHDL:
- Do the VHDL description in the lab.
- Write the Project Report document.
- Final Presentation and Demo.
22
CREATING THE GROUPS
 Groups of 6 people (three lab groups together).
 Decide your group and sign up between Sep. 14th and 16th.
 Group members must:
- Be registered in the course (deadline Sep. 14th).
- Pass lab 2 to be allowed to do the project.
 We will publish the list of definitive lab groups on Sep. 17th.
23
DEFINITION OF REQUIREMENTS
 As soon as your group is confirmed (on Sep 17th), book
the first meeting with the supervisor.
 To book the meeting, the supervisor will have a list
outside his office, where you can write your group number.
 First meeting (Sep. 17th or 18th):
- Discuss the project tasks that you have thought about. Ask
questions that you have. Decide the project manager.
- After the meeting, write the Requirement Specification. Submit it
24h before the second meeting.
 Second meeting (Sep. 22rd or 23th):
- Discuss the proposed Requirement Specification with the
supervisor.
24
HARDWARE DESIGN PART
 In this phase you have to do the hardware design part of
your system (no VHDL implementation).
 The result of this phase will be the Design Specification and
Project Plan documents, and the First Presentation.
 The supervisor and the other teachers will be available for
discussions. You will also have a third meeting with the
supervisor, where you discuss the first version of the Design
Specification.
 It is important that you plan this phase well. Doing the
hardware design and explaining it in the document takes time
and cannot be done in a few days.
25
DESCRIPTION IN VHDL PART
 In this phase, you have to describe your design in VHDL.
 The result of this phase will be the Project Report and the
Final Presentation.
 The lab will be available and you are welcome at any time
where there are no other courses running.
 Your supervisor and the other teachers will be available at
any time to help you. There will also be specific times when
the teachers are in the lab.
 If you did a good design, the description in VHDL should be
easy to do. For debugging, prepare a good test bench.
26
DOCUMENTS
 Information that you have to read and use:
- Project Specification.
- Guidelines to Write the Documents for the Project.
- How to Design a HW System.
- How to Describe a HW Circuit.
- Template for the Time Reports.
 Document that you have to create:
- Requirement Specification.
- Design Specification and Project Plan.
- Project Report.
- First Presentation, Final presentation.
27
FINAL CONSIDERATIONS
 Today’s presentation has been a summary of the project.
The complete information is in the Project Specification
document. Read it carefully.
 The Project Specification is clearly divided in phases, so
that you know what you have to do at each time.
 For writing documents, read also carefully the
Guidelines to Write the Documents for the project.
 Deadlines are shown in the Project Specification and on
the web page of the course.
 If you get stuck, do not waste time. Ask the teachers!
28
CHECKLIST FOR LECTURE 4
 VHDL language: the order of the statements in VHDL
does not matter
 More VHDL for testbench: wait, report, instantiation.
 Data types
 Storage circuits: memory types, RAM, ROM,
FIFO/Buffer.
 VHDL: type, boolean, real, time, enumeration, array,
RAM, Dual-port RAM, ROM.
 Description of the project (development part).
29
AT HOME
 Review the checklist for lecture 4 and check that you
understand all the concepts and you know how to use
them.
 Do the Assignment 2. It has to be presented at the
beginning of lecture 6.
 Read the Project Specification document carefully.
 Find classmates to form a group together with them.
30
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