Digital Average Current-Mode Controller for DC–DC

Digital Average Current-Mode Controller for DC–DC
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
Digital Average Current-Mode Controller for DC–DC
Converters in Physical Vapor Deposition Applications
Milan Ilic, Member, IEEE, and Dragan Maksimovic, Senior Member, IEEE
Abstract—A dc power supply in physical vapor deposition (PVD)
applications operates as a constant power source during normal
operation or as a constant current source during fast micro arcs
in the plasma. A two-loop control is usually applied: an external
(slower) loop controls the output power, while an internal (fast)
loop controls the current. This paper introduces a digital average
current mode controller for dc power supplies in PVD applications. The controller provides a current source response to fast
disturbances, and enables equal current sharing among buck converter modules operating in parallel. Adaptive adjustments of the
compensator gain in the digital current control loop enable operation over wide ranges of output power and voltage. The proposed
control strategy is robust and noise insensitive. The current and
power control algorithms are implemented on a digital signal processor/field-programmable gate array-based digital control platform using a low-cost 10-bit 500 kS/s analog-to-digital converter.
The performance is verified on a 25 kW experimental prototype.
Index Terms—Current-mode control, DC–DC converters, digital
control, physical vapor deposition.
I. INTRODUCTION
P
HYSICAL VAPOR DEPOSITION (PVD) processes, often
called plasma processes, are used for materials deposition
in diverse industries, including manufacturing of semiconductor
circuits, flat panel displays, data storage media, optical components, architectural glass [1]–[3], and thin-film photovoltaic
modules [4], [5]. The dc power supplies for PVD processes typically provide 10 to 50 kW of power during normal operation.
The deposition thickness depends on the power supply output
power, which has to be precisely controlled (within 1%). The
power supply must behave as a power source during normal
operation or as a constant current source during fast discharge
(known as arc) in the plasma [6], which results in a temporary
near-short-circuit condition at the output. An arc can last less
than 100 ns (known as micro arc), or it can cause additional
cathode emission (known as hard arc) that requires turn off of
the power supply for tens of s to stop further cathode damage.
During arc condition, the output voltage changes very rapidly
100 kV/ s). Hence, noise immunity is a very im(
portant practical requirement. A two-loop control is usually applied: an external (slower) loop controls the output power (or
Manuscript received August 15, 2006; revised September 15, 2007. Recommended for publication by Associate Editor S. Y. Hui.
M. Ilic is with Advanced Energy, Fort Collins, CO 80525 USA (e-mail: milan.
[email protected]).
D. Maksimovic is with the Colorado Power Electronics Center, Electrical
and Computer Engineering Department, University of Colorado, Boulder, CO
80309 USA (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2008.920880
Fig. 1. Interleaved ZCT buck converter [8].
voltage in some special plasma applications), while an internal
(fast) loop controls the current [7].
The zero current transition (ZCT) converter shown in Fig. 1
has been proposed in [8] for high-power, high-voltage dc–dc applications, such as the PVD processes. In this converter topology
the switch turn-on losses and the diode recovery losses are significantly reduced. In addition, the two switches, which are operated out of phase, share the power. As a result, efficient operation at relatively high switching frequency is possible. Averaged
switch modeling of the interleaved ZCT buck converter has been
discussed in [9].
The main objectives of this paper are to present the control
design challenges, digital controller implementation techniques
and experimental results for the ZCT converter of Fig. 1 in a
25 kW PVD power supply operating at 31.25 kHz switching
frequency.
In a conventional design, the external power-control loop,
which is usually based on a digital integral compensator, receives a set point command from a system controller in a digital format. A digital-to-analog (D/A) converter then converts
the calculated set point for the current loop to an analog current reference. Average current mode control [10], which offers
a degree of immunity against the noise due to plasma arcing
or switching transitions, is the most frequently applied control
method for the inner loop. The challenges in the design of the
inner current control loop are to achieve wide bandwidth and robust operation over a wide range of operating conditions (output
voltage range 50–650 V, power range 250 W to 25 kW, output
current up to 83 A).
In a digital control implementation, parameters can be adaptively adjusted to meet the control requirements over the entire ranges of operating conditions. An important concern, however, is the bandwidth limitation due to delays associated with
analog to digital (A/D) conversion, computation, and pulsewidth
modulation (PWM). To address this issue, various predictive or
dead-beat digital current control techniques have been proposed
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ILIC AND MAKSIMOVIC: DIGITAL AVERAGE CURRENT-MODE CONTROLLER
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Fig. 2. Block diagram of the digital average current-mode controller.
[11]–[19]. However, in these approaches the current is sampled
once per switching cycle, which is not suitable for PVD applications where the noise levels are high due to fast arc events
and switching transients, especially in systems where multiple
power supplies are connected in parallel and the duty cycle can
vary in a wide range (from less than 10% to more than 90%).
Digital current control approaches based on multiple samples
per period have been discussed in the context of charge control
emulation [20] and emulation of hysteretic current control [21].
Multiple samples per switching period can lead to effectively
shorter response delay, at the expense of a faster current A/D
converter.
For the application considered in this paper, benefits of digital
emulation of the average current control include shorter delay
and improved noise immunity. Since the switching frequency
is relatively low, multiple samples per period can be obtained
using a relatively low-cost A/D converter. The system model
and the proposed control method are introduced in Section II.
Section III describes compensator design, including adaptive
adjustments of the compensator gain in the digital current control loop to enable operation over wide ranges of output power
and voltage. Simulation results and results of experimental verification on the 25 kW prototype are described in Section IV.
Conclusions are given in Section V.
II. SYSTEM MODEL AND DIGITAL AVERAGE
CURRENT-MODE CONTROLLER
The most important requirements for the inner current control
loop are as follows.
• Noise immunity. The plasma power supply operates in a
very noisy environment due to arcs in the plasma, the rate
of which can be as high as 1000 arcs/s.
• Wide bandwidth of the current control loop is necessary to
obtain sufficiently high output impedance. Plasma in newer
PVD processes can behave as a large incremental negative impedance in the frequency range of 0.5–20 kHz. Designing the power supply for high output impedance is one
way to ensure system stability.
• Robustness over a very wide range of operating conditions.
In the experimental prototype described in this paper, the
output voltage range is 300–650 V (full output power is
available), the output power range is 2.5 to 25 kW, and the
output current is up to 83.3 A.
To address these challenges, we consider realization of a digital average current-mode controller. The system block diagram
is shown in Fig. 2.
Fig. 3. Timing diagram of the predictive average current-mode control [16] and
the averaging method described in this paper. GD1 and GD2 are the gate drive
signals for the switches S1 and S2, respectively, in the converter of Fig. 1.
A. Current Sensing and Averaging
is sensed using a Hall-effect sensor
The inductor current
(LEM). The sensed current signal passes through an antialiasing
, and is converted to digital form
analog lowpass filter
using a 10-bit 500 kS/s A/D converter. Implementation of the
inductor current sampling and processing deserves attention.
In predicitive current mode control approaches [11]–[17] the
inductor current is sampled once per switching period, which
means that a low-cost, low sampling-rate and low-power A/D
converter can be used. In the predictive average current-mode
control [16], [17], a triangle-wave PWM enables sampling of
the current signal in the middle of the switch on time (or in the
middle of the switch off time), which is advantegous for noise
immunity. Unfortunately, these approaches are not well suited
for current-mode control in power supplies for PVD applications because it is not possible to ensure noise immunity by selecting a single sampling point during a switching period. The
duty cycle variations are very wide, and the environment is very
noisy due to plasma arcs and switching disturbances from power
stages operated in parallel.
In order to improve noise immunity, after passing through the
, the current signal is sampled multiple
antialiasing filter
times per switching period and a digital averaging filter
computes the average current. In the experimental prototype, the
switching frequency is 31.25 kHz, and the switching period is
s. The current is sampled at the rate of 500 kS/s, and
the sampling period is 2 s. Sixteen samples per switching period are averaged to produce a digital equivalent of the average
inductor current. Since the switching frequency is relatively low,
a relatively low-cost A/D converter meets the requirement for
multiple samples of the inductor current per switching period.
Fig. 3 compares the timing diagrams of the predictive control
algorithm described in [16] with the timing diagram of the averaging approach described in this paper. In the predictive control
implementation, the current is sampled once per switching period and the next duty cycle value
is calculated during
the next switching period (corresponding to
s
in our prototype). If, for example, a short-circuit arc transient
occurs immediately after the sampling, the change will be observed after a delay equal to a switching period, and the control action will be executed as
, i.e., as much as two
switching periods (64 s) after the transient. This delay in reaction can potentially damage the plasma process. In the timing
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
Fig. 5. Small-signal model of the interleaved ZCT buck converter with the proposed average current-mode controller.
Fig. 4. Frequency responses of the averaging filter and the Bessel filter
approximation.
diagram of the method described in this paper, the averaging
filter outputs the average current value just before executing the
next switching pulse and the updated duty cycle is computed
with a delay of only 2 s.
In frequency domain, the effects of the delay associated with
the averaging filter can be inferred starting from the discretetime transfer function of the averaging filter (operating with the
sampling period of 2 s, or 1/16 of the switching period):
(1)
The magnitude and phase responses of the averaging filter
are shown in Fig. 4. Since the sampling is synchronized with
the switching frequency (with 16 samples per switching period)
the filter provides very high attenuation for the first seven harmonics of the switching frequency and significantly removes
the effects of the switching noise from the computed average
value. To account for the averaging filter responses in the current control loop that operates at the sampling rate equal to the
switching period, we approximate the filter low-frequency response as a fourth-order Bessel filter
with 31.5 kHz
cut-off frequency. As shown in Fig. 4, this filter approximates
the averaging filter response very well up to one-half of the
switching frequency. It can be observed that the phase response
corresponds to the effective delay of one-half of the switching
period.
Given the averaging filter that operates at the rate equal to
16 times the switching frequency, the antialiasing filter
is implemented as an analog second-order Bessel filter with a
cut-off frequency of 63 kHz. This filter provides 25 dB attenuation at one half of the sampling frequency (500 kS/s) of the
averaging filter, which further improves the system noise immunity without significant increases in the phase delay.
B. System Model and Current Loop Requirements
The complete equivalent continuous-time small signal model
of the system is shown in Fig. 5. It is a modified version of the
models described in [22]–[24].
is the analog antialiasing
filter,
is the constant current-sensing gain (including A/D
converter gain),
is the approximate continuous-time
Fig. 6. Small signal averaged switch model for the switch network of the interleaved ZCT buck converter.
model of the digital averaging filter,
models the delay of
the A/D converter (conversion time) as well as the loop calculation time, and
is the transfer function of the
discrete-time digital current-loop compensator
. The
small-signal averaged model of the switch network in the interleaved ZCT buck converter shown in Fig. 1 is shown in Fig. 6,
where the model parameters are as follows [9]:
(2)
is the dc conversion ratio
where
From the model, the converter
can be found as
.
transfer
functions
(3)
(4)
where
(5)
(6)
From (3) and (4) it follows that the ZCT converter responses
are similar to the responses of a conventional buck converter
except for a reduced -factor associated with lossless damping
due to zero-current transitions [9]. Also, from (4) and (6) we
note that the control-to-current gain
is inversely proportional to the load resistance .
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ILIC AND MAKSIMOVIC: DIGITAL AVERAGE CURRENT-MODE CONTROLLER
Fig. 7. Frequency responses of the control-to-current transfer function
two extreme operating points.
G
, for
The parameters in the experimental ZCT buck converter of
Fig. 1 are as follows:
H
F
V
V
kW
H
s
The load changes in a very wide range, from the minimum
V and
kW to the maxvalue of 3.6 at
imum value of 169 at
V and
kW. Wide
load variations result in wide variations of the control-to-current responses, as shown in Fig. 7. The low output load resistance results in high gain, low factor, and two real poles with
a dominant pole at 1.16 kHz. The high output load resistance
results in low gain (32 dB lower), high factor, and relatively
high peaking at the resonant frequency of the LC filter.
As mentioned earlier, because of the possibility that the
plasma behaves as a relatively large incremental negative
resistance, it is important to consider the current control loop
requirements in terms of the output impedance. From the
small-signal model in [9], the open-loop output impedance can
be found as
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Fig. 8. Magnitude and phase responses of the open-loop output impedance
Z
.
the output impedance is too low, the negative load impedance
can result in instability and oscillations. It is therefore desired
to achieve a current-loop bandwidth of several kHz, and a
closed-loop output impedance of at least 6 at lower power
levels.
From Fig. 5, the equivalent -domain current loop gain
can be found as
(8)
includes the current sensing gain and the
where
A/D converter gain, and the filter transfer functions are shown
in (9), at the bottom of the page.
Using the system model and the loop gain (8), the next section
describes a design of the digital current-loop compensator to
address the challenges of wide-bandwidth operation over the
very wide range of operating conditions.
III. CURRENT-LOOP COMPENSATOR DESIGN
A. PI Compensator Design
Consider a standard PI digital current-loop compensator
based on the continuous-time PI template
(7)
(10)
The magnitude and phase responses of the open-loop output
impedance are shown in Fig. 8. At frequencies up to about
1.5 kHz, the magnitude of the open-loop output impedance is
less than 6 . In experiments with different processes, negative
impedances as high as 6 have been observed at lower power
levels (less than 5 kW) in the frequency range of 0.5–20 kHz. If
The compensator is applied to the error
between the comset by the
puted average current and the current reference
outer power control loop. To provide some phase boost, the
compensator zero is placed at 600 Hz, below the power stage
(9)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
TABLE I
OUTPUT LOAD LOOK-UP TABLE
value for the output power . The look-up table is shown in
Table I.
Between the values listed in Table I, a linear interpolation is
used to determine the estimated load resistance as
(12)
where and refer to the indexes of the power and voltage entries, respectively, in Table I. The calculation in (12) can be further simplified by storing the multiplicative constants in a table.
, the table includes
For example, in addition to
Fig. 9. Magnitude and phase responses of the loop gain T for two operating
points.
(13)
Similarly, in addition to
, the table includes the constant
dominant pole frequency. The compensator pole is placed at
5 kHz, well above the target crossover frequency. The gain is
. Using standard zero-order hold mapping [25],
(10) is converted to a discrete-time compensator, which is implemented as
(11)
where the current error signal is calculated as the difference between the current set point and the computed inductor current
.
average value,
The magnitude and phase responses of the current loop gain
(8) with the PI compensator (11) are shown in Fig. 9 for the
two extreme operating points. For the minimum-load resistance
V,
kW, the loop crossover frequency
case of
is 2.6 kHz and the phase margin is about 40 . Unfortunately,
since the gain is inversely proportional to the load resistance,
as discussed in Section II, very different results are obtained
V,
for the maximum load resistance case of
kW. The crossover frequency is only 43 Hz, and therefore
the closed-loop bandwidth is very low in this case.
B. Adaptive Gain Adjustments
To correct for the wide variations in the loop gain, it is desirable to adaptively adjust the compensator gain in proportion to
. In adaptive control theory, the
the load resistance
approach of adjusting the compensator parameters in response
to changes in operating conditions is known as “gain scheduling” [26]. In the implementation described in this paper, the
is estimated using a look-up table based on
load resistance
the measured value of the output voltage
and the set-point
(14)
using Table I and
The maximum error in computing
(12)–(14) is 3%–4% at light load.
found from (12), the compensator template (10) is
With
modified to have the gain
proportional to
and equal to
V,
kW,
3.967 at the maximum power point (
). Then, using
,
a discrete-time compensator with adaptively adjusted gain is
obtained
(15)
The magnitude and phase responses of the loop gain with
adaptively adjusted gain of the compensator are shown in
Fig. 10. Note that the low-frequency responses are now almost
the same for the two extreme operating points. However, because of the increased factor in the maximum resistance case,
the loop gain does not cross zero, which results in instability of
the current loop at light load.
C. Improved Compensator Design
To correct for the stability problems at light loads, the compensator template (10) is further modified by adding a pole at
1.7 kHz
, and by reducing the adapin order to maintain adetively adjustable gain to
quate phase margins for all loads. The additional pole approxwhen the load resistance is
imately cancels the zero in
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ILIC AND MAKSIMOVIC: DIGITAL AVERAGE CURRENT-MODE CONTROLLER
1433
Using the system model in Fig. 5 and the power stage smallsignal model in Fig. 6, a small-signal model for finding the
closed-loop output impedance is shown in Fig. 12.
From Fig. 12, the closed-loop output impedance is found as
(18)
where
(19)
Fig. 10. Magnitude and phase responses of the loop gain T with adaptively
adjusted gain of the PI compensator, for two operating points.
The magnitude and phase responses of the closed-loop output
impedance are shown in Figs. 13 and 14 for the two extreme operating points, respectively. At low frequencies and low power,
the closed-loop output impedance is significantly higher than
open loop impedance.
IV. EXPERIMENTAL RESULTS
Fig. 11. Magnitude and phase responses of the loop gain T with adaptively
adjusted gain of the improved compensator, for two operating points.
very high. The modified continuous-time compensator template
is
(16)
which, using the zero-order hold mapping [25] together with the
, results in the following
adaptive gain adjustments,
discrete-time realization
(17)
The resulting magnitude and phase responses are shown in
Fig. 11. The crossover frequency and therefore the closed-loop
bandwidth vary from 1.12 kHz for the minimum load resistance
case to about 2.79 kHz for the maximum load resistance case.
The phase margins are 47 and 70 , respectively.
The controller has been implemented using a TI DSP
TMS320C2407 and a XILINX Spartan 3 FPGA. DSP runs
the external power loop, handles user I/O communication, and
for adaptive gain calculations.
estimates the load impedance
The power loop includes a simple integral compensator, and
has a closed-loop bandwidth of less than 300 Hz. As a result,
the power control loop does not affect the closed-loop output
impedance in the range of frequencies of interest (0.5–20 kHz).
The FPGA processes current samples including digital averaging filter, computes the duty-cycle command based on the
improved compensator (16) with adaptively adjusted gain, and
implements the digital PWM (DPWM). The compensator calculations on the FPGA are performed in fixed-point arithmetic
using 18-bit built-in hardware multipliers. The switching period
is 32 s and the DPWM time resolution is 20 ns, which gives
11 bits of DPWM resolution, sufficient to avoid limit cycling
oscillations [27], [28].
The experimental prototype has been tested with plasma load.
Fig. 15 shows the output voltage and output current waveforms
obtained with the simple PI controller (10), at a low output
kW). At this operating point, the plasma
power set point (
incremental negative impedance is estimated at
. Since the
current loop crossover frequency is very low, as shown in Fig. 9,
the power supply output impedance is low (less than 3.2 ). The
resulting instability leads to oscillations at about 800 Hz, which
can be observed in Fig. 15. Fig. 15 also shows how arcs result
in temporary short-circuit conditions at the output.
Under the same conditions, the improved compensator (16)
with adaptive gain adjustment results in stable operation, as
shown in Fig. 16. In plasma applications, the anode (positive terminal) is grounded, which is why the voltage and current waveforms are shown as negative values.
Comparisons of predicted and measured frequency responses
of the current loop gain in Figs. 17 and 18 provide further verification of the power supply performance using the improved
compensator with adaptive gain adjustment.
Fig. 17 shows a comparison between simulated and measured
results for the magnitude and phase responses of the current loop
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
Fig. 12. Model for output impedance calculation.
Fig. 13. Closed-loop output impedance: V = 300 V, P = 25 kW.
Fig. 15. Experimental waveforms (2 ms/div) illustrating instability at P =
5 kW set point with plasma load, for the power supply using the simple PI
compensator (11).
Fig. 14. Closed-loop output impedance: V = 650 V, P = 2:5 kW.
gain for the output load of
, and the output power
of
kW, while Fig. 18 shows the corresponding results
for the output load of
and the output power of
kW. The measured results are consistent with the model
predictions: the proposed approach results in sufficiently high
Fig. 16. Stable operation at P = 5 kW set point with plasma load (2 ms/div),
for the power supply using the improved compensator (16) with adaptive gain
adjustment.
crossover frequencies and phase margins over the wide range of
output power levels.
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ILIC AND MAKSIMOVIC: DIGITAL AVERAGE CURRENT-MODE CONTROLLER
Fig. 17. Magnitude and phase responses of the loop gain T with adaptively
adjusted gain of the improved compensator, for R = 3:6 , P = 25 kW:
simulated versus measured results.
Fig. 18. Magnitude and phase responses of the loop gain T with adaptively
adjusted gain of the improved compensator, for R = 167 , P = 2:53 kW:
simulated versus measured results.
1435
Fig. 20. Current loop transient response for load change from 10
(0.2 ms/div).
to 5 Fig. 21. Transient response for a power set point change from 1 kW to 15 kW
(2 ms/div).
Fig. 20 shows a transient response of the inner current loop for
the load change from 10 to 5 . The settling time of about 0.5 ms
is in agreement with the designed current loop bandwidth, which
is greater than 1 kHz at all operating points.
A step transient output power response (power set point
changed from 1 to 15 kW) of the system with resistive load is
shown in Fig. 21.
V. CONCLUSION
Fig. 19. Current loop transient response for load change from 5
(0.2 ms/div).
to 10 Fig. 19 shows a step load transient response of the inner current loop: the current set point is constant (approximately 30A)
and the resistive load is changed from 5 to 10 . Similarly,
In this paper we present a digital average current mode controller suitable for power supplies in PVD applications where
challenges include very wide ranges of operating conditions,
and a noisy environment due to arc transients or operation of
multiple converters in parallel. The current control loop uses an
averaging filter to enhance immunity in the noisy environment.
The current loop calculation is executed in less than 2 s on a
TI DSP TMS320C2407/Spartan 3 combination, which results in
fast response times to arc transients. The current loop crossover
frequency is between 1 and 3 kHz using a PI compensator with
adaptive gain adjustments to address operation over very wide
ranges of output voltage and load. An outer power control loop
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
and the inner adaptive average current control loop are implemented on a digital signal processer/field-programmable gate
array digital control platform and the performances are verified
on a 25 kW (300 V, 83.3 A) experimental interleaved zero current transition buck prototype.
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Milan Ilic (M’91) received the B.S. and M.S. degrees in electrical engineering from the University
of Belgrade, Yugoslavia, in 1984 and 1987, respectively, and the Ph.D. degree from the University of
Colorado, Boulder, in 2007.
From 1984 to 1994, he was with the Department of
Electronics at the Faculty of Electrical Engineering,
Belgrade as a Teaching and Research Assistant. From
1997 to 2001, he was with Corporate Research and
Development, General Electric Company, Schenectady, NY where he was involved in design of medical electronics. Since 2001, he has been with Advanced Energy Industries, Fort
Collins, CO. His current research areas include high frequency high power supplies, digital control techniques, and power supplies for special applications.
Dragan Maksimovic (SM’05) received the B.S. and
M.S. degrees in electrical engineering from the University of Belgrade, Yugoslavia, in 1984 and 1986,
respectively, and the Ph.D. degree from the California
Institute of Technology, Pasadena, in 1989.
From 1989 to 1992, he was with the University
of Belgrade, Yugoslavia. Since 1992, he has been
with the Department of Electrical and Computer
Engineering, University of Colorado at Boulder,
where he is currently a Professor and Director of the
Colorado Power Electronics Center (CoPEC). His
current research interests include digital control techniques and mixed-signal
integrated circuit design for power electronics.
Dr. Maksimovic received the NSF CAREER Award in 1997, the Power Electronics Society TRANSACTIONS Prize Paper Award in 1997, the Bruce Holland
Excellence in Teaching Award in 2004, and the University of Colorado Inventor
of the Year Award in 2006.
Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on September 9, 2009 at 14:15 from IEEE Xplore. Restrictions apply.
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