F-41D_PDP4brochure_Sep63

F-41D_PDP4brochure_Sep63
PROG RAM M ED DATA PROCESSOR-4
F·41D
DIGITAL EQUIPMENT CORPORATION
Los Angeles
San Francisco
•
Washington
MAYNARD,
Parsippany, N.J.
MASSACHUSETTS
Ottawa
DIGITAL EQUIPMENT CORPORATION.
Munich
'0
10 M·9/63
PRINTED IN U .S .A .
F·4ID
MAYNARD,
MASSACHUSETTS
P
gra
d Data Processor -
(PDP-4) is a general purpose, high speed, solid state
computer designed to be the control element in an information processing system or a complete
scientific compl,Jter. It is a single address, parallel, binary machine with an 18-bit word length
using l's or 2's complement arithmetic. A random access magnetic core memory with a complete cycle time of 8 microseconds is used to achieve a computation rate of 62,500 additions
per second. Other features include:
•
OP"R N II COMPILER Including symbolic assembly with debugging and floating
point arithmetic packages.
TIMe. C N ROL Provides buffering and control for multiple input-output conE
nections, program and data interrupt facilities, and a real time clock. >
L IP
0 DE ING Eight Auto-Indexing Memory locations simplify programming and increase the speed of table look-up and other routines.
P 10
D
IG
completely executed.
Basic instructions require only 8 or 16 microseconds to be
Provides facilities which simplify and speed
up multiple precision
operations.
Programmed Data Processor-4 has been
developed to meet the requirements of the
engineering and scientific profession. Special emphasis has been placed on a powerful input-output interface in the computer.
Extensive applications in the system control and data reduction fields are well
within PDP-4's capability.
2
Magnetic Drums, Display Scopes , Magnetic Tape, Line
Printers, Punched Cards, Punched Tape, and Analog Converters.
•
... AL MfMORY EXPANSIO
Provision is made for memory expansion up
to 32K .
Adds 23 instructions to a standard
PDP-4 including Multiply, Divide, Normalize and Long-Shift.
Copyright 1963 by Digital Equipment Corporation
3
STANDARD PDP-4
The PDP-4 includes all essential elements for
optimum performance as a systems component.
The standard machine consists of:
ACS
CENTRAL
PROCESSOR
CONTROL
A CENTRAL PROCESSOR which performs
arithmetic operations, controls the memory,
and handles information entering and leaving
the machine;
ACCUMULATOR
SWITCHES
18
INSTRUCTION
REGISTER
MA
MEMORY
ADDRESS
13
MEMORY
A REAL TIME CONTROL - which provides the
computer with an additional capability to operate a large variety of input-output devices with
different information handling rates.
AN OPERATOR CONSOLE - which contains all
controls needed to observe and modify the status of the Central Processor;
A PAPER TAPE READER which permits
information and instructions to be read from 5,
7 or 8 -hole perforated paper tape into the Cen tral Processor at the rate of 300 lines per
second.
A 4096-WORD MEMORY - which provides storage for information being collected or distributed and instructions for the Central Processor;
Various options which extend the usefulness of
the PDP-4 are described on Pages 7, 8 and 9.
4096
WORDS
CENTRAL
PROCESSOR
I
--- --- -t
~------~~~------------~--~----~I
I
REAL TIME CONTROL
~------~--------~----------~------~I
I
I
\' -____________
J
~y~-------------J
INPUT-OUTPUT DEVICES
PDP-4 SYSTEM DIAGRAM
ENTRAL PROCESSOR
OPTIONS
BLOCK TRANSFER DRUM SYSTEMTYPE 24
The Type 134 extends the memory capacity of
the PDP-4 from 4096 to 8192 words. Additional
modules require the use of a memory extension
control (see below).
The drum system operates on a serial transfer
basis in 256-word blocks. It is available in three
capacities: 16, 32, 65 thousand words.
CORE MEMORY MODULE-TYPE 135
The Type 135 extends the memory capacity of
the PDP-4 by 8192 words.
CORE MEMORY EXTENSION
ONTROl - T PE 16
The Type 16 extends the memory control capa bility of the PDP-4 from 8192 to 32 ,768 words _
4
-
FIRST EXTRA 4096-WORD
CORE MEMORY MODULE-TYPE 134
EXTENDED ARITHMETIC ElEMENTTYPE 18
~he
Extended Arithmetic Element (EAE) adds
23 micro coded instructions to PDP-4 which facilitate high speed multiplication, division, and
shifting. The EAE contains an 18-bit register,
the Multiplier Quotient (MQ); a 6-bit register,
the Step Counter (SC); and a 3-bit Instruction
Register.
5
REAL TIME CONTR L
provides program
skip instructions conditioned by the state of
input·output device logic lines. The instruction
following a skip instruction will not be executed
if the line is active.
The Real Time Control of the PDP-4 provides
the following functions:
consists of decoding
elements to select and control external devices
by various combinations of input-output transfer instructions. Pulses may be used to: (a)
control external devices; (b) read out information from PDP-4 through the Information Distributor; (c) read in information to PDP-4 through
the Information Collector, and (d) test the status
of external devices.
INPUT-OUT UT OPTI 'NS
Cathode Ray Tube Displays
either graphical or tabular data. Separately
variable 10-bit X and Y coordinates and programmable intensity control.
permits conditions
from input-output devices to interrupt the pro·
gram and initiate a subroutine which may return
to the original program when the cause for interruption has been processed. The machine
state is preserved during a Program Interrupt.
This type of interrupt is suited for information
or event rates in the range of 1 to 2,000 cycles
per second.
information is
received from input devices (selected by the
Device Selector) and is transferred to the Central Processor. Information is read in parallel
(up to IS bits) from multiple inputs.
A photoelectric device with which the operator
can sense displayed data and input modifying
signals to the computer. The computer can then
change its operation according to previously
programmed instructions.
RATOR - allows a device to interrupt the program and deposit or extract data
from the Core Memory at an address specified
by the device. The Data Interrupt is suited for
high speed information transfers. Up to 125,000
IS-bit words may be transferred per second.
permits distribution of information from the Central Processor to all output devices. Only the output
device selected (or addressed) by the Device
Selector samples and reads the information
contained in the Information Distributor.
- produces a signal which
increments a Core Memory register at a rate of
60 cycles per second. When the register overflows, a Program Interrupt occurs.
Automatically translates digital computer words
into format information for display. Plots symbols on a 35·dot matrix in one of four sizes on
the Type 30 CRT Display. Average plotting rate:
140 microseconds per symbol.
Displays data on a 16-inch cathode ray tube.
Information is plotted point by point to form
Plots data point by point on a Textronix oscilloscope.
Ten bits per axis. (Osci lIoscope not
included.)
REAL TIME CONTROL
lOT Pulses (3 x 20)
(3 x64 Max)
Jumper Connections
To 10 Devices. IC, and lOS
From DS _"7.I;:::OT~pu~ls:;:es~~-===:::-:=:-,
(8 x 18 Max)
..-=L;;.;.ine::s:-'(7;....;X::....:l""8)~--====--I
From Input Devices ....:D;.::.at:.;;.
18
from 10 Device Flags
--....!.::'---...~~~~J
Data Lines (18)
To Input Devices
Selected lOT
From DS _....::P!!!UI~ses!...l.!(1~6)_+r_-;;:;;;;-;:;----,
From 10 Device Flags --=.::.:....=-~_-=~.--J
From 10 Device Flags
Paper Tape and Card Equipment
_==::....>.:;::..L.-~
Request
_D: : :a~ta: ?D: : ire: ; ct: : :io:! . n.....:~I_I::.:.NT.:..::~::.::~1::.::'U::..:PT:.......JI--...::D:::;at::..a--+- Request Acknowleged
(in out)
13 Address
Operates at a rate of up to 200 cards per minute. Cards are read column by column. Column
information may be read in alphanumeric or
binary mode. The alphanumeric mode converts
the 12-bit Hollerith Code of one column into the
6·bit binary-coded decimal code with code validity checking. The binary mode reads a 12-bit
column directly into the PDP-4. Approximately
one per cent of a Card Reader program running
time is required to read the SO columns of information at the 200 cards per minute rate.
minute. Approximately 0 .3 per cent of program
running time is required to operate the Card
Punch at the 100-card-per-minute rate. Buffer
holds one SO-bit row.
c
18 Incomi ng
Data
I - - - - - C > 18 OutgOing Data
6
Enables the operation of a standard IBM Type
523 Summary Punch with PDP-4. Cards are
punched row by row at a rate of 100 cards per
The Type 75 is a Teletype BRPE Punch with an
operating speed of 63.3 lines or characters per
second. It punches 5, 7 or S-hole tape. (Shown
with Standard Perforated Tape Reader.)
7
Printers
second. The number of characters per inch is
variable from 1 to 200; the number of bits per
character is 7.
AUTOMATIC LINE PRINTER AND
CONTROL- TYPE 64
Prints 300 lines per minute, 120 columns per
line, 64 characters per column.
.
PRINTER-KEYBOARD AND CONTROLTYPE 65
The Type 65 is a Teletype Model KSR·2S Printer
and Keyboard with an input and printing speed
of 10 characters per second.
Magnetic Tape Equipment
AUTOMATIC MAGNETIC TAPE
CONTROL-TYPE 57A
'VIAGNETIC TAPE CONTROL-TYPE 54
Controls up to four Magnetic Tape Transport
Units, Type 50. Information is read from or
written on the tape under program control.
Subroutines are available to read and write IBM
compatible tapes having a density of 200 , 6
1 bit characters per inch.
+
S
Fixed address magnetic tape for high speed
loading and readout as well as program updating. Two logically independent tape drives handle 260 foot pocket-size reels of % inch Mylar
tape at a speed of SO inches per second. Information is written on non·adjacent, redundant
tracks in the Phase Recording System at densi·
ties of 375 bits per track inch and may be transferred at a rate of 90,000 bits per second. Tape
handling and utility transfer relutines available.
In-Out Connections and Controls
18-BIT OUTPUT RELAY BUFFER TYPE 140
fer between the computer and external devices
at word rates to 125 KC.
Provides contacts which operate devices of
higher power rating. The relays have form "0"
contacts, which open and close in approximately
3 milliseconds.
CL C
INTERFACE FOR IBM 7090
CONNECTION - -YPE 50
Controls a maximum of eight tape transports
automatically. Provides information transfer
through computer's data interrupt facility. Con ·
trois reading or writing of tape at various rates
compatible with IBM, BCD or binary parity
modes.
The Type 57A can be used in conjunction with
one of the following interfaces.
Tape Control Interface Type 520 - permits
attachment of the Type 50 Tape Transport.
Tape Control Interface Type 521 - permits
attachment of the Type 570 Tape Trans·
port.
Tape Control Interface Type 522 - permits
attachment for one of the following type
transports: IBM series 729 model II, IV,
V, VI or IBM series 7330. Character trans·
fer capabilities of 7.2 to 90 KC at densities
of 200, 556, and SOO.
MICRO TAPE DUAL TAPE TRANSPORT
AND CONTROL - TYPE 555-550
Provides communication between PDp·4 and
IBM 7090 at a 10,000 cps, lS·bit word rate.
DATA CONT
E 3'
Controls and double buffers high speed trans·
~
IPLE
TYPE 132
Provides 16 inputs to the POP-4 enabling 16
memory registers to be used as IS-bit counter.
Priority addressing system permits combined
input counting rate to 125,000 cps.
..,
lEU
DE 33
VI L
It"L~
ER-
Provides high·speed 'transfer between PDp·4
Core Memory and three input·output devices.
Maximum combined transfer rate: 125,000 cps,
IS-bit words.
Analog-to-Digital Equipment
!.
GENERAL PURPOSE ANALOG TO
o VE -~
VPE 138
HIGH SPEED ANALOG TO DIGITAL
A general purpose ' analog to digital converter
used to convert input analog voltages into digi·
tal numbers for computer entry.
Converts analog signals to digital information
with 10·bit accuracies in S microseconds for
com puter ent ry.
GENERAL PURPOSE 64 CHANNEL
MULTIPLEXER CONT~OL - TYPE 1
Controls up to 64 channels of analog input to
be multiplexed into the analog to digital con·
verter.
HIGH SPEED MULTIPLEXER CONTR
- ..
High speed multiplexer for use with the Type
142 Analog to Digital Converter.
Special purpose analog to digital converters , multiplexers, multiplex switches, digital to
analog converters, plotters and loggers with various speeds , accuracies, and input ranges
are available for special requirements.
9
PDP-4 Instructions
Mnemonlc
Code
MEMORY REFERENCE INSTRUCTIONS
Addressable or memory reference instructions which
a memory address. The address portion of the instruction
word specifies the location of an operand in the memory.
I
Mnemonic
Code
Octal
Code
Time
(psec)
cal
00
16
The PDP-4 instruction format includes 4 bits for
instruction code, 1 bit for indirect modified addressing and 13 bits for memory address or
variations of the basic instructions.
dac Y
04
16
0123456789 10 11 12 13 14 15 16 17
Instruction
~l'
Code
Indirect Bit
Operand Address
jms Y
10
Same as jms 20. The address portion
of this instruction is ignored. The
cal instruction may be used for
calling subroutines via a master cen.tral program which keeps track 0
exit addresses, allocates storage,
and supplies parameters to the subroutines.
Operating times of PDP-4 instructions are in
multiples of the 8 microsecond memory cycle.
Add, deposit, and load for example , are twocycle instructions completed in 16 microseconds. Input-output connections are programmed
by specifying iot instructions which affect the
state of selected devices. The instructions may
be microprogrammed to allow one basic instruction to handle one or more devices by changing
the bits of the command.
dzm Y
lac Y
xor Y
add Y
tad Y
14
20
24
30
34
16
Deposit zero in memory. The contents of register V are changed to
zero. The original contents of Yare
lost.
16
Load AC. The C(V) replace the C
The previous C(AC) are lost.
C(V) are unaffected.
16
Exclusive OR. The exclusive "OR"
logical function is performed on a
bit-by-bit basis between the C(AC)
and C(Y). The result is left in the
AC and the original C(AC) are lost.
16
Add (ONE's Complement). The C(V)
are added to the C(AC) in ONE
complement arithmetic. The result
left in the AC and the original C(AC)
is lost. This type add instruction is
commonly used for most arithmetic.
The Link bit is set to a ONE if the
sum of the magnitude of C(V) and
C(AC) is greater than 2" - 1.
16
Add (TWO's Complement). The C(V)
are added to C(AC) in TWO's
plement arithmetic. If there is
carry out of bit 0, the Link will be
set to ONE. This type of add in·
struction is useful in multiple pre·
cision arithmetic.
!II
10
iszY
44
and V
16
50
16
•
•
•
•
sad Y
jmpy
16
54
8
60
ment. This is a micro program instruction using bits 4-17 to specify
the desired operations. Combinations of the individual operations
can be made. The operations are
specified by bits as follows
Operation
40
8+ The instruction in register Y will be
instruction executed. The computer will act as if
execute
the instruction located in V were in
time
the place of the xct Y.
Deposit Accumulator. C(AC)* are
deposited in memory register V.
The C(AC) are unaffected by this
operation.
+
When the indirect bit is a ONE , indirect address ing (or deferring) is specified . A defer memory
cycle is required during which time the contents
of the memory cell addressed are selected and
the address part of this cell is used as the effec tive address of the original instruction . The
instruction part of the cell and the indirect bit
are ignored when obtaining the effective address. In addition , if the cell indirectly addressed
is lO a-17 a, a ON E is added to the contents of
that cell before the address part is used as the
effective address (auto-indexing).
Time
(psec)
xct V
Operation
Jump to Subroutine. C(PC) are
posited in memory register Y. Th
next instruction will be taken from
V
I, the beginning of the subroutine.
16
•
Octal
Code
Index and Skip if zero. The C(Y) are
replaced by C(y)
1. The C(AC) are
unaffected by this instruction. The
addition is done using two's comple·
ment arithmetic. If the sum is +0,
the next instruction is skipped.
+
Logical AND. The logical "AND"
function is performed on a bit-by-bit
basis between C(AC) and C(Y). The
result is left in the AC and the original C(AC) are lost.
C(Y) are compared with the C(AC).
If the two numbers are different, the
next instruction in the sequence is
skipped. The C(AC) and C(Y) are
both unaffected by the instruction .
Jump. The C(PC) are reset to address V. The next instruction to be
executed is taken from memory
register Y. The original contents of
the PC are lost.
AUGMENTED INSTRUCTIONS
Augmented instructions provide micro programming capability by using the address portion of the instruction to select
logical operations. These instructions do not address a
memory register.
Mnemonic Octal
Code
Code
cma
cml
oas
ral
rtl
rar
rtr
hit
sma
spa
sza
sna
snl
szl
skp
cll
cia
1
2
Complement AC.
Complement Link.
Inclusive OR AC switches with AC.
4
10
Rotate AC and Link left one place.
2010 Rotate AC and Link two places left.
Rotate AC and Link right one place.
20
2020 Rotate AC and Link two places right.
Halt the machine
40
Skip on minus AC. If AC o = I, the next
100
instruction In sequence is skipped.
1100 Skip on plus AC. If AC o
0, the next
instruction in sequence is skipped.
200
Skip if AC
O.
1200 Skip if AC :t: O.
400
Skip if Link :t: O.
1400 Skip if Link
O.
1000 Skip unconditionally.
4000 Clear Link.
10000 Clear AC.
=
=
=
76
8
Mnemonic
Code
Octal
Code
iot
70xxxx
Time
(psec)
8
The address postion of this instruction may be used to specify a
constant.
The operate instructions use bits 5 through 17 to specify
variations of the basic instructions.
opr
74xxxx
8
Operate. The operate instruction is
also the conditioning (skip) instruction. When a particular condition is
present, the following instruction will
be skipped. The various micro program events occur at different times
to allow several events to be programmed which affect the same ele-
2,3
3
2,3
4
1
1
1
1
1
1
1
2
2
Operation
In Out Transfer. This instruction
which forms a micro program is used
to select an input or output device.
The instruction forms a micro program and has the following format:
Function
OPERATE GROUP
3
3
3
3 ,
IN-OUT TRANSFER GROUP
The instructions in this group are similar to the Operate
Group instructions except they pertain to the transfer of information between the Central Processor and various inputoutput devices. Bits 4 through 17 select and control inputoutput devices.
The following instruction loads itself into the AC.
law
SltIuence of
Occurrence
Opll'ltion
Specifies the in-out instruction
(Operation Code 1110)
May be used to select sub·device
Selects the device
May be used to select sub·device
Clears the AC at event time 1 if a ONE
Transfers an lOT pulse at event time 3 if a ONE
Transfers an lOT pulse at event time 2 if a ONE
Transfers an lOT pulse at event time 1 if a ONE
Command Bits
0·3
4·5
6·11
12-13
14
15
16
17
Bits 13· 17 may be used together in any combination to allow
various types of in·out command structures, and these may
handle 1, 2 , or 3 devices per selection (bits 4·12) depending
upon the requirements of the devices.
C(AC): contents of the accumulator.
11
PROGRAMMING AIDS
The PDP-4 Programming System includes FORTRAN II, a Symbolic Assembly
and Debugging System, maintenance routines, and numerous other programming aids_
FORTRAN II
Keys and toggle switches available on the
PDP-4 control panel provide maximum ease of
operation . Their functions are as follows:
Console Keys
START
Starts the processor. The first instruction is
taken from memory cell specified by the setting
of the ADDRESS switches. The START operation
clears the AC and Link, and turns off the Program Interrupt.
STOP
Causes the processor to halt functional operations at the completion of the memory cycle in
progress at the time of key operation.
CONTINUE
Causes the processor to resume operation beginning at the address specified by the Program
Counter (PC).
EXAMINE
Sets the contents of the memory location indicated by the Address Switches into the Accumulator (AC) and Memory Buffer.
The Memory Address Register will contain the
address of the memory location being examined and the program counter will contain the
address of the next location.
DEPOSIT
Sets the word selected by the Accumulator
Switches (ACS) into the memory at the location
specified by the Address Switches. The results
will remain in the Accumulator and the Memory
Buffer. The Memory Address Register will contain the address of the memory location holding
the information, and the Program Counter will
contain the address of the next location.
12
EXAMINE NEXT
Sets the contents of the memory at the address
specified by the Program Counter into the Accumulator and the Memory Buffer. The C(PC) .
are indexed by one, and the Memory Address
Register will contain the address of the location
examined.
DEPOSIT NEXT
Sets the contents of the Accumulator Switches
into the memory at the location specified by the
Program Counter. The C(PC) will be indexed
by one, and the Memory Address Register will
contain the address of the location holding the
information.
PDP-4 FORTRAN II allows the programmer an
unusual degree of freedom in many instances:
For example, mixed expressions and n-dimensional arrays are allowed. An important feature
is the retention of the original symbols from the
FORTRAN source language tape through the
PDP-FORTRAN II FEATURES
FIXED POINT
CONSTANTS:
1-6 decimal digits absolute value ~ 131,071
FLOATING POINT
CONSTANTS:
10 decimal digits precision. Exponent range 2(2 17-1)
to-2(2 17-1)
VARIABLE NAMES:
1-6 alphanumeric characters
SUBSCRIPTS:
Any arithmetic expression representing an integer
quantity: Variables in a subscript m'ay themselves be
subscripted to any depth. N dimensional arrays are
permitted.
STATEMENTS:
Mixed expressions containing both fixed and floating
point variables are permitted. A maximum of 300
characters are allowed (statement numbers not
counted)
Console Toggle Switches
POWER
Turns on the power.
SINGLE STEP
Causes the processor to halt at the completion
of each memory cycle. This switch is particularly useful in maintenance tasks. Repeated
operation of the Continue Key will step the program one cycle at a time so that the state of
the machine can be examined at each step.
STATEMENT
NUMBERS:
Subroutines not contained in the FORTRAN library
may be compiled by the use of Function and Subroutine statements. Functions and subroutines may
be fixed or floating point valued as defined by initial
letter of F-type function convention. Arguments
may be arbitrary arithmetic expressions, including
functions.
INPUT AND OUTPUT:
MICRO-TAPE, paper tape, punched cards, teletype,
display. Format may be specified by use of a
FORMAT statement.
STATEMENTS
AVAILABLE:
Arithmetic statements, I/O statements with FORMAT,
DO, Dimension, Common, IF, GOTO, Assign, Continue, Call, Subroutine, Function, Return.
Causes the processor to stop at the completion
of each instruction.
REPEAT
S E
Controls the speed of the repeat function.
1-99999
FUNCTIONS AND
SUBROUTINES:
SINGLE INSTRUCTION
Causes operations initiated by console keys to
be repeated as long as the keys are depressed_
The operations are performed at the rate set
by the Speed Switch.
final binary program, making the system easy
to use and reducing debugging time. Compilation of the original FORTRAN source program
is performed alone, with subprograms compiled
and assembled separately. Hence, should mistakes occur in FORTRAN coding, only the main
program need be recompiled.
13
Utility Routines
Symbolic Assembly and
Debugging System
AS-....
BLY PROGR
DDT
A one·pass assembler that allows mnemonic
symbols to be used for addresses and instruc·
tions. Constant and variable storage registers
are automatically assigned. This assembler wiil
produce relocatable or absolute binary output,
as desired by the user.
L
T
N~
0
0
Performs relocation and linking of binary pro·
grams that have been assembled separately.
'DE
0-
CAL
C TAPE-4
Debugging may be done at run time using the
teleprinter. Break points may be inserted into
a program at arbitrary points so that the state
and operation of a program may be observed.
The source program symbols may be used for
communication.
o
PUNCI-I ROUTINES
AN LER
Facilitates the calling of subroutines. Permits
greater freedom in the use of subroutines, in·
cluding recursive calls.
T R
o
.... R
Verifies and duplicates tapes.
Maintenance Routines
T ....
Allows the editing of symbolic tapes.
Many of these maintenance routines are also
used on DEC's standard acceptance tests. Spe·
cial I/ O test programs are available as required.
E
Arithmetic Routines
(Continuous Test) Repeatedly tests all basic
machine functions.
C 10
DOUBLE PRECISION
A collection of subroutines which allow the user
to perform double precision arithmetic with
35·bit signed numbers.
s
Single precision signed one's complement.
Performs operations upon floating point numbers, with approximately 10 decimal digits of
Allow punching in either block format binary or
read·in mode format.
precIsion, and an exponent which may be as
large as 2(2 17'1) in magnitude.
Provided by the Extended Arithmetic Element
Type 18, also includes shift and normalize func·
tions permitting fast floating point operations.
T
A sequence of programs which test the opera·
tion of all PDp·4 instructions except the iot
group.
EC
o
IND ,..
Maintenance programs to check the memory
module for proper address selection.
EA -
E
Checks the operation of the reader and punch
using different patterns and variable times.
E E
E
Tests the input and output facilities of the tele·
printer by repeating the typed message, echo
checking, etc.
Provides continuous memory testing with four
different patterns.
Routines to calculate floating point, arctan (x),
sin (x), cos (x), ex, log (x), xv, {X.
lID Programs
Facilitates use of Type 57A and Type 54 Control units.
Tracks the light pen across the face of the
Type 30 Precision CRT Display.
....
For use with Micro Tape 555.
A high speed plotting routine for use with the
Type 33 Symbol Generator.
14
,.. ,
Permits simultaneous use of the paper tape
reader, paper tape punch, card reader, card
punch, high speed line printer, teleprinter and
keyboard, buffering all input and output.
15
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