bq2004E/H Fast-Charge ICs Features General Description
bq2004E/H
Fast-Charge ICs
Features
General Description
ture and voltage are within configured limits.
➤ Fast charge and conditioning of
nickel cadmium or nickel-metal
hydride batteries
The bq2004E and bq2004H Fast
Charge ICs provide comprehensive
fast charge control functions together
with high-speed switching power control circuitry on a monolithic CMOS
device.
Temperature, voltage, and time are
monitored throughout fast charge.
Fast charge is terminated by any of
the following:
➤ Hysteretic PWM switch-mode
current regulation or gated control of an external regulator
➤ Easily integrated into systems or
used as a stand-alone charger
➤ Pre-charge qualification of temperature and voltage
➤ Configurable, direct LED outputs
display battery and charge status
➤ Fast-charge termination by ∆ temperature/∆ time, peak volume detection, -∆V, maximum voltage,
maximum temperature, and maximum time
➤ Op t i o n al to p - o f f char g e a nd
pulsed current maintenance
charging
➤ Logic-level controlled low-power
mode (< 5µA standby current)
Pin Connections
Integration of closed-loop current
control circuitry allows the bq2004
to be the basis of a cost-effective solution for stand-alone and systemintegrated chargers for batteries of
one or more cells.
Switch-activated discharge-beforecharge allows bq2004E/H-based chargers to support battery conditioning
and capacity determination.
High-efficiency power conversion is
accomplished using the bq2004E/H as
a hysteretic PWM controller for
switch-mode regulation of the charging current. The bq2004E/H may alternatively be used to gate an externally regulated charging current.
Fast charge may begin on application
of the charging supply, replacement
of the battery, or switch depression.
For safety, fast charge is inhibited
unless/until the battery tempera-
Rate of temperature rise
(∆T/∆t)
n
Peak voltage detection (PVD)
n
Negative delta voltage (-∆V)
n
Maximum voltage
n
Maximum temperature
n
Maximum time
After fast charge, optional top-off
and pulsed current maintenance
phases with appropriate display
mode selections are available.
T h e b q 2 0 0 4 H d if f er s f r om t h e
bq2004E only in that fast charge,
hold-off, and top-off time units have
been scaled up by a factor of two,
and the bq2004H provides different
display selections. Timing differences between the two ICs are illustrated in Table 1. Display differences are shown in Table 2.
Pin Names
DCMD
Discharge command
SNS
Sense resistor input
DSEL
Display select
LED1
Charge status output 1
VSEL
Voltage termination
select
LED2
Charge status output 2
VSS
System ground
VCC
5.0V ± 10% power
MOD
Charge current control
DIS
Discharge control
output
INH
Charge inhibit input
DCMD
1
16
INH
DSEL
2
15
DIS
VSEL
3
14
MOD
TM1
4
13
VCC
TM1
Timer mode select 1
TM2
5
12
VSS
TM2
Timer mode select 2
TCO
6
11
LED2
TCO
Temperature cutoff
TS
7
10
LED1
BAT
8
9
SNS
TS
Temperature sense
BAT
Battery voltage
16-Pin Narrow DIP
or Narrow SOIC
n
PN2004E01.eps
SLUS081A - APRIL 2005
1
bq2004E/H
SNS
Pin Descriptions
DCMD
SNS controls the switching of MOD based on
an external sense resistor in the current
path of the battery. SNS is the reference potential for both the TS and BAT pins. If
SNS is connected to VSS, then MOD switches
high at the beginning of charge and low at
the end of charge.
Discharge-before-charge control input
The DCMD input controls the conditions
that enable discharge-before-charge. DCMD
is pulled up internally. A negative-going
pulse on DCMD initiates a discharge to endof-discharge voltage (EDV) on the BAT pin,
followed by a new charge cycle start. Tying
D C M D to g r o und e nabl e s a u t om a t ic
discharge-before-charge on every new charge
cycle start.
DSEL
LED1–
LED2
Display select input
Vss
Ground
This three-state input configures the charge
status display mode of the LED1 and LED2 outputs and can be used to disable top-off and
pulsed-trickle. See Table 2.
VCC
VCC supply input
5.0V, ±10% power input.
MOD is a push-pull output that is used to
control the charging current to the battery.
MOD switches high to enable charging current to flow and low to inhibit charging
current flow.
DIS
Timer mode inputs
INH
Temperature sense input
Input, referenced to SNS, for an external
thermister monitoring battery temperature.
BAT
Charge inhibit input
When low, the bq2004E/H suspends all
charge actions, drives all outputs to high impedance, and assumes a low-power operational state. When transitioning from low to
high, a new charge cycle is started.
Temperature cut-off threshold input
Input to set maximum allowable battery
temperature. If the potential between TS
and SNS is less than the voltage at the TCO
input, then fast charge or top-off charge is terminated.
TS
Discharge control output
Push-pull output used to control an external
transistor to discharge the battery before
charging.
TM1 and TM2 are three-state inputs that
configure the fast charge safety timer, voltage
termination hold-off time, “top-off ”, and
trickle charge control. See Table 1.
TCO
Charge current control output
Voltage termination select input
This three-state input controls the voltagete r m i nat i o n te chni q ue us ed b y t h e
bq2004E/H. When high, PVD is active.
When floating, -∆V is used. When pulled low,
both PVD and -∆V are disabled.
TM1–
TM2
Charge status outputs
Push-pull outputs indicating charging
status. See Table 2.
MOD
VSEL
Charging current sense input
Battery voltage input
BAT is the battery voltage sense input, referenced to SNS. This is created by a highimpedance resistor-divider network connected between the positive and the negative
terminals of the battery.
2
bq2004E/H
Functional Description
Discharge-Before-Charge
Figure 2 shows a block diagram and Figure 3 shows a
state diagram of the bq2004E/H.
The DCMD input is used to command discharge-beforecharge via the DIS output. Once activated, DIS becomes
active (high) until VCELL falls below VEDV, at which time
DIS goes low and a new fast charge cycle begins.
Battery Voltage and Temperature
Measurements
The DCMD input is internally pulled up to VCC (its inactive state). Leaving the input unconnected, therefore,
results in disabling discharge-before-charge. A negative
going pulse on DCMD initiates discharge-before-charge
at any time regardless of the current state of the
bq2004. If DCMD is tied to VSS, discharge-before-charge
will be the first step in all newly started charge cycles.
Battery voltage and temperature are monitored for
maximum allowable values. The voltage presented on
the battery sense input, BAT, should represent a
two-cell potential for the battery under charge. A
resistor-divider ratio of:
RB1 N
=
-1
RB2 2
Starting A Charge Cycle
is recommended to maintain the battery voltage within
the valid range, where N is the number of cells, RB1 is
the resistor connected to the positive battery terminal,
and RB2 is the resistor connected to the negative battery terminal. See Figure 1.
A new charge cycle is started by:
1.
Application of VCC power.
2.
VCELL falling through the maximum cell voltage,
VMCV where:
Note: This resistor-divider network input impedance to
end-to-end should be at least 200kΩ and less than 1MΩ.
VMCV = 0.8 ∗ VCC ± 30mV
3.
A ground-referenced negative temperature coefficient thermistor placed in proximity to the battery may be used as a
low-cost temperature-to-voltage transducer. The temperature sense voltage input at TS is developed using a
resistor-thermistor network between VCC and VSS. See
Figure 1. Both the BAT and TS inputs are referenced to
SNS, so the signals used inside the IC are:
A transition on the INH input from low to high.
If DCMD is tied low, a discharge-before-charge will be
executed as the first step of the new charge cycle. Otherwise, pre-charge qualification testing will be the first
step.
The battery must be within the configured temperature
and voltage limits before fast charging begins.
VBAT - VSNS = VCELL
and
The valid battery voltage range is VEDV < VBAT < VMCV
where:
VTS - VSNS = VTEMP
VEDV = 0.4 ∗ VCC ± 30mV
Negative Temperature
Coefficient Thermister
VCC
PACK +
RT1
PACK+
bq2004E/H
TS
RB1
bq2004E/H
BAT
RB2
SNS
RT2
SNS
PACK-
N
T
C
PACK -
Fg2004a.eps
Figure 1. Voltage and Temperature Monitoring
3
bq2004E/H
TM1 TM2
TCO
Timing
Control
TCO
Check
OSC
LED1
LED2
DSEL
TS
LTF
Check
Display
Control
VTS - VSNS
DCMD
DVEN
VBAT - VSNS
Charge Control
State Machine
A/D
SNS
EDV
Check
Discharge
Control
MOD
Control
PWR
Control
DIS
MOD
INH
MCV
Check
BAT
VCC VSS
BD200401.eps
Figure 2. Block Diagram
Fast charge continues until termination by one or more
of the six possible termination conditions:
The valid temperature range is VHTF < VTEMP < VLTF,
where:
VLTF = 0.4 ∗ VCC ± 30mV
n
Delta temperature/delta time (∆T/∆t)
VHTF = [(1/3 ∗ VLTF) + (2/3 ∗ VTCO)] ± 30mV
n
Peak voltage detection (PVD)
n
Negative delta voltage (-∆V)
n
Maximum voltage
n
Maximum temperature
n
Maximum time
VTCO is the voltage presented at the TCO input pin, and is
configured by the user with a resistor divider between VCC
and ground. The allowed range is 0.2 to 0.4 ∗ VCC.
If the temperature of the battery is out of range, or the
voltage is too low, the chip enters the charge pending
state and waits for both conditions to fall within their allowed limits. During the charge-pending mode, the IC
first applies a top-off charge to the battery.
PVD and -∆V Termination
The bq2004E/H samples the voltage at the BAT pin once
every 34s. When -∆V termination is selected, if VCELL is
lower than any previously measured value by 12mV
±4mV (6mV/cell), fast charge is terminated. When PVD
termination is selected, if VCELL is lower than any previously measured value by 6mV ±2mV (3mV/cell), fast
charge is terminated. The PVD and -∆V tests are valid
in the range 0.4 ∗ VCC < VCELL < 0.8 ∗ VCC.
The top-off charge, at the rate of 1 8 of the fast charge,
continues until the fast-charge conditions are met or the
top-off time-out period is exceeded. The IC then trickle
charges until the fast-charge conditions are met. There
is no time limit on the charge pending state; the charger
remains in this state as long as the voltage or temperature conditons are outside of the allowed limits. If the
voltage is too high, the chip goes to the battery absent
state and waits until a new charge cycle is started.
4
bq2004E/H
VSEL Input
Low
Float
High
∆T/∆t Termination
Voltage Termination
Disabled
The bq2004E/H samples at the voltage at the TS pin
every 34s, and compares it to the value measured two
samples earlier. If VTEMP has fallen 16mV ±4mV or
more, fast charge is terminated. The ∆T/∆t termination
test is valid only when VTCO < VTEMP < VLTF.
-∆V
PVD
Voltage Sampling
Temperature Sampling
Each sample is an average of voltage measurements.
The IC takes 32 measurements in PVD mode and 16
measurements in -∆V mode. The resulting sample periods (9.17ms and 18.18ms, respectively) filter out harmonics centered around 55Hz and 109Hz. This technique minimizes the effect of any AC line ripple that
may feed through the power supply from either 50Hz or
60Hz AC sources. Tolerance on all timing is ±16%.
Each sample is an average of 16 voltage measurements.
The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the
power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%.
Maximum Voltage, Temperature, and Time
Temperature and Voltage Termination
Hold-off
Anytime VCELL rises above VMCV, the LEDs go off and current flow into the battery ceases immediately. If VCELL
then falls back below VMCV before tMCV = 1.5s ±0.5s, the
chip transitions to the Charge Complete state (maximum
voltage termination). If VCELL remains above VMCV at the
expiration of tMCV, the bq2004E/H transitions to the Battery Absent state (battery removal). See Figure 3.
A hold-off period occurs at the start of fast charging.
During the hold-off period, -∆V and ∆T/∆t termination
are disabled. The MOD pin is enabled at a duty cycle of
260µs active for every 1820µs inactive. This modulation
results in an average rate 1/8th that of the fast charge
rate. This avoids premature termination on the voltage
spikes sometimes produced by older batteries when
fast-charge current is first applied. Maximum voltage
and maximum temperature terminations are not affected by the hold-off period.
Maximum temperature termination occurs anytime
V TEMP falls below the temperature cutoff threshold
VTCO. Charge will also be terminated if VTEMP rises
above the low temperature fault threshold, VLTF, after
fast charge begins.
Table 1. Fast Charge Safety Time/Hold-Off/Top-Off Table
Typical
Fast-Charge
Safety
Time (min)
Corresponding
Fast-Charge
Rate
2004E
2004H
C/4
C/8
Low
C/2
C/4
1C
C/2
2C
Typical
PVD, -∆V
Hold-Off
Time (s)
2004E
2004H
2004E
Low
325
650
137
Float
Low
154
325
High
Low
77
154
1C
Low
Float
39
77
137
TM1
TM2
Top-Off
Rate
2004H 2004E
2004H
PulseTrickle
Rate
PulseTrickle
Period (Hz)
2004E
2004H
273
Disabled
Disabled
546
546
Disabled
C/512
15
273
546
Disabled
C/512
7.5
15
273
Disabled
C/512
3.75
7.5
30
4C
2C
Float
Float
19
39
68
137
C/512
1.88
3.75
C/2
C/4
High
Float
154
325
546
546
C/16
C/32
C/512
15
30
1C
C/2
Low
High
77
154
273
546
C/8
C/16
C/512
7.5
15
2C
1C
Float
High
39
77
137
273
C/4
C/18
C/512
3.75
7.5
4C
2C
High
High
19
39
68
137
C/2
C/4
C/512
1.88
3.75
Note: Typical conditions = 25°C, VCC = 5.0V.
5
Disabled
Disabled
bq2004E/H
Table 2. bq2004E/H LED Output Summary
Mode 1
bq2004E
DSEL = VSS
Charge Action State
LED1
LED2
Battery absent
Low
Low
Fast charge pending or a discharge-before-charge in progress
High
High
Fast charging
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
LED1
LED2
Battery absent
Low
Low
Discharge-before-charge in progress
High
Mode 1
bq2004H
DSEL = VSS
Charge Action State
Fast charge pending
Low
High
1
second high
second low
8
1
8
Fast charging
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
Mode 2
bq2004E
LED1
LED2
Battery absent
Charge Action State (See note)
Low
Low
Fast charge pending or discharge-before-charge in progress
High
High
Fast charging
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
LED1
LED2
DSEL = Floating
Mode 2
bq2004H
Charge Action State (See note)
Battery absent
Low
Low
Discharge-before-charge in progress
High
High
DSEL = Floating Fast charge pending
Low
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
LED1
LED2
Charge Action State
Battery absent
Note:
second high
second low
8
1
8
Fast charging
Mode 3
bq2004E/H
DSEL = VCC
1
Low
Low
1
8
1
8
second high
second low
Fast charge pending or discharge-before-charge in progress
Low
Fast charging
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
Pulse trickle is inhibited in Mode 2.
6
bq2004E/H
Maximum charge time is configured using the TM pin.
Time settings are available for corresponding charge
rates of C/4, C/2, 1C, and 2C. Maximum time-out termination is enforced on the fast-charge phase, then reset,
and enforced again on the top-off phase, if selected.
There is no time limit on the trickle-charge phase.
Charge Current Control
Top-off Charge
When used in switch mode configuration, the nominal
regulated current is:
The bq2004E/H controls charge current through the MOD
output pin. The current control circuitry is designed to support implementation of a constant-current switching regulator
or to gate an externally regulated current source.
An optional top-off charge phase may be selected to
follow fast charge termination for the C/2 through 4C
rates. This phase may be necessary on NiMH or other
battery chemistries that have a tendency to terminate
charge prior to reaching full capacity. With top-off enabled, charging continues at a reduced rate after
fast-charge termination for a period of time equal to
0.235∗ the fast-charge safety time (See Table 1.) During top-off, the MOD pin is enabled at a duty cycle of
260µs active for every 1820µs inactive. This modulation results in an average rate 1/8th that of the fast
charge rate. Maximum voltage, time, and temperature
are the only termination methods enabled during topoff.
IREG = 0.225V/RSNS
Charge current is monitored at the SNS input by the
voltage drop across a sense resistor, RSNS, between the
low side of the battery pack and ground. RSNS is sized to
provide the desired fast charge current.
If the voltage at the SNS pin is less than VSNSLO, the
MOD output is switched high to pass charge current to
the battery.
When the SNS voltage is greater than VSNSHI, the MOD
output is switched low—shutting off charging current to
the battery.
VSNSLO = 0.04 ∗ VCC ± 25mV
Pulse-Trickle Charge
VSNSHI = 0.05 ∗ VCC ± 25mV
Pulse-trickle charging may be configured to follow the
fast charge and optional top-off charge phases to compensate for self-discharge of the battery while it is idle
in the charger.
When used to gate an externally regulated current
source, the SNS pin is connected to VSS, and no sense resisitor is required.
In the pulse-trickle mode, MOD is active for 260µs of a
period specified by the settings of TM1 and TM2. See
Table 1. The resulting trickle-charge rate is C/512.
Both pulse trickle and top-off may be disabled by tying
TM1 and TM2 to VSS or by selecting Mode 2 in the display.
Charge Status Indication
Charge status is indicated by the LED1 and LED2 outputs. The state of these outputs in the various charge cycle phases is given in Table 2 and illustrated in Figure 3.
In all cases, if VCELL exceeds the voltage at the MCV
pin, both LED1 and LED2 outputs are held low regardless of other conditions. Both can be used to directly
drive an LED.
7
bq2004E/H
New Charge Cycle Started by
Any One of:
Falling Edge
on DCMD
VCC Rising to Valid Level
Yes
Battery Replacement
(VCELL Falling through VMCV)
DCMD Tied to Ground?
Inhibit (INH) Released
No
VEDV < VCELL < VMCV
Charge
Pending
VCELL < VEDV
Battery Voltage?
VCELL < VEDV
VTEMP > VLTF or
VTEMP < VHTF
Top-Off and
Pulse-Trickle
Charge
Battery Temperature?
DischargeBefore-Charge
VCELL > VMCV
VCELL > VMCV
VCELL >
VMCV
VHTF < VTEMP < VLTF
Battery
Absent
VEDV < VCELL < VMCV
and
VHTF < VTEMP < VLTF
Fast
Charge
VCELL > VMCV
- V or
T/ t or
VTEMP < VTCO
or
Maximum Time Out
Top-Off
Selected?
Pulse
Trickle
Charge
t > tMCV
Pulse
Trickle
Charge
VCELL <
VMCV
VCELL >
VMCV
Top-Off
Charge
Yes
VTEMP < VTCO
or 0.235 Maximum
Time Out
No
Charge
Complete
VCELL >
VMCV
Pulse
Trickle
Charge
SD2004EH.eps
Figure 3. Charge Algorithm State Diagram
8
bq2004E/H
Absolute Maximum Ratings
Symbol
Parameter
Minimum
Maximum
Unit
VCC
VCC relative to VSS
-0.3
+7.0
V
VT
DC voltage applied on any pin excluding VCC relative to VSS
-0.3
+7.0
V
TOPR
Operating ambient temperature
-20
+70
°C
TSTG
Storage temperature
-55
+125
°C
TSOLDER
Soldering temperature
-
+260
°C
TBIAS
Temperature under bias
-40
+85
°C
Note:
VSNSHI
VSNSLO
Commercial
10 sec max.
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Thresholds
Symbol
Notes
(TA = TOPR; VCC ± 10%)
Parameter
High threshold at SNS resulting in MOD = Low
Low threshold at SNS resulting in MOD = High
Rating
Tolerance
Unit
0.05 * VCC
±0.025
V
0.04 * VCC
±0.025
V
Notes
VTEMP ≥ VLTF inhibits/terminates charge
VLTF
Low-temperature fault
0.4 * VCC
±0.030
V
VHTF
High-temperature fault
(1/3 * VLTF) + (2/3 * VTCO)
±0.030
V
VEDV
End-of-discharge voltage
0.4 * VCC
±0.030
V
VMCV
Maximum cell voltage
0.8 * VCC
±0.030
V
VTHERM
TS input change for∆T/∆t
detection
-16
±4
mV
VCC = 5V, TA = 25°C
-12
±4
mV
VCC = 5V, TA = 25°C
-6
±2
mV
VCC = 5V, TA = 25°C
-∆V
PVD
BAT input change for -∆V
detection
BAT input change for PVD
detection
9
VTEMP ≤ VHTF inhibits
charge
VCELL < VEDV inhibits
fast charge
VCELL > VMCV inhibits/
terminates charge
bq2004E/H
Recommended DC Operating Conditions (TA = TOPR)
Symbol
Condition
Minimum
Typical
Maximum
Unit
Notes
VCC
Supply voltage
4.5
5.0
5.5
V
VBAT
Battery input
0
-
VCC
V
VCELL
BAT voltage potential
0
-
VCC
V
VTS
Thermistor input
0
-
VCC
V
VTEMP
TS voltage potential
0
-
VCC
V
VTS - VSNS
VTCO
Temperature cutoff
0.2 * VCC
-
0.4 * VCC
V
Valid ∆T/∆t range
Logic input high
2.0
-
-
V
DCMD, INH
Logic input high
VCC - 0.3
-
-
V
TM1, TM2, DSEL, VSEL
Logic input low
-
-
0.8
V
DCMD, INH
Logic input low
-
-
0.3
V
TM1, TM2, DSEL, VSEL
VBAT - VSNS
VIH
VIL
VOH
Logic output high
VCC - 0.8
-
-
V
DIS, MOD, LED1, LED2,
IOH ≤ -10mA
VOL
Logic output low
-
-
0.8
V
DIS, MOD, LED1, LED2,
IOL ≤ 10mA
ICC
Supply current
-
1
3
mA
Outputs unloaded
ISB
Standby current
-
-
1
µA
INH = VIL
IOH
DIS, LED1, LED2, MOD source
-10
-
-
mA
@VOH = VCC - 0.8V
IOL
DIS, LED1, LED2, MOD sink
10
-
-
mA
@VOL = VSS + 0.8V
Input leakage
-
-
±1
µA
INH, BAT, V = VSS to VCC
Input leakage
50
-
400
µA
DCMD, V = VSS to VCC
IL
IIL
Logic input low source
-
-
70
µA
TM1, TM2, DSEL, VSEL,
V = VSS to VSS + 0.3V
IIH
Logic input high source
-70
-
-
µA
TM1, TM2, DSEL, VSEL,
V = VCC - 0.3V to VCC
IIZ
Tri-state
-2
-
2
µA
TM1, TM2, DSEL, and VSEL
should be left disconnected
(floating) for Z logic input state
Note:
All voltages relative to VSS except as noted.
10
bq2004E/H
Impedance
Symbol
Parameter
Minimum
Typical
Maximum
Unit
RBAT
Battery input impedance
50
-
-
MΩ
RTS
TS input impedance
50
-
-
MΩ
RTCO
TCO input impedance
50
-
-
MΩ
RSNS
SNS input impedance
50
-
-
MΩ
Timing
Symbol
(TA = 0 to +70°C; VCC ± 10%)
Parameter
tPW
Pulse width for DCMD
and INH pulse command
dFCV
Time base variation
fREG
Minimum Typical
Maximum
Unit
Notes
1
-
-
µs
Pulse start for charge or discharge
before charge
-16
-
16
%
VCC = 4.75V to 5.25V
MOD output regulation
frequency
-
-
300
kHz
tMCV
Maximum voltage termination time limit
1
-
2
s
Note:
Typical is at TA = 25°C, VCC = 5.0V.
11
Time limit to distinguish battery removed from charge complete.
bq2004E/H
16-Pin DIP Narrow (PN)
16-Pin PN (0.300" DIP)
Inches
12
Millimeters
Dimension
Min.
Max.
Min.
Max.
A
0.160
0.180
4.06
4.57
A1
0.015
0.040
0.38
1.02
B
0.015
0.022
0.38
0.56
B1
0.055
0.065
1.40
1.65
C
0.008
0.013
0.20
0.33
D
0.740
0.770
18.80
19.56
E
0.300
0.325
7.62
8.26
E1
0.230
0.280
5.84
7.11
e
0.300
0.370
7.62
9.40
G
0.090
0.110
2.29
2.79
L
0.115
0.150
2.92
3.81
S
0.020
0.040
0.51
1.02
bq2004E/H
16-Pin SOIC Narrow (SN)
16-Pin SN (0.150" SOIC)
Inches
D
e
B
E
H
A
C
A1
.004
L
13
Millimeters
Dimension
Min.
Max.
Min.
Max.
A
0.060
0.070
1.52
1.78
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.18
0.25
D
0.385
0.400
9.78
10.16
E
0.150
0.160
3.81
4.06
e
0.045
0.055
1.14
1.40
H
0.225
0.245
5.72
6.22
L
0.015
0.035
0.38
0.89
bq2004E/H
Data Sheet Revision History
Change No.
Page No.
1
All
2
3
Description
Nature of Change
Combined bq2004E and bq2004H, revised and
expanded format of this data sheet
Clarification
7
Separated bq2004E and bq2004H in Table 2, LED
Output Summary
Clarification
5
Description of charge-pending state
Clarification
9
Corrected VSNSLO tolerance
Was: ±0.010
Is: ±0.025
4
5
Note:
Change 1 = Oct. 1997 B changes from Sept. 1996 (bq2004E), Feb. 1997 (bq2004H).
Change 2 = Feb. 1998 C changes from Oct. 1997 B.
Change 3 = Dec. 1998 D changes from Feb. 1998 C.
Change 4 = June 1999 E changes from Dec. 1998 D.
Change 5 = Apr. 2005 F changes from June 1999 E.
14
bq2004E/H
Ordering Information
bq2004
Package Option:
PN = 16-pin narrow plastic DIP
SN = 16-pin narrow SOIC
Device:
E = bq2004E Fast-Charge IC
H= bq2004H Fast-Charge IC
15
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ2004ESNTR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
BQ2004HSNTR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ2004ESNTR
SOIC
D
16
2500
367.0
367.0
38.0
BQ2004HSNTR
SOIC
D
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
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