datasheet for PUMA68F16006 by Apta Group

datasheet for PUMA68F16006 by Apta Group
512K x 32 FLASH MODULE
PUMA 68F16006/A-70/90/12/15
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Description
The PUMA 68F16006 is a high density 16Mbit
CMOS 5V Only FLASH memory module in a
JEDEC 68 pin surface mount PLCC, with read
access times of 70, 90, 120, and 150ns. The plastic
device is screened to ensure high reliability.
The output width is user configerable as 8 , 16 or
32 bits using four Chip Selects (CE1~4) for
optimum application flexibility.
The module incorporates Embedded Algorithms for
Program and Erase with Sector architecture (64K
sector) and supports full chip erase.
Features
• Fast Access Times of 70/90/120/150 ns.
• Output Configurable as 32 / 16 / 8 bit wide.
• Industrial, Military or Military (High Rel) grade.
• Automatic Write/Erase by Embedded Algorithm - end of
Write/Erase indicated by DATA Polling and Toggle Bit.
• Flexible Sector Erase Architecture - 64K byte sector
size, with hardware protection of any number of sectors.
• Single Byte Program of 16µs (Min.), Sector Program
time of 1 sec (typ.)
• Erase/Write Cycle Endurance 100,000 (Min.) - E variant.
Pin Definition (see page 24 for 'A' version)
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
Vcc
Block Diagram (see page 24 for 'A' version)
Issue 4.4 : May 2001
A0~A18
OE
WE
512K x 8
512K x 8
512K x 8
512K x 8
FLASH
FLASH
FLASH
FLASH
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
VIEW
17
53
FROM
18
52
19
51
ABOVE
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
A17
NC
NC
NC
A18
GND
NC
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
A0-A18
CE1-4
OE
GND
Address Input
Chip Enables
Output Enable
Ground
Pin Functions
D0-D31
WE
Vcc
Data Inputs/Outputs
Write Enable (WE1-4 for 'A' version)
Power (+5V)
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
Absolute Maximum Ratings (1)
max
unit
-2.0 to +7
V
-2.0 to +7
V
-2.0 to +14
V
-65 to +150 °C
Voltage on any pin w.r.t. Gnd
Supply Voltage (2)
Voltage on A9 w.r.t. Gnd (3)
Storage Temperature
Notes : (1)
(2)
(3)
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operationof the device at those or any other conditions above those indicated in the operational sections of this
specification
is not implied.
Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V
During transitions voltage may overshoot by +/-2V for upto 20ns
Minimum DC input voltage on A9 is -0.5V during voltage transitions, A9 may overshoot Vss to -2V for periods of up to
20ns, maximum DC input voltage in A9 is 13.5V which may overshoot to 14.0V for periods up to 20ns
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
VCC
VIH
VIL
TA
TAI
TAM
min
4.5
2.0
0.7VCC
0
-40
-55
typ
5.0
-
max
5.5
VCC+0.5
VCC+0.3
70
85
125
unit
V
V
V
°C
O
C (-I suffix)
O
C (-M\MB suffix)
DC Electrical Characteristic (TA=-55°C to +125°C,VCC=5V ± 10%)
Parameter
Symbol Test Condition
I/P Leakage Current Address, OE
A9 Input Leakage Current
Other Pins
Output Leakage Current
VCC Operating Current
32 bit
16 bit
8 bit
ILI1
ILI1
ILI2
ILO
ICCO32
ICCO16
ICCO8
VCC=VCC max, VIN=0V or VCC
VCC Program/Erase Current
32 bit
16 bit
8 bit
ICCP32
ICCP16
ICCP8
Programming in Progress
Standby Supply Current
Autoselect / Sector Protect Voltage
Voltage for Sector Unprotect
Output Low Voltage
Output High Voltage
Low VCC Lock-Out Voltage
ISB1
VID
VSP
VOL
VOH1
VLKO
VCC=VCC max, CE=VIH(1) OE = VIH
VCC=VCC max, A9=12.5V
VCC=VCC max, VIN=0V or VCC
VCC=VCC max, VOUT=0V or VCC
CE=VIL(1), OE=VIH, IOUT=0mA, f=6MHz
As above
As above
As above
As above
VCC = 5.0V
VCC = 5.0V
IOL=12mA. VCC = VCC min.
IOH=-2.5mA. VCC = VCC min.
min
typ max
Unit
-
-
±4
200
±1
±4
160
82
43
µA
µA
µA
µA
mA
mA
mA
-
-
240
122
63
mA
mA
mA
11.5
9.5
2.4
3.2
-
4
12.5
10.5
0.45
4.2
mA
V
V
V
V
V
Notes (1) CE above are accessed through CE1-4. These inputs must be operated simultaneoulsy for 32 bit operation,
in pairs in 16 bit mode and singly for 8 bit mode.
2
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
Capacitance (TA=25°C,f=1MHz)
Parameter
Input Capacitance
Output Capacitance
Address, OE
Other pins
32 bit
Symbol
Test Condition
CIN1
CIN2
VIN=0V
VIN=0V
COUT32
VOUT=0V
typ
max
Unit
-
30
36
pF
pF
-
48
pF
Note: These parameters are calculated, not measured.
AC Test Conditions
* Input pulse levels : 0.0V to 3.0V
* Input rise and fall times : 5 ns
* Input and output timing reference levels : 1.5V
* VCC = 5V +/- 10%
* Module tested in 32 bit mode
I/O Pin
166 Ω
1.76V
30pF
3
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
min
70
70
typ
-
max
-
min
90
90
typ max
-
Unit
ns
Read Cycle Time
t RC
Address to output delay
t ACC
-
-
70
-
-
90
ns
Chip enable to output
tCE
-
-
70
-
-
90
ns
Output enable to output
tOE
-
-
35
-
-
35
ns
Output enable to output High Z
tDF
-
-
20
-
-
20
ns
Output hold time from address
tOH
0
-
-
0
-
-
ns
CE or OE whichever occurs first
Parameter
Symbol
120
typ max
-
Read Cycle Time
tRC
Address to output delay
t ACC
-
-
120
-
-
150
ns
Chip enable to output
tCE
-
-
120
-
-
150
ns
Output enable to output
tOE
-
-
50
-
-
55
ns
Output enable to output High Z
tDF
-
-
30
-
-
35
ns
Output hold time from address
tOH
0
-
-
0
-
-
ns
CE or OE whichever occurs first
4
min
150
150
typ max
-
min
120
Unit
ns
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
Write/Erase/Program
Parameter
Symbol
Write Cycle time (4)
tWC
min
90
typ
-
max
-
unit
ns
Address Setup time
tAS
0
-
-
ns
Address Hold time
tAH
50
-
-
ns
Data Setup Time
tDS
50
-
-
ns
Data hold Time
tDH
0
-
-
ns
Output Enable Setup Time
tOES
0
-
-
ns
Read Recover before Write tGHWL
0
-
-
ns
CE setup time
tCE
0
-
-
ns
CE hold time
tCH
0
-
-
ns
WE Pulse Width
tWP
50
-
-
ns
WE Pulse Width High
tWPH
20
-
-
ns
Programming operation
tWHWH1
-
16
-
µs
Sector Erase operation (1)
tWHWH2
-
1
30
sec
tWHWH2
-
8
-
sec
tVCS
50
-
-
µs
tVLHT
4
-
-
µs
Write Pulse Width 1 (2)
tWPP1
100
-
-
µs
(2)
tWPP2
10
-
-
ms
OE setup to WE active(2,4,5) tOESP
4
-
-
µs
CE setup to WE active(3,4,5) tCSP
4
-
-
µs
Chip Erase operation
(1)
Vcc setup time (4)
Voltage Transition Time
Write Pulse Width 2
(2,4)
Notes: (1) This does not include the preprogramming time.
(2) These timings are for Sector Protect/Unprotect operations.
(3) This timing is only for Sector Unprotect.
(4) Not 100% tested.
(5) WE refers to WE1~4 on the PUMA 67F16006A.
5
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
Write/Erase/Program Alternate CE controlled Writes
Parameter
Symbol
Write Cycle time (2)
tWC
min
90
typ
-
max Unit
ns
Address Setup time
tAS
0
-
-
ns
Address Hold time
tAH
50
-
-
ns
Data Setup Time
tDS
50
-
-
ns
Data hold Time
tDH
0
-
-
ns
Output Enable Setup Time
tOES
0
-
-
ns
Read Recover before Write
tGHEL
0
-
-
ns
tWS
0
-
-
ns
tWH
0
-
-
ns
CE Pulse Width
tCP
50
-
-
ns
CE Pulse Width High
tCPH
120
-
-
ns
tWHWH1
-
16
-
us
tWHWH2
-
1
30
sec
Chip Erase operation (1)
tWHWH2
-
8
-
sec
Vcc setup time (2)
tVCE
-
50
-
us
WE setup time
WE hold time
(3)
(3)
Programming operation
Sector Erase operation
(1)
Note: (1) Does not include pre-programming time.
(2) Not 100% tested.
(3) WE refers to WE1~4 on the PUMA 67F16006A.
6
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
AC Waveforms for Read Operation
t RC
Addresses Stable
Addresses
t ACC
CE
t DF
t OE
OE
t OH
t CE
WE
High Z
Outputs
High Z
Output Valid
AC Waveforms Program
Data Polling
Address
5555H
PA
tWC
t AS
PA
tAH
tRC
CE
t GHWL
OE
tWP
tWHP
tWHWH1
WE
tOE
tCS
tDF
t DH
DATA
A0H
PD
DQ7
DDOUT
OUT
tDS
tCE
VCC
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the out put of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
7
t OH
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
A.C Waveforms - Alternate CE controlled Program operation timings
Data Polling
Address
5555H
PA
t WC
tAS
PA
tAH
tR C
WE
t GHE L
OE
tC P
tC HP
t WHWH 1
CE
t OE
t WS
tD F
t DH
DATA
A0H
PD
DQ7
DDOUT
OUT
tD S
tC E
V
t OH
CC
NOTES:
1. PA is address of memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
AC Waveforms for Data Polling During Embedded Algorithm Operations
tCH
CE
t DF
tOE
OE
tOEH
t CE
WE
tOH
*
DQ7
DQ7=
Valid Data
DQ7
HIGH Z
t WHWH 1 or 2
DQ0-DQ6
= Invalid
DQ0-DQ6
DQ0-DQ7=
Vaild Data
tOE
8
HIGH Z
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
CE
WE
tOEH
OE
*
DATA
(DQ0-DQ7)
DQ6=Toggle
tOH
DQ6=
Stop Toggling
DQ6=Toggle
DQ0-DQ7
Valid
t OE
* DQ6 stops toggling ( the device has completed the embedded operations)
AC Waveforms For Sector Protection
A18
A17
A16
SAX
SAY
A0
A1
A6
12V
5V
A9
tVLHT
tVLHT
12V
5V
OE
tVLHT
tWPP
WE
tOESP
CE
Don't Care
Data
01H
tOE
SAX = sector Addr for intial sector
SAY = sector Addr for next sector
9
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
AC Waveforms for Sector Unprotect
A18
A17
A16
A0
A1
A5
A6
VID or VSP
A9
DATA
VSP
5.0V
WE
VSP
5.0V
tVLHT
OE
tCESP
CE
tVLHT
tWPP
tCESP
tWPP2
AC Waveforms Chip / Sector Erase
tAS
Address
5555H
tAH
2AAAH
5555H
5555H
2AAAH
SA
CE
tGHWL
OE
tWP
WE
tWPH
tCS
tDH
Data
Vcc
tDS
AAH
55H
80H
AAH
5HH
55H
tVCS
NOTES:
1. SA is the address for sector erase. Addresses = don't care for Chip Erase.
10
10H/30H
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
EMBEDDED PROGRAMMING ALGORITHM
Start
Write Program Command
Sequence
(see below)
Data Poll Device
Increment Address
Last
Address
?
No
Yes
Programming
Completed
Program Command Sequence (Address /Command)
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program data
11
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
EMBEDDED ERASE ALGORITHM
START
Write Erase Command Sequence
See below
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
Individual Sector/Mulitiple Sector
(Address/Command):
Erase Command Sequence
(Address/Command):
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
5555H/10H
2AAAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
12
}
Additional sector
erase commands
are optional
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
DATA POLLING ALGORITHM
START
Read Byte
(DQ0-DQ7)
Addr =VA
DQ7 = Data ?
YES
NO
NO
DQ5 = 1 ?
YES
Read Byte
(DQ0-DQ7)
Addr =VA
DQ7 = Data ?
YES
PASS
NO
FAIL
NOTE:
1. DQ7 is rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
2. VA = Byte address for programming.
= Any of the sector addresses within the sector being erased during sector erase operation
= XXXXXH during chip erase
TOGGLE BIT ALGORITHM
START
Read Byte
(DQ0-DQ7)
Addr=VA
NO
DQ6=Toggle ?
YES
NO
DQ5 = 1 ?
YES
Read Byte
(DQ0-DQ7)
Addr=VA
DQ6=Toggle ?
NO
PASS
YES
FAIL
NOTES:
1. DQ6 is rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time as DQ5 changing to "1".
2 VA = As above.
13
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
SECTOR UNPROTECT ALGORITHM
START
Protect All Sectors
PLSCNT = 1
Set
A0=A9=Vil
A5=Vih
(setup for sector
unprotection)
PLSCNT=PLSCNT+1
Set
/OE=Vid orVsp
/WE=Vsp
Time Out 10ms
Activate
first /CE pulse
/OE=/WE=Vih
A9=Vid or Vsp
Time Out 100us
Write
Electric Signature
Command
Remove
Vid or Vsp on A9
Write "Reset"
command
/CE=Vih
Set up
Sector Address "SA0"
A0=Vil, A1=A6=Vih
Activate
second /CE pulse
Read
Data from Device
Increment
Sector Address
NO
Data = 00H?
YES
YES
NO
PLSCNT=1000?
Sector
Address = SA7?
YES
Remove
Vid or Vsp on A9
Write "Reset"
command
END
NOTES:
SA0 = The First Sector Address
SA7 = The Last Sector Address
(Sector Address is indicated
using A16 to A18)
14
Remove
Vid or Vsp on A9
Write "Reset"
command
Device Failed
NO
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
SECTOR PROTECTION ALOGORITHM
START
Set Up Sector Addr
(A20, A19, A18)
PLSCNT = 1
OE=VID,
OE = VID,A9=VID
A9 = VID
CE = VIL,RESET=VIH
RESET = VIH
CE=VIL,
Activate WE Pulse
Time Out 100us
Power Down OE
WE = VIH
CE=OE=VIL
A9 should remain VID
Increment
PLSCNT
Read from Sector
Addr=SA, A1, A0 = 10 , A6 = 0
NO
PLSCNT
= 25
?
Data
=01H
?
NO
YES
YES
Remove VID from A9
Write Reset Command
Protect
Another
Sector
Device Failed
NO
Remove VID From A9
Write Reset Command
Sector Protection
Complete
15
YES
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
DEVICE OPERATION
The following description deals with the device operating in 8 bit mode accessed through CE1,
however status flag definitions shown apply equally to the corresponding flag for each device in the module.
Read Mode
The device has two control functions which must be satisfied in order to obtain data at the outputs
CE1-4 is the power control and should be used for device selection
OE is the output control and should be used to gate data to the output pins if the device is selected.
Standby Mode
Two standby modes are available :
CMOS standby : CE1-4 held at Vcc +/- 0.5V
TTL standby : CE1-4 held at VIH
In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is
deselected during erasure or programming the device will draw active current until the operation is completed.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify the die manufacturer and type. This mode is intended for use by programming equipment. This mode is functional over the
full military temperature range. The autoselect codes for the first device are as follows :
Type
A18
A17
A16
A6
A1
A0
Code
(HEX)
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacture
Code
X
X
X
VIL
VIL
VIL
04H
0
0
0
0
0
0
0
1
X
X
X
VIL
VIL
VIH
A4H
1
0
1
0
0
1
0
0
VIL
VIH
VIL
01H*
0
0
0
0
0
0
0
1
Device Code
Sector
Protection
Sector Address
* Outputs 01H at protected sector address
To activate this mode the programming equipment must force VID on address A9 . Two identifier bytes may
then be sequenced from each die device outputs by toggling A0 from VIL to VIH. All addresses are dont care
apart from A1 & A0. All identifiers for manufacturer and device will exhibit odd parity with D7 defined as the
parity bit. In order to read the proper device codes when executing the autoselect A1 must be VIL.
Write
Device erasure and programming are accomplished via the command register. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The
register is a latch used to store the commands along with the address and data information required to execute
the command. The command register is written by bringing WE/WE1-4 to VIL while CE1-4 is at VIL and
OE is at VIH.Addresses are latched on the falling edge of WE/WE1-4 while data is latched on the rising edge.
16
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
The following table defines these register command sequences.
Command
Sequence
Read/Reset
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Addr
Data
Second Bus
Write Cycle
Addr
Data
Third Bus
Write Cycle
Addr
Fourth Bus
Read/Write
Cycle
Data
Addr
Data
RA
RD
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr
Data
Addr
Data
Read/Reset
1
XXXH
F0H
Read/Reset
4
5555H
AAH
2AAAH
55H
5555H
F0H
Autoselect
4
5555H
AAH
2AAAH
55H
5555H
90H
Byte Program
4
5555H
AAH
2AAAH
55H
5555H
A0H
PA
Data
Chip Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Sector Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
30H
Sector Erase Suspend
Erase can be suspended during sector erase with Addr (don't care) Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Addr (Don't Care), Data (30H)
NOTES:
1. Address bit A15,A16,A17, A18=X=Don't care. Write Sequences may be initiated with A15, A17 and A18 in either
state.
2. Address bit A15,A16,A17, A18=X=Don't care for all address commands except for Program Address (PA)
and Sector Address (SA).
3. RA=Address of the memory location to be read.
PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE pulse .
SA=Address of the sector to be erased. The combination of A18, A17 and A16 will uniquely select any
sector.
4. RD=Data read from location RA during read operation.
PD=Data to be programmed at location PA. Data is latched on the falling edge of WE
Read / Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters.
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ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
Sector Protection
The device features hardware sector protection. This feature will disable both program and erase operations
in any number of sectors (0 through 8). The sector protect feature is enabled using programming equipment at
the users site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, and
CE=VIH. The sector adresses (A18, A17 and A16) should be set to the sector to be protected. Programming of
the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the
same. Sector addresses must be held constant during the WE pulse.
To verify programming of the protection equipment circuitry, the programming equipment must force VID on
address pin A9 with CE and OE at VIL and WE at VIH. Reading the device at a particular sector address (A16,
A17 and A18) while (A6,A1,A0) = (0,1,0) will produce 01H at data output D0 for a protected sector. Otherwise
the device will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0, , A1
and A6 , are don't care. Address with A1=VIL are reserved for autoselect codes. If a verify of the sector protection circuitry were done at these addresses, the device would output the manufacturer and device codes
respectively.
It is also possible to determine if a sector is protected in the system by writing the autoselect command.
Performing a read operation at XX02H , where the higher order addresses (A16, A17, A18) are sector
addresses,(other addresses are a don't care) will produce 01H data if those sectors are protected. Otherwise
the devidce will read 00H for an unprotected sector.
Sector Address Table
A18
A17
A16
Address Range
SA0
0
0
0
000000h-0FFFFh
SA1
0
0
1
10000h-1FFFFh
SA2
0
1
0
20000h-2FFFFh
SA3
0
1
1
30000h-3FFFFh
SA4
1
0
0
40000h-4FFFFh
SA5
1
0
1
50000h-5FFFFh
SA6
1
1
0
60000h-6FFFFh
SA7
1
1
1
70000h-7FFFFh
Sector Unprotect
Sectors which have previously been protected from being programmed or erased may be unprotected using
the Sector Unprotect Algorithm. All sectors must be placed in the protection mode using the protection
algorithm before unprotection can proceed.
A special high voltage for unprotection VSP is defined to be 10V+/-0.5V.
The unprotection mode is entered by setting OE to VID or VSP, WE to VSP, A5 to VIH and A0=A9 to VIL. Unprotect
is invoked by applying to negative pulses on CE for a period of tWPP2.
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PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target systems. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally a desired system design practice.
The device contains an autoselect operation to supplement traditional PROM programming methodology. The
operation is initiated by writing the autoselect command sequence into the command register. Following the
command write, a read cycle from address XX00H retrieves the manufacture code of 01H. A read cycle from
address XX01H returns the device code A4H. A read cycle from address XXX2H returns information as to
which sectors are protected. All manufacturer and device codes will exhibit odd parity with the MSB (D7)
defined as the parity bit.
To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycle. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of WE/WE1-4 or CE1-4, whichever happens later, while the data are latched on the
rising edge of WE/WE1-4 or CE1-4 whichever happens first. The rising edge of WE/WE1-4 or CE1-4 begins
programming. Upon executing the Embedded Program Algorithm Command sequence the system is not
required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on D7 is equivalent to data written to this bit (see written Operations Status) at which time
the device returns to read mode. Data Polling must be performed at the memory location which is being
programmed.
Programming is allowed in any address sequence and across sector boundaries.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device automatically will program and verify the entire memory for an all
zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings during
these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.
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ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing
the "Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The
sector address (any address location within the desired sector) is latched on the falling edge of WE, while the
command (data) is latched on the rising edge of WE. A time-out of 50us from the rising edge of the last sector
erase command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing the six bus cycle operations as desribed above. This
sequence is followed with writes of the sector erase command 30H to addresses in other sectors required to
be concurrently erased. A time-out of 50us from the rising edge of the WE pulse for the last sector erase
command will initiate the sector erase. If another sector erase command is wriiten within the 50us time-out
window the timer is reset. Any command other than sector erase within the time-out window will reset the
device to the read mode, ignoring the previous command string (refer to Write Operation Status section for
Sector Erase Timer operation). Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 7).
Sector erase doesn't require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors
the remaining unselected sectors are not affected. The system is not required to provide any controls or
timings during these operations.
The automatic sector erase begins after the 50us time-out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on D7 is "1" ( see Written Operation Status
Section) at which time the device returns to read mode. Data polling must be preformed at an address within
any of the sectors being erased.
Erase Suspend
Erase suspend allows the user to interupt the chip and read data (not program) from a non busy sector while it
is in the middle of a sector erase operation, which may take several seconds.
The command can only be used during sector erase operation and otherwise will be ignored. The erase
suspend command B0h is also allowed during the Sector Erase Operation that will include the sector erase
time out period after the sector erase commands B0h. Writing this command during the timeout will result in
immediate termination of the time out period and any subsequent writes of Sector Erase Command will be
taken as Erase Resume.
To suspend the erase operation and go into erase suspend mode (pseudo read mode) requires between 0.1
and 10µs, during which time the user can read from a sector that is not being erased. The toggle bit stops
toggling when the device enters pseudo read mode and an address of a sector not being erased must be used
to read the toggle bit.
After the user writes the erase suspend command and waits until the toggle bit stops toggling, data reads from
the device may then be performed. After an Erase Resume command the internal counters, which are used to
count the high voltage pulses required to program or erase, are reset. The Exceed Time limit flag D5 is set if
the count exceeds a certain limit. (The resetting of the counters is necessary as the erase suspend command
can potentially interupt the high voltage pulses.)
20
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
Operating Modes
The following modes are used to control the device.
OPERATION
CE
OE
WE
A0
A1
A6
A9
I /O
Auto-Select Manufacturer Code
L
L
H
L
L
L
V ID
Code
Auto Select Device Code
L
L
H
H
L
L
V ID
Code
Read(1)
L
L
H
A0
A1
A6
Standby
H
X
X
X
X
X
X
High Z
Output Disable
L
H
H
X
X
X
X
High Z
Write
L
H
L
A0
A1
A6
A9
Din
Enable Sector Protect
L
VID
L
X
X
X
VID
X
Verify Sector Protect
L
L
H
H
L
V ID
L
A9
D OUT
Code
1) L=VIL, H=VIH, X=Don't Care
NOTE:
1) WE can be VIL if OE is VIL , OE at VIH initiates write cycle.
WRITE OPERATIONS STATUS
HARDWARE SEQUENCE FLAGS
STATUS
D7
D6
D5
D3
Auto-Programming
DQ7 Toggle
0
0
In Progress Programming in auto erase
0
Toggle
0
1
Erasing in Auto Erase
0
Toggle
0
1
Auto-Programming
DQ7
Toggle
1
1
Exceeded Programming in auto erase
0
Toggle
1
1
Time limits Erasing in Auto-Erase
0
Toggle
1
D2-D0
(D)
(D)
1
NOTE: DQ0, DQ1, DQ2, DQ4 are reserve pins for future use.
D7 Data Polling
The device features Data Polling as a method to indicate to the host system that the Embedded Algorithms
are in progress or completed.
During the Embedded Programming Algorithm, an attempt to read the device will produce complement data
of the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read
the device will produce the true data last written to D7. Data Polling is valid after the rising edge of the forth
WE pulse in the four write pulse sequence.
During the Embedded Erase Algorithm, D7 will be "0" until the erase operation is completed. Upon completion
data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, Data Polling is valid after the last rising edge of the sector erase WE
pulse.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out.
21
ISSUE 4.4 : May 2001
D6
PUMA 68F16006/A-70/90/12/15
Toggle Bit
The device also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device
will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is
completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the
Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For chip erase,
the Toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during
the sector time-out.
D5 Exceeding Time Limits
D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will
produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only
operating function of the device under this condition. The CE circuit will partially power down the device under
these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions . To
reset the device, write reset command sequence to the device. This allows the system to continue to use the
other active sectors in the device, if this failure occurs during sector erase operations, it specifies that a particular sector is bad and may not be re-used. The device must be reset to use other sectors. While the reset
command sequence and execute program or erase command sequence.
If this failure occurs during chip erase operation , it specifies that the device chip or combination of sectors are
bad. If this failure occurs during the byte programming operation, it specifies that the active sectors containing
that byte is bad and may not be re-used.
The D5 failure condition may also appear if the user tries to program a non blank location without erasing. In
this case the device locks out and never completes the embedded algorithm operation. Hence the system
never reads a valid data on D7 and D6 never stops toggling. Once the device has exceeded timing limits, the
D5 bit will indicate '1'
D4
Hardware Sequence Flag
If the device has exceeded the specified erase or program time and D5 is "1", then D4 will indicate at which
step in the algorithm the device exceeded the limits. A "0" in D4 indicates in programming, a "1" indicates an
erase.
D3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may
be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional
sector erase commands. To insure the command has been accepted, the software should check the status of
D3 prior to and following each subsequent sector erase command. If D3 were high on the second status
check, the command may not have been accepted.
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PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up
and power down transitions or system noise.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for VCC
less than 3.2V (typically 3.7V). If VCC<VLKO, the command register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored
until the VCC level is greater than VLKO. It is usually correct to prevent unintentional writes when VCC is above
3.2V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CE, WE will not initiate a write cycle
Logical Inhibit
Writing is inhibited by holding any one of OE=VIL, CE=VIH or WE=VIH. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
Power Up Write Inhibit
Power-up of the device with WE=CE=VIL and OE=VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Protect
Sectors of the device may be hardware protected at the users factory. The protection circuitry will disable both
program and erase functions for the protected sector(s). Requests to program or erase a protected sector will
be ignored by the device.
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Byte Programming Time
Chip Programming Time
Erase/Program Cycles
Min
Limits
Typ
Max
Unit
1
Comments
30
sec
Excludes 00H programming
(Note 1)
prior to erasure.
16
1000
us
Excludes System-level overhead.
(Note 2)
8.0
50
sec Excludes system-level overhead.
(Note 1)
100,000 1,000,000
cycles 10,000 Min for none E variant
Notes: (1) 25OC, 5V VCC, 100,000 cycles.
(2) The Embedded Algorithms allow for 48ms byte program time.
23
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
Version 'A' Block Diagram
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
Vcc
Version 'A' Pin Definition
PUMA 68F16006A
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
A17
WE2
WE3
WE4
A18
GND
NC
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
VIEW
17
53
FROM
18
52
19
51
ABOVE
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A0~A18
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
OE
WE4
WE3
WE2
WE1
512K x 8
FLASH
512K x 8
FLASH
512K x 8
FLASH
512K x 8
FLASH
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
SCREENING
Military Screening Procedure
Screening Flow for high reliability product is in accordance with Mil-883 method 5004 .
MB MODULE SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
1010 Condition B (10 Cycles,-55oC to +125oC)
100%
Pre-Burn-in electrical
Burn-in
Per applicable device specifications at TA=+25oC
TA=+125oC,160hrs minimum.
100%
100%
Final Electrical Tests
Per applicable Device Specification
Static (DC)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (AC)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
External Visual
2009 Per vendor or customer specification
100%
Temperature cycle
Burn-In
24
PUMA 68F16006/A-70/90/12/15
ISSUE 4.4 : May 2001
Package Information
Dimensions in mm(inches)
Plastic 68 Pin JEDEC Surface mount PLCC
25.27 (0.995) sq.
5.08
(0.200) max
25.02 (0.985) sq.
0.10 (0.004)
23.11 (0.910)
0.46
(0.018) typ.
24.13 (0.950)
1.27
(0.050) typ.
0.90 (0.035) typ.
Ordering Information
PUMA 68F16006AMB-70E
Speed
70
90
12
15
=
=
=
=
70 ns
90 ns
120 ns
150 ns
Temp. range/screening
Blank = Commercial Temperature
I = Industrial Temperature
M = Military Temperature
Special Features
Blank = Single WE
A = WE1-4
Organisation
16006 = 512K x 32, user configurable
as 1M x 16 and 2M x 8
Memory Type
Package
F = FLASH
PUMA 68 = 68 pin "J" Leaded PLCC
NOTE: The E variant is designated to parts with extended Erase/Write Cycle Endurance (100,000 Min.). If not
specified when ordered only a Erase/Write Cycle Endurance of 10,000 Minimum can be
guaranteed.
25
ISSUE 4.4 : May 2001
PUMA 68F16006/A-70/90/12/15
Visual Inspection Standard
All devices inspected to ANSI/J-STD-001B Class 2 standard
Moisture Sensitivity
Devices are moisture sensitive.
Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH).
After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow,
or equivalent processing (peak package body temp 220OC) must be :
A : Mounted within 72 Hours at factory conditions of <30OC/60% RH
OR
B : Stored at <20% RH
If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking
as specified below.
If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers
OR
B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers.
Packaging Standard
Devices packaged in dry nitrogen, JED-STD-020.
Packaged in trays as standard.
Tape and reel available for shipment quantities exceeding 200pcs upon request.
Soldering Recomendations
IR/Convection -
Ramp Rate
Temp. exceeding 183OC
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
150 secs. max.
225OC
20 secs max.
6OC/sec max.
Vapour Phase -
Ramp up rate
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
215 - 219OC
60 secs max.
6OC/sec max.
The above conditions must not be exceeded.
Note : The above recommendations are based on standard industry practice. Failure to comply with
the above recommendations invalidates product warranty.
26
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