UPD78064B Data Sheet
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78064B
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78064B is a product in the µPD78064B Subseries within the 78K/0 Series.
The Electro Magnetic Interference (EMI) noise generated inside the µPD78064B is reduced compared to the
µPD78064 Subseries.
A one-time PROM version, µPD78P064B that can operate in the same power supply voltage as the mask ROM
version, and various development tools are also provided.
For the details of functional description, refer to the following user’s manual. Be sure to read them before
starting design.
µPD78064B Subseries User’s Manual
: U10785E
78K/0 Series User’s Manual Instructions : U12326E
FEATURES
• Internal high-capacity ROM and RAM
• Internal ROM
: 32 Kbytes
• Internal high-speed RAM : 1024 bytes
• LCD display RAM
: 40 × 4 bits
• Three packages
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
• Minimum instruction execution time can be varied from
high-speed (0.4 µs) to ultra-low-speed (122 µs)
• I/O ports: 57 (including segment signal output alternatefunction pin)
• LCD controller/driver
Power supply voltage : VDD = 2.0 to 6.0 V
(static display mode)
: VDD = 2.5 to 6.0 V (1/3 bias)
: VDD = 2.7 to 6.0 V (1/2 bias)
• 8-bit resolution A/D converter: 8 channels
• Serial interface: 2 channels
• Timer: 5 channels
• Power supply voltage: VDD = 2.0 to 6.0 V
APPLICATIONS
Internal tuner audio equipment, communication equipment such as radio and cellular phone, pagers, meters, etc.
ORDERING INFORMATION
Part Number
Package
µPD78064BGC-×××-7EA
µPD78064BGC-×××-8EU
µPD78064BGF-×××-3BA
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Caution Two types of packages are available for the µPD78064BGC (refer to 11. PACKAGE DRAWINGS). For the
suppliable packages, consult an NEC sales representative.
Remark ××× indicates ROM code suffix.
The information in this document is subject to change without notice.
Document No. U11590EJ2V0DS00 (2nd edition)
Date Published June 1997 N
Printed in Japan
The mark
shows major revised points.
©
1996
µPD78064B
78K/0 SERIES DEVELOPMENT
The following shows the 78K/0 Series products development. Subseries names are shown inside frames.
Mass-produced products
Products under development
The subseries whose names end with Y supports
the I2C bus specifications.
Control
100-pin
µ PD78075B
µ PD78075BY
EMI noise reduced version of µ PD78078
100-pin
µ PD78078
µ PD78078Y
100-pin
µ PD78070A
µPD78070AY
ROM-less version of µPD78078
Enhanced serial I/O of µ PD78078 and functions are defined.
Enhanced serial I/O of µ PD78054, EMI noise reduced version
EMI noise reduced version of µPD78054
80-pin
µ PD780058
µPD780018AY
µPD780058YNote
80-pin
µ PD78058F
µPD78058FY
80-pin
µ PD78054
µPD78054Y
100-pin
Added timers to µPD78054 and enhanced external interface
Added UART and D/A to µ PD78014 and enhanced I/Os
64-pin
µ PD780034
µ PD780034Y
Enhanced A/D of µ PD780024
64-pin
µ PD780024
µ PD780024Y
Enhanced serial I/O of µ PD78018F, EMI noise reduced version
64-pin
µ PD78014H
64-pin
µ PD78018F
µ PD78018FY
Low-voltage (1.8 V) version of µ PD78014 and enhanced ROM/RAM size options
64-pin
µ PD78014
µ PD78014Y
Added A/D and 16-bit timer to µ PD78002
64-pin
µ PD780001
64-pin
µ PD78002
42-/44-pin
µ PD78083
EMI noise reduced version of µPD78018F
Added A/D to µPD78002
µ PD78002Y
Basic subseries for control applications
Equipped with UART and operates at low-voltage (1.8 V)
Inverter control
64-pin
µ PD780964
Enhanced A/D of µ PD780924
64-pin
µ PD780924
Equipped with inverter control circuit and UART, EMI noise reduced version
78K/0
Series
FIPTM driving
100-pin
µ PD780208
Enhanced I/O and FIP C/D of µPD78044F, 53 display outputs
100-pin
µ PD780228
Enhanced I/O and FIP C/D of µPD78044H, 48 display outputs
80-pin
µ PD78044H
Added N-ch open-drain I/O to µ PD78044F, 34 display outputs
80-pin
µ PD78044F
Basic subseries for driving FIPs, 34 display outputs
LCD driving
100-pin
µ PD780308
100-pin
µ PD78064B
100-pin
µ PD78064
µ PD780308Y
Enhanced SIO of µ PD78064, expanded ROM and RAM
EMI noise reduced version of µPD78064
µ PD78064Y
Basic subseries for driving LCDs, equipped with UART
IEBusTM supported
80-pin
µ PD78098B
EMI noise reduced version of µPD78098
80-pin
µ PD78098
Added IEBus controller to µPD78054
Meter control
80-pin
µ PD780973
Equipped with controller/driver for driving automobile meters
LV
64-pin
Note Planned
2
µPD78P0914
Equipped with PWM output, LV digital code decoder, and Hsync counter
µPD78064B
The following shows the major differences among subseries products.
Function
Subseries Name
Control
ROM
Capacity
µPD78075B
32 K to 40 K
µPD78078
48 K to 60 K
µPD78070A
–
µPD780058
24 K to 60 K
µPD78058F
48 K to 60 K
µPD78054
16 K to 60 K
µPD780034
8 K to 32 K
Timer
8-bit 10-bit 8-bit
8-bit 16-bit Watch WDT A/D
4ch
1ch
1ch
1ch
8ch
A/D
D/A
–
2ch
2ch
–
8ch
8ch
–
–
µPD78014H
8 K to 60 K
µPD78014
8 K to 32 K
µPD780001
8K
µPD78002
8 K to 16 K
–
–
–
–
8ch
µPD780964
FIP
driving
µPD780208
32 K to 60 K
2ch
1ch
1ch
µPD780228
48 K to 60 K
3ch
–
–
µPD78044H
32 K to 48 K
2ch
1ch
1ch
µPD78044F
16 K to 40 K
µPD780308
48 K to 60 K
µPD78064B
32 K
µPD78064
16 K to 32 K
3ch Note
–
1ch
µPD780924
32 K to 60 K
Meter
control
µPD780973
LV
µPD78P0914
3ch (UART: 1ch)
88
1.8 V
61
2.7 V
3ch (Time division 68
UART: 1ch)
1.8 V
3ch (UART: 1ch)
2.7 V
69
√
3ch (UART: 1ch, Time
division 3-wire: 1ch)
51
2ch
53
1.8 V
1ch
–
8ch
8ch
–
8ch
–
39
–
53
√
1ch (UART: 1ch)
33
1.8 V
–
–
2ch (UART: 2ch)
47
2.7 V
√
–
2ch
74
2.7 V
–
1ch
72
4.5 V
68
2.7 V
57
2.0 V
–
2ch
2ch
1ch
1ch
1ch
8ch
–
–
driving
IEBus
µPD78098B
supported µPD78098
External
MIN. Value Expansion
1ch
1ch
Inverter
control
LCD
VDD
2.7 V
µPD78083
8 K to 32 K
I/O
2.0 V
µPD780024
µPD78018F
Serial Interface
3ch (Time division
UART: 1ch)
2ch (UART: 1ch)
2ch
1ch
1ch
1ch
8ch
–
2ch
3ch (UART: 1ch)
69
2.7 V
√
24 K to 32 K
3ch
1ch
1ch
1ch
5ch
–
–
2ch (UART: 1ch)
56
4.5 V
–
32 K
6ch
–
–
1ch
8ch
–
–
2ch
54
4.5 V
√
40 K to 60 K
Note 10-bit timer: 1 channel
3
µPD78064B
FUNCTION OVERVIEW
Item
Internal memory
Function
ROM
32 Kbytes
High-speed RAM
1024 bytes
LCD display RAM
40 × 4 bits
General registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Instruction
cycle
When main system clock
is selected
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation)
When subsystem clock
122 µs (@ 32.768-kHz operation)
is selected
Instruction set
•
•
•
•
I/O ports
(including segment signal output
alternate-function pins)
Total
• CMOS input
• CMOS I/O
: 57
: 02
: 55
A/D converter
• 8-bit resolution × 8 channels
LCD controller/driver
• Segment signal output : Maximum 40
• Common signal output : Maximum 4
• Bias
: 1/2 or 1/3 switchable
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel
• 3-wire serial I/O/UART mode selectable
: 1 channel
Timer
•
•
•
•
Timer output
3 (14-bit PWM output capability: 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz
(@ 5.0-MHz operation with main system clock)
32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0-MHz operation with main system clock)
Vectored interrupt
source
4
16-bit operation
Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulate (set, reset, test, Boolean operation)
BCD adjust, etc.
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
Maskable
Internal: 12, external: 6
Non-maskable
Internal: 1
Software
1
:
:
:
:
1
2
1
1
channel
channels
channel
channel
Test input
Internal: 1, external: 1
Power supply voltage
VDD = 2.0 to 6.0 V
Package
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
µPD78064B
CONTENTS
1.
PIN CONFIGURATION (Top View) ................................................................................................ 6
2.
BLOCK DIAGRAM ............................................................................................................................ 9
3.
PIN FUNCTIONS ............................................................................................................................. 10
3.1
Port Pins ................................................................................................................................................... 10
3.2
3.3
Non-port Pins .......................................................................................................................................... 12
Pin I/O Circuits and Recommended Connection of Unused Pins ................................................... 13
4.
MEMORY SPACE ............................................................................................................................ 17
5.
PERIPHERAL HARDWARE FUNCTION FEATURE .................................................................. 18
6.
5.1
5.2
Port ............................................................................................................................................................ 18
Clock Generator ...................................................................................................................................... 19
5.3
5.4
Timer/Event Counter ............................................................................................................................... 19
Clock Output Control Circuit................................................................................................................. 22
5.5
5.6
Buzzer Output Control Circuit .............................................................................................................. 22
A/D Converter .......................................................................................................................................... 23
5.7
5.8
Serial Interface ........................................................................................................................................ 23
LCD Controller/Driver ............................................................................................................................. 25
INTERRUPT FUNCTIONS AND TEST FUNCTIONS ................................................................. 26
6.1
6.2
Interrupt Functions ................................................................................................................................. 26
Test Functions ......................................................................................................................................... 30
7.
STANDBY FUNCTION .................................................................................................................... 31
8.
RESET FUNCTION .......................................................................................................................... 31
9.
INSTRUCTION SET ........................................................................................................................ 32
10. ELECTRICAL SPECIFICATIONS ................................................................................................... 34
11. PACKAGE DRAWINGS .................................................................................................................. 54
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 57
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 58
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 60
5
µPD78064B
1. PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
µPD78064BGC-×××-7EA
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
AVREF
P100
9
10
P101
VSS
P102
11
12
13
P103
P30/TO0
14
15
P31/TO1
P32/TO2
16
17
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
18
19
20
21
P72/SCK2/ASCK
X1
X2
IC
XT1/P07
VDD
XT2
P71/SO2/TXD
71
P70/SI2/RXD
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P80/S39
70
69
68
P81/S38
P82/S37
P83/S36
67
66
65
P84/S35
P85/S34
64
63
62
61
60
59
58
57
56
55
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
S20
S19
S18
S13
S14
S15
S16
S17
54
22
53
23
52
24
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
COM3
BIAS
VLC0
COM0
COM1
COM2
P113
P112
P111
P110
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1/TI01
P00/INTP0/TI00
RESET
7
8
S6
S7
S8
S9
S10
S11
S12
P17/ANI7
AVDD
5
6
S3
S4
S5
P14/ANI4
P15/ANI5
P16/ANI6
S0
S1
S2
P12/ANI2
P13/ANI3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
2
73
3
72
4
VLC1
VLC2
VSS
P11/ANI1
AVSS
P117
P116
P115
P114
P10/ANI0
µPD78064BGC-×××-8EU
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS.
2. The AVDD pin functions as both an A/D converter power supply and a port power supply. When
the µPD78064B is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVDD pin to another power supply which has the same potential
as VDD.
3. The AVSS pin functions as both an A/D converter ground and a port ground. When the µPD78064B
is used in applications where the noise generated inside the microcontroller needs to be
reduced, connect the AVSS pin to another ground line than VSS.
6
µPD78064B
VDD
XT1/P07
9
10
XT2
RESET
P00/INTP0/TI00
11
12
13
P01/INTP1/TI01
P02/INTP2
14
15
P03/INTP3
P04/INTP4
16
17
P05/INTP5
P110
P111
P112
P113
18
19
20
21
22
P114
P115
P116
P117
AVSS
P10/ANI0
23
24
25
26
27
28
S22
S21
S23
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
VSS
VLC2
VLC1
VLC0
BIAS
COM3
COM2
COM1
COM0
P37
53
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P13/ANI3
P14/ANI4
P15/ANI5
P11/ANI1
P12/ANI2
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
75
74
73
7
8
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
X2
X1
76
5
6
VSS
P102
P103
P71/SO2/TXD
P72/SCK2/ASCK
IC
AVREF
P100
P101
P27/SCK0
P70/SI2/RXD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
2
78
3
77
4
P16/ANI6
P17/ANI7
AVDD
P26/SO0/SB1
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P25/SI0/SB0
• 100-pin plastic QFP (14 × 20 mm)
µPD78064BGF-×××-3BA
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS.
2. The AVDD pin functions as both an A/D converter power supply and a port power supply. When
the µPD78064B is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVDD pin to another power supply which has the same potential
as VDD.
3. The AVSS pin functions as both an A/D converter ground and a port ground. When the µPD78064B
is used in applications where the noise generated inside the microcontroller needs to be
reduced, connect the AVSS pin to another ground line than VSS.
7
µPD78064B
ANI0 to ANI7
ASCK
: Analog Input
: Asynchronous Serial Clock
P110 to P117
PCL
: Port11
: Programmable Clock
AVDD
AVREF
: Analog Power Supply
: Analog Reference Voltage
RESET
RxD
: Reset
: Receive Data
AVSS
BIAS
: Analog Ground
: LCD Power Supply Bias Control
S0 to S39
SB0, SB1
: Segment Output
: Serial Bus
BUZ
COM0 to COM3
: Buzzer Clock
: Common Output
SI0, SI2
SO0, SO2
: Serial Input
: Serial Output
IC
INTP0 to INTP5
: Internally Connected
: Interrupt from Peripherals
SCK0, SCK2
TI00, TI01
: Serial Clock
: Timer Input
P00 to P05, P07 : Port0
P10 to P17
: Port1
TI1, TI2
TO0 to TO2
: Timer Input
: Timer Output
P25 to P27
P30 to P37
: Port2
: Port3
TxD
VDD
: Transmit Data
: Power Supply
P70 to P72
P80 to P87
: Port7
: Port8
VLC0 to VLC2
VSS
: LCD Power Supply
: Ground
P90 to P97
P100 to P103
: Port9
: Port10
X1, X2
XT1, XT2
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
8
µPD78064B
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
P00
16-bit TIMER/
EVENT COUNTER
PORT0
P01 to P05
P07
TO1/P31
TI1/P33
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 1
8-bit TIMER/
EVENT COUNTER 2
PORT1
P10 to P17
PORT2
P25 to P27
PORT3
P30 to P37
PORT7
P70 to P72
PORT8
P80 to P87
PORT9
P90 to P97
PORT10
P100 to P103
PORT11
P110 to P117
WATCHDOG TIMER
WATCH TIMER
SI0/SB0/P25
SO0/SB1/P26
SERIAL
INTERFACE 0
78K/0
CPU CORE
ROM
SCK0/P27
SI2/RxD/P70
SO2/TxD/P71
SERIAL
INTERFACE 2
SCK2/ASCK/P72
S0 to S23
ANI0/P10 to
ANI7/P17
RAM
A/D CONVERTER
LCD
CONTROLLER/
DRIVER
AVREF
INTP0/P00 to
INTP5/P05
BUZ/P36
PCL/P35
S24/P97 to
S31/P90
S32/P87 to
S39/P80
COM0 to COM3
VLC0 to VLC2
INTERRUPT
CONTROL
BIAS
fLCD
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
VDD
VSS
AVDD AVSS IC
SYSTEM
CONTROL
RESET
X1
X2
XT1/P07
XT2
9
µPD78064B
3. PIN FUNCTIONS
3.1
Port Pins (1/2)
Pin Name
P00
Input
P01
After
Reset
Alternate
Function
Input only.
Input
INTP0/TI00
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor
can be used by software.
Input
INTP1/TI01
I/O
Function
Port 0
Input/output 7-bit I/O port.
P02
INTP2
P03
INTP3
P04
INTP4
P05
INTP5
P07Note 1
Input
Input only.
Input
XT1
P10 to P17
Input/output
Port 1
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.Note 2
Input
ANI0 to ANI7
P25
Input/output
Port 2
3-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Input
SI0/SB0
Input/output Port 3
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Input
P26
P27
P30
P31
P32
P33
SO0/SB1
SCK0
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P70
Input/output
P71
P72
Port 7
3-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Input
SI2/RxD
SO2/TxD
SCK2/ASCK
Notes 1.
When using the P07/XT1 pins as an input port, set (1) bit 6 (FRC) of the processor clock control register
2.
(PCC) (the on-chip feedback resistor of the subsystem clock oscillator should not be used).
When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, port 1 is set to input mode.
However, the on-chip pull-up resistor is automatically disabled.
10
µPD78064B
3.1
Port Pins (2/2)
Pin Name
I/O
Function
After
Reset
Alternate
Function
P80 to P87
Input/output Port 8
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Input/output port/segment signal output function can be specified in 2-bit
units by the LCD display control register (LCDC).
Input
S39 to S32
P90 to P97
Input/output Port 9
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Input/output port/segment signal output function can be specified in 2-bit
units by the LCD display control register (LCDC).
Input
S31 to S24
P100 to P103
Input/output Port 10
4-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
LEDs can be driven directly.
Input
—
P110 to P117
Input/output Port 11
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Falling edge detection capability.
Input
—
Caution For pins which also function as port pins, do not perform the following operations during A/D
conversion. If these operations are performed, the total error ratings cannot be kept (except for LCD
segment output alternate-function pin).
<1> Rewrite the output latch while the pin is used as a port pin.
<2> Change the output level of the pin used as an output pin, even if it is not used as a port pin.
11
µPD78064B
3.2
Non-port Pins (1/2)
Pin Name
INTP0
I/O
Function
Input
External interrupt request input by which the effective edge (rising edge,
falling edge, or both rising edge and falling edge) can be specified.
INTP1
After
Reset
Input
Alternate
Function
P00/TI00
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
P05
SI0
Input
Serial interface serial data input.
Input
SI2
SO0
P70/RxD
Output
Serial interface serial data output.
Input
SO2
SB0
P26/SB1
P71/TxD
Input/output Serial interface serial data input/output.
Input
SB1
SCK0
P25/SB0
P25/SI0
P26/SO0
Input/output Serial interface serial clock input/output.
Input
SCK2
P27
P72/ASCK
RxD
Input
Asynchronous serial interface serial data input.
Input
P70/SI2
TxD
Output
Asynchronous serial interface serial data output.
Input
P71/SO2
ASCK
Input
Asynchronous serial interface serial clock input.
Input
P72/SCK2
TI00
Input
External count clock input to 16-bit timer (TM0).
Input
P00/INTP0
TI01
Capture trigger signal input to capture register (CR00).
P01/INTP1
TI1
External count clock input to 8-bit timer (TM1).
P33
TI2
External count clock input to 8-bit timer (TM2).
P34
TO0
Output
16-bit timer (TM0) output (shared with 14-bit PWM output).
Input
P30
TO1
8-bit timer (TM1) output.
P31
TO2
8-bit timer (TM2) output.
P32
PCL
Output
Clock output (for main system clock, subsystem clock trimming).
Input
P35
BUZ
Output
Buzzer output.
Input
P36
S0 to S23
Output
LCD controller/driver segment signal output.
S24 to S31
Output
—
Input
P97 to P90
S32 to S39
COM0 to COM3
P87 to P80
Output
LCD controller/driver common signal output.
Output
—
VLC0 to VLC2
—
LCD drive voltage. Split resistors can be incorporated by mask option.
—
—
BIAS
—
LCD drive power supply.
—
—
12
µPD78064B
3.2
Non-port Pins (2/2)
Pin Name
I/O
Function
After
Alternate
Reset
Function
ANI0 to ANI7
Input
A/D converter analog input.
Input
P10 to P17
AVREF
Input
A/D converter reference voltage input.
—
—
AVDD
—
A/D converter analog power supply (shared with the port power supply).
—
—
AVSS
—
A/D converter ground potential (shared with the port ground potential).
—
—
RESET
Input
System reset input.
—
—
X1
Input
Main system clock oscillation crystal connection.
—
—
X2
—
—
—
XT1
Input
XT2
—
VDD
—
VSS
IC
Subsystem clock oscillation crystal connection.
Input
P07
—
—
Positive power supply (except for port).
—
—
—
Ground potential (except for port).
—
—
—
Internal connection. Connect directly to VSS pin.
—
—
Cautions 1. The AVDD pin functions as both an A/D converter power supply and a port power supply. When
the µPD78064B is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVDD pin to another power supply which has the same potential
as VDD.
2. The AVSS pin functions as both an A/D converter ground and a port ground. When the µPD78064B
is used in applications where the noise generated inside the microcontroller needs to be
reduced, connect the AVSS pin to another ground line than VSS.
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Input/Output
Circuit Type
I/O
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-D
Input/output
16
Input
P10/ANI0 to P17/ANI7
11-C
Input/output
P25/SI0/SB0
10-C
Pin Name
Recommended Connection when Not Used
Connect to VSS.
Individually connect to VSS via a resistor.
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1
Connect to VDD.
Individually connect to VDD or VSS via a resistor.
P26/SO0/SB1
P27/SCK0
P30/TO0
5-J
P31/TO1
P32/TO2
13
µPD78064B
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Pin Name
P33/TI1
Input/Output
Circuit Type
I/O
8-D
Input/output
Recommended Connection when Not Used
Individually connect to VDD or VSS via a resistor.
P34/TI2
P35/PCL
5-J
P36/BUZ
P37
P70/SI2/RxD
8-D
P71/SO2/TxD
5-J
P72/SCK2/ASCK
8-D
P80/S39 to P87/S32
17-E
P90/S31 to P97/S24
P100 to P103
5-J
P110 to P117
8-D
S0 to S23
17-D
COM0 to COM3
18-B
VLC0 to VLC2
Individually connect to VDD via a resistor.
Output
—
—
RESET
2
Input
XT2
16
—
AVREF
—
Leave open.
BIAS
—
Leave open.
Connect to VSS.
AVDD
Connect to another power supply which has the same potential as VDD.
AVSS
Connect to another ground line which has the same potential as VSS.
IC
Connect to VSS directly.
14
µPD78064B
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2
Type 10-C
AVDD
pull-up
enable
P-ch
AVDD
IN
data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristic
open-drain
output disable
N-ch
AVSS
Type 11-C
Type 5-J
AVDD
AVDD
pull-up
enable
pull-up
enable
P-ch
P-ch
AVDD
data
P-ch
AVDD
IN/OUT
data
P-ch
output
disable
IN/OUT
output
disable
Comparator
N-ch
N-ch
P-ch
AVSS
+
–
AVSS
VREF
input
enable
N-ch
AVSS
(Threshold voltage)
input
enable
Type 16
Type 8-D
AVDD
pull-up
enable
feedback
cut-off
P-ch
P-ch
AVDD
data
P-ch
IN/OUT
output
disable
N-ch
AVSS
XT1
XT2
15
µPD78064B
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 17-D
Type 18-B
VLC0
VLC0
P-ch
P-ch
VLC1
VLC1
N-ch
N-ch
P-ch
P-ch
SEG
data
OUT
N-ch
P-ch
COM
data
N-ch
VLC2
VLC2
N-ch
P-ch
N-ch
VSS
VSS
Type 17-E
AVDD
pull-up
enable
P-ch
AVDD
data
P-ch
IN/OUT
N-ch
output
disable
AVSS
input
enable
VLC0
P-ch
VLC1
N-ch
P-ch
SEG
data
N-ch
P-ch
VLC2
N-ch
VSS
16
N-ch
P-ch
OUT
µPD78064B
4. MEMORY SPACE
The memory map of the µPD78064B is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH
Special Function Register (SFR)
256 × 8 bits
FF00H
FEFFH
General Registers
FEE0H
32 × 8 bits
Internal High-speed RAM
1024 × 8 bits
FB00H
FAFFH
7FFFH
Program Area
Data Memory
Space
Use Prohibited
FA80H
FA7FH
1000H
0FFFH
CALLF Entry Area
LCD Display RAM
40 × 4 bits
FA58H
0800H
07FFH
FA57H
Program Area
Use Prohibited
8000H
7FFFH
Program
Memory
Space
0080H
007FH
CALLT Table Area
Internal ROM
0040H
003FH
32768 × 8 bits
0000H
Vector Table Area
0000H
17
µPD78064B
5. PERIPHERAL HARDWARE FUNCTION FEATURE
5.1
Port
There are two kinds of I/O port.
• CMOS input (P00, P07)
• CMOS input/output (P01 to P05, Port 1 to 3, 7 to 11)
: 2
: 55
Total
: 57
Table 5-1. Functions of Ports
Name
Port 0
Pin Name
Function
P00, P07
Dedicated input port
P01 to P05
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 1
P10 to P17
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 2
P25 to P27
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 3
P30 to P37
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 7
P70 to P72
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 8
P80 to P87
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display
control register (LCDC).
Port 9
P90 to P97
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display
control register (LCDC).
Port 10
P100 to P103
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Can drive LEDs directly.
Port 11
P110 to P117
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
18
µPD78064B
5.2 Clock Generator
There are two kinds of clocks, main system clock and subsystem clock.
The instruction execution time can also be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation with main system clock)
• 122 µs (@ 32.768-kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
XT2
Subsystem
Clock
Oscillator
Watch Timer
Clock Output
Function
fXT
Prescaler
X1
X2
Main
System
Clock
Oscillator
fX
Selector
Clock to
Peripheral
Hardware
Prescaler
fXX
1/2
Scaler
fX
2
fXX
2
fXX
22
fXX
23
fXX fXT
24 2
STOP
Selector
CPU
Clock
(fCPU)
Standby
Control
Circuit
To INTP0
Sampling Clock
5.3 Timer/Event Counter
Five timer/event counter channels are incorporated.
• 16-bit timer/event counter
• 8-bit timer/event counter
: 1 channel
: 2 channels
• Watch timer
• Watchdog timer
: 1 channel
: 1 channel
Table 5-2. Timer/Event Counter Types and Functions
16-bit Timer/
Event Counter
Type
Function
8-bit Timer/
Event Counter
Watch Timer
Watchdog Timer
Interval timer
1 channel
2 channels
1 channel
1 channel
External event counter
1 channel
2 channels
—
—
Timer output
1 output
2 outputs
—
—
PWM output
1 output
—
—
—
Pulse width measurement
2 inputs
—
—
—
Square wave output
1 output
2 outputs
—
—
One-shot pulse output
1 output
—
—
—
Interrupt request
2
2
1
1
Test input
—
—
1 input
—
19
µPD78064B
Figure 5-2. 16-bit Timer/Event Counter Block Diagram
Internal Bus
INTP1
TI01/P01/INTP1
16-bit
Capture/Compare
Register (CR00)
Selector
PWM
Pulse
Output
Control
Circuit
Match
Watch Timer Output
2fXX
fXX
fXX/22
Clear
Edge
Detector
TI00/P00/INTP0
Output
Control Circuit
TO0/P30
16-bit
Timer Register
(TM0)
Selector
fXX/2
INTTM00
Selector
Match
INTTM01
INTP0
16-bit
Capture/Compare
Register
(CR01)
Internal Bus
Figure 5-3. 8-bit Timer/Event Counter Block Diagram
Internal Bus
INTTM1
8-bit
Compare
Register (CR10)
8-bit
Compare Register
(CR20)
Selector
Match
Match
fXX/2 to
Output
Control
Circuit
INTTM2
fXX/29
fXX/211
TO2/P32
Selector
8-bit
Timer Register 1
(TM1)
TI1/P33
Clear
Selector
8-bit
Timer Register 2
(TM2)
Clear
fXX/2 to fXX/29
fXX/211
Selector
Selector
TI2/P34
Output
Control
Circuit
Internal Bus
20
TO1/P31
µPD78064B
Figure 5-4. Watch Timer Block Diagram
fW
214
fXX/27
Selector
Selec- fW
tor
5-bit Counter
Selector
Prescaler
fXT
fW
24
fW
25
fW
26
fW
27
fW
28
INTWT
fW
213
fW
29
INTTM3
Selector
To 16-bit
Timer/Event
Counter
To LCD
Controller/
Driver
Figure 5-5. Watchdog Timer Block Diagram
fXX
23
Prescaler
fXX
24
fXX
25
fXX
26
fXX
27
fXX
28
fXX
29
fXX
211
INTWDT
Maskable
Interrupt
Request
Selector
8-bit Counter
Control
Circuit
RESET
INTWDT
Non-maskable
Interrupt
Request
21
µPD78064B
5.4 Clock Output Control Circuit
Clocks of the following frequency can be output as clock outputs.
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (@ 5.0-MHz operation with
main system clock)
• 32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Figure 5-6. Clock Output Control Circuit Block Diagram
fXX
fXX/2
fXX/22
fXX/23
fXX/24
fXX/25
fXX/26
fXX/27
fXT
5.5
Synchronization
Circuit
Selector
Output Control Circuit
PCL/P35
Buzzer Output Control Circuit
Clocks of the following frequency can be output as buzzer outputs.
• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (@ 5.0-MHz operation with main system clock)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
fXX/29
fXX/210
fXX/211
22
Selector
Output Control Circuit
BUZ/P36
µPD78064B
5.6 A/D Converter
Eight 8-bit resolution A/D converter channels are incorporated.
The following two types of start-up method are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series Resistor String
AVDD
AVREF
ANI0/P10
Sample & Hold Circuit
ANI1/P11
ANI2/P12
Voltage Comparator
ANI3/P13
Selector
ANI4/P14
Tap
Selector
ANI5/P15
ANI6/P16
AVSS
Successive Approximation
Register (SAR)
ANI7/P17
Edge
Detector
INTP3/P03
Control
Circuit
INTAD
INTP3
A/D Conversion Result
Register (ADCR)
Internal Bus
Caution For pins which also function as port pins (refer to 3.1 Port Pins), do not perform the following
operations during A/D conversion. If these operations are performed, the total error ratings cannot
be kept (except for LCD segment output alternate-function pin).
<1> Rewrite the output latch while the pin is used as a port pin.
<2> Change the output level of the pin used as an output pin, even if it is not used as a port pin.
5.7
Serial Interface
Two clocked serial interface channels are incorporated.
• Serial interface channel 0
• Serial interface channel 2
Table 5-3. Serial Interface Types and Functions
Function
Serial Interface Channel 0
Serial Interface Channel 2
3-wire serial I/O mode
Yes (MSB/LSB-first switchable)
Yes (MSB/LSB-first switchable)
SBI (serial bus interface) mode
Yes (MSB-first)
No
2-wire serial I/O mode
Yes (MSB-first)
No
Asynchronous serial interface
(UART) mode
No
Yes (Dedicated baud rate generator
incorporated)
23
µPD78064B
Figure 5-9. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
Selector
Serial I/O
Shift Register 0 (SIO0)
Output
Latch
SO0/SB1/P26
Selector
SCK0/P27
Busy/Acknowledge
Output Circuit
Bus Release/Command/
Acknowledge Detector
Interrupt Request
Signal Generator
Serial Clock Counter
INTCSI0
fXX/2 to fXX/28
Serial Clock Control Circuit
Selector
TO2
Figure 5-10. Serial Interface Channel 2 Block Diagram
Internal bus
RXD/SI2/P70
Receive Buffer
Register (RXB/SIO2)
Direction
Control Circuit
Direction
Control Circuit
Transmit Shift
Register (TXS/SIO2)
Receive Shift
Register (RXS)
Transmit
Control Circuit
TXD/SO2/P71
Receive
Control Circuit
ASCK/SCK2/P72
INTSER
INTSR/INTCSI2
SCK Output
Control Circuit
Baud Rate
Generator
24
fXX to fXX/210
INTST
µPD78064B
5.8 LCD Controller/Driver
An LCD controller/driver with the following functions is incorporated.
• Selection of 5 types of display mode
• 16 of the segment signal of outputs can be switched to input/output ports in units of 2. (P80/S39 to P87/S32,
P90/S31 to P97/S24)
Table 5-4. Display Mode Types and Maximum Number of Display Pixels
Bias Method
Time Multiplexing
—
1/2
Static
2
3
3
4
1/3
Common Signal Used
Maximum Number of Display Pixels
COM0 (COM1 to COM3)
COM0, COM1
COM0 to COM2
COM0 to COM2
COM0 to COM3
40 (40 segments × 1 common)
80 (40 segments × 2 commons)
120 (40 segments × 3 commons)
160 (40 segments × 4 commons)
Figure 5-11. LCD Controller/Driver Block Diagram
Internal Bus
fW
26
Prescaler
Display
Data Memory
fW
29
Timing Controller
Segment
Data Selector
fW
28
fW
27
LCDCL
Selector
Port
Output Data
LCD Drive Voltage
Generator
Common Driver
Segment Driver
S0
S23 S24/P97
S39/P80
COM0 COM1 COM2 COM3
VLC2
VLC1
VLC0
BIAS
25
µPD78064B
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions
There are twenty interrupt sources of three different kinds, as shown below.
• Non-maskable : 1
• Maskable
: 18
• Software
26
: 1
µPD78064B
Table 6-1. Interrupt Source List
Interrupt Source
Interrupt
Type
Default
PriorityNote 1
Nonmaskable
—
INTWDT
Watchdog timer overflow (with watchdog timer
mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow (with interval timer
mode selected)
1
INTP0
Pin input edge detection
2
Notes 1.
2.
Trigger
Vector
Table
Address
Basic
Configuration
TypeNote 2
Internal
0004H
(A)
(B)
0006H
(C)
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTCSI0
Serial interface channel 0 transfer termination
8
INTSER
Serial interface channel 2 UART reception
error generation
0018H
9
INTSR
Serial interface channel 2 UART reception
termination
001AH
INTCSI2
Serial interface channel 2 3-wire transfer
termination
INTST
Serial interface channel 2 UART transmission
termination
001CH
11
INTTM3
Reference time interval signal from watch timer
001EH
12
INTTM00
16-bit timer register and capture/compare
register (CR00) match signal generation
0020H
13
INTTM01
16-bit timer register and capture/compare
register (CR01) match signal generation
0022H
14
INTTM1
8-bit timer/event counter 1 match signal
generation
0024H
15
INTTM2
8-bit timer/event counter 2 match signal
generation
0026H
16
INTAD
A/D converter conversion termination
0028H
—
BRK
BRK instruction execution
10
Software
Name
Internal/
External
External
Internal
—
0014H
003EH
(B)
(E)
Default priority is a priority order when more than one maskable interrupt request is generated simultaneously.
0 is the highest priority and 16 the lowest priority.
Basic configuration types (A) to (E) correspond to those shown in Figure 6-1.
27
µPD78064B
Figure 6-1. Basic Configuration of Interrupt Functions (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Priority
Control
Circuit
Interrupt
Request
Vector Table
Address
Generator
Standby Release
Signal
(B) Internal maskable interrupt
Internal Bus
MK
Interrupt
Request
IE
PR
ISP
Vector Table
Address
Generator
Priority
Control
Circuit
IF
Standby Release
Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Interrupt
Request
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
Sampling
Clock
Edge
Detector
MK
IF
IE
PR
Priority
Control
Circuit
ISP
Vector Table
Address
Generator
Standby
Release
Signal
28
µPD78064B
Figure 6-1. Basic Configuration of Interrupt Functions (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
Interrupt
Request
MK
Edge
Detector
IE
PR
Priority
Control
Circuit
IF
ISP
Vector Table
Address
Generator
Standby
Release
Signal
(E) Software interrupt
Internal Bus
Priority
Control
Circuit
Interrupt
Request
IF
Vector Table
Address
Generator
: Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
29
µPD78064B
6.2 Test Functions
There are two test functions as shown in Table 6-2.
Table 6-2. Test Input Source List
Test Input Source
Name
Internal/External
Trigger
INTWT
Watch timer overflow
Internal
INTPT11
Port 11 falling edge detection
External
Figure 6-2. Basic Configuration of Test Function
Internal Bus
MK
Test Input
Signal
IF
IF : Test input flag
MK : Test mask flag
30
Standby Release
Signal
µPD78064B
7. STANDBY FUNCTION
The standby function is a function to reduce the consumption current and there are the following two kinds of standby
functions.
• HALT mode : Halts CPU operating clock and can reduce average consumption current by the intermittent
operation along with the normal operation.
• STOP mode : Halts main system clock oscillation. Halts all operations with the main system clock and sets ultralow power dissipation state with subsystem clock only.
Figure 7-1. Standby Function
CSS = 1
Subsystem Clock OperationNote
Main System Clock Operation
CSS = 0
STOP
Instruction
Interrupt
Request
(
Note
STOP Mode
Main System Clock
Oscillation Halted
HALT Instruction
HALT Instruction
Interrupt
Request
Interrupt
Request
)
HALT Mode
Clock Supply to CPU Halted,
Oscillation Maintained
(
)
HALT ModeNote
Clock Supply to CPU Halted,
Oscillation Maintained
(
)
Halting the main system clock enables the consumption current to be reduced.
When the CPU is operated by the subsystem clock, the main system clock should be halted by setting the bit
7 (MCC) of the processor clock control register (PCC). The STOP instruction is not available.
Caution
When the main system clock is stopped and the system is operated by the subsystem clock, the
main system clock should be returned to after securing the oscillation stabilization time by a
program.
8. RESET FUNCTION
There are the following two kinds of resetting methods.
• External reset by RESET pin
• Internal reset by watchdog timer runaway time detection
31
µPD78064B
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd operand
#byte
A
rNote
sfr
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
saddr !addr16 PSW
[DE]
[HL]
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
1st operand
A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
B, C
sfr
saddr
!addr16
PSW
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
1
None
ROR
ROL
RORC
ROLC
INC
DEC
DBNZ
MOV
MOV
MOV
[DE]
[HL]
MOV
MOV
[HL+byte]
[HL+B]
[HL+C]
X
C
MOV
Note Except r = A
32
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
[HL+byte]
[HL+B]
$addr16
[HL+C]
DBNZ
INC
DEC
PUSH
POP
ROR4
ROL4
MULU
DIVUW
µPD78064B
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd operand
#word
AX
rpNote
sfrp
saddrp
!addr16
SP
None
1st operand
AX
rp
sfrp
saddrp
!addr16
SP
ADDW
SUBW
CMPW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
MOVW
MOVW
MOVW
MOVW
MOVWNote
INCW, DECW
PUSH, POP
MOVW
MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
1st operand
A.bit
MOV1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
(4) Call instruction/branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd operand
AX
!addr16
!addr11
[addr5]
$addr16
1st operand
Basic
instruction
Compound
instruction
BR
CALL
BR
CALLF
CALLT
BR, BC, BNC,
BZ, BNZ
BT, BF,
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
33
µPD78064B
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Ratings
Unit
VDD
–0.3 to +7.0
V
AVDD
–0.3 to VDD + 0.3
V
AVREF
–0.3 to VDD + 0.3
V
AVSS
–0.3 to +0.3
V
Input voltage
VI
–0.3 to VDD + 0.3
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Analog input voltage
VAN
P10 to P17
AVSS – 0.3 to AVREF + 0.3
V
Output current high
IOH
1 pin
–10
mA
Total for P01 to P05, P10 to P17, P25 to P27,
P30 to P37, P70 to P72, P80 to P87, P90 to P97,
P100 to P103, P110 to P117
–15
mA
1 pin
Peak value
30
mA
r.m.s. value
15
mA
Total for P01 to P05, P10 to P17, Peak value
P25 to P27, P30 to P37, P70 to
P72, P80 to P87, P90 to P97,
r.m.s. value
P100 to P103, P110 to P117
100
mA
70
mA
Supply voltage
Output current low
Symbol
IOLNote
Test Conditions
Analog input pin
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] × √Duty
Caution The product quality may be damaged even if a value of only one of the above parameters exceeds
the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That
is, the absolute maximum rating is a rating value which may cause a product to be damaged
physically. The absolute maximum rating values must therefore be observed in using the product.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
CAPACITANCE (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz
15
pF
Output capacitance
COUT
Unmeasured pins returned to
15
pF
I/O capacitance
CIO
0 V.
15
pF
34
µPD78064B
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Ceramic
Recommended circuit
X1
IC X2
resonator
Parameter
C1
C2
V DD = Oscillation
Oscillation
frequency
(fX)Note 1
resonator
C2
X1
X2
C1
frequency
timeNote 2
µPD74HCU04
X1
Unit
5
MHz
4
ms
5
MHz
10
ms
voltage range MIN.
1
Oscillation
V DD = 4.5 to 6.0 V
timeNote 2
X1 input
X2
1
MAX.
(fX)Note 1
stabilization
External clock
TYP.
voltage range
Oscillation
IC
MIN.
After VDD reaches oscillation
Oscillation
stabilization
Crystal
Test conditions
30
1.0
5.0
MHz
85
500
ns
frequency (fX)Note 1
X1 input
high-/low-level width
(tXH , tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC CHARACTERISTICS for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1.
When using the main system clock oscillator, wiring in the area enclosed with the dotted line
should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
2.
If the main system clock oscillator is operated by the subsystem clock when the main system
clock is stopped, reswitching to the main system clock should be performed after the oscillation
stabilization time has been obtained by the program.
35
µPD78064B
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Crystal
resonator
Recommended circuit
IC XT1
XT2
Parameter
Test conditions
Oscillation frequency
(fXT)Note 1
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
R2
C3
C4
Oscillation stabilization
timeNote 2
VDD = 4.5 to 6.0 V
10
External clock
XT1
XT2
XT1 input frequency
(fXT)Note 1
32
100
kHz
XT1 input
high-/low-level
width (tXTH/tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC CHARACTERISTICS for instruction execution time.
2. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line
should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
2. The subsystem clock oscillator is designed as a low amplification circuit to provide low
consumption current, causing misoperation by noise more frequently than the main system
clock oscillation circuit. Special care should therefore be taken to wiring method when the
subsystem clock is used.
36
µPD78064B
RECOMMENDED OSCILLATOR CONSTANT
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = –40 to +85°C)
Manufacturer
Product name
Frequency (MHz)
Recommended
Circuit Constant
Oscillation
Voltage Range
C1 (pF)
C2 (pF)
MIN. (V)
MAX. (V)
Remarks
Murata Mfg.
Co., Ltd.
CSA5.00MG
5.00
30
30
2.2
6.0
CST5.00MGW
5.00
On-chip
On-chip
2.7
6.0
Matsushita
Electronics
Components
Co., Ltd.
EF0GC5004A4
5.00
On-chip
On-chip
2.7
6.0
Lead type
EF0EC5004A4
5.00
On-chip
On-chip
2.0
6.0
Round lead type
EF0EN5004A4
5.00
33
33
2.7
6.0
Lead type
EF0S5004B5
5.00
On-chip
On-chip
2.7
6.0
Chip type
KBR-5.0MSA
5.00
33
33
2.7
6.0
Lead type
PBRC5.00A
5.00
33
33
2.7
6.0
Chip type
KBR-5.0MKS
5.00
On-chip
On-chip
2.7
6.0
Lead type
KBR-5.0MWS
5.00
On-chip
On-chip
2.7
6.0
Chip type
Kyocera
Corporation
SUBSYSTEM CLOCK: CRYSTAL RESONATOR (TA = –40 to +60°C)
Manufacturer
Product name
Kyocera
KF-38G-12P0200Note
Corporation
(Load capacitance 12 pF)
Recommended
Circuit Constant
Frequency (kHz)
32.768
Oscillation
Voltage Range
C3 (pF)
C4 (pF)
R2 (kΩ)
MIN. (V)
MAX. (V)
15
22
220
2.0
6.0
Note KF-38G-12P0200 is a maintainance product.
Caution The oscillator constant and the oscillation voltage range are the conditions required for stable
oscillation, but do not guarantee oscillation frequency accuracy. In the case of application requiring
oscillation frequency accuracy, the oscillation frequency of the resonator must be adjusted in a
mounted circuit. For details, contact the resonator manufacturer directly.
37
µPD78064B
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Input voltage
high-level
Symbol
VIH1
VIH2
VIH3
VIH4
Input voltage
low-level
VIL1
VIL2
Test Conditions
MAX.
Unit
0.7VDD
VDD
V
0.8VDD
VDD
V
0.8VDD
VDD
V
0.85VDD
VDD
V
VDD – 0.5
VDD
V
VDD – 0.2
VDD
V
4.5 V ≤ VDD ≤ 6.0 V
0.8VDD
VDD
V
2.7 V ≤ VDD < 4.5 V
0.9VDD
VDD
V
2.0 V ≤ VDD < 2.7 VNote
0.9VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
0
0.2VDD
V
0
0.15VDD
V
0
0.4
V
0
0.2
V
4.5 V ≤ VDD ≤ 6.0 V
0
0.2VDD
V
2.7 V ≤ VDD < 4.5 V
0
0.1VDD
V
2.0 V ≤ VDD < 2.7 VNote
0
0.1VDD
V
VDD = 4.5 to 6.0 V, IOH = –1 mA
VDD – 1.0
VDD
V
IOH = –100 µA
VDD – 0.5
VDD
V
2.0
V
0.4
V
0.2VDD
V
0.5
V
P10 to P17, P30 to P32,
P35 to P37, P80 to P87,
P90 to P97, P100 to P103
VDD = 2.7 to 6.0 V
P00 to P05, P25 to P27,
P33, P34, P70 to P72,
P110 to P117, RESET
VDD = 2.7 to 6.0 V
X1, X2
VDD = 2.7 to 6.0 V
XT1/P07, XT2
P10 to P17, P30 to P32,
P35 to P37, P80 to P87,
P90 to P97, P100 to P103
VDD = 2.7 to 6.0 V
P00 to P05, P25 to P27,
VDD = 2.7 to 6.0 V
MIN.
TYP.
P33, P34, P70 to P72,
P110 to P117, RESET
VIL3
VIL4
Output voltage
high-level
Output voltage
low-level
VOH
VOL1
X1, X2
VDD = 2.7 to 6.0 V
XT1/P07, XT2
P100 to P103
VDD = 4.5 to 6.0 V,
IOL = 15 mA
P01
P25
P70
P90
VDD = 4.5 to 6.0 V,
IOL = 1.6 mA
to
to
to
to
P05,
P27,
P72,
P97,
P10 to P17,
P30 to P37,
P80 to P87,
P110 to P117
VOL2
SB0, SB1, SCK0
VOL3
IOL = 400 µA
0.4
VDD = 4.5 to 6.0 V,
open-drain,
pulled high (R = 1 kΩ)
Note When P07/XT1 pin is used as P07, the inverse phase of P07 should be input to XT2 pin.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
38
µPD78064B
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Input leakage
current
high-level
Symbol
ILIH1
Test Conditions
VIN = VDD
ILIH2
Input leakage
current
low-level
ILIL1
VIN = 0 V
ILIL2
MIN.
TYP.
MAX.
Unit
P00 to P05, P10 to P17,
P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117
3
µA
X1, X2, XT1/P07, XT2
20
µA
P00 to P05, P10 to P17,
P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117
–3
µA
X1, X2, XT1/P07, XT2
–20
µA
Output leakage
current high-level
ILOH
VOUT = VDD
3
µA
Output leakage
current low-level
ILOL
VOUT = 0 V
–3
µA
90
kΩ
500
kΩ
Software
pull-up resistor
Supply currentNote 1
R
IDD1
IDD2
4.5 V ≤ VDD ≤ 6.0 V
VIN = 0 V, P01 to P05,
P10 to P17, P25 to P27,
P30 to P37, P70 to P72,
P80 to P87, P90 to P97,
2.7 V ≤ VDD < 4.5 V
P100 to P103, P110 to P117
15
40
20
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 %Note 4
(fXX = 2.5 MHz)Note 2
operating mode
VDD = 3.0 V ± 10 %Note 5
4
12
mA
0.6
1.8
mA
VDD = 2.2 V ± 10 %Note 5
0.35
1.05
mA
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 %Note 4
(fXX = 5.0 MHz)Note 3
operating mode
VDD = 3.0 V ± 10 %Note 5
6.5
19.5
mA
0.8
2.4
mA
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 %
(fXX = 2.5 MHz)Note 2
HALT mode
VDD = 3.0 V ± 10 %
1.4
4.2
mA
500
1500
µA
VDD = 2.2 V ± 10 %
280
840
µA
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 %
(fXX = 5.0 MHz)Note 3
HALT mode
VDD = 3.0 V ± 10 %
1.6
4.8
mA
650
1950
µA
Notes 1. The current flowing in VDD and AVDD, excluding the current flowing in an A/D converter, on-chip pull-up
resistors and LCD split resistors
2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
3. Main system clock fXX = fX operation (when OSMS is set to 01H)
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
5. Low-speed mode operation (when PCC is set to 04H)
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
39
µPD78064B
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Supply
currentNote 1
Symbol
Test Conditions
IDD3
32.768-kHz crystal oscillation
operating modeNote 2
IDD4
32.768-kHz crystal oscillation
HALT modeNote 2
IDD5
XT1 = VDD
STOP mode
When feedback resistor is connected
XT1 = VDD
STOP mode
When feedback resistor is disconnected
IDD6
MIN.
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
=
=
=
=
=
=
=
=
=
=
=
=
5.0
3.0
2.2
5.0
3.0
2.2
5.0
3.0
2.2
5.0
3.0
2.2
V
V
V
V
V
V
V
V
V
V
V
V
±
±
±
±
±
±
±
±
±
±
±
±
10
10
10
10
10
10
10
10
10
10
10
10
%
%
%
%
%
%
%
%
%
%
%
%
TYP.
MAX.
Unit
60
32
24
25
5
2.5
1
0.5
0.3
0.1
0.05
0.05
120
64
48
55
15
12.5
30
10
10
30
10
10
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Notes 1. The current flowing in VDD and AVDD, excluding the current flowing in an A/D converter, on-chip pull-up
resistors and LCD split resistors
2. When the main system clock is stopped.
40
µPD78064B
DC CHARACTERISTICS (TA = –10 to +85°C)
(1) Static Display Mode (VDD = 2.0 to 6.0 V)
Parameter
Symbol
Test Conditions
LCD drive voltage
VLCD
LCD split resistor
LCD output voltage
deviationNote (common)
LCD output voltage
deviationNote (segment)
RLCD
VODC
IO = ±5 µA
VODS
IO = ±1 µA
2.0 V ≤ VLCD ≤ VDD
VLCD0 = VLCD
MIN.
TYP.
MAX.
Unit
2.0
60
0
100
VDD
150
±0.2
V
kΩ
V
±0.2
V
0
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment
and common outputs (VLCDn; n = 0, 1, 2).
(2) 1/3 Bias Method (VDD = 2.5 to 6.0 V)
Parameter
Symbol
Test Conditions
LCD drive voltage
VLCD
LCD split resistor
LCD output voltage
deviationNote (common)
LCD output voltage
deviationNote (segment)
RLCD
VODC
IO = ±5 µA
VODS
IO = ±1 µA
2.5 V ≤ VLCD ≤ VDD
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
MIN.
TYP.
MAX.
Unit
2.5
60
0
100
VDD
150
±0.2
V
kΩ
V
±0.2
V
0
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment
and common outputs (VLCDn; n = 0, 1, 2).
(3) 1/2 Bias Method (VDD = 2.7 to 6.0 V)
Parameter
Symbol
Test Conditions
LCD drive voltage
LCD split resistor
LCD output voltage
deviationNote (common)
LCD output voltage
deviationNote (segment)
VLCD
RLCD
VODC
IO = ±5 µA
VODS
IO = ±1 µA
2.7 V ≤ VLCD ≤ VDD
VLCD0 = VLCD
VLCD1 = VLCD × 1/2
VLCD2 = VLCD1
MIN.
TYP.
MAX.
Unit
2.7
60
0
100
VDD
150
±0.2
V
kΩ
V
±0.2
V
0
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment
and common outputs (VLCDn; n = 0, 1, 2).
41
µPD78064B
AC CHARACTERISTICS
(1) Basic Operation (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Cycle time
(Minimum
instruction
execution time)
TCY
TI00 input
high-/low-level width
tTIH00,
tTIL00
TI01 input
high-/low-level width
TI1, TI2 input
frequency
TI1, TI2 input
high-/low-level width
Interrupt input
high-/low-level
width
tTIH01,
tTIL01
fTI1
RESET low-level
width
tRSL
tTIH1,
tINTL1
tINTH,
tINTL
Test Conditions
Operating on main system clock
(fXX = 2.5 MHz)Note 1
Operating on main system clock
(fXX = 5.0 MHz)Note 2
Operating on subsystem clock
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
VDD = 2.7 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
INTP0
INTP1 to INTP5,
P110 to P117
VDD = 2.7 to 6.0 V
MIN.
0.8
2.2
4.5 ≤ VDD ≤ 6.0 V
0.4
2.7 ≤ VDD < 4.5 V
0.8
40Note 3
2/fsam + 0.1Note 4
2/fsam + 0.2Note 4
2/fsam + 0.5Note 4
10
20
0
0
100
1.8
8/f samNote 4
VDD = 2.7 to 6.0 V
10
20
10
20
TYP.
MAX.
Unit
122
64
64
32
32
125
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
MHz
kHz
ns
µs
µs
µs
µs
µs
µs
VDD = 2.7 to 6.0 V
4
275
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
2. Main system clock fXX = fX operation (when OSMS is set to 01H)
3. This is the value when the external clock is used. The value is 114 µs (MIN.) when the crystal resonator
is used.
4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam
is possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4).
42
µPD78064B
TCY vs VDD (At main system clock fXX = fX/2 operation)
TCY vs VDD (At main system clock fXX = fX operation)
60
60
Cycle Time TCY [ µ s]
Cycle Time TCY [ µ s]
32
10
Guaranteed Operation
Range
2.0
10
Guaranteed Operation
Range
2.0
1.0
0.8
1.0
0.8
0.4
0.4
0
1
2
3
4
5
Supply Voltage VDD [V]
6
0
1
2
3
4
5
6
Supply Voltage VDD [V]
43
µPD78064B
(2) Serial Interface (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
(a) Serial interface channel 0
(i)
3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY1
tKH1,
Test Conditions
SI0 hold time (from SCK0↑)
SO0 output delay time
from SCK0↓
tSIK1
MAX.
Unit
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
VDD = 4.5 to 6.0 V
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
300
ns
400
ns
tKSI1
tKSO1
TYP.
4.5 V ≤ VDD ≤ 6.0 V
tKL1
SI0 setup time (to SCK0↑)
MIN.
C = 100
pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of SCK0, SO0 output line.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY2
Test Conditions
TYP.
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
tKH2,
4.5 V ≤ VDD ≤ 6.0 V
400
ns
tKL2
2.7 V ≤ VDD < 4.5 V
800
ns
1600
ns
100
ns
SI0 setup time (to SCK0↑)
tSIK2
SI0 hold time (from SCK0↑)
tKSI2
SO0 output delay time
from SCK0↓
tKSO2
SCK0 rise, fall time
tR2,
tF2
400
C = 100 pFNote
Note C is the load capacitance of SO0 output line.
44
MIN.
ns
300
ns
1000
ns
µPD78064B
(iii) SBI mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY3
SCK0 high-/low-level
tKH3,
width
tKL3
SB0, SB1 setup time
tSIK3
Test Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
(to SCK0↑)
SB0, SB1 hold time
tKSI3
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY3/2 – 50
ns
tKCY3/2 – 150
ns
100
ns
300
ns
tKCY3/2
ns
(from SCK0↑)
SB0, SB1 output delay
tKSO3
R = 1 kΩ,
VDD = 4.5 to 6.0 V
C = 100 pFNote
time from SCK0↓
0
250
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
tKCY3
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY3
ns
SB0, SB1 high-level width
tSBH
tKCY3
ns
SB0, SB1 low-level width
tSBL
tKCY3
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
(iv) SBI mode (SCK0... External clock input)
Parameter
SCK0 cycle time
Symbol
tKCY4
SCK0 high-/low-level
tKH4,
width
tKL4
SB0, SB1 setup time
tSIK4
Test Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
(to SCK0↑)
SB0, SB1 hold time
tKSI4
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
tKCY4/2
ns
(from SCK0↑)
SB0, SB1 output delay
tKSO4
R = 1 kΩ,
C = 100 pFNote
time from SCK0↓
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0, SB1 high-level width
tSBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 rise, fall time
tR4,
tF4
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
45
µPD78064B
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
Test Conditions
R = 1 kΩ,
C = 100
SCK0 high-level width
SCK0 low-level width
SB0, SB1 setup time
tKL5
(to SCK0↑)
SB0, SB1 hold time
(from SCK0↑)
tKSI5
SB0, SB1 output delay
time from SCK0↓
tKSO5
MAX.
Unit
1600
ns
3200
ns
VDD = 2.7 to 6.0 V
tKCY5/2 – 160
ns
tKCY5/2 – 190
ns
VDD = 4.5 to 6.0 V
tSIK5
TYP.
VDD = 2.7 to 6.0 V
pFNote
tKH5
MIN.
tKCY5/2 – 50
ns
tKCY5/2 – 100
ns
4.5 V ≤ VDD ≤ 6.0 V
300
ns
2.7 V ≤ VDD < 4.5 V
350
ns
400
ns
600
ns
300
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
(vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-level width
SCK0 low-level width
Symbol
tKCY6
tKH6
tKL6
Test Conditions
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
ns
3200
ns
650
ns
1300
ns
800
ns
1600
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK6
100
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI6
tKCY6/2
ns
SB0, SB1 output delay
tKSO6
time from SCK0↓
SCK0 rise, fall time
R = 1 kΩ,
C = 100
pFNote
VDD = 4.5 to 6.0 V
0
0
tR6,
tF6
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
46
300
ns
500
ns
1000
ns
µPD78064B
(b) Serial interface channel 2
(i)
3-wire serial I/O mode (SCK2... Internal clock output)
Parameter
SCK2 cycle time
SCK2 high-/low-level width
Symbol
tKCY7
tKH7,
Test Conditions
SI2 hold time (from SCK2↑)
SO2 output delay time
tSIK7
MAX.
Unit
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
4.5 V ≤ VDD ≤ 6.0 V
tKCY7/2 – 50
ns
tKCY7/2 – 100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
300
ns
400
ns
tKSI7
tKSO7
TYP.
4.5 V ≤ VDD ≤ 6.0 V
tKL7
SI2 setup time (to SCK2↑)
MIN.
C = 100
pFNote
300
ns
MAX.
Unit
from SCK2↓
Note C is the load capacitance of SCK2, SO2 output line.
(ii) 3-wire serial I/O mode (SCK2... External clock input)
Parameter
SCK2 cycle time
SCK2 high-/low-level width
Symbol
tKCY8
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
400
ns
tKL8
2.7 V ≤ VDD < 4.5 V
SI2 hold time (from SCK2↑)
tKSI8
tKSO8
TYP.
800
4.5 V ≤ VDD ≤ 6.0 V
tSIK8
MIN.
4.5 V ≤ VDD ≤ 6.0 V
tKH8,
SI2 setup time (to SCK2↑)
SO2 output delay time
Test Conditions
C = 100
pFNote
800
ns
1600
ns
100
ns
400
ns
300
ns
1000
ns
from SCK2↓
SCK2 rise, fall time
tR8,
tF8
Note C is the load capacitance of SO2 output line.
47
µPD78064B
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Transfer rate
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
78125
bps
2.7 V ≤ VDD < 4.5 V
39063
bps
19531
bps
MAX.
Unit
(iv) UART mode (External clock input)
Parameter
ASCK cycle time
Symbol
tKCY9
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
ASCK high-/low-level
tKH9,
4.5 V ≤ VDD ≤ 6.0 V
400
ns
width
tKL9
2.7 V ≤ VDD < 4.5 V
800
ns
1600
Transfer rate
ASCK rise, fall time
48
tR9,
tF9
ns
4.5 V ≤ VDD ≤ 6.0 V
39063
bps
2.7 V ≤ VDD < 4.5 V
19531
bps
9766
bps
1000
ns
µPD78064B
AC Timing Test Point (Excluding X1, XT1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test Points
Clock Timing
1/fX
tXL
tXH
VIH3 (MIN.)
VIL3 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH4 (MIN.)
VIL4 (MAX.)
XT1 Input
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI1, TI2
49
µPD78064B
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tRn
tFn
SCK0, SCK2
tSIKm
SI0, SI2
tKSIm
Input Data
tKSOm
SO0, SO2
Output Data
m = 1, 2, 7, 8
n = 2, 8
SBI mode (bus release signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tR4
tF4
SCK0
tKSB
tSBL
tSBH
tSBK
tSIK3, 4
SB0, SB1
tKSO3, 4
SBI mode (command signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tR4
tF4
SCK0
tKSB
tSBK
tSIK3, 4
SB0, SB1
tKSO3, 4
50
tKSI3, 4
tKSI3, 4
µPD78064B
2-wire serial I/O mode:
tKCY5, 6
tKL5, 6
tKH5, 6
tR6
tF6
SCK0
tSIK5, 6
tKSI5, 6
tKSO5, 6
SB0, SB1
UART mode:
tKCY9
tKL9
tKH9
tR9
tF9
ASCK
A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Symbol
Test Conditions
Resolution
MIN.
TYP.
MAX.
Unit
8
8
8
bit
±0.6
%
±1.4
%
200
µs
2.7 V ≤ AVREF ≤ 6.0 V
Total errorNote
Conversion time
tCONV
19.1
Sampling time
tSAMP
12/fXX
Analog input voltage
VIAN
AVSS
AVREF
V
Reference voltage
AVREF
2.0
AVDD
V
AVREF-AVSS resistance
RAIREF
4
µs
14
kΩ
Note Quantization error (±1/2 LSB) is not included. This is expressed in proportion to the full-scale value.
51
µPD78064B
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85°C)
Parameter
Symbol
Data retention
supply voltage
VDDDR
Data retention
IDDDR
supply current
Release signal set time
tSREL
Oscillation
stabilization
wait time
tWAIT
Test Conditions
MIN.
TYP.
MAX.
Unit
6.0
V
10
µA
1.8
VDDDR = 1.8 V
Subsystem clock stopped and
feedback resistor disconnected
0.1
µs
0
Release by RESET
217/fx
ms
Release by interrupt
Note
ms
Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS),
selection of 212/fXX and 214/fXX to 217/fXX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
52
µPD78064B
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP5
RESET Input Timing
tRSL
RESET
53
µPD78064B
11. PACKAGE DRAWINGS
100-PIN PLASTIC QFP (FINE PITCH) (14 × 14 mm)
A
B
75
76
51
50
F
Q
R
S
D
C
detail of lead end
26
25
100
1
G
H
I
M
J
M
P
K
N
L
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
16.0±0.2
B
14.0±0.2
0.630±0.008
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
16.0±0.2
0.630±0.008
F
G
1.0
1.0
0.039
0.039
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0±0.2
0.039 +0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.17 +0.03
–0.07
0.007 +0.001
–0.003
N
0.10
0.004
P
1.45
0.057
Q
0.125±0.075
0.005±0.003
R
S
5°±5°
1.7 MAX.
5°±5°
0.067 MAX.
P100GC-50-7EA-2
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
54
µPD78064B
100-PIN PLASTIC LQFP (FINE PITCH) (14 × 14 mm)
A
B
75
76
51
50
detail of lead end
S
C D
Q
100
1
R
26
25
F
G
H
I
M
J
K
P
M
N
NOTE
Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
L
ITEM
MILLIMETERS
INCHES
A
16.00±0.20
0.630±0.008
B
14.00±0.20
0.551 +0.009
–0.008
C
14.00±0.20
0.551 +0.009
–0.008
D
16.00±0.20
0.630±0.008
F
1.00
0.039
G
1.00
0.039
H
0.22 +0.05
–0.04
0.009±0.002
I
0.08
0.003
J
0.50 (T.P.)
0.020 (T.P.)
K
1.00±0.20
0.039 +0.009
–0.008
L
0.50±0.20
0.020 +0.008
–0.009
M
0.17 +0.03
–0.07
0.007 +0.001
–0.003
N
0.08
0.003
P
1.40±0.05
0.055±0.002
Q
0.10±0.05
0.004±0.002
R
3° +7°
–3°
3° +7°
–3°
S
1.60 MAX.
0.063 MAX.
S100GC-50-8EU
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
55
µPD78064B
100-PIN PLASTIC QFP (14 × 20 mm)
A
B
Q
F
G
H
I M
5°±5°
31
30
S
100
1
detail of lead end
D
51
50
C
80
81
J
M
P
K
N
L
P100GF-65-3BA1-2
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ±0.4
0.929 ±0.016
B
20.0 ±0.2
0.795 +0.009
–0.008
C
14.0 ±0.2
0.551+0.009
–0.008
D
17.6 ±0.4
0.693 ±0.016
F
0.8
0.031
G
0.6
0.024
H
0.30 ±0.10
0.012+0.004
–0.005
I
0.15
0.006
J
0.65 (T.P.)
0.026 (T.P.)
K
1.8 ±0.2
0.071+0.008
–0.009
L
0.8 ±0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1 ±0.1
0.004 ±0.004
S
3.0 MAX.
0.119 MAX.
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
56
µPD78064B
12. RECOMMENDED SOLDERING CONDITIONS
The µPD78064B should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
(1) µPD78064BGC-×××-7EA : 100-pin plastic QFP (fine pitch) (14 × 14 mm)
µPD78064BGC-×××-8EU : 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125°C)
IR35-107-2
VPS
Package peak temperature: 215°C, Duration: 40 sec. (at 200°C or above),
Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125°C)
VP15-107-2
Partial heating
Pin temperature: 300°C max. Duration: 3 sec. max. (per device side)
—
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH.
(2) µPD78064BGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above),
Number of times: 3 times max.
IR35-00-3
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above),
Number of times: 3 times max.
VP15-00-3
Wave soldering
Solder bath temperature: 260 °C max., Duration: 10 sec. max., Number of times: Once,
Preliminary heat temperature: 120 °C max. (Package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300 °C max. Duration: 3 sec. max. (per device side)
—
Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
57
µPD78064B
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78064B.
Language Processing Software
RA78K/0Notes 1, 2, 3, 4
78K/0 Series common assembler package
CC78K/0Notes 1, 2, 3, 4
78K/0 Series common C compiler package
DF78064Notes 1, 2, 3, 4
µPD78064 Subseries common device file
CC78K/0-LNotes 1, 2, 3, 4
78K/0 Series common C compiler library source file
PROM Writing Tools
PG-1500
PROM programmer
PA-78P0308GC, PA-78P064GC Programmer adapters connected to PG-1500
PA-78P0308GF, PA-78P064GF
PG-1500 controllerNotes 1, 2
PG-1500 control program
Debugging Tools
IE-78000-R
78K/0 Series common in-circuit emulator
IE-78000-R-A
78K/0 Series common in-circuit emulator (for integrated debugger)
IE-78000-R-BK
78K/0 Series common break board
IE-780308-R-EM
µPD780308 Subseries common emulation board
EP-78064GC-R
µPD78064 Subseries common emulation probes
EP-78064GF-R
TGC-100SDW
Adapter to be mounted on a target system board made for 100-pin plastic QFP (GC7EA and GC-8EU types).
This product is manufactured by TOKYO ELETECH Corporation. Consult your local
NEC sales representative when purchasing it.
EV-9200GF-100
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
SM78K0Notes 5, 6, 7
78K/0 Series common system simulator
ID78K0Notes 4, 5, 6, 7
IE-78000-R-A integrated debugger
SD78K/0Notes 1, 2
IE-78000-R screen debugger
DF78064Notes 1, 2, 4, 5, 6, 7
µPD78064 Subseries common device file
Real-time OS
RX78K/0Notes 1, 2, 3, 4
78K/0 Series real-time OS
MX78K0Notes 1, 2, 3, 4
78K/0 Series OS
58
µPD78064B
Fuzzy Inference Development Support System
FE9000Note 1, FE9200Note 6
Fuzzy knowledge data creation tool
FT9080Note 1,
Translator
FT9085Note 2
FI78K0Notes 1, 2
Fuzzy inference module
FD78K0Notes 1, 2
Fuzzy inference debugger
Notes 1. PC-9800 Series (MS-DOSTM) based
2. IBM PC/ATTM and compatibles (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 Series 300TM (HP-UXTM) based
4. HP9000 Series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 Series (EWSUX/V) based
5. PC-9800 Series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
Remarks 1.
2.
For third party development tools, see the 78K/0 Series Selection Guide (IF-1185).
RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78064.
59
µPD78064B
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document No.
µPD78064B Subseries User’s Manual
µPD78064B Data Sheet
English
Japanese
U10785E
U10785J
This manual
U11590J
µPD78064B(A) Data Sheet
U11597E
U11597J
78K/0 Series User’s Manual Instructions
U12326E
U12326J
78K/0 Series Instruction Table
—
U10903J
78K/0 Series Instruction Set
—
U10904J
µPD78064B Subseries Special Function Register Table
—
To be prepared
Development Tool Related Documents (User’s Manual)
Document Name
RA78K Series Assembler Package
Document No.
English
Japanese
Operation
EEU-1399
EEU-809
Language
EEU-1404
EEU-815
EEU-1402
EEU-817
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
CC78K Series C Compiler
CC78K0 C Compiler
Operation
U11802E
U11802J
Assembly Language
U11801E
U11801J
Structured Assembly Language
U11789E
U11789J
Operation
EEU-1280
EEU-656
Language
EEU-1284
EEU-655
Operation
U11517E
U11517J
Language
U11518E
U11518J
Programming know-how
EEA-1208
EEA-618
—
U12322J
PG-1500 PROM Programmer
EEU-1335
U11940J
PG-1500 Controller PC-9800 Series (MS-DOS) based
EEU-1291
EEU-704
PG-1500 Controller IBM PC Series (PC DOS) based
U10540E
EEU-5008
IE-78000-R
U11376E
EEU-810
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
IE-78000-R-A
U10057E
U10057J
IE-78000-R-BK
EEU-1427
EEU-867
IE-780308-R-EM
U11362E
U11362J
EP-78064
SM78K0 System Simulator Windows based
SM78K Series System Simulator
EEU-1469
EEU-934
Reference
U10181E
EEU-5002
External Parts User
U10092E
U10092J
—
U11151J
Open Interface Specifications
ID78K0 Integrated Debugger EWS based
Reference
ID78K0 Integrated Debugger PC based
Reference
U11539E
U11539J
ID78K0 Integrated Debugger Windows based
Guides
U11649E
U11649J
SD78K/0 Screen Debugger
Introduction
U10539E
EEU-852
PC-9800 Series (MS-DOS) based
Reference
—
U10952J
SD78K/0 Screen Debugger
Introduction
EEU-1414
EEU-5024
IBM PC/AT (PC DOS) based
Reference
U11279E
U11279J
Caution The above related documents are subject to change without prior notice. Be sure to use the latest
version when starting design.
60
µPD78064B
Embedded Software Related Documents (User’s Manual)
Document Name
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Document No.
English
Japanese
Basics
—
EEU-912
Installation
—
EEU-911
Basics
—
U12257J
EEU-1438
EEU-829
Fuzzy Knowledge Data Creation Tool
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator
EEU-1444
EEU-862
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module
EEU-1441
EEU-858
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger
EEU-1458
EEU-921
Other Related Documents
Document Name
Document No.
English
IC Package Manual
Japanese
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
Reliable Quality Maintenance on NEC Semiconductor Devices
C10983E
C10983J
—
MEM-539
Electrostatic Discharge (ESD) Test
Semiconductor Devices Quality Guarantee Guide
Microcomputer Product Series Guide
MEI-1202
C11893J
—
U11416J
Caution The above related documents are subject to change without prior notice. Be sure to use the latest
version when starting design.
61
µPD78064B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.
62
µPD78064B
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and components,
host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from
country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
63
µPD78064B
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property
arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in
its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard”, “Special”, and “Specific”. The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program” for a specific application. The recommended applications of a
device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for
life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems or medical equipment for life support, etc.
The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they
should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
64
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