datasheet for W13VA2G4S by Super Talent Technology Corporation

datasheet for W13VA2G4S by Super Talent Technology Corporation
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
DDR3 VLP-Registered/ECC DIMM Module
2GB based on 1Gbit component
FBGA with Pb-Free
Revision 1.0 (May. 2008)
-Initial Release
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Products and Specifications discussed herein are subject to change without notice
1
© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
1.0 Feature
•
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•
•
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•
JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
8 independent internal bank
Programmable CAS latencies (5,6,7,8,9,10,11)
400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for
1600Mb/sec/pin
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) and 8(DDR3-1600)
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow
seamless read or write [either On the fly using A12 or MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On-Die termination using ODT pin
8-bit pre-fetch
Asynchronous Reset
Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
Serial presence detect with EEPROM
VLP-RDIMM Dimension (Nominal) 18.75 mm high, 133.35 mm wide
Based on JEDEC standard reference Raw Cards Lay out.
RoHS compliant
Gold plated contacts
2.0 Ordering Information
Part number
Density
Module
Organization
Component
composition
Component
PKG
Module
Rank
Description
W13VA2G4x
2GB
256Mx72
256Mx4*18
FBGA
1
PC3-10600
Note: Last Character x of the Part Number stand for DRAM vendor
S=Samsung; M=Micron; H=Hynix
3.0 Operating Frequencies
DDR3-1333
Unit
CL-tRCD-tRP
9-9-9
tCK
CAS Latency
tCK(min)
9
1.5
tCK
ns
tRCD(min)
13.5
ns
tRP(min)
13.5
ns
tRAS(min)
36
ns
tRC(min)
49.5
ns
4.0 Absolute Maximum DC Rating
Symbol
Parameter
Rating
Units
Vin , Vout
Voltage on any pin relative to VSS
-0.4 ~ 1.975
V
VDD
Voltage on VDD & VDDQ supply relative to Vss
-0.4 ~ 1.975
V
VDDQ
Short circuit current
-0.4 ~ 1.975
V
VDDL
Power dissipation
-0.4 ~ 1.975
V
TSTG
Storage Temperature
-55 ~ + 100
°C
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Products and Specifications discussed herein are subject to change without notice
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© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
5.0 DIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREFDQ
121
VSS
31
DQ25
151
VSS
61
A2
181
A1
91
DQ41
211
VSS
2
VSS
122
DQ4
32
VSS
152
DQS12
62
VDD
182
VDD
92
VSS
212
DQS14,NC
3
DQ0
123
DQ5
33
DQS3
153
DQS12
63
NC,CK1
183
VDD
93
DQS5
213
DQS14,NC
4
DQ1
124
VSS
34
DQS3
154
VSS
64
NC,CK1
184
CK0
94
DQS5
214
VSS
5
VSS
125
DQS9
35
VSS
155
DQ30
95
VSS
215
DQ46
6
DQS0
126
DQS9
36
DQ26
156
DQ31
65
VDD
185
CK0
DQ47
DQ42
216
DQ47
7
DQS0
127
VSS
37
DQ27
157
VSS
66
VDD
186
VDD
97
DQ43
217
VSS
8
VSS
128
DQ6
38
VSS
158
CB4,NC
67
VREFCA
187
EVENT,NC
98
VSS
218
DQ52
9
DQ2
129
DQ7
39
CB0,NC
159
CB5,NC
68
NC/Par_in
188
A0
99
DQ48
219
DQ53
10
DQ3
130
VSS
40
CB1,NC
160
VSS
69
VDD
189
VDD
100
DQ49
220
VSS
11
VSS
131
DQ12
41
VSS
161
DQS17,NC
70
A10/AP
190
BA1
101
VSS
221
DQS15,NC
12
DQ8
132
DQ13
42
DQS8
162
DQS17,NC
71
BA0
191
VDD
102
DQS6
222
DQS15,NC
13
DQ9
133
VSS
43
DQS8
163
VSS
72
VDD
192
RAS
103
DQS6
223
VSS
14
VSS
134
DQS10
44
VSS
164
CB6,NC
73
WE
193
S0
104
VSS
224
DQ54
15
DQS1
135
DQS10
45
CB2,NC
165
CB7,NC
74
CAS
194
VDD
105
DQ50
225
DQ55
16
DQS1
136
VSS
46
CB3,NC
166
VSS
75
VDD
195
ODT0
106
DQ51
226
VSS
17
VSS
137
DQ14
47
VSS
167
NC
76
NC
196
A13
107
VSS
227
DQ60
18
DQ10
138
DQ15
48
VTT,NC
168
RESET
77
NC
197
VDD
108
DQ56
228
DQ61
19
DQ11
139
VSS
49
VTT,NC
169
CKE1,NC
78
VDD
198
NC
109
DQ57
229
VSS
20
VSS
140
DQ20
50
CKE0
170
VDD
79
NC
199
VSS
110
VSS
230
DQS16,NC
21
DQ16
141
DQ21
51
VDD
171
A15
80
VSS
200
DQ36
111
DQS7
231
DQS16,NC
22
DQ17
142
VSS
52
BA2
172
A14
81
DQ32
201
DQ37
112
DQS7
232
VSS
23
VSS
143
DQS11
53
ERR_OUT
173
VDD
82
DQ33
202
VSS
113
VSS
233
DQ62
24
DQS2
144
DQS11
54
VDD
174
A12
83
VSS
203
DQS13,NC
114
DQ58
234
DQ63
25
DQS2
145
VSS
55
A11
175
A9
84
DQS4
204
DQS13,NC
115
DQ59
235
VSS
26
VSS
146
DQ22
56
A7
176
VDD
85
DQS4
205
VSS
116
VSS
236
VDDSPD
27
DQ18
147
DQ23
57
VDD
177
A8
86
VSS
206
DQ38
117
SA0
237
SA1
28
DQ19
148
VSS
58
A5
178
A6
87
DQ34
207
DQ39
118
SCL
238
SDA
29
VSS
149
DQ28
59
A4
179
VDD
88
DQ35
208
VSS
119
SA2
239
VSS
30
DQ24
150
DQ29
60
VDD
180
A3
89
VSS
209
DQ44
120
VTT
240
VTT
90
DQ40
210
DQ45
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KEY
Products and Specifications discussed herein are subject to change without notice
3
© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
6.0 DIMM Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A15
Address input (Multiplexed)
ODT0~ODT1
On Die Termination
A10/AP
Address Input/Auto pre-charge
CB0~CB7
ECC Data check bits Input/Output
BA0 ~ BA2
Bank Select
DQ0~DQ63
Data Input/Output
CK0 ~ CK2,
CK0~CK2
Clock input
DQS0~DQS8
Data strobes, negative line
CKE0, CKE1
Clock enable input
DM (0~8),
Data Masks/Data strobes (Read)
S0, S1
Chip select input
DQS0~DQS8
Data Strobes
RAS
Row address strobe
RFU
Reserved for future used
CAS
Column address strobe
VTT
SDRAM I/O termination power supply
WE
Write Enable
TEST
Memory bus test tool
SCL
SPD Clock Input
VDD
Core Power
SDA
SPD Data Input/Output
VDDQ
I/O Power
SA0~SA2
SPD Address
VSS
Ground
Par_In
Parity bit for address & Control bus
VREFDQ
SDRAM Input/Output Reference Supply
event
VDDSPD
Serial EEPROM Power Supply
Register and PLL control pin
VREFCA
Command Address Reference Supply
EVENT
Reset
EVENT pin on TS/SPD part, Temperature
7.0 Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Pre-charge
256Mx4(1Gb)base
A0-A13
A0-A9, A11
BA0-BA2
A10
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Products and Specifications discussed herein are subject to change without notice
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© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
8.0 Functional Block Diagram: 2GB, 256x72 Module (Populated as 1 rank of x4 SDRAM Module)
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Products and Specifications discussed herein are subject to change without notice
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© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
9.0
DDR3 SDRAM
AC & DC Operating Conditions
Recommended operating conditions (Voltage referenced to Vss=0V, TA=0 to 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
VDD
VDDQ
VREFDQ(DC)
VREFCA(DC)
VTT
Supply Voltage
Supply Voltage for Output
I/O Reference Voltage (DQ)
I/O Reference Voltage (CMD/Add)
Termination Voltage
1.425
1.425
0.49*VDDQ
0.49*VDDQ
0.49*VDDQ
1.5
1.5
0.50*VDDQ
0.50*VDDQ
0.50*VDDQ
1.575
1.575
0.51*VDDQ
0.51*VDDQ
0.51*VDDQ
V
V
V
V
V
10.0 Capacitance (Max.)
Symbol
Parameter/Condition
Min
-
Input capacitance, CK and CK
CCK
CI1
-
Input capacitance, CKE and CS
-
Input capacitance, Addr, RAS, CAS, WE
CI2
CIO
-
Input capacitance, DQ, DM, DQS, DQS
Max
Unit
11
pF
12
pF
12
pF
10
pF
11.1 AC Timing Parameters & Specifications
(AC operating conditions unless otherwise noted)
Parameter
DDR3-1333
Symbol
Minimum Clock Cycle Time (DLL off mode)
tCK(DLL_OFF)
Average Clock Period
tCK(avg)
min
Units
max
8
-
tCK(avg) min +tJIT
ns
ps
(per)min
tCK(avg) max +tJIT
(per)max
ps
Clock Period
tCK(abs)
Average high pulse width
tCH(avg)
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
tCK(avg)
Clock Period Jitter
tJIT(per)
-80
80
ps
Clock Period Jitter during DLL locking period
tJIT(per, lck)
-80
80
ps
Cycle to Cycle Period Jitter
tJIT(cc)
160
-
ps
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc, lck)
140
-
ps
Cumulative error across 2 cycles
tERR(2per)
- 118
118
ps
Cumulative error across 3 cycles
tERR(3per)
- 140
140
ps
Cumulative error across 4 cycles
tERR(4per)
- 155
155
ps
Cumulative error across 5 cycles
tERR(5per)
- 168
168
ps
Cumulative error across 6 cycles
tERR(6per)
- 177
177
ps
Cumulative error across 7 cycles
tERR(7per)
- 186
186
ps
Cumulative error across 8 cycles
tERR(8per)
- 193
193
ps
Cumulative error across 9 cycles
tERR(9per)
- 200
200
ps
Cumulative error across 10 cycles
tERR(10per)
- 205
205
ps
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© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
11.2 AC Timing Parameters & Specifications (con’t)
Parameter
Symbol
Cumulative error across 11 cycles
tERR(11per)
Cumulative error across 12 cycles
tERR(12per)
DDR3-1333
min
Units
max
- 210
210
ps
- 215
215
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
tCK(avg)
Absolute clock Low pulse width
tCL(abs)
0.43
-
tCK(avg)
tDQSQ
-
125
ps
ps
Data Timing
DQS, /DQS to DQ skew, per group, per access
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK(avg)
DQ low-impedance time from CK, /CK
tLZ(DQ)
-500
250
ps
DQ high-impedance time from CK, /CK
tHZ(DQ)
-
250
ps
Data setup time to DQS, /DQS referenced to Vih(ac)Vil(ac) levels
tDS(base)
TBD
-
ps
Data hold time to DQS, /DQS referenced to Vih(ac)Vil(ac) levels
tDH(base)
TBD
-
ps
DQ and DM Input pulse width for each input
tDIPW
400
-
ps
DQS, /DQS READ Preamble
tRPRE
0.9
-
tCK
DQS, /DQS differential READ Postamble
tRPST
0.3
-
tCK
DQS, /DQS output high time
tQSH
0.4
-
tCK(avg)
Data Strobe Timing
DQS, /DQS output low time
tQSL
0.4
-
tCK(avg)
DQS, /DQS WRITE Preamble
tWPRE
0.9
-
tCK
DQS, /DQS WRITE Postamble
tWPST
0.3
-
tCK
DQS, /DQS rising edge output access time from rising CK, /CK
tDQSCK
-255
255
ps
DQS, /DQS low-impedance time (Referenced from RL-1)
tLZ(DQS)
-500
250
ps
DQS, /DQS high-impedance time (Referenced from RL+BL/2)
tHZ(DQS)
250
-
ps
DQS, DQS differential input low pulse width
tDQSL
0.45
0.55
tCK
DQS, DQS differential input high pulse width
tDQSH
0.45
0.55
tCK
DQS, DQS rising edge to CK, CK rising edge
tDQSS
-0.25
0.25
tCK(avg)
DQS,DQS faling edge setup time to CK, CK rising edge
tDSS
0.2
-
tCK(avg)
DQS,DQS faling edge hold time to CK, CK rising edge
tDSH
0.2
-
tCK(avg)
DLL locking time
tDLLK
512
-
nCK
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
internal READ Command to PRECHARGE Command delay
tRTP
Delay from start of internal write transaction to internal read
command
tWTR
WRITE recovery time
tWR
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
nCK
Mode Register Set command update delay
tMOD
max
(12tCK,15ns)
-
CAS# to CAS# command delay
tCCD
4
-
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
nCK
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Products and Specifications discussed herein are subject to change without notice
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© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
11.3 AC Timing Parameters & Specifications (con’t)
Parameter
Symbol
Multi-Purpose Register Recovery Time
tMPRR
ACTIVE to PRECHARGE command period
tRAS
DDR3-1333
min
Units
max
1
-
nCK
36
70,000
ns
max
(4tCK,6ns)
max
(4tCK,7.5ns)
ACTIVE to ACTIVE command period for 1KB page size
tRRD
ACTIVE to ACTIVE command period for 2KB page size
tRRD
Four activate window for 1KB page size
tFAW
30
-
ns
Four activate window for 2KB page size
tFAW
45
-
ns
tIS(base)
65
-
ps
tIH(base)
140
-
ps
tIS(base)
AC150
65+125
-
ps
tIPW
620
-
ps
Power-up and RESET calibration time
tZQinitI
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
tCK
Normal operation short calibration time
tZQCS
64
-
tCK
tXPR
max(5tCK, tRFC+ 10ns)
-
Exit Self Refresh to commands not requiring a locked DLL
tXS
max(5tCK,tRFC+ 10ns)
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tDLLK(min)
-
Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac)
levels
Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac)
levels
Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac)
levels
Control & Address Input pulse width for each input
-
Calibration Timing
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
Minimum CKE low width for Self refresh entry to exit timing
tCKESR
Valid Clock Requirement after Self Refresh Entry (SRE)
tCKSRE
Valid Clock Requirement before Self Refresh Exit (SRX)
tCKSRX
tCKE(min) +
1tCK
max(5tCK,
10ns)
max(5tCK,
10ns)
nCK
-
Power Down Timing
Exit Power Down with DLL on to any valid command; Exit Precharge Power
Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands requiring a locked
DLL
tXP
tXPDLL
CKE minimum pulse width
tCKE
Command pass disable delay
tCPDED
max
(3tCK,6ns)
-
max(10tCK, 24ns)
-
max(3tCK, 5.625ns)
-
1
-
nCK
Power Down Entry to Exit Timing
tPD
tCKE(min)
9*tREFI
tCK
Timing of ACT command to Power Down entry
tACTPDEN
1
-
nCK
Timing of PRE command to Power Down entry
tPRPDEN
1
-
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
RL + 4 +1
-
Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BL4OTF)
tWRPDEN
WL + 4 +(tWR/tCK)
-
nCK
Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF)
tWRAPDEN
WL + 4 +WR+1
-
nCK
tWRPDEN
WL + 2 +(tWR/
tCK(avg))
-
nCK
Timing of WR command to Power Down entry (BL4MRS)
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Products and Specifications discussed herein are subject to change without notice
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© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
11.4 AC Timing Parameters & Specifications (con’t)
DDR3-1333
Parameter
Symbol
Timing of WRA command to Power Down entry
(BL4MRS)
tWRAPDEN
WL +2 +WR +1
-
Timing of REF command to Power Down entry
tREFPDEN
1
-
Timing of MRS command to Power Down entry
tMRSPDEN
tMOD(min)
-
min
Units
max
nCK
ODT Timing
ODT high time without write command or with wirte commandand BC4
ODTH4
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
nCK
Asynchronous RTT tum-on delay (Power-Down with DLL frozen)
tAONPD
1
9
ns
Asynchronous RTT tum-off delay (Power-Down with DLL frozen)
tAOFPD
1
9
ns
ODT turn-on
tAON
-250
250
ps
RTT_NOM and RTT_WR turn-off time from ODTL off reference
tAOF
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
tCK(avg)
First DQS pulse rising edge after tDQSS margining mode is programmed
tWLMRD
40
-
tCK
DQS/DQS delay after tDQS margining mode is programmed
tWLDQSEN
25
-
tCK
Setup time for tDQSS latch
tWLS
195
-
ps
Hold time of tDQSS latch
tWLH
195
-
ps
Write leveling output delay
tWLO
0
9
ns
Write leveling output error
tWLOE
0
2
ns
Write Leveling Timing
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Products and Specifications discussed herein are subject to change without notice
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© 2006 Super Talent Tech., Corporation.
240-Pin DDR3-VLP-Reg/ECC-DIMM
DDR3 SDRAM
12.0 Physical Dimensions: (256Mbx4 Based)
256Mx72 (1 Ranks)
Tolerances: ± 0.005(.13) unless otherwise specified
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Products and Specifications discussed herein are subject to change without notice
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