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Arria 10 Core Fabric and General Purpose
I/Os Handbook
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A10-HANDBOOK
2015.12.16
101 Innovation Drive
San Jose, CA 95134
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TOC-2
Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices
Contents
Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices...............1-1
LAB ............................................................................................................................................................... 1-1
MLAB ................................................................................................................................................1-2
Local and Direct Link Interconnects ............................................................................................1-3
Shared Arithmetic Chain and Carry Chain Interconnects ....................................................... 1-4
LAB Control Signals........................................................................................................................ 1-5
ALM Resources ............................................................................................................................... 1-6
ALM Output .................................................................................................................................... 1-7
ALM Operating Modes .............................................................................................................................. 1-8
Normal Mode .................................................................................................................................. 1-8
Extended LUT Mode .................................................................................................................... 1-11
Arithmetic Mode ...........................................................................................................................1-12
Shared Arithmetic Mode ............................................................................................................. 1-13
LAB Power Management Techniques ................................................................................................... 1-15
Document Revision History.....................................................................................................................1-15
Embedded Memory Blocks in Arria 10 Devices................................................. 2-1
Types of Embedded Memory..................................................................................................................... 2-1
Embedded Memory Capacity in Arria 10 Devices...................................................................... 2-2
Embedded Memory Design Guidelines for Arria 10 Devices............................................................... 2-2
Consider the Memory Block Selection..........................................................................................2-2
Guideline: Implement External Conflict Resolution.................................................................. 2-3
Guideline: Customize Read-During-Write Behavior................................................................. 2-3
Guideline: Consider Power-Up State and Memory Initialization............................................ 2-6
Guideline: Control Clocking to Reduce Power Consumption.................................................. 2-7
Embedded Memory Features..................................................................................................................... 2-7
Embedded Memory Modes........................................................................................................................ 2-9
Embedded Memory Configurations for Single-port Mode..................................................... 2-10
Embedded Memory Configurations for Dual-port Modes......................................................2-11
Embedded Memory Clocking Modes..................................................................................................... 2-12
Clocking Modes for Each Memory Mode.................................................................................. 2-12
Asynchronous Clears in Clocking Modes.................................................................................. 2-13
Output Read Data in Simultaneous Read/Write....................................................................... 2-13
Independent Clock Enables in Clocking Modes....................................................................... 2-13
Parity Bit in Embedded Memory Blocks................................................................................................ 2-14
Byte Enable in Embedded Memory Blocks............................................................................................ 2-14
Byte Enable Controls in Memory Blocks....................................................................................2-14
Data Byte Output........................................................................................................................... 2-15
RAM Blocks Operations............................................................................................................... 2-15
Memory Blocks Packed Mode Support.................................................................................................. 2-15
Memory Blocks Address Clock Enable Support....................................................................................2-16
Memory Blocks Asynchronous Clear..................................................................................................... 2-17
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Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices
TOC-3
Memory Blocks Error Correction Code Support.................................................................................. 2-18
Error Correction Code Truth Table............................................................................................2-19
Document Revision History.....................................................................................................................2-20
Variable Precision DSP Blocks in Arria 10 Devices........................................... 3-1
Supported Operational Modes in Arria 10 Devices................................................................................ 3-2
Features..............................................................................................................................................3-5
Resources.......................................................................................................................................................3-6
Design Considerations................................................................................................................................ 3-7
Operational Modes.......................................................................................................................... 3-8
Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic.............................................. 3-9
Accumulator for Fixed-Point Arithmetic.....................................................................................3-9
Chainout Adder............................................................................................................................. 3-10
Block Architecture..................................................................................................................................... 3-10
Input Register Bank....................................................................................................................... 3-13
Pipeline Register.............................................................................................................................3-15
Pre-Adder for Fixed-Point Arithmetic....................................................................................... 3-16
Internal Coefficient for Fixed-Point Arithmetic....................................................................... 3-16
Multipliers.......................................................................................................................................3-16
Adder............................................................................................................................................... 3-16
Accumulator and Chainout Adder for Fixed-Point Arithmetic............................................. 3-17
Systolic Registers for Fixed-Point Arithmetic............................................................................3-18
Double Accumulation Register for Fixed-Point Arithmetic................................................... 3-18
Output Register Bank.................................................................................................................... 3-18
Operational Mode Descriptions.............................................................................................................. 3-18
Operational Modes for Fixed-Point Arithmetic........................................................................3-19
Operational Modes for Floating-Point Arithmetic................................................................... 3-27
Document Revision History.....................................................................................................................3-34
Clock Networks and PLLs in Arria 10 Devices................................................... 4-1
Clock Networks............................................................................................................................................ 4-1
Clock Resources in Arria 10 Devices.............................................................................................4-2
Hierarchical Clock Networks......................................................................................................... 4-5
Types of Clock Networks................................................................................................................ 4-7
Clock Network Sources.................................................................................................................4-11
Clock Control Block...................................................................................................................... 4-12
Clock Power Down........................................................................................................................ 4-15
Clock Enable Signals......................................................................................................................4-15
Arria 10 PLLs..............................................................................................................................................4-16
PLL Usage....................................................................................................................................... 4-18
PLL Architecture............................................................................................................................4-18
PLL Cascading................................................................................................................................ 4-19
PLL Control Signals.......................................................................................................................4-19
Clock Feedback Modes..................................................................................................................4-20
Clock Multiplication and Division.............................................................................................. 4-21
Programmable Phase Shift............................................................................................................4-22
Programmable Duty Cycle........................................................................................................... 4-22
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TOC-4
Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices
Clock Switchover........................................................................................................................... 4-22
PLL Reconfiguration and Dynamic Phase Shift........................................................................ 4-27
Document Revision History.....................................................................................................................4-28
I/O and High Speed I/O in Arria 10 Devices...................................................... 5-1
I/O and Differential I/O Buffers in Arria 10 Devices..............................................................................5-2
I/O Standards and Voltage Levels in Arria 10 Devices...........................................................................5-2
I/O Standards Support for FPGA I/O in Arria 10 Devices........................................................ 5-2
I/O Standards Support for HPS I/O in Arria 10 Devices........................................................... 5-4
I/O Standards Voltage Levels in Arria 10 Devices...................................................................... 5-5
MultiVolt I/O Interface in Arria 10 Devices................................................................................ 5-6
Altera I/O IPs for Arria 10 Devices........................................................................................................... 5-6
I/O Resources in Arria 10 Devices.............................................................................................................5-7
GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices.............................................. 5-7
GPIO Buffers and LVDS Channels in Arria 10 Devices...........................................................5-12
I/O Banks Groups in Arria 10 Devices....................................................................................... 5-15
I/O Vertical Migration for Arria 10 Devices..............................................................................5-24
Architecture and General Features of I/Os in Arria 10 Devices......................................................... 5-25
I/O Element Structure in Arria 10 Devices................................................................................ 5-25
Features of I/O Pins in Arria 10 Devices.................................................................................... 5-27
Programmable IOE Features in Arria 10 Devices..................................................................... 5-28
On-Chip I/O Termination in Arria 10 Devices.........................................................................5-34
External I/O Termination for Arria 10 Devices........................................................................ 5-43
High Speed Source-Synchronous SERDES and DPA in Arria 10 Devices........................................ 5-52
SERDES Circuitry.......................................................................................................................... 5-53
SERDES I/O Standards Support in Arria 10 Devices............................................................... 5-54
Differential Transmitter in Arria 10 Devices............................................................................. 5-56
Differential Receiver in Arria 10 Devices................................................................................... 5-57
PLLs and Clocking for Arria 10 Devices.....................................................................................5-66
Timing and Optimization for Arria 10 Devices........................................................................ 5-77
Using the I/Os and High Speed I/Os in Arria 10 Devices....................................................................5-82
I/O and High-Speed I/O General Guidelines for Arria 10 Devices........................................ 5-82
Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards........................... 5-84
Guideline: Do Not Drive I/O Pins During Power Sequencing................................................5-85
Guideline: Maximum DC Current Restrictions........................................................................ 5-85
Guideline: Altera LVDS SERDES IP Core Instantiation..........................................................5-85
Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode....................................................... 5-85
Guideline: Minimizing High Jitter Impact on Arria 10 GPIO Performance........................ 5-86
Document Revision History.....................................................................................................................5-87
External Memory Interfaces in Arria 10 Devices............................................... 6-1
Key Features of the Arria 10 External Memory Interface Solution...................................................... 6-1
Memory Standards Supported by Arria 10 Devices................................................................................6-2
External Memory Interface Widths in Arria 10 Devices........................................................................6-3
External Memory Interface I/O Pins in Arria 10 Devices...................................................................... 6-4
Memory Interfaces Support in Arria 10 Device Packages......................................................................6-5
Arria 10 Package Support for DDR3 x40 with ECC................................................................... 6-6
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Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices
TOC-5
Arria 10 Package Support for DDR3 x40 with ECC for HPS.................................................... 6-7
Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank............................6-8
Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank for HPS...........6-10
Arria 10 Package Support for DDR4 x40 with ECC................................................................. 6-11
Arria 10 Package Support for DDR4 x40 with ECC for HPS.................................................. 6-12
Arria 10 Package Support for DDR4 x72 with ECC Single-Rank...........................................6-13
Arria 10 Package Support for DDR4 x72 with ECC Dual-Rank............................................. 6-14
Arria 10 Package Support for DDR4 x72 with ECC Single-Rank for HPS............................6-15
External Memory Interface IP Support in Arria 10 Devices................................................................6-15
Ping Pong PHY IP......................................................................................................................... 6-16
External Memory Interface Architecture of Arria 10 Devices.............................................................6-17
I/O Bank.......................................................................................................................................... 6-18
I/O AUX.......................................................................................................................................... 6-29
Document Revision History.....................................................................................................................6-31
Configuration, Design Security, and Remote System Upgrades in Arria 10
Devices............................................................................................................. 7-1
Enhanced Configuration and Configuration via Protocol.....................................................................7-1
Configuration Schemes............................................................................................................................... 7-2
Active Serial Configuration............................................................................................................ 7-3
Passive Serial Configuration.........................................................................................................7-13
Fast Passive Parallel Configuration............................................................................................. 7-18
JTAG Configuration......................................................................................................................7-22
Configuration Details................................................................................................................................7-25
MSEL Pin Settings..........................................................................................................................7-25
CLKUSR.......................................................................................................................................... 7-26
Configuration Sequence................................................................................................................7-27
Configuration Timing Waveforms..............................................................................................7-29
Device Configuration Pins............................................................................................................7-33
Configuration Pin Options in the Quartus Prime Software.................................................... 7-35
Configuration Data Compression............................................................................................... 7-36
Remote System Upgrades Using Active Serial Mode........................................................................... 7-37
Configuration Images....................................................................................................................7-38
Configuration Sequence in the Remote Update Mode.............................................................7-39
Remote System Upgrade Circuitry..............................................................................................7-39
Enabling Remote System Upgrade Circuitry............................................................................. 7-40
Remote System Upgrade Registers.............................................................................................. 7-40
Remote System Upgrade State Machine.....................................................................................7-42
User Watchdog Timer...................................................................................................................7-42
Design Security...........................................................................................................................................7-43
JTAG Secure Mode........................................................................................................................ 7-44
Secure Mode................................................................................................................................... 7-44
Security Key Types.........................................................................................................................7-44
Security Modes............................................................................................................................... 7-45
Design Security Implementation Steps.......................................................................................7-45
Document Revision History.....................................................................................................................7-46
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TOC-6
Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices
SEU Mitigation for Arria 10 Devices.................................................................. 8-1
SEU Mitigation Overview........................................................................................................................... 8-1
SEU Mitigation Applications......................................................................................................... 8-1
Configuration RAM.........................................................................................................................8-1
Embedded Memory......................................................................................................................... 8-2
Arria 10 Mitigation Techniques.................................................................................................................8-2
Memory Blocks Error Correction Code Support........................................................................ 8-3
Error Detection and Correction for CRAM.................................................................................8-3
Specifications.............................................................................................................................................. 8-11
Error Detection Frequency...........................................................................................................8-11
Error Detection Time.................................................................................................................... 8-11
EMR Update Interval.................................................................................................................... 8-12
Error Correction Time.................................................................................................................. 8-12
Document Revision History.....................................................................................................................8-13
JTAG Boundary-Scan Testing in Arria 10 Devices............................................ 9-1
BST Operation Control .............................................................................................................................. 9-1
IDCODE ...........................................................................................................................................9-1
Supported JTAG Instruction .........................................................................................................9-2
JTAG Secure Mode ......................................................................................................................... 9-5
JTAG Private Instruction ...............................................................................................................9-5
I/O Voltage for JTAG Operation ..............................................................................................................9-5
Performing BST ...........................................................................................................................................9-6
Enabling and Disabling IEEE Std. 1149.1 BST Circuitry ...................................................................... 9-6
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing.......................................................................9-7
IEEE Std. 1149.1 Boundary-Scan Register ...............................................................................................9-7
Boundary-Scan Cells of an Arria 10 Device I/O Pin...................................................................9-8
IEEE Std. 1149.6 Boundary-Scan Register..................................................................................9-10
Document Revision History.....................................................................................................................9-12
Power Management in Arria 10 Devices...........................................................10-1
Power Consumption..................................................................................................................................10-1
Dynamic Power Equation.............................................................................................................10-2
Power Reduction Techniques.................................................................................................................. 10-2
SmartVID ....................................................................................................................................... 10-2
VCC PowerManager....................................................................................................................... 10-3
Programmable Power Technology.............................................................................................. 10-3
Low Static Power Device Grades................................................................................................. 10-4
SmartVID and VCC PowerManager Features Implementation.............................................. 10-4
Power Sense Line....................................................................................................................................... 10-6
Voltage Sensor............................................................................................................................................10-6
Input Signal Range for External Analog Signal......................................................................... 10-7
Using Voltage Sensor in Arria 10 Devices..................................................................................10-7
Temperature Sensing Diode...................................................................................................................10-12
Internal Temperature Sensing Diode........................................................................................10-12
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Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices
TOC-7
External Temperature Sensing Diode....................................................................................... 10-14
Power-On Reset Circuitry...................................................................................................................... 10-15
Power Supplies Monitored and Not Monitored by the POR Circuitry............................... 10-17
Power-Up and Power-Down Sequences...............................................................................................10-18
Power Supply Design...............................................................................................................................10-19
Document Revision History...................................................................................................................10-20
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1
Logic Array Blocks and Adaptive Logic Modules
in Arria 10 Devices
2015.12.16
A10-LAB
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The logic array block (LAB) is composed of basic building blocks known as adaptive logic modules
(ALMs). You can configure the LABs to implement logic functions, arithmetic functions, and register
functions.
You can use a quarter of the available LABs in the Arria® 10 devices as a memory LAB (MLAB). Certain
devices may have higher MLAB ratio.
The Quartus® Prime software and other supported third-party synthesis tools, in conjunction with
parameterized functions such as the library of parameterized modules (LPM), automatically choose the
appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions.
This chapter contains the following sections:
• LAB
• ALM Operating Modes
Related Information
Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
LAB
The LABs are configurable logic blocks that consist of a group of logic resources. Each LAB contains
dedicated logic for driving control signals to its ALMs.
MLAB is a superset of the LAB and includes all the LAB features.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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ISO
9001:2008
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A10-LAB
2015.12.16
MLAB
Figure 1-1: LAB Structure and Interconnects Overview in Arria 10 Devices
This figure shows an overview of the Arria 10 LAB and MLAB structure with the LAB interconnects.
C4
C27
Row Interconnects of
Variable Speed and Length
R32
R3/R6
ALMs
Direct-Link
Interconnect from
Adjacent Block
Direct-Link
Interconnect from
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
Local
Interconnect
LAB
MLAB
Local Interconnect is Driven
from Either Side by Columns and LABs,
and from Above by Rows
Column Interconnects of
Variable Speed and Length
MLAB
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM.
You can configure each ALM in an MLAB as a 32 (depth) x 2 (width) memory block, resulting in a
configuration of 32 (depth) x 20 (width) simple dual-port SRAM block.
MLAB supports the following 64-deep modes in soft implementation using the Quartus Prime software:
• 64 (depth) x 8 (width)
• 64 (depth) x 9 (width)
• 64 (depth) x 10 (width)
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Local and Direct Link Interconnects
1-3
Figure 1-2: LAB and MLAB Structure for Arria 10 Devices
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LAB Control Block
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
LAB Control Block
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
MLAB
LAB
Local and Direct Link Interconnects
Each LAB can drive out 40 ALM outputs. Two groups of 20 ALM outputs can drive the adjacent LABs
directly through direct-link interconnects.
The direct link connection feature minimizes the use of row and column interconnects, providing higher
performance and flexibility.
The local interconnect drives ALMs in the same LAB using column and row interconnects, and ALM
outputs in the same LAB.
Neighboring LABs, MLABs, M20K blocks, or digital signal processing (DSP) blocks from the left or right
can also drive the LAB’s local interconnect using the direct link connection.
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Shared Arithmetic Chain and Carry Chain Interconnects
Figure 1-3: LAB Local and Direct Link Interconnects for Arria 10 Devices
Direct-Link Interconnect from the
Right LAB, MLAB/M20K Memory
Block, DSP Block, or IOE Output
Direct-Link Interconnect from the
Left LAB, MLAB/M20K Memory
Block, DSP Block, or IOE Output
ALMs
ALMs
Direct-Link
Interconnect
to Left
Direct-Link
Interconnect
to Right
Local
Interconnect
MLAB
LAB
Shared Arithmetic Chain and Carry Chain Interconnects
There are two dedicated paths between ALMs—carry chain and shared arithmetic chain. Arria 10 devices
include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains
for efficient arithmetic functions. These ALM-to-ALM connections bypass the local interconnect. The
Quartus Prime Compiler automatically takes advantage of these resources to improve utilization and
performance.
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LAB Control Signals
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Figure 1-4: Shared Arithmetic Chain and Carry Chain Interconnects
Local Interconnect
Routing among ALMs
in the LAB
ALM 1
ALM 2
Local
Interconnect
ALM 3
Carry Chain and Shared
Arithmetic Chain
Routing to Adjacent ALM
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
ALM 9
ALM 10
LAB Control Signals
Each LAB contains dedicated logic for driving the control signals to its ALMs, and has two unique clock
sources and three clock enable signals.
The LAB control block generates up to three clocks using the two clock sources and three clock enable
signals. Each clock and the clock enable signals are linked.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock.
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. The
inherent low skew of the MultiTrack interconnect allows clock and control signal distribution in addition
to data. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of
different lengths and speeds used for inter- and intra-design block connectivity.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear signal. The ALM directly supports an asynchro‐
nous clear function. The register preset is implemented as the NOT-gate push-back logic in the Quartus
Prime software. Each LAB supports up to two clears.
Arria 10 devices provide a device-wide reset pin (DEV_CLRn) that resets all the registers in the device. You
can enable the DEV_CLRn pin in the Quartus Prime software before compilation. The device-wide reset
signal overrides all other control signals.
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ALM Resources
Figure 1-5: LAB-Wide Control Signals for Arria 10 Devices
This figure shows the clock sources and clock enable signals in a LAB.
There are two unique
clock signals per LAB.
6
Dedicated Row
LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclkena0
or asyncload
or labpreset
labclr1
syncload
labclk2
labclkena1
labclkena2
labclr0
synclr
ALM Resources
Each ALM contains a variety of LUT-based resources that can be divided between two combinational
adaptive LUTs (ALUTs) and four registers.
With up to eight inputs for the two combinational ALUTs, one ALM can implement various combina‐
tions of two functions. This adaptability allows an ALM to be completely backward-compatible with fourinput LUT architectures. One ALM can also implement any function with up to six inputs and certain
seven-input functions.
One ALM contains four programmable registers. Each register has the following ports:
•
•
•
•
Data
Clock
Synchronous and asynchronous clear
Synchronous load
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock enable signal
and the clock and clear control signals of an ALM register.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives
directly to the outputs of an ALM.
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ALM Output
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Note: The Quartus Prime software automatically configures the ALMs for optimized performance.
Figure 1-6: ALM High-Level Block Diagram for Arria 10 Devices
shared_arith_in
carry_in
Combinational/
Memory ALUT0
dataf0
datae0
dataa
6-Input LUT
labclk
adder0
reg0
datab
reg1
To General Routing
datac
datad
datae1
adder1
6-Input LUT
reg2
dataf1
Combinational/
Memory ALUT1
shared_arith_out
carry_out
reg3
ALM Output
The general routing outputs in each ALM drive the local, row, and column routing resources. Two ALM
outputs can drive column, row, or direct link routing connections.
The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output
while the register drives another output.
Register packing improves device utilization by allowing unrelated register and combinational logic to be
packed into a single ALM. Another mechanism to improve fitting is to allow the register output to feed
back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. The ALM can
also drive out registered and unregistered versions of the LUT or adder output.
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ALM Operating Modes
Figure 1-7: ALM Connection Details for Arria 10 Devices
syncload
aclr[1:0]
clk[2:0] sclr
shared_arith_in
carry_in
dataf0
datae0
dataa
datab
datac
GND
4-Input
LUT
3-Input
LUT
+
D
CLR
Q
Row, Column
Direct Link Routing
Q
Row, Column
Direct Link Routing
Q
Row, Column
Direct Link Routing
Q
Row, Column
Direct Link Routing
3
3-Input
LUT
D
4-Input
LUT
datad
3-Input
LUT
CLR
3
D
+
3-Input
LUT
D
VCC
CLR
CLR
datae1
dataf1
shared_arith_out carry_out
ALM Operating Modes
The Arria 10 ALM operates in any of the following modes:
•
•
•
•
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Normal Mode
Normal mode allows two functions to be implemented in one Arria 10 ALM, or a single function of up to
six inputs.
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Normal Mode
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Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
The ALM can support certain combinations of completely independent functions and various combina‐
tions of functions that have common inputs.
The Quartus Prime Compiler automatically selects the inputs to the LUT. ALMs in normal mode support
register packing.
Figure 1-8: ALM in Normal Mode
Combinations of functions with fewer inputs than those shown are also supported. For example,
combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2,
and 5 and 2.
dataf0
datae0
datac
dataa
4-Input
LUT
combout0
datab
datad
datae1
dataf1
4-Input
LUT
combout1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
datad
datae1
dataf1
dataf0
datae0
datac
dataa
datab
datad
datae1
dataf1
3-Input
LUT
5-Input
LUT
4-Input
LUT
5-Input
LUT
combout0
5-Input
LUT
combout1
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
6-Input
LUT
combout1
datad
datae1
dataf1
combout1
combout0
combout1
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dataf0
datae0
datac
dataa
datab
datae1
dataf1
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Normal Mode
For the packing of 2 five-input functions into one ALM, the functions must have at least two common
inputs. The common inputs are dataa and datab. The combination of a four-input function with a fiveinput function requires one common input (either dataa or datab).
In the case of implementing 2 six-input functions in one ALM, four inputs must be shared and the
combinational function must be the same. In a sparsely used device, functions that could be placed in one
ALM may be implemented in separate ALMs by the Quartus Prime software to achieve the best possible
performance. As a device begins to fill up, the Quartus Prime software automatically uses the full potential
of the Arria 10 ALM. The Quartus Prime Compiler automatically searches for functions using common
inputs or completely independent functions to be placed in one ALM to make efficient use of device
resources. In addition, you can manually control resource use by setting location assignments.
Figure 1-9: Input Function in Normal Mode
labclk
datae0
dataf1
dataa
datab
datac
datad
6-Input
LUT
reg0
reg1
To General Routing
datae1
dataf0
reg2
These inputs are available
for register packing.
reg3
You can implement any six-input function using the following inputs:
•
•
•
•
•
dataa
datab
datac
datad
datae0 and dataf1, or datae1 and dataf0
If you use datae0 and dataf1 inputs, you can obtain the following outputs:
• output driven to register0 or register0 is bypassed
• output driven to register1 or register1 is bypassed
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Extended LUT Mode
1-11
You can use the datae1 or dataf0 input, whichever is available, as the packed register input to register2
or register3.
If you use datae1 and dataf0 inputs, you can obtain the following outputs:
• output driven to register2 or register2 is bypassed
• output driven to register3 or register3 is bypassed
You can use the datae0 or dataf1 input, whichever is available, as the packed register input to register0
or register1.
Extended LUT Mode
Figure 1-10: Template for Supported 7-Input Functions in Extended LUT Mode for Arria 10 Devices
labclk
datae0
datae1
dataf0
dataa
datab
datac
datad
Extended
LUT
reg0
reg1
To General Routing
dataf1
This input is available
for register packing.
reg2
reg3
A 7-input function can be implemented in a single ALM using the following inputs:
•
•
•
•
•
•
•
dataa
datab
datac
datad
datae0
datae1
dataf0 or dataf1
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Arithmetic Mode
If you use dataf0 input, you can obtain the following outputs:
• output driven to register0 or register0 is bypassed
• output driven to register1 or register1 is bypassed
You can use the dataf1 input as the packed register input to register2 or register3.
If you use dataf1 input, you can obtain the following outputs:
• output driven to register2 or register2 is bypassed
• output driven to register3 or register3 is bypassed
You can use the dataf0 input as the packed register input to register0 or register1.
Arithmetic Mode
The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders.
The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output
of two 4-input functions.
The ALM supports simultaneous use of the adder’s carry output along with combinational logic outputs.
The adder output is ignored in this operation.
Using the adder with the combinational logic output provides resource savings of up to 50% for functions
that can use this mode.
Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and
subtract control, synchronous clear, and synchronous load.
The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down,
and add/subtract control signals. These control signals are good candidates for the inputs that are shared
between the four LUTs in the ALM.
The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the
LAB. You can individually disable or enable these signals for each register. The Quartus Prime software
automatically places any registers that are not used by the counter into other LABs.
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Shared Arithmetic Mode
1-13
Figure 1-11: ALM in Arithmetic Mode for Arria 10 Devices
datae0
dataf0
datac
datab
dataa
datad
datae1
dataf1
carry_in
adder0
4-Input
LUT
reg0
4-Input
LUT
adder1
4-Input
LUT
reg1
To General Routing
reg2
4-Input
LUT
carry_out
reg3
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared
arithmetic mode.
The two-bit carry select feature in Arria 10 devices halves the propagation delay of carry chains within the
ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is
implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB
before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for
implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the
first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the
bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the
column. You can bypass the top-half of the LAB columns and bottom-half of the MLAB columns.
The Quartus Prime Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared
arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs
vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A carry chain
can continue as far as a full column.
Shared Arithmetic Mode
The ALM in shared arithmetic mode can implement a 3-input add in the ALM.
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Shared Arithmetic Mode
This mode configures the ALM with four 4-input LUTs. Each LUT either computes the sum of three
inputs or the carry of three inputs. The output of the carry computation is fed to the next adder using a
dedicated connection called the shared arithmetic chain.
Figure 1-12: ALM in Shared Arithmetic Mode for Arria 10 Devices
shared_arith_in
carry_in
labclk
4-Input
LUT
datae0
datac
datab
dataa
datad
datae1
reg0
4-Input
LUT
reg1
4-Input
LUT
To General Routing
reg2
4-Input
LUT
reg3
shared_arith_out
carry_out
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a
3-input adder. This significantly reduces the resources necessary to implement large adder trees or
correlator functions.
The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.
Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns
can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in
an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column
is top-half bypassable; while in MLAB, columns are bottom-half bypassable.
The Quartus Prime Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long
shared arithmetic chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and
DSP blocks. A shared arithmetic chain can continue as far as a full column.
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LAB Power Management Techniques
1-15
LAB Power Management Techniques
The following techniques are used to manage static and dynamic power consumption within the LAB:
• Arria 10 LABs operate in high-performance mode or low-power mode. The Quartus Prime software
automatically optimizes the LAB power consumption mode based on your design.
• Clocks, especially LAB clocks, consumes a significant portion of dynamic power. Each LAB's clock and
clock enable signals are linked and can be controlled by a shared, gated clock. Use the LAB-wide clock
enable signal to gate the LAB-wide clock without disabling the entire clock tree. In your HDL code for
registered logic, use a clock-enable construct.
Related Information
Power Optimization chapter, Quartus Prime Handbook
Provides more information about implementing static and dynamic power consumption within the LAB.
Document Revision History
Date
Version
Changes
November
2015
2015.11.02
Changed instances of Quartus II to Quartus Prime.
December
2013
2013.12.02
Initial release.
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The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of
small- and large-sized memory arrays to fit your design requirements.
Related Information
Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
Types of Embedded Memory
The Arria 10 devices contain two types of memory blocks:
• 20 Kb M20K blocks—blocks of dedicated memory resources. The M20K blocks are ideal for larger
memory arrays while still providing a large number of independent ports.
• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dualpurpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The
MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applica‐
tions, wide and shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive
logic modules (ALMs). In the Arria 10 devices, you can configure these ALMs as ten 32 x 2 blocks,
giving you one 32 x 20 simple dual-port SRAM block per MLAB.
Related Information
embedded cell (EC)
Provides information about embedded cell
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Embedded Memory Capacity in Arria 10 Devices
Embedded Memory Capacity in Arria 10 Devices
Table 2-1: Embedded Memory Capacity and Distribution in Arria 10 Devices
Variant
Arria 10 GX
Arria 10 GT
Arria 10 SX
M20K
MLAB
Product
Line
Block
RAM Bit (Kb)
Block
RAM Bit (Kb)
Total RAM Bit (Kb)
GX 160
440
8,800
1,680
1,050
9,850
GX 220
587
11,740
2,703
1,690
13,430
GX 270
750
15,000
3,922
2,452
17,452
GX 320
891
17,820
4,363
2,727
20,547
GX 480
1,431
28,620
6,662
4,164
32,784
GX 570
1,800
36,000
8,153
5,096
41,096
GX 660
2,131
42,620
9,260
5,788
48,408
GX 900
2,423
48,460
15,017
9,386
57,846
GX 1150
2,713
54,260
20,774
12,984
67,244
GT 900
2,423
48,460
15,017
9,386
57,846
GT 1150
2,713
54,260
20,774
12,984
67,244
SX 160
440
8,800
1,680
1,050
9,850
SX 220
587
11,740
2,703
1,690
13,430
SX 270
750
15,000
3,922
2,452
17,452
SX 320
891
17,820
4,363
2,727
20,547
SX 480
1,431
28,620
6,662
4,164
32,784
SX 570
1,800
36,000
8,153
5,096
41,096
SX 660
2,131
42,620
9,260
5,788
48,408
Embedded Memory Design Guidelines for Arria 10 Devices
There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
Consider the Memory Block Selection
The Quartus Prime software automatically partitions the user-defined memory into the memory blocks
based on your design's speed and size constraints. For example, the Quartus Prime software may spread
out the memory across multiple available memory blocks to increase the performance of the design.
To assign the memory to a specific block size manually, use the RAM IP core in the parameter editor.
For the MLABs, you can implement single-port SRAM through emulation using the Quartus Prime
software. Emulation results in minimal additional use of logic resources.
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Guideline: Implement External Conflict Resolution
2-3
Because of the dual purpose architecture of the MLAB, only data input registers, output registers, and
write address registers are available in the block. The MLABs gain read address registers from the ALMs.
Note: For Arria 10 devices, the Resource Property Editor and the TimeQuest Timing Analyzer report the
location of the M20K block as EC_X<number>_Y<number>_N<number>, although the allowed
assigned location is M20K_ X<number>_Y<number>_N<number>. Embedded Cell (EC) is the
sublocation of the M20K block.
Guideline: Implement External Conflict Resolution
In the true dual-port RAM mode, you can perform two write operations to the same memory location.
However, the memory blocks do not have internal conflict resolution circuitry. To avoid unknown data
being written to the address, implement external conflict resolution logic to the memory block.
Guideline: Customize Read-During-Write Behavior
Customize the read-during-write behavior of the memory blocks to suit your design requirements.
Figure 2-1: Read-During-Write Data Flow
This figure shows the difference between the two types of read-during-write operations available—same
port and mixed port.
Port A
data in
FPGA Device
Port B
data in
Mixed-port
data flow
Same-port
data flow
Port A
data out
Port B
data out
Same-Port Read-During-Write Mode
The same-port read-during-write mode applies to a single-port RAM or the same port of a true dual-port
RAM.
Table 2-2: Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write Mode
This table lists the available output modes if you select the embedded memory blocks in the same-port readduring-write mode.
Output Mode
"new data"
Memory Type
M20K
The new data is available on the rising edge
of the same clock cycle on which the new
data is written.
M20K, MLAB
The RAM outputs "don't care" values for a
read-during-write operation.
(flow-through)
"don't care"
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Mixed-Port Read-During-Write Mode
Figure 2-2: Same-Port Read-During-Write: New Data Mode
This figure shows sample functional waveforms of same-port read-during-write behavior in the “new
data” mode.
clk_a
0A
address
0B
rden
wren
byteena
data_a
11
B456
A123
q_a (asynch)
A123
DDDD
C789
B456
C789
EEEE
DDDD
FFFF
EEEE
FFFF
Mixed-Port Read-During-Write Mode
The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two
ports perform read and write operations on the same memory address using the same clock—one port
reading from the address, and the other port writing to it.
Table 2-3: Output Modes for RAM in Mixed-Port Read-During-Write Mode
Output Mode
"new data"
Memory Type
MLAB
Description
A read-during-write operation to different ports causes the
MLAB registered output to reflect the “new data” on the next
rising edge after the data is written to the MLAB memory.
This mode is available only if the output is registered.
"old data"
M20K, MLAB
A read-during-write operation to different ports causes the
RAM output to reflect the “old data” value at the particular
address.
For MLAB, this mode is available only if the output is
registered.
"don't care"
M20K, MLAB
The RAM outputs “don’t care” or “unknown” value.
• For M20K memory, the Quartus Prime software does not
analyze the timing between write and read operations.
• For MLAB, the Quartus Prime software analyzes the timing
between write and read operations by default. To disable
this behavior, turn on the Do not analyze the timing
between write and read operation. Metastability issues are
prevented by never writing and reading at the same
address at the same time option.
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Mixed-Port Read-During-Write Mode
Output Mode
"constrained
don't care"
Memory Type
2-5
Description
MLAB
The RAM outputs “don’t care” or “unknown” value. The
Quartus Prime software analyzes the timing between write and
read operations in the MLAB.
Figure 2-3: Mixed-Port Read-During-Write: New Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “new
data” mode.
clk_a&b
wren_a
A0
address_a
data_a
AAAA
A1
BBBB
CCCC
DDDD
EEEE
FFFF
11
byteena_a
rden_b
address_b
q_b (synch)
A0
A1
AAAA
XXXX
BBBB
CCCC
DDDD
EEEE
FFFF
Figure 2-4: Mixed-Port Read-During-Write: Old Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “old
data” mode.
clk_a&b
wren_a
address_a
data_a
A0
AAAA
A1
BBBB
CCCC
byteena_a
DDDD
FFFF
EEEE
11
rden_b
address_b
q_b (asynch)
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A0
A0 (old data)
A1
AAAA
BBBB
A1 (old data)
DDDD
EEEE
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Guideline: Consider Power-Up State and Memory Initialization
Figure 2-5: Mixed-Port Read-During-Write: Don’t Care or Constrained Don’t Care Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “don’t
care” or “constrained don’t care” mode.
clk_a&b
wren_a
address_a
data_a
byteena_a
A1
A0
AAAA
BBBB
CCCC
11
01
10
DDDD
EEEE
FFFF
11
rden_b
address_b
A1
A0
q_b (asynch)
XXXX (unknown data)
In the dual-port RAM mode, the mixed-port read-during-write operation is supported if the input
registers have the same clock.
Related Information
Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
Provides more information about the RAM IP core that controls the read-during-write behavior.
Guideline: Consider Power-Up State and Memory Initialization
Consider the power up state of the different types of memory blocks if you are designing logic that
evaluates the initial power-up values, as listed in the following table.
Table 2-4: Initial Power-Up Values of Embedded Memory Blocks
Memory Type
MLAB
M20K
Output Registers
Power Up Value
Used
Zero (cleared)
Bypassed
Read memory contents
Used
Zero (cleared)
Bypassed
Zero (cleared)
By default, the Quartus Prime software initializes the RAM cells in Arria 10 devices to zero unless you
specify a .mif.
All memory blocks support initialization with a .mif. You can create .mif files in the Quartus Prime
software and specify their use with the RAM IP core when you instantiate a memory in your design. Even
if a memory is pre-initialized (for example, using a .mif), it still powers up with its output cleared.
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Guideline: Control Clocking to Reduce Power Consumption
2-7
Related Information
• Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User
Guide
Provides more information about .mif files.
• Quartus Prime Handbook Volume 1: Design and Synthesis
Provides more information about .mif files.
Guideline: Control Clocking to Reduce Power Consumption
Reduce AC power consumption of each memory block in your design:
• Use Arria 10 memory block clock-enables to allow you to control clocking of each memory block.
• Use the read-enable signal to ensure that read operations occur only when necessary. If your design
does not require read-during-write, you can reduce your power consumption by deasserting the readenable signal during write operations, or during the period when no memory operations occur.
• Use the Quartus Prime software to automatically place any unused memory blocks in low-power mode
to reduce static power.
Embedded Memory Features
Table 2-5: Memory Features in Arria 10 Devices
This table summarizes the features supported by the embedded memory blocks.
Features
M20K
MLAB
730 MHz
700 MHz
20,480
640
Parity bits
Supported
Supported
Byte enable
Supported
Supported
Packed mode
Supported
—
Address clock enable
Supported
Supported
Simple dual-port mixed width
Supported
—
True dual-port mixed width
Supported
—
FIFO buffer mixed width
Supported
—
Memory Initialization File (.mif)
Supported
Supported
Mixed-clock mode
Supported
Supported
Fully synchronous memory
Supported
Supported
—
Only for flow-through read
memory operations.
Maximum operating frequency
Total RAM bits (including parity bits)
Asynchronous memory
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Embedded Memory Features
Features
M20K
MLAB
Power-up state
Output ports are
cleared.
• Registered output ports—
Cleared.
• Unregistered output ports—
Read memory contents.
Asynchronous clears
Output registers and
output latches
Output registers and output
latches
Write/read operation triggering
Rising clock edges
Rising clock edges
Same-port read-during-write
Output ports set to
"new data" or "don't
care".
Output ports set to "don't care".
Mixed-port read-during-write
Output ports set to
"old data" or "don't
care".
Output ports set to "old data", "new
data", "don't care", or "constrained
don't care".
ECC support
Soft IP support using
the Quartus Prime
software.
Soft IP support using the Quartus
Prime software.
Built-in support in
x32-wide simple dualport mode.
Related Information
Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
Provides more information about the embedded memory features.
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Embedded Memory Modes
2-9
Embedded Memory Modes
Table 2-6: Memory Modes Supported in the Embedded Memory Blocks
This table lists and describes the memory modes that are supported in the Arria 10 embedded memory blocks.
Memory Mode
Single-port RAM
M20K
Support
MLAB
Support
Yes
Yes
Description
You can perform only one read or one write operation at a
time.
Use the read enable port to control the RAM output ports
behavior during a write operation:
• To retain the previous values that are held during the most
recent active read enable—create a read-enable port and
perform the write operation with the read enable port
deasserted.
• To show the new data being written, the old data at that
address, or a "Don't Care" value when read-during-write
occurs at the same address location—do not create a readenable signal, or activate the read enable during a write
operation.
Simple dual-port
RAM
Yes
Yes
You can simultaneously perform one read and one write
operations to different locations where the write operation
happens on port A and the read operation happens on port B.
True dual-port
RAM
Yes
—
You can perform any combination of two port operations: two
reads, two writes, or one read and one write at two different
clock frequencies.
Shift-register
Yes
Yes
You can use the memory blocks as a shift-register block to save
logic cells and routing resources.
This is useful in DSP applications that require local data storage
such as finite impulse response (FIR) filters, pseudo-random
number generators, multi-channel filtering, and auto- and
cross- correlation functions. Traditionally, the local data
storage is implemented with standard flip-flops that exhaust
many logic cells for large shift registers.
The input data width (w), the length of the taps (m), and the
number of taps (n) determine the size of a shift register
(w × m × n). You can cascade memory blocks to implement
larger shift registers.
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Embedded Memory Configurations for Single-port Mode
Memory Mode
ROM
M20K
Support
MLAB
Support
Yes
Yes
Description
You can use the memory blocks as ROM.
• Initialize the ROM contents of the memory blocks using
a .mif or .hex.
• The address lines of the ROM are registered on M20K
blocks but can be unregistered on MLABs.
• The outputs can be registered or unregistered.
• The output registers can be asynchronously cleared.
• The ROM read operation is identical to the read operation
in the single-port RAM configuration.
FIFO
Yes
Yes
You can use the memory blocks as FIFO buffers. Use the
SCFIFO and DCFIFO megafunctions to implement single- and
dual-clock asynchronous FIFO buffers in your design.
For designs with many small and shallow FIFO buffers, the
MLABs are ideal for the FIFO mode. However, the MLABs do
not support mixed-width FIFO mode.
Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the
memory block input registers during read or write operations. This is applicable if you use the
memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM
mode.
Related Information
• Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User
Guide
Provides more information about memory modes.
• RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide
Provides more information about implementing the shift register mode.
• SCFIFO and DCFIFO IP Cores User Guide
Provides more information about implementing FIFO buffers.
Embedded Memory Configurations for Single-port Mode
Table 2-7: Single-port Embedded Memory Configurations for Arria 10 Devices
This table lists the maximum configurations supported for single-port RAM and ROM modes.
Memory Block
MLAB
(1)
Depth (bits)
Programmable Width
32
x16, x18, or x20
64(1)
x8, x9, x10
Supported through software emulation and consumes additional MLAB blocks.
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Embedded Memory Configurations for Dual-port Modes
Memory Block
Depth (bits)
Programmable Width
512
x40, x32
1K
x20, x16
2K
x10, x8
4K
x5, x4
8K
x2
16K
x1
M20K
2-11
Embedded Memory Configurations for Dual-port Modes
Table 2-8: Memory Configurations for Simple Dual-Port RAM Mode
This table lists the memory configurations for the simple dual-port RAM mode. Mixed-width configurations are
only supported in M20K blocks.
Read
Port
Write Port
16K x 1
8K x 2
4K x 4
4K x 5
2K x 8
2K x 10
1K x 16
1K x 20
512 x 32
512 x 40
16K
x1
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
8K x
2
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
4K x
4
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
4K x
5
—
—
—
Yes
—
Yes
—
Yes
—
Yes
2K x
8
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
2K x
10
—
—
—
Yes
—
Yes
—
Yes
—
Yes
1K x
16
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
1K x
20
—
—
—
Yes
—
Yes
—
Yes
—
Yes
512
x 32
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
512
x 40
—
—
—
Yes
—
Yes
—
Yes
—
Yes
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Embedded Memory Clocking Modes
Table 2-9: Memory Configurations for True Dual-Port Mode
This table lists the memory configurations for the true dual-port RAM mode. Mixed-width configurations are
only supported in M20K blocks.
Port B
Port A
16K x 1
8K x 2
4K x 4
4K x 5
2K x 8
2K x 10
1K x 16
1K x 20
16K x
1
Yes
Yes
Yes
—
Yes
—
Yes
—
8K x 2
Yes
Yes
Yes
—
Yes
—
Yes
—
4K x 4
Yes
Yes
Yes
—
Yes
—
Yes
—
4K x 5
—
—
—
Yes
—
Yes
—
Yes
2K x 8
Yes
Yes
Yes
—
Yes
—
Yes
—
2K x 1
0
—
—
—
Yes
—
Yes
—
Yes
1K x 1
6
Yes
Yes
Yes
—
Yes
—
Yes
—
1K x 2
0
—
—
—
Yes
—
Yes
—
Yes
Embedded Memory Clocking Modes
This section describes the clocking modes for the Arria 10 memory blocks.
Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the
memory block input registers during read or write operations.
Clocking Modes for Each Memory Mode
Table 2-10: Memory Blocks Clocking Modes Supported for Each Memory Mode
Memory Mode
Clocking Mode
Single-Port
Simple DualPort
True DualPort
ROM
FIFO
Single clock mode
Yes
Yes
Yes
Yes
Yes
Read/write clock mode
—
Yes
—
—
Yes
Input/output clock mode
Yes
Yes
Yes
Yes
—
Independent clock mode
—
—
Yes
Yes
—
Note: The clock enable signals are not supported for write address, byte enable, and data input registers
on MLAB blocks.
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Single Clock Mode
2-13
Single Clock Mode
In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory
block.
Read/Write Clock Mode
In the read/write clock mode, a separate clock is available for each read and write port. A read clock
controls the data-output, read-address, and read-enable registers. A write clock controls the data-input,
write-address, write-enable, and byte enable registers.
Input/Output Clock Mode
In input/output clock mode, a separate clock is available for each input and output port. An input clock
controls all registers related to the data input to the memory block including data, address, byte enables,
read enables, and write enables. An output clock controls the data output registers.
Independent Clock Mode
In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all
registers on the port A side; clock B controls all registers on the port B side.
Note: You can create independent clock enable for different input and output registers to control the shut
down of a particular register for power saving purposes. From the parameter editor, click More
Options (beside the clock enable option) to set the available independent clock enable that you
prefer.
Asynchronous Clears in Clocking Modes
In all clocking modes, asynchronous clears are available only for output latches and output registers. For
the independent clock mode, this is applicable on both ports.
Output Read Data in Simultaneous Read/Write
If you perform a simultaneous read/write to the same address location using the read/write clock mode,
the output read data is unknown. If you require the output read data to be a known value, use single-clock
or input/output clock mode and select the appropriate read-during-write behavior in the IP core
parameter editor.
Independent Clock Enables in Clocking Modes
Independent clock enables are supported in the following clocking modes:
• Read/write clock mode—supported for both the read and write clocks.
• Independent clock mode—supported for the registers of both ports.
To save power, you can control the shut down of a particular register using the clock enables.
Related Information
Guideline: Control Clocking to Reduce Power Consumption on page 2-7
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Parity Bit in Embedded Memory Blocks
Parity Bit in Embedded Memory Blocks
Table 2-11: Parity Bit Support for the Embedded Memory Blocks
This table describes the parity bit support for the memory blocks.
M20K
MLAB
• The parity bit is the fifth bit associated with each • The parity bit is the ninth bit associated with
4 data bits in data widths of 5, 10, 20, and 40
each byte.
(bits 4, 9, 14, 19, 24, 29, 34, and 39).
• The ninth bit can store a parity bit or serve as an
• In non-parity data widths, the parity bits are
additional bit.
skipped during read or write operations.
• Parity function is not performed on the parity
• Parity function is not performed on the parity
bit.
bit.
Byte Enable in Embedded Memory Blocks
The embedded memory blocks support byte enable controls:
• The byte enable controls mask the input data so that only specific bytes of data are written. The
unwritten bytes retain the values written previously.
• The write enable (wren) signal, together with the byte enable (byteena) signal, control the write
operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren
signal controls the writing.
• The byte enable registers do not have a clear port.
• If you are using parity bits, on the M20K blocks, the byte enable function controls 8 data bits and 2
parity bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
• Byte enables operate in a one-hot fashion. The LSB of the byteena signal corresponds to the LSB of the
data bus.
• The byte enable signals are active high.
Byte Enable Controls in Memory Blocks
Table 2-12: byteena Controls in x20 Data Width
byteena[1:0]
Data Bits Written
11 (default)
[19:10]
[9:0]
10
[19:10]
—
01
—
[9:0]
Table 2-13: byteena Controls in x40 Data Width
byteena[3:0]
Data Bits Written
1111 (default)
[39:30]
[29:20]
[19:10]
[9:0]
1000
[39:30]
—
—
—
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Data Byte Output
byteena[3:0]
Data Bits Written
0100
—
[29:20]
—
—
0010
—
—
[19:10]
—
0001
—
—
—
[9:0]
Data Byte Output
In M20K blocks or MLABs, when you set a byte-enable bit to 0, the embedded memory IP sets the
corresponding data byte output to a “don't care” value. You must ensure that the option Get X's for write
masked bytes instead of old data when byte enable is always selected.
RAM Blocks Operations
Figure 2-6: Byte Enable Functional Waveform
This figure shows how the wren and byteena signals control the operations of the RAM blocks.
inclock
wren
address
data
byteena
contents at a0
contents at a1
an
a0
a1
a2
XXXXXXXX
a3
a4
a0
XXXXXXXX
ABCDEF12
XXXX
1000
0100
0010
0001
FFFFFFFF
FFCDFFFF
FFFFFFFF
contents at a3
XXXX
ABFFFFFF
FFFFFFFF
contents at a2
1111
FFFFEFFF
FFFFFFFF
contents at a4
FFFFFF12
ABCDEF12
FFFFFFFF
don’t care: q (asynch)
doutn
ABXXXXXX
XXCDXXXX
XXXXEFXX
XXXXXX12
ABCDEF12
ABFFFFFF
current data: q (asynch)
doutn
ABFFFFFF
FFCDFFFF
FFFFEFFF
FFFFFF12
ABCDEF12
ABFFFFFF
Memory Blocks Packed Mode Support
The M20K memory blocks support packed mode.
The packed mode feature packs two independent single-port RAM blocks into one memory block. The
Quartus Prime software automatically implements packed mode where appropriate by placing the
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Memory Blocks Address Clock Enable Support
physical RAM block in true dual-port mode and using the MSB of the address to distinguish between the
two logical RAM blocks. The size of each independent single-port RAM must not exceed half of the target
block size.
Memory Blocks Address Clock Enable Support
The embedded memory blocks support address clock enable, which holds the previous address value for
as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dualport mode, each port has its own independent address clock enable. The default value for the address
clock enable signal is low (disabled).
Figure 2-7: Address Clock Enable
This figure shows an address clock enable block diagram. The address clock enable is referred to by the
port name addressstall.
address[0]
1
0
address[0]
register
address[N]
1
0
address[N]
register
address[0]
address[N]
addressstall
clock
Figure 2-8: Address Clock Enable During Read Cycle Waveform
This figure shows the address clock enable waveform during the read cycle.
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory)
an
q (synch) doutn-1
q (asynch)
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doutn
a1
a0
doutn
dout0
dout0
a4
dout4
dout1
dout1
a5
dout4
dout5
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Memory Blocks Asynchronous Clear
2-17
Figure 2-9: Address Clock Enable During the Write Cycle Waveform
This figure shows the address clock enable waveform during the write cycle.
inclock
wraddress
a0
a1
a2
a3
a4
a5
a6
data
00
01
02
03
04
05
06
wren
addressstall
latched address
(inside memory)
contents at a0
an
a1
a0
XX
01
02
contents at a2
XX
contents at a3
XX
contents at a4
a5
00
XX
contents at a1
a4
04
XX
contents at a5
03
XX
05
Memory Blocks Asynchronous Clear
The M20K memory blocks support asynchronous clear on output latches and output registers. If your
RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear.
The clear is an asynchronous signal and it is generated at any time. The internal logic extends the clear
pulse until the next rising edge of the output clock. When the clear is asserted, the outputs are cleared and
stay cleared until the next read cycle.
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Memory Blocks Error Correction Code Support
Figure 2-10: Output Latch Clear in Arria 10 Devices (Non-ECC Mode)
clk
rden
aclr
clr at
latch
D0
out
D2
D1
Figure 2-11: Output Latch Clear in Arria 10 Devices (ECC Mode)
cken
clk
rden
aclr
clr at
latch
D0
out
D0
D1
D2
Memory Blocks Error Correction Code Support
ECC allows you to detect and correct data errors at the output of the memory. ECC can perform singleerror correction, double-adjacent-error correction, and triple-adjacent-error detection in a 32-bit word.
However, ECC cannot detect four or more errors.
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Error Correction Code Truth Table
2-19
The M20K blocks have built-in support for ECC when in x32-wide simple dual-port mode:
• The M20K runs slower than non-ECC simple-dual port mode when ECC is engaged. However, you
can enable optional ECC pipeline registers before the output decoder to achieve higher performance
compared to non-pipeline ECC mode at the expense of one cycle of latency.
• The M20K ECC status is communicated with two ECC status flag signals—e (error) and ue
(uncorrectable error). The status flags are part of the regular output from the memory block. When
ECC is engaged, you cannot access two of the parity bits because the ECC status flag replaces them.
Related Information
Memory Blocks Error Correction Code Support
Error Correction Code Truth Table
Table 2-14: ECC Status Flags Truth Table
Status
e (error)
ue (uncorrectable error)
eccstatus[1]
eccstatus[0]
0
0
No error.
0
1
Illegal.
1
0
A correctable error occurred and the
error has been corrected at the
outputs; however, the memory array
has not been updated.
1
1
An uncorrectable error occurred and
uncorrectable data appears at the
outputs.
If you engage ECC:
• You cannot use the byte enable feature.
• Read-during-write old data mode is not supported.
Figure 2-12: ECC Block Diagram for M20K Memory
Status Flag
Generation
40
8
32
Input
Register
32
ECC
Encoder
8
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Memory
Array
40
Optional
Pipeline
Register
2
40
40
ECC
Decoder
38
Output
Register
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Document Revision History
Document Revision History
Date
Version
Changes
December
2015
2015.12.14
• Updated the number of M20K memory blocks for Arria 10 GX 660
from 2133 to 2131 and corrected the total RAM bit from 48,448 Kb to
48,408 Kb.
November
2015
2015.11.02
• Updated the following topics: Embedded Memory Configurations for
Single-port mode and Embedded Memory Configurations for Dualport mode.
• Updated the description in the Data Byte Output topic.
• Updated the Embedded Memory Capacity and Distribution table.
• Changed instances of Quartus II to Quartus Prime.
June 2015
2015.06.15
Updated links.
May 2015
2015.05.04
• Updated Mega Wizard Plug-In manager to IP Core parameter editor.
• Updated Megafunction to IP core.
August 2014
2014.08.18
• Added a new timing diagram for output latch clear in ECC mode.
• Added a note to clarify that for Arria 10 devices, the Resource
Property Editor and the TimeQuest Timing Analyzer report the
location of the M20K block as EC_X<number>_Y<number>_N<number>
• Updated the RAM bit value in M20K block for Arria 10 GX 660 and
Arria 10 SX 660.
December
2013
2013.12.02
Initial release.
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Variable Precision DSP Blocks in Arria 10
Devices
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A10-DSP
Subscribe
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This chapter describes how the variable-precision digital signal processing (DSP) blocks in Arria 10
devices are optimized to support higher bit precision in high-performance DSP applications.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Supported Operational Modes in Arria 10 Devices
Supported Operational Modes in Arria 10 Devices
Table 3-1: Supported Combinations of Operational Modes and Features for Variable Precision DSP Block in
Arria 10 Devices
VariablePrecision
DSP Block
Resource
Operation
Mode
Supported
Operation
Instance
Pre-Adder
Support
Coefficient
Support
Input
Cascade
Support
Fixed-point
independent
18 x 19
multiplication
2
Yes
Yes
Yes (2)
No
No
Fixed-point
independent
27 x 27
multiplication
1
Yes
Yes
Yes (3)
Yes
Yes
Fixed-point
1 variable
two 18 x 19
precision
multiplier
DSP
adder mode
block
Fixed-point
18 x 18
multiplier
adder summed
with 36-bit
input
1
Yes
Yes
Yes(2)
Yes
Yes
1
No
No
No
Yes
Yes
1
Yes
Yes
Yes(2)
Yes
Yes
Fixed-point
18 x 19 systolic
mode
(2)
(3)
Chainin
Support
Chainout Support
Each of the two inputs to a pre-adder has a maximum width of 18-bit. When the input cascade is used to
feed one of the pre-adder inputs, the maximum width for the input cascade is 18-bit.
When you enable the pre-adder feature, the input cascade support is not available.
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Supported Operational Modes in Arria 10 Devices
VariablePrecision
DSP Block
Resource
Operation
Mode
Supported
Operation
Instance
Pre-Adder
Support
Coefficient
Support
Input
Cascade
Support
Floating-point
multiplication
mode
1
No
No
No
No
Yes
Floating-point
adder or
subtract mode
1
No
No
No
No
Yes
Floating-point
multiplier
1 variable adder or
precision subtract mode
DSP
Floating-point
block
multiplier
accumulate
mode
1
No
No
No
Yes
Yes
1
No
No
No
No
Yes
Floating-point
vector one
mode
1
No
No
No
Yes
Yes
Floating-point
vector two
mode
1
No
No
No
Yes
Yes
2
Complex
Variable 18x19
precision multiplication
DSP
blocks
1
No
No
Yes
No
No
Variable Precision DSP Blocks in Arria 10 Devices
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Chainin
Support
Chainout Support
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Supported Operational Modes in Arria 10 Devices
Table 3-2: Supported Combinations of Operational Modes and Dynamic Control Features for Variable
Precision DSP Blocks in Arria 10 Devices
Variable-Precision DSP
Block Resource
1 variable
precision DSP
block
2 variable
precision DSP
blocks
Altera Corporation
Operation Mode
Dynamic
ACCUMULATE
Dynamic
LOADCONST
Dynamic SUB
Dynamic NEGATE
Fixed-point
independent
18 x 19
multiplication
No
No
No
No
Fixed-point
independent
27 x 27
multiplication
Yes
Yes
No
Yes
Fixed-point two
18 x 19
multiplier adder
mode
Yes
Yes
Yes
Yes
Fixed-point
18 x 18
multiplier adder
summed with
36-bit input
Yes
Yes
Yes
Yes
Fixed-point
18 x 19 systolic
mode
Yes
Yes
Yes
Yes
Floating-point
multiplication
mode
No
No
No
No
Floating-point
adder or subtract
mode
No
No
No
No
Floating-point
multiplier adder
or subtract mode
No
No
No
No
Floating-point
multiplier
accumulate
mode
Yes
No
No
No
Floating-point
vector one mode
No
No
No
No
Floating-point
vector two mode
No
No
No
No
Complex 18 x 19
multiplication
No
No
No
No
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Features
3-5
Features
The Arria 10 variable precision DSP blocks support fixed-point arithmetic and floating-point arithmetic.
Features for fixed-point arithmetic:
•
•
•
•
•
•
•
•
•
•
High-performance, power-optimized, and fully registered multiplication operations
18-bit and 27-bit word lengths
Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication
results
Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when pre-adder is used to
form the tap-delay line for filtering applications
Cascading 64-bit output bus to propagate output results from one block to the next block without
external logic support
Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
Biased rounding support
Features for floating-point arithmetic:
• A completely hardened architecture that supports multiplication, addition, subtraction, multiply-add,
and multiply-subtract
• Multiplication with accumulation capability and a dynamic accumulator reset control
• Multiplication with cascade summation capability
• Multiplication with cascade subtraction capability
• Complex multiplication
• Direct vector dot product
• Systolic FIR filter
Related Information
• Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
• Arria 10 Device Overview - Variable-Precision DSP Block
Provides more information about the number of multipliers in each Arria 10 device.
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Resources
Resources
Table 3-3: Resources for Fixed-Point Arithmetic in Arria 10 Devices
The table lists the variable-precision DSP resources by bit precision for each Arria 10 device.
Independent Input and Output
Variant
Arria 10
GX
Arria 10
GT
Arria 10
SX
Altera Corporation
Product Line
Variableprecision
Multiplications Operator
DSP Block
18 x 19
27 x 27
Multiplier
Multiplier
18 x 19
18 x 18
Multiplier
Adder Sum
Mode
Multiplier Adder
Summed with 36 bit
Input
GX 160
156
312
156
156
156
GX 220
192
384
192
192
192
GX 270
830
1,660
830
830
830
GX 320
984
1,968
984
984
984
GX 480
1,368
2,736
1,368
1,368
1,368
GX 570
1,523
3,046
1,523
1,523
1,523
GX 660
1,687
3,374
1,687
1,687
1,687
GX 900
1,518
3,036
1,518
1,518
1,518
GX 1150
1,518
3,036
1,518
1,518
1,518
GT 900
1,518
3,036
1,518
1,518
1,518
GT 1150
1,518
3,036
1,518
1,518
1,518
SX 160
156
312
156
156
156
SX 220
192
384
192
192
192
SX 270
830
1,660
830
830
830
SX 320
984
1,968
984
984
984
SX 480
1,368
2,736
1,368
1,368
1,368
SX 570
1,523
3,046
1,523
1,523
1,523
SX 660
1,687
3,374
1,687
1,687
1,687
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Design Considerations
3-7
Table 3-4: Resources for Floating-Point Arithmetic in Arria 10 Devices
The table lists the variable-precision DSP resources by bit precision for each Arria 10 device.
Variant
Product Line
Variableprecision
DSP Block
Arria 10
GX
Arria 10
GT
Arria 10
SX
Single
Precision
FloatingPoint
Multiplica‐
tion Mode
Single-Precision
Floating-Point
Adder Mode
SinglePrecision
FloatingPoint
Multiply
Accumulate
Mode
Peak
Giga Floating-Point
Operations per
Second (GFLOPs)
GX 160
156
156
156
156
140
GX 220
192
192
192
192
173
GX 270
830
830
830
830
747
GX 320
984
984
984
984
886
GX 480
1,369
1,368
1,368
1,368
1,231
GX 570
1,523
1,523
1,523
1,523
1,371
GX 660
1,687
1,687
1,687
1,687
1,518
GX 900
1,518
1,518
1,518
1,518
1,366
GX 1150
1,518
1,518
1,518
1,518
1,366
GT 900
1,518
1,518
1,518
1,518
1,366
GT 1150
1,518
1,518
1,518
1,518
1,366
SX 160
156
156
156
156
140
SX 220
192
192
192
192
173
SX 270
830
830
830
830
747
SX 320
984
984
984
984
886
SX 480
1,369
1,368
1,368
1,368
1,231
SX 570
1,523
1,523
1,523
1,523
1,371
SX 660
1,687
1,687
1,687
1,687
1,518
Design Considerations
You should consider the following elements in your design:
Table 3-5: Design Considerations
DSP Implementation
Design elements
Fixed-Point Arthmetic
•
•
•
•
Operational modes
• Operational modes
Internal coefficient and pre-adder • Chainout adder
Accumulator
Chainout adder
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Operational Modes
The Quartus Prime software provides the following design templates for you to implement DSP blocks in
Arria 10 devices.
Table 3-6: DSP Design Templates Available in Arria 10 Devices
Operational Mode
Available Design Templates
18 x 18 Independent Multiplier Mode
Single Multiplier with Preadder and Coefficient
27 x 27 Independent Multiplier Mode
• M27x27 with Dynamic Negate
• M27x27 with Preadder and Coefficient
• M27x27 with Input Cascade, Output Chaining,
Accumulator, Double Accumulator and Preload Constant
Multiplier Adder Sum Mode
• M18x19_sumof2 with Dynamic Sub and Dynamic Negate
• M18x19_sumof2 with Preadder and Coefficient
• M18x19_sumof2 with Input Cascade, Output Chaining,
Accumulator, Double Accumulator and Preload Constant
18 x 19 Multiplication Summed with 36- • M18x19_plus36 with Dynamic Sub and Dynamic Negate
Bit Input Mode
• M18x19_plus36 with Input Cascade, Output Chaining,
Accumulator, Double Accumulato and Preload Constant
18-bit Systolic FIR Mode
• M18x19_systolic with Preadder and Coefficient
• M18x19_systolic with Input Cascade, Output Chaining,
Accumulator, Double Accumulator and Preload Constant
You can get the design templates using the following steps:
1. In Quartus Prime software, open a new Verilog HDL or VHDL file.
2. From Edit tab, click on Insert Template.
3. From the Insert Template window prompt, you may click on Verilog HDL or VHDL depending on
your preferred design language.
4. Click on Full Designs to expand the options.
5. From the options, click on Arithmetic -> DSP Features -> DSP Features for 20-nm Device.
6. Choose the design template that match your system requirement and click Insert to append the design
template to a new .v or .vhd file.
Operational Modes
The Quartus Prime software includes IP cores that you can use to control the operation mode of the
multipliers. After entering the parameter settings with the IP Catalog, the Quartus Prime software
automatically configures the variable precision DSP block.
Variable-precision DSP block can also be implemented using DSP Builder Advanced Blockset and
OpenCL™.
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Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic
3-9
Table 3-7: Operational Modes
Fixed-Point Arithmetic
Floating-Point Arithmetic
Altera provides two methods for implementing
various modes of the Arria 10 variable precision
DSP block in a design—using the Quartus Prime
DSP IP core and HDL inferring.
Altera provides one method for implementing
various modes of the Arria 10 variable precision
DSP block in a design—using the Quartus Prime
DSP IP core.
The following Quartus Prime IP cores are
supported for the Arria 10 variable precision DSP
blocks in the fixed-point arithmetic implementa‐
tion:
The following Quartus Prime IP core is supported
for the Arria 10 variable precision DSP blocks in the
floating-point arithmetic implementation:
•
•
•
•
LPM_MULT
ALTERA_MULT_ADD
ALTMULT_COMPLEX
Arria 10 Native Fixed Point DSP IP core
• ALTERA_FP_FUNCTIONS
• Arria 10 Native Floating Point DSP IP core
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Integer Arithmetic Megafunctions User Guide
Floating-Point Megafunctions User Guide - ALTERA_FP_FUNCTIONS IP Core
Quartus Prime Software Help
Arria 10 Native Fixed Point DSP IP User Guide
Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic
When you enable input register for the pre-adder feature, these input registers must have the same clock
setting.
The input cascade support is only available for 18-bit mode when you enable the pre-adder feature.
In both 18-bit and 27-bit modes, you can use the coefficient feature and pre-adder feature independently.
When internal coefficient feature is enabled in 18-bit modes, you must enable both top and bottom
coefficient.
When pre-adder feature is enabled in 18-bit modes, you must enable both top and bottom pre-adder.
Accumulator for Fixed-Point Arithmetic
The accumulator in the Arria 10 devices supports double accumulation by enabling the 64-bit double
accumulation registers located between the output register bank and the accumulator.
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Chainout Adder
Chainout Adder
Table 3-8: Chainout Adder
Fixed-Point Arithmetic
Floating-Point Arithmetic
You can use the output chaining path to add results You can use the output chaining path to add results
from another DSP block.
from another DSP block.
Support for certain operation modes:
• Multiply-add or multiply-subtract mode
• Vector one mode
• Vector two mode
Block Architecture
The Arria 10 variable precision DSP block consists of the following elements:
Table 3-9: Block Architecture
DSP Implementation
Block architecture
Fixed-Point Arithmetic
•
•
•
•
•
•
•
Input register bank
Pipeline register
Pre-adder
Internal coefficient
Multipliers
Adder
Accumulator and chainout
adder
• Systolic registers
• Double accumulation
register
• Output register bank
Floating-Point Arithmetic
•
•
•
•
•
•
Input register bank
Pipeline register
Multipliers
Adder
Accumulator and chainout adder
Output register bank
If the variable precision DSP block is not configured in fixed-point arithmetic systolic FIR mode, both
systolic registers are bypassed.
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Block Architecture
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Figure 3-1: Variable Precision DSP Block Architecture in 18 x 19 Mode for Fixed-Point Arithmetic in
Arria 10 Devices
CLK[2..0]
scanin
chainin[63..0]
ENA[2..0]
When enabled, systolic registers are clocked with the
same clock source as the output register bank.
ACLR[1..0]
LOADCONST
ACCUMULATE
NEGATE
SUB
dataa_y0[18..0]
COEFSELA[2..0]
Pipleine Register
dataa_x0[17..0]
+/Input Register Bank
dataa_z0[17..0]
Systolic
Register
Multiplier
Pre-Adder
Systolic
Registers
Constant
x
+/-
Internal
Coefficient
Adder
Multiplier
+/-
+
Chainout adder/
accumulator
+/-
datab_z1[17..0]
x
datab_x1[17..0]
COEFSELB[2..0]
Output Register Bank
Pre-Adder
datab_y1[18..0]
Double
Accumulation
Register
Resulta_[63:0]
Resultb_[36:0]
Internal
Coefficient
scanout
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Block Architecture
Figure 3-2: Variable Precision DSP Block Architecture in 27 x 27 Mode for Fixed-Point Arithmetic in
Arria 10 Devices
chainin[63..0]
LOADCONST
ACCUMULATE
Constant
NEG
dataa_y0[26..0]
dataa_z0[25..0]
Input
Register
Bank
Pipeline
Register
Pre-Adder
+/-
Double
Accumulation
Register
Chainout Adder/
Accumulator
Multiplier
x
+
+/-
dataa_x0[26..0]
COEFSELA[2..0]
Output
Register
Bank
Internal
Coefficients
Result[63..0]
64
chainout[63..0]
Figure 3-3: Variable Precision DSP Block Architecture for Floating-Point Arithmetic in Arria 10 Devices
chainin[31:0]
accumulate
Pipeline
Register
dataa_x0[31:0]
dataa_y0[31:0]
dataa_z0[31:0]
Input
Register
Bank
Pipeline
Register
Adder
Output
Register
Bank
result[31:0]
Pipeline
Register
Multiplier
chainout[31:0]
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Input Register Bank
3-13
Input Register Bank
Table 3-10: Input Register Bank
Fixed-Point Arithmetic
• Data
• Dynamic control signals
• Two sets of delay registers
Floating-Point Arithmetic
• Data
• Dynamic ACCUMULATE control signal
All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier
operand can feed an input register or a multiplier directly, bypassing the input registers.
The following variable precision DSP block signals control the input registers within the variable
precision DSP block:
• CLK[2..0]
• ENA[2..0]
• ACLR[0]
In fixed-point arithmetic 18 x 19 mode, you can use the delay registers to balance the latency require‐
ments when you use both the input cascade and chainout features.
The tap-delay line feature allows you to drive the top leg of the multiplier input, dataa_y0 and datab_y1 in
fixed-point arithmetic 18 x 19 mode and dataa_y0 only in fixed-point arithmetic 27 x 27 mode, from the
general routing or cascade chain.
Two Sets of Delay Registers for Fixed-Point Arithmetic
The two delay registers along with the input cascade chain that can be used in fixed-point arithmetic
18 x 19 mode are the top delay registers and bottom delay registers. Delay registers are not supported in
18 × 19 multiplication summed with 36-bit input mode and 27 × 27 mode.
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Two Sets of Delay Registers for Fixed-Point Arithmetic
Figure 3-4: Input Register of a Variable Precision DSP Block in Fixed-Point Arithmetic 18 x 19 Mode for
Arria 10 Devices
The figures show the data registers only. Registers for the control signals are not shown.
CLK[2..0]
ENA[2..0]
scanin[18..0]
ACLR[0]
dataa_y0[18..0]
dataa_z0[17..0]
dataa_x0[17..0]
Top delay registers
datab_y1[18..0]
datab_z1[17..0]
datab_x1[17..0]
Bottom delay registers
scanout[18..0]
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Pipeline Register
3-15
Figure 3-5: Input Register of a Variable Precision DSP Block in Fixed-Point Arithmetic 27 x 27 Mode for
Arria 10 Devices
The figures show the data registers only. Registers for the control signals are not shown.
CLK[2..0]
ENA[2..0]
scanin[26..0]
ACLR[0]
dataa_y0[26..0]
dataa_z0[25..0]
dataa_x0[26..0]
scanout[26..0]
Pipeline Register
Pipeline register is used to get the maximum Fmax performance. Pipeline register can be bypassed if high
Fmax is not needed.
The following variable precision DSP block signals control the pipeline registers within the variable
precision DSP block:
• CLK[2..0]
• ENA[2..0]
• ACLR[1]
Floating-point arithmetic has 2 latency layers of pipeline registers where you can perform one of the
following:
• Bypass all latency layers of pipeline registers
• Use either one latency layers of pipeline registers
• Use both latency layers of pipeline registers
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Pre-Adder for Fixed-Point Arithmetic
Pre-Adder for Fixed-Point Arithmetic
Each variable precision DSP block has two 19-bit pre-adders. You can configure these pre-adders in the
following configurations:
• Two independent 19-bit pre-adders
• One 27-bit pre-adder
The pre-adder supports both addition and subtraction in the following input configurations:
• 18-bit (signed or unsigned) addition or subtraction for 18 x 19 mode
• 26-bit addition or subtraction for 27 x 27 mode
When both pre-adders within the same DSP block are used, they must share the same operation type
(either addition or subtraction).
Internal Coefficient for Fixed-Point Arithmetic
The Arria 10 variable precision DSP block has the flexibility of selecting the multiplicand from either the
dynamic input or the internal coefficient.
The internal coefficient can support up to eight constant coefficients for the multiplicands in 18-bit and
27-bit modes. When you enable the internal coefficient feature, COEFSELA/COEFSELB are used to control
the selection of the coefficient multiplexer.
Multipliers
A single variable precision DSP block can perform many multiplications in parallel, depending on the
data width of the multiplier and implementation.
There are two multipliers per variable precision DSP block. You can configure these two multipliers in
several operational modes:
Table 3-11: Operational Modes
Fixed-Point Arithmetic
Floating-Point Arithmetic
• One 27 x 27 multiplier
• Two 18 (signed or unsigned) x 19 (signed)
multipliers
One floating-point arithmetic single precision
multiplier
Related Information
Operational Mode Descriptions on page 3-18
Provides more information about the operational modes of the multipliers.
Adder
Depending on the operational mode, you can use the adder as follows:
• One 55-bit or 38-bit adder
• One floating-point arithmetic single precision adder
DSP Implementation
Fixed-Point Arithmetic
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Addition Using Dynamic SUB
Port
Subtraction Using Dynamic SUB Port
Yes
Yes
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Accumulator and Chainout Adder for Fixed-Point Arithmetic
3-17
DSP Implementation
Addition Using Dynamic SUB
Port
Subtraction Using Dynamic SUB Port
Floating-Point Arithmetic
No
No
Accumulator and Chainout Adder for Fixed-Point Arithmetic
The Arria 10 variable precision DSP block supports a 64-bit accumulator and a 64-bit adder for fixedpoint arithmetic.
The following signals can dynamically control the function of the accumulator:
• NEGATE
• LOADCONST
• ACCUMULATE
The accumulator supports double accumulation by enabling the 64-bit double accumulation registers
located between the output register bank and the accumulator.
The accumulator and chainout adder features are not supported in two fixed-point arithmetic
independent 18 x 19 modes.
Table 3-12: Accumulator Functions and Dynamic Control Signals
This table lists the dynamic signals settings and description for each function. In this table, X denotes a "don't
care" value.
Function
Description
NEGATE
LOADCONST
ACCUMULATE
Zeroing
Disables the
accumulator.
0
0
0
Preload
The result is always
added to the preload
value. Only one bit of
the 64-bit preload
value can be “1”. It
can be used as
rounding the DSP
result to any position
of the 64-bit result.
0
1
0
Accumulation
Adds the current
result to the previous
accumulate result.
0
X
1
Decimation +
Accumulate
This function takes
the current result,
converts it into two’s
complement, and
adds it to the
previous result.
1
X
1
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Systolic Registers for Fixed-Point Arithmetic
Function
Decimation +
Chainout Adder
Description
NEGATE
LOADCONST
ACCUMULATE
This function takes
the current result,
converts it into two’s
complement, and
adds it to the output
of previous DSP
block.
1
0
0
Systolic Registers for Fixed-Point Arithmetic
There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not
configured in fixed-point arithmetic systolic FIR mode, both systolic registers are bypassed.
The first set of systolic registers consists of 18-bit and 19-bit registers that are used to register the 18-bit
and 19-bit inputs of the upper multiplier, respectively.
The second set of systolic registers are used to delay the chainin input from the previous variable precision
DSP block.
You must clock all the systolic registers with the same clock source as the output register. Output registers
must be turned on.
Double Accumulation Register for Fixed-Point Arithmetic
The double accumulation register is an extra register in the feedback path of the accumulator. Enabling
the double accumulation register will cause an extra clock cycle delay in the feedback path of the
accumulator.
This register has the same CLK, ENA, and ACLR settings as the output register bank.
By enabling this register, you can have two accumulator channels using the same number of variable
precision DSP block. This is useful when processing interleaved complex data (I, Q).
Output Register Bank
The positive edge of the clock signal triggers the 74-bit bypassable output register bank and is cleared after
power up.
The following variable precision DSP block signals control the output register per variable precision DSP
block:
• CLK[2..0]
• ENA[2..0]
• ACLR[1]
Operational Mode Descriptions
This section describes how you can configure an Arria 10 variable precision DSP block to efficiently
support the fixed-point arithmetic and floating-point arithmetic operational modes.
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Operational Modes for Fixed-Point Arithmetic
3-19
Table 3-13: Operational Modes
Fixed-Point Arithmetic
•
•
•
•
Independent multiplier mode
Multiplier adder sum mode
Independent complex multiplier
18 x 18 multiplication summed with 36-Bit input
mode
• Systolic FIR mode
Floating-Point Arithmetic
•
•
•
•
•
•
•
•
Multiplication mode
Adder or subtract mode
Multiply-add or multiply-subtract mode
Multiply accumulate mode
Vector one mode
Vector two mode
Direct vector dot product
Complex multiplication
Operational Modes for Fixed-Point Arithmetic
Independent Multiplier Mode
In independent input and output multiplier mode, the variable precision DSP blocks perform individual
multiplication operations for general purpose multipliers.
Configuration
Multipliers per Block
18 (signed) x 19 (signed)
2
18 (unsigned) x 18 (unsigned)
2
27 (signed or unsigned) x 27 (signed or unsigned)
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18 x 18 or 18 x 19 Independent Multiplier
18 x 18 or 18 x 19 Independent Multiplier
Figure 3-6: Two 18 x 18 or 18 x 19 Independent Multiplier per Variable Precision DSP Block for Arria 10
Devices
In this figure, the variables are defined as follows:
• n = 19 and m = 37 for 18 x 19 operand
• n = 18 and m = 36 for 18 x 18 operand
Variable-Precision DSP Block
Multiplier
n
data_b1[(n-1)..0]
m
x
[(m-1)..0]
18
Output Register Bank
n
data_b0[(n-1)..0]
Pipeline Register
Input Register Bank
data_a1[17..0]
Multiplier
m
x
[(m-1)..0]
18
data_a0[17..0]
27 x 27 Independent Multiplier
Figure 3-7: One 27 x 27 Independent Multiplier Mode per Variable Precision DSP Block for Arria 10
Devices
In this mode, the result can be up to 64 bits when combined with a chainout adder or accumulator.
Variable-Precision DSP Block
Multiplier
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x
Output Register Bank
Pipeline Register
27
dataa_a0[26..0]
Input Register Bank
27
dataa_b0[26..0]
54
Result[53..0]
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Independent Complex Multiplier
3-21
Independent Complex Multiplier
The Arria 10 devices support the 18 x 19 complex multiplier mode using two fixed-point arithmetic
multiplier adder sum mode.
Figure 3-8: Sample of Complex Multiplication Equation
The imaginary part [(a × d) + (b × c)] is implemented in the first variable-precision DSP block, while the
real part [(a × c) - (b × d)] is implemented in the second variable-precision DSP block.
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18 x 19 Complex Multiplier
18 x 19 Complex Multiplier
Figure 3-9: One 18 x 19 Complex Multiplier with Two Variable Precision DSP Blocks for Arria 10 Devices
Variable-Precision DSP Block 1
Multiplier
19
c[18..0]
x
Adder
Pipeline Register
19
d[18..0]
Input Register Bank
b[17..0]
18
Multiplier
+
Output Register Bank
18
38
Imaginary Part
(ad+bc)
x
a[17..0]
Variable-Precision DSP Block 2
Multiplier
19
d[18..0]
x
Adder
18
Pipeline Register
c[18..0]
Input Register Bank
19
Multiplier
-
Output Register Bank
18
b[17..0]
38
Real Part
(ac-bd)
x
a[17..0]
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Multiplier Adder Sum Mode
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Multiplier Adder Sum Mode
Figure 3-10: One Sum of Two 18 x 19 Multipliers with One Variable Precision DSP Block for Arria 10
Devices
Variable-Precision DSP Block
SUB_COMPLEX
Multiplier
19
dataa_y0[18..0]
x
18
+/Multiplier
datab_y1[18..0]
38
Output Register Bank
Pipeline Register
19
Input Register Bank
dataa_x0[17..0]
Adder
Result[37..0]
x
18
datab_x1[17..0]
18 x 19 Multiplication Summed with 36-Bit Input Mode
Arria 10 variable precision DSP blocks support one 18 x 19 multiplication summed to a 36-bit input.
Use the upper multiplier to provide the input for an 18 x 19 multiplication, while the bottom multiplier is
bypassed. The datab_y1[17..0] and datab_y1[35..18] signals are concatenated to produce a 36-bit
input.
Figure 3-11: One 18 x 19 Multiplication Summed with 36-Bit Input Mode for Arria 10 Devices
Variable-Precision DSP Block
SUB_COMPLEX
Multiplier
19
x
+/-
Output Register Bank
18
datab_y1[35..18]
Pipeline Register
18
dataa_x0[17..0]
Input Register Bank
dataa_y0[17..0]
37
Result[37..0]
18
datab_y1[17..0]
Adder
Systolic FIR Mode
The basic structure of a FIR filter consists of a series of multiplications followed by an addition.
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Mapping Systolic Mode User View to Variable Precision Block...
Figure 3-12: Basic FIR Filter Equation
Depending on the number of taps and the input sizes, the delay through chaining a high number of
adders can become quite large. To overcome the delay performance issue, the systolic form is used with
additional delay elements placed per tap to increase the performance at the cost of increased latency.
Figure 3-13: Systolic FIR Filter Equivalent Circuit
y [n ]
w 2[ n ]
w 1[ n ]
c1
c2
w k[ n ]
w k −1 [ n ]
c k −1
ck
x[n ]
Arria 10 variable precision DSP blocks support the following systolic FIR structures:
• 18-bit
• 27-bit
In systolic FIR mode, the input of the multiplier can come from four different sets of sources:
•
•
•
•
Two dynamic inputs
One dynamic input and one coefficient input
One coefficient input and one pre-adder output
One dynamic input and one pre-adder output
Mapping Systolic Mode User View to Variable Precision Block Architecture View
The following figure shows that the user view of the systolic FIR filter (a) can be implemented using the
Arria 10 variable precision DSP blocks (d) by retiming the register and restructuring the adder. Register B
can be retimed into systolic registers at the chainin, dataa_y0 and dataa_x0 input paths as shown in (b).
The end result of the register retiming is shown in (c). The summation of two multiplier results by
restructuring the inputs and location of the adder are added to the chainin input by the chainout adder as
shown in (d).
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18-Bit Systolic FIR Mode
Figure 3-14: Mapping Systolic Mode User View to Variable Precision Block Architecture View
(a) Systolic FIR Filter
User View
x[n]
dataa_y0 x[n]
w1[n]
dataa_x0 c1
c1
x[n-2]
(b) Variable Precision Block
Architecture View (Before Retiming)
datab_y1 x[n-2]
w2[n]
datab_x1 c2
c2
w1[n]
Adder
dataa_y0 x[n-4]
c4
datab_x1 c2
w3[n]
First DSP Block
Register B
datab_y1 x[n-6]
datab_x1 c4
datab_y1 x[n-2]
datab_x1 c2
Multiplier
w2[n]
Multiplier
Result
Systolic
Registers
Register B
dataa_y0 x[n-4]
First DSP Block
Result
Retiming
Chainin from
Previous DSP Block
Systolic
Registers
Systolic
Register
Register B
dataa_y0 x[n-4]
w3[n]
Chainout
Adder
dataa_x0 c3
Adder
Output
Register A Register
Bank
Output
Register
Bank
Register A
Register A
y[n]
Adder
w1[n]
Chainin from
Previous DSP Block
Chainout
Adder
dataa_x0 c3
dataa_x0 c1
Multiplier
Chainin from
Previous DSP Block
Register B
w4[n]
Result
dataa_y0 x[n]
Multiplier
w2[n]
datab_y1 x[n-2]
Output
Register A Register
Bank
First DSP Block
(d) Variable Precision Block
Architecture View (Adder Restructured)
w1[n]
dataa_x0 c1
Multiplier
w3[n]
c3
x[n-6]
dataa_y0 x[n]
Multiplier
w2[n]
Register A
x[n-4]
(c) Variable Precision Block
Architecture View (After Retiming)
Systolic
Register
w3[n]
dataa_x0 c3
Chainout
Adder
w4[n]
datab_y1 x[n-6]
Output
Register C Register
Bank
Result
datab_x1 c4
y[n]
Second DSP Block
Second DSP Block
w4[n]
datab_y1 x[n-6]
Output
Register C Register
Bank
Result
y[n]
datab_x1 c4
Second DSP Block
w4[n]
Adder
Output
Register C Register
Bank
Result
y[n]
18-Bit Systolic FIR Mode
In 18-bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby giving 7 bits of
overhead when using an 18 x 19 operation mode, resulting 37-bit result. This allows a total sixteen 18 x 19
multipliers or eight Arria 10 variable precision DSP blocks to be cascaded as systolic FIR structure.
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27-Bit Systolic FIR Mode
Figure 3-15: 18-Bit Systolic FIR Mode for Arria 10 Devices
chainin[43..0]
44
COEFSELA[2..0]
datab_y1[17..0]
datab_z1[17..0]
datab_x1[17..0]
COEFSELB[2..0]
Systolic
Registers
18
x
+/-
3
Internal
Coefficient
Adder
Multiplier
Pre-Adder
18
18
+/-
+
Chainout adder or
accumulator
Output Register Bank
dataa_x0[17..0]
+/-
18
Pipeline Register
dataa_z0[17..0]
18
Input Register Bank
dataa_y0[17..0]
Systolic
Register
Multiplier
Pre-Adder
When enabled, systolic registers are clocked with the
same clock source as the output register bank.
x
44
18
Result[43..0]
3
Internal
Coefficient
18-bit Systolic FIR
44
chainout[43..0]
27-Bit Systolic FIR Mode
In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation,
providing 10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of eleven 27 x
27 multipliers or eleven Arria 10 variable precision DSP blocks to be cascaded as systolic FIR structure.
The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block. Systolic
registers are not required in this mode.
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Operational Modes for Floating-Point Arithmetic
Figure 3-16: 27-Bit Systolic FIR Mode for Arria 10 Devices
chainin[63..0]
64
Multiplier
Pre-Adder
COEFSELA[2..0]
27
3
+/27
x
+/-
Internal
Coefficient
Adder
+
Chainout adder or
accumulator
Output Register Bank
dataa_x0[26..0]
26
Pipeline Register
dataa_z0[25..0]
26
Input Register Bank
dataa_y0[25..0]
27-bit Systolic FIR
64
chainout[63..0]
Operational Modes for Floating-Point Arithmetic
Single Floating-Point Arithmetic Functions
One floating-point arithmetic DSP can perform the following:
• Multiplication mode
• Adder or subtract mode
• Multiply accumulate mode
Multiplication Mode
This mode allows you to apply basic floating-point multiplication (y*z).
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Adder or Subtract Mode
Figure 3-17: Multiplication Mode for Arria 10 Devices
chainin[31:0]
accumulate
dataa_x0[31:0]
dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Bank
Adder
Output
Register
Bank
Pipeline
Register
Multiplier Bank
dataa_z0[31:0]
result[31:0]
chainout[31:0]
Adder or Subtract Mode
This mode allows you to apply basic floating-point addition (x+y) or basic floating-point subtraction
(x-y).
Figure 3-18: Adder or Subtract Mode for Arria 10 Devices
chainin[31:0]
accumulate
dataa_x0[31:0]
dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
dataa_z0[31:0]
Pipeline
Register
Bank
Pipeline
Register
Multiplier Bank
Adder
Output
Register
Bank
result[31:0]
chainout[31:0]
Multiply Accumulate Mode
This mode performs floating-point multiplication followed by floating-point addition with the previous
multiplication result { ((y*z) + acc) or ((y*z) - acc) }
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Multiple Floating-Point Arithmetic Functions
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Figure 3-19: Multiply Accumulate Mode for Arria 10 Devices
chainin[31:0]
accumulate
dataa_x0[31:0]
dataa_y0[31:0]
dataa_z0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Bank
Adder
Pipeline
Register
Multiplier Bank
Output
Register
Bank
result[31:0]
chainout[31:0]
Multiple Floating-Point Arithmetic Functions
Two or more floating-point arithmetic DSP can perform the following:
• Multiply-add or multiply-subtract mode which uses single floating-point arithmetic DSP if the chainin
parameter is turn off
• Vector one mode
• Vector two mode
• Direct vector dot product
• Complex multiplication
Multiply-Add or Multiply-Subtract Mode
This mode performs floating-point multiplication followed by floating-point addition or floating-point
subtraction { ((y*z) + x) or ((y*z) - x) }. The chainin parameter allows you to enable a multiple-chain
mode.
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Vector One Mode
Figure 3-20: Multiply-Add or Multiply-Subtract Mode for Arria 10 Devices
chainin[31:0]
accumulate
dataa_x0[31:0]
dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Bank
Adder
Output
Register
Bank
result[31:0]
Pipeline
Register
Multiplier Bank
dataa_z0[31:0]
chainout[31:0]
Vector One Mode
This mode performs floating-point multiplication followed by floating-point addition with the chainin
input from the previous variable DSP Block. Input x is directly fed into chainout.
(result = y*z + chainin , where chainout = x)
Figure 3-21: Vector One Mode for Arria 10 Devices
chainin[31:0]
accumulate
dataa_x0[31:0]
dataa_y0[31:0]
dataa_z0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Bank
Adder
Output
Register
Bank
Pipeline
Register
Multiplier Bank
result[31:0]
chainout[31:0]
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Vector Two Mode
3-31
Vector Two Mode
This mode performs floating-point multiplication where the multiplication result is directly fed to
chainout. The chainin input from the previous variable DSP Block is then added to input x as the output
result. (result = x + chainin, where chainout = y*z)
Figure 3-22: Vector Two Mode for Arria 10 Devices
chainin[31:0]
accumulate
dataa_x0[31:0]
dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
dataa_z0[31:0]
Pipeline
Register
Bank
Adder
Output
Register
Bank
result[31:0]
Pipeline
Register
Multiplier Bank
chainout[31:0]
Direct Vector Dot Product
In the following figure, the direct vector dot product is implemented by several DSP blocks by setting the
following DSP modes:
• Multiply-add and subtract mode with chainin parameter turned on
• Vector one
• Vector two
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Complex Multiplication
Figure 3-23: Direct Vector Dot Product
chainin[31:0]
accumulate
dataa_x0[31:0]
J dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Vector One
Pipeline
Register
Bank
Multiplier
Pipeline
Register
Bank
Adder
Pipeline
Register
Bank
Adder
chainout[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Output
Register
Bank
Pipeline
Register
Multiplier Bank
E dataa_z0[31:0]
Vector One
result[31:0] EF + GH
chainout[31:0]
chainin[31:0]
accumulate
D dataa_y0[31:0]
Adder
result[31:0]
chainin[31:0]
accumulate
AB + CD dataa_x0[31:0]
Pipeline
Register
Bank
Output
Register
Bank
Pipeline
Register
Bank
Vector Two
F dataa_y0[31:0]
Adder
result[31:0] IJ +KL
chainout[31:0]
Input
Register
Bank
G dataa_z0[31:0]
EF + GH dataa_x0[31:0]
Pipeline
Register
Bank
Output
Register
Bank
chainin[31:0]
accumulate
H dataa_y0[31:0]
Adder
Pipeline
Register
Multiplier Bank
I dataa_z0[31:0]
AB + CD + EF + GH dataa_x0[31:0]
Pipeline
Register
Bank
Pipeline
Register
Bank
Input
Register
Bank
C dataa_z0[31:0]
Multiplier
Output
Register
Bank
result[31:0] AB + CD + EF + GH
Output
Register
Bank
result[31:0] AB + CD
Pipeline
Register
Bank
Vector Two
chainout[31:0]
chainin[31:0]
accumulate
dataa_x0[31:0]
B dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Multiplier Bank
A dataa_z0[31:0]
Multi-Chain
chainout[31:0]
Complex Multiplication
The Arria 10 devices support the floating-point arithmetic single precision complex multiplier using four
Arria 10 variable-precision DSP blocks.
Figure 3-24: Sample of Complex Multiplication Equation
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Complex Multiplication
3-33
The imaginary part [(a × d) + (b × c)] is implemented in the first two variable-precision DSP blocks, while
the real part [(a × c) - (b × d)] is implemented in the second variable-precision DSP block.
Figure 3-25: Complex Multiplication with Result Real
chainin[31:0]
accumulate
dataa_x0[31:0]
a dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Bank
Adder
Pipeline
Register
Bank
Subtract
Output
Register
Bank
Pipeline
Register
Multiplier Bank
c dataa_z0[31:0]
result[31:0]
Multiplication Mode
chainout[31:0]
chainin[31:0]
accumulate
dataa_x0[31:0]
b dataa_y0[31:0]
d dataa_z0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Output
Register
Bank
result[31:0] Result Real
Pipeline
Register
Multiplier Bank
Multiply-Subtract Mode
chainout[31:0]
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Document Revision History
Figure 3-26: Complex Multiplication with Imaginary Result
chainin[31:0]
accumulate
dataa_x0[31:0]
a dataa_y0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Bank
Adder
Output
Register
Bank
Pipeline
Register
Multiplier Bank
d dataa_z0[31:0]
Multiplication Mode
result[31:0]
chainout[31:0]
chainin[31:0]
accumulate
dataa_x0[31:0]
b dataa_y0[31:0]
c dataa_z0[31:0]
Pipeline
Register
Bank
Input
Register
Bank
Pipeline
Register
Bank
Adder
Output
Register
Bank
result[31:0] Result Imaginary
Pipeline
Register
Multiplier Bank
Multiply-Add Mode
chainout[31:0]
Document Revision History
Date
December 2015
Altera Corporation
Version
2015.11.14
Changes
• Corrected the number of DSP blocks for Arria 10 GX 660 from 1688
to 1687 in the table listing floating-point arithmetic resources.
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Document Revision History
Date
Version
3-35
Changes
November 2015
2015.11.02
• Update resource count for Arria 10 GX 320, GX 480, GX 660, SX 320,
SX 480, a SX 660 devices in Number of Multipliers in Arria 10
Devices table.
• Updated the Input Register Bank table to specify input register bank
for dynamic control signal in floating-point arithmetic is only
applicable for Dynamic ACCUMULATE control signal.
• Clarified that 18 x19 systolic FIR mode, there are 7-bits overhead and
37-bits result.
• Updated the number of supported cascaded DSP blocks for 18-bit
and 27-bit systolic FIR modes.
• Changed instances of Quartus II to Quartus Prime
May 2015
2015.05.04
• Update Chainin and Chainout support for all Floating Point modes in
Supported Combinations of Operational Modes and Features for
Variable Precision DSP Block in Arria 10 Devices table.
• Added steps to retrieve design templates for Independent Multiplier
Mode, Multiplier Adder Sum Mode, and Systolic FIR Mode.
• Added Arria 10 Native Floating Point DSP IP core in Operational
Modes table.
January 2015
2015.01.23
• Added information for primitive DSP.
• Update Supported Combinations of Operational Modes and
Features for Variable Precision DSP Block in Arria 10 Devices table
with the column title Supported Operation Instance.
• Update resource for Single Precision Floating Point Adders in
Number of Multipliers in Arria 10 Devices table.
• Removed double accumulation registers are set statically in the
programming file statement in Accumulator for Fixed-Point
Arithmetic section.
• Added ALTERA_FP_FUNCTIONS in the list of Quartus II DSP IP
for floating-point arithmetic.
• Added clarification on operational modes supported for delay
registers in fixed-point arithmetic.
• Added clarification that both top and bottom internal coefficient and
pre-adder must be enabled if these features are being used.
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Document Revision History
Date
Version
August 2014
2014.08.18
• Added floating-point arithmetic.
• Added Dynamic ACCUMULATE, Dynamic LOADCONST,
Dynamic SUB, Dynamic NEGATE to variable precision DSP blocks
operational modes.
• Added top delay registers and bottom delay registers along the input
cascade chain.
• Added the variable precision DSP block signals that control the
piepeline registers within the variable precision DSP block.
• Added condition that when both pre-adders within the same DSP
block are used, they must share the same operation type (either
addition or subtraction).
• Updated 55-bit adder.
• Added 38-bit adder.
• Updated two 18 x 19 modes—where the adder is bypassed.
• Updated Decimation to Decimation + Accumulate.
• Added Decimation + Chainout Adder for accumulator functions and
dynamic control signals.
• Added 27 (signed or unsigned) x 27 (signed or unsigned) configura‐
tion with 1 multiplier per block.
• Removed the chainout adder or accumulator from one sum of two
18 x 19 multipliers with one variable precision DSP block and one 18
x 18 multiplication summed with 36-Bit input mode block diagram.
• Updated the basic FIR filter equation.
• Added mapping systolic mode user view to variable precision block
architecture view.
• Added systolic registers are not required in 27-bit systolic FIR mode.
December 2013
2013.12.02
Initial release.
Altera Corporation
Changes
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Clock Networks and PLLs in Arria 10 Devices
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A10-CLKPLL
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This chapter describes the advanced features of hierarchical clock networks and phase-locked loops
(PLLs) in Arria 10 devices. The Quartus Prime software enables the PLLs and their features without
external devices.
Related Information
Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
Clock Networks
The Arria 10 devices contain the following clock networks that are organized into a hierarchical structure:
• Global clock (GCLK) networks
• Regional clock (RCLK) networks
• Periphery clock (PCLK) networks
• Small periphery clock (SPCLK) networks
• Large periphery clock (LPCLK) networks
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trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Clock Resources in Arria 10 Devices
Clock Resources in Arria 10 Devices
Table 4-1: Clock Resources in Arria 10 Devices
Clock Input Pins
Device
Number of
Resources Available
•
•
•
•
10AS016
10AS022
10AX016
10AX022
• HSSI: 8 singleended
• I/O: 32 singleended or 16
differential
•
•
•
•
10AS027
10AS032
10AX027
10AX032
• HSSI: 16
single-ended
• I/O: 32
single-ended
or 16
differential
• 10AS048
• 10AX048
• HSSI: 24
single-ended
• I/O: 48
single-ended
or 24
differential
•
•
•
•
10AS057
10AS066
10AX057
10AX066
• HSSI: 32
single-ended
• I/O: 64
single-ended
or 32
differential
•
•
•
•
10AT090
10AT115
10AX090
10AX115
• HSSI: 64
single-ended
• I/O: 64
single-ended
or 32
differential
Altera Corporation
Source of Clock Resource
For high-speed serial interface (HSSI):
REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T][p,n]
pins
For I/O: CLK_[2,3][A..L]_[0,1][p,n] pins
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GCLK Networks
Device
Number of
Resources Available
All
32
Source of Clock Resource
• Physical medium attachment (PMA) and physical
coding sublayer (PCS) TX and RX clocks per channel
• PMA and PCS TX and RX divide clocks per channel
• Hard IP core clock output signals
• DLL clock outputs
• Fractional PLL (fPLL) and I/O PLL C counter outputs
• fPLL and I/O PLL M counter outputs for feedback
• REFCLK and clock input pins
• Core signals
• Phase aligner counter outputs
RCLK Networks
Device
•
•
•
•
•
•
•
•
Number of
Resources Available
10AS016
10AS022
10AS027
10AS032
10AX016
10AX022
10AX027
10AX032
8
• 10AS048
• 10AX048
12
•
•
•
•
•
•
•
•
16
10AS057
10AS066
10AX057
10AX066
10AT090
10AT115
10AX090
10AX115
Clock Networks and PLLs in Arria 10 Devices
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Source of Clock Resource
• Physical medium attachment (PMA) and physical
coding sublayer (PCS) TX and RX clocks per channel
• PMA and PCS TX and RX divide clocks per channel
• Hard IP core clock output signals
• DLL clock outputs
• fPLL and I/O PLL C counter outputs
• fPLL and I/O PLL M counter outputs for feedback
• REFCLK and clock input pins
• Core signals
• Phase aligner counter outputs
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Clock Resources in Arria 10 Devices
SPCLK Networks
Device
•
•
•
•
•
•
•
•
10AS016
10AS022
10AX016
10AX022
10AS027
10AS032
10AX027
10AX032
• 10AS048
• 10AX048
Number of
Resources Available
For HSSI:
144
216
•
•
•
•
10AS057
10AS066
10AX057
10AX066
288
•
•
•
•
10AT090
10AT115
10AX090
10AX115
384
Altera Corporation
Source of Clock Resource
• Physical medium attachment (PMA) and physical
coding sublayer (PCS) TX and RX clocks per channel
• PMA and PCS TX and RX divide clocks per channel
• Hard IP core clock output signals
• DLL clock outputs
• fPLL C and M counter outputs
• REFCLK and clock input pins
• Core signals
For I/O:
•
•
•
•
•
DPA outputs (LVDS I/O only)
I/O PLL C and M counter outputs
Clock input pins
Core signals
Phase aligner counter outputs
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Hierarchical Clock Networks
4-5
LPCLK Networks
Device
•
•
•
•
•
•
•
•
Number of
Resources Available
10AS016
10AS022
10AX016
10AX022
10AS027
10AS032
10AX027
10AX032
• 10AS048
• 10AX048
Source of Clock Resource
For HSSI:
24
36
•
•
•
•
10AS057
10AS066
10AX057
10AX066
48
•
•
•
•
10AT090
10AT115
10AX090
10AX115
64
• Physical medium attachment (PMA) and physical
coding sublayer (PCS) TX and RX clocks per channel
• PMA and PCS TX and RX divide clocks per channel
• Hard IP core clock output signals
• DLL clock outputs
• fPLL C and M counter outputs
• REFCLK and clock input pins
• Core signals
For I/O:
•
•
•
•
•
DPA outputs (LVDS I/O only)
I/O PLL C and M counter outputs
Clock input pins
Core signals
Phase aligner counter outputs
For more information about the clock input pins connections, refer to the pin connection guidelines.
Related Information
Arria 10 Device Family Pin Connection Guidelines
Hierarchical Clock Networks
Arria 10 devices cover 3 levels of clock networks hierarchy. The sequence of the hierarchy is as follows:
1. GCLK, RCLK, PCLK, and GCLK and RCLK feedback clocks
2. Section clock (SCLK)
3. Row clocks
Each HSSI and I/O column contains clock drivers to drive down shared buses to the respective GCLK,
RCLK, and PCLK clock networks.
Arria 10 clock networks (GCLK, RCLK, and PCLK) are routed through SCLK before each clock is
connected to the clock routing for each HSSI or I/O bank. The settings for SCLK are transparent. The
Quartus Prime software automatically routes the SCLK based on the GCLK, RCLK, and PCLK networks.
Each SCLK spine has a consistent height, matching that of HSSI and I/O banks. The number of SCLK
spine in a device depends on the number of HSSI and I/O banks.
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Hierarchical Clock Networks
Figure 4-1: SCLK Spine Regions for Arria 10 Devices
Bank
SCLK Spine Region
HSSI
Column
I/O
Column
I/O
Column
HSSI
Column
Arria 10 devices provide a maximum of 33 SCLK networks in the SCLK spine region. The SCLK networks
can drive six row clocks in each row clock region. The row clocks are the clock resources to the core
functional blocks, PLLs, and I/O interfaces, and HSSI interfaces of the device. Six unique signals can be
routed into each row clock region. The connectivity pattern of the multiplexers that drive each SCLK
limits the clock sources to the SCLK spine region. Each SCLK can select the clock resources from GCLK,
RCLK, LPCLK, or SPCLK lines.
The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or GCLK and RCLK feedback
clock networks in each SCLK spine region. The GCLK, RCLK, PCLK, and GCLK and RCLK feedback
clocks share the same SCLK routing resources. To ensure successful design fitting in the Quartus Prime
software, the total number of clock resources must not exceed the SCLK limits in each SCLK spine region.
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Types of Clock Networks
Figure 4-2: Hierarchical Clock Networks in SCLK Spine
First level
Feedback clock output from the
PLL that drives into the SCLKs.
GCLK/GCLK feedback
RCLK/RCLK feedback
The maximum number of
resources available for the
clock networks that can drive
the SCLKs in each spine
region in the largest device.
SPCLK
LPCLK
Second level
Third level
32
8
24
8
SCLK
33
6
Row clock
Types of Clock Networks
Global Clock Networks
GCLK networks serve as low-skew clock sources for functional blocks, such as adaptive logic modules
(ALMs), digital signal processing (DSP), embedded memory, and PLLs. Arria 10 I/O elements (IOEs) and
internal logic can also drive GCLKs to create internally-generated global clocks and other high fan-out
control signals, such as synchronous or asynchronous clear and clock enable signals.
Arria 10 devices provide GCLKs that can drive throughout the device. GCLKs cover every SCLK spine
region in the device. Each GCLK is accessible through the direction as indicated in the Symbolic GCLK
Networks diagram.
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Regional Clock Networks
Figure 4-3: Symbolic GCLK Networks in Arria 10 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device
package.
Bank
GCLK[11:8]
GCLK[27:24]
GCLK[7:0]
GCLK[23:16]
GCLK[15:12]
GCLK[31:28]
HSSI
Column
I/O
Column
I/O
Column
HSSI
Column
Regional Clock Networks
RCLK networks provide low clock insertion delay and skew for logic contained within a single RCLK
region. The Arria 10 IOEs and internal logic within a given region can also drive RCLKs to create
internally-generated regional clocks and other high fan-out signals.
Arria 10 devices provide RCLKs that can drive through the chip horizontally. RCLKs cover all the SCLK
spine regions in the same row of the device. The top and bottom HSSI and I/O banks have RCLKs that
cover 2 rows vertically. The other intermediate HSSI and I/O banks have RCLKs that cover 6 rows
vertically. The following figure shows the RCLK network coverage.
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Figure 4-4: RCLK Networks in Arria 10 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device
package.
Bank
Network Coverage for RCLK[3..0]
RCLK[3..0]
RCLK[7..4]
RCLK[11..8]
RCLK[15..12]
HSSI
Column
I/O
Column
I/O
Column
Network Coverage for RCLK[7..4]
Network Coverage for RCLK[11..8]
Network Coverage for RCLK[15..12]
HSSI
Column
Periphery Clock Networks
PCLK networks provide the lowest insertion delay and the same skew as RCLK networks.
Small Periphery Clock Networks
Each HSSI or I/O bank has 12 SPCLKs. SPCLKs cover one SCLK spine region in HSSI bank and one
SCLK spine region in I/O bank adjacent to each other in the same row.
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Periphery Clock Networks
Figure 4-5: SPCLK Networks for Arria 10 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device
package.
Bank
12
12
HSSI
Column
I/O
Column
I/O
Column
HSSI
Column
Large Periphery Clock Networks
Each HSSI or I/O bank has 2 LPCLKs. LPCLKs have larger network coverage compared to SPCLKs.
LPCLKs cover one SCLK spine region in HSSI bank and one SCLK spine region in I/O bank adjacent to
each other in the same row. Top and bottom HSSI and I/O banks have LPCLKs that cover 2 rows
vertically. The other intermediate HSSI and I/O banks have LPCLKs that cover 4 rows vertically.
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Clock Network Sources
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Figure 4-6: LPCLK Networks for Arria 10 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device
package.
Bank
2
2
2
2
HSSI
Column
4
4
2
2
I/O
Column
I/O
Column
HSSI
Column
Clock Network Sources
This section describes the clock network sources that can drive the GCLK, RCLK, and PCLK networks.
Dedicated Clock Input Pins
The sources of dedicated clock input pins are as follows:
• fPLL—REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T][p,n] from HSSI column
• I/O PLL—CLK_[2,3][A..L]_[0,1][p,n] from I/O column
You can use the dedicated clock input pins for high fan-out control signals, such as asynchronous clears,
presets, and clock enables, for protocol signals through the GCLK or RCLK networks.
The dedicated clock input pins can be either differential clocks or single-ended clocks. When you use the
dedicated clock input pins as single-ended clock inputs, only the following pins have dedicated
connections to the PLL:
• fPLL—REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T]p
• I/O PLL—CLK_[2,3][A..L]_[0,1][p,n]
The dedicated clock input pins, REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T]n, drive the fPLLs
over global or regional clock networks and do not have dedicated routing paths to the fPLLs.
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Internal Logic
Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will
not be able to fully compensate for the global or regional clock. Altera recommends using the dedicated
clock input pins for optimal performance to drive the PLLs.
Internal Logic
You can drive each GCLK and RCLK network using core routing to enable internal logic to drive a high
fan-out, low-skew signal.
DPA Outputs
Each DPA can drive the PCLK networks.
HSSI Clock Outputs
HSSI clock outputs can drive the GCLK, RCLK, and PCLK networks.
PLL Clock Outputs
The fPLL and I/O PLL clock outputs can drive all clock networks.
Clock Control Block
Every GCLK, RCLK, and PCLK network has its own clock control block. The control block provides the
following features:
• Clock source selection (dynamic selection available only for GCLKs)
• Clock power down (static or dynamic clock enable or disable available only for GCLKs and RCLKs)
Related Information
Clock Control Block (ALTCLKCTRL) IP Core User Guide
Provides more information about ALTCLKCTRL IP core and clock multiplexing schemes.
Pin Mapping in Arria 10 Devices
Table 4-2: Mapping Between the Clock Input Pins, PLL Counter Outputs, and Clock Control Block Inputs for
HSSI Column
Clock
Fed by
inclk[0]
PLL counters C0 and C2 from adjacent fPLLs.
inclk[1]
PLL counters C1 and C3 from adjacent fPLLs.
inclk[2] and inclk[3]
Any of the two dedicated clock pins on the same HSSI bank.
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GCLK Control Block
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Table 4-3: Mapping Between the Clock Input Pins, PLL Counter Outputs, and Clock Control Block Inputs for
I/O Column
One counter can only be assigned to one inclk.
Clock
Fed by
inclk[0]
CLK_[2,3][A..L]_0p or any counters from adjacent I/O PLLs.
inclk[1]
CLK_[2,3][A..L]_0n or any counters from adjacent I/O PLLs.
inclk[2]
CLK_[2,3][A..L]_1p or any counters from adjacent I/O PLLs.
inclk[3]
CLK_[2,3][A..L]_1n or any counters from adjacent I/O PLLs.
GCLK Control Block
You can select the clock source for the GCLK select block either statically or dynamically using internal
logic to drive the multiplexer-select inputs.
When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or a
combination of clock pins or PLL outputs.
Figure 4-7: GCLK Control Block for Arria 10 Devices
For the corresponding CLKSELECT[1..0]
of the HSSI column or I/O column,
refer to the Pin Mapping tables.
When the device is in user mode,
you can dynamically control the
clock select signals through internal
logic.
PLL Counter
Outputs/CLK Pins
CLKSELECT[1..0]
This multiplexer
supports user-controllable
dynamic switching
4
HSSI
Output
CLKn
Pin
The CLKn pin is not a dedicated clock
input when used as a single-ended
PLL clock input. The CLKn pin can
drive the PLL using the GCLK.
DPA
Output
Internal
Logic
2
Static Clock
Select
Enable/
Disable
GCLK
Internal
Logic
When the device is in user mode, you can only
set the clock select signals through a
configuration file (SRAM object file [.sof] or
programmer object file [.pof]) because the
signals cannot be controlled dynamically.
You can set the input clock sources and the clkena signals for the GCLK network multiplexers through
the Quartus Prime software using the ALTCLKCTRL IP core.
When selecting the clock source dynamically using the ALTCLKCTRL IP core, choose the inputs using
the CLKSELECT[0..1] signal.
Note: You can only switch dedicated clock inputs from the same I/O or HSSI bank.
Related Information
Pin Mapping in Arria 10 Devices on page 4-12
Provides the mapping between the clock input pins, PLL counter outputs, and clock control block inputs
for HSSI column and I/O column.
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RCLK Control Block
RCLK Control Block
You can only control the clock source selection for the RCLK select block statically using configuration bit
settings in the configuration file (.sof or .pof) generated by the Quartus Prime software.
Figure 4-8: RCLK Control Block for Arria 10 Devices
The CLKn pin is not a dedicated
clock input when used as a
single-ended PLL clock input. The
CLKn pin can drive the PLL using
the RCLK.
CLKp CLKn
Pin Pin
HSSI Output
PLL Counter
Outputs
DPA Output
2
Internal Logic
Static Clock Select
When the device is in user mode,
you can only set the clock select
signals through a configuration file
(.sof or .pof); they cannot be
controlled dynamically.
Enable/
Disable
Internal
Logic
RCLK
You can set the input clock sources and the clkena signals for the RCLK networks through the Quartus
Prime software using the ALTCLKCTRL IP core.
PCLK Control Block
PCLK control block drives both SPCLK and LPCLK networks.
To drive the HSSI PCLK, select the HSSI output, fPLL output, or clock input pin.
To drive the I/O PCLK, select the DPA clock output, I/O PLL output, or clock input pin.
Figure 4-9: PCLK Control Block for HSSI Column for Arria 10 Devices
CLKp Pin
CLKn Pin
HSSI Output
Fractional PLL Output
Static Clock Select
PCLK from
HSSI Column
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Clock Power Down
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Figure 4-10: PCLK Control Block for I/O Column for Arria 10 Devices
CLKp Pin
CLKn Pin
DPA Output
I/O PLL Output
Static Clock Select
PCLK from
I/O Column
You can set the input clock sources and the clkena signals for the PCLK networks through the Quartus
Prime software using the ALTCLKCTRL IP core.
Clock Power Down
You can power down the GCLK and RCLK clock networks using both static and dynamic approaches.
When a clock network is powered down, all the logic fed by the clock network is in off-state, reducing the
overall power consumption of the device. The unused GCLK, RCLK, and PCLK networks are automati‐
cally powered down through configuration bit settings in the configuration file (.sof or .pof) generated by
the Quartus Prime software.
The dynamic clock enable or disable feature allows the internal logic to control power-up or power-down
synchronously on the GCLK and RCLK networks. This feature is independent of the PLL and is applied
directly on the clock network.
Note: You cannot dynamically enable or disable GCLK or RCLK networks that drive PLLs.
Clock Enable Signals
You cannot use the clock enable and disable circuit of the clock control block if the GCLK or RCLK
output drives the input of a PLL.
Figure 4-11: clkena Implementation with Clock Enable and Disable Circuit
This figure shows the implementation of the clock enable and disable circuit of the clock control block.
The R1 and R2 bypass paths are
not available for the PLL external
clock outputs.
clkena
D
Clock Select
Multiplexer Output
Q
R1
D
Q
R2
GCLK/
RCLK/
PLL_[2,3][A..L]_CLKOUT[0..3][p,n]
The select line is statically
controlled by a bit setting in
the .sof or .pof.
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Arria 10 PLLs
The clkena signals are supported at the clock network level instead of at the PLL output counter level.
This allows you to gate off the clock even when you are not using a PLL. You can also use the clkena
signals to control the dedicated external clocks from the PLLs.
Figure 4-12: Example of clkena Signals
This figure shows a waveform example for a clock output enable. The clkena signal is synchronous to the
falling edge of the clock output.
Clock Select
Multiplexer Output
Use the clkena signals to enable or disable the
GCLK and RCLK networks or the
PLL_[2,3][A..L]_CLKOUT[0..3][p,n] pins.
clkena
AND Gate Output
with R2 Bypassed
(ena Port Registered as
Falling Edge of Input Clock)
AND Gate Output
with R2 Not Bypassed
(ena Port Registered as Double
Register with Input Clock)
Arria 10 devices have an additional metastability register that aids in asynchronous enable and disable of
the GCLK and RCLK networks. You can optionally bypass this register in the Quartus Prime software.
The PLL can remain locked, independent of the clkena signals, because the loop-related counters are not
affected. This feature is useful for applications that require a low-power or sleep mode. The clkena signal
can also disable clock outputs if the system is not tolerant of frequency overshoot during resynchroniza‐
tion.
Arria 10 PLLs
PLLs provide robust clock management and synthesis for device clock management, external system clock
management, and high-speed I/O interfaces.
The Arria 10 device family contains the following PLLs:
• fPLLs—can function as fractional PLLs or integer PLLs
• I/O PLLs—can only function as integer PLLs
The fPLLs are located adjacent to the transceiver blocks in the HSSI banks. Each HSSI bank contains two
fPLLs. You can configure each fPLL independently in conventional integer mode. In fractional mode, the
fPLL can operate with third-order delta-sigma modulation. Each fPLL has four C counter outputs and one
L counter output.
The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer
(SERDES) blocks in the I/O banks. Each I/O bank contains one I/O PLL. The I/O PLLs can operate in
conventional integer mode. Each I/O PLL has nine C counter outputs. In some specific device package,
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you can use the I/O PLLs in the I/O banks that are not bonded out in your design. These I/O PLLs must
take their reference clock source from the FPGA core or through a dedicated cascade connection from
another I/O PLLs in the same I/O column.
Arria 10 devices have up to 32 fPLLs and 16 I/O PLLs in the largest densities. Arria 10 PLLs have different
core analog structure and features support.
Table 4-4: PLL Features in Arria 10 Devices —Preliminary
Feature
Fractional PLL
I/O PLL
Integer mode
Yes
Yes
Fractional mode
Yes
—
4
9
M counter divide factors
8 to 127
4 to 160
N counter divide factors
1 to 32
1 to 80
C counter divide factors
1 to 512
1 to 512
L counter divide factors
1, 2, 4, 8
—
Dedicated external clock outputs
—
Yes
Dedicated clock input pins
Yes
Yes
External feedback input pin
—
Yes
Spread-spectrum input clock tracking (4)
Yes
Yes
Source synchronous compensation
—
Yes
Direct compensation
Yes
Yes
Normal compensation
—
Yes
Zero-delay buffer compensation
—
Yes
External feedback compensation
—
Yes
LVDS compensation
—
Yes
Feedback compensation bonding
Yes
—
Voltage-controlled oscillator (VCO) output
drives the DPA clock
—
Yes
72 ps
78.125 ps
Fixed 50% duty cycle
Yes
Yes
Yes
C output counters
Phase shift resolution (5)
Programmable duty cycle
Power down mode
(4)
(5)
Provided input clock jitter is within input jitter tolerance specifications.
The smallest phase shift is determined by the VCO period divided by four (for fPLL) or eight (for I/O PLL).
For degree increments, the Arria 10 device can shift all output frequencies in increments of at least 45° (for
I/O PLL) or 90° (for fPLL). Smaller degree increments are possible depending on the frequency and divide
parameters.
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PLL Usage
PLL Usage
fPLLs are optimized for use as transceiver transmit PLLs and for synthesizing reference clock frequencies.
You can use the fPLLs as follows:
• Reduce the number of required oscillators on the board
• Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single
reference clock source
• Compensate clock network delay
• Transmit clocking for transceivers
I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use the I/O PLLs as
follows:
• Reduce the number of required oscillators on the board
• Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single
reference clock source
• Simplify the design of external memory interfaces and high-speed LVDS interfaces
• Ease timing closure because the I/O PLLs are tightly coupled with the I/Os
• Compensate clock network delay
• Zero delay buffering
PLL Architecture
Figure 4-13: Fractional PLL High-Level Block Diagram for Arria 10 Devices
For single-ended clock inputs, only the REFCLK_GXBp pin
has a dedicated connection to the PLL. If you use the
REFCLK_GXBn pin, a global or regional clock is used.
GCLK/RCLK
Cascade Input from
Adjacent Fractional PLL
and Dedicated refclk
4
inclk0
Clock
inclk1 Switchover
Block
Lock
Circuit
÷N
PFD
pll_locked
CP
LF
VCO
÷C0
4
÷C1
÷C2
clkswitch
clkbad0
clkbad1
activeclock
÷C3
Delta Sigma
Modulator
÷M
Direct Compensation Mode
Feedback Compensation Bonding Mode
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PMA Clocks
PLL Output Multiplexer
Dedicated Clock Inputs
÷L
Casade Output to
Adjacent Fractional PLL
and ATX/CDR PLLs.
GCLKs
RCLKs
FBOUT
This FBOUT port is fed by
the M counter in the PLLs.
IQTXRXCLK
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Figure 4-14: I/O PLL High-Level Block Diagram for Arria 10 Devices
To DPA Block
For single-ended clock inputs, both the CLKp and CLKn pins
have dedicated connection to the PLL.
Dedicated Clock Inputs
4
GCLK/RCLK
locked
8
inclk0
Clock
inclk1 Switchover
Block
Cascade Input
from Adjacent I/O PLL
and Dedicated refclk
÷N
PFD
CP
LF
VCO
Casade Output
to Adjacent I/O PLL
GCLKs
RCLKs
÷C0
8
clkswitch
clkbad0
clkbad1
activeclock
÷C1
÷C2
÷C3
PLL Output Multiplexer
Lock
Circuit
÷C8
÷M
Direct Compensation Mode
Zero Delay Buffer, External Feedback Modes
LVDS Compensation Mode
Source Synchronous, Normal Modes
LVDS RX/TX Clock
LVDS RX/TX Load Enable
FBOUT
External Memory
Interface DLL
This FBOUT port is fed by
the M counter in the PLLs.
FBIN
LVDS Clock Network
GCLK/RCLK Network
PLL Cascading
Arria 10 devices support PLL-to-PLL cascading. PLL cascading synthesizes more output clock frequencies
than a single PLL.
If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting and the
destination (downstream) PLL must have a high-bandwidth setting. During cascading, the output of the
source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of
cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the
cascaded PLLs may amplify phase noise at certain frequencies.
Arria 10 devices support the following PLL-to-PLL cascading modes:
• I/O-PLL-to-I/O-PLL cascading—Upstream I/O PLL and downstream I/O PLL must be located within
the same I/O column.
• fPLL-to-fPLL cascading
• fPLL-to-ATX-PLL cascading
• fPLL-to-CMU-PLL cascading
Related Information
• Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Provides more information about I/O PLL cascading in the Quartus Prime software.
• Implementing PLL cascading, Arria 10 Transceiver PHY User Guide
Provides more information about fPLL cascading in the Quartus Prime software.
PLL Control Signals
You can use the reset signal to control PLL operation and resynchronization, and use the locked signal to
observe the status of the PLL.
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Reset
Reset
The reset signal port of the IP core for each PLL is as follows:
• fPLL—pll_powerdown
• I/O PLL—reset
The reset signal is the reset or resynchronization input for each PLL. The device input pins or internal
logic can drive these input signals.
When the reset signal is driven high, the PLL counters reset, clearing the PLL output and placing the PLL
out-of-lock. The VCO is then set back to its nominal setting. When the reset signal is driven low again,
the PLL resynchronizes to its input clock source as it re-locks.
You must assert the the reset signal every time the PLL loses lock to guarantee the correct phase relation‐
ship between the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset)
after a loss-of-lock condition using the Quartus Prime parameter editor.
You must include the reset signal if either of the following conditions is true:
• PLL reconfiguration or clock switchover is enabled in the design
• Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock
condition
Note: • If the input clock to the PLL is not toggling or is unstable after power up, assert the reset signal
after the input clock is stable and within specifications.
• For fPLL, after device power-up, you must reset the fPLL when the fPLL power-up calibration
process has completed (pll_cal_busy signal deasserts).
Locked
The locked signal port of the IP core for each PLL is as follows:
• fPLL—pll_locked
• I/O PLL—locked
The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock
has locked onto the reference clock both in phase and frequency.
Clock Feedback Modes
Clock feedback modes compensate for clock network delays to align the PLL clock input rising edge with
the rising edge of the clock output. Select the appropriate type of compensation for the timing critical
clock path in your design.
PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode
unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and
avoids expending compensation clocking resources unnecessarily.
The default clock feedback mode is direct compensation mode.
fPLLs support the following clock feedback modes:
• Direct compensation
• Feedback compensation bonding
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I/O PLLs support the following clock feedback modes:
•
•
•
•
•
•
Direct compensation
Normal compensation
Source synchronous compensation
LVDS compensation
Zero delay buffer (ZDB) compensation
External feedback (EFB) compensation
Related Information
• Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Provides more information about I/O PLL operation modes.
• PLL Feedback and Cascading Clock Network, Arria 10 Transceiver PHY User Guide
Provides more information about fPLL operation modes.
Clock Multiplication and Division
An Arria 10 PLL output frequency is related to its input reference clock source by a scale factor of
M/(N × C) in integer mode. The input clock is divided by a pre-scale factor, N, and is then multiplied by the
M feedback factor. The control loop drives the VCO to match fin × (M/N).
The Quartus Prime software automatically chooses the appropriate scale factors according to the input
frequency, multiplication, and division values entered into the Altera IOPLL IP core for I/O PLL and
Arria 10 FPLL IP core for fPLL.
Pre-Scale Counter, N and Multiply Counter, M
Each PLL has one pre-scale counter, N, and one multiply counter, M. The M and N counters do not use dutycycle control because the only purpose of these counters is to calculate frequency division.
Post-Scale Counter, C
Each output port has a unique post-scale counter, C. For multiple C counter outputs with different
frequencies, the VCO is set to the least common multiple of the output frequencies that meets its
frequency specifications. For example, if the output frequencies required from one I/O PLL are 55 MHz
and 100 MHz, the Quartus Prime software sets the VCO frequency to 1.1 GHz (the least common
multiple of 55 MHz and 100 MHz within the VCO operating frequency range). Then the post-scale
counters, C, scale down the VCO frequency for each output port.
Post-Scale Counter, L
The fPLL has an additional post-scale counter, L. The L counter synthesizes the frequency from its clock
source using the M/(N × L) scale factor. The L counter generates a differential clock pair (0 degree and 180
degree) and drives the HSSI clock network.
Delta-Sigma Modulator
The delta-sigma modulator (DSM) is used together with the M multiply counter to enable the fPLL to
operate in fractional mode. The DSM dynamically changes the M counter factor on a cycle-to-cycle basis.
The different M counter factors allow the "average" M counter factor to be a non-integer.
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Programmable Phase Shift
Fractional Mode
In fractional mode, the M counter value equals to the sum of the M feedback factor and the fractional value.
The fractional value is equal to K/2X, where K is an integer between 0 and (2X – 1), and X = 32.
Integer Mode
For a fPLL operating in integer mode, M is an integer value and DSM is disabled.
The I/O PLL can only operate in integer mode.
Related Information
• Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Provides more information about I/O PLL software support in the Quartus Prime software.
• PLLs and Clock Networks chapter, Arria 10 Transceiver PHY User Guide
Provides more information about fPLL software support in the Quartus Prime software.
Programmable Phase Shift
The programmable phase shift feature allows both fPLLs and I/O PLLs to generate output clocks with a
fixed phase offset.
The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift
increment is 1/8 (for I/O PLL) or 1/4 (for fPLL) of the VCO period. For example, if an I/O PLL operates
with a VCO frequency of 1000 MHz, phase shift steps of 125 ps are possible.
The Quartus Prime software automatically adjusts the VCO frequency according to the user-specified
phase shift values entered into the IP core.
Programmable Duty Cycle
The programmable duty cycle feature allows I/O PLLs to generate clock outputs with a variable duty cycle.
This feature is only supported by the I/O PLL post-scale counters, C. fPLLs do not support the program‐
mable duty cycle feature and only have fixed 50% duty cycle.
The I/O PLL C counter value determines the precision of the duty cycle. The precision is 50% divided by
the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty-cycle
options from 5% to 90%. If the I/O PLL is in external feedback mode, set the duty cycle for the counter
driving the fbin pin to 50%.
The Quartus Prime software automatically adjusts the VCO frequency according to the user's desired duty
cycle entered into the IP core.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise
non-overlapping clocks.
Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature
for clock redundancy or for a dual-clock domain application where a system turns to the redundant clock
if the previous clock stops running. The design can perform clock switchover automatically when the
clock is no longer toggling or based on a user control signal, clkswitch.
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Automatic Switchover
4-23
Arria 10 PLLs support the following clock switchover modes:
• Automatic switchover—The clock sense circuit monitors the current reference clock. If the current
reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.
• Manual clock switchover—Clock switchover is controlled using the clkswitch signal. When the
clkswitch signal goes from logic high to logic low, and stays low for at least three clock cycles for the
inclk being switched to, the reference clock to the PLL is switched from inclk0 to inclk1, or viceversa.
• Automatic switchover with manual override—This mode combines automatic switchover and manual
clock switchover. When the clkswitch signal goes low, it overrides the automatic clock switchover
function. As long as the clkswitch signal is low, further switchover action is blocked.
Automatic Switchover
Arria 10 PLLs support a fully configurable clock switchover capability.
Figure 4-15: Automatic Clock Switchover Circuit Block Diagram
This figure shows a block diagram of the automatic switchover circuit built into the PLL.
clkbad0
clkbad1
activeclock
Clock
Sense
Switchover
State Machine
clksw
Clock Switch
Control Logic
inclk0
inclk1
N Counter
Multiplexer
Out
clkswitch
PFD
refclk
fbclk
When the current reference clock is not present, the clock sense block automatically switches to the
backup clock for PLL reference. You can select a clock source as the backup clock by connecting it to the
inclk1 port of the PLL in your design.
The clock switchover circuit sends out three status signals—clkbad0, clkbad1, and activeclock—from
the PLL to implement a custom switchover circuit in the logic array.
In automatic switchover mode, the clkbad0 and clkbad1 signals indicate the status of the two clock
inputs. When they are asserted, the clock sense block detects that the corresponding clock input has
stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1
is greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selected as
the reference clock to the PLL. When the frequency difference between the two clock inputs is more than
20%, the activeclock signal is the only valid status signal.
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Automatic Switchover
Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current
reference clock to the PLL stops toggling. You can switch back and forth between inclk0 and inclk1 any
number of times when one of the two clocks fails and the other clock is available.
For example, in applications that require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal (clksw) that controls the multiplexer select input.
In this case, inclk1 becomes the reference clock for the PLL.
When using automatic clock switchover mode, the following requirements must be satisfied:
• Both clock inputs must be running when the FPGA is configured.
• The period of the two clock inputs can differ by no more than 20%.
The input clocks must meet the input jitter specifications to ensure proper operation of the status signals.
Glitches in the input clock may be seen as a greater than 20% difference in frequency between the input
clocks.
If the current clock input stops toggling while the other clock is also not toggling, switchover is not
initiated and the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but
their period difference is within 20%, the clock sense block detects when a clock stops toggling. However,
the PLL may lose lock after the switchover is completed and needs time to relock.
Note: You must reset the PLL using the reset signal to maintain the phase relationships between the PLL
input and output clocks when using clock switchover.
Figure 4-16: Automatic Switchover After Loss of Clock Detection
This figure shows an example waveform of the switchover feature in automatic switchover mode. In this
example, the inclk0 signal is held low. After the inclk0 signal is held low for approximately two clock
cycles, the clock sense circuitry drives the clkbad0 signal high. As the reference clock signal (inclk0) is
not toggling, the switchover state machine controls the multiplexer through the clkswitch signal to
switch to the backup clock, inclk1.
inclk0
inclk1
muxout
clkbad0
clkbad1
activeclock
Switchover is enabled on the falling
edge of inclk0 or inclk1, depending on
which clock is available. In this figure,
switchover is enabled on the falling
edge of inclk1.
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Automatic Switchover with Manual Override
4-25
Automatic Switchover with Manual Override
In automatic switchover with manual override mode, you can use the clkswitch signal for user- or
system-controlled switch conditions. You can use this mode for same-frequency switchover, or to switch
between inputs of different frequencies.
For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using the
clkswitch signal. The automatic clock-sense circuitry cannot monitor clock input (inclk0 and inclk1)
frequencies with a frequency difference of more than 100% (2×).
This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a
system-controlled switchover between the frequencies of operation.
You must choose the backup clock frequency and set the M, N, C, L, and K counters so that the VCO
operates within the recommended operating frequency range. The Altera IOPLL (for I/O PLL) and
Arria 10 FPLL (for fPLL) parameter editors notifies you if a given combination of inclk0 and inclk1
frequencies cannot meet this requirement.
Figure 4-17: Clock Switchover Using the clkswitch (Manual) Control
This figure shows a clock switchover waveform controlled by the clkswitch signal. In this case, both
clock sources are functional and inclk0 is selected as the reference clock. The switchover sequence starts
when the clkswitch signal goes low. On the falling edge of inclk0, the counter’s reference clock, muxout,
is gated off to prevent clock glitching. On the falling edge of inclk1, the reference clock multiplexer
switches from inclk0 to inclk1 as the PLL reference. The activeclock signal changes to indicate the
clock which is currently feeding the PLL.
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
To initiate a manual clock switchover event,
both inclk0 and inclk1 must be running when
the clkswitch signal goes low.
In automatic override with manual switchover mode, the activeclock signal inverts after the clkswitch
signal transitions from logic high to logic low. Since both clocks are still functional during the manual
switch, neither clkbad signal goes high. Because the switchover circuit is negative-edge sensitive, the
rising edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0.
When the clkswitch signal goes low again, the process repeats.
The clkswitch signal and automatic switch work only if the clock being switched to is available. If the
clock is not available, the state machine waits until the clock is available.
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Manual Clock Switchover
Related Information
• Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Provides more information about I/O PLL software support in the Quartus Prime software.
• PLLs and Clock Networks chapter, Arria 10 Transceiver PHY User Guide
Provides more information about fPLL software support in the Quartus Prime software.
Manual Clock Switchover
In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as
the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the clkswitch signal transitions from logic high to logic low,
and being held high for at least three inclk cycles for the inclk being switched to.
You must bring the clkswitch signal back high again to perform another switchover event. If you do not
require another switchover event, you can leave the clkswitch signal in a logic low state after the initial
switch.
Pulsing the clkswitch signal low for at least three inclk cycles for the inclk being switched to performs
another switchover event.
If inclk0 and inclk1 are different frequencies and are always running, the clkswitch signal minimum
high time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
Figure 4-18: Manual Clock Switchover Circuitry in Arria 10 PLLs
clkswitch
Clock Switch
Control Logic
inclk0
inclk1
N Counter
muxout
PFD
refclk
fbclk
You can delay the clock switchover action by specifying the switchover delay in the Altera IOPLL (for I/O
PLL) and Arria 10 FPLL (for fPLL) IP cores. When you specify the switchover delay, the clkswitch signal
must be held high for at least three inclk cycles for the inclk being switched to plus the number of the
delay cycles that has been specified to initiate a clock switchover.
Related Information
• Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Provides more information about I/O PLL software support in the Quartus Prime software.
• PLLs and Clock Networks chapter, Arria 10 Transceiver PHY User Guide
Provides more information about fPLL software support in the Quartus Prime software.
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Guidelines
4-27
Guidelines
When implementing clock switchover in Arria 10 PLLs, use the following guidelines:
• Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of each
other. Failing to meet this requirement causes the clkbad0 and clkbad1 signals to not function
properly.
• When using manual clock switchover, the difference between inclk0 and inclk1 can be more than
100% (2×). However, differences in frequency, phase, or both, of the two clock sources will likely cause
the PLL to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships
between the input and output clocks.
• Both inclk0 and inclk1 must be running when the clkswitch signal goes low to initiate the manual
clock switchover event. Failing to meet this requirement causes the clock switchover to not function
properly.
• Applications that require a clock switchover feature and a small frequency drift must use a lowbandwidth PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly
than a high-bandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping
of the clock to the output more slowly than a high-bandwidth PLL. However, be aware that the lowbandwidth PLL also increases lock time.
• After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a
new clock. The time it takes for the PLL to relock depends on the PLL configuration.
• The phase relationship between the input clock to the PLL and the output clock from the PLL is
important in your design. Assert the reset signal for at least 10 ns after performing a clock switchover.
Wait for the locked signal to go high and be stable before re-enabling the output clocks from the PLL.
• The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO
locks on to the backup clock, as shown in the following figure.
Figure 4-19: VCO Switchover Operating Frequency
Primary Clock Stops Running
Switchover Occurs
∆ F vco
VCO Tracks Secondary Clock
PLL Reconfiguration and Dynamic Phase Shift
fPLLs and I/O PLLs support PLL reconfiguration and dynamic phase shift with the following features:
• PLL reconfiguration—Reconfigure the M, N, and C counters. Able to reconfigure the fractional settings
(for fPLL).
• Dynamic phase shift—Perform positive or negative phase shift. fPLLs support only single phase step in
one dynamic phase shift operation, where each phase step is equal to 1/4 of the VCO period. I/O PLLs
support multiple phase steps in one dynamic phase shift operation, where each phase step is equal to
1/8 of the VCO period.
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Related Information
• AN728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10 Devices
Provides more information about implementing I/O PLL reconfiguration in Altera PLL Reconfig IP
core and implementing I/O PLL dynamic phase shift in Altera IOPLL IP core.
• Using PLLs and Clock Networks, Arria 10 Transceiver PHY User Guide
Provides more information about implementing fPLL reconfiguration in the Quartus Prime software.
Document Revision History
Date
November
2015
Version
2015.11.02
Changes
• Updated the description in Hierarchical Clock Networks section:
Arria 10 devices provide a maximum of 33 SCLK networks in the
SCLK spine region.
• Updated GCLK Control Block for Arria 10 Devices diagram.
• Removed the following description in the GCLK Control Block
section: The inputs from the clock pins feed the inclk[0..1] ports of
the multiplexer, and the PLL outputs feed the inclk[2..3] ports.
• Added descriptions about I/O PLL in the Arria 10 PLLs section.
• Updated PLL Features in Arria 10 Devices table.
• Updated the feature from integer and fractional PLLs to integer
and fractional modes.
• Updated M counter divide factors for fPLL from "1 to 320" to "8 to
127".
• Updated M counter divide factors for I/O PLL from "1 to 512" to "4
to 160".
• Updated N counter divide factors for fPLL from "1 to 512" to "1 to
80".
• Updated C counter divide factors for fPLL from "1 to 320" to "1 to
512".
• Removed normal compensation support in fPLL.
• Changed "Fractional PLL bonding compensation" to "Feedback
compensation bonding".
• Updated phase shift resolution for fPLL from 41.667 ps to 72 ps.
• Updated compensation mode in Fractional PLL High-Level Block
Diagram for Arria 10 Devices.
• Updated clock feedback modes for fPLL.
• Removed normal compensation.
• Changed fPLL bonding compensation to feedback compensation
bonding.
• Updated description for dynamic phase shift in the PLL Reconfigura‐
tion and Dynamic Phase Shift section.
• Changed instances of Quartus II to Quartus Prime.
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Document Revision History
Date
Version
4-29
Changes
May 2015
2015.05.04
• Updated the number of RCLK/RCLK feedback from 12 to 8 in the
Hierarchical Clock Networks in SCLK Spine diagram.
• Added description to the Global Clock Networks section: Each GCLK
is accessible through the direction as indicated in the Symbolic GCLK
Networks diagram.
• Updated HSSI outputs to HSSI clock outputs in the Clock Network
Sources section.
• Specified that the fPLL and I/O PLL clock outputs can drive all clock
networks in the PLL Clock Outputs section.
• Added descriptions on PLL cascading bandwidth requirements and
PLL cascading modes.
• Added a note on fPLL reset requirement in the PLL Control Signals
(Reset) section.
January 2015
2015.01.23
• Updated the dedicated clock input pins that have dedicated
connections to the I/O PLL (CLK_[2,3][A..L]_[0,1][p,n]) when
used as single-ended clock inputs.
• Removed the dedicated clock input pins, CLK_[2,3][A..L]_[0,1]n,
that drive the I/O PLLs over global or regional clock networks and do
not have dedicated routing paths to the I/O PLLs.
• Removed a note to Internal Logic in the Clock Network Sources
section. Note removed: Internally-generated GCLKs or RCLKs
cannot drive the Arria 10 PLLs. The input clock to the PLL has to
come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed
RCLKs.
• Added clock control block pin mapping tables for HSSI and I/O
columns.
• Updated Fractional PLL High-Level Block Diagram for Arria 10
Devices. Changed CLKp to REFCLK_GXBp and CLKn to REFCLK_GXBn in
the note for dedicated clock inputs.
• Updated the note to dedicated clock inputs in I/O PLL High-Level
Block Diagram for Arria 10 Devices because all four clock inputs can
be used as dedicated clock inputs for I/O PLL. The note was changed
from "For single-ended clock inputs, only the CLKp pin has a
dedicated connection to the PLL. If you use the CLKn pin, a global or
regional clock is used." to "For single-ended clock inputs, both the
CLKp and CLKn pins have dedicated connection to the PLL."
• Added PLL cascading information.
• Clarified that when the reset signal is driven low again, the PLL
resynchronizes to its input clock source as it re-locks.
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Document Revision History
Date
Version
Changes
• Added description for clock feedback mode: Clock feedback modes
compensate for clock network delays to align the PLL clock input
rising edge with the rising edge of the clock output. Select the
appropriate type of compensation for the timing critical clock path in
your design. PLL compensation is not always needed. A PLL should
be configured in direct (no compensation) mode unless a need for
compensation is identified. Direct mode provides the best PLL jitter
performance and avoids expending compensation clocking resources
unnecessarily.
• Updated clock switchover from positive trigger from clkswitch
signal to negative trigger from clkswitch signal.
• Added the links to the following documents:
• Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User
Guide—Provides more information about I/O PLL software
support in the Quartus Prime software.
• PLLs and Clock Networks chapter, Arria 10 Transceiver PHY User
Guide—Provides more information about fPLL software support
in the Quartus Prime software.
• I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10
Devices—Provides more information about implementing I/O
PLL reconfiguration in Altera PLL Reconfig IP core and
implementing I/O PLL dynamic phase shift in Altera IOPLL IP
core.
August 2014
December
2013
Altera Corporation
2014.08.18
2013.12.02
•
•
•
•
•
•
Updated the dedicated clock input pins name from HSSI banks.
Updated the description in Hierarchical Clock Networks section.
Updated the description in Dedicated Clock Input Pins section.
Removed PCLK network from the Internal Logic section.
Updated the description in PCLK Control Block section.
Updated the following diagrams:
•
•
•
•
• PCLK Control Block for HSSI Column for Arria 10 Devices
• PCLK Control Block for I/O Column for Arria 10 Devices
Removed IQTXRXCLK compensation mode.
Updated fractional PLL and I/O PLL high-level block diagrams.
Updated the description for manual clock switchover.
Updated the description for PLL reconfiguration.
Initial release.
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The Arria 10 I/Os support the following features:
• Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
• Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, SSTL, and POD I/O
standards
• Serializer/deserializer (SERDES)
• Programmable output current strength
• Programmable slew-rate
• Programmable bus-hold
• Programmable weak pull-up resistor
• Programmable pre-emphasis for DDR4 and LVDS standards
• Programmable I/O delay
• Programmable differential output voltage (VOD)
• Open-drain output
• On-chip series termination (RS OCT) with and without calibration
• On-chip parallel termination (RT OCT)
• On-chip differential termination (RD OCT)
• HSTL and SSTL input buffer with dynamic power down
• Dynamic on-chip parallel termination for all I/O banks
• Internally generated VREF with DDR4 calibration
Note: The information in this chapter is applicable to all Arria 10 variants, unless noted otherwise.
Related Information
Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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I/O and Differential I/O Buffers in Arria 10 Devices
I/O and Differential I/O Buffers in Arria 10 Devices
The general purpose I/Os (GPIOs) consist of LVDS I/O and 3 V I/O banks:
• LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins
form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination
between the two pins. You can use each LVDS channel as transmitter only or receiver only. Each
LVDS channel supports transmit SERDES and receive SERDES with DPA circuitry. For example, if
you use 30 channels of the available 72 channels as transmitters, you can use the balance 42 channels as
receivers.
• 3 V I/O bank—supports only single-ended I/O standards up to 3 V. Each adjacent I/O pair also
supports Differential SSTL and Differential HSTL I/O standards. The single-ended output of the
3 V I/O supports all programmable I/O element (IOE) features except:
•
•
•
•
Programmable pre-emphasis
RD on-chip termination (OCT)
Calibrated RS and RT OCT
Internal VREF generation
Arria 10 devices support LVDS on all LVDS I/O banks:
• All LVDS I/O banks support true LVDS input with RD OCT and true LVDS output buffer.
• The devices do not support emulated LVDS channels.
• The devices support single-ended I/O reference clock for the I/O PLL that drives the SERDES.
Related Information
• FPGA I/O Resources in Arria 10 GX Packages on page 5-12
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 GX packages.
• FPGA I/O Resources in Arria 10 GT Packages on page 5-14
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 GT packages.
• FPGA I/O Resources in Arria 10 SX Packages on page 5-14
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 SX packages.
I/O Standards and Voltage Levels in Arria 10 Devices
The Arria 10 device family consists of FPGA and SoC devices. Apart from the FPGA I/O buffers, the
Arria 10 SoC devices also have HPS I/O buffers with different I/O standards support.
I/O Standards Support for FPGA I/O in Arria 10 Devices
Table 5-1: Supported I/O Standards in FPGA I/O for Arria 10 Devices
I/O Standard
3.0 V LVTTL/3.0 V
LVCMOS
Altera Corporation
Device
Variant
Support
Devices with
3 V I/O banks
only. Refer to
related
information.
I/O Buffer Type Support
LVDS I/O
3V I/O
No
Yes
Application
Standard Support
General purpose
JESD8-B
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I/O Standards Support for FPGA I/O in Arria 10 Devices
I/O Standard
Device
Variant
Support
I/O Buffer Type Support
LVDS I/O
3V I/O
Application
Standard Support
2.5 V LVCMOS
Devices with
3 V I/O banks
only. Refer to
related
information.
No
Yes
General purpose
JESD8-5
1.8 V LVCMOS
All
Yes
Yes
General purpose
JESD8-7
1.5 V LVCMOS
All
Yes
Yes
General purpose
JESD8-11
1.2 V LVCMOS
All
Yes
Yes
General purpose
JESD8-12
SSTL-18 Class I and Class
II
All
Yes
Yes
DDR2
JESD8-15
SSTL-15 Class I and Class
II
All
Yes
Yes
DDR3
—
SSTL-15
All
Yes
Yes
DDR3
JESD79-3D
SSTL-135
All
Yes
Yes
DDR3L
—
SSTL-125
All
Yes
Yes
DDR3U
—
SSTL-12
All
Yes
No
RLDRAM 3
—
POD12
All
Yes
No
DDR4
JESD8-24
1.8 V HSTL Class I and
Class II
All
Yes
Yes
DDR II+,
QDR II+, and
RLDRAM 2
JESD8-6
1.5 V HSTL Class I and
Class II
All
Yes
Yes
DDR II+,
QDR II+, QDR II,
and RLDRAM 2
JESD8-6
1.2 V HSTL Class I and
Class II
All
Yes
Yes
General purpose
JESD8-16A
HSUL-12
All
Yes
Yes
LPDDR2
—
Differential SSTL-18 Class I
and Class II
All
Yes
Yes
DDR2
JESD8-15
Differential SSTL-15 Class I
and Class II
All
Yes
Yes
DDR3
—
Differential SSTL-15
All
Yes
Yes
DDR3
JESD79-3D
Differential SSTL-135
All
Yes
Yes
DDR3L
—
Differential SSTL-125
All
Yes
Yes
DDR3U
—
Differential SSTL-12
All
Yes
No
RLDRAM 3
—
Differential POD12
All
Yes
No
DDR4
JESD8-24
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I/O Standards Support for HPS I/O in Arria 10 Devices
I/O Standard
Device
Variant
Support
I/O Buffer Type Support
LVDS I/O
3V I/O
Application
Standard Support
Differential 1.8 V HSTL
Class I and Class II
All
Yes
Yes
DDR II+,
QDR II+, and
RLDRAM 2
JESD8-6
Differential 1.5 V HSTL
Class I and Class II
All
Yes
Yes
DDR II+,
QDR II+, QDR II,
and RLDRAM 2
JESD8-6
Differential 1.2 V HSTL
Class I and Class II
All
Yes
Yes
General purpose
JESD8-16A
Differential HSUL-12
All
Yes
Yes
LPDDR2
—
LVDS
All
Yes
No
SGMII, SFI, and
SPI
ANSI/TIA/EIA644
Mini-LVDS
All
Yes
No
SGMII, SFI, and
SPI
—
RSDS
All
Yes
No
SGMII, SFI, and
SPI
—
LVPECL
All
Yes
No
SGMII, SFI, and
SPI
—
Related Information
• FPGA I/O Resources in Arria 10 GX Packages on page 5-12
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 GX packages.
• FPGA I/O Resources in Arria 10 GT Packages on page 5-14
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 GT packages.
• FPGA I/O Resources in Arria 10 SX Packages on page 5-14
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 SX packages.
I/O Standards Support for HPS I/O in Arria 10 Devices
Table 5-2: Supported I/O Standards in HPS I/O for Arria 10 SX Devices—Preliminary
I/O Standard
Application
Standard Support
3.0 V LVTTL/3.0 V LVCMOS
General purpose
JESD8-B
2.5 V LVCMOS
General purpose
JESD8-5
1.8 V LVCMOS
General purpose
JESD8-7
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I/O Standards Voltage Levels in Arria 10 Devices
I/O Standards Voltage Levels in Arria 10 Devices
Table 5-3: Arria 10 I/O Standards Voltage Levels
This table lists the typical power supplies for each supported I/O standards in Arria 10 devices.
VCCIO (V)
I/O Standard
(6)
VCCPT (V)
VREF (V)
VTT (V)
Input(6)
Output
(Pre-Driver
Voltage)
(Input Ref
Voltage)
(Board Termination
Voltage)
3.0 V LVTTL/3.0 V LVCMOS
3.0
3.0
1.8
—
—
2.5 V LVCMOS
2.5
2.5
1.8
—
—
1.8 V LVCMOS
1.8
1.8
1.8
—
—
1.5 V LVCMOS
1.5
1.5
1.8
—
—
1.2 V LVCMOS
1.2
1.2
1.8
—
—
SSTL-18 Class I and Class II
VCCPT
1.8
1.8
0.9
0.9
SSTL-15 Class I and Class II
VCCPT
1.5
1.8
0.75
0.75
SSTL-15
VCCPT
1.5
1.8
0.75
0.75
SSTL-135
VCCPT
1.35
1.8
0.675
—
SSTL-125
VCCPT
1.25
1.8
0.625
—
SSTL-12
VCCPT
1.2
1.8
0.6
—
POD12
VCCPT
1.2
1.8
0.84
1.2
1.8 V HSTL Class I and Class
II
VCCPT
1.8
1.8
0.9
0.9
1.5 V HSTL Class I and Class
II
VCCPT
1.5
1.8
0.75
0.75
1.2 V HSTL Class I and Class
II
VCCPT
1.2
1.8
0.6
0.6
HSUL-12
VCCPT
1.2
1.8
0.6
—
Differential SSTL-18 Class I
and Class II
VCCPT
1.8
1.8
—
0.9
Differential SSTL-15 Class I
and Class II
VCCPT
1.5
1.8
—
0.75
Differential SSTL-15
VCCPT
1.5
1.8
—
0.75
Differential SSTL-135
VCCPT
1.35
1.8
—
0.675
Differential SSTL-125
VCCPT
1.25
1.8
—
0.625
Differential SSTL-12
VCCPT
1.2
1.8
—
0.6
Differential POD12
VCCPT
1.2
1.8
—
1.2
Input for the SSTL, HSTL, Differential SSTL, Differential HSTL, POD, Differential POD, LVDS, RSDS,
Mini-LVDS, LVPECL, HSUL, and Differential HSUL are powered by VCCPT
I/O and High Speed I/O in Arria 10 Devices
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VCCIO (V)
I/O Standard
VCCPT (V)
VREF (V)
VTT (V)
Input(6)
Output
(Pre-Driver
Voltage)
(Input Ref
Voltage)
(Board Termination
Voltage)
Differential 1.8 V HSTL Class
I and Class II
VCCPT
1.8
1.8
—
0.9
Differential 1.5 V HSTL Class
I and Class II
VCCPT
1.5
1.8
—
0.75
Differential 1.2 V HSTL Class
I and Class II
VCCPT
1.2
1.8
—
0.6
Differential HSUL-12
VCCPT
1.2
1.8
—
—
LVDS
VCCPT
1.8
1.8
—
—
Mini-LVDS
VCCPT
1.8
1.8
—
—
RSDS
VCCPT
1.8
1.8
—
—
LVPECL (Differential clock
input only)
VCCPT
—
1.8
—
—
Related Information
• Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing on page 5-83
• Guideline: VREF Sources and VREF Pins on page 5-83
MultiVolt I/O Interface in Arria 10 Devices
The MultiVolt I/O interface feature allows Arria 10 devices in all packages to interface with systems of
different supply voltages:
•
•
•
•
Each I/O bank in Arria 10 devices has its own VCCIO supply and can support only one VCCIO voltage.
The supported VCCIO voltage is 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, or 3.0 V.
The 2.5 V and 3.0 V VCCIO is supported only on the 3 V I/O buffer type.
The I/O buffers are powered by VCC, VCCPT and VCCIO.
Altera I/O IPs for Arria 10 Devices
The I/O system is supported by several Altera I/O IPs.
•
•
•
•
Altera GPIO—supports operations of the GPIO components.
Altera LVDS SERDES—supports operations of the high-speed source-synchronous SERDES.
Altera OCT—supports the OCT calibration block.
Altera PHYlite—supports dynamic OCT and I/O delays for strobe-based capture I/O elements.
Related Information
• Altera PHYlite for Memory IP Core User Guide
(6)
Input for the SSTL, HSTL, Differential SSTL, Differential HSTL, POD, Differential POD, LVDS, RSDS,
Mini-LVDS, LVPECL, HSUL, and Differential HSUL are powered by VCCPT
Altera Corporation
I/O and High Speed I/O in Arria 10 Devices
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I/O Resources in Arria 10 Devices
5-7
• Altera GPIO IP Core User Guide
• Altera OCT IP Core User Guide
• Altera LVDS SERDES IP Core User Guide
I/O Resources in Arria 10 Devices
GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
GPIO Buffers and LVDS Channels in Arria 10 Devices on page 5-12
I/O Banks Groups in Arria 10 Devices on page 5-15
I/O Vertical Migration for Arria 10 Devices on page 5-24
GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices
The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, DPA, and SERDES
circuitries.
For more details about the modular I/O banks available in each device package, refer to the related
information.
Figure 5-1: I/O Banks for Arria 10 GX 160 and GX 220 Devices—Preliminary
Transceiver Block
2L
2K
2J
3B
3A
2A
I/O and High Speed I/O in Arria 10 Devices
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LVDS I/O
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GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices
Figure 5-2: I/O Banks for Arria 10 SX 160 and SX 220 Devices—Preliminary
Transceiver Block
2K
HPS I/O
2L
2J
3B
3A
2A
3 V I/O
LVDS I/O
Transceiver Block
Figure 5-3: I/O Banks for Arria 10 GX 270 and GX 320 Devices—Preliminary
2L
3D
2K
3C
2J
3B
3A
2A
3 V I/O
LVDS I/O
Figure 5-4: I/O Banks for Arria 10 SX 270 and SX 320 Devices—Preliminary
Transceiver Block
2L
2J
HPS I/O
2K
3D
3C
3B
3A
2A
Altera Corporation
3 V I/O
LVDS I/O
I/O and High Speed I/O in Arria 10 Devices
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GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices
5-9
Figure 5-5: I/O Banks for Arria 10 GX 480 Devices—Preliminary
3F
2L
3E
Transceiver Block
2K
3D
2J
3C
2I
3B
2A
3A
3 V I/O
LVDS I/O
Figure 5-6: I/O Banks for Arria 10 SX 480 Devices—Preliminary
3F
Transceiver Block
2K
HPS I/O
2L
3E
3D
2J
3C
2I
3B
2A
I/O and High Speed I/O in Arria 10 Devices
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3A
3 V I/O
LVDS I/O
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GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices
Figure 5-7: I/O Banks for Arria 10 GX 570 and GX 660 Devices—Preliminary
3H
2L
3G
2K
3F
Transceiver Block
2J
3E
2I
3D
2H
3C
2G
3B
2A
3A
3 V I/O
LVDS I/O
Figure 5-8: I/O Banks for Arria 10 SX 570 and SX 660 Devices—Preliminary
3H
2K
HPS I/O
2L
3G
3F
Transceiver Block
2J
3E
2I
3D
2H
3C
2G
3B
2A
Altera Corporation
3A
3 V I/O
LVDS I/O
I/O and High Speed I/O in Arria 10 Devices
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5-11
2L
3H
2K
3G
2J
3F
2I
3E
2H
3D
2G
3C
2F
3B
Transceiver Block
Transceiver Block
Figure 5-9: I/O Banks for Arria 10 GX 900, GX 1150, GT 900, and GT 1150 Devices—Preliminary
3A
2A
LVDS I/O
Related Information
• Device Transceiver Layout
Provides more information about the transceiver banks in Arria 10 devices.
• Modular I/O Banks for Arria 10 GX Devices on page 5-16
Lists the number of I/O pins in the available I/O banks for each Arria 10 GX package.
• Modular I/O Banks for Arria 10 GT Devices on page 5-19
Lists the number of I/O pins in the available I/O banks for each Arria 10 GT package.
• Modular I/O Banks for Arria 10 SX Devices on page 5-20
Lists the number of I/O pins in the available I/O banks for each Arria 10 SX package.
• FPGA I/O Resources in Arria 10 GX Packages on page 5-12
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 GX packages.
• FPGA I/O Resources in Arria 10 GT Packages on page 5-14
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 GT packages.
• FPGA I/O Resources in Arria 10 SX Packages on page 5-14
Lists the number of 3 V and LVDS I/O buffers available in Arria 10 SX packages.
• Arria 10 Device Pin-Out Files
Provides the pin-out file for each Arria 10 device. For the SoC devices, the pin-out files also list the I/O
banks that are shared by the FPGA fabric and the HPS.
• Altera GPIO IP Core User Guide
• PLLs and Clocking for Arria 10 Devices on page 5-66
I/O and High Speed I/O in Arria 10 Devices
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GPIO Buffers and LVDS Channels in Arria 10 Devices
GPIO Buffers and LVDS Channels in Arria 10 Devices
FPGA I/O Resources in Arria 10 GX Packages
Table 5-4: GPIO Buffers and LVDS Channels in Arria 10 GX Devices—Preliminary
• The U19 package is a ball grid array with 0.8 mm pitch. All other packages are ball grid arrays with 1.0 mm
pitch.
• The LVDS channels counts do not include dedicated clock pins.
Product Line
GX 160
GX 220
GX 270
GX 320
GX 480
GX 570
Altera Corporation
Package
GPIO
LVDS Channels
Code
Type
3 V I/O
LVDS I/O
Total
U19
484-pin UBGA
48
148
196
74
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
240
288
120
U19
484-pin UBGA
48
148
196
74
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
240
288
120
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
312
360
156
F34
1,152-pin FBGA
48
336
384
168
F35
1,152-pin FBGA
48
336
384
168
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
312
360
156
F34
1,152-pin FBGA
48
336
384
168
F35
1,152-pin FBGA
48
336
384
168
F29
780-pin FBGA
48
312
360
156
F34
1,152-pin FBGA
48
444
492
222
F35
1,152-pin FBGA
48
348
396
174
F34
1,152-pin FBGA
48
444
492
222
F35
1,152-pin FBGA
48
348
396
174
F36
1,152-pin FBGA
48
384
432
192
NF40
1,517-pin FBGA
48
540
588
270
KF40
1,517-pin FBGA
96
600
696
300
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FPGA I/O Resources in Arria 10 GX Packages
Product Line
GX 660
GX 900
GX 1150
Package
GPIO
LVDS Channels
Code
Type
3 V I/O
LVDS I/O
Total
F34
1,152-pin FBGA
48
444
492
222
F35
1,152-pin FBGA
48
348
396
174
F36
1,152-pin FBGA
48
384
432
192
NF40
1,517-pin FBGA
48
540
588
270
KF40
1,517-pin FBGA
96
600
696
300
F34
1,152-pin FBGA
0
504
504
252
F36
1,152-pin FBGA
0
432
432
216
NF40
1,517-pin FBGA
0
600
600
300
RF40
1,517-pin FBGA
0
342
342
154
NF45
1,932-pin FBGA
0
768
768
384
SF45
1,932-pin FBGA
0
624
624
312
UF45
1,932-pin FBGA
0
480
480
240
F34
1,152-pin FBGA
0
504
504
252
F36
1,152-pin FBGA
0
432
432
216
NF40
1,517-pin FBGA
0
600
600
300
RF40
1,517-pin FBGA
0
342
342
154
NF45
1,932-pin FBGA
0
768
768
384
SF45
1,932-pin FBGA
0
624
624
312
UF45
1,932-pin FBGA
0
480
480
240
Related Information
• Modular I/O Banks for Arria 10 GX Devices on page 5-16
Lists the number of I/O pins in the available I/O banks for each Arria 10 GX package.
• I/O Standards Support for FPGA I/O in Arria 10 Devices on page 5-2
• GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
• I/O and Differential I/O Buffers in Arria 10 Devices on page 5-2
I/O and High Speed I/O in Arria 10 Devices
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FPGA I/O Resources in Arria 10 GT Packages
FPGA I/O Resources in Arria 10 GT Packages
Table 5-5: GPIO Buffers and LVDS Channels in Arria 10 GT Devices—Preliminary
• All packages are ball grid arrays with 1.0 mm pitch.
• The LVDS channels counts do not include dedicated clock pins.
Product
Line
GT 900
GT 1150
Package
GPIO Buffers
LVDS Channels
Code
Type
3 V I/O
LVDS I/O
Total
NF40
1,517-pin FBGA
0
600
600
300
SF45
1,932-pin FBGA
0
624
624
312
UF45
1,932-pin FBGA
0
480
480
240
NF40
1,517-pin FBGA
0
600
600
300
SF45
1,932-pin FBGA
0
624
624
312
UF45
1,932-pin FBGA
0
480
480
240
Related Information
• Modular I/O Banks for Arria 10 GT Devices on page 5-19
Lists the number of I/O pins in the available I/O banks for each Arria 10 GT package.
• I/O Standards Support for FPGA I/O in Arria 10 Devices on page 5-2
• GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
• I/O and Differential I/O Buffers in Arria 10 Devices on page 5-2
FPGA I/O Resources in Arria 10 SX Packages
Table 5-6: GPIO Buffers and LVDS Channels in Arria 10 SX Devices—Preliminary
• The U19 package is a ball grid array with 0.8 mm pitch. All other packages are ball grid arrays with 1.0 mm
pitch.
• The LVDS channels counts do not include dedicated clock pins.
Product Line
SX 160
SX 220
Altera Corporation
Package
GPIO Buffers
LVDS Channels
Code
Type
3 V I/O
LVDS I/O
Total
U19
484-pin UBGA
48
148
196
74
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
240
288
120
U19
484-pin UBGA
48
148
196
74
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
240
288
120
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I/O Banks Groups in Arria 10 Devices
Product Line
SX 270
SX 320
SX 480
SX 570
SX 660
Package
GPIO Buffers
LVDS Channels
Code
Type
3 V I/O
LVDS I/O
Total
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
312
360
156
F34
1,152-pin FBGA
48
336
384
168
F35
1,152-pin FBGA
48
336
384
168
F27
672-pin FBGA
48
192
240
96
F29
780-pin FBGA
48
312
360
156
F34
1,152-pin FBGA
48
336
384
168
F35
1,152-pin FBGA
48
336
384
168
F29
780-pin FBGA
48
312
360
156
F34
1,152-pin FBGA
48
444
492
222
F35
1,152-pin FBGA
48
348
396
174
F34
1,152-pin FBGA
48
444
492
222
F35
1,152-pin FBGA
48
348
396
174
NF40
1,517-pin FBGA
48
540
588
270
KF40
1,517-pin FBGA
96
600
696
300
F34
1,152-pin FBGA
48
444
492
222
F35
1,152-pin FBGA
48
348
396
174
NF40
1,517-pin FBGA
48
540
588
270
KF40
1,517-pin FBGA
96
600
696
300
Related Information
• Modular I/O Banks for Arria 10 SX Devices on page 5-20
Lists the number of I/O pins in the available I/O banks for each Arria 10 SX package.
• I/O Standards Support for FPGA I/O in Arria 10 Devices on page 5-2
• GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
• I/O and Differential I/O Buffers in Arria 10 Devices on page 5-2
I/O Banks Groups in Arria 10 Devices
The I/O pins in Arria 10 devices are arranged in groups called modular I/O banks:
• Modular I/O banks have independent supplies that allow each bank to support different I/O standards.
• Each modular I/O bank can support multiple I/O standards that use the same voltage.
Related Information
• Modular I/O Banks for Arria 10 GX Devices on page 5-16
• Modular I/O Banks for Arria 10 GT Devices on page 5-19
• Modular I/O Banks for Arria 10 SX Devices on page 5-20
I/O and High Speed I/O in Arria 10 Devices
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Modular I/O Banks for Arria 10 GX Devices
Modular I/O Banks for Arria 10 GX Devices
The following tables list the I/O banks available, the total number of I/O pins in each bank, and the total
number of I/O pins for each product line and device package of the Arria 10 GX device family variant.
Table 5-7: Modular I/O Banks for Arria 10 GX 160 and GX 220 Devices—Preliminary
Product Line
GX 160
Package
I/O Bank
GX 220
U19
F27
F29
U19
F27
F29
2A
48
48
48
48
48
48
2J
48
48
48
48
48
48
2K
48
48
48
48
48
48
2L
48
48
48
48
48
48
3A
—
48
48
—
48
48
3B
4
—
48
4
—
48
196
240
288
196
240
288
Total
Table 5-8: Modular I/O Banks for Arria 10 GX 270 and GX 320 Devices—Preliminary
Product Line
Package
I/O Bank
Total
Altera Corporation
GX 270
GX 320
F27
F29
F34
F35
F27
F29
F34
F35
2A
48
48
48
48
48
48
48
48
2J
48
48
48
48
48
48
48
48
2K
48
48
48
48
48
48
48
48
2L
48
48
48
48
48
48
48
48
3A
48
48
48
48
48
48
48
48
3B
—
48
48
48
—
48
48
48
3C
—
48
48
48
—
48
48
48
3D
—
24
48
48
—
24
48
48
240
360
384
384
240
360
384
384
I/O and High Speed I/O in Arria 10 Devices
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Modular I/O Banks for Arria 10 GX Devices
5-17
Table 5-9: Modular I/O Banks for Arria 10 GX 480 Devices—Preliminary
Product Line
GX 480
Package
I/O Bank
F29
F34
F35
2A
48
48
48
2I
—
12
12
2J
48
48
48
2K
48
48
48
2L
48
48
48
3A
48
48
48
3B
48
48
48
3C
48
48
48
3D
24
48
48
3E
—
48
—
3F
—
48
—
360
492
396
Total
Table 5-10: Modular I/O Banks for Arria 10 GX 570 and GX 660 Devices—Preliminary
Product Line
Package
I/O
Bank
GX 570
GX 660
F34
F35
F36
NF40
KF40
F34
F35
F36
NF40
KF40
2A
48
48
48
48
48
48
48
48
48
48
2G
—
—
—
—
24
—
—
—
—
24
2H
—
—
—
—
48
—
—
—
—
48
2I
12
12
48
12
48
12
12
48
12
48
2J
48
48
48
48
48
48
48
48
48
48
2K
48
48
48
48
48
48
48
48
48
48
2L
48
48
48
48
48
48
48
48
48
48
3A
48
48
48
48
48
48
48
48
48
48
3B
48
48
48
48
48
48
48
48
48
48
3C
48
48
48
48
48
48
48
48
48
48
3D
48
48
48
48
48
48
48
48
48
48
3E
48
—
—
48
48
48
—
—
48
48
3F
48
—
—
48
48
48
—
—
48
48
3G
—
—
—
48
48
—
—
—
48
48
3H
—
—
—
48
48
—
—
—
48
48
I/O and High Speed I/O in Arria 10 Devices
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Modular I/O Banks for Arria 10 GX Devices
Product Line
GX 570
GX 660
Package
F34
F35
F36
NF40
KF40
F34
F35
F36
NF40
KF40
Total
492
396
432
588
696
492
396
432
588
696
Table 5-11: Modular I/O Banks for Arria 10 GX 900 Devices—Preliminary
Product Line
Package
I/O Bank
Total
Altera Corporation
GX 900
F34
F36
NF40
RF40
NF45
SF45
UF45
2A
48
48
48
48
48
48
48
2F
—
—
—
48
48
—
—
2G
—
—
—
—
48
—
—
2H
—
—
—
—
48
—
—
2I
24
48
24
—
48
48
48
2J
48
48
48
—
48
48
48
2K
48
48
48
48
48
48
48
2L
48
48
48
48
48
48
48
3A
48
48
48
28
48
48
48
3B
48
48
48
27
48
48
48
3C
48
48
48
—
48
48
48
3D
48
48
48
—
48
48
48
3E
48
—
48
—
48
48
48
3F
48
—
48
—
48
48
—
3G
—
—
48
47
48
48
—
3H
—
—
48
48
48
48
—
504
432
600
342
768
624
480
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Modular I/O Banks for Arria 10 GT Devices
Table 5-12: Modular I/O Banks for Arria 10 GX 1150 Devices—Preliminary
Product Line
Package
I/O Bank
GX 1150
F34
F36
NF40
RF40
NF45
SF45
UF45
2A
48
48
48
48
48
48
48
2F
—
—
—
48
48
—
—
2G
—
—
—
—
48
—
—
2H
—
—
—
—
48
—
—
2I
24
48
24
—
48
48
48
2J
48
48
48
—
48
48
48
2K
48
48
48
48
48
48
48
2L
48
48
48
48
48
48
48
3A
48
48
48
28
48
48
48
3B
48
48
48
27
48
48
48
3C
48
48
48
—
48
48
48
3D
48
48
48
—
48
48
48
3E
48
—
48
—
48
48
48
3F
48
—
48
—
48
48
—
3G
—
—
48
47
48
48
—
3H
—
—
48
48
48
48
—
504
432
600
342
768
624
480
Total
Related Information
•
•
•
•
GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
FPGA I/O Resources in Arria 10 GX Packages on page 5-12
I/O Banks Groups in Arria 10 Devices on page 5-15
Guideline: Altera LVDS SERDES IP Core Instantiation on page 5-85
Modular I/O Banks for Arria 10 GT Devices
The following tables list the I/O banks available, the total number of I/O pins in each bank, and the total
number of I/O pins for each product line and device package of the Arria 10 GT device family variant.
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Modular I/O Banks for Arria 10 SX Devices
Table 5-13: Modular I/O Banks for Arria 10 GT 900 and GT 1150 Devices—Preliminary
Product Line
Package
I/O Bank
GT 900
GT 1150
NF40
SF45
UF45
NF40
NF45
UF45
2A
48
48
48
48
48
48
2F
—
—
—
—
48
—
2G
—
—
—
—
48
—
2H
—
—
—
—
48
—
2I
24
48
48
24
48
48
2J
48
48
48
48
48
48
2K
48
48
48
48
48
48
2L
48
48
48
48
48
48
3A
48
48
48
48
48
48
3B
48
48
48
48
48
48
3C
48
48
48
48
48
48
3D
48
48
48
48
48
48
3E
48
48
48
48
48
48
3F
48
48
—
48
48
—
3G
48
48
—
48
48
—
3H
48
48
—
48
48
—
600
624
480
600
768
480
Total
Related Information
•
•
•
•
GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
FPGA I/O Resources in Arria 10 GT Packages on page 5-14
I/O Banks Groups in Arria 10 Devices on page 5-15
Guideline: Altera LVDS SERDES IP Core Instantiation on page 5-85
Modular I/O Banks for Arria 10 SX Devices
The following tables list the I/O banks available, the total number of I/O pins in each bank, and the total
number of I/O pins for each product line and device package of the Arria 10 SX device family variant.
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Modular I/O Banks for Arria 10 SX Devices
Table 5-14: Modular I/O Banks for Arria 10 SX 160 and SX 220 Devices—Preliminary
Product Line
SX 160
Package
I/O Bank
SX 220
U19
F27
F29
U19
F27
F29
2A
48
48
48
48
48
48
2J
48
48
48
48
48
48
2K
48
48
48
48
48
48
2L
48
48
48
48
48
48
3A
—
48
48
—
48
48
3B
4
—
48
4
—
48
196
240
288
196
240
288
Total
Table 5-15: Modular I/O Banks for Arria 10 SX 270 and SX 320 Devices—Preliminary
Product Line
Package
I/O Bank
SX 270
SX 320
F27
F29
F34
F35
F27
F29
F34
F35
2A
48
48
48
48
48
48
48
48
2J
48
48
48
48
48
48
48
48
2K
48
48
48
48
48
48
48
48
2L
48
48
48
48
48
48
48
48
3A
48
48
48
48
48
48
48
48
3B
—
48
48
48
—
48
48
48
3C
—
48
48
48
—
48
48
48
3D
—
24
48
48
—
24
48
48
240
360
384
384
240
360
384
384
Total
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Modular I/O Banks for Arria 10 SX Devices
Table 5-16: Modular I/O Banks for Arria 10 SX 480 Devices—Preliminary
Product Line
SX 480
Package
I/O Bank
F29
F34
F35
2A
48
48
48
2I
—
12
12
2J
48
48
48
2K
48
48
48
2L
48
48
48
3A
48
48
48
3B
48
48
48
3C
48
48
48
3D
24
48
48
3E
—
48
—
3F
—
48
—
360
492
396
Total
Table 5-17: Modular I/O Banks for Arria 10 SX 570 and SX 660 Devices—Preliminary
Product Line
Package
I/O Bank
Altera Corporation
SX 570
SX 660
F34
F35
NF40
KF40
F34
F35
NF40
KF40
2A
48
48
48
48
48
48
48
48
2G
—
—
—
24
—
—
—
24
2H
—
—
—
48
—
—
—
48
2I
12
12
12
48
12
12
12
48
2J
48
48
48
48
48
48
48
48
2K
48
48
48
48
48
48
48
48
2L
48
48
48
48
48
48
48
48
3A
48
48
48
48
48
48
48
48
3B
48
48
48
48
48
48
48
48
3C
48
48
48
48
48
48
48
48
3D
48
48
48
48
48
48
48
48
3E
48
—
48
48
48
—
48
48
3F
48
—
48
48
48
—
48
48
3G
—
—
48
48
—
—
48
48
3H
—
—
48
48
—
—
48
48
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Modular I/O Banks for Arria 10 SX Devices
Product Line
SX 570
5-23
SX 660
Package
F34
F35
NF40
KF40
F34
F35
NF40
KF40
Total
492
396
588
696
492
396
588
696
Related Information
•
•
•
•
GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
FPGA I/O Resources in Arria 10 SX Packages on page 5-14
I/O Banks Groups in Arria 10 Devices on page 5-15
Guideline: Altera LVDS SERDES IP Core Instantiation on page 5-85
I/O and High Speed I/O in Arria 10 Devices
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I/O Vertical Migration for Arria 10 Devices
I/O Vertical Migration for Arria 10 Devices
Figure 5-10: Migration Capability Across Arria 10 Product Lines—Preliminary
• The arrows indicate the migration paths. The devices included in each vertical migration path are
shaded. Devices with fewer resources in the same path have lighter shades.
• To achieve the full I/O migration across product lines in the same migration path, restrict I/Os and
transceivers usage to match the product line with the lowest I/O and transceiver counts.
• An LVDS I/O bank in the source device may be mapped to a 3 V I/O bank in the target device. To use
memory interface clock frequency higher than 533 MHz, assign external memory interface pins only to
banks that are LVDS I/O in both devices.
• There may be nominal 0.15 mm package height difference between some product lines in the same
package type.
• Some migration paths are not shown in the Quartus Prime software Pin Migration View.
Variant
Arria 10 GX
Arria 10 GT
Arria 10 SX
Product
Line
U19
F27
F29
F34
F35
Package
F36 KF40 NF40 RF40 NF45 SF45 UF45
GX 160
GX 220
GX 270
GX 320
GX 480
GX 570
GX 660
GX 900
GX 1150
GT 900
GT 1150
SX 160
SX 220
SX 270
SX 320
SX 480
SX 570
SX 660
Note: To verify the pin migration compatibility, use the Pin Migration View window in the Quartus
Prime software Pin Planner.
Related Information
• Verifying Pin Migration Compatibility on page 5-25
• Migrating Assignments to Another Target Device
Provides more information about vertical I/O migrations.
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Verifying Pin Migration Compatibility
5-25
Verifying Pin Migration Compatibility
You can use the Pin Migration View window in the Quartus Prime software Pin Planner to assist you in
verifying whether your pin assignments migrate to a different device successfully. You can vertically
migrate to a device with a different density while using the same device package, or migrate between
packages with different densities and ball counts.
1. Open Assignments > Pin Planner and create pin assignments.
2. If necessary, perform one of the following options to populate the Pin Planner with the node names in
the design:
3.
4.
5.
6.
7.
8.
• Analysis & Elaboration
• Analysis & Synthesis
• Fully compile the design
Then, on the menu, click View > Pin Migration View.
To select or change migration devices:
a. Click Device to open the Device dialog box.
b. Under Migration compatibility click Migration Devices.
To show more information about the pins:
a. Right-click anywhere in the Pin Migration View window and select Show Columns.
b. Then, click the pin feature you want to display.
If you want to view only the pins, in at least one migration device, that have a different feature than the
corresponding pin in the migration result, turn on Show migration differences.
Click Pin Finder to open the Pin Finder dialog box to find and highlight pins with specific function‐
ality.
If you want to view only the pins highlighted by the most recent query in the Pin Finder dialog box,
turn on Show only highlighted pins.
To export the pin migration information to a Comma-Separated Value file (.csv), click Export.
Related Information
• I/O Vertical Migration for Arria 10 Devices on page 5-24
• Migrating Assignments to Another Target Device
Provides more information about vertical I/O migrations.
Architecture and General Features of I/Os in Arria 10 Devices
I/O Element Structure in Arria 10 Devices on page 5-25
Features of I/O Pins in Arria 10 Devices on page 5-27
Programmable IOE Features in Arria 10 Devices on page 5-28
On-Chip I/O Termination in Arria 10 Devices on page 5-34
External I/O Termination for Arria 10 Devices on page 5-43
I/O Element Structure in Arria 10 Devices
The I/O elements (IOEs) in Arria 10 devices contain a bidirectional I/O buffer and I/O registers to
support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.
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I/O Bank Architecture in Arria 10 Devices
The IOEs are located in I/O columns within the core fabric of the Arria 10 device.
The Arria 10 SX devices also have IOEs for the HPS.
The GPIO IOE register consists of the DDR register, the half rate register, and the transmitter delay chains
for input, output, and output enable (OE) paths:
•
•
•
•
You can take data from the combinatorial path or the registered path.
Only the core clock clocks the data.
The half rate clock routed from the core clocks the half rate register.
The full rate clock from the core clocks the full rate register.
I/O Bank Architecture in Arria 10 Devices
In each I/O bank, there are four I/O lanes with 12 I/O pins in each lane. Other than the I/O lanes, each
I/O bank also contains dedicated circuitries including the I/O PLL, DPA block, SERDES, hard memory
controller, and I/O sequencer.
Figure 5-11: I/O Bank Structure
2L
3H
2K
3G
2J
3F
2I
3E
2H
3D
2G
3C
2F
3B
3A
2A
Altera Corporation
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
I/O Center
Transceiver Block
Transceiver Block
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
I/O PLL
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
I/O Lane
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
I/O Lane
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
I/O DLL
I/O CLK
OCT
VR
Hard Memory Controller
and
PHY Sequencer
I/O Lane
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
I/O Lane
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
SERDES & DPA
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I/O Buffer and Registers in Arria 10 Devices
5-27
Related Information
Guideline: VREF Sources and VREF Pins on page 5-83
Describes VREF restrictions related to the I/O lanes.
I/O Buffer and Registers in Arria 10 Devices
I/O registers are composed of the input path for handling data from the pin to the core, the output path
for handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to
the output buffer. These registers allow faster source-synchronous register-to-register transfers and
resynchronization.
The input and output paths contains the following blocks:
• Input registers—support half/full rate data transfer from peripheral to core, and support double or
single data rate data capture from I/O buffer.
• Output registers—support half/full rate data transfer from core to peripheral, and support double or
single data rate data transfer to I/O buffer.
• OE registers—support half or full rate data transfer from core to peripheral, and support single data
rate data transfer to I/O buffer.
The input and output paths also support the following features:
•
•
•
•
Clock enable.
Asynchronous or synchronous reset.
Bypass mode for input and output paths.
Delays chains on input and output paths.
Figure 5-12: IOE Structure for Arria 10 Devices
This figure shows the Arria 10 FPGA IOE structure.
Core
GPIO
Register
Buffer
OE
Path
IO_OE
Delay Chain
Write Data from Core
Output
Path
IO_OUT
Delay Chain
Read Data to Core
Input
Path
IO_IN
Delay Chain
OE from Core
Bypass Mode from Core
Bypass Mode to Core
Features of I/O Pins in Arria 10 Devices
Open-Drain Output on page 5-27
Bus-Hold Circuitry on page 5-28
Weak Pull-up Resistor on page 5-28
Open-Drain Output
The optional open-drain output for each I/O pin is equivalent to an open collector output. If it is
configured as an open drain, the logic value of the output is either high-Z or logic low.
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Bus-Hold Circuitry
Use an external resistor to pull the signal to a logic high.
Bus-Hold Circuitry
Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the
device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of
the configuration.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH), approximately 7 kΩ, to weakly pull
the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next
input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to
hold a signal level when the bus is tri-stated.
For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from
the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent
over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the VCCIO
level.
If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the
I/O pin for differential signals, disable the bus-hold feature.
Weak Pull-up Resistor
Each I/O pin provides an optional programmable pull-up resistor during user mode. The pull-up resistor,
typically 25 kΩ, weakly holds the I/O to the VCCIO level.
The Arria 10 device supports programmable weak pull-up resistors only on user I/O pins but not on
dedicated configuration pins, dedicated clock pins, or JTAG pins .
If you enable this option, you cannot use the bus-hold feature.
Programmable IOE Features in Arria 10 Devices
Table 5-18: Arria 10 Programmable IOE Features Settings and Assignment Name
Feature
Setting
Condition
Quartus Prime
Assignment Name
Slew Rate Control
0 (Slow), 1 (Fast).
Default is 1.
Disabled if you use the
RS OCT feature.
I/O Delay
Refer to the device
datasheet
—
SLEW_RATE
INPUT_DELAY_CHAIN
OUTPUT_DELAY_CHAIN
Open-Drain Output
On, Off. Default is Off
—
Bus-Hold
On, Off. Default is Off.
Disabled if you use the
weak pull-up resistor
feature.
Weak Pull-up
Resistor
On, Off. Default is Off.
Disabled if you use the
bus-hold feature.
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AUTO_OPEN_DRAIN_PINS
ENABLE_BUS_HOLD_CIRCUITRY
WEAK_PULL_UP_RESISTOR
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Programmable IOE Features in Arria 10 Devices
Feature
Setting
Condition
Quartus Prime
Assignment Name
Pre-Emphasis
0 (disabled), 1
(enabled). Default is 1.
—
PROGRAMMABLE_PREEMPHASIS
Differential Output
Voltage
0 (low), 1 (medium
low), 2 (medium high),
3 (high). Default is 2.
—
PROGRAMMABLE_VOD
Table 5-19: Arria 10 Programmable IOE Features I/O Standards and Buffer Types Support
I/O Buffer Type Support
Feature
I/O Standards Support
LVDS I/O
3 V I/O
HPS I/O
(SoC Devices Only)
Slew Rate Control
I/O Delay
Open-Drain Output
Bus-Hold
Weak Pull-up
Resistor
Pre-Emphasis
• 3.0 V LVTTL
• 1.2 V, 1.5 V, 1.8 V, and 3.0 V
LVCMOS
• SSTL-18, SSTL-15, SSTL-135,
SSTL-125, and SSTL-12
• 1.2 V, 1.5 V, and 1.8 V HSTL
• HSUL-12
• POD12
• Differential SSTL-18, Differential
SSTL-15, Differential SSTL-135,
Differential
SSTL-125, and Differential SSTL-12
• Differential 1.2 V, 1.5 V, and 1.8 V
HSTL
• Differential HSUL-12
• 3.0 V LVTTL
• 1.2 V, 1.5 V, 1.8 V, and 3.0 V
LVCMOS
•
•
•
•
•
LVDS
RSDS
Mini-LVDS
LVPECL
Differential POD12
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Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
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Programmable Current Strength
I/O Buffer Type Support
Feature
LVDS I/O
I/O Standards Support
3 V I/O
HPS I/O
(SoC Devices Only)
Differential Output
Voltage
•
•
•
•
Yes
LVDS
RSDS
Mini-LVDS
LVPECL
Yes
—
Related Information
•
•
•
•
•
•
•
Programmable IOE Delay
Programmable Current Strength on page 5-30
Programmable Output Slew-Rate Control on page 5-31
Programmable IOE Delay on page 5-31
Programmable Open-Drain Output on page 5-32
Programmable Pre-Emphasis on page 5-32
Programmable Differential Output Voltage on page 5-33
Programmable Current Strength
You can use the programmable current strength to mitigate the effects of high signal attenuation that is
caused by a long transmission line or a legacy backplane.
Table 5-20: Programmable Current Strength Settings for Arria 10 Devices
The output buffer for each Arria 10 device I/O pin has a programmable current strength control for the I/O
standards listed in this table.
I/O Standard
IOH / IOL Current Strength Setting (mA) or
DDR3 OCT Setting (Ω)
(Default setting in bold)
(SoC Devices Only)
(7)
3.0 V LVTTL/3.0 V CMOS
16, 12, 8, 4
16, 12, 8, 4
2.5 V LVCMOS
16, 12, 8, 4
16, 12, 8, 4
1.8 V LVCMOS
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
1.5 V LVCMOS
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
1.2 V LVCMOS
8, 6, 4, 2
—
SSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
SSTL-18 Class II
16
8, 16
SSTL-15 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
SSTL-15 Class II
16
8, 16
12, 10, 8, 6, 4
12, 10, 8, 6, 4
1.8 V HSTL Class I
(7)
Supported in HPS
The programmable current strength information for the HPS is preliminary.
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Programmable Output Slew-Rate Control
I/O Standard
IOH / IOL Current Strength Setting (mA) or
DDR3 OCT Setting (Ω)
(Default setting in bold)
5-31
Supported in HPS
(SoC Devices Only)
(7)
1.8 V HSTL Class II
16
16
1.5 V HSTL Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
1.5 V HSTL Class II
16
16
1.2 V HSTL Class I
12, 10, 8, 6, 4
—
1.2 V HSTL Class II
16
—
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best current
strength setting for your specific application.
Programmable Output Slew-Rate Control
The programmable output slew-rate control in the output buffer of each regular- and dual-function I/O
pin allows you to configure the following:
• Fast slew-rate—provides high-speed transitions for high-performance systems.
• Slow slew-rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling
edges.
You can specify the slew-rate on a pin-by-pin basis because each I/O pin contains a slew-rate control.
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best slew rate
setting for your specific application.
Programmable IOE Delay
You can activate the programmable IOE delays to ensure zero hold times, minimize setup times, or
increase clock-to-output times. This feature helps read and write timing margins because it minimizes the
uncertainties between signals in the bus.
Each pin can have a different input delay from pin-to-input register or a delay from output
register-to-output pin values to ensure that the signals within a bus have the same delay going into or out
of the device.
• In the output and OE paths, there are the output and OE delays which have 50 ps incremental delays
and a maximum delay of 800 ps.
• In the input paths, there are two input delay chains with incremental delays of 50 ps and a maximum
delay of 3.2 ns.
For more information about the programmable IOE delay specifications, refer to the device datasheet.
Related Information
Programmable IOE Delay
(7)
The programmable current strength information for the HPS is preliminary.
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Programmable Open-Drain Output
Programmable Open-Drain Output
An open-drain output provides a high-impedance state on output when logic-to-pin is high. If logic-topin is low, output is low.
You can attach several open-drain output to a wire. This connection type is like a logical OR function and
is commonly called an active-low wired-OR circuit. If at least one of the outputs is in logic 0 state (active),
the circuit sinks the current and brings the line to low voltage.
You can use open-drain output if you are connecting multiple devices to a bus. For example, you can use
the open-drain output for system-level control signals that can be asserted by any device or as an
interrupt.
You can enable the open-drain output assignment using one these methods:
• Design the tristate buffer using OPNDRN primitive.
• Turn on the Auto Open-Drain Pins option in the Quartus Prime software.
Although you can design open-drain output without enabling the option assignment, you will not be
using the open-drain output feature of the I/O buffer. The open-drain output feature in the I/O buffer
provides you the best propagation delay from OE to output.
Programmable Pre-Emphasis
The VOD setting and the output impedance of the driver set the output current limit of a high-speed
transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full VOD level
before the next edge, producing pattern-dependent jitter. With pre-emphasis, the output current is
boosted momentarily during switching to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus
helps to compensate for the frequency-dependent attenuation along the transmission line. The overshoot
introduced by the extra current happens only during a change of state switching to increase the output
slew rate and does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis
required depends on the attenuation of the high-frequency component along the transmission line.
Figure 5-13: Programmable Pre-Emphasis
This figure shows the LVDS output with pre-emphasis.
Voltage boost
from pre-emphasis
OUT
VP
V OD
OUT
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VP
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voltage (peak–peak)
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Table 5-21: Quartus Prime Software Assignment Editor—Programmable Pre-Emphasis
This table lists the assignment name for programmable pre-emphasis and its possible values in the Quartus Prime
software Assignment Editor.
Field
Assignment
To
tx_out
Assignment name
Programmable Pre-emphasis
Allowed values
0 (disabled), 1 (enabled). Default is 1.
Programmable Differential Output Voltage
The programmable VOD settings allow you to adjust the output eye opening to optimize the trace length
and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller
VOD swing reduces power consumption. You can statically adjust the VOD of the differential signal by
changing the VOD settings in the Quartus Prime software Assignment Editor.
Figure 5-14: Differential VOD
This figure shows the VOD of the differential LVDS output.
Single-Ended Waveform
Positive Channel (p)
VOD
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD (diff peak - peak) = 2 x VOD (single-ended)
VOD
p-n=0V
VOD
Table 5-22: Quartus Prime Software Assignment Editor—Programmable VOD
This table lists the assignment name for programmable VOD and its possible values in the Quartus Prime software
Assignment Editor. Value "0" is available for the RSDS and mini-LVDS I/O standards only, and is not available for
the LVDS I/O standard.
Field
Assignment
To
tx_out
Assignment name
Programmable Differential Output Voltage (VOD)
Allowed values
0 (low), 1 (medium low), 2 (medium high), 3 (high).
Default is 2.
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On-Chip I/O Termination in Arria 10 Devices
On-Chip I/O Termination in Arria 10 Devices
Serial (RS) and parallel (RT) OCT provides I/O impedance matching and termination capabilities. OCT
maintains signal quality, saves board space, and reduces external component costs.
The Arria 10 devices support OCT in all FPGA and HPS I/O banks. For the 3 V and HPS I/Os, the I/Os
support only OCT without calibration.
Figure 5-15: Single-ended Termination (RS and RT)
This figure shows the single-ended termination schemes supported in Arria 10 device. RT1 and RT2 are
dynamic parallel terminations and are enabled only if the device is receiving. In bidirectional applications,
RT1 and RT2 are automatically switched on when the device is receiving and switched off when the device
is driving.
Driving Device
Receiving Device
V CCIO
V CCIO
2 × R T2
2 × R T1
RS
Z 0 = 50 Ω
V REF
2 × R T1
2 × R T2
GND
GND
Table 5-23: OCT Schemes Supported in Arria 10 Devices
Direction
Output
Input
OCT Schemes
I/O Type Support
LVDS I/O
3 V I/O
HPS I/O
RS OCT with calibration
Yes
—
—
RS OCT without calibration
Yes
Yes
Yes
RT OCT with calibration
Yes
—
—
RD OCT (LVDS I/O standard
only)
Yes
—
—
Dynamic RS and RT OCT
Yes
Yes
Yes
Bidirectional
Related Information
•
•
•
•
•
•
Altera Corporation
Altera OCT IP Core User Guide
RS OCT without Calibration in Arria 10 Devices on page 5-35
RS OCT with Calibration in Arria 10 Devices on page 5-36
RT OCT with Calibration in Arria 10 Devices on page 5-38
Dynamic OCT on page 5-40
Differential Input RD OCT on page 5-42
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• OCT Calibration Block in Arria 10 Devices on page 5-42
RS OCT without Calibration in Arria 10 Devices
The Arria 10 devices support RS OCT for single-ended and voltage-referenced I/O standards. RS OCT
without calibration is supported on output only.
Table 5-24: Selectable I/O Standards for RS OCT Without Calibration
This table lists the output termination settings for uncalibrated OCT on different I/O standards.
I/O Standard
Device Variant Support
Uncalibrated OCT (Output)
RS (Ω)
3.0 V LVTTL/3.0 V LVCMOS
GX, SX
25/50
2.5 V LVCMOS
GX, SX
25/50
1.8 V LVCMOS
All
25/50
1.5 V LVCMOS
All
25/50
1.2 V LVCMOS
All
25/50
SSTL-18 Class I
All
50
SSTL-18 Class II
All
25
SSTL-15 Class I
All
50
SSTL-15 Class II
All
25
SSTL-15
All
34, 40
SSTL-135
All
34, 40
SSTL-125
All
34, 40
SSTL-12
All
40, 60, 240
POD12
All
34, 40, 48, 60
1.8 V HSTL Class I
All
50
1.8 V HSTL Class II
All
25
1.5 V HSTL Class I
All
50
1.5 V HSTL Class II
All
25
1.2 V HSTL Class I
All
50
1.2 V HSTL Class II
All
25
HSUL-12
All
34.3, 40, 48, 60, 80
Differential SSTL-18 Class I
All
50
Differential SSTL-18 Class II
All
25
Differential SSTL-15 Class I
All
50
Differential SSTL-15 Class II
All
25
Differential SSTL-15
All
34, 40
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RS OCT with Calibration in Arria 10 Devices
I/O Standard
Uncalibrated OCT (Output)
Device Variant Support
RS (Ω)
Differential SSTL-135
All
34, 40
Differential SSTL-125
All
34, 40
Differential SSTL-12
All
40, 60, 240
Differential POD12
All
34, 40, 48, 60
Differential 1.8 V HSTL Class I
All
50
Differential 1.8 V HSTL Class II
All
25
Differential 1.5 V HSTL Class I
All
50
Differential 1.5 V HSTL Class II
All
25
Differential 1.2 V HSTL Class I
All
50
Differential 1.2 V HSTL Class II
All
25
Differential HSUL-12
All
34.3, 40, 48, 60, 80
Driver-impedance matching provides the I/O driver with controlled output impedance that closely
matches the impedance of the transmission line. As a result, you can significantly reduce signal reflections
on PCB traces.
If you select matching impedance, current strength is no longer selectable.
Figure 5-16: RS OCT Without Calibration
This figure shows the RS as the intrinsic impedance of the output transistors.
Receiving
Device
Driver
Series Termination
V CCIO
RS
Z 0 = 50 Ω
RS
GND
Related Information
On-Chip I/O Termination in Arria 10 Devices on page 5-34
RS OCT with Calibration in Arria 10 Devices
The Arria 10 devices support RS OCT with calibration in all LVDS I/O banks.
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Table 5-25: Selectable I/O Standards for RS OCT With Calibration
This table lists the output termination settings for calibrated OCT on different I/O standards.
Calibrated OCT (Output)
Device Variant
Support
RS (Ω)
RZQ (Ω)
1.8 V LVCMOS
All
25, 50
100
1.5 V LVCMOS
All
25, 50
100
1.2 V LVCMOS
All
25, 50
100
SSTL-18 Class I
All
50
100
SSTL-18 Class II
All
25
100
SSTL-15 Class I
All
50
100
SSTL-15 Class II
All
25
100
SSTL-15
All
25, 50
100
34, 40
240
SSTL-135
All
34, 40
240
SSTL-125
All
34, 40
240
SSTL-12
All
40, 60, 240
240
POD12
All
34, 40, 48, 60
240
1.8 V HSTL Class I
All
50
100
1.8 V HSTL Class II
All
25
100
1.5 V HSTL Class I
All
50
100
1.5 V HSTL Class II
All
25
100
1.2 V HSTL Class I
All
50
100
1.2 V HSTL Class II
All
25
100
HSUL-12
All
34, 40, 48, 60, 80
240
Differential SSTL-18 Class I
All
50
100
Differential SSTL-18 Class II
All
25
100
Differential SSTL-15 Class I
All
50
100
Differential SSTL-15 Class II
All
25
100
Differential SSTL-15
All
25, 50
100
34, 40
240
Differential SSTL-135
All
34, 40
240
Differential SSTL-125
All
34, 40
240
Differential SSTL-12
All
40, 60, 240
240
Differential POD12
All
34, 40, 48, 60
240
Differential 1.8 V HSTL Class I
All
50
100
I/O Standard
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RT OCT with Calibration in Arria 10 Devices
Calibrated OCT (Output)
I/O Standard
Device Variant
Support
RS (Ω)
RZQ (Ω)
Differential 1.8 V HSTL Class II
All
25
100
Differential 1.5 V HSTL Class I
All
50
100
Differential 1.5 V HSTL Class II
All
25
100
Differential 1.2 V HSTL Class I
All
50
100
Differential 1.2 V HSTL Class II
All
25
100
Differential HSUL-12
All
34, 40, 48, 60, 80
240
The RS OCT calibration circuit compares the total impedance of the I/O buffer to the external reference
resistor connected to the RZQ pin and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. When the calibration circuit finds the correct
impedance, the circuit powers down and stops changing the characteristics of the drivers.
Figure 5-17: RS OCT with Calibration
This figure shows the RS as the intrinsic impedance of the output transistors.
Driver
Series Termination
Receiving
Device
V CCIO
RS
Z 0 = 50 Ω
RS
GND
Related Information
On-Chip I/O Termination in Arria 10 Devices on page 5-34
RT OCT with Calibration in Arria 10 Devices
The Arria 10 devices support RT OCT with calibration in all LVDS I/O banks but not in the 3 V I/O
banks. RT OCT with calibration is available only for configuration of input and bidirectional pins. Output
pin configurations do not support RT OCT with calibration. If you use RT OCT, the VCCIO of the bank
must match the I/O standard of the pin where you enable the RT OCT.
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5-39
Table 5-26: Selectable I/O Standards for RT OCT With Calibration
This table lists the input termination settings for calibrated OCT on different I/O standards.
Calibrated OCT (Input)
Device Variant
Support
RT (Ω)
RZQ (Ω)
SSTL-18 Class I
All
50
100
SSTL-18 Class II
All
50
100
SSTL-15 Class I
All
50
100
SSTL-15 Class II
All
50
100
SSTL-15
All
30, 40, 60,120
240
SSTL-135
All
30, 40, 60, 120
240
SSTL-125
All
30, 40, 60, 120
240
SSTL-12
All
60, 120
240
POD12
All
34, 40, 48, 60, 80,
120, 240
240
1.8 V HSTL Class I
All
50
100
1.8 V HSTL Class II
All
50
100
1.5 V HSTL Class I
All
50
100
1.5 V HSTL Class II
All
50
100
.2 V HSTL Class I
All
50
100
1.2 V HSTL Class II
All
50
100
Differential SSTL-18 Class I
All
50
100
Differential SSTL-18 Class II
All
50
100
Differential SSTL-15 Class I
All
50
100
Differential SSTL-15 Class II
All
50
100
Differential SSTL-15
All
30, 40, 60,120
240
Differential SSTL-135
All
30, 40, 60, 120
240
Differential SSTL-125
All
30, 40, 60, 120
240
Differential SSTL-12
All
60, 120
240
Differential POD12
All
34, 40, 48, 60, 80,
120, 240
240
Differential 1.8 V HSTL
Class I
All
50
100
Differential 1.8 V HSTL
Class II
All
50
100
Differential 1.5 V HSTL
Class I
All
50
100
I/O Standard
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Dynamic OCT
Calibrated OCT (Input)
Device Variant
Support
RT (Ω)
RZQ (Ω)
Differential 1.5 V HSTL
Class II
All
50
100
Differential 1.2 V HSTL
Class I
All
50
100
Differential 1.2 V HSTL
Class II
All
50
100
I/O Standard
The RT OCT calibration circuit compares the total impedance of the I/O buffer to the external resistor
connected to the RZQ pin. The circuit dynamically enables or disables the transistors until the total
impedance of the I/O buffer matches the external resistor.
Calibration occurs at the end of the device configuration. When the calibration circuit finds the correct
impedance, the circuit powers down and stops changing the characteristics of the drivers.
Figure 5-18: RT OCT with Calibration
Transmitter
Receiving Device
V CCIO
2 × R T2
Z 0 = 50 Ω
V REF
2 × R T2
GND
Related Information
On-Chip I/O Termination in Arria 10 Devices on page 5-34
Dynamic OCT
Dynamic OCT is useful for terminating a high-performance bidirectional path by optimizing the signal
integrity depending on the direction of the data. Dynamic OCT also helps save power because device
termination is internal—termination switches on only during input operation and thus draw less static
power.
Note: If you use the SSTL-15, SSTL-135, and SSTL-125 I/O standards with the DDR3 memory interface,
Altera recommends that you use OCT with these I/O standards to save board space and cost. OCT
reduces the number of external termination resistors used.
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Dynamic OCT
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Table 5-27: Dynamic OCT Based on Bidirectional I/O
Dynamic RT OCT or RS OCT is enabled or disabled based on whether the bidirectional I/O acts as a receiver or
driver.
Dynamic OCT
Dynamic RT OCT
Dynamic RS OCT
Bidirectional I/O
State
Acts as a receiver
Enabled
Acts as a driver
Disabled
Acts as a receiver
Disabled
Acts as a driver
Enabled
Figure 5-19: Dynamic RT OCT in Arria 10 Devices
Related Information
On-Chip I/O Termination in Arria 10 Devices on page 5-34
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Differential Input RD OCT
Differential Input RD OCT
All I/O pins and dedicated clock input pins in Arria 10 devices support on-chip differential termination,
RD OCT. The Arria 10 devices provide a 100 Ω, on-chip differential termination option on each differen‐
tial receiver channel for LVDS standards.
You can enable on-chip termination in the Quartus Prime software Assignment Editor.
Figure 5-20: On-Chip Differential I/O Termination
Differential Receiver
with On-Chip 100 Ω
Termination
LVDS
Transmitter
Z 0 = 50 Ω
RD
Z 0 = 50 Ω
Table 5-28: Quartus Prime Software Assignment Editor—On-Chip Differential Termination
This table lists the assignment name for on-chip differential termination in the Quartus Prime software
Assignment Editor.
Field
Assignment
To
rx_in
Assignment name
Input Termination
Value
Differential
Related Information
On-Chip I/O Termination in Arria 10 Devices on page 5-34
OCT Calibration Block in Arria 10 Devices
You can calibrate the OCT using the OCT calibration block available in each I/O bank.
You can use RS and RT OCT in the same I/O bank for different I/O standards if the I/O standards use the
same VCCIO supply voltage. You cannot configure the RS OCT and the programmable current strength for
the same I/O buffer.
The OCT calibration process uses the RZQ pin that is available in every calibration block in a given I/O
bank for series- and parallel-calibrated termination:
• Each OCT calibration block has an external 240 Ω reference resistor associated with it through the RZQ
pin.
• Connect the RZQ pin to GND through an external 100 Ω or 240 Ω resistor (depending on the RS or RT
OCT value).
• The RZQ pin shares the same VCCIO supply voltage with the I/O bank where the pin is located.
• The RZQ pin is a dual-purpose I/O pin and functions as a general purpose I/O pin if you do not use
the calibration circuit.
Arria 10 devices support calibrated RS and calibrated RT OCT on all LVDS I/O pins except for dedicated
configuration pins.
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Related Information
• Altera OCT IP Core User Guide
• On-Chip I/O Termination in Arria 10 Devices on page 5-34
External I/O Termination for Arria 10 Devices
Table 5-29: External Termination Schemes for Different I/O Standards
I/O Standard
External Termination Scheme
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
No external termination required
1.2 V LVCMOS
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
Single-Ended SSTL I/O Standard Termination
SSTL-15 Class II
SSTL-15 (8)
SSTL-135 (8)
SSTL-125 (8)
No external termination required
SSTL-12(8)
POD12
Single-Ended POD I/O Standard Termination
Differential SSTL-18 Class I
Differential SSTL-18 Class II
Differential SSTL-15 Class I
Differential SSTL I/O Standard Termination
Differential SSTL-15 Class II
Differential SSTL-15 (8)
Differential SSTL-135 (8)
Differential SSTL-125 (8)
No external termination required
Differential SSTL-12(8)
Differential POD12
(8)
Differential POD I/O Standard Termination
Altera recommends that you use OCT with these I/O standards to save board space and cost. OCT reduces
the number of external termination resistors used.
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Single-Ended I/O Termination
I/O Standard
External Termination Scheme
1.8 V HSTL Class I
1.8 V HSTL Class II
1.5 V HSTL Class I
1.5 V HSTL Class II
Single-Ended HSTL I/O Standard Termination
1.2 V HSTL Class I
1.2 V HSTL Class II
HSUL-12
No external termination required
Differential 1.8 V HSTL Class I
Differential 1.8 V HSTL Class II
Differential 1.5 V HSTL Class I
Differential 1.5 V HSTL Class II
Differential HSTL I/O Standard Termination
Differential 1.2 V HSTL Class I
Differential 1.2 V HSTL Class II
Differential HSUL-12
No external termination required
LVDS
LVDS I/O Standard Termination
RSDS
Mini-LVDS
LVPECL
RSDS/mini-LVDS I/O Standard Termination
Differential LVPECL I/O Standard Termination
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best termination
scheme for your specific application.
Single-Ended I/O Termination
Voltage-referenced I/O standards require an input VREF and a termination voltage (VTT). The reference
voltage of the receiving device tracks the termination voltage of the transmitting device.
The supported I/O standards such as SSTL-12, SSTL-125, SSTL-135, and SSTL-15 typically do not require
external board termination.
Altera recommends that you use OCT with these I/O standards to save board space and cost. OCT
reduces the number of external termination resistors used.
Note: You cannot use RS and RT OCT simultaneously. For more information, refer to the related
information.
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Single-Ended I/O Termination
Figure 5-21: SSTL I/O Standard Termination
This figure shows the details of SSTL I/O termination on Arria 10 devices.
Termination
SSTL Class I
SSTL Class II
V TT
V TT
50 Ω
25 Ω
V TT
50 Ω
50 Ω
External
On-Board
Termination
25 Ω
V REF
Transmitter
Receiver
Receiver
V TT
V TT
Series OCT 25 Ω
50 Ω
OCT Transmit
V REF
Transmitter
V TT
Series OCT 50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
V REF
V REF
Transmitter
Receiver
Transmitter
Receiver
V TT
FPGA
Parallel OCT
V CCIO
50 Ω
OCT Receive
100 Ω
50 Ω
25 Ω
V REF
V REF
100 Ω
GND
Transmitter
Receiver
100 Ω
GND
Transmitter
V CCIO
Series
OCT 25 Ω
V REF
100 Ω
100 Ω
FPGA
I/O and High Speed I/O in Arria 10 Devices
100 Ω
V REF
V CCIO
100 Ω
50 Ω
100 Ω
GND
Receiver
V REF
50 Ω
OCT in
Bidirectional
Pins
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100 Ω
V CCIO
V CCIO
Series
OCT 50 Ω
FPGA
Parallel OCT
V CCIO
50 Ω
100 Ω
25 Ω
50 Ω
50 Ω
GND
100 Ω
Series
OCT 50 Ω
FPGA
GND
FPGA
100 Ω
V REF
GND
Series
OCT 25 Ω
FPGA
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Single-Ended I/O Termination
Figure 5-22: HSTL I/O Standard Termination
This figure shows the details of HSTL I/O termination on the Arria 10 devices.
Termination
HSTL Class II
HSTL Class I
V TT
V TT
50 Ω
V TT
50 Ω
External
On-Board
Termination
50 Ω
50 Ω
50 Ω
V REF
V REF
Transmitter
Transmitter
Receiver
Receiver
V TT
V TT
V TT
Series OCT 50 Ω
Series OCT 25 Ω
50 Ω
OCT Transmit
50 Ω
50 Ω
50 Ω
50 Ω
V REF
V REF
Transmitter
Transmitter
Receiver
V CCIO
Receiver
V TT
FPGA
Parallel OCT
100 Ω
50 Ω
50 Ω
V REF
V REF
100 Ω
100 Ω
Transmitter
Receiver
GND
V CCIO
Series
OCT 50 Ω
Transmitter
V CCIO
Series
OCT 25 Ω
100 Ω
100 Ω
GND
FPGA
Altera Corporation
V REF
100 Ω
50 Ω
100 Ω
V REF
V CCIO
100 Ω
50 Ω
OCT in
Bidirectional
Pins
Receiver
GND
V CCIO
V REF
100 Ω
FPGA
Parallel OCT
50 Ω
100 Ω
OCT Receive
V CCIO
GND
100 Ω
Series
OCT 50 Ω
FPGA
GND
FPGA
100 Ω
V REF
GND
Series
OCT 25 Ω
FPGA
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Figure 5-23: POD I/O Standard Termination
This figure shows the details of POD I/O termination on the Arria 10 devices.
POD
Termination
V CCIO
External
On-Board
Termination
Transmitter
Receiver
40 Ω
50 Ω
VREF
V CCIO
OCT
Transmit
Transmitter
Receiver
40 Ω
50 Ω
VREF
Series OCT, RS
V CCIO
OCT
Receive
Transmitter
Receiver
40 Ω
50 Ω
VREF
Parallel OCT RT
FPGA
V CCIO
OCT in
Bidirectional
Pins
Series
OCT RS
Series OCT RS
V CCIO
Parallel
OCT, RT
40 Ω
50 Ω
VREF
VREF
Related Information
Dynamic OCT on page 5-40
Differential I/O Termination for Arria 10 Devices
The I/O pins are organized in pairs to support differential I/O standards. Each I/O pin pair can support
differential input and output buffers.
The supported I/O standards such as Differential SSTL-12, Differential SSTL-15, Differential SSTL-125,
and Differential SSTL-135 typically do not require external board termination.
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Differential HSTL, SSTL, HSUL, and POD Termination
Altera recommends that you use OCT with these I/O standards to save board space and cost. OCT
reduces the number of external termination resistors used.
Related Information
• Differential HSTL, SSTL, HSUL, and POD Termination on page 5-48
• LVDS, RSDS, and Mini-LVDS Termination on page 5-50
• LVPECL Termination on page 5-51
Differential HSTL, SSTL, HSUL, and POD Termination
Differential HSTL, SSTL, HSUL, and POD inputs use LVDS differential input buffers. However, RD
support is only available if the I/O standard is LVDS.
Differential HSTL, SSTL, HSUL, and POD outputs are not true differential outputs. These I/O standards
use two single-ended outputs with the second output programmed as inverted.
Figure 5-24: Differential SSTL I/O Standard Termination
This figure shows the details of Differential SSTL I/O termination on Arria 10 devices.
Termination
Differential SSTL Class I
Differential SSTL Class II
V TT
50 Ω
25 Ω
V TT
V TT
50 Ω
50 Ω
V TT
V TT
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
25 Ω
External
On-Board
Termination
25 Ω
25 Ω
50 Ω
50 Ω
Transmitter
Receiver
Transmitter
V CCIO
Series OCT 25 Ω
Series OCT 50 Ω
Receiver
OCT
V CCIO
V TT
50 Ω
100 Ω
Z 0 = 50 Ω
V CCIO
100 Ω
Z 0 = 50 Ω
V TT
V CCIO
100 Ω
100 Ω
50 Ω
100 Ω
GND
Z 0 = 50 Ω
100 Ω
GND
Z 0 = 50 Ω
100 Ω
Transmitter
Altera Corporation
V TT
GND
100 Ω
Receiver
Transmitter
GND
Receiver
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Figure 5-25: Differential HSTL I/O Standard Termination
This figure shows the details of Differential HSTL I/O standard termination on Arria 10 devices.
Termination
Differential HSTL Class I
Differential HSTL Class II
V TT
50 Ω
V TT
V TT
50 Ω
50 Ω
V TT
V TT
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
V TT
50 Ω
External
On-Board
Termination
Transmitter
Receiver
V CCIO
Series OCT 50 Ω
Transmitter
Series OCT 25 Ω
Receiver
V TT
50 Ω
100 Ω
Z 0 = 50 Ω
OCT
V CCIO
V CCIO
100 Ω
Z 0 = 50 Ω
V TT
V CCIO
100 Ω
100 Ω
50 Ω
100 Ω
GND
Z 0 = 50 Ω
100 Ω
GND
Z 0 = 50 Ω
100 Ω
Transmitter
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100 Ω
Receiver
Transmitter
GND
Receiver
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LVDS, RSDS, and Mini-LVDS Termination
Figure 5-26: Differential POD I/O Standard Termination
This figure shows the details of Differential POD I/O termination on the Arria 10 devices.
Differential POD
Termination
V CCIO V CCIO
40 Ω
40 Ω
50 Ω
External
On-Board
Termination
50 Ω
Transmitter
Series OCT R
Receiver
V CCIO
Parallel OCT, R
S
T
RT
Z 0 = 50 Ω
OCT
V CCIO
RT
Z 0 = 50 Ω
Transmitter
Receiver
Related Information
Differential I/O Termination for Arria 10 Devices on page 5-47
LVDS, RSDS, and Mini-LVDS Termination
All I/O banks have dedicated circuitry to support the true LVDS, RSDS, and mini-LVDS I/O standards by
using true LVDS output buffers without resistor networks.
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LVPECL Termination
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Figure 5-27: LVDS I/O Standard Termination
This figure shows the LVDS I/O standard termination. The on-chip differential resistor is available in all
I/O banks.
Termination
LVDS
Differential Outputs
Differential Inputs
50 Ω
External
On-Board
Termination
100 Ω
50 Ω
Differential Outputs
OCT Receiver
(True LVDS
Output)
Differential Inputs
OCT
50 Ω
100 Ω
50 Ω
Receiver
Related Information
• Differential I/O Standards Specifications
• National Semiconductor (www.national.com)
For more information about the RSDS I/O standard, refer to the RSDS Specification on the National
Semiconductor web site.
• Differential I/O Termination for Arria 10 Devices on page 5-47
LVPECL Termination
The Arria 10 devices support the LVPECL I/O standard on input clock pins only:
• LVPECL input operation is supported using LVDS input buffers.
• LVPECL output operation is not supported.
Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL
input common-mode voltage.
Note: Altera recommends that you use IBIS models to verify your LVPECL AC/DC-coupled termination.
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High Speed Source-Synchronous SERDES and DPA in Arria 10 Devices
Figure 5-28: LVPECL AC-Coupled Termination
LVPECL
Output Buffer
LVPECL
Input Buffer
0.1 µF
V ICM
Z 0 = 50 Ω
50 Ω
0.1 µF
Z 0 = 50 Ω
50 Ω
Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the
Arria 10 LVPECL input buffer specification.
Figure 5-29: LVPECL DC-Coupled Termination
LVPECL
Output Buffer
LVPECL
Input Buffer
Z 0 = 50 Ω
100 Ω
Z 0 = 50 Ω
For information about the VICM specification, refer to the device datasheet.
Related Information
• Differential I/O Standards Specifications
• Differential I/O Termination for Arria 10 Devices on page 5-47
High Speed Source-Synchronous SERDES and DPA in Arria 10 Devices
The high-speed differential I/O interfaces and DPA features in Arria 10 devices provide advantages over
single-ended I/Os and contribute to the achievable overall system bandwidth. Arria 10 devices support the
LVDS, mini-LVDS, and reduced swing differential signaling (RSDS) differential I/O standards.
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SERDES Circuitry
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Figure 5-30: I/O Bank Support for High-Speed Differential I/O
This figure shows the I/O bank support for high-speed differential I/O in the Arria 10 devices.
LVDS I/Os
I/Os with
Dedicated
SERDES Circuitry
LVDS Interface
with 'Use External PLL'
Option Enabled
LVDS Interface
with 'Use External PLL'
Option Disabled
Related Information
• I/O Standards Support for FPGA I/O in Arria 10 Devices on page 5-2
Provides information about the supported differential I/O standards.
• GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
• FPGA I/O Resources in Arria 10 GX Packages on page 5-12
Provides the number of LVDS channels.
• FPGA I/O Resources in Arria 10 GT Packages on page 5-14
Provides the number of LVDS channels.
• FPGA I/O Resources in Arria 10 SX Packages on page 5-14
Provides the number of LVDS channels.
• Altera LVDS SERDES IP Core User Guide
SERDES Circuitry
Each LVDS I/O channel in Arria 10 devices have built-in serializer/deserializer (SERDES) circuitry that
supports high-speed LVDS interfaces. You can configure the SERDES circuitry to support sourcesynchronous communication protocols such as RapidIO®, XSBI, serial peripheral interface (SPI), and
asynchronous protocols.
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SERDES I/O Standards Support in Arria 10 Devices
Figure 5-31: SERDES
This figure shows a transmitter and receiver block diagram for the LVDS SERDES circuitry with the
interface signals of the transmitter and receiver data paths. The figure shows a shared PLL between the
transmitter and receiver. If the transmitter and receiver do not share the same PLL, you require two I/O
PLLs. In single data rate (SDR) and double data rate (DDR) modes, the data width is 1 and 2 bits,
respectively.
2
Serializer
tx_in
IOE supports SDR, DDR, or non-registered datapath
+
–
DIN DOUT
tx_out
LVDS Transmitter
tx_coreclock
3 (load_enable, fast_clock, tx_coreclock)
IOE supports SDR, DDR, or non-registered datapath
Deserializer
Bit Slip
10
FPGA
Fabric
rx_divfwdclk
rx_coreclock
DOUT
LVDS Receiver
IOE
DIN
DOUT
DIN
fast_clock
2
(load_enable,
fast_clock) Clock Mux
Synchronizer
DOUT
DIN
+ rx_in
–
DPA Circuitry
Retimed
DIN
Data
DPA Clock
dpa_fast_clock
rx_out
2
10
fast_clock
10 bits
maximum
data width
10
IOE
3
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
DPA Clock Domain
LVDS Clock Domain
I/O PLL
8 Serial LVDS
Clock Phases
rx_inclock / tx_inclock
The Altera LVDS SERDES transmitter and receiver requires various clock and load enable signals from an
I/O PLL. The Quartus Prime software configures the PLL settings automatically. The software is also
responsible for generating the various clock and load enable signals based on the input reference clock
and selected data rate.
Note: For the maximum data rate supported by the Arria 10 devices, refer to the device overview.
Related Information
• Summary of Features, Arria 10 Device Overview
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
SERDES I/O Standards Support in Arria 10 Devices
These tables list the I/O standards supported by the SERDES receiver and transmitter, and the respective
Quartus Prime software assignment values. The SERDES receiver and transmitter also support all
differential HSTL, differential HSUL, and differential SSTL I/O standards.
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Table 5-30: SERDES Receiver I/O Standards Support—Preliminary
I/O Standard
Quartus Prime Software Assignment Value (Preliminary)
True LVDS
LVDS
Differential 1.2 V HSTL Class I
Differential 1.2-V HSTL Class I
Differential 1.2 V HSTL Class II
Differential 1.2-V HSTL Class II
Differential HSUL-12
Differential 1.2-V HSUL
Differential SSTL-12
Differential 1.2-V SSTL
Differential SSTL-125
Differential 1.25-V SSTL
Differential SSTL-135
Differential 1.35-V SSTL
Differential 1.5 V HSTL Class I
Differential 1.5-V HSTL Class I
Differential 1.5 V HSTL Class II
Differential 1.5-V HSTL Class II
Differential SSTL-15
Differential 1.5-V SSTL
Differential SSTL-15 Class I
Differential 1.5-V SSTL Class I
Differential SSTL-15 Class II
Differential 1.5-V SSTL Class II
Differential 1.8 V HSTL Class I
Differential 1.8-V HSTL Class I
Differential 1.8 V HSTL Class II
Differential 1.8-V HSTL Class II
Differential SSTL-18 Class I
Differential 1.8-V SSTL Class I
Differential SSTL-18 Class II
Differential 1.8-V SSTL Class II
Differential POD12
Differential 1.2-V POD
Table 5-31: SERDES Transmitter I/O Standards Support
I/O Standard
Quartus Prime Software Assignment Value
True LVDS
LVDS
Differential 1.2 V HSTL Class I
Differential 1.2-V HSTL Class I
Differential 1.2 V HSTL Class II
Differential 1.2-V HSTL Class II
Differential HSUL-12
Differential 1.2-V HSUL
Differential SSTL-12
Differential 1.2-V SSTL
Differential SSTL-125
Differential 1.25-V SSTL
Differential SSTL-135
Differential 1.35-V SSTL
Differential 1.5 V HSTL Class I
Differential 1.5-V HSTL Class I
Differential 1.5 V HSTL Class II
Differential 1.5-V HSTL Class II
Differential SSTL-15
Differential 1.5-V SSTL
Differential SSTL-15 Class I
Differential 1.5-V SSTL Class I
Differential SSTL-15 Class II
Differential 1.5-V SSTL Class II
Differential 1.8 V HSTL Class I
Differential 1.8-V HSTL Class I
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Differential Transmitter in Arria 10 Devices
I/O Standard
Quartus Prime Software Assignment Value
Differential 1.8 V HSTL Class II
Differential 1.8-V HSTL Class II
Differential SSTL-18 Class I
Differential 1.8-V SSTL Class I
Differential SSTL-18 Class II
Differential 1.8-V SSTL Class II
Differential POD12
Differential 1.2-V POD
mini-LVDS
mini-LVDS
RSDS
RSDS
Differential Transmitter in Arria 10 Devices
The Arria 10 transmitter contains dedicated circuitry to support high-speed differential signaling. The
differential transmitter buffers support the following features:
• LVDS signaling that can drive out LVDS, mini-LVDS, and RSDS signals
• Programmable VOD and programmable pre-emphasis
Table 5-32: Dedicated Circuitries and Features of the Differential Transmitter
Dedicated Circuitry / Feature
Description
Differential I/O buffer
Supports LVDS, mini-LVDS, and RSDS
SERDES
Up to 10 bit serializer
Phase-locked loops (PLLs)
Clocks the load and shift registers
Programmable VOD
Static
Programmable pre-emphasis
Boosts output current
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
Transmitter Blocks in Arria 10 Devices
The dedicated circuitry consists of a true differential buffer, a serializer, and I/O PLLs that you can share
between the transmitter and receiver. The serializer takes up to 10 bits wide parallel data from the FPGA
fabric, clocks it into the load registers, and serializes it using shift registers that are clocked by the I/O PLL
before sending the data to the differential buffer. The MSB of the parallel data is transmitted first.
Note: To drive the LVDS channels, you must use the PLLs in integer PLL mode.
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Serializer Bypass for DDR and SDR Operations
Figure 5-32: LVDS Transmitter
This figure shows a block diagram of the transmitter. In SDR and DDR modes, the data width is 1 and 2
bits, respectively.
2
FPGA
Fabric
10 bits
maximum
data width
Serializer
tx_in
10
IOE
IOE supports SDR, DDR, or non-registered datapath
+
–
DIN DOUT
tx_out
LVDS Transmitter
tx_coreclock
3 (load_enable, fast_clock, tx_coreclock)
LVDS Clock Domain
tx_inclock
I/O PLL
Serializer Bypass for DDR and SDR Operations
The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR
mode.
You can bypass the serializer to support DDR (x2) and SDR (x1) operations to achieve a serialization
factor of 2 and 1, respectively. The deserializer bypass is supported through the Altera GPIO IP core.
Figure 5-33: Serializer Bypass
This figure shows the serializer bypass path. In DDR mode, tx_inclock clocks the IOE register. In SDR
mode, data is passed directly through the IOE. In SDR and DDR modes, the data width to the IOE is 1
and 2 bits, respectively.
2
FPGA
Fabric
tx_in
Serializer
2
IOE
IOE supports SDR, DDR, or non-registered datapath
+
-
DIN DOUT
tx_out
LVDS Transmitter
tx_coreclock
3
(load_enable, fast_clock, tx_coreclock)
I/O PLL
Note: Disabled blocks and signals are grayed out
Differential Receiver in Arria 10 Devices
The receiver has a differential buffer and I/O PLLs that you can share among the transmitter and receiver,
a DPA block, a synchronizer, a data realignment block, and a deserializer. The differential buffer can
receive LVDS, mini-LVDS, and RSDS signal levels. You can statically set the I/O standard of the receiver
pins to LVDS, mini-LVDS, or RSDS in the Quartus Prime software Assignment Editor.
Note: To drive the LVDS channels, you must use the PLLs in integer PLL mode.
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Receiver Blocks in Arria 10 Devices
Table 5-33: Dedicated Circuitries and Features of the Differential Receiver
Dedicated Circuitry / Feature
Description
Differential I/O buffer
Supports LVDS, mini-LVDS, and RSDS
SERDES
Up to 10 bit deserializer
Phase-locked loops (PLLs)
Generates different phases of a clock for data synchronizer
Data realignment (Bit slip)
Inserts bit latencies into serial data
DPA
Chooses a phase closest to the phase of the serial data
Synchronizer (FIFO buffer)
Compensate for phase differences between the data and the
receiver’s input reference clock
Skew adjustment
Manual
On-chip termination (OCT)
100 Ω in LVDS I/O standards
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
Receiver Blocks in Arria 10 Devices
The Arria 10 differential receiver has the following hardware blocks:
•
•
•
•
Altera Corporation
DPA block
Synchronizer
Data realignment block (bit slip)
Deserializer
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DPA Block
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Figure 5-34: Receiver Block Diagram
This figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the
IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and
sends a maximum of 10 bits to the internal logic.
IOE supports SDR, DDR, or non-registered datapath
2
IOE
rx_out
Deserializer
Bit Slip
10
DOUT
FPGA
Fabric
DIN
DOUT
DIN
fast_clock
2
(load_enable,
fast_clock) Clock Mux
rx_divfwdclk
rx_coreclock
LVDS Receiver
Synchronizer
+ rx_in
–
DPA Circuitry
Retimed
DIN
Data
DPA Clock
DIN
DOUT
dpa_fast_clock
10
fast_clock
10 bits
maximum
data width
3
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
DPA Clock Domain
LVDS Clock Domain
I/O PLL
8 Serial LVDS
Clock Phases
rx_inclock
DPA Block
The DPA block takes in high-speed serial data from the differential input buffer and selects one of the
eight phases that the I/O PLLs generate to sample the data. The DPA chooses a phase closest to the phase
of the serial data. The maximum phase offset between the received data and the selected phase is 1/8 unit
interval (UI)(9), which is the maximum quantization error of the DPA. The eight phases of the clock are
equally divided, offering a 45° resolution.
(9)
The unit interval is the period of the clock running at the serial data rate (fast clock).
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Synchronizer
Figure 5-35: DPA Clock Phase to Serial Data Timing Relationship
This figure shows the possible phase relationships between the DPA clocks and the incoming serial data.
rx_in
D0
D1
D2
D3
D4
Dn
0°
45°
90°
135°
180°
225°
270°
315°
T vco
0.125T vco
T VCO = PLL serial clock period
The DPA block continuously monitors the phase of the incoming serial data and selects a new clock phase
if it is required. You can prevent the DPA from selecting a new clock phase by asserting the optional
rx_dpa_hold port, which is available for each channel.
DPA circuitry does not require a fixed training pattern to lock to the optimum phase out of the eight
phases. After reset or power up, the DPA circuitry requires transitions on the received data to lock to the
optimum phase. An optional output port, rx_dpa_locked, is available to indicate an initial DPA lock
condition to the optimum phase after power up or reset. Use data checkers such as a cyclic redundancy
check (CRC) or diagonal interleaved parity (DIP-4) to validate the data.
An independent reset port, rx_dpa_reset, is available to reset the DPA circuitry. You must retrain the
DPA circuitry after reset.
Note: The DPA block is bypassed in non-DPA mode.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
Synchronizer
The synchronizer is a 1 bit wide and 6 bit deep FIFO buffer that compensates for the phase difference
between dpa_fast_clock—the optimal clock that the DPA block selects—and the fast_clock that the
I/O PLLs produce. The synchronizer can only compensate for phase differences, not frequency
differences, between the data and the receiver’s input reference clock.
An optional port, rx_fifo_reset, is available to the internal logic to reset the synchronizer. The
synchronizer is automatically reset when the DPA first locks to the incoming data. Altera recommends
using rx_fifo_reset to reset the synchronizer when the data checker indicates that the received data is
corrupted.
Note: The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.
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Data Realignment Block (Bit Slip)
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Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the
received serial data streams. If you enable the DPA, the received data is captured with different clock
phases on each channel. This difference may cause misalignment of the received data from channel to
channel. To compensate for this channel-to-channel skew and establish the correct received word
boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the
data by inserting bit latencies into the serial stream.
An optional rx_bitslip_ctrl port controls the bit insertion of each receiver independently controlled
from the internal logic. The data slips one bit on the rising edge of rx_bitslip_ctrl. The requirements
for the rx_bitslip_ctrl signal include the following items:
•
•
•
•
The minimum pulse width is one period of the parallel clock in the logic array.
The minimum low time between pulses is one period of the parallel clock.
The signal is an edge-triggered signal.
The valid data is available four parallel clock cycles after the rising edge of rx_bitslip_ctrl.
Figure 5-36: Data Realignment Timing
This figure shows receiver output (rx_out) after one bit slip pulse with the deserialization factor set to 4.
rx_inclock
rx_in
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
rx_coreclock
rx_bitslip_ctrl
rx_out
3210
321x
32x1
3x21
xx21
0321
The data realignment circuit has a bit slip rollover value set to the deserialization factor. An optional
status port, rx_bitslip_max, is available to the FPGA fabric from each channel to indicate the reaching of
the preset rollover point.
Figure 5-37: Receiver Data Realignment Rollover
This figure shows a preset value of four bit-times before rollover occurs. The rx_bitslip_max signal
pulses for one rx_coreclock cycle to indicate that rollover has occurred.
rx_inclock
rx_bitslip_ctrl
rx_coreclock
rx_bitslip_max
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Deserializer
Deserializer
You can statically set the deserialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 by using the Quartus
Prime software.
The IOE contains two data input registers that can operate in DDR or SDR mode. You can bypass the
deserializer to support DDR (x2) and SDR (x1) operations. The deserializer bypass is supported through
the Altera GPIO IP core.
Figure 5-38: Deserializer Bypass
This figure shows the deserializer bypass path.
Bit Slip
FPGA
Fabric
rx_divfwdclk
rx_coreclock
DOUT
DIN
DOUT
Synchronizer
DIN
fast_clock
2
(load_enable,
fast_clock) Clock Mux
LVDS Receiver
DOUT
DIN
+ rx_in
–
DPA Circuitry
Retimed
DIN
Data
DPA Clock
dpa_fast_clock
Deserializer
10
fast_clock
rx_out
IOE supports SDR, DDR, or non-registered datapath
2
IOE
2
3
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
I/O PLL
8 Serial LVDS
Clock Phases
Note: Disabled blocks and signals are grayed out
You cannot use the DPA and data realignment circuit when you bypass the deserializer.
Receiver Modes in Arria 10 Devices
The Arria 10 devices support the following receiver modes:
• Non-DPA mode
• DPA mode
• Soft-CDR mode
Note: If you use DPA mode, follow the recommended initialization and reset flow. The recommended
flow ensures that the DPA circuit can detect the optimum phase tap from the PLL to capture data
on the receiver.
Related Information
Recommended Initialization and Reset Flow
Provides the recommended procedure to initialize and reset the Altera LVDS SERDES IP core.
Non-DPA Mode
The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is registered at the rising
edge of the serial fast_clock clock that is produced by the I/O PLLs.
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DPA Mode
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You can select the rising edge option with the Quartus Prime parameter editor. The fast_clock clock
that is generated by the I/O PLLs clocks the data realignment and deserializer blocks.
Figure 5-39: Receiver Datapath in Non-DPA Mode
This figure shows the non-DPA datapath block diagram. In SDR and DDR modes, the data width from
the IOE is 1 and 2 bits, respectively.
IOE supports SDR, DDR, or non-registered datapath
2
IOE
rx_out
Deserializer
Bit Slip
10
DOUT
FPGA
Fabric
DIN
DOUT
DIN
fast_clock
2
(load_enable,
fast_clock) Clock Mux
rx_divfwdclk
rx_coreclock
LVDS Receiver
Synchronizer
DIN
DOUT
+ rx_in
–
DPA Circuitry
Retimed
DIN
Data
DPA Clock
dpa_fast_clock
10
fast_clock
10 bits
maximum
data width
3
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
LVDS Clock Domain
I/O PLL
8 Serial LVDS
Clock Phases
rx_inclock
Note: Disabled blocks and signals are grayed out
DPA Mode
The DPA block chooses the best possible clock (dpa_fast_clock) from the eight fast clocks that the I/O
PLL sent. This serial dpa_fast_clock clock is used for writing the serial data into the synchronizer. A
serial fast_clock clock is used for reading the serial data from the synchronizer. The same fast_clock
clock is used in data realignment and deserializer blocks.
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Soft-CDR Mode
Figure 5-40: Receiver Datapath in DPA Mode
This figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active. In
SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
10
Deserializer
Bit Slip
10
DOUT
FPGA
Fabric
DIN
DOUT
DIN
fast_clock
2
(load_enable,
fast_clock) Clock Mux
rx_divfwdclk
rx_coreclock
LVDS Receiver
Synchronizer
DIN
DOUT
+ rx_in
–
DPA Circuitry
Retimed
DIN
Data
DPA Clock
dpa_fast_clock
rx_out
IOE supports SDR, DDR, or non-registered datapath
2
IOE
fast_clock
10 bits
maximum
data width
3
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
DPA Clock Domain
LVDS Clock Domain
I/O PLL
8 Serial LVDS
Clock Phases
rx_inclock
Note: Disabled blocks and signals are grayed out
In DPA mode, you must place all receiver channels of an LVDS instance in one I/O bank. Because each
I/O bank has a maximum of 24 LVDS I/O buffer pairs, each LVDS instance can support a maximum of 24
DPA channels.
Related Information
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
• Receiver Blocks in Arria 10 Devices on page 5-58
Lists and describes the receiver hardware blocks.
Soft-CDR Mode
The Arria 10 LVDS channel offers the soft-CDR mode to support the GbE and SGMII protocols. A
receiver PLL uses the local clock source for reference.
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Soft-CDR Mode
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Figure 5-41: Receiver Datapath in Soft-CDR Mode
This figure shows the soft-CDR mode datapath. In SDR and DDR modes, the data width from the IOE is
1 and 2 bits, respectively.
IOE supports SDR, DDR, or non-registered datapath
2
IOE
rx_out
Deserializer
Bit Slip
10
DOUT
FPGA
Fabric
DIN
DOUT
DIN
fast_clock
2
(load_enable,
fast_clock) Clock Mux
rx_divfwdclk
rx_coreclock
LVDS Receiver
Synchronizer
+ rx_in
–
DPA Circuitry
Retimed
DIN
Data
DPA Clock
DIN
DOUT
dpa_fast_clock
10
fast_clock
10 bits
maximum
data width
3
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
DPA Clock Domain
LVDS Clock Domain
I/O PLL
8 Serial LVDS
Clock Phases
rx_inclock
Note: Disabled blocks and signals are grayed out
In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an optimal DPA clock
phase to sample the data. This clock is used for bit slip operation and deserialization. The DPA block also
forwards the selected DPA clock, divided by the deserialization factor called rx_divfwdclk, to the FPGA
fabric, along with the deserialized data. This clock signal is put on the periphery clock (PCLK) network.
If you use the soft-CDR mode, do not assert the rx_dpa_reset port after the DPA has trained. The DPA
continuously chooses new phase taps from the PLL to track parts per million (PPM) differences between
the reference clock and incoming data.
You can use every LVDS channel in soft-CDR mode and drive the FPGA fabric using the PCLK network
in the Arria 10 device family. In soft-CDR mode, the rx_dpa_locked signal is not valid because the DPA
continuously changes its phase to track PPM differences between the upstream transmitter and the local
receiver input reference clocks. However, you can use the rx_dpa_locked signal to determine the initial
DPA locking conditions that indicate the DPA has selected the optimal phase tap to capture the data. The
rx_dpa_locked signal is expected to deassert when operating in soft-CDR mode. The parallel clock,
rx_coreclock, generated by the I/O PLLs, is also forwarded to the FPGA fabric.
In soft-CDR mode, you must place all receiver channels of an LVDS instance in one I/O bank. Because
each I/O bank has a maximum of 12 PCLK resources, each LVDS instance can support a maximum of 12
soft-CDR channels.
Related Information
• Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode on page 5-85
• Periphery Clock Networks on page 4-9
Provides more information about PCLK networks.
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PLLs and Clocking for Arria 10 Devices
To generate the parallel clocks (rx_coreclock and tx_coreclock) and high-speed clocks (fast_clock),
the Arria 10 devices provide I/O PLLs in the high-speed differential I/O receiver and transmitter channels.
Related Information
• GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
• Clocking Differential Transmitters on page 5-66
• Clocking Differential Receivers on page 5-67
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
• Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only on page 5-68
• Guideline: Pin Placement for Differential Channels on page 5-68
Each I/O bank contains its own PLL. The I/O bank PLL can drive all receiver and transmitter channels in
the same bank, and transmitter channels in adjacent I/O banks. However, the I/O bank PLL cannot drive
receiver channels in another I/O bank or transmitter channels in non-adjacent I/O banks.
• LVDS Interface with External PLL Mode on page 5-71
Clocking Differential Transmitters
The I/O PLL generates the load enable (load_enable) signal and the fast_clock signal (the clock
running at serial data rate) that clocks the load and shift registers. You can statically set the serialization
factor to x3, x4, x5, x6, x7, x8, x9, or x10 using the Quartus Prime software. The load enable signal is
derived from the serialization factor setting.
You can configure any Arria 10 transmitter data channel to generate a source-synchronous transmitter
clock output. This flexibility allows the placement of the output clock near the data outputs to simplify
board layout and reduce clock-to-data skew.
Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate
factors. You can specify these settings statically in the Quartus Prime parameter editor:
• The transmitter can output a clock signal at the same rate as the data—with a maximum output clock
frequency that each speed grade of the device supports.
• You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor.
• You can set the phase of the clock in relation to the data at 0° or 180° (edge- or center-aligned). The
I/O PLLs provide additional support for other phase shifts in 45° increments.
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Clocking Differential Receivers
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Figure 5-42: Transmitter in Clock Output Mode
This figure shows the transmitter in clock output mode. In clock output mode, you can use an LVDS
channel as a clock output channel.
Transmitter Circuit
Series
Parallel
FPGA
Fabric
I/O
PLL
Txclkout+
Txclkout–
fast_clock
load_enable
Related Information
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
• PLLs and Clocking for Arria 10 Devices on page 5-66
Clocking Differential Receivers
The I/O PLL receives the external clock input and generates different phases of the same clock. The DPA
block automatically chooses one of the clocks from the I/O PLL and aligns the incoming data on each
channel.
The synchronizer circuit is a 1 bit wide by 6 bit deep FIFO buffer that compensates for any phase
difference between the DPA clock and the data realignment block. If necessary, the user-controlled data
realignment circuitry inserts a single bit of latency in the serial bit stream to align to the word boundary.
The deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the
internal logic.
The physical medium connecting the transmitter and receiver LVDS channels may introduce skew
between the serial data and the source-synchronous clock. The instantaneous skew between each LVDS
channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver. The
three different modes—non-DPA, DPA, and soft-CDR—provide different options to overcome skew
between the source synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the serial data.
Non-DPA mode allows you to statically select the optimal phase between the source synchronous clock
and the received serial data to compensate skew. In DPA mode, the DPA circuitry automatically chooses
the best phase to compensate for the skew between the source synchronous clock and the received serial
data. Soft-CDR mode provides opportunities for synchronous and asynchronous applications for chip-tochip and short reach board-to-board applications for SGMII protocols.
Note: Only the non-DPA mode requires manual skew adjustment.
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Guideline: Use PLLs in Integer PLL Mode for LVDS
Related Information
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-68
• PLLs and Clocking for Arria 10 Devices on page 5-66
Guideline: Use PLLs in Integer PLL Mode for LVDS
Each I/O bank has its own PLL (I/O PLL) to drive the LVDS channels. These I/O PLLs operate in integer
mode only.
Related Information
PLLs and Clocking for Arria 10 Devices on page 5-66
Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
The high-speed clock generated from the PLL is intended to clock the LVDS SERDES circuitry only. Do
not use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is
restricted by the PLL FOUT specification.
For more information about the FOUT specification, refer to the device datasheet.
Related Information
• PLL Specifications
• PLLs and Clocking for Arria 10 Devices on page 5-66
Guideline: Pin Placement for Differential Channels
Each I/O bank contains its own PLL. The I/O bank PLL can drive all receiver and transmitter channels in
the same bank, and transmitter channels in adjacent I/O banks. However, the I/O bank PLL cannot drive
receiver channels in another I/O bank or transmitter channels in non-adjacent I/O banks.
PLLs Driving Differential Transmitter Channels
For differential transmitters, the PLL can drive the differential transmitter channels in its own I/O bank
and adjacent I/O banks. However, the PLL cannot drive the channels in a non-adjacent I/O bank.
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Guideline: Pin Placement for Differential Channels
5-69
Figure 5-43: PLLs Driving Differential Transmitter Channels
Valid: PLL driving transmitter channels in
adjacent banks
Invalid: PLL driving transmitter channels
across banks
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
PLL
Bank A
PLL
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff Channel
Diff TX
Diff Channel
Diff TX
Diff Channel
PLL
Bank B
PLL
Diff TX
Diff Channel
Diff TX
Diff Channel
Diff TX
Diff Channel
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
PLL
Bank C
PLL
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Bank A
Bank B
Bank C
PLLs Driving DPA-Enabled Differential Receiver Channels
For differential receivers, the PLL can drive all channels in the same I/O bank but cannot drive across
banks.
Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the
data phase of its associated channel. If you enable a DPA channel in a bank, you can use both singleended I/Os and differential I/O standards in the bank.
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Guideline: Pin Placement for Differential Channels
DPA usage adds some constraints to the placement of high-speed differential receiver channels. The
Quartus Prime compiler automatically checks the design and issues error messages if there are placement
guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.
Figure 5-44: PLLs Driving DPA-Enabled Differential Receiver Channels
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
PLL
Bank A
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
PLL
Bank B
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
DPA-enabled Diff RX
Interleaved PLLs Driving DPA-Enabled Differential Transmitter and Receiver Channels
If you use differential transmitter channels and DPA-enabled receiver channels simultaneously in a bank,
you can interleave the receiver channels driven by the I/O PLL in the bank with transmitter channels
driven by an I/O PLL in an adjacent bank.
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LVDS Interface with External PLL Mode
5-71
Figure 5-45: Interleaved PLLs Driving DPA-Enabled Differential Transmitter and Receiver Channels
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
PLL
Bank A
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
Bank B
PLL
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
DPA-enabled Diff RX
Diff TX
Related Information
PLLs and Clocking for Arria 10 Devices on page 5-66
LVDS Interface with External PLL Mode
The Altera LVDS SERDES IP core parameter editor provides an option for implementing the LVDS
interface with the Use External PLL option. With this option enabled you can control the PLL settings,
such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other
settings. You must also instantiate an Altera IOPLL IP core to generate the various clock and load enable
signals.
If you enable the Use External PLL option with the Altera LVDS SERDES transmitter and receiver, the
following signals are required from the Altera IOPLL IP core:
•
•
•
•
•
Serial clock input to the SERDES of the Altera LVDS SERDES transmitter and receiver
Load enable to the SERDES of the Altera LVDS SERDES transmitter and receiver
Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
Asynchronous PLL reset port of the Altera LVDS SERDES receiver
PLL VCO signal for the DPA and soft-CDR modes of the Altera LVDS SERDES receiver
Related Information
• Altera LVDS SERDES IP Core User Guide
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Altera IOPLL Signal Interface with Altera LVDS SERDES IP Core
•
•
•
•
PLLs and Clocking for Arria 10 Devices on page 5-66
Altera IOPLL Signal Interface with Altera LVDS SERDES IP Core on page 5-72
Altera IOPLL Parameter Values for External PLL Mode on page 5-73
Connection between Altera IOPLL and Altera LVDS SERDES on page 5-76
Altera IOPLL Signal Interface with Altera LVDS SERDES IP Core
Table 5-34: Signal Interface Between Altera IOPLL and Altera LVDS SERDES IP cores
This table lists the signal interface between the output ports of the Altera IOPLL IP core and the input ports of the
Altera LVDS SERDES transmitter and receiver.
From the Altera IOPLL IP core
lvds_clk[0] (serial clock output
signal)
To the Altera LVDS SERDES
Transmitter
To the Altera LVDS SERDES Receiver
ext_fclk (serial clock
input to the transmitter)
ext_fclk (serial clock input to the
ext_loaden (load enable
ext_loaden (load enable for the
ext_coreclock (parallel
ext_coreclock (parallel core clock)
receiver)
• Configure this signal using
outclk0 in the PLL.
• Select Enable LVDS_CLK/
LOADEN 0 or Enable LVDS_
CLK/LOADEN 0 & 1 option for
the Access to PLL LVDS_CLK/
LOADEN output port setting. In
most cases, select Enable LVDS_
CLK/LOADEN 0.
The serial clock output can only drive
ext_fclk on the Altera LVDS
SERDES transmitter and receiver.
This clock cannot drive the core logic.
loaden[0] (load enable output)
• Configure this signal using
outclk1 in the PLL.
• Select Enable LVDS_CLK/
LOADEN 0 or Enable LVDS_
CLK/LOADEN 0 & 1 option for
the Access to PLL LVDS_CLK/
LOADEN output port setting. In
most cases, select Enable LVDS_
CLK/LOADEN 0.
outclk2 (parallel clock output)
locked
Altera Corporation
to the transmitter)
core clock)
—
deserializer)
pll_areset (asynchronous PLL reset
port)
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Altera IOPLL Parameter Values for External PLL Mode
From the Altera IOPLL IP core
To the Altera LVDS SERDES
Transmitter
—
phout[7:0]
• This signal is required only for
LVDS receiver in DPA or softCDR mode.
• Configure this signal by turning
on Specify VCO frequency in the
PLL and specifying the VCO
frequency value.
• Turn on Enable access to PLL
DPA output port.
5-73
To the Altera LVDS SERDES Receiver
ext_vcoph
This signal is required only for LVDS
receiver in DPA or soft-CDR mode.
Note: With soft SERDES, a different clocking requirement is needed.
Related Information
• Altera LVDS SERDES IP Core User Guide
Provides more information about the different clocking requirement for soft SERDES.
• LVDS Interface with External PLL Mode on page 5-71
Altera IOPLL Parameter Values for External PLL Mode
The following examples show the clocking requirements to generate output clocks for Altera LVDS
SERDES using the Altera IOPLL IP core. The examples set the phase shift with the assumption that the
clock and data are edge aligned at the pins of the device.
Note: For other clock and data phase relationships, Altera recommends that you first instantiate your
Altera LVDS SERDES interface without using the external PLL mode option. Compile the IP cores
in the Quartus Prime software and take note of the frequency, phase shift, and duty cycle settings
for each clock output. Enter these settings in the Altera IOPLL IP core parameter editor and then
connect the appropriate output to the Altera LVDS SERDES IP cores.
Table 5-35: Example: Generating Output Clocks Using an Altera IOPLL IP core (No DPA and Soft-CDR Mode)
This table lists the parameter values that you can set in the Altera IOPLL parameter editor to generate three
output clocks using an Altera IOPLL IP core if you are not using DPA and soft-CDR mode.
Parameter
Frequency
outclk0
outclk1
outclk2
(Connects as lvds_clk[0] to
the ext_fclk port of Altera
LVDS SERDES transmitter or
receiver)
(Connects as loaden[0] to
the ext_loaden port of
Altera LVDS SERDES
transmitter or receiver)
(Used as the core clock for
the parallel data registers for
both transmitter and
receiver, and connects to the
ext_coreclock port of
Altera LVDS SERDES)
data rate
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factor
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Altera IOPLL Parameter Values for External PLL Mode
Parameter
outclk0
outclk1
outclk2
(Connects as lvds_clk[0] to
the ext_fclk port of Altera
LVDS SERDES transmitter or
receiver)
(Connects as loaden[0] to
the ext_loaden port of
Altera LVDS SERDES
transmitter or receiver)
(Used as the core clock for
the parallel data registers for
both transmitter and
receiver, and connects to the
ext_coreclock port of
Altera LVDS SERDES)
Phase shift
180°
[(deserialization factor – 1)/ 180/serialization factor
deserialization factor] x 360°
(outclk0 phase shift
divided by the serializa‐
tion factor)
Duty cycle
50%
100/serialization factor
50%
The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are
edge aligned. Introducing a phase shift of 180° to sampling clock (c0) ensures that the input data is centeraligned with respect to the outclk0, as shown in the following figure.
Figure 5-46: Phase Relationship for External PLL Interface Signals
refclk
VCO clk
(internal PLL clk)
lvds_clk[0]
(180° phase shift)
loaden[0]
(324° phase shift)
outclk2
(18° phase shift)
RX serial data
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tx_outclk
TX serial data
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D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
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Altera IOPLL Parameter Values for External PLL Mode
5-75
Table 5-36: Example: Generating Output Clocks Using an Altera IOPLL IP core (With DPA and Soft-CDR
Mode)
This table lists the parameter values that you can set in the Altera IOPLL parameter editor to generate four output
clocks using an Altera IOPLL IP core if you are using DPA and soft-CDR mode. The locked output port of Altera
IOPLL must be inverted and connected to the pll_areset port of the Altera LVDS SERDES IP core if you are
using DPA and soft-CDR mode.
Parameter
outclk0
outclk1
(Connects as lvds_
clk[0] to the ext_
fclk port of Altera
loaden[0] to the
ext_loaden port of
LVDS SERDES
transmitter or
receiver)
(Connects as
Altera LVDS SERDES
transmitter or
receiver)
outclk2
VCO Frequency
(Used as the core clock
(Connects as
for the parallel data
phout[7:0] to the
registers for both
ext_vcoph[7:0] port
transmitter and
of Altera LVDS
receiver, and connects
SERDES)
to the ext_coreclock
port of Altera LVDS
SERDES)
Frequency
data rate
data rate/serialization data rate/serialization data rate
factor
factor
Phase shift
180°
[(deserialization
180/serialization
—
factor - 1)/deserializa‐ factor
tion factor] x 360°
(outclk0 phase shift
divided by the seriali‐
zation factor)
Duty cycle
50%
100/serialization
factor
50%
—
Related Information
• Receiver Skew Margin for Non-DPA Mode on page 5-80
RSKM equation used for the phase shift calculations.
• LVDS Interface with External PLL Mode on page 5-71
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Connection between Altera IOPLL and Altera LVDS SERDES
Connection between Altera IOPLL and Altera LVDS SERDES
Figure 5-47: LVDS Interface with the Altera IOPLL IP core (Without DPA and Soft-CDR Mode)
This figure shows the connections between the Altera IOPLL and Altera LVDS SERDES IP core if you are
not using DPA and soft-CDR mode.
FPGA Fabric
LVDS Transmitter
Transmitter
Core Logic
D
Q
(Altera LVDS SERDES)
tx_in
tx_coreclk
LVDS Receiver
rx_coreclk
Receiver
Core Logic
ext_fclk
ext_loaden
ext_coreclock
(Altera LVDS SERDES)
Q
lvds_clk[0]
loaden[0]
outclk2
Altera IOPLL
refclk
rst
locked
D
rx_out
ext_fclk
ext_loaden
ext_coreclock
pll_areset
Figure 5-48: LVDS Interface with the Altera IOPLL IP core (With DPA)
This figure shows the connections between the Altera IOPLL and Altera LVDS SERDES IP core if you are
using DPA. The locked output port must be inverted and connected to the pll_areset port.
FPGA Fabric
LVDS Transmitter
Transmitter
Core Logic
D
Q
tx_in
tx_coreclk
Altera Corporation
ext_fclk
ext_loaden
ext_coreclock
LVDS Receiver
rx_coreclk
Receiver
Core Logic
(Altera LVDS SERDES)
(Altera LVDS SERDES)
Q
D
lvds_clk[0]
loaden[0]
outclk2
phout[7..0]
locked
Altera IOPLL
refclk
rst
ext_fclk
ext_vcoph[7..0]
rx_out
ext_loaden
ext_coreclock
pll_areset
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Figure 5-49: LVDS Interface with the Altera IOPLL IP core (With Soft-CDR Mode)
This figure shows the connections between the Altera IOPLL and Altera LVDS SERDES IP core if you are
using soft-CDR mode. The locked output port must be inverted and connected to the pll_areset port.
FPGA Fabric
LVDS Transmitter
Transmitter
Core Logic
D
Q
tx_in
tx_coreclk
ext_fclk
ext_loaden
ext_coreclock
LVDS Receiver
rx_coreclk
Receiver
Core Logic
(Altera LVDS SERDES)
(Altera LVDS SERDES)
Q
D
lvds_clk[0]
loaden[0]
outclk2
phout[7..0]
locked
Altera IOPLL
refclk
rst
ext_fclk
ext_vcoph[7..0]
rx_out
ext_loaden
rx_divfwdclk
ext_coreclock
pll_areset
When generating the Altera IOPLL IP core, use the LVDS compensation mode. Instantiation of rst is
optional.
The ext_coreclock port is automatically enabled in an LVDS receiver in external PLL mode. The
Quartus Prime compiler output error messages if this port is not connected as shown in the preceding
figures.
Related Information
LVDS Interface with External PLL Mode on page 5-71
Timing and Optimization for Arria 10 Devices
Source-Synchronous Timing Budget
The topics in this section describe the timing budget, waveforms, and specifications for sourcesynchronous signaling in the Arria 10 device family.
The LVDS I/O standard enables high-speed transmission of data, resulting in better overall system
performance. To take advantage of fast system performance, you must analyze the timing for these highspeed signals. Timing analysis for the differential block is different from traditional synchronous timing
analysis techniques.
The basis of the source synchronous timing analysis is the skew between the data and the clock signals
instead of the clock-to-output setup times. High-speed differential data transmission requires the use of
timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and
clock jitter.
This section defines the source-synchronous differential data orientation timing parameters, the timing
budget definitions for the Arria 10 device family, and how to use these timing parameters to determine
the maximum performance of a design.
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Differential Data Orientation
Differential Data Orientation
There is a set relationship between an external clock and the incoming data. For operations at 1 Gbps and
a serialization factor of 10, the external clock is multiplied by 10. You can set phase-alignment in the PLL
to coincide with the sampling window of each data bit. The data is sampled on the falling edge of the
multiplied clock.
Figure 5-50: Bit Orientation in the Quartus Prime Software
This figure shows the data bit orientation of the x10 mode.
incloc k/outcloc k
10 LVDS Bits
MSB
9
data in
8
7
6
5
4
3
2
LSB
0
1
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at high frequencies.
Figure 5-51: Bit-Order and Word Boundary for One Differential Channel
This figure shows the data bit orientation for a channel operation and is based on the following
conditions:
• The serialization factor is equal to the clock multiplication factor.
• The phase alignment uses edge alignment.
• The operation is implemented in hard SERDES.
Transmitter Channel Operation (x8 Mode)
tx_coreclock
tx_out
X
X
X
Previous Cycle
X X X X
7 6
MSB
X
Current Cycle
5 4 3
2
1
0
LSB
X
Next Cycle
X X X
X
X
X
X
X
X
Receiver Channel Operation (x8 Mode)
rx_inclock
rx_in
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
rx_coreclock
rx_out [7..0]
XXXXXXXX
XXXXXXXX
XXXX7654
3210XXXX
Note: These waveforms are only functional waveforms and do not convey timing information
For other serialization factors, use the Quartus Prime software tools to find the bit position within the
word.
Differential Bit Naming Conventions
The following table lists the conventions for differential bit naming for 18 differential channels. The MSB
and LSB positions increase with the number of channels used in a system.
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Table 5-37: Differential Bit Naming
This table lists the conventions for differential bit naming for 18 differential channels. The MSB and LSB positions
increase with the number of channels used in a system.
Receiver Channel Data Number
Internal 8-Bit Parallel Data
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
17
135
128
18
143
136
Transmitter Channel-to-Channel Skew
The receiver skew margin calculation uses the transmitter channel-to-channel skew (TCCS)—an
important parameter based on the Arria 10 transmitter in a source-synchronous differential interface:
• TCCS is the difference between the fastest and slowest data output transitions, including the TCO
variation and clock skew.
• For LVDS transmitters, the TimeQuest Timing Analyzer provides the TCCS value in the TCCS report
(report_TCCS) in the Quartus Prime compilation report, which shows TCCS values for serial output
ports.
• You can also get the TCCS value from the device datasheet.
For the Arria 10 devices, perform PCB trace compensation to adjust the trace length of each LVDS
channel to improve channel-to-channel skew when interfacing with non-DPA receivers at data rate above
840 Mbps. The Quartus Prime software Fitter Report panel reports the amount of delay you must add to
each trace for the Arria 10 device. You can use the recommended trace delay numbers published under
the LVDS Transmitter/Receiver Package Skew Compensation panel and manually compensate the skew
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Receiver Skew Margin for Non-DPA Mode
on the PCB board trace to reduce channel-to-channel skew, thus meeting the timing budget between
LVDS channels.
Related Information
• High-Speed I/O Specifications
• Altera LVDS SERDES IP Core User Guide
Provides more information about the LVDS Transmitter/Receiver Package Skew Compensation report
panel.
Receiver Skew Margin for Non-DPA Mode
Different modes of LVDS receivers use different specifications, which can help in deciding the ability to
sample the received serial data correctly:
• In DPA mode, use DPA jitter tolerance instead of the receiver skew margin (RSKM).
• In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed
source-synchronous differential signals in the receiver data path.
Figure 5-52: RSKM Equation
This equation expresses the relationship between RSKM, TCCS, and SW.
Conventions used for the equation:
• RSKM—the timing margin between the receiver’s clock input and the data input sampling window,
and the jitter induced from core noise and I/O switching noise.
• Time unit interval (TUI)—time period of the serial data.
• SW—the period of time that the input data must be stable to ensure that data is successfully sampled
by the LVDS receiver. The SW is a device property and varies with device speed grade.
• TCCS—the timing difference between the fastest and the slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measure‐
ment.
You must calculate the RSKM value to determine whether the LVDS receiver can sample the data
properly or not, given the data rate and device. A positive RSKM value indicates that the LVDS receiver
can sample the data properly, whereas a negative RSKM indicates that it cannot sample the data properly.
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Figure 5-53: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
This figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
Receiver
Input Data
TCCS
RSKM
SW
tSW (min)
Bit n
Timing Budget
Internal
Clock
Falling Edge
RSKM
tSW (max)
Bit n
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
TCCS
RSKM
RSKM
TCCS
2
Receiver
Input Data
SW
For LVDS receivers, the Quartus Prime software provides an RSKM report showing the SW, TUI, and
RSKM values for non-DPA LVDS mode:
• You can generate the RSKM report by executing the report_RSKM command in the TimeQuest
Timing Analyzer. You can find the RSKM report in the Quartus Prime compilation report in the
TimeQuest Timing Analyzer section.
• To obtain the RSKM value, assign the input delay to the LVDS receiver through the constraints menu
of the TimeQuest Timing Analyzer. The input delay is determined according to the data arrival time at
the LVDS receiver port, with respect to the reference clock.
• If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name
to the clock that reference the source synchronous clock that feeds the LVDS receiver.
• If you do not set any input delay in the TimeQuest Timing Analyzer, the receiver channel-to-channel
skew defaults to zero.
• You can also directly set the input delay in a Synopsys Design Constraint file (.sdc) using the
set_input_delay command.
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Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
Example 5-1: RSKM Calculation Example
This example shows the RSKM calculation for Arria 10 devices at 1 Gbps data rate with a 200 ps
board channel-to-channel skew.
•
•
•
•
•
TCCS = 100 ps (pending characterization)
SW = 300 ps (pending characterizatoin
TUI = 1000 ps
Total RCCS = TCCS + Board channel-to-channel skew = 100 ps + 200 ps = 300 ps
RSKM = (TUI – SW – RCCS) / 2 = (1000 ps – 300 ps – 300 ps) / 2 = 200 ps
Because the RSKM is greater than 0 ps, the receiver non-DPA mode will work correctly.
Related Information
• Altera LVDS SERDES IP Core User Guide
Provides more information about the LVDS Transmitter/Receiver Package Skew Compensation report
panel.
• The Quartus Prime TimeQuest Timing Analyzer
Provides more information about .sdc commands and the TimeQuest Timing Analyzer.
Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver from the TimeQuest
Timing Analyzer constraints menu.
1. On the menu in the TimeQuest Timing Analyzer, select Constraints > Set Input Delay.
2. In the Set Input Delay window, select the desired clock using the pull-down menu. The clock name
must reference the source synchronous clock that feeds the LVDS receiver.
3. Click the Browse button (next to the Targets field).
4. In the Name Finder window, click List to view a list of all available ports. Select the LVDS receiver
serial input ports according to the input delay you set, and click OK.
5. In the Set Input Delay window, set the appropriate values in the Input delay options and Delay value
fields.
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Repeat from step 1 to assign the appropriate delay for all the LVDS receiver input ports. If you have
already assigned Input Delay and you need to add more delay to that input port, turn on the Add
Delay option.
Using the I/Os and High Speed I/Os in Arria 10 Devices
I/O and High-Speed I/O General Guidelines for Arria 10 Devices
There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
Guideline: VREF Sources and VREF Pins on page 5-83
Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing on page 5-83
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Guideline: VREF Sources and VREF Pins
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Guideline: VREF Sources and VREF Pins
For Arria 10 devices, consider the following VREF pins guidelines:
• Arria 10 devices support internal and external VREF sources. You can use the internal VREF with
calibration to support DDR4 using the POD12 I/O standard.
• There is an external VREF pin for every I/O bank, providing one external VREF source for all I/Os in
the same bank.
• Each I/O lane in the bank also has its own internal VREF generator. You can configure each I/O lane
independently to use its internal VREF or the I/O bank's external VREF source. All I/O pins in the
same I/O lane will use the same VREF source.
• You can place any combination of input, output, or bidirectional pins near VREF pins. There is no VREF
pin placement restriction.
• The VREF pins are dedicated for single-ended I/O standards. You cannot use the VREF pins as user
I/Os.
For more information about pin capacitance of the VREF pins, refer to the device datasheet.
Related Information
•
•
•
•
•
•
I/O Standards Voltage Levels in Arria 10 Devices on page 5-5
Pin Capacitance
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
I/O Bank Architecture in Arria 10 Devices on page 5-26
Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing
To ensure device reliability and proper operation when you use the device for 3.0 V I/O interfacing, do
not violate the absolute maximum ratings of the device. For more information about absolute maximum
rating and maximum allowed overshoot during transitions, refer to the device datasheet.
Tip: Perform IBIS or SPICE simulations to make sure the overshoot and undershoot voltages are within
the specifications.
Single-Ended Transmitter Application
If you use the Arria 10 device as a transmitter, use slow slew-rate and series termination to limit the
overshoot and undershoot at the I/O pins. Transmission line effects that cause large voltage deviations at
the receiver are associated with an impedance mismatch between the driver and the transmission lines. By
matching the impedance of the driver to the characteristic impedance of the transmission line, you can
significantly reduce overshoot voltage. You can use a series termination resistor placed physically close to
the driver to match the total driver impedance to the transmission line impedance.
Single-Ended Receiver Application
If you use the Arria 10 device as a receiver, use an external clamping diode to limit the overshoot and
undershoot voltage at the I/O pins.
The 3.0 V I/O standard is supported using the bank supply voltage (VCCIO) at 3.0 V and a VCCPT voltage
of 1.8 V. In this method, the clamping diode can sufficiently clamp overshoot voltage to within the DC
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Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
and AC input voltage specifications. The clamped voltage is expressed as the sum of the VCCIO and the
diode forward voltage.
Related Information
• I/O Standards Voltage Levels in Arria 10 Devices on page 5-5
• Absolute Maximum Ratings
• Maximum Allowed Overshoot and Undershoot Voltage
Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
Each I/O bank can simultaneously support multiple I/O standards. The following sections provide
guidelines for mixing non-voltage-referenced and voltage-referenced I/O standards in the devices.
Non-Voltage-Referenced I/O Standards
An I/O bank can simultaneously support any number of input signals with different I/O standard
assignments if the I/O standards support the VCCIO level of the I/O bank.
For output signals, a single I/O bank supports non-voltage-referenced output signals that drive at the
same voltage as VCCIO. Because an I/O bank can only have one VCCIO value, it can only drive out the value
for non-voltage-referenced signals.
For example, an I/O bank with a 2.5 V VCCIO setting can support 2.5 V standard inputs and outputs, and
3.0 V LVCMOS inputs only.
Voltage-Referenced I/O Standards
To accommodate voltage-referenced I/O standards:
• Each Arria 10 FPGA I/O bank contains a dedicated VREF pin.
• Each bank can have only a single VCCIO voltage level and a single voltage reference (VREF) level.
The voltage-referenced input buffer is powered by VCCPT. Therefore, an I/O bank featuring single-ended
or differential standards can support different voltage-referenced standards under the following
conditions:
• The VREF are the same levels.
• On-chip parallel termination (RT OCT) is disabled.
If you enable RT OCT, the voltage for the input standard and the VCCIO of the bank must match.
This feature allows you to place voltage-referenced input signals in an I/O bank with a VCCIO of 2.5 V or
below. For example, you can place HSTL-15 input pins in an I/O bank with 2.5 V VCCIO. However, the
voltage-referenced input with RT OCT enabled requires the VCCIO of the I/O bank to match the voltage of
the input standard. RT OCT cannot be supported for the HSTL-15 I/O standard when VCCIO is 2.5 V.
Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
An I/O bank can support voltage-referenced and non-voltage-referenced pins by applying each of the rule
sets individually.
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Guideline: Do Not Drive I/O Pins During Power Sequencing
5-85
Examples:
• An I/O bank can support SSTL-18 inputs and outputs, and 1.8 V inputs and outputs with a 1.8 V
VCCIO and a 0.9 V VREF.
• An I/O bank can support 1.5 V standards, 1.8 V inputs (but not outputs), and 1.5 V HSTL I/O
standards with a 1.5 V VCCIO and 0.75 V VREF.
Guideline: Do Not Drive I/O Pins During Power Sequencing
The Arria 10 I/O buffers are powered by VCC, VCCPT, and VCCIO.
Because the Arria 10 devices do not support hot socketing, do not drive the I/O pins externally during
power up and power down. This includes all I/O pins including FPGA and HPS I/Os. Adhere to this
guideline to:
• Avoid excess I/O pin current.
• Achieve minimum current draw and avoid I/O glitch during power up or power down.
• Avoid permanent damage on the 3 V I/O buffers in 2.5 V or 3 V operation.
Related Information
Power-Up and Power-Down Sequences on page 10-18
Guideline: Maximum DC Current Restrictions
There are no restrictions on the maximum DC current of any 10 consecutive I/O pins for Arria 10
devices.
Arria 10 devices conform to the VCCIO Electro-Migration (EM) rule and IR drop targets for all I/O
standard drive strength settings—ensuring reliability over the lifetime of the devices.
Guideline: Altera LVDS SERDES IP Core Instantiation
In DPA or soft-CDR mode, you can instantiate only one Altera LVDS SERDES IP core instance for each
I/O bank.
Related Information
• Modular I/O Banks for Arria 10 GX Devices on page 5-16
• Modular I/O Banks for Arria 10 GT Devices on page 5-19
• Modular I/O Banks for Arria 10 SX Devices on page 5-20
Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
You can use only specific LVDS pin pairs in soft-CDR mode. Refer to the pinout file of each device to
determine the LVDS pin pairs that support the soft-CDR mode.
Related Information
• Arria 10 Device Pin-Out Files
Provides the pin-out file for each Arria 10 device. For the SoC devices, the pin-out files also list the I/O
banks that are shared by the FPGA fabric and the HPS.
• Soft-CDR Mode on page 5-64
• Periphery Clock Networks on page 4-9
Provides more information about PCLK networks.
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Guideline: Minimizing High Jitter Impact on Arria 10 GPIO Performance
Guideline: Minimizing High Jitter Impact on Arria 10 GPIO Performance
In your Arria 10 design flow, follow these guidelines to minimize undesired jitter impact on the GPIO
performance.
• Perform power delivery network analysis using Altera PDN tool 2.0. This analysis helps you to design a
robust and efficient power delivery networks with the necessary decoupling capacitors. Use the Arria
10 Early Power Estimator (EPE) to determine the current requirements for VCC and other power
supplies. Perform the PDN analysis based on the current requirements of all the power supply rails
especially the VCC power rail.
• Use voltage regulator with remote sensor pins to compensate for the DC IR drop associated with the
PCB and device package from the VCC power supply while maintaining the core performance. For
more details about the connection guideline for the differential remote sensor pins for VCC power,
refer to the pin connection guidelines.
• The input clock jitter must comply with the Arria 10 PLL input clock cycle-to-cycle jitter specification
to produce low PLL output clock jitter. You must supply a clean clock source with jitter of less than
120 ps. For details about the recommended operating conditions, refer to the PLL specifications in the
device datasheet.
• Use dedicated PLL clock output pin to transmit clock signals for better jitter performance. The I/O
PLL in each I/O bank supports two dedicated clock output pins. You can use the PLL dedicated clock
output pin as a reference clock source for the FPGA. For optimum jitter performance, supply an
external clean clock source. For details about the jitter specifications for the PLL dedicated clock
output pin, refer to the device datasheet.
• If the GPIO is operating at a frequency higher than 250 MHz, use terminated I/O standards. SSTL,
HSTL, POD and HSUL I/O standads are terminated I/O standards. Altera recommends that you use
the HSUL I/O standard for shorter trace or interconnect with a reference length of less than two
inches.
• Implement the GPIO or source synchronous I/O interface using the Altera PHYLite for Parallel
Interfaces IP core. Altera recommends that you use the Altera PHYLite for Parallel Interfaces IP core if
you cannot close the timing for the GPIO or source-synchronous I/O interface for data rates of more
than 200 Mbps. For guidelines to migrate your design from the Altera GPIO IP core to the Altera
PHYLite for Parallel Interfaces IP core, refer to the related information.
• Use the small periphery clock (SPCLK) network. The SPCLK network is designed for high speed I/O
interfaces and provides the smallest insertion delay. The following list ranks the clock insertion delays
for the clock networks, from the largest to the smallest:
•
•
•
•
Global clock network (GCLK)
Regional clock network (RCLK)
Large periphery clock network (LPCLK)
SPCLK
Related Information
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
• Arria 10 Device Datasheet
• Altera GPIO to Altera PHYLite Design Migration Guidelines
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Document Revision History
5-87
Document Revision History
Date
December
2015
Version
2015.12.14
Changes
• Updated the table listing the I/O standards voltage support to remove
3.0 V VCCIO input from the 2.5 V I/O standard.
• Updated the topic about MultiVolt I/O interface to update VCCP to
VCC.
• Corrected the I/O standards supported for the open-drain output,
bus-hold, and weak pull-up resistor features in the table summarizing
the programmable IOE features.
• Updated the topic about the data realignment block (bit slip) to
specify that valid data is available four parallel clock cycles after the
rising edge of rx_bitslip_ctrl. Previously, valid data is available
after two parallel clock cycles.
• Updated the topic about external I/O termination for devices to add
footnotes about using OCT for SSTL-12 and Differential SSTL-12 I/O
standards, and note about recommendation to perform IBIS or
SPICE simulations.
• Updated the topic about uncalibrated RS OCT:
•
•
•
•
•
•
• Updated the RS values of SSTL-15 to remove 25 Ω and 50 Ω.
• Added the Differential SSTL-15, Differential SSTL-135, Differen‐
tial SSTL-125, Differential SSTL-12, Differential POD12, and
Differential HSUL-12 I/O standards.
Updated the topic about calibrated RS OCT to add the Differential
POD12 I/O standard.
Updated the topic about calibrated RT OCT to remove 20 Ω RT OCT
support and to add the Differential POD12 I/O standard.
Removed the Differential SSTL-2 Class I and Class II I/O standards
from the tables listing the SERDES receiver and transmitter I/O
standards support.
Updated the topic about the voltage-referenced I/O standard under
the guideline for mixing voltage-referenced and non-voltagereferenced I/O standards.
Added design guideline for minimizing high jitter impact on the
GPIO performance.
Updated the following signal names:
• dpa_diffioclk to dpa_fast_clock
• dpa_load_en to dpa_load_enable
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Document Revision History
Date
November
2015
Version
2015.11.02
Changes
• Updated the topic about serializer bypass for SDR and DDR
operations to specify that the serializer bypass is supported through
the Altera GPIO IP core.
• Added a footnote with the definition of unit interval (UI) in the topic
about the DPA block.
• Updated the topic about the data realignment block (bit slip). The bit
slip rollover value is now automatically set to the deserialization
factor.
• Updated the topic about the deserializer to specify that the deserial‐
izer bypass is supported through the Altera GPIO IP core.
• Updated the topic about PLLs and clocking to correct the parallel
clock names from rx_outclock and tx_outclock to rx_coreclock
and tx_coreclock.
• Updated the topic about using the PLLs in integer mode for LVDS to
clarify that the I/O PLLs operate in integer mode only.
• Updated the following port/signal names:
• rx_dpll_hold to rx_dpa_hold
• rx_reset to rx_dpa_reset
• rx_channel_data_align to rx_bitslip_ctrl
• rx_cda_max to rx_bitslip_max
• rx_outclock to rx_coreclock
• lvds_diffioclk and diffioclk to fast_clock
• lvds_load_en and load_en to load_enable
• Updated the topic about pin placement for differential channels:
• Improved clarity about PLLs driving interleaved differential
transmitter and DPA-enabled receiver channels
• Removed the note about bank placement DDIO and SDR I/Os
• Updated the topic about the signal interface between Altera IOPLL
and the Altera LVDS SERDES IP core in external PLL mode.
• Updated the topic about Altera IOPLL IP core parameter values for
external PLL mode:
• Phase shift of outclk0 from -180° to 180°
• Phase shift of outclk2 from -180/serialization factor to 180/seriali‐
zation factor (-18° to 18°)
• Updated the definition of RSKM for the RSKM equation in the topic
about the receiver skew margin in non-DPA mode.
• Changed instances of Quartus II to Quartus Prime.
June 2015
Altera Corporation
2015.06.15
Corrected label for Arria 10 GT product lines in the vertical migration
figure.
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Document Revision History
Date
May 2015
Version
2015.05.04
5-89
Changes
• Updated the statements in the topic about the I/O and differential I/O
buffers to improve clarity.
• Updated the I/O resources information for the U19 package of the
Arria 10 GX 160, GX 220, SX 160, and SX 220 devices:
•
•
•
•
Updated LVDS I/O count from 144 to 148
Updated total GPIO from 192 to 196
Updated number of LVDS channels from 72 to 74
Added bank 3A and removed bank 3C in the figures and related
modular I/O banks tables
• Updated the figure showing the IOE structure to clarify that the delay
chains are separate.
• Updated the modular I/Os for banks 3A (from null to 48) and 3B
(from 48 to null) for the F27 package of the Arria 10 GX 270, GX 320,
SX 270, and SX 320 devices.
January 2015
2014.01.23
• Added topic about programmable open-drain output.
• Restructured the topic about pin placement for differential channels
to enhance clarity.
• Corrected contents that specified DPA-enabled transmitter channels.
There is no DPA for transmitter channels.
• Added guideline about instantiating only one Altera LVDS SERDES
IP core instance for each I/O bank.
• Added guideline about using only specific LVDS pin pairs in softCDR mode.
• Updated the section that describes usage of the LVDS interface with
external PLL:
• Updated information about the required signals in Altera IOPLL
and Altera LVDS SERDES IP cores.
• Updated the examples of parameter values to generate output
clocks using Altera IOPLL IP core.
• Updated the LVDS clock phase relationship diagram for external
PLL interface signals.
• Updated the diagrams that show the connections between Altera
IOPLL and Altera LVDS SERDES IP cores.
• Added footnote to clarify that you can use pre-emphasis for LVDS
and POD12 I/O standards. The POD12 I/O standard supports DDR4.
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Document Revision History
Date
Version
August 2014
2014.08.18
Changes
• Updated description of the 3 V I/O bank regarding support for
programmable IOE features.
• Added statement to clarify that apart from FPGA I/O buffers, the
Arria 10 SoC devices also contains HPS I/O buffers with different I/O
standards support.
• Separated I/O bank 2A in each I/O banks location figures to signify
that it is not consecutive with other I/O banks.
• Updated LVDS I/O and SERDES circuitry descriptions to clarify that
each LVDS channel have built-in transmit SERDES and receive
SERDES.
• Removed reference to on-chip clamping diode. Arria 10 devices do
not have on-chip clamping diode. Use an external clamping diode
where applicable.
• Added a related information link to the Arria 10 Transceiver PHY
User Guide that describes the transceiver I/O banks locations.
• Updated the I/O vertical migration figure to show vertical migration
between Arria 10 GX and Arria 10 SX devices.
• Updated all references to "megafunction" to "IP core".
• Updated all references to "MegaWizard Plug-in Manager" to
"parameter editor".
• Updated all references to Altera PLL IP core to Altera IOPLL IP core.
• Updated the signal names for using the LVDS interface with the
External PLL mode:
•
•
•
•
December
2013
Altera Corporation
2013.12.02
tx_inclock and rx_inclock to ext_fclk
tx_enable rx_enable to ext_loaden
rx_dpaclock to ext_vcoph[7..0]
rx_synclock to ext_coreclock
Initial release.
I/O and High Speed I/O in Arria 10 Devices
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External Memory Interfaces in Arria 10 Devices
2015.12.16
A10-EMI
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The efficient architecture of the Arria 10 external memory interface allows you to fit wide external
memory interfaces within the small modular I/O banks structure. This capability enables you to support a
high level of system bandwidth.
Compared to previous generation Arria devices, the new architecture and solution provide the following
advantages:
• Pre-closed timing in the controller and from the controller to the PHY.
• Easier pin placement.
For maximum performance and flexibility, the architecture offers hard memory controller and hard PHY
for key interfaces, and soft multi-port front end (MPFE) implementation.
Related Information
• Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
• Arria 10 FPGA and SoC External Memory Resources
Provides more resources about the Arria 10 external memory solution.
• External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported
external memory interfaces in Altera devices.
Key Features of the Arria 10 External Memory Interface Solution
• The solution offers completely hardened external memory interfaces for several protocols.
• The devices feature columns of I/Os that are mixed within the core logic fabric instead of I/O banks on
the device periphery.
• A single hard Nios® II block calibrates all the memory interfaces in an I/O column.
• The I/O columns are composed of groups of I/O modules called I/O banks.
• Each I/O bank contains a dedicated integer PLL (IO_PLL), hard memory controller, and delay-locked
loop.
• The PHY clock tree is shorter compared to previous generation Arria devices and only spans one I/O
bank.
• Interfaces spanning multiple I/O banks require multiple PLLs using a balanced reference clock
network.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
6-2
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Memory Standards Supported by Arria 10 Devices
Related Information
External Memory Interface Architecture of Arria 10 Devices on page 6-17
Provides more information about the I/O columns and I/O banks architecture.
Memory Standards Supported by Arria 10 Devices
The I/Os are designed to provide high performance support for existing and emerging external memory
standards.
Table 6-1: Memory Standards Supported by the Hard Memory Controller
This table lists the overall capability of the hard memory controller. For specific details, refer to the External
Memory Interface Spec Estimator and Arria 10 Device Datasheet.
Memory Standard
DDR4 SDRAM
Rate Support
Ping Pong PHY
Support
Maximum Frequency
Yes
1,067
—
1,333
Yes
533
—
667
Yes
1,067
—
1,067
Yes
533
—
667
Yes
933
—
933
Half rate
—
533
Quarter rate
—
800
Quarter rate
Half rate
DDR3 SDRAM
Quarter rate
Half rate
DDR3L SDRAM
Quarter rate
LPDDR3 SDRAM
(MHz)
Table 6-2: Memory Standards Supported by the Soft Memory Controller
Memory Standard
Rate Support
Maximum Frequency
(MHz)
(10)
RLDRAM 3 (10)
Quarter rate
1,200
QDR IV SRAM(10)
Quarter rate
1,067
Arria 10 devices support this external memory interface using hard PHY with soft memory controller.
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External Memory Interface Widths in Arria 10 Devices
Memory Standard
Rate Support
6-3
Maximum Frequency
(MHz)
QDR II/II+/II+ Xtreme SRAM
Full rate
333
Half rate
633
Table 6-3: Memory Standards Supported by the HPS Hard Memory Controller
The hard processor system (HPS) is available in Arria 10 SoC devices only.
Memory Standard
Rate Support
Maximum Frequency
(MHz)
DDR4 SDRAM
Half rate
1,333
DDR3 SDRAM
Half rate
1,067
DDR3L SDRAM
Half rate
933
LPDDR3
Half rate
800
Related Information
• External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported
external memory interfaces in Altera devices.
• Ping Pong PHY IP on page 6-16
Provides a brief description of the Ping Pong PHY.
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
External Memory Interface Widths in Arria 10 Devices
The Arria 10 devices can support the following external memory interface widths:
• Up to x144 interfaces for DDR4 and DDR3
• Up to x72 for RLDRAM 3 and QDR II+ Xtreme
External Memory Interfaces in Arria 10 Devices
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External Memory Interface I/O Pins in Arria 10 Devices
Table 6-4: Required I/O Banks for Interface Widths
This table lists the number of I/O banks required to support different external memory interface widths. You must
implement each single memory interface using the I/O banks in the same I/O column.
This table is a guideline and represents the worst-case scenario for these interface widths. Certain interfaces can be
implemented using fewer I/Os and will not take up the full I/O bank.
Except for DDR4 interfaces, if the total number of address/command pins exceeds 36, you require one more I/O
bank than the number listed in this table. For DDR4 interfaces, the additional I/O bank is required if the number
of address/command pins exceeds 37.
Interface Width
Required Number of I/O Banks
x8
1
x16, x24, x32, x40
2
x48, x56, x64, x72
3
x80, x88, x96, x104
4
x112, x120, x128, x136
5
x144
6
External Memory Interface I/O Pins in Arria 10 Devices
The memory interface circuitry is available in every I/O bank. The Arria 10 devices feature differential
input buffers for differential read-data strobe and clock operations.
The controller and sequencer in an I/O bank can drive address command (A/C) pins only to fixed I/O
lanes location in the same I/O bank. The minimum requirement for the A/C pins are three lanes.
However, the controller and sequencer of an I/O bank can drive data groups to I/O lanes in adjacent I/O
banks (above and below).
Pins that are not used for memory interfacing functions are available as general purpose I/O (GPIO) pins.
Figure 6-1: I/O Banks Interface Sharing
Sequencer
NIOS II
processor
Data pins
Address command pins (fixed)
Unused (available as GPIO)
Altera Corporation
I/O Bank
Controller
Sequencer
I/O Bank
Controller
Sequencer
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
Memory 2
I/O Bank
Controller
Memory 1
This figure shows an example of two x16 interfaces shared by three I/O banks.
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Memory Interfaces Support in Arria 10 Device Packages
6-5
Related Information
External Memory Interface Architecture of Arria 10 Devices on page 6-17
Provides more information about the I/O columns and I/O banks architecture.
Memory Interfaces Support in Arria 10 Device Packages
Note: The number of I/O pins in an I/O bank, and the availability of I/O banks, varies across device
packages. Only I/O banks with 48 I/O pins are usable for external memory interfaces. Because the
external memory interface must be placed in consecutive I/O banks in a column, I/O bank 2A is
not usable for external memory interfaces. For details about the I/O banks available for each device
package and the consecutive location of the I/O banks, refer to the related information.
Arria 10 Package Support for DDR3 x40 with ECC on page 6-6
Arria 10 Package Support for DDR3 x40 with ECC for HPS on page 6-7
Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank on page 6-8
Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank for HPS on page 6-10
Arria 10 Package Support for DDR4 x40 with ECC on page 6-11
Arria 10 Package Support for DDR4 x40 with ECC for HPS on page 6-12
Arria 10 Package Support for DDR4 x72 with ECC Single-Rank on page 6-13
Arria 10 Package Support for DDR4 x72 with ECC Dual-Rank on page 6-14
Arria 10 Package Support for DDR4 x72 with ECC Single-Rank for HPS on page 6-15
Related Information
•
•
•
•
GPIO Banks, SERDES, and DPA Locations in Arria 10 Devices on page 5-7
Modular I/O Banks for Arria 10 GX Devices on page 5-16
Modular I/O Banks for Arria 10 GT Devices on page 5-19
Modular I/O Banks for Arria 10 SX Devices on page 5-20
External Memory Interfaces in Arria 10 Devices
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Arria 10 Package Support for DDR3 x40 with ECC
Arria 10 Package Support for DDR3 x40 with ECC
To support one DDR3 x40 interface with ECC (32 bits data + 8 bits ECC), you require two I/O banks.
Table 6-5: Number of DDR3 x40 Interfaces (with ECC) Supported Per Device Package
This table lists the number of external memory interfaces supported for the core for each device package. The
numbers shown are using HPS shared I/O banks to implement core EMIF configurations. The number reduces
when HPS shared I/O banks are used to implement HPS EMIF configurations.
Note: For some device packages, you can also use the 3 V I/O banks for external memory interfaces. However, the
maximum memory interface clock frequency is capped at 533 MHz. To use higher memory clock frequen‐
cies, exclude the 3 V I/O bank from external memory interfaces.
Package
Product
Line
U19
F27
F29
F34
F35
F36
NF40
KF40
RF40
NF45
SF45
UF45
GX 160
1
1
2
—
—
—
—
—
—
—
—
—
GX 220
1
1
2
—
—
—
—
—
—
—
—
—
GX 270
—
1
2
3
3
—
—
—
—
—
—
—
GX 320
—
1
2
3
3
—
—
—
—
—
—
—
GX 480
—
—
2
4
3
—
—
—
—
—
—
—
GX 570
—
—
—
4
3
4(11)
5
6(11)
—
—
—
—
GX 660
—
—
—
4
3
4
(11)
5
6
—
—
—
—
GX 900
—
—
—
4
—
4
5
—
1
7
6
4
GX 1150
—
—
—
4
—
4
5
—
1
7
6
4
GT 900
—
—
—
—
—
—
5
—
—
—
6
4
GT 1150
—
—
—
—
—
—
5
—
—
—
6
4
SX 160
1
1
2
—
—
—
—
—
—
—
—
—
SX 220
1
1
2
—
—
—
—
—
—
—
—
—
SX 270
—
1
2
3
3
—
—
—
—
—
—
—
SX 320
—
1
2
3
3
—
—
—
—
—
—
—
SX 480
—
—
2
4
3
—
—
—
—
—
—
—
SX 570
—
—
—
4
3
—
5
6(11)
—
—
—
—
SX 660
—
—
—
4
3
—
5
6
—
—
—
—
(11)
(11)
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
(11)
This number includes using the 3 V I/O bank for external memory interfaces. Otherwise, the number of
external memory interfaces possible is reduced by one.
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Arria 10 Package Support for DDR3 x40 with ECC for HPS
6-7
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
Arria 10 Package Support for DDR3 x40 with ECC for HPS
To support one DDR3 x40 interface with ECC (32 bits data + 8 bits ECC) for HPS, you require two I/O
banks below the top 3 V I/O bank in the DDR column.
Table 6-6: Number of DDR3 x40 Interfaces (with ECC) for HPS Supported Per Device Package
This table lists the number of external memory interfaces supported for HPS only.
Package
Product
Line
U19
F27
F29
F34
F35
F36
NF40
KF40
RF40
NF45
SF45
UF45
SX 160
1
1
1
—
—
—
—
—
—
—
—
—
SX 220
1
1
1
—
—
—
—
—
—
—
—
—
SX 270
—
1
1
1
1
—
—
—
—
—
—
—
SX 320
—
1
1
1
1
—
—
—
—
—
—
—
SX 480
—
—
1
1
1
—
—
—
—
—
—
—
SX 570
—
—
—
1
1
—
1
1
—
—
—
—
SX 660
—
—
—
1
1
—
1
1
—
—
—
—
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
External Memory Interfaces in Arria 10 Devices
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Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank
Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank
To support one DDR3 x72 interface with ECC (64 bits data + 8 bits ECC) single and dual-rank, you
require three I/O banks.
Table 6-7: Number of DDR3 x72 Interfaces (with ECC) Single and Dual-rank Supported Per Device Package
This table lists the number of external memory interfaces supported for the core for each device package. The
numbers shown are using HPS shared I/O banks to implement core EMIF configurations. The number reduces
when HPS shared I/O banks are used to implement HPS EMIF configurations.
Note: For some device packages, you can also use the 3 V I/O banks for external memory interfaces. However, the
maximum memory interface clock frequency is capped at 533 MHz. To use higher memory clock frequen‐
cies, exclude the 3 V I/O bank from external memory interfaces.
Package
Product
Line
U19
F27
F29
F34
F35
F36
NF40
KF40
RF40
NF45
SF45
UF45
GX 160
1(12)
1(12)
1(12)
—
—
—
—
—
—
—
—
—
GX 220
(12)
1
1
1
—
—
—
—
—
—
—
—
—
GX 270
—
1(12)
2(12)
2(12)
2(12)
—
—
—
—
—
—
—
GX 320
—
1
(12)
2
2
(12)
2
—
—
—
—
—
—
—
GX 480
—
—
2(12)
3(12)
2(12)
—
—
—
—
—
—
—
GX 570
—
—
—
3(12)
2(12)
2
3(12)
3
—
—
—
—
GX 660
—
—
—
3
(12)
2
2
3
3
—
—
—
—
GX 900
—
—
—
3
—
2
3
—
0
4
3
2
GX 1150
—
—
—
3
—
2
3
—
0
4
3
2
GT 900
—
—
—
—
—
—
3
—
—
—
3
2
GT 1150
—
—
—
(12)
(12)
(12)
(12)
(12)
(12)
—
—
—
3
—
—
—
3
2
(12)
1
—
—
—
—
—
—
—
—
—
SX 160
1
1
SX 220
1(12)
1(12)
1(12)
—
—
—
—
—
—
—
—
—
SX 270
—
1(12)
2(12)
2(12)
2(12)
—
—
—
—
—
—
—
SX 320
—
(12)
1
2
2
2
(12)
—
—
—
—
—
—
—
SX 480
—
—
2(12)
3(12)
2(12)
—
—
—
—
—
—
—
SX 570
—
—
—
3(12)
2(12)
—
3(12)
3
—
—
—
—
SX 660
—
—
—
3
2
—
3
3
—
—
—
—
(12)
(12)
(12)
(12)
(12)
(12)
(12)
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
(12)
This number includes using the 3 V I/O bank for external memory interfaces. Otherwise, the number of
external memory interfaces possible is reduced by one.
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Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank
6-9
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
External Memory Interfaces in Arria 10 Devices
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Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank for...
Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank for HPS
To support one DDR3 x72 interface with ECC (64 bits data + 8 bits ECC) single and dual-rank for HPS,
you require three I/O banks below the top 3 V I/O bank in the DDR column.
Table 6-8: Number of DDR3 x72 Interfaces (with ECC) Single and Dual-Rank for HPS Supported Per Device
Package
This table lists the number of external memory interfaces supported for HPS only.
Product Line
Package
U19
F27
F29
F34
F35
NF40
KF40
SX 160
0
0
0
—
—
—
—
SX 220
0
0
0
—
—
—
—
SX 270
—
0
0
0
0
—
—
SX 320
—
0
0
0
0
—
—
SX 480
—
—
0
0
0
—
—
SX 570
—
—
—
0
0
0
1
SX 660
—
—
—
0
0
0
1
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
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Arria 10 Package Support for DDR4 x40 with ECC
6-11
Arria 10 Package Support for DDR4 x40 with ECC
To support one DDR4 x40 interface with ECC (32 bits data + 8 bits ECC), you require two I/O banks.
Table 6-9: Number of DDR4 x40 Interfaces (with ECC) Supported Per Device Package
This table lists the number of external memory interfaces supported for the core for each device package. The
numbers shown are using HPS shared I/O banks to implement core EMIF configurations. The number reduces
when HPS shared I/O banks are used to implement HPS EMIF configurations.
Note: For some device packages, you can also use the 3 V I/O banks for external memory interfaces. However, the
maximum memory interface clock frequency is capped at 533 MHz. To use higher memory clock frequen‐
cies, exclude the 3 V I/O bank from external memory interfaces.
Package
Product
Line
U19
F27
F29
F34
F35
F36
NF40
KF40
RF40
NF45
SF45
UF45
GX 160
1
1
2
—
—
—
—
—
—
—
—
—
GX 220
1
1
2
—
—
—
—
—
—
—
—
—
GX 270
—
1
2
3
3
—
—
—
—
—
—
—
GX 320
—
1
2
3
3
—
—
—
—
—
—
—
GX 480
—
—
2
4
3
—
—
—
—
—
—
—
GX 570
—
—
—
4
3
4(13)
5
6(13)
—
—
—
—
GX 660
—
—
—
4
3
4
(13)
5
6
—
—
—
—
GX 900
—
—
—
4
—
4
5
—
1
7
6
4
GX 1150
—
—
—
4
—
4
5
—
1
7
6
4
GT 900
—
—
—
—
—
—
5
—
—
—
6
4
GT 1150
—
—
—
—
—
—
5
—
—
7
6
4
SX 160
1
1
2
—
—
—
—
—
—
—
—
—
SX 220
1
1
2
—
—
—
—
—
—
—
—
—
SX 270
—
1
2
3
3
—
—
—
—
—
—
—
SX 320
—
1
2
3
3
—
—
—
—
—
—
—
SX 480
—
—
2
4(14)
3
—
—
—
—
—
—
—
SX 570
—
—
—
4
3
—
5
6(13)
—
—
—
—
SX 660
—
—
—
4
3
—
5
6
—
—
—
—
(13)
(13)
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
(13)
(14)
This number includes using the 3 V I/O bank for external memory interfaces. Otherwise, the number of
external memory interfaces possible is reduced by one.
This number includes using I/O banks 2K and 2J. If you use I/O bank 2K for DDR4 x32 interface in the
FPGA, the HPS will not have access to a DDR4 x32 interface.
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• Examples of External Memory Interface Implementations for DDR4
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
Arria 10 Package Support for DDR4 x40 with ECC for HPS
To support one DDR4 x40 interface with ECC (32 bits data + 8 bits ECC) for HPS, you require two I/O
banks below the top 3 V I/O bank in the DDR column.
Table 6-10: Number of DDR4 x40 Interfaces (with ECC) Supported Per Device Package for HPS
This table lists the number of external memory interfaces supported for HPS only.
Package
Product
Line
U19
F27
F29
F34
F35
F36
NF40
KF40
RF40
NF45
SF45
UF45
SX 160
1
1
1
—
—
—
—
—
—
—
—
—
SX 220
1
1
1
—
—
—
—
—
—
—
—
—
SX 270
—
1
1
1
1
—
—
—
—
—
—
—
SX 320
—
1
1
1
1
—
—
—
—
—
—
—
SX 480
—
—
1
1
1
—
—
—
—
—
—
—
SX 570
—
—
—
1
1
—
1
1
—
—
—
—
SX 660
—
—
—
1
1
—
1
1
—
—
—
—
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
Altera Corporation
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Arria 10 Package Support for DDR4 x72 with ECC Single-Rank
6-13
Arria 10 Package Support for DDR4 x72 with ECC Single-Rank
To support one DDR4 x72 interface (64 bits data + 8 bits ECC) single-rank, you require three I/O banks.
Table 6-11: Number of DDR4 x72 Interfaces (with ECC) Single-Rank Supported Per Device Package
This table lists the number of external memory interfaces supported for the core for each device package. The
numbers shown are using HPS shared I/O banks to implement core EMIF configurations. The number reduces
when HPS shared I/O banks are used to implement HPS EMIF configurations.
Package
Product
Line
U19
F27
F29
F34
F35
F36
NF40
KF40
RF40
NF45
SF45
UF45
GX 160
0
0
0
—
—
—
—
—
—
—
—
—
GX 220
0
0
0
—
—
—
—
—
—
—
—
—
GX 270
—
0
1
1
1
—
—
—
—
—
—
—
GX 320
—
0
1
1
1
—
—
—
—
—
—
—
GX 480
—
—
1
2
1
—
—
—
—
—
—
—
GX 570
—
—
—
2
1
2
2
3
—
—
—
—
GX 660
—
—
—
2
1
2
2
3
—
—
—
—
GX 900
—
—
—
3
—
2
3
—
0
4
3
2
GX 1150
—
—
—
3
—
2
3
—
0
4
3
2
GT 900
—
—
—
—
—
—
3
—
—
—
3
2
GT 1150
—
—
—
—
—
—
3
—
—
—
3
2
SX 160
0
0
0
—
—
—
—
—
—
—
—
—
SX 220
0
0
0
—
—
—
—
—
—
—
—
—
SX 270
—
0
1
1
1
—
—
—
—
—
—
—
SX 320
—
0
1
1
1
—
—
—
—
—
—
—
SX 480
—
—
1
2
1
—
—
—
—
—
—
—
SX 570
—
—
—
2
1
—
2
3
—
—
—
—
SX 660
—
—
—
2
1
—
2
3
—
—
—
—
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
• Examples of External Memory Interface Implementations for DDR4
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
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Arria 10 Package Support for DDR4 x72 with ECC Dual-Rank
Arria 10 Package Support for DDR4 x72 with ECC Dual-Rank
To support one DDR4 x72 interface with ECC (64 bits data + 8 bits ECC) dual-rank, you require 3.25 I/O
banks (three I/O banks and one I/O lane in an adjacent I/O bank).
Table 6-12: Number of DDR4 x72 Interfaces (with ECC) Dual-Rank Supported Per Device Package
This table lists the number of external memory interfaces supported for the core for each device package. The
numbers shown are using HPS shared I/O banks to implement core EMIF configurations. The number reduces
when HPS shared I/O banks are used to implement HPS EMIF configurations.
Package
Product
Line
U19
F27
F29
F34
F35
F36
NF40
KF40
RF40
NF45
SF45
UF45
GX 160
0
0
0
—
—
—
—
—
—
—
—
—
GX 220
0
0
0
—
—
—
—
—
—
—
—
—
GX 270
—
0
1
1
1
—
—
—
—
—
—
—
GX 320
—
0
1
1
1
—
—
—
—
—
—
—
GX 480
—
—
1
1
1
—
—
—
—
—
—
—
GX 570
—
—
—
1
1
1
2
2
—
—
—
—
GX 660
—
—
—
1
1
1
2
2
—
—
—
—
GX 900
—
—
—
2
—
2
3
—
0
4
3
2
GX 1150
—
—
—
2
—
2
3
—
0
4
3
2
GT 900
—
—
—
—
—
—
3
—
—
—
3
2
GT 1150
—
—
—
—
—
—
3
—
—
—
3
2
SX 160
0
0
0
—
—
—
—
—
—
—
—
—
SX 220
0
0
0
—
—
—
—
—
—
—
—
—
SX 270
—
0
1
1
1
—
—
—
—
—
—
—
SX 320
—
0
1
1
1
—
—
—
—
—
—
—
SX 480
—
—
1
1
1
—
—
—
—
—
—
—
SX 570
—
—
—
1
1
—
2
2
—
—
—
—
SX 660
—
—
—
1
1
—
2
2
—
—
—
—
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
• Examples of External Memory Interface Implementations for DDR4
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
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6-15
Arria 10 Package Support for DDR4 x72 with ECC Single-Rank for HPS
Arria 10 Package Support for DDR4 x72 with ECC Single-Rank for HPS
To support one DDR4 x72 interface with ECC (64 bits data + 8 bits ECC) single-rank for HPS, you
require three I/O banks below the top 3 V I/O bank in the DDR column.
Table 6-13: Number of DDR4 x72 Interfaces (with ECC) Single-Rank for HPS Supported Per Device Package
This table lists the number of external memory interfaces supported for HPS only.
Product Line
Package
U19
F27
F29
F34
F35
NF40
KF40
SX 160
0
0
0
—
—
—
—
SX 220
0
0
0
—
—
—
—
SX 270
—
0
0
0
0
—
—
SX 320
—
0
0
0
0
—
—
SX 480
—
—
0
0
0
—
—
SX 570
—
—
—
0
0
0
1
SX 660
—
—
—
0
0
0
1
Related Information
• Device Variants and Packages
Provides more information about the device packages such as the types, sizes, and number of pins.
• Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
• Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller
Provides information on supported memory interface clock frequency per device speed grade.
External Memory Interface IP Support in Arria 10 Devices
Table 6-14: Types of Altera IP Support for Each Memory Standard
This table lists the memory controller IPs provided by Altera. You can also use your own soft memory controller
for all memory standards supported by Arria 10 devices.
Memory Standard
(15)
(16)
(17)
Controller
Hard Sequencer
Hard
Soft
DDR4 SDRAM(15)
Yes
—
Yes
DDR3 SDRAM (16)
Yes
—
Yes
DDR3L SDRAM (16)
Yes
—
Yes
LPDDR3 SDRAM(17)
Yes
—
Yes
x4/x8 DQ group, POD12 I/O standard, and burst lengths BL8.
x4/x8 DQ group and burst lengths BL8.
Arria 10 devices support single component x32 data using x8 DQ group.
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Ping Pong PHY IP
Controller
Memory Standard
Hard Sequencer
Hard
Soft
RLDRAM 3(18)
—
Yes
Yes
QDR IV SRAM
—
Yes
Yes
QDR II/II+/II+ Xtreme SRAM
—
Yes
Yes
Related Information
Memory Standards Supported by Arria 10 Devices on page 6-2
Lists all memory standards that the Arria 10 devices support.
Ping Pong PHY IP
The Ping Pong PHY IP allows two memory interfaces to share address/command buses using time
multiplexing. The Ping Pong PHY IP gives you the advantage of using less pins compared to two
independent interfaces, without any impact on throughput.
Figure 6-2: Conventional 2T Timing
Conventionally, the address and command buses of a DDR3 quarter-rate interface use 2T timing—they
are issued for two full-rate clock cycles.
CK
CSn
Addr, ba
Extra Setup Time
Active Period
2T Command Issued
(18)
Arria 10 devices support this external memory interface using hard PHY with soft memory controller.
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External Memory Interface Architecture of Arria 10 Devices
6-17
Figure 6-3: Ping Pong PHY 1T Timing
With the Ping Pong PHY, address and command signals from two independent controllers are
multiplexed onto shared buses by delaying one of the controller outputs by one full-rate clock cycle. The
result is 1T timing, with a new command being issued on each full-rate clock cycle.
CK
CSn[0]
CSn[1]
Addr, ba
Cmd
Dev1
Cmd
Dev0
Related Information
• Memory Standards Supported by Arria 10 Devices on page 6-2
• Hard Memory Controller Features on page 6-20
External Memory Interface Architecture of Arria 10 Devices
The Arria 10 external memory interface solution is designed to provide a high performance, rapid, and
robust implementation of external memory interfacing. Instead of periphery I/Os like in the previous
generation Arria devices, Arria 10 devices feature columns of I/Os.
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I/O Bank
Figure 6-4: I/O Column Architecture
The I/O column consists of the I/O banks and an I/O-AUX block.
IO-AUX
Hard NIOS
I/O Bank
Controller
Sequencer
I/O Bank
Controller
Sequencer
I/O Bank
Controller
Sequencer
I/O Bank
Controller
Sequencer
I/O Bank
Controller
Sequencer
I/O Bank
Controller
Sequencer
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
I/O Lane
Related Information
• Key Features of the Arria 10 External Memory Interface Solution on page 6-1
• External Memory Interface I/O Pins in Arria 10 Devices on page 6-4
I/O Bank
The hard IP is organized into vertical I/O banks. These modular I/O banks can be stitched together to
form large interfaces.
Each I/O bank consists of the following blocks:
•
•
•
•
Altera Corporation
Embedded hard controller
Hard sequencer
Dedicated DLL
Integer PLL
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Hard Memory Controller
6-19
• OCT calibration block
• PHY clock network
• Four I/O lanes
Hard Memory Controller
The Arria 10 hard memory controller is designed for high speed, high performance, high flexibility, and
area efficiency. The hard memory controller supports all the popular and emerging memory standards
including DDR4, DDR3, and LPDDR3.
The high performance is achieved by implementing advanced dynamic command and data reordering
algorithms. In addition, efficient pipelining techniques are also applied to the design to improve the
memory bandwidth usage and reduce the latency while keeping the speed high. The hard solution offers
the best availability and shorter time-to-market. The timing inside the controller and from the controller
to the PHY have been pre-closed by Altera—simplifying timing closure.
The controller architecture is a modular design and fits in a single I/O bank. This structure offers you the
best flexibility from the hard solution:
• You can configure each I/O bank as either one of the following paths:
• A control path that drives all the address/command pins for the memory interface.
• A data path that drives up to 32 data pins for DDR-type interfaces.
• You can place your memory controller in any location.
• You can pack up multiple banks together to form memory interfaces of different widths up to 144 bits.
For more flexibility, you can bypass the hard memory controller and use your custom IP if required.
Figure 6-5: Hard Memory Controller Architecture
Command
Generator
ECC / RMW
Controller
Global Timer
Burst
Adapter
Timing
Bank Pool
Arbiter
Data Buffer
Control
Burst_gen
AFI Interface
Input Interface / AMM Adapter
Sideband
Control
Register
Control MMR
Read / Write Data Buffer
The hard memory controller consists of the following logic blocks:
•
•
•
•
Core and PHY interfaces
Main control path
Data buffer controller
Read and write data buffers
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Hard Memory Controller Features
The core interface supports both Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming
(Avalon-ST) interface protocols. The interface communicating to PHY follows the Altera PHY Interface
(AFI) protocol. The whole control path is split into the main control path and the data buffer controller.
Hard Memory Controller Features
Table 6-15: Features of the Arria 10 Hard Memory Controller
Feature
Memory devices support
Description
Supports the following memory devices:
• DDR4 SDRAM
• DDR3 SDRAM
• LPDDR3 for low power
Memory controller support
• Custom controller support—configurable bypass mode that allows
you to bypass the hard memory controller and use custom
controller.
• Ping Pong controller—allows two instances of the hard memory
controller to time-share the same set of address/command pins.
Interface protocols support
• Supports Avalon-MM and Avalon-ST interfaces.
• The PHY interface adheres to the AFI protocol.
Rate support
You can configure the controller to run at half rate or quarter rate.
Configurable memory interface
width
Supports widths from 8 to 144 bits, in 8 bits increments
Multiple ranks support
Supports up to 4 ranks.
Burst adaptor
Able to accept bursts of any size up to a maximum burst length of 255
on the local interface of the controller and map the bursts to efficient
memory commands.
Efficiency optimization features
• Open-page policy—by default, data traffic is closed-page on every
access. However, the controller will intelligently keep a row open
based on incoming traffic, which can improve the efficiency of the
controller especially for random traffic.
• Pre-emptive bank management—the controller is able to issue bank
management commands early, which ensure that the required row
is open when the read or write occurs.
• Data reordering—the controller reorders read/write commands.
• Additive latency—the controller can issue a READ/WRITE
command after the ACTIVATE command to the memory bank
prior to tRCD, which increases the command efficiency.
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Hard Memory Controller Features
Feature
6-21
Description
User requested priority
You can assign priority to commands. This feature allows you to
specify that higher priority commands get issued earlier to reduce
latency.
Starvation counter
Ensures all requests are served after a predefined time out period,
which ensures that low priority access are not left behind while
reordering data for efficiency.
Timing for address/command
bus
To maximize command bandwidth, you can double the number of
memory commands in one controller clock cycle:
• Quasi-1T addressing for half-rate address/command bus.
• Quasi-2T addressing for quarter-rate address/command bus.
Bank interleaving
Able to issue read or write commands continuously to "random"
addresses. You must correctly cycle the bank addresses.
On-die termination
The controller controls the on-die termination signal for the memory.
This feature improves signal integrity and simplifies your board design.
Refresh features
• User-controlled refresh timing—optionally, you can control when
refreshes occur and this allows you to prevent important read or
write operations from clashing with the refresh lock-out time.
• Per-rank refresh—allows refresh for each individual rank.
• Controller-controlled refresh.
ECC support
• 8 bit ECC code; single error correction, double error detection
(SECDED).
• User ECC supporting pass through user ECC bits as part of data
bits.
DQS tracking
Track the DQS timing and make auto adjustment.
Power saving features
• Low power modes (power down and self-refresh)—optionally, you
can request the controller to put the memory into one of the two
low power states.
• Automatic power down—puts the memory device in power down
mode when the controller is idle. You can configure the idle waiting
time.
• Memory clock gating.
Mode register set
Access the memory mode register.
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Main Control Path
Feature
Description
DDR4 features
• Bank group support—supports different timing parameters for
between bank groups.
• Data Bus CRC—data bus encoding and decoding.
• Command/Address parity—command and address bus parity
check.
• Alert reporting—responds to the error alert flag.
• Multipurpose register access— supports multipurpose register
access in serial readout mode.
• Fine granularity refresh—supports 1x, 2x, and 4x fixed refresh rates.
• Temperature controlled refresh—adjust refresh rate according to
temperature range.
• Low power auto self refresh— operating temperature triggered auto
adjustment to self refresh rate.
• Gear down mode—allows memory device to run at either 1N or 2N
rate. Supports only fixed configuration but not the on-the-fly
change.
• Maximum power saving.
LPDDR3 feature
• Deep power down mode—achieves maximum power reduction by
eliminating power to memory array. Data will not be retained when
the device enters the deep power down mode.
• Partial array self refresh.
• Per bank refresh.
User ZQ calibration
User-controlled long or short ZQ calibration request for DDR3 or
DDR4.
Related Information
Ping Pong PHY IP on page 6-16
Provides a brief description of the Ping Pong PHY.
Main Control Path
The main control path performs the following functions:
•
•
•
•
Altera Corporation
Contains the command processing pipeline.
Monitors all the timing parameters.
Keeps track of memory access commands dependencies.
Guards against memory access hazards.
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Main Control Path
6-23
Table 6-16: Main Control Path Components
Component
Description
Input interface
• Accepts memory access commands from the core logic at half or quarter rate.
• Uses the Avalon-MM or Avalon-ST protocol. The default protocol is AvalonST. You can enable a hard adapter through a configuration register to make
the input interface Avalon-MM compatible.
• The hard memory controller has a native Avalon-ST interface. You can
instantiate a standard soft adaptor to bridge the Avalon-ST interface to
AMBA AXI.
• To support all bypass modes and keep the port count minimum, the super set
of all port lists is used as the physical width. Ports are shared among the
bypass modes.
Command generator
and burst adapter
• Drains your commands from the input interface and feeds them to the timing
bank pool.
• If read-modify-write is required, inserts the necessary read-modify-write read
and write commands into the stream.
• The burst adapter chops your arbitrary burst length to the number specified
by the memory types.
• Burst chop feature is supported for DDR3 and DDR4.
Timing Bank Pool
• Key component in the memory controller.
• Sets parallel queues to track command dependencies.
• Signals the ready status of each command being tracked to the arbiter for the
final dispatch.
• Big scoreboard structure. The number of entries is currently sized to 8 where
it monitors up to 8 commands at the same time.
• Handles the memory access hazards (RAW, WAR and WAW) while part of
the timing constraints are being tracked.
• High responsibility to assist the arbiter in implementing reordering:
• Row command reordering (activate and pre-charge).
• Column command reordering (read and write).
• When the pool is full, a flow control signal will be sent back upstream to stall
the traffic.
Arbiter
• Enforces the arbitration rules.
• Performs the final arbitration to select a command from all ready commands,
and issues the selected command to the memory.
• Supports quasi-1T mode for half rate and quasi-2T mode for quarter rate.
• For the quasi modes, a row command must be paired with a column
command.
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Data Buffer Controller
Component
Global Timer
Description
Tracks the global timing constraints including:
• tFAW—the Four Activates Window parameter that specifies the time period in
which only four activate commands are allowed.
• tRRD—the delay between back-to-back activate commands to different banks.
• Some of the bus turnaround time parameters.
MMR/IOCSR
•
•
•
•
Sideband
Executes the refresh and power down features.
ECC controller
Although ECC encoding and decoding is performed in soft logic(19), the ECC
controller maintains the read-modify-write state machine in the hard solution.
AFI interface
The memory controller communicates to the PHY using this interface.
The host of all the configuration registers.
Uses Avalon-MM bus to talk to the core.
Core logic can read and write all the configuration bits.
The debug bus is routed to the core through this block.
Data Buffer Controller
The data buffer controller has the following main responsibilities:
• Manages the read and write access to the data buffers:
• Provides the data storing pointers to the buffers when the write data is accepted or the read return
data arrives.
• Provides the draining pointer when the write data is dispatched to memory or the read data is read
out of the buffer and sent back to users.
• Satisfies the required write latency.
• If ECC support is enabled, assists the main control path to perform read-modify-write.
Data reordering is performed with the data buffer controller and the data buffers.
Each I/O bank contains two data buffer controller blocks for the data buffer lanes that are split within
each bank. To improve your timing, place the data buffer controller physically close to the I/O lanes.
Delay-Locked Loop
The delay-locked loop (DLL) finds the delay setting for 9 bits delay chain so that the delay of the chain is
equivalent to one clock cycle.
Each I/O bank has one delay-locked loop (DLL) located in the center that supports a frequency range of
800 MHz to 1.3 GHz.
(19)
ECC encoding and decoding is performed in soft logic to exempt the hard connection from routing data
bits to a central ECC calculation location. Routing data to a central location removes the modular design
benefits and reduces flexibility.
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Sequencer
6-25
The reference clock for the DLL comes from the output of the PLL in the same I/O bank. The DLL divides
the reference clock by eight and creates two clock pulses—launch and measure. The phase difference
between launch and measure is one reference clock cycle. The clock pulse launch is routed through the
delay setting controlled by the delay chain. The delayed launch is then compared to measure.
The setting for the DLL delay chains is from a 9 bit counter, which moves up or down to alter the delay
time until the delayed launch and measure are aligned in the same phase. Once the DLL is locked, the
delay through the delay chain is equivalent to one reference clock cycle, and the delay setting is sent out to
the DQS delay block.
Sequencer
The sequencer enables high-frequency memory interface operation by calibrating the interface to
compensate for variations in setup and hold requirements caused by transmission delays.
The sequencer implements a calibration algorithm to determine the combination of delay and phase
settings that are necessary to maintain center-alignment of data and clock signals, even in the presence of
significant delay variations. Programmable delay chains in the FPGA I/Os then implement the calculated
delays to ensure that data remains centered.
A sequencer is embedded in every I/O bank. The sequencer is comprised of the following components:
•
•
•
•
A read-write manager.
An address/command set or instruction ROM.
Helper modules such as PHY manager, data manager, and tracking manager.
Data pattern and data out buffers on a per-pin basis that are managed by the read-write manager.
All major components of the sequencer are connected on the Avalon bus, providing controllability,
visibility, and flexibility to the Nios II subsystem.
Figure 6-6: Sequencer
Bridge
IO48
Sequencer
IO48
Sequencer
IO48
Sequencer
Avalon Bus
Write, Read, Clock, Address[19:0], Write_Data[31:0], Read_Data[31:0]
87
Cmd_decoder
Inst_ROM (128)
Sequencer
IO48
Sequencer
IO48
Sequencer
Current
Mirror
IO48
IO AUX
dq_out_delay
LFIFO
dqs_out_delay
VFIFO
dq_in_delay
Postamble_tracking
dqs_in_delay
x12_checker
x1_checker
AC DO ROM (64)
AC ROM (512)
PHY Manager
rd pattern RAM (64)
x4
Bridge
External Memory
Interface Microcontroller
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x48
Per bank control
Per lane control
Per I/O control
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Clock Tree
The Arria 10 external memory interface PHY clock network is designed to support the 1.3 GHz DDR4
memory standard.
Compared to previous generation devices, the PHY clock network has a shorter clock tree that generates
less jitter and less duty cycle distortion.
The PHY clock network consists of:
• Reference clock tree
• PHY clock tree
• DQS clock tree
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Clock Tree
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Figure 6-7: Clock Network Diagram
The reference clock tree adopts a modular design to facilitate easy integration.
2
I/O Bank
2
x16/x18 DQS/DQSB
x8/x9 DQS/DQSB
2
x32/x36 DQS/DQSB
2
2
2
13
I/O Lane
2
48
13
I/O Lane
48
I/O Center
Hard Memory
Controller and
Sequencer
Clock in pins
Splitter
2
2
2
DQS clock tree
6
x8/x9 DQS/DQSB
2
x16/x18 DQS/DQSB
2
I/O PLL
4
2
Only half of the
recovered clock
connect to PCLK
GPIO register clocks
from core clock network
To core clock network
To core fb clock network
Core reference clock
ioclkin[3:0]
8
13
2
2
2
core_clk_in[1:0]
core_clk_out[1:0]
6
6
6
6
6
6
6
13
I/O Lane
I/O Lane
Recovered clock to
PCLK network
fbclk_in
DLL
2
pllcout[8:0]
pllmout
coreclk
GPIO register clocks
from core clock network
13
dll clk
core fb
lvds fb
phy_clk_phs
lvds fb
Phase Align
core fb
phy_clk[1:0]
pa_clkout
2
x8/x9 DQS/DQSB
ext_clk
9
pll ccnt out
pll mcnt out
clkpin_in
4
Reference CLK
Clock out pins
cascad_out
cascad_in
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
PHY CLK
x8/x9 DQS/DQSB
6
6
6
6
6
6
6
6
6
6
6
6
48
6
6
6
6
48
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
LVDS/DPA
GPIO register clocks
from core clock network
Recovered clock to
PCLK network
Only half of the
recovered clock
connect to PCLK
GPIO register clocks
from core clock network
2
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I/O Lane
I/O Lane
There are four I/O lanes in each I/O bank. Each I/O lane contains 12 I/O pins with identical read and
write data paths and buffers.
Figure 6-8: I/O Lane Architecture
PLL
I/O Lane
DLL
To IO_AUX Avalon bus
To hard logic and core
Dynamic
OCT Control
Avalon-MM
Read
Data
Buffer
Read
FIFO
Write
Data
Buffer
Write
FIFO
DDIO
DQ Delay
DQS Delay
To buffers
Phase
Interpolator
FIFO
Control
Per bit logic
Per lane logic
Per bank logic
Post-amble
Data Path Component
Description
Input path
Contains capture registers and read FIFO.
Output or output enable (oe) path
Consists of:
• Write FIFO
• Clock mux
• Phase intepolater— supports around 5 to 10 ps
resolution based on frequency
• Double data rate control
Input delay chain
Supports around 5 ps resolution with a delay range of 0 to
625 ps.
Read/write buffer
The write data buffer has built in options to take data from
the core or from the hard memory controller.
Related Information
General Pin-Out Guidelines for Arria 10 EMIF IP
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DQS Logic Block
6-29
DQS Logic Block
The DQS logic block contains:
•
•
•
•
Post-amble register
DQS delay chain
FIFO control
Multi-rank switch control block
DQS Delay Chain
The DQS delay chain provides variable delay to the DQS signal, allowing you to adjust the DQS signal
timing during calibration to maximize the tsetup and thold for DQ capture.
To keep the delay value constant, the DQS delay chain also contains:
• Logic to track temperature and low frequency voltage variation
• Shadow registers to hold calibrated delay settings for multi-rank interfaces, and switch the DQS delay
chain setting to one of up to four different settings.
I/O AUX
There is one I/O AUX block in each I/O column:
• Contains a hard Nios II processor and supporting embedded memory block.
• Handles the calibration algorithm for the entire I/O column
• Communicates to the sequencer in each I/O bank through a dedicated Avalon interface
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I/O AUX
Figure 6-9: IO AUX Block Diagram
IO AUX
JTAG
Debug
Core
Interrupt
Hard
NIOS
Avalon Decoder
RAM
Interval
Timer
Address Wrapper
to use ECC bit for data
Avalon
Decoder
Avalon
Decoder
Master 1
Slave 2
Configuration
Data Wrapper
Slave 1
Slave 5
Master 2
Slave 4
Slave 3
Avalon
Decoder
Avalon
Decoder
Async.
Clock
Crossing
FIFO
Avalon
Decoder
Async.
Clock
Crossing
FIFO
Avalon Decoder
Debug
Registers
CORE
SLD node
SLD Hub
Sequencer
Bridge
Calibration bus
to I/O banks
Avalon Interconnect
Generates wait
for NIOS
To
Signal Tap
To Debug Console
The hard Nios II processor performs the following operations:
• Configures and starts calibration tasks on the sequencers
• Collects and processes data
• Uses the final results to configure the I/Os
A combination of both Nios II code and the sequencers, the algorithm implementation supports calibra‐
tion for the following memory interface standards:
•
•
•
•
DDR2, DDR3, and DDR4 SDRAM
QDR II and QDR IV SRAM
RLDRAM 3
LPDDR2 and LPDDR3
Note: Altera recommends that you use the Nios subsystem for memory interface calibration.
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Document Revision History
Date
Version
Changes
November
2015
2015.11.02
• Removed BC4 and On-the-fly supports for DDR4, DDR3 and DDR3L
SDRAM in Table Types of Altera IP Support for Each Memory
Standard.
• Change supported DQ Group for DDR4, DDR3, and DDR3L
SDRAM to x4/x8 in Table Types of Altera IP Support for Each
Memory Standard.
• Added LPDDR3 SDRAM in hard memory controller and IP support.
• Added link to Arria 10 Device Datasheet - Memory Standards
Supported by the Hard Memory Controller and Arria 10 Device
Datasheet - Memory Standards Supported by the Soft Memory
Controller.
• Added Arria 10 package support for DDR3 x32 with ECC for HPS,
DDR3 x 72 Single and Dual-Rank for HPS, DDR4 x32 with ECC for
HPS, and DDR3 x72 Single-Rank tables.
• Changed instances of Quartus II to Quartus Prime.
June 2015
2015.06.15
Removed the DFI label on the figure showing the hard memory
controller architecture. Arria 10 devices do not support DFI.
May 2015
2015.05.15
Corrected the DDR3 half rate and quarter rate maximum frequencies in
the table that lists the memory standards supported by the Arria 10 hard
memory controller.
May 2015
2015.05.04
Updated the table that lists the memory standards supported by the hard
memory controller in Arria 10 devices.
January 2015
2015.01.23
• Updated the table that lists the memory standards supported by Arria
10 devices.
• Removed hard memory controller and IP support for LPDDR3
SDRAM.
• Removed support for RLDRAM 2.
• Updated support for QDR II+/II+ Xtreme SRAM to also include
QDR II SRAM.
• Added soft memory controller support for QDR IV.
• Added footnote to clarify that the number of DDR4 x32 interfaces
support for the F34 package of the Arria 10 SX 480 device includes
using I/O bank 2K. If you use I/O bank 2K in a DDR4 x32 interface
for the FPGA, the HPS will not have access to a DDR4 x32 interface.
• Added information to clarify that the DDR3 and DDR4 x32 interface
with ECC includes 32 bits data and 8 bits ECC.
• Removed information about hard and soft portions of the Nios
subsytem. The hard memory controller IP for Arria 10 calibrates the
external memory interface using the hard Nios II processor only.
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Document Revision History
Date
Version
August 2014
2014.08.18
• Removed hard memory controller half rate support for DDR4
SDRAM.
• Removed hard memory controller and IP support for DDR3U
SDRAM.
• Added soft memory controller full rate support for QDR II+ SRAM
and QDR II+ Xtreme SRAM.
• Updated the list of external memory standards supported by the HPS.
• Updated the number of DDR3 x72 (single-rank) memory interfaces
supported for the U19 package.
• Removed the note about using 3 V I/O banks for the HPS. For the
HPS, the 3 V I/O bank is not used for external memory interfaces.
• Updated the number of DDR3 x72 (dual-rank) memory interfaces
supported for the Arria 10 SX devices.
• Updated the number of DDR4 x32 (with ECC) memory interfaces
supported for the NF45 package of the Arria 10 GT 1150 device.
• Added soft memory controller IP support for QDR II+ SRAM.
• Added information to clarify that RLDRAM3 support uses hard PHY
with soft memory controller.
• Updated the table that lists the features of the hard memory
controller to improve accuracy and add missing information.
• Added a note before the topics listing external memory interface
package support to clarify that not all I/O banks are available for
external memory interfaces.
• Moved the external memory interface pins guidelines and the
examples of external memory interface implementations for DDR4 to
the External Memory Interface Handbook.
December
2013
2013.12.10
Updated the HPS memory standards support from LPDDR2 to
LPDDR3.
December
2013
2013.12.02
Initial release.
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Configuration, Design Security, and Remote
System Upgrades in Arria 10 Devices
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A10-CONFIG
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This chapter describes the configuration schemes, design security, and remote system upgrade that are
supported by the Arria 10 devices.
Related Information
• Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
• Arria 10 Device Datasheet
Provides more information about the estimated uncompressed .rbf file sizes, FPP DCLK-to-DATA[]
ratio, and timing parameters for all supported configuration schemes.
Enhanced Configuration and Configuration via Protocol
Table 7-1: Configuration Schemes and Features of Arria 10 Devices
Arria 10 devices support 1.8 V programming voltage and several configuration modes.
Scheme
(20)
(21)
(22)
(23)
Data
Width
Max Clock
Max Data
Decompression
Design
Partial
Rate
Rate (Mbps)
Security (2 Reconfiguration
(20)
1)
(22)
(MHz)
Remote
System
Update
JTAG
1 bit
33
33
—
—
Yes(23)
—
Active Serial
(AS) through
the EPCQ-L
configuration
device
1 bit,
100
400
Yes
Yes
Yes(23)
Yes
4 bits
Enabling either compression or design security features affects the maximum data rate. Refer to the Arria 10
Device Datasheet for more information.
Encryption and compression cannot be used simultaneously.
Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial
reconfiguration, contact Altera for support.
Partial configuration can be performed only when it is configured as internal host.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
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Configuration Schemes
Scheme
Data
Width
Passive serial
(PS) through
CPLD or
external
microcon‐
troller
1 bit
Fast passive
parallel (FPP)
through
CPLD or
external
microcon‐
troller
Configuration
via HPS
Max Clock
Max Data
Decompression
Design
Partial
Rate
Rate (Mbps)
Security (2 Reconfiguration
(20)
1)
(22)
(MHz)
Yes
Yes
8 bits
Yes
Yes
16 bits
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
32 bits
16 bits
32 bits
Configuration x1, x2,
via Protocol
[CvP (PCIe)] x4, and
100
100
100
3200
100
3200
—
8000
Yes(23)
Remote
System
Update
Parallel
Flash
Loader
(PFL) IP
core
Yes(24)
PFL IP
core
Yes(24)
—
Yes(23)
—
x8 lanes
You can configure Arria 10 devices through PCIe using Configuration via Protocol (CvP). The Arria 10
CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.
Related Information
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Provides more information about the CvP configuration scheme.
Configuration Schemes
This section describes the AS, PS, FPP, and JTAG configuration schemes.
Related Information
• Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Provides more information about the CvP configuration scheme.
(20)
(21)
(22)
(24)
Enabling either compression or design security features affects the maximum data rate. Refer to the Arria 10
Device Datasheet for more information.
Encryption and compression cannot be used simultaneously.
Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial
reconfiguration, contact Altera for support.
Supported at a maximum clock rate of 100 MHz.
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Active Serial Configuration
7-3
• Design Planning for Partial Reconfiguration
Provides more information about partial reconfiguration.
Active Serial Configuration
Figure 7-1: High-Level Overview of EPCQ-L Programming for the AS Configuration Scheme
Quartus Prime
Software
Configuration Data
using JTAG
FPGA
SFL
EPCQ-L
In the AS configuration scheme, configuration data is stored in the EPCQ-L configuration device. You
can program the EPCQ-L device in-system using the JTAG interface with the Serial Flash Loader (SFL) IP
core. You can do so by using an FPGA as a bridge between the JTAG interface and the EPCQ-L device.
The AS memory interface block in the Arria 10 device controls the configuration process.
The AS configuration scheme supports AS x1 (1-bit data width) and AS x4 (4-bit data width) modes. The
AS x4 mode provides four times faster configuration time than the AS x1 mode. In the AS configuration
scheme, the Arria 10 device controls the configuration interface.
Note: For SFL Programming, the MSEL pins must be set to Active Serial to prevent programmer fails to
read the EPCQ-L ID.
Related Information
• Arria 10 Device Datasheet
Provides more information about the AS configuration timing.
• AN 370: Using the Serial Flash Loader with the Quartus Prime Software
• Nios II Flash Programmer User Guide
• EPCQ-L Serial Configuration Devices Datasheet
• EPCQ-L Device Package Information
Provides more information about EPCQ-L packaging specifications, thermal resistance and
dimensions.
DATA Clock (DCLK)
Arria 10 devices generate the serial clock, DCLK, that provides timing to the serial interface. In the AS
configuration scheme, Arria 10 devices drive control signals on the falling edge of DCLK and latch the
configuration data on the following falling edge of this clock pin.
The maximum DCLK frequency supported by the AS configuration scheme is 100 MHz. You can source
DCLK using CLKUSR or the internal oscillator. If you use the internal oscillator, you can choose a 12.5, 25,
50, or 100 MHz clock under the Device and Pin Options dialog box, in the Configuration page of the
Quartus Prime software.
After power-up, DCLK is driven by a 12.5 MHz internal oscillator by default. The Arria 10 device
determines the clock source and frequency to use by reading the option bit in the programming file.
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Active Serial Single-Device Configuration
Related Information
Arria 10 Device Datasheet
Provides more information about the DCLK frequency specification in the AS configuration scheme.
Active Serial Single-Device Configuration
To configure Arria 10 device, connect the device to a quad-serial configuration (EPCQ-L) device, as
shown in the following figures.
Figure 7-2: Single Device AS x1 Mode Configuration
Connect the pull-up resistors to
V CCPGM at 1.8-V power supply.
V CCPGM
V CCPGM
10 kΩ
V CCPGM
10 kΩ
10 kΩ
EPCQ-L Device
FPGA Device
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA
DCLK
nCS
ASDI
Altera Corporation
GND
AS_DATA1
DCLK
nCSO[0]
ASDO
nCEO
MSEL[2..0]
CLKUSR
N.C.
For more information,
refer to the MSEL pin
settings.
You can use CLKUSR pin to
supply the external clock
source to drive DCLK
during configuration.
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Active Serial Multi-Device Configuration
7-5
Figure 7-3: Single Device AS x4 Mode Configuration
Connect the pull-up resistors to
V CCPGM at 1.8-V power supply.
V CCPGM
V CCPGM
10 kΩ
V CCPGM
10 kΩ
10 kΩ
EPCQ-L Device
FPGA Device
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
GND
AS_DATA0/
ASDO
AS_DATA1
AS_DATA2
AS_DATA3
DCLK
nCSO[0]
nCEO
N.C.
For more information,
refer to the MSEL pin
settings.
MSEL[2..0]
CLKUSR
You can use CLKUSR pin to
supply the external clock
source to drive DCLK
during configuration.
Active Serial Multi-Device Configuration
You can configure multiple Arria 10 devices that are connected to a chain. Only AS x1 mode supports
multi-device configuration.
The first device in the chain is the configuration master. Subsequent devices in the chain are configuration
slaves.
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Pin Connections and Guidelines
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Hardwire the MSEL pins of the first device in the chain to select the AS configuration scheme. For
subsequent devices in the chain, hardwire their MSEL pins to select the PS configuration scheme. Any
other Altera® devices that support the PS configuration can also be part of the chain as a configuration
slave.
• Tie the following pins of all devices in the chain together:
•
•
•
•
•
nCONFIG
nSTATUS
DCLK
DATA[]
CONF_DONE
By tying the CONF_DONE, nSTATUS, and nCONFIG pins together, the devices initialize and enter user
mode at the same time. If any device in the chain detects an error, configuration stops for the entire
chain and you must reconfigure all the devices. For example, if the first device in the chain flags an
error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.
• Ensure that DCLK and DATA[] are buffered every fourth device to prevent signal integrity and clock
skew problems.
Using Multiple Configuration Data
To configure multiple Arria 10 devices in a chain using multiple configuration data, connect the devices
to an EPCQ-L device, as shown in the following figure.
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Active Serial Configuration with Multiple EPCQ-L Devices
7-7
Figure 7-4: Multiple Device AS Configuration When Both Devices in the Chain Receive Different Sets of
Configuration Data
Connect the pull-up resistors to
V CCPGM at a 1.8-V power
supply.
V CCPGM
V CCPGM
V CCPGM
10 kΩ
10 kΩ
10 kΩ
EPCQ-L Device
FPGA Device Master
FPGA Device Slave
nSTATUS
nSTATUS
CONF_DONE
CONF_DONE
nCONFIG
nCE
nCONFIG
nCEO
nCE
nCEO
GND
DATA
DCLK
AS_DATA1
DCLK
nCS
ASDI
nCSO[0]
ASDO
You can leave the nCEO pin
unconnected or use it as a user I/O
pin when it does not feed another
device’s nCE pin.
MSEL[2..0]
CLKUSR
DATA0
DCLK
MSEL [2..0]
For the appropriate MSEL settings
based on POR delay settings, set the
slave device MSEL setting to the PS
scheme.
Buffers
Connect the repeater buffers between the
FPGA master and slave device for AS_DATA1
or DATA0 and DCLK for every fourth device.
For more information, refer to the
MSEL pin settings.
You can use the CLKUSR pin to
supply the external clock source to
drive DCLK during configuration.
When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next
device in the chain. Configuration automatically begins for the second device in one clock cycle.
Active Serial Configuration with Multiple EPCQ-L Devices
Arria 10 devices support up to three EPCQ-L devices for configuration and remote system upgrade.
You can use up to three EPCQ-L devices per Arria 10 device. Each EPCQ-L device gets a dedicated nCSO
pin, but shares other pins, as shown in the following figure.
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Estimating the Active Serial Configuration Time
Figure 7-5: AS Configuration with Multiple EPCQ-L Devices
VCCPGM VCCPGM
10 KΩ
EPCQ-L 0
DATA0
DATA1
DATA2
DATA3
CONFDONE
nSTATUS
nCE
10 KΩ
10 KΩ
AS_DATA0/ASDO
AS_DATA1
AS_DATA2
AS_DATA3
DCLK
nCS
FPGA
nCEO
MSEL[2:0]
DCLK
nCS[0]
nCS[1]
nCS[2]
EPCQ-L 1
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
EPCQ-L 2
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
You can configure the number of EPCQ-L devices using the Quartus Prime software.
Estimating the Active Serial Configuration Time
The AS configuration time is mostly the time it takes to transfer the configuration data from an EPCQ-L
device to the Arria 10 device. By default, the AS x1 mode is used. The Arria 10 device determines the AS
mode by reading the option bit in the programming file.
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Using EPCQ-L Devices
7-9
Use the following equations to estimate the configuration time:
• AS x1 mode
.rbf Size x (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum configuration time.
• AS x4 mode
.rbf Size x (minimum DCLK period / 4 bits per DCLK cycle) = estimated minimum configuration time.
Compressing the configuration data decreases the configuration time. The amount of time increased
varies depending on the configuration method and corresponding DCLK ratio.
Using EPCQ-L Devices
EPCQ-L devices support AS x1 and AS x4 modes.
Note: Arria 10 devices support EPCQ-L devices only.
Each Arria 10 device has three nCSO pins—nCSO[2..0]. This allows Arria 10 device to connect up to three
EPCQ-L devices.
The advantages of connecting up to three EPCQ-L devices:
• Ability to store multiple design files for remote system upgrade.
• Increase storage beyond the largest single EPCQ-L device available.
Related Information
• EPCQ-L Serial Configuration Devices Datasheet
• EPCQ-L Device Package Information
Provides more information about EPCQ-L packaging specifications, thermal resistance and
dimensions.
Controlling EPCQ-L Devices
During configuration, Arria 10 devices enable the EPCQ-L device by driving its nCSO output pin low,
which connects to the chip select (nCS) pin of the EPCQ-L device. Arria 10 devices use the DCLK and ASDO
pins to send operation commands and read address signals to the EPCQ-L device. The EPCQ-L device
provides data on its serial data output (DATA[]) pin, which connects to the AS_DATA[] input of the Arria
10 devices.
Note: If you wish to gain control of the EPCQ-L pins, hold the nCONFIG pin low and pull the nCE pin
high. This causes the device to reset and tri-state the AS configuration pins.
Trace Length Guideline
The maximum trace length apply to both single- and multi-device AS configuration setups as listed in the
following table. The trace length is the length from the Arria 10 device to the EPCQ-L device.
Note: The maximum skew between board level DCLK and AS_DATA [3..0] traces should not be more
than 400 ps.
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Programming EPCQ-L Devices
Table 7-2: Maximum Trace Length for AS x1 and x4 Configurations for Arria 10 Devices
Arria 10 Device AS Pins
Maximum Board Trace Length (Inches)
12.5/ 25/ 50 MHz
100 MHz
DCLK
10
6
AS_DATA[3..0]
10
6
nCSO[2..0]
10
6
Related Information
AS Timing Parameters in Arria 10 Device Datasheet
Provides more information about data setup time and hold time requirement.
Programming EPCQ-L Devices
You can program EPCQ-L devices in-system using a USB-Blaster™, EthernetBlaster, EthernetBlaster II, or
ByteBlaster™ II download cable. Alternatively, you can program the EPCQ-L using a microprocessor with
the SRunner software driver.
In-system programming (ISP) offers you the option to program the EPCQ-L either using an AS program‐
ming interface or a JTAG interface. Using the AS programming interface, the configuration data is
programmed into the EPCQ-L by the Quartus Prime software or any supported third-party software.
Using the JTAG interface, an Altera IP called the SFL IP core must be downloaded into the Arria 10
device to form a bridge between the JTAG interface and the EPCQ-L. This allows the EPCQ-L to be
programmed directly using the JTAG interface.
Related Information
• AN 370: Using the Serial Flash Loader with the Quartus Prime Software
• AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming
• Nios II Flash Programmer User Guide
Programming EPCQ-L Using the JTAG Interface
To program an EPCQ-L device using the JTAG interface, connect the device as shown in the following
figure.
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Programming EPCQ-L Using the Active Serial Interface
7-11
Figure 7-6: Connection Setup for Programming the EPCQ-L Using the JTAG Interface
V CCPGM
V CCPGM
10 kΩ
V CCPGM
10 kΩ
10 kΩ
EPCQ-L Device
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
GND
Connect the pull-up resistors to
V CCPGM at a 1.8-V
power supply.
V CCPGM V CCPGM
FPGA Device
nSTATUS
TCK
CONF_DONE
TDO
nCONFIG
nCE
TMS
TDI
AS_DATA0/ASDO
AS_DATA1
AS_DATA2 Serial
Flash
AS_DATA3
Loader
DCLK
nCSO[0] MSEL[2..0]
CLKUSR
Instantiate SFL in your
design to form a bridge
between the EPCQ-L and
the 10-pin header.
V CCPGM
The resistor value can vary
from 1 k Ω to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for your
setup.
Pin 1
1 kΩ
Download Cable
GND 10-Pin Male Header GND
(JTAG Mode) (Top View)
For more information, refer to
the MSEL pin settings.
Use the CLKUSR pin to supply the external clock
source to drive DCLK during configuration.
Programming EPCQ-L Using the Active Serial Interface
To program an EPCQ-L device using the AS interface, connect the device as shown in the following
figure.
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Programming EPCQ-L Using the Active Serial Interface
Figure 7-7: Connection Setup for Programming the EPCQ-L Using the AS Interface
Using the AS header, the programmer serially transmits the operation commands and configuration bits
to the EPCQ-L on DATA0.
Connect the pull-up resistors to V CCPGM
at a 1.8-V power supply.
V CCPGM
V CCPGM
V CCPGM
10 kΩ 10 kΩ 10 kΩ
FPGA Device
CONF_DONE
nCEO
nSTATUS
nCONFIG
nCE
EPCQ-L Device
10 kΩ
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
AS_DATA0/ASDO
AS_DATA1
AS_DATA2
AS_DATA3
MSEL[2..0]
DCLK
CLKUSR
nCSO[0]
Pin 1
V CCPGM
N.C.
For more information, refer to
the MSEL pin settings.
Use the CLKUSR pin to supply
the external clock source to
drive DCLK during
configuration.
Power up the USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II cable’s
V CC(TRGT) to V CCPGM .
USB-Blaster or ByteBlaster II
GND
(AS Mode)
10-Pin Male Header
When programming the EPCQ-L devices, the download cable disables access to the AS interface by
driving the nCE pin high. The nCONFIG line is also pulled low to hold the Arria 10 device in the reset stage.
After programming completes, the download cable releases nCE and nCONFIG, allowing the pull-down and
pull-up resistors to drive the pin to GND and VCCPGM, respectively.
During the EPCQ-L programming using the download cable, DATA0 transfers the programming data,
operation command, and address information from the download cable into the EPCQ-L. During the
EPCQ-L verification using the download cable, DATA1 transfers the programming data back to the
download cable.
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Passive Serial Configuration
7-13
Passive Serial Configuration
Figure 7-8: High-Level Overview of Flash Programming for PS Configuration Scheme
Quartus Prime
Software
Configuration Data
using JTAG
CPLD
FPGA
PFL
Common
Flash
Interface
Altera FPGA Not Used
for Flash Programming
CFI Flash
Memory
The PS configuration scheme uses an external host. You can use a microprocessor, MAX II device,
MAX V device, or a host PC as the external host.
You can use an external host to control the transfer of configuration data from an external storage such as
flash memory to the FPGA. The design that controls the configuration process resides in the external host.
You can store the configuration data in Programmer Object File (.pof), .rbf, .hex, or .ttf. If you are using
configuration data in .rbf, .hex, or .ttf, send the LSB of each data byte first. For example, if the .rbf
contains the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000
1101-1000 0111-0111 1000-0000 0101-1111.
You can use the PFL IP core with a MAX II or MAX V device to read configuration data from the flash
memory device and configure the Arria 10 device.
For a PC host, connect the PC to the device using a download cable such as the Altera USB-Blaster USB
port, ByteBlaster II parallel port, EthernetBlaster, and EthernetBlaster II download cables.
The configuration data is shifted serially into the DATA0 pin of the device.
If you are using the Quartus Prime programmer and the CLKUSR pin is enabled, you do not need to
provide a clock source for the pin to initialize your device.
Related Information
• Arria 10 Hard Processor System Technical Reference Manual
Provides more information about the configuration via HPS.
• Parallel Flash Loader IP Core User Guide
Passive Serial Single-Device Configuration Using an External Host
To configure Arria 10 device, connect the device to an external host, as shown in the following figure.
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Passive Serial Single-Device Configuration Using an Altera Download...
Figure 7-9: Single Device PS Configuration Using an External Host
Memory
ADDR
DATA0
V CCPGM V CCPGM
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor
Connect the resistor to a power supply that provides an acceptable
input signal for the FPGA device. VCCPGM must be high enough to
meet the VIH specification of the I/O on the device and the external
host. Altera recommends powering up all the configuration system
I/Os with VCCPGM .
FPGA Device
10 kΩ
CONF_DONE
nSTATUS
nCE
GND
nCEO
DATA0
nCONFIG
DCLK
MSEL[2..0]
N.C.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
For more information, refer to
the MSEL pin settings.
Passive Serial Single-Device Configuration Using an Altera Download Cable
To configure Arria 10 device, connect the device to a download cable, as shown in the following figure.
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Passive Serial Multi-Device Configuration
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Figure 7-10: Single Device PS Configuration Using an Altera Download Cable
V CCPGM
V CCPGM
10 kΩ
V CCPGM
10 kΩ
V CCPGM
10 kΩ
V CCPGM
10 kΩ
FPGA Device
CONF_DONE
nSTATUS
10 kΩ
Connect the pull-up resistor to the
same supply voltage (VCCIO ) as the
USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II
cable.
MSEL[2..0]
nCE
GND
nCEO
N.C.
DCLK
DATA0
nCONFIG
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
V CCIO
GND
You only need the pull-up resistors on
DATA0 and DCLK if the download
cable is the only configuration scheme
used on your board. This ensures that
DATA0 and DCLK are not left floating
after configuration. For example, if you
are also using a MAX II device, MAX V
device, or microprocessor, you do not
need the pull-up resistors on DATA0
and DCLK.
For more information,
refer to the MSEL pin
settings.
Shield
GND
Passive Serial Multi-Device Configuration
You can configure multiple Arria 10 devices that are connected in a chain.
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Tie the following pins of all devices in the chain together:
•
•
•
•
•
nCONFIG
nSTATUS
DCLK
DATA0
CONF_DONE
By tying the CONF_DONE and nSTATUS pins together, the devices initialize and enter user mode at the
same time. If any device in the chain detects an error, configuration stops for the entire chain and you
must reconfigure all the devices. For example, if the first device in the chain flags an error on the
nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.
• If you are configuring the devices in the chain using the same configuration data, the devices must be
of the same package and density.
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Using Multiple Configuration Data
Using Multiple Configuration Data
To configure multiple Arria 10 devices in a chain using multiple configuration data, connect the devices
to the external host as shown in the following figure.
Note: By default, the nCEO pin is disabled in the Quartus Prime software. For the multi-device configura‐
tion chain, you must enable the nCEO pin in the Quartus Prime software. Otherwise, device
configuration could fail.
Figure 7-11: Multiple Device PS Configuration when Both Devices Receive Different Sets of
Configuration Data
Memory
ADDR
DATA0
Connect the resistor to a power supply that provides an acceptable input signal for
the FPGA device. VCCPGM must be high enough to meet the VIH specification of the
I/O on the device and the external host. Altera recommends powering up all the
configuration system I/Os with VCCPGM .
V CCPGM V CCPGM
10 kΩ
FPGA Device 1
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor
CONF_DONE
nSTATUS
nCE
nCEO
GND
DATA0
nCONFIG
MSEL[2..0]
DCLK
FPGA Device 2
CONF_DONE
nSTATUS
nCE
nCEO
N.C.
You can leave the nCEO pin
unconnected or use it as a
user I/O pin when it does not
feed another device’s nCE
pin.
DATA0
nCONFIG
DCLK
MSEL[2..0]
For more information, refer
to the MSEL pin settings.
After a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next
device in the chain. Configuration automatically begins for the second device in one clock cycle.
Using One Configuration Data
To configure multiple Arria 10 devices in a chain using one configuration data, connect the devices to an
external host, as shown in the following figure.
Note: By default, the nCEO pin is disabled in the Quartus Prime software. For the multi-device configura‐
tion chain, you must enable the nCEO pin in the Quartus Prime software. Otherwise, device
configuration could fail.
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Using PC Host and Download Cable
7-17
Figure 7-12: Multiple Device PS Configuration When Both Devices Receive the Same Set of
Configuration Data
Memory
ADDR
DATA0
Connect the resistor to a power supply that provides an acceptable input
signal for the FPGA device. VCCPGM must be high enough to meet the VIH
specification of the I/O on the device and the external host. Altera
recommends powering up all the configuration system I/Os with VCCPGM .
V CCPGM V CCPGM
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor
10 kΩ
FPGA Device 2
FPGA Device 1
CONF_DONE
nSTATUS
nCEO
nCE
CONF_DONE
nSTATUS
nCE
N.C.
GND
GND
DATA0
nCONFIG
MSEL[2..0]
DCLK
nCEO
N.C.
DATA0
nCONFIG
DCLK
MSEL[2..0]
For more information,
refer to the MSEL pin
settings.
You can leave the nCEO
pin unconnected or use it
as a user I/O pin.
The nCE pins of the devices in the chain are connected to GND, allowing configuration for these devices
to begin and end at the same time.
Using PC Host and Download Cable
To configure multiple Arria 10 devices, connect the devices to a download cable, as shown in the
following figure.
Note: By default, the nCEO pin is disabled in the Quartus Prime software. For the multi-device configura‐
tion chain, you must enable the nCEO pin in the Quartus Prime software. Otherwise, device
configuration could fail.
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Fast Passive Parallel Configuration
Figure 7-13: Multiple Device PS Configuration Using an Altera Download Cable
Connect the pull-up resistor to the
same supply voltage (VCCIO) as the
USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II
cable.
V CCPGM
V CCPGM
10 kΩ
10 kΩ
MSEL[2..0]
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
V CCPGM
GND
nCEO
nCE
10 kΩ
For more information, refer to
the MSEL pin settings.
10 kΩ
CONF_DONE
nSTATUS
DCLK
V CCPGM
You only need the pull-up resistors on
DATA0 and DCLK if the download cable
is the only configuration scheme used
on your board. This ensures that
DATA0 and DCLK are not left floating
after configuration. For example, if you
are also using a configuration device,
you do not need the pull-up resistors on
DATA0 and DCLK.
10 kΩ
FPGA Device 1
V CCPGM
V CCPGM
GND
DATA0
nCONFIG
GND
FPGA Device 2
MSEL[2..0]
CONF_DONE
nSTATUS
DCLK
nCEO
N.C.
nCE
DATA0
nCONFIG
When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next
device. Configuration automatically begins for the second device.
Fast Passive Parallel Configuration
Figure 7-14: High-Level Overview of Flash Programming for FPP Configuration Scheme
Quartus Prime
Software
Configuration Data
using JTAG
CPLD
FPGA
PFL
Common
Flash
Interface
Altera FPGA Not Used
for Flash Programming
CFI Flash
Memory
The FPP configuration scheme uses an external host, such as a microprocessor, MAX® II device, or
MAX V device. This scheme is the fastest method to configure Arria 10 devices. The FPP configuration
scheme supports 8-, 16-, and 32-bits data width.
You can use an external host to control the transfer of configuration data from an external storage such as
flash memory to the FPGA. The design that controls the configuration process resides in the external host.
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Fast Passive Parallel Single-Device Configuration
7-19
You can store the configuration data in Raw Binary File (.rbf), Hexadecimal (Intel-Format) File (.hex), or
Tabular Text File (.ttf) formats.
You can use the PFL IP core with a MAX II or MAX V device to read configuration data from the flash
memory device and configure the Arria 10 device.
Note: Two DCLK falling edges are required after the CONF_DONE pin goes high to begin the initialization of
the device for both uncompressed and compressed configuration data in an FPP configuration.
Related Information
• Altera Parallel Flash Loader IP Core User Guide
• Arria 10 Device Datasheet
Provides more information about the FPP configuration timing.
Fast Passive Parallel Single-Device Configuration
To configure an Arria 10 device, connect the device to an external host as shown in the following figure.
Note: If you are using the FPP x8 configuration mode, use DATA[7..0] pins. If you are using FPP x16
configuration mode, use DATA[15..0] pins. If you are using FPP x32 configuration mode, use
DATA[31..0] pins.
Figure 7-15: Single Device FPP Configuration Using an External Host
Connect the resistor to a supply that
provides an acceptable input signal
for the FPGA device. V CCPGM must be
high enough to meet the V IH
specification of the I/O on the device
and the external host. Altera
recommends powering up all
configuration system I/Os with VCCPGM .
Memory
ADDR DATA[7..0]
V CCPGM V CCPGM
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
10 kΩ
FPGA Device
MSEL[2..0]
CONF_DONE
nSTATUS
nCEO
nCE
GND
For more information, refer to
the MSEL pin settings.
N.C.
DATA[]
nCONFIG
DCLK
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
Fast Passive Parallel Multi-Device Configuration
You can configure multiple Arria 10 devices that are connected in a chain.
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Pin Connections and Guidelines
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Tie the following pins of all devices in the chain together:
•
•
•
•
•
nCONFIG
nSTATUS
DCLK
DATA[]
CONF_DONE
By tying the CONF_DONE and nSTATUS pins together, the devices initialize and enter user mode at the
same time. If any device in the chain detects an error, configuration stops for the entire chain and you
must reconfigure all the devices. For example, if the first device in the chain flags an error on the
nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.
• Ensure that DCLK and DATA[] are buffered for every fourth device to prevent signal integrity and clock
skew problems.
• All devices in the chain must use the same data width.
• If you are configuring the devices in the chain using the same configuration data, the devices must be
of the same package and density.
Using Multiple Configuration Data
To configure multiple Arria 10 devices in a chain using multiple configuration data, connect the devices
to an external host as shown in the following figure.
Note: If you are using the FPP x8 configuration mode, use DATA[7..0] pins. If you are using FPP x16
configuration mode, use DATA[15..0] pins. If you are using FPP x32 configuration mode, use
DATA[31..0] pins.
Note: By default, the nCEO pin is disabled in the Quartus Prime software. For multi-device configuration
chain, you must enable the nCEO pin in the Quartus Prime software. Otherwise, device configura‐
tion could fail.
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Using One Configuration Data
7-21
Figure 7-16: Multiple Device FPP Configuration Using an External Host When Both Devices Receive a
Different Set of Configuration Data
Connect the resistor to a supply
that provides an acceptable input
signal for the FPGA device.
V CCPGM must be high enough to
meet the V IH specification of the
I/O on the device and the external
host. Altera recommends
powering up all configuration
system I/Os with V CCPGM .
Memory
ADDR DATA[7..0]
For more information, refer to
the MSEL pin settings.
V CCPGM V CCPGM
10 kΩ
10 kΩ
FPGA Device Master
FPGA Device Slave
MSEL[2..0]
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
CONF_DONE
nSTATUS
nCE
nCEO
MSEL[2..0]
CONF_DONE
nSTATUS
nCE
GND
DATA[]
nCONFIG
DCLK
DATA[]
nCONFIG
DCLK
nCEO
N.C.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
Buffers
Connect the repeater buffers between the
FPGA master and slave device for DATA[]
and DCLK for every fourth device.
When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next
device in the chain. Configuration automatically begins for the second device in one clock cycle.
Using One Configuration Data
To configure multiple Arria 10 devices in a chain using one configuration data, connect the devices to an
external host as shown in the following figure.
Note: If you are using the FPP x8 configuration mode, use DATA[7..0] pins. If you are using FPP x16
configuration mode, use DATA[15..0] pins. If you are using FPP x32 configuration mode, use
DATA[31..0] pins.
Note: By default, the nCEO pin is disabled in the Quartus Prime software. For multi-device configuration
chain, you must enable the nCEO pin in the Quartus Prime software. Otherwise, device configura‐
tion could fail.
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JTAG Configuration
Figure 7-17: Multiple Device FPP Configuration Using an External Host When Both Devices Receive the
Same Data
Connect the resistor to a supply that
provides an acceptable input signal for the
FPGA device. VCCPGM must be high
enough to meet the V IH specification of
the I/O on the device and the external
host. Altera recommends powering up all
configuration system I/Os with V CCPGM .
Memory
For more information, refer to
the MSEL pin settings.
V CCPGM V CCPGM
ADDR DATA[7..0]
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
FPGA Device Slave
FPGA Device Master
MSEL[2..0]
10 kΩ
CONF_DONE
nSTATUS
nCE
GND
nCEO
MSEL[2..0]
CONF_DONE
nSTATUS
nCEO
nCE
N.C.
DATA[]
nCONFIG
DCLK
GND
DATA[]
nCONFIG
DCLK
N.C.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
Buffers
Connect the repeater buffers between the
FPGA master and slave device for DATA[]
and DCLK for every fourth device.
The nCE pins of the device in the chain are connected to GND, allowing configuration for these devices to
begin and end at the same time.
JTAG Configuration
In Arria 10 devices, JTAG instructions take precedence over other configuration schemes.
The Quartus Prime software generates an SRAM Object File (.sof) that you can use for JTAG configura‐
tion using a download cable in the Quartus Prime software programmer. Alternatively, you can use the
JRunner software with .rbf or a JAM™ Standard Test and Programming Language (STAPL) Format File
(.jam) or JAM Byte Code File (.jbc) with other third-party programmer tools.
Note: You cannot use the Arria 10 decompression or design security features if you are configuring your
Arria 10 device using JTAG-based configuration.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Arria 10 devices do not
affect JTAG boundary-scan or programming operations.
The USB-Blaster download cable can support VCCPGM supply at 1.5 V or 1.8 V. The USB-Blaster
download cable do not support a target supply voltage of 1.2 V.
Related Information
• Device Configuration Pins on page 7-33
Provides more information about JTAG configuration pins.
• JTAG Secure Mode on page 7-44
• Arria 10 Device Datasheet
Provides more information about the JTAG configuration timing.
• Programming Support for Jam STAPL Language
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JTAG Single-Device Configuration
•
•
•
•
USB-Blaster Download Cable User Guide
ByteBlaster II Download Cable User Guide
EthernetBlaster Communications Cable User Guide
EthernetBlaster II Communications Cable User Guide
JTAG Single-Device Configuration
To configure a single device in a JTAG chain, the programming software sets the other devices to the
bypass mode. A device in a bypass mode transfers the programming data from the TDI pin to the TDO pin
through a single bypass register. The configuration data is available on the TDO pin one clock cycle later.
The Quartus Prime software can use the CONF_DONE pin to verify the completion of the configuration
process through the JTAG port:
• CONF_DONE pin is low—indicates that configuration has failed.
• CONF_DONE pin is high—indicates that configuration was successful.
After the configuration data is transmitted serially using the JTAG TDI port, the TCK port is clocked an
additional 1,222 cycles to perform device initialization.
To configure Arria 10 device using a download cable, connect the device as shown in the following figure.
Figure 7-18: JTAG Configuration of a Single Device Using a Download Cable
The resistor value can vary from
1 kΩ to 10 kΩ. Perform signal
integrity analysis to select the
resistor value for your setup.
V CCPGM
10 kΩ
V CCPGM
10 kΩ
GND
You must connect
nCE to GND or drive
it low for successful
JTAG configuration.
V CCPGM
V CCPGM
FPGA Device
nCE
N.C. nCEO
nSTATUS
CONF_DONE
nCONFIG
MSEL[2..0]
DCLK
Connect the pull-up
resistor V CCPGM.
TCK
TDO
TMS
TDI
V CCPGM
Download Cable
10-Pin Male Header
(JTAG Mode) (Top View)
Pin 1
V CCPGM
TRST
If you only use the JTAG configuration, connect
nCONFIG to VCCPGM and MSEL[2..0] to GND. Pull
DCLK either high or low, whichever is convenient
on your board. If you are using JTAG in
conjunction with another configuration scheme,
connect MSEL[2..0], nCONFIG, and DCLK based
on the selected configuration scheme.
GND
1 kΩ
GND
GND
To configure Arria 10 device using a microprocessor, connect the device as shown in the following figure.
You can use JRunner as your software driver.
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JTAG Multi-Device Configuration
Figure 7-19: JTAG Configuration of a Single Device Using a Microprocessor
Memory
ADDR
V CCPGM V CCPGM
DATA
V CCPGM
TRST
TDI
TCK
TMS
TDO
Microprocessor
10 kΩ
FPGA Device
10 kΩ
nSTATUS
CONF_DONE
DCLK
nCONFIG
MSEL[2..0]
nCEO
nCE
N.C.
GND
The microprocessor must use
the same I/O standard as
V CCPGM to drive the JTAG pins.
Connect the pull-up resistor to a
supply that provides an
acceptable input signal for all
FPGA devices in the chain.
V CCPGM must be high enough to
meet the VIH specification of the
I/O on the device.
If you only use the JTAG configuration, connect
nCONFIG to VCCPGM and MSEL[2..0] to GND. Pull
DCLK high or low. If you are using JTAG in
conjunction with another configuration scheme, set
the MSEL[2..0] pins and tie nCONFIG and DCLK
based on the selected configuration scheme.
Connect nCE to GND or
drive it low.
Related Information
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
JTAG Multi-Device Configuration
You can configure multiple devices in a JTAG chain.
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Isolate the CONF_DONE and nSTATUS pins to allow each device to enter user mode independently.
• One JTAG-compatible header is connected to several devices in a JTAG chain. The number of devices
in the chain is limited only by the drive capability of the download cable.
• If you have four or more devices in a JTAG chain, buffer the TCK, TDI, and TMS pins with an on-board
buffer. You can also connect other Altera devices with JTAG support to the chain.
• JTAG-chain device programming is ideal when the system contains multiple devices or when testing
your system using the JTAG boundary-scan testing (BST) circuitry.
Using a Download Cable
The following figure shows a multi-device JTAG configuration.
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Configuration Details
Figure 7-20: JTAG Configuration of Multiple Devices Using a Download Cable
Connect the pull-up
resistor V CCPGM .
Download Cable
10-Pin Male Header
(JTAG Mode)
Pin 1
If you only use the JTAG configuration, connect nCONFIG to V CCPGM and MSEL[2..0]
to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are
using JTAG in conjunction with another configuration scheme, connect MSEL[2..0],
nCONFIG, and DCLK based on the selected configuration scheme.
FPGA Device
V CCPGM
V CCPGM
10 kΩ
10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[2..0]
nCE
V CCPGM
V CCPGM
GND
V CCPGM
TDI
TMS
TDO
TCK
FPGA Device
V CCPGM
10 kΩ
10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[2..0]
nCE
GND
TDI
TMS
TDO
TCK
FPGA Device
V CCPGM V CCPGM
V CCPGM
10 kΩ
10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[2..0]
nCE
GND
TDI
TMS
TCK
TDO
1 kΩ The resistor value can vary from 1 kΩ to 10
kΩ. Perform signal integrity analysis to
select the resistor value for your setup.
Related Information
AN 656: Combining Multiple Configuration Schemes
Provides more information about combining JTAG configuration with other configuration schemes.
Configuration Details
This section describes the MSEL pin settings, configuration sequence, device configuration pins, configura‐
tion pin options, and configuration data compression.
MSEL Pin Settings
To select a configuration scheme, hardwire the MSEL pins to VCCPGM or GND without pull-up or
pull-down resistors.
Note:
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CLKUSR
Table 7-3: MSEL Pin Settings for Each Configuration Scheme of Arria 10 Devices
• Do not drive the MSEL pins with a microprocessor or another device.
• Use PS or FPP MSEL pin setting for configuration via HPS.
Configuration Scheme
VCCPGM (V)
JTAG-based configuration
—
AS (x1 and x4)
1.8
PS and
FPP (x8, x16, and x32)
1.2/1.5/1.8
Power-On Reset
(POR) Delay
—
Valid MSEL[2..0]
Use any valid MSEL pin settings
below
Fast
010
Standard
011
Fast
000
Standard
001
Note: You must also select the configuration scheme in the Configuration page of the Device and Pin
Options dialog box in the Quartus Prime software. Based on your selection, the option bit in the
programming file is set accordingly.
Related Information
• Arria 10 Hard Processor System Technical Reference Manual
Provides more information about the configuration via HPS.
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides more information about JTAG pins voltage-level connection.
CLKUSR
You can use CLKUSR pin as the clock source for Arria 10 device configuration and initialization. CLKUSR
pin can also be used for configuration and transceiver calibration simultaneously.
For transceiver calibration, CLKUSR must be a free-running clock running between 100 MHz to 125 MHz
at power-up depending on the device’s configuration scheme as shown in the following table. Transceiver
calibration starts utilizing the CLKUSR during device configuration and may continue to use it even when
the device enters user mode.
Table 7-4: Available Configuration Clock Source and Transceiver Calibration CLKUSR Frequency for
Arria 10 Devices
Configuration mode
AS
Supported Clock Source for
Device Configuration
Internal Oscillator, CLKUSR
Internal Oscillator, CLKUSR
DCLK only
DCLK
PS
FPP (x8, x16,
x32)
Altera Corporation
Supported Clock Source for
Device Initialization
Internal Oscillator, CLKUSR,
Supported CLKUSR
Frequency for Transceiver
Calibration
100 MHz
100 to 125 MHz
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Configuration Sequence
7-27
Related Information
Arria 10 Device Family Pin Connection Guidelines
Provides more information about CLKUSR pin.
Configuration Sequence
Describes the configuration sequence and each configuration stage.
Figure 7-21: Configuration Sequence for Arria 10 Devices
Power Up
• nSTATUS and CONF_DONE
driven low
• All I/Os pins are tied to an
internal weak pull-up
• Clears configuration RAM bits
Power supplies including VCCPGM reach
recommended operating voltage
Reset
• nSTATUS and CONF_DONE
remain low
• All I/Os pins are tied to an
internal weak pull-up
• Samples MSEL pins
nSTATUS and nCONFIG released high
CONF_DONE pulled low
Configuration Error Handling
• nSTATUS pulled low
• CONF_DONE remains low
• Restarts configuration if option
enabled
Configuration
Writes configuration data to
FPGA
CONF_DONE released high
Initialization
• Initializes internal logic and
registers
• Enables I/O buffers
INIT_DONE released high
(if option enabled)
User Mode
Executes your design
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Power Up
You can initiate reconfiguration by pulling the nCONFIG pin low to at least the minimum tCFG low-pulse
width except for configuration using the partial reconfiguration operation. When this pin is pulled low,
the nSTATUS and CONF_DONE pins are pulled low and all I/O pins are tied to an internal weak pull-up.
Power Up
Power up all the power supplies that are monitored by the POR circuitry. All power supplies, including
VCCPGM, must ramp up from 0 V to the recommended operating voltage level within the ramp-up time
specification. Otherwise, hold the nCONFIG pin low until all the power supplies reach the recommended
voltage level.
VCCPGM Pin
The configuration input buffers do not have to share power lines with the regular I/O buffers in Arria 10
devices. Connect VCCPGM to 1.8 V.
The operating voltage for the configuration input pin is independent of the I/O banks power supply,
VCCIO, during configuration. Therefore, Arria 10 devices do not require configuration voltage constraints
on VCCIO.
Altera recommends connecting the I/O banks power supply, VCCIO, of the dual-purpose configuration
pins for FPP x8, x16, and x32 to VCCPGM.
Related Information
• Arria 10 Device Datasheet
Provides more information about the ramp-up time specifications.
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides more information about configuration pin connections.
• Device Configuration Pins on page 7-33
Provides more information about configuration pins.
Reset
POR delay is the time frame between the time when all the power supplies monitored by the POR
circuitry reach the recommended operating voltage and when nSTATUS is released high and the Arria 10
device is ready to begin configuration.
Set the POR delay using the MSEL pins.
The user I/O pins are tied to an internal weak pull-up until the device is configured.
Related Information
• MSEL Pin Settings on page 7-25
• Arria 10 Device Datasheet
Provides more information about the POR delay specification.
Configuration
For more information about the DATA[] pins for each configuration scheme, refer to the appropriate
configuration scheme.
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Configuration Error Detection
7-29
Configuration Error Detection
When the Quartus Prime software generates the configuration bitstream, the software also computes a 32bit CRC value for each CRAM frame. A configuration bitstream contains one CRC value for each data
frames. The length of the data frame can vary for each device.
As each data frame is loaded into the FPGA during configuration, the precomputed CRC value shifts into
the CRC circuitry. At the same time, the CRC engine in the FPGA computes the CRC value for the data
frame and compares it against the precomputed CRC value. If both CRC values do not match, the
nSTATUS pin is set to low to indicate a configuration error.
Configuration Error Handling
To restart configuration automatically, turn on the Auto-restart configuration after error option in the
General page of the Device and Pin Options dialog box in the Quartus Prime software.
If you do not turn on this option, you can monitor the nSTATUS pin to detect errors. To restart configura‐
tion, pull the nCONFIG pin low for at least the duration of tCFG.
Related Information
Arria 10 Device Datasheet
Provides more information about t STATUS and t CFG timing parameters.
Initialization
The initialization clock source is from the internal oscillator, CLKUSR pin, or DCLK pin. By default, the
internal oscillator is the clock source for initialization. If you use the internal oscillator, the Arria 10
device will be provided with enough clock cycles for proper initialization.
Note: If you use the optional CLKUSR pin as the initialization clock source and the nCONFIG pin is pulled
low to restart configuration during device initialization, ensure that the CLKUSR or DCLK pin
continues toggling until the nSTATUS pin goes low and then goes high again.
The CLKUSR pin provides you with the flexibility to synchronize initialization of multiple devices or to
delay initialization. Supplying a clock on the CLKUSR pin during initialization does not affect configura‐
tion. After the CONF_DONE pin goes high, the CLKUSR or DCLK pin is enabled after the time specified by
tCD2CU. When this time period elapses, Arria 10 devices require a minimum number of clock cycles as
specified by Tinit to initialize properly and enter user mode as specified by the tCD2UMC parameter.
Related Information
Arria 10 Device Datasheet
Provides more information about t CD2CU , t init , and t CD2UMC timing parameters, and initialization clock
source.
User Mode
You can enable the optional INIT_DONE pin to monitor the initialization stage. After the INIT_DONE pin is
pulled high, initialization completes and your design starts executing. The user I/O pins will then function
as specified by your design.
Configuration Timing Waveforms
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FPP Configuration Timing
FPP Configuration Timing
Figure 7-22: FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Reconfiguration triggered
t CF2CK
tCFG
nCONFIG
t CF2ST0
tCF2ST1
nSTATUS (1)
tST2CK
DCLK
DATA[31..0] (4)
tSTATUS
(5)
tCLK
CONF_DONE (2)
tCH tCL
tCF2CD
(3)
(7)
tDH
Word 0 Word 1 Word 2 Word 3
User Mode
Word n-1
Word 0 Word 1
tDSU
User I/O
High-Z
High-Z
User Mode
INIT_DONE (6)
CONFIGURATION
Power-up & Reset
STATE
tCD2UM
Configuration
Initialization
User Mode
Reset
Configuration
(1) After power-up, the device holds nSTATUS low for the time of the POR delay.
(2) After power-up, before and during configuration, CONF_DONE is low.
(3) Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required.
(4) For FPP ×16, use DATA[15..0]. For FPP ×8, use DATA[7..0]. DATA[31..0] are available as a user I/O pin after configuration. The state of this pin depends on
the dual-purpose pin settings.
(5) To ensure a successful configuration, send the entire configuration data to the device. CONF_DONE is released high when the device receives all the
configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode.
(6) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
(7) Do not toggle the DCLK high before nSTATUS is pulled high.
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FPP Configuration Timing
Figure 7-23: FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Reconfiguration triggered
t CF2CK
tCFG
nCONFIG
t CF2ST0
tCF2ST1
nSTATUS (1)
CONF_DONE (2)
DCLK (4)
DATA[31..0] (6)
(6)
tCLK
tST2CK
(8)
tSTATUS
tCH tCL
1
tCF2CD
r
2
(5)
1
2
r
r
(3)
1
tDSU
User I/O
Word 0
Word 2
User Mode
Word (n-1)
Word 0
tDH
High-Z
High-Z
User Mode
INIT_DONE (7)
CONFIGURATION
Power-up & Reset
STATE
tCD2UM
Configuration
Initialization
User Mode
Reset
Configuration
(1) After power-up, the device holds nSTATUS low for the time as specified by the POR delay.
(2) After power-up, before and during configuration, CONF_DONE is low.
(3) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(4) “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable settings.
(5) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0] pins prior to sending the first DCLK rising edge.
(6) To ensure a successful configuration, send the entire configuration data to the device. CONF_DONE is released high after the device receives all the configuration data successfully.
After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode.
(7) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
(8) Do not toggle the DCLK high before nSTATUS is pulled high.
Related Information
DCLK-to-DATA[] Ratio (r) for FPP Configuration
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AS Configuration Timing
AS Configuration Timing
Figure 7-24: AS Configuration Timing Waveform
Reconfiguration
triggered
tCF2ST1
tCF2ST1
nCONFIG
nSTATUS
CONF_DONE
DCLK
tCO
AS_DATA0/ASDO
tDH
Read Address
tSU
AS_DATA1 (1)
User I/O
bit 0
bit 1
bit(n-2) bit(n-1)
User Mode
High-Z
High-Z
tSU(2)
INIT_DONE (3)
CONFIGURATION
Power-up & Reset
STATE
Configuration
Initialization
User Mode
Reset Configuration
(1) If you are using AS ×4 mode, this signal represents the AS_DATA[3..0] and EPCQ-L sends in 4-bits of data for each DCLK cycle.
(2) The initialization clock can be from internal oscillator or CLKUSR pin.
(3) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
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PS Configuration Timing
7-33
PS Configuration Timing
Figure 7-25: PS Configuration Timing Waveform
The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Reconfiguration triggered
t CF2CK
tCFG
nCONFIG
tCF2ST0
tCF2ST1
nSTATUS (1)
CONF_DONE (2)
tST2CK
tSTATUS
(5)
tCLK
tCH tCL
tCF2CD
(3)
(7)
DCLK
tDH
DATA0
Bit 1 Bit 2
Bit 0
Bit 3
(4)
Bit (n-1)
Bit 0
tDSU
User I/O
High-Z
High-Z
User Mode
INIT_DONE (6)
CONFIGURATION
Power-up & Reset
STATE
tCD2UM
Configuration
Initialization
User Mode
Reset
Configuration
(1) After power-up, the device holds nSTATUS low for the time of the POR delay.
(2) After power-up, before and during configuration, CONF_DONE is low.
(3) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(4) DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins Option.
(5) To ensure a successful configuration, send the entire configuration data to the device. CONF_DONE is released high after the device receives all the
configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode.
(6) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
(7) Do not toggle the DCLK high before nSTATUS is pulled high.
Device Configuration Pins
Configuration Pins Summary
The following table lists the Arria 10 configuration pins and their power supply.
Note: The TDI, TMS, TCK, TDO, and TRST pins are powered by VCCPGM.
Note: The CLKUSR, DEV_OE, DEV_CLRn, DATA[31..1], and DATA0 pins are powered by VCCPGM during
configuration and by VCCIO of the bank in which the pin resides if you use it as a user I/O pin.
Table 7-5: Configuration Pin Summary for Arria 10 Devices
Configuration Pin
Configuration
Scheme
Input/Output
User Mode
Powered By
TDI
JTAG
Input
—
VCCPGM
TMS
JTAG
Input
—
VCCPGM
TCK
JTAG
Input
—
VCCPGM
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Device Configuration Pins
Configuration Pin
Configuration
Scheme
Input/Output
User Mode
Powered By
TDO
JTAG
Output
—
VCCPGM
TRST
JTAG
Input
—
VCCPGM
All
schemes
Input
I/O
VCCPGM/VCCIO (25)
Optional,
all
schemes
Output
I/O
VCCPGM /Pull-up
All
schemes
Bidirectional
—
VCCPGM/Pull-up
FPP and
PS
Input
—
VCCPGM
AS
Output
—
VCCPGM
Optional,
all
schemes
Input
I/O
VCCPGM/VCCIO (25)
Optional,
all
schemes
Input
I/O
VCCPGM/VCCIO (25)
Optional,
all
schemes
Output
I/O
Pull-up
All
schemes
Input
—
VCCPGM
All
schemes
Bidirectional
—
VCCPGM/Pull-up
All
schemes
Input
—
VCCPGM
All
schemes
Output
I/O
Pull-up
All
schemes
Input
—
VCCPGM
FPP
Input
I/O
VCCPGM/VCCIO (25)
FPP and
PS
Input
I/O
VCCPGM/VCCIO (25)
AS
Output
—
VCCPGM
All
schemes
Input
—
VCC
AS_DATA[3..1]
AS
Bidirectional
—
VCCPGM
AS_DATA0/ASDO
AS
Bidirectional
—
VCCPGM
CLKUSR
CRC_ERROR
CONF_DONE
DCLK
DEV_OE
DEV_CLRn
INIT_DONE
MSEL[2..0]
nSTATUS
nCE
nCEO
nCONFIG
DATA[31..1]
DATA0
nCSO[2..0]
nIO_PULLUP
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Configuration Pin Options in the Quartus Prime Software
Configuration Pin
PR_REQUEST
PR_READY
PR_ERROR
PR_DONE
Configuration
Scheme
Input/Output
User Mode
7-35
Powered By
Partial
Input
Reconfigur
ation
I/O
VCCPGM/VCCIO (25)
Partial
Output
Reconfigur
ation
I/O
VCCPGM/VCCIO (25)
Partial
Output
Reconfigur
ation
I/O
VCCPGM/VCCIO (25)
Partial
Output
Reconfigur
ation
I/O
VCCPGM/VCCIO (25)
Related Information
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides more information about each configuration pin.
Configuration Pin Options in the Quartus Prime Software
The following table lists the dual-purpose configuration pins available in the Device and Pin Options
dialog box in the Quartus Prime software.
Table 7-6: Configuration Pin Options
Configuration Pin
Category Page
Option
CLKUSR
General
Enable user-supplied start-up clock
(CLKUSR)
DEV_CLRn
General
Enable device-wide reset
(DEV_CLRn)
DEV_OE
General
Enable device-wide output enable
(DEV_OE)
INIT_DONE
General
Enable INIT_DONE output
nCEO
General
Enable nCEO pin
Enable Error Detection CRC_ERROR
pin
CRC_ERROR
Error Detection CRC
Enable open drain on CRC_ERROR
pin
Enable internal scrubbing
(25)
This pin is powered by VCCPGM before and during configuration and is powered by VCCIO if used as a
user I/O pin during user mode.
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Configuration Data Compression
Configuration Pin
Category Page
Option
PR_REQUEST
PR_READY
PR_ERROR
General
Enable PR pin
PR_DONE
Related Information
Reviewing Printed Circuit Board Schematics with the Quartus Prime Software
Provides more information about the device and pin options dialog box setting.
Configuration Data Compression
Arria 10 devices can receive compressed configuration bitstream and decompress the data in real-time
during configuration. Preliminary data indicates that compression typically reduces the configuration file
size by 30% to 55% depending on the design.
Decompression is supported in all configuration schemes except the JTAG configuration scheme.
You can enable compression before or after design compilation.
Note: You cannot enable encryption and compression at the same time for all configuration scheme.
Enabling Compression Before Design Compilation
To enable compression before design compilation, follow these steps:
1. On the Assignment Menu, click Device.
2. Select your Arria 10 device and then click Device and Pin Options.
3. In the Device and Pin Options window, select Configuration under the Category list and turn on
Generate compressed bitstreams.
Enabling Compression After Design Compilation
To enable compression after design compilation, follow these steps:
1. On the File menu, click Convert Programming Files.
2. Select the programming file type (.pof, .sof, .hex, .hexout, .rbf, or .ttf). For POF output files, select a
configuration device.
3. Under the Input files to convert list, select SOF Data.
4. Click Add File and select an Arria 10 device .sof.
5. Select the name of the file you added to the SOF Data area and click Properties.
6. Turn on the Compression check box.
Using Compression in Multi-Device Configuration
The following figure shows a chain of two Arria 10 devices. Compression is only enabled for the first
device.
This setup is supported by the AS or PS multi-device configuration only.
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Remote System Upgrades Using Active Serial Mode
7-37
Figure 7-26: Compressed and Uncompressed Serial Configuration Data in the Same Configuration File
Serial Configuration Data
Uncompressed
Compressed
Configuration
Configuration
Data
Data
Decompression
Controller
FPGA
FPGA
Device 1
Device 2
nCE
nCEO
nCE
nCEO
EPCQ-L or
External Host
N.C.
GND
For the FPP configuration scheme, a combination of compressed and uncompressed configuration in the
same multi-device configuration chain is not allowed because of the difference on the DCLK-to-DATA[]
ratio.
Remote System Upgrades Using Active Serial Mode
Arria 10 devices contain dedicated remote system upgrade circuitry. You can use this feature to upgrade
your system from a remote location.
Figure 7-27: Arria 10 Remote System Upgrade Block Diagram
1
Development
Location
Data
Data
Data
FPGA
Remote System
Upgrade Circuitry
2
Configuration
Memory
FPGA Configuration
3
You can design your system to manage remote upgrades of the application configuration images in the
configuration device. The following list is the sequence of the remote system upgrade:
1. The logic (embedded processor or user logic) in the Arria 10 device receives a configuration image
from a remote location. You can connect the device to the remote source using communication
protocols such as TCP/IP, PCI, user datagram protocol (UDP), UART, or a proprietary interface.
2. The logic stores the configuration image in non-volatile configuration memory.
3. The logic starts reconfiguration cycle using the newly received configuration image.
When an error occurs, the circuitry detects the error, reverts to a safe configuration image, and provides
error status to your design.
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Configuration Images
Configuration Images
Arria 10 devices offer a new remote system upgrade feature which provides direct-to-application and
application-to-application updates. When the Arria 10 device is powered up in the remote update
programming mode, the Arria 10 device loads the factory or application configuration image as indicated
by the start address pointer at 32'd0 address of the EPCQ-L device.
Each Arria 10 device in your system requires one factory image. The factory image is a user-defined
configuration image that contains logic to perform the following:
• Processes errors based on the status provided by the dedicated remote system upgrade circuitry.
• Communicates with the remote host, receives new application images, and stores the images in the
local non-volatile memory device.
• Determines the application image to load into the Arria 10 device.
• Enables or disables the user watchdog timer and loads its time-out value.
• Instructs the dedicated remote system upgrade circuitry to start a reconfiguration cycle.
You can also create one or more application images for the device. An application image contains selected
functionalities to be implemented in the target device.
Store the images at the following locations in the EPCQ-L devices:
• Factory configuration image—PGM[31..0] = 32'h00000020 start address on the EPCQ-L device.
• Application configuration image—any sector boundary. Altera recommends that you store only one
image at one sector boundary.
• Start address (0x00 to 0x1F)—storing the 32-bit address pointer to load the application configuration
image upon power up.
Figure 7-28: Start Address and Factory Address Location
The following diagram illustrates factory, user data, application 1, and application 2 sections. Each section
starts at a new sector boundary.
Application 2
Application 1
User Data
Factory
Factory Address 32’d32
Start Address 32’d0
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Programmed by
Quartus Prime Software
Address Pointer
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Configuration Sequence in the Remote Update Mode
7-39
Configuration Sequence in the Remote Update Mode
Figure 7-29: Transitions Between Factory and Application Configurations in Remote Update Mode
Reconfiguration
or Start Address = 0
Read Start Address
from Flash
Factory Configuration
Load Factory POF
Reconfiguration
or Start Address = 0
After POR or
nCONFIG Assertion
Error Count <= 3
Application Configuration
Error Count > 3
Reconfiguration &
Start Address = 32
Enter Factory
User Mode
Reconfiguration &
Start Address > 0 and not 32
Load Application
Number POF
No Error
Watchdog
Timeout
Enter Application
User Mode
Reconfiguration &
Start Address > 0
and not 32
Reconfiguration &
Start Address = 32
Upon power up or reconfiguration triggered using nCONFIG, the AS controller reads the start address from
the EPCQ-L device and loads the initial configuration image, either the factory or application configura‐
tion image. If the initial image is an application configuration image and an error occurs, the controller
tries to load the same initial application configuration image for three times before loading the factory
configuration image. If the initial application configuration image encounters a user watchdog timeout
error, the controller loads the factory configuration image. You can load a new application configuration
image during factory user mode or application user mode. If an error is encountered, the controller loads
the factory configuration image.
Related Information
Remote System Upgrade State Machine on page 7-42
A detailed description of the configuration sequence in the remote update mode.
Remote System Upgrade Circuitry
The remote system upgrade circuitry contains the remote system upgrade registers, watchdog timer, and a
state machine that controls these components.
Note: If you are using the Altera Remote Update IP core, the IP core controls the RU_DOUT,
RU_CTL[1:0], , RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals internally to perform all
the related remote system upgrade operations.
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Enabling Remote System Upgrade Circuitry
Figure 7-30: Remote System Upgrade Circuitry
Internal Oscillator
Status Register (SR)
[4..0]
Control Register
[45..0]
Logic Array
Update Register
[45..0]
update
dout
Bit [4..0]
Shift Register
din
dout
capture
Bit [45..0]
Remote
System
Upgrade
State
Machine
din
capture
User
Timeout Watchdog
Timer
clkout capture update
Logic Array clkin
RU_DOUT
RU_CTL[1:0]
RU_CLK
RU_DIN
RU_nCONFIG
RU_nRSTIMER
Logic Array
Related Information
Arria 10 Device Datasheet
Provides more information about remote system upgrade circuitry timing specifications.
Enabling Remote System Upgrade Circuitry
To enable the remote system upgrade feature, select Active Serial or Configuration Device from the
Configuration scheme list in the Configuration page of the Device and Pin Options dialog box in the
Quartus Prime software.
Altera-provided Altera Remote Update IP core provides a memory-like interface to the remote system
upgrade circuitry and handles the shift register read and write protocol in the Arria 10 device logic.
Related Information
Altera Remote Update IP Core User Guide
Remote System Upgrade Registers
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Control Register
7-41
Table 7-7: Remote System Upgrade Registers
Register
Description
Shift
This register is accessible by the core logic and allows the update, status, and
control registers to be written and sampled by user logic.
Control
This register contains the current page address, watchdog timer settings, and
one bit specifying the current configuration image—factory configuration or
application configuration image. This register is used by the AS controller to
load the configuration image from the EPCQ-L device during remote system
upgrade.
Update
This register contains similar data as the control register, but this register is
updated by the factory configuration or application configuration image by
shifting data into the shift register, followed by an update. The soft IP core of
the remote system upgrade updates this register with the values to be used in
the control register during the next reconfiguration cycle.
Status
This register is written by the remote update block during every reconfigura‐
tion cycle to record the trigger of a reconfiguration. This information is used
by the soft IP core of the remote system upgrade to determine the appropriate
action following a reconfiguration cycle.
Related Information
• Control Register on page 7-41
• Status Register on page 7-42
Control Register
Table 7-8: Control Register Bits
Bit
0
Name
AnF
Reset
Value(26)
1'b0
Description
Application not Factory bit. Indicates the
configuration image type currently loaded in
the device; 0 for factory image and 1 for
application image. When this bit is 1, the
access to the control register is limited to read
only and the watchdog timer is enabled.
Factory configuration design must set this bit
to 1 before triggering reconfiguration using
an application configuration image.
(26)
This is the default value after the device exits POR and during reconfiguration back to the factory configura‐
tion image.
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Status Register
Bit
Name
Reset
Value(26)
Description
32'h000000 AS configuration start address.
00
1..32
PGM[0..31]
33
Wd_en
1'b0
User watchdog timer enable bit. Set this bit to
1 to enable the watchdog timer.
34..45
Wd_timer[11..0]
12'h000
User watchdog time-out value.
Status Register
Table 7-9: Status Register Bits
Bit
Name
Reset
Value(27)
Description
0
CRC
1'b0
When set to 1, indicates CRC error during applica‐
tion configuration.
1
nSTATUS
1'b0
When set to 1, indicates that nSTATUS is asserted by
an external device due to error.
2
Core_nCONFIG
1'b0
When set to 1, indicates that reconfiguration has
been triggered by the logic array of the device.
3
nCONFIG
1'b0
When set to 1, indicates that nCONFIG is asserted.
4
Wd
1'b0
When set to 1, indicates that the user watchdog
time-out.
Remote System Upgrade State Machine
The operation of the remote system upgrade state machine is as follows:
1. After power-up, the remote system upgrade registers are reset to 0 and the factory or application
configuration image is loaded based on the start address stored at 0x00 to 0x1F in the EPCQ-L device.
2. In factory configuration image, the user logic sets the AnF bit to 1 and the start address of the applica‐
tion image to be loaded. The user logic also writes the watchdog timer settings.
3. When the configuration reset (RU_CONFIG) goes low, the state machine updates the control register
with the contents of the update register, and triggers reconfiguration using the application configura‐
tion image.
4. If error occurs, the state machine falls back to the factory image. The control and update registers are
reset to 0, and the status register is updated with the error information.
5. After successful reconfiguration, the system stays in the application configuration.
User Watchdog Timer
(26)
(27)
This is the default value after the device exits POR and during reconfiguration back to the factory configura‐
tion image.
After the device exits POR and power-up, the status register content is 5'b00000.
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Design Security
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The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely.
You can use the timer to detect functional errors when an application configuration is successfully loaded
into the device. The timer is automatically disabled in the factory configuration; enabled in the application
configuration.
Note: If you do not want this feature in the application configuration, you need to turn off this feature by
setting the Wd_en bit to 1'b0 in the update register during factory configuration user mode
operation. You cannot disable this feature in the application configuration.
The counter is 29 bits wide and has a maximum count value of 229. When specifying the user watchdog
timer value, specify only the most significant 12 bits. The granularity of the timer setting is 217 cycles. The
cycle time is based on the frequency of the user watchdog timer internal oscillator.
The timer begins counting as soon as the application configuration enters user mode. When the timer
expires, the remote system upgrade circuitry generates a time-out signal, updates the status register, and
triggers the loading of the factory configuration image. To reset the time, assert RU_nRSTIMER.
Related Information
Arria 10 Device Datasheet
Provides more information about the operating range of the user watchdog internal oscillator's frequency.
Design Security
The Arria 10 design security feature supports the following capabilities:
• Enhanced built-in advanced encryption standard (AES) decryption block to support 256-bit key
industry-standard design security algorithm (FIPS-197 Certified)
• Volatile and non-volatile key programming support
• Secure operation mode for both volatile and non-volatile key through tamper protection bit setting
• Limited accessible JTAG instruction during power-up in the secure mode
• Supports board-level testing
• Supports off-board key programming for non-volatile key
• Available in all configuration schemes except JTAG
• Supports remote system upgrades feature
• Supports POF authentication and protection against Side-Channel Attack
• Disables external JTAG and HPS JTAG through a fuse bit or option bits
• Disables all JTAG instructions from power-up until the device is initialized
The Arria 10 design security feature provides the following security protection for your designs:
• Security against copying—the security key is securely stored in the Arria 10 device and cannot be read
out through any interface. In addition, as configuration file read-back is not supported in Arria 10
devices, your design information cannot be copied.
• Security against reverse engineering—reverse engineering from an encrypted configuration file is very
difficult and time consuming because the Arria 10 configuration file formats are proprietary and the
file contains millions of bits that require specific decryption.
• Security against tampering—After you set the tamper protection bit, the Arria 10 device can only
accept configuration files encrypted with the same key. Additionally, programming through the JTAG
interface and configuration interface is blocked.
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JTAG Secure Mode
When you use design security with Arria 10 devices in an FPP configuration scheme, it requires a
different DCLK-to-DATA[] ratio.
Note: You cannot enable encryption and compression at the same time for all configuration scheme.
JTAG Secure Mode
When you issue the EX_JTAG_SECURE instruction, Arria 10 devices are in the JTAG secure mode. During
this mode, many JTAG instructions are disabled. Arria 10 devices only allow mandatory JTAG 1149.1
instructions to be exercised. These JTAG instructions are SAMPLE/PRELOAD, BYPASS, EXTEST, and optional
instructions such as IDCODE and SHIFT_EDERROR_REG.
Note: After you issue the EX_JTAG_SECURE instruction, the Arria 10 device cannot be unlocked.
Related Information
Supported JTAG Instruction on page 9-2
Secure Mode
When you enable the tamper-protection bit, Arria 10 devices are in the secure mode after power-up.
During this mode, some JTAG instructions are disabled.
Security Key Types
Arria 10 devices offer two types of keys—volatile and non-volatile. The following table lists the differences
between the volatile key and non-volatile keys.
Table 7-10: Security Key Types
Key Types
Key Programmability Power Supply for Key
Storage
Programming Method
Volatile
• Reprogrammable Required external
battery, VCCBAT (28)
• Erasable
On-board
Non-volatile
One-time
programming
On-board and in-socket
programming (29)
Does not require an
external battery
Both non-volatile and volatile key programming offers protection from reverse engineering and copying.
If you set the tamper-protection bit, the design is also protected from tampering.
You can perform key programming through the JTAG pins interface. Ensure that the nSTATUS pin is
released high before any key-programming attempts.
Note: To clear the volatile key, issue the KEY_CLR_VREG JTAG instruction. To verify the volatile key has
been cleared, issue the KEY_VERIFY JTAG instruction.
(28)
(29)
VCCBAT is a dedicated power supply for volatile key storage. VCCBAT continuously supplies power to the
volatile register regardless of the on-chip supply condition.
Third-party vendors offer in-socket programming.
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Security Modes
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Related Information
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides more information about the V CCBAT pin connection recommendations.
• Arria 10 Device Datasheet
Provides more information about battery specifications.
• Supported JTAG Instruction on page 9-2
Security Modes
Table 7-11: Supported Security Modes
Security Mode
Tamper
Protection Bit
Setting
Device Accepts
Unencrypted File
Device Accepts
Encrypted File
Security Level
No key
—
Yes
No
—
Volatile Key
—
Yes
Yes
Secure
Volatile Key with
Tamper Protection Bit
Set
Set
No
Yes
Secure with tamper
resistant
Non-volatile Key
—
Yes
Yes
Secure
Non-volatile Key with
Tamper Protection Bit
Set
Set
No
Yes
Secure with tamper
resistant
The use of unencrypted configuration bitstream in the volatile key and non-volatile key security modes is
supported for board-level testing only.
Note: For the volatile key with tamper protection bit set security mode, Arria 10 devices do not accept the
encrypted configuration file if the volatile key is erased. If the volatile key is erased and you want to
reprogram the key, you must use the volatile key security mode.
Enabling the tamper protection bit disables the test mode in Arria 10 devices and disables programming
through the JTAG interface. This process is irreversible and prevents Altera from carrying out failure
analysis.
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Document Revision History
Figure 7-31: Design Security Implementation Steps
AES Key
Programming File
Step 3
FPGA Device
Key Storage
Step 1
AES Decryption
256-bit User-Defined Quartus Prime Software
Key
AES Encryptor
Step 4
Step 1
Encrypted
Configuration
File
Step 2
Memory or
Configuration
Device
To carry out secure configuration, follow these steps:
1. The Quartus Prime software generates the design security key programming file and encrypts the
configuration data using the user-defined 256-bit security key.
2. Store the encrypted configuration file in the external memory.
3. Program the AES key programming file into the Arria 10 device through a JTAG interface.
4. Configure the Arria 10 device. At the system power-up, the external memory device sends the
encrypted configuration file to the Arria 10 device.
Document Revision History
Date
December
2015
Altera Corporation
Version
2015.12.14
Changes
• Updated CLKUSR information.
• Moved CLKUSR subsection from Active Serial Configuration to
Configuration Details.
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Document Revision History
Date
Version
7-47
Changes
November
2015
2015.11.02
• Updated the term configuration mode to configuration scheme for
consistency.
• Added link at MSEL pin setting to Arria 10 Hard Processor System
Technical Reference Manual.
• Combined PS and FPP row in MSEL pin settings table. Both schemes
have the same MSEL pin setting.
• Added description to MSEL pin setting table for configuration via
HPS to use PS or FPP MSEL pin setting.
• Updated configuration modes and features table to include Yes for
partial reconfiguration in JTAG, AS and PS configuration mode
together with a footnote mentioning only if partial reconfiguration is
configured as internal host.
• Updated note about compression and encryption cannot be used a
the same time for all configuration scheme.
• Updated timing waveforms FPP, AS and PS to include pre power-up
state.
• Removed step to select Remote from the Configuration mode list in
the Configuration page of the Device and Pin Options dialog box in
the Quartus II software.
• Added note about setting the MSEL pin to active serial to prevent
EPCQ-L ID read failure during SFL programming.
• Changed instances of Quartus II to Quartus Prime.
May 2015
2015.05.04
• Added Timing waveforms for FPP, AS and PS configuration.
• Updated 'Trace Length and Loading' to 'Trace Length Guideline' and
remove loading contents.
• Added link to Arria 10 Device Datasheet for loading information.
• Update FPP to support 8 and 32 bits in 'Configuration Modes and
Features of Arria 10 Devices'.
• Added note in 'Design Security' and 'Configuration Data Compres‐
sion' about compression and encryption cannot be used a the same
time.
January 2015
2015.01.23
• Updated CLKUSR pin usage during AS configuration at 100 MHz.
• Updated Max clock rate of PS, FPP x8, FPP x16 and Configuration
via HPS from 125 MHz to 100 MHz.
• Updated Remote System Upgrade Circuitry diagram by replacing
RU_SHIFTnLD and RU_CAPTnUPDT to RU_CTL[1:0].
• Updated ALTREMOTE_UPDATE megafunction to Altera remote
Update IP Core.
• Updated user watchdog time-out value from 34..46 to 34..45.
• Updated nIO_PULLUP to be powered by VCC.
• Added note to Max Data Rate in Configuration Modes and Features
of Arria 10 Devices table.
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Document Revision History
Date
Version
August 2014
2014.08.18
• Added the Active Serial Configuration with Multiple EPCQ-L
Devices section.
• Removed the Unique Chip ID section.
• Updated the JTAG Configuration section to include details on the
USB-Blaster download cable support.
• Updated the Power Up section.
• Updated Configuration Images section to include start address.
• Updated the Configuration Sequence in the Remote Update Mode
section.
• Updated the Remote System Upgrade State Machine section.
• Updated Figure 7-18: JTAG Configuration of a Single Device Using a
Microprocessor to update the power reference of the JTAG pins.
• Updated Figure 7-20: Configuration Sequence for Arria 10 Devices.
• Updated Figure 7-22: Arria 10 Remote System Upgrade Block
Diagram.
• Updated Table 7-1: Configuration Modes and Features of Arria 10
Devices to update the supported clock rate for Partial Reconfigura‐
tion.
• Updated Table 7-3: MSEL Pin Settings for Each Configuration
Scheme of Arria 10 Devices to include the supported VCCPGM
voltages for the FPP and PS configuration schemes.
• Updated Table 7-6: Remote System Upgrade Registers to update the
description for the shift, control, update, and status registers.
• Updated Table 7-7: Control Register Bits.
• Removed the Unique Chip ID section.
December
2013
2013.12.02
Initial release.
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SEU Mitigation for Arria 10 Devices
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2015.12.16
A10-SEU
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SEU Mitigation Overview
Single event upsets (SEU) is the change in state of a storage element inside a device or system, typically
Static Random Access Memory (SRAM), caused by cosmic radiation effects. This state is a soft error and
can often be fixed by changing the state of the storage element back to its original value and there is no
permanent damage to the device itself. Because of the unintended memory state, the device may operate
erroneously until this upset is fixed.
The Soft Error Rate (SER) is expressed as Failure-in-Time (FIT) units, defined as one soft error
occurrence every billion hours of operation. Often SEU mitigation is not required because of the low
chance of occurrence. However, for highly complex systems, such as with multiple high-density
components, error rate may be a significant system design factor. If your system includes multiple FPGAs
and requires very high reliability and availability, you should consider the implications of the soft errors,
and use the available techniques for detecting and recovering from these types of errors.
Related Information
• Introduction to Single-Event Upsets
• Understanding Single Event Functional Interrupts in FPGA Designs
• Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
SEU Mitigation Applications
Arria 10 SEU mitigation feature can help to ensure the system is functioning properly all the time, to
avoid the system being malfunction from an SEU event, or to handle the SEU event if it is critical to the
system. Common systems that requires SEU mitigation feature are as follows:
• Military or aerospace—flight systems
• Automotive or industrial—safety applications
• Telecom, data center or cloud computing—high system up-time
Configuration RAM
FPGAs use memory both in user logic (bulk memory and registers) and in Configuration RAM (CRAM).
CRAM is the memory loaded with the user's design. The CRAM configures all logic and routing in the
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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Embedded Memory
device. If an SEU strikes a CRAM bit, the effect can be harmless if the CRAM bit is not in use. However,
functional error is possible if it affects critical logic internal signal routing such as a lookup table bit.
Embedded Memory
The Arria 10 devices contain two types of memory blocks:
• 20 Kb M20K blocks—blocks of dedicated memory resources. The M20K blocks are ideal for larger
memory arrays while still providing a large number of independent ports.
• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dualpurpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The
MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applica‐
tions, wide and shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive
logic modules (ALMs). In the Arria 10 devices, you can configure these ALMs as ten 32 x 2 blocks,
giving you one 32 x 20 simple dual-port SRAM block per MLAB.
Embedded memory is susceptible to SEU, Altera implement interleaving and special layout techniques to
minimize the FIT rate, and added Error Correction Code (ECC) feature to reduce SEU FIT rate to close to
zero.
Related Information
Embedded Memory Blocks in Arria 10 Devices
Arria 10 Mitigation Techniques
Arria 10 devices feature various single-event upset (SEU) mitigation approaches for different application
areas.
Table 8-1: SEU Mitigation Areas and Approaches for Arria 10 Devices
Area
SEU Mitigation Approach
Silicon design: CRAM/SRAMs/
flip flops
Altera uses various design techniques to reduce upsets and/or limit to
correctable double-bit errors.
Error Detection Cyclic
redundancy check (EDCRC) /
Scrubbing
You can enable the EDCRC feature for detecting CRAM SEU events
and automatic correction of CRAM contents.
M20K SRAM block
Altera implemented interleaving, special layout techniques, and Error
Correction Code (ECC) reduces SEU FIT rate to almost zero.
Sensitivity processing
You can use sensitivity processing to identify if the SEU in CRAM bit is
a used or unused bit.
Fault injection
You can use fault injection feature to validate the system response to
the SEU event by changing the CRAM state to trigger an error.
Hierarchical tagging
A complementary capability to sensitivity processing and fault
injection for reporting SEU and constraining injection to specific
portions of design logic.
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Memory Blocks Error Correction Code Support
Area
Triple Modular Redundancy
(TMR)
8-3
SEU Mitigation Approach
You can implement TMR technique on critical logic such as state
machines.
Memory Blocks Error Correction Code Support
ECC allows you to detect and correct data errors at the output of the memory. ECC can perform singleerror correction, double-adjacent-error correction, and triple-adjacent-error detection in a 32-bit word.
However, ECC cannot detect four or more errors.
The M20K blocks have built-in support for ECC when in x32-wide simple dual-port mode:
• The M20K runs slower than non-ECC simple-dual port mode when ECC is engaged. However, you
can enable optional ECC pipeline registers before the output decoder to achieve higher performance
compared to non-pipeline ECC mode at the expense of one cycle of latency.
• The M20K ECC status is communicated with two ECC status flag signals—e (error) and ue
(uncorrectable error). The status flags are part of the regular output from the memory block. When
ECC is engaged, you cannot access two of the parity bits because the ECC status flag replaces them.
Related Information
Memory Blocks Error Correction Code Support
Error Detection and Correction for CRAM
The hardened on-chip EDCRC circuitry allows you to perform the following operations without any
impact on the fitting or performance of the device:
•
•
•
•
Auto-detection of cyclic redundancy check (CRC) errors during configuration.
Optional soft errors (SEU and MBU) detection and identification in user mode.
Fast soft error detection. The error detection speed is improved.
Two types of check bits:
• Frame-based check bits—stored in CRAM and used to verify the integrity of the frame.
• Column-based check bits—stored in registers and used to protect integrity of all frames.
During error detection in user mode, a number of EDCRC engines run in parallel for Arria 10 devices.
The number of error detection CRC engines depends on the frame length—total bits in a frame.
Each column-based error detection CRC engine reads 128 bits from each frame and processes within four
cycles. To detect errors, the error detection CRC engine needs to read back all frames.
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Error Detection Cyclic Redundancy Check
Error Detection Cyclic Redundancy Check
Figure 8-1: Block Diagram for Error Detection in User Mode
The block diagram shows the registers and data flow in user mode.
Readback
Bitstream
Correction
Syndrome Error Detection Pattern
CRC
Calculation
Search Engine
Write Back to
CRAM for Correction
CRC_ERROR
Error Message Register
JTAG Update User Update
Register
Register
HPS Update
Register
JTAG Shift
Register
User Shift
Register
HPS Shift
Register
JTAG
TDO
General
Routing
HPS
Output
Table 8-2: Error Detection Registers
Name
Description
Error message registers
(EMR)
Contains error details for single-bit and double-adjacent errors. The error
detection circuitry updates this register each time the circuitry detects an
error.
User update register
This register is automatically updated with the contents of the EMR one
clock cycle after the contents of this register are validated. The user update
register includes a clock enable, which must be asserted before its contents
are written to the user shift register. This requirement ensures that the user
update register is not overwritten when its contents are being read by the
user shift register.
User shift register
This register allows user logic to access the contents of the user update
register via the core interface.
You can use the Altera Error Message Register Unloader IP Core to shift-out
the EMR information through user shift register. For more information,
please refer to related information.
JTAG update register
Altera Corporation
This register is automatically updated with the contents of the EMR one
clock cycle after the content of this register is validated. The JTAG update
register includes a clock enable, which must be asserted before its contents
are written to the JTAG shift register. This requirement ensures that the
JTAG update register is not overwritten when its contents are being read by
the JTAG shift register.
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EDCRC Check Bits
Name
8-5
Description
JTAG shift register
This register allows you to access the contents of the JTAG update register
via the JTAG interface using the SHIFT_EDERROR_REG JTAG instruction.
HPS update register
This register is automatically updated with the contents of the EMR one
clock cycle after the content of this register is validated. The HPS update
register includes a clock enable, which must be asserted before its contents
are written to the HPS shift register. This requirement ensures that the HPS
update register is not overwritten when its contents are being read by the
HPS shift register.
HPS shift register
This register allows you to access the contents of the HPS update register via
the HPS interface.
Related Information
• Altera Error Message Register Unloader IP Core User Guide
Provides more information about using the user shift register to shift-out the EMR.
• FPGA Manager Address Map and Register Definitions in Arria 10 Hard Processor System
Technical Reference Manual
Provides more information about using hard processor system to read the error detection registers.
EDCRC Check Bits
Figure 8-2: Check Bits Calculation for Error Detection CRC
128-Bits
Data
128-Bits
Data
128-Bits
Data
128-Bits
Data
128-Bits
Data
32-Bits ColumnBased CRC
Column 0
Column 1
32-Bits
Frame-Based CRC
32-Bits
Frame-Based CRC
32-Bits
Frame-Based CRC
32-Bits
Frame-Based CRC
32-Bits
Column-Based CRC
Last Column
Frame 0
Frame 1
Frame 2
Last Frame
EDCRC Check Bits Updates
Frame-based EDCRC is calculated on-chip during configuration. Column-based EDCRC is updated after
configuration.
When you enable the EDCRC feature, after the device enters user mode, the EDCRC function starts
reading CRAM frames. The data collected from the read-back frame is validated against the frame-based
CRC.
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CRC_ERROR Pin Behavior
After the initial frame-based verification is completed, the column-based CRC check bits will be
calculated based on the respective column CRAM. The EDCRC hard block will recalculate the columnbased CRC check bits in one of the following scenarios:
• FPGA re-configuration
• After successful partial reconfiguration (PR) session
• After configuration via protocol (CvP) session
CRC_ERROR Pin Behavior
If a CRAM error is detected, the CRC_ERROR signal goes high. After the signal goes low, you can access the
error message register (EMR) to obtain information about the error type and location.
Figure 8-3: Timing Diagram for Column-Based EDCRC
If the error is correctable, there will be a second pulse in one SEU event. The complete EMR will only be
available at the falling edge of the second pulse.
Next SEU Event
One SEU Event
Column-Based CRC
Assertion Time
Duration to expect 2nd
pulse triggered by
Frame-Based EDCRC Error
Frame-Based CRC
Assertion Time
CRC ERROR Pin
Column-Based
Error Detected
Column-Based EMR
is Available
Complete EMR is Available
Unload EMR Ends
Unload EMR Start
Figure 8-4: Timing Diagram for Column-Based or Frame-Based EDCRC
Figure shows an example of CRC_ERROR Pin Behavior for column-based or frame-based EDCRC with a
single pulse observed in one SEU event.
• When column-based EDCRC detects an uncorrectable error, the error type is 111.
• When frame-based EDCRC detects an error during column-based checks bits calculation, column
error type is 0
Column-Based/Frame-Based CRC
Assertion Time
CRC ERROR Pin
Frame-Based
Error Detected
Unload EMR
Starts
Related Information
Arria 10 Device Family Pin Connection Guidelines
Provides more information about CRC_ERROR connection guidelines.
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Error Message Register
Error Message Register
The EMR contains information on the error type, the location of the error, and the actual syndrome. This
register is 78 bits wide in Arria 10 Device. The EMR does not identify the location bits for other types of
errors. The location of the errors consists of the frame number, double word location and bit location
within the frame and column.
You can shift out the contents of the register through the following:
• SHIFT_EDERROR_REG JTAG instruction
• Core interface
• HPS Shift register
Figure 8-5: Error Message Register Map
MSB
LSB
Frame Address
Column-Based
Double Word
Column-Based
Bit
Column-Based
Type
Frame-Based
Syndrome
Frame-Based
Double Word
Frame-Based
Bit
Frame-Based
Type
16 bits
2 bits
5 bits
3 bits
32 bits
10 bits
5 bits
3 bits
Column-CheckBit Update
Reserved
1 bit
1 bit
Table 8-3: Error Message Register Width and Description
Name
Width (Bits)
Description
Frame Address
16
Frame Number of the error location
Column-Based Double
Word
2
There are 4 double words per frame in a column. It
indicates the double word location of the error
Column-Based Bit
5
Error location within 32-bit double word
Column-Based Type
3
Types of error shown in Table 3
Frame-based syndrome
register
32
Contains the 32-bit CRC signature calculated for the current
frame. If the CRC value is 0, the CRC_ERROR pin is driven
low to indicate no error. Otherwise, the pin is pulled high.
Frame-Based Double Word
10
Double word location within the CRAM frame. Double
word 0 locates in the left most
Frame-Based Bit
5
Error location within 32-bit double word
Frame-Based Type
3
Types of error shown in Error Type in EMR table
Reserved
1
Reserved bit
Column-Check-Bit Update
1
Logic high if there is error encountered during column
check bits update stage. The CRC_ERROR will be asserted and
stay high until the FPGA is reconfigured.
Retrieving Error Information
You can retrieve the EMR contents via the core interface or the JTAG interface using the
SHIFT_EDERROR_REG JTAG instruction. Altera provides Error Message Register Unloader IP Core that
unload EMR content via core interface and allows it to be shared between several design component.
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Error Type in EMR
Related Information
Altera Error Message Register Unloader IP Core User Guide
Provides more information about using the user shift register to shift-out the EMR.
Error Type in EMR
Table 8-4: Error Type in EMR
The following table lists the possible error types reported in the error type field in the EMR.
Error Types
Frame-based Type
Column-based
Type
Bit 2
Bit 1
Bit 0
Description
0
0
0
No error
0
0
1
Single-bit error
0
1
X
Double-adjacent error
1
1
1
Uncorrectable error
0
0
0
No error
0
0
1
Single bit error
0
1
X
Double-adjacent error
1
0
X
Double-adjacent error
1
1
0
Double-adjacent error
1
1
1
Uncorrectable error
SEU Sensitivity
Reconfiguring a running FPGA has a significant impact on the system using the FPGA. When planning
for SEU recovery, account for the time required to bring the FPGA to a state consistent with the current
state of the system. For example, if an internal state machine is in an illegal state, it may require reset. In
addition, the surrounding logic may need to account for this unexpected operation.
Often an SEU impacts CRAM bits not used by the implemented design. Many configuration bits are not
used because they control logic and routing wires that are not used in a design. Depending on the
implementation, 40% of all CRAM bits can be used even in the most heavily utilized devices. This means
that only 40% of SEU events require intervention, and you can ignore 60% of SEU events. The utilized bits
are considered as critical bits while the non-utilized bits are considered as non-critical bits.
You can determine that portions of the implemented design are not utilized in the FPGA’s function.
Examples may include test circuitry implemented but not important to the operation of the device, or
other non-critical functions that may be logged but do not need to be reprogrammed or reset.
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Hierarchy Tagging
8-9
Figure 8-6: Sensitivity Processing Flow
Normal
Operation
CRAM CRC
Error?
no
yes
Notify
System
Look Up Sensitivity
of CRAM Bit
Critical Bit?
no
yes
Take Corrective
Action
Hierarchy Tagging
Hierarchy tagging is the process of classifying the sensitivity of the portions of your design.
You can perform hierarchy tagging using the Quartus Prime software by creating a design partition, and
then assigning the parameter Advanced SEU Detection (ASD) Region to that partition. The parameter
can assume a value from 0 to 15, so there are 16 different classifications of system responses to the
portions of your design.
The design hierarchy sensitivity processing depends on the contents of the Sensitivity Map Header file
(.smh). This file determines the correct (least disruptive) recovery sequence for any CRAM bit flip.
The .smh designates the sensitivity of each portion of the FPGA’s logic design.
To generate the .smh, you must designate the sensitivity of the design from a functional logic view, using
the hierarchy tagging procedure.
Related Information
Altera Advanced SEU Detection IP Core User Guide
Provides more information about hierarchy tagging using Altera Advanced SEU Detection IP core.
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Evaluating Your System’s Response to Functional Upsets
Evaluating Your System’s Response to Functional Upsets
The ratio of SEU strikes versus functional interrupts is the Single Event Functional Interrupt (SEFI) ratio.
Minimizing this ratio improves SEU mitigation. SEUs can randomly strike any memory element, system
testing is important to ensure a comprehensive recovery response. You can use the Fault Injection
Debugger to aid in SEU recovery response.
The Fault Injection Debugger allows you to operate the FPGA in your system and inject random CRAM
bit flips to test the ability of the FPGA and the system to detect and recover fully from an SEU. You should
be able to observe your FPGA and your system recover from these simulated SEU strikes. You can then
refine your FPGA and system recovery sequence by observing these strikes. You can determine the SEFI
rate of your design by using the Altera Fault Injection.
If you have recorded an SEU in the device’s Error Message Register, the Fault Injection Debugger also
allows you to specify a targeted fault to be injected (rather than inject the fault in a random location).
Related Information
• Altera Fault Injection IP Core User Guide
Provides more information about injecting soft error to simulate SEU using Altera Fault Injection IP
Core.
• Debugging Single Event Upset Using the Fault Injection Debugger
Provides more information about using Fault Injection Debugger.
Recovering from CRC Errors
Arria 10 devices support the internal scrubbing capability. The internal scrubbing feature corrects CRAM
upsets automatically when an upset is detected. However, internal scrubbing does not fix the FPGA to a
known good state. The time between the error and completion of scrubbing can be tens of millisecond.
This duration represents many thousands of clock cycles in which data was legally written to memories, or
status registers. It is good practice to always follow any SEU event with a soft-reset to bring the FPGA
operation to the known good state.
If a soft-reset could not bring the FPGA to the known good state, you can reconfigure the device to
rewrite the CRAM and reinitialize the design registers. The system that hosts the Arria 10 device must
control the device reconfiguration. You can reconfigure the Arria 10 device by driving the nCONFIG signal
low. When reconfiguration completes successfully, the Arria 10 device operates as intended.
Related Information
Configuration, Design Security, and Remote System Upgrades for Arria 10 Devices
Provides more information about configuration sequence.
Enabling Internal Scrubbing
When error detection is enabled, Arria 10 devices use column-based CRC to detect errors. When errors
are found, frame-based CRC is used to locate and correct the errors when internal scrubbing is enabled.
To enable the internal scrubbing feature, follow these steps:
1.
2.
3.
4.
Altera Corporation
On the Assignments menu, click Device.
Click Device and Pin Options and select the Error Detection CRC tab.
Turn on Enable internal scrubbing.
Click OK.
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Specifications
8-11
Specifications
This section lists the error detection frequencies and CRC calculation time for error detection in user
mode.
Error Detection Frequency
When you are unable to meet the EMR update interval specification, you can reduce the error detection
frequency. You can control the speed of the error detection process by setting the division factor of the
clock frequency in the Quartus Prime software. The divisor is N, where N can be any value listed in the
following table.
The speed of the error detection process for each data frame is determined by the following equation:
Figure 8-7: Error Detection Frequency Equation
Error Detection Frequency
=
Internal Oscillator Frequency
N
Table 8-5: Error Detection Frequency Range for Arria 10 Devices
The following table lists the FMIN and FMAX for each speed grade.
Note: Frequencies shown are when N = 1. For N = 2 or 4, divide frequency shown accordingly.
Speed Grade
Error Detection Frequency
fMIN
fMAX
1
49
77
2
45
77
3
42
77
Error Detection Time
The time taken to detect the SEU error relative to the actual SEU event. This is determined by the device
in use and the frequency of the error detection clock.
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EMR Update Interval
Table 8-6: CRC Calculation Time in Arria 10 Devices
Error detection timeMaximum = Error detection time x
Error Detection Frequency fMAX
( Error Detection Frequency f ) x N
MIN
Error detection timeMinimum = Error detection time x N
• Speed grade 1: N=1, 2 or 4.
• Speed grade 2 and 3: N=2 or 4 only.
Variant
GX/SX
GX/ GT
Density
Error Detection Time (ms)
160 / 220
14.29
270 / 320
14.29
480
21.13
570/ 660
27.84
900 / 1150
27.84
EMR Update Interval
You must unload the EMR data within the minimum EMR Update Interval to avoid the current EMR
data from being overwritten by the information of the next error. However, Altera EMR Unloader IP
Core can handle this by ensuring no EMR data loss during unloading process. The IP core will detect the
loss of EMR information by flagging the emr_error signal.
The interval between each update of the error message register depends on the device and the frequency
of the error detection clock.
Table 8-7: Estimated EMR Update Interval in Arria 10 Devices
EMR update interval Maximum = EMR update interval x
Error Detection Frequency fMAX
( Error Detection Frequency f ) x N
MIN
EMR update intervalMinimum = EMR update interval x N
• Speed grade 1: N=1, 2 or 4.
• Speed grade 2 and 3: N=2 or 4 only.
Variant
GX/SX
GX/ GT
Density
EMR Update Interval (ms)
160 / 220
0.28
270 / 320
0.28
480
0.41
570/ 660
0.54
900 / 1150
0.55
Error Correction Time
Arria 10 offers fast error correction capability, the correction time for each device variant are shown in the
following table.
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Document Revision History
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Table 8-8: Error Correction Time
Error Detection Frequency fMAX
( Error Detection Frequency f ) x N
Correction timeMaximum
= Correction time x
Correction timeMinimum
= Correction time x N
MIN
Note: • Speed grade 1: N=1, 2 or 4.
• Speed grade 2 and 3: N=2 or 4 only.
Variant
GX/SX
GX/GT
Density
Correction Time (µs)
160/220
19.73
270/320
27.62
480
27.21
570/660
27.21
900/1150
39.68
Document Revision History
Date
Version
Changes
December 2015
2015.12.14
• Updated chapter structure.
• Added Error Correction Time specifica‐
tion.
• Added brief description and external
related information link for Embedded
Memory, Memory Blocks Error Correction
Code Support, SEU Sensitivity, Hierarchy
Tagging, and Evaluating your System
Response to SEU.
• Updated divisor value in Error Detection
Frequency.
• Updated Error Detection Frequency
Range table showing fMAX and fMIN.
• Updated Estimated EMR Update Interval
and CRC Calculation Time table.
• Added equation for EMR update interval
and CRC calculation time.
November 2015
2015.11.02
Changed instances of Quartus II to Quartus
Prime.
June 2015
2015.06.15
Updated links to Altera EMR Unloader IP
Core User Guide, Altera Fault Injection IP
Core User Guide and Altera Advance SEU
Detection IP Core User Guide.
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Document Revision History
Date
Version
Changes
May 2015
2015.05.04
• Added links to Altera EMR Unloader IP
Core User Guide, Altera Fault Injection IP
Core User Guide and Altera Advance SEU
Detection IP Core User Guide.
• Updated CRC_ERROR pin behavior to
included column-based and frame-based
CRC error detection and frame-based only
CRC error detection.
• Updated column-based type in 'Error
Type in EMR' at Bit 0.
• Editorial changes.
• Updated the divisor value and range for
error detection frequency.
• Updated CRC calculation time by
including speed grade and rearranged
accordingly.
• Updated EMR update interval.
• Updated Error Message Register Map and
registers in Error Detection in User Mode
block diagram.
January 2015
2015.01.23
• Added EMR timing interval.
• Added CRC calculation time.
• Added timing diagram
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Document Revision History
Date
Version
8-15
Changes
August 2014
2014.08.18
• Updated the Error Detection Features
section.
• Updated the Configuration Error
Detection section to revise the CRC value.
• Updated the User Mode Error Detection
section to add in the check bits calculation
for error detection CRC.
• Updated the CRC_ERROR Pin Behavior
section.
• Updated the Retrieving Error Information
section.
• Updated the CRC_ERROR Pin section to
update the pin description.
• Updated Table 8-4 to updated the descrip‐
tion of the frame-based syndrome register,
user update register, and user shift
register.
• Updated Table 8-5 to update the error
types naming to frame-based and columnbased types.
December 2013
2013.12.02
Initial release.
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JTAG Boundary-Scan Testing in Arria 10
Devices
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This chapter describes the boundary-scan test (BST) features in Arria 10 devices.
Related Information
Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
BST Operation Control
Arria 10 GX, Arria 10 GT, and Arria 10 SX devices support IEEE Std. 1149.1 BST and IEEE Std. 1149.6
BST. You can perform BST on Arria 10 devices before, after, and during configuration.
IDCODE
The IDCODE is unique for each Arria 10 device. Use this code to identify the devices in a JTAG chain.
Table 9-1: IDCODE Information for Arria 10 Devices—Preliminary
IDCODE (32 Bits)
Variant
Arria 10 GX
Product Line
Version (4 Bits)
Part Number (16 Bits)
Manufacture
Identity (11
Bits)
LSB (1 Bit)
GX 160
0000
0010 1110 1100 0010
000 0110 1110
1
GX 220
0000
0010 1110 0100 0010
000 0110 1110
1
GX 270
0000
0010 1110 1100 0011
000 0110 1110
1
GX 320
0000
0010 1110 0100 0011
000 0110 1110
1
GX 480
0000
0010 1110 0100 0100
000 0110 1110
1
GX 570
0000
0010 1110 1100 0101
000 0110 1110
1
GX 660
0000
0010 1110 0100 0101
000 0110 1110
1
GX 900
0000
0010 1110 1100 0110
000 0110 1110
1
GX 1150
0000
0010 1110 1000 0110
000 0110 1110
1
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Supported JTAG Instruction
IDCODE (32 Bits)
Variant
Product Line
Version (4 Bits)
Part Number (16 Bits)
Manufacture
Identity (11
Bits)
LSB (1 Bit)
GT 900
0000
0010 1110 0100 0110
000 0110 1110
1
GT 1150
0000
0010 1110 0000 0110
000 0110 1110
1
SX 160
0000
0010 1110 1000 0010
000 0110 1110
1
SX 220
0000
0010 1110 0000 0010
000 0110 1110
1
SX 270
0000
0010 1110 1000 0011
000 0110 1110
1
SX 320
0000
0010 1110 0000 0011
000 0110 1110
1
SX 480
0000
0010 1110 0000 0100
000 0110 1110
1
SX 570
0000
0010 1110 1000 0101
000 0110 1110
1
SX 660
0000
0010 1110 0000 0101
000 0110 1110
1
Arria 10 GT
Arria 10 SX
Supported JTAG Instruction
Table 9-2: JTAG Instructions Supported by Arria 10 Devices
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
• Allows you to capture and
examine a snapshot of signals at
the device pins during normal
device operation and permits an
initial data pattern to be an output
at the device pins.
• Use this instruction to preload the
test pattern into the update
registers before loading the
EXTEST instruction.
EXTEST
00 0000 1111
• Allows you to test the external
circuit and board-level intercon‐
nects by forcing a test pattern at
the output pins, and capturing the
test results at the input pins.
Forcing known logic high and low
levels on output pins allows you to
detect opens and shorts at the pins
of any device in the scan chain.
• The high-impedance state of
EXTEST is overridden by bus hold
and weak pull-up resistor features.
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Supported JTAG Instruction
JTAG Instruction
Instruction Code
9-3
Description
BYPASS
11 1111 1111
• Places the 1-bit bypass register
between the TDI and TDO pins.
During normal device operation,
the 1-bit bypass register allows the
BST data to pass synchronously
through the selected devices to
adjacent devices.
• You will get a '0' reading in the
bypass register out.
USERCODE
00 0000 0111
Selects the 32-bit USERCODE register
and places it between the TDI and TDO
pins to allow serial shifting of
USERCODE out of TDO.
IDCODE
00 0000 0110
• Identifies the devices in a JTAG
chain. If you select IDCODE, the
device identification register is
loaded with the 32-bit
vendor-defined identification
code.
• Selects the IDCODE register and
places it between the TDI and TDO
pins to allow serial shifting of
IDCODE out of TDO.
• IDCODE is the default instruction at
power up and in the TAP RESET
state. Without loading any
instructions, you can go to the
SHIFT_DR state and shift out the
JTAG device ID.
HIGHZ
00 0000 1011
• Sets all user I/O pins to an inactive
drive state.
• Places the 1-bit bypass register
between the TDI and TDO pins.
During normal operation, the
1-bit bypass register allows the
BST data to pass synchronously
through the selected devices to
adjacent devices while tri-stating
all I/O pins until a new JTAG
instruction is executed.
• If you are testing the device after
configuration, the programmable
weak pull-up resistor or the bus
hold feature overrides the HIGHZ
value at the pin.
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Supported JTAG Instruction
JTAG Instruction
Instruction Code
Description
CLAMP
00 0000 1010
• Places the 1-bit bypass register
between the TDI and TDO pins.
During normal operation, the
1-bit bypass register allows the
BST data to pass synchronously
through the selected devices to
adjacent devices while holding the
I/O pins to a state defined by the
data in the boundary-scan register.
• If you are testing the device after
configuration, the programmable
weak pull-up resistor or the bus
hold feature overrides the CLAMP
value at the pin. The CLAMP value
is the value stored in the update
register of the boundary-scan cell
(BSC).
PULSE_NCONFIG
00 0000 0001
Emulates pulsing the nCONFIG pin
low to trigger reconfiguration even
though the physical pin is not
affected.
EXTEST_PULSE
00 1000 1111
Enables board-level connectivity
checking between the transmitters
and receivers that are AC coupled by
generating three output transitions:
• Driver drives data on the falling
edge of TCK in the
UPDATE_IR/DR state.
• Driver drives inverted data on the
falling edge of TCK after entering
the RUN_TEST/IDLE state.
• Driver drives data on the falling
edge of TCK after leaving the
RUN_TEST/IDLE state.
EXTEST_TRAIN
00 0100 1111
Behaves the same as the
EXTEST_PULSE instruction except that
the output continues to toggle on the
TCK falling edge as long as the TAP
controller is in the RUN_TEST/IDLE
state.
SHIFT_EDERROR_REG
00 0001 0111
The JTAG instruction connects the
EMR to the JTAGpin in the error
detection block between the TDI and
TDO pins.
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JTAG Secure Mode
9-5
Note: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might
not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG
instruction only when the nCONFIG and nSTATUS signals are high.
Related Information
JTAG Secure Mode on page 7-44
Provides more information about PULSE_NCONFIG and CONFIG_IO JTAG instructions.
JTAG Secure Mode
In the JTAG secure mode, the JTAG pins support only the BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE, and
USERCODE JTAG instructions.
JTAG Private Instruction
Caution: Never invoke the following instruction codes. These instructions can damage and render the
device unusable:
•
•
•
•
•
•
•
•
•
•
•
1100010000
1100010011
0111100000
0101011110
0000101010
0011100000
0000101010
0101000001
1110000001
0001010101
1010100001
I/O Voltage for JTAG Operation
The Arria 10 device operating in IEEE Std. 1149.1 and IEEE Std. 1149.6 mode uses four required JTAG
pins—TDI, TDO, TMS, TCK, and one optional pin, TRST.
The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have internal weak
pull-up resistors. The 1.8-, 1.5-, or 1.2-V VCCPGM supply powers the TDI, TDO, TMS, TCK, and TRST pins. All
user I/O pins are tri-stated during JTAG configuration.
The JTAG pins support 1.8 V, 1.5V, and 1.2V TTL/CMOS I/O standard. For any voltages higher than
1.8 V, you have to use level shifter. The output voltage of the level shifter for the JTAG pins must be the
same as set for the VCCPGM supply.
Note: Do not drive a signal with a voltage higher than 1.8-, 1.5-, and 1.2-V VCCPGM supply for the TDI,
TMS, TCK, and TRST pins. The voltage supplies for TDI, TMS, TCK, and TRST input pins must be the
same as set for the VCCPGM supply.
Table 9-3: TDO Output Buffer
TDO Output Buffer
VCCPGM
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1.8
1.5
1.2
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Performing BST
TDO Output Buffer
VOH (MIN)
Voltage (V)
1.7
1.4
1.1
Performing BST
You can issue BYPASS, IDCODE, and SAMPLE JTAG instructions before, after, or during configuration
without having to interrupt configuration.
To issue other JTAG instructions, follow these guidelines:
• To perform testing before configuration, hold the nCONFIG pin low.
• To perform BST during configuration, issue CONFIG_IO JTAG instruction to interrupt configuration.
While configuration is interrupted, you can issue other JTAG instructions to perform BST. After BST
is completed, issue the PULSE_NCONFIG JTAG instruction or pulse nCONFIG low to reconfigure the
device.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Arria 10 devices do not
affect JTAG boundary-scan or configuration operations. Toggling these pins does not disrupt BST
operation (other than the expected BST behavior).
If you design a board for JTAG configuration of Arria 10 devices, consider the connections for the
dedicated configuration pins.
Note: For SoC devices, JTAG connections in the FPGA block and JTAG connections in the HPS block
are chained to the Arria 10 device. JTAG connections in the FPGA have higher priority over the
JTAG connections in the HPS block.
Note: If you perform the HIGHZ JTAG instruction before or during configuration, you need to pull the
nIO_PULLUP pin to high to disable the internal weak pull-up resistors in the I/O elements. If you
perform this JTAG instruction during user mode, you can pull high or pull low the nIO_PULLUP
pin.
Note: If you perform BST during user mode, you are not able to capture the correct values for the
PR_ENABLE, CRC_ERROR, and CVP_CONFDONE pins when these pins are not used as user I/O pins.
Note: You can perform JTAG BST only when both nCONFIG and nSTATUS goes high after power-up.
Related Information
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides more information about pin connections.
• Arria 10 Device Datasheet
Provides more information about JTAG configuration timing.
• JTAG Configuration on page 7-22
Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
The IEEE Std. 1149.1 BST circuitry is enabled after the Arria 10 device powers up. However for Arria 10
SoC FPGAs, you must power up both HPS and FPGA to perform BST.
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Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
9-7
To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required,
disable the circuitry permanently with pin connections as listed in the following table.
Table 9-4: Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Arria 10 Devices
JTAG Pins(31)
Connection for Disabling
TMS
VCCPGM
TCK
GND
TDI
VCCPGM
TDO
Leave open
TRST
GND
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
Consider the following guidelines when you perform BST with IEEE Std. 1149.1 devices:
• If the “10...” pattern does not shift out of the instruction register through the TDO pin during the first
clock cycle of the SHIFT_IR state, the TAP controller did not reach the proper state. To solve this
problem, try one of the following procedures:
• Verify that the TAP controller has reached the SHIFT_IR state correctly. To advance the TAP
controller to the SHIFT_IR state, return to the RESET state and send the 01100 code to the TMS pin.
• Check the connections to the VCC, GND, JTAG, and dedicated configuration pins on the device.
• Perform a SAMPLE/PRELOAD test cycle before the first EXTEST test cycle to ensure that known data is
present at the device pins when you enter EXTEST mode. If the OEJ update register contains 0, the data
in the OUTJ update register is driven out. The state must be known and correct to avoid contention
with other devices in the system.
• Do not perform EXTEST testing during in-circuit reconfiguration because EXTEST is not supported
during in-circuit reconfiguration. To perform testing, wait for the configuration to complete or issue
the CONFIG_IO instruction to interrupt configuration.
• After configuration, you cannot test any pins in a differential pin pair. To perform BST after configu‐
ration, edit and redefine the BSC group that correspond to these differential pin pairs as an internal
cell.
Related Information
IEEE 1149.1 BSDL Files
Provides more information about the BSC group definitions.
IEEE Std. 1149.1 Boundary-Scan Register
The boundary-scan register is a large serial shift register that uses the TDI pin as an input and the TDO pin
as an output. The boundary-scan register consists of 3-bit peripheral elements that are associated with
(31)
The JTAG pins are dedicated. Software option is not available to disable JTAG in Arria 10 devices.
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Boundary-Scan Cells of an Arria 10 Device I/O Pin
Arria 10 I/O pins. You can use the boundary-scan register to test external pin connections or to capture
internal data.
Figure 9-1: Boundary-Scan Register
This figure shows how test data is serially shifted around the periphery of the IEEE Std. 1149.1 device.
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
dedicated
configuration pin.
Internal Logic
TAP Controller
TDI
TMS
TCK
TDO
Boundary-Scan Cells of an Arria 10 Device I/O Pin
The Arria 10 device 3-bit BSC consists of the following registers:
• Capture registers—Connect to internal device data through the OUTJ, OEJ, and PIN_IN signals.
• Update registers—Connect to external data through the PIN_OUT and PIN_OE signals.
The TAP controller generates the global control signals for the IEEE Std. 1149.1 BST registers (shift,
clock, and update) internally. A decode of the instruction register generates the MODE signal.
The data signal path for the boundary-scan register runs from the serial data in (SDI) signal to the serial
data out (SDO) signal. The scan register begins at the TDI pin and ends at the TDO pin of the device.
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Boundary-Scan Cells of an Arria 10 Device I/O Pin
Figure 9-2: User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Arria 10 Devices
SDO
INJ
From or
to device
I/O circuitry
and/or
logic array
PIN_IN
0
1
D Q
Input
D Q
Input
0
1
D
D
OE
OE
0
1
D Q
Output
D Q
Output
CLK
UPDATE
Capture
Registers
Update
Registers
Input
Buffer
0
1
RDEBUG
OEJ
Q
Q
0
1 1
OUTJ
SHIFT SDIN
HIGHZ
MODE
0
1
PIN_OE
0
1
PIN_OUT
Pad
Output
Buffer
Global
Signals
Note: TDI, TDO, TMS, TCK, TRST, VCC, GND, VREF, VSIGP, VSIGN, TEMPDIODE, and RREF pins do not have
BSCs.
Table 9-5: Boundary-Scan Cell Descriptions for Arria 10 Devices
This table lists the capture and update register capabilities of all BSCs within Arria 10 devices.
Captures
Pin Type
Output
Capture
Register
User I/O pins OUTJ
Dedicated
clock input
No
Connect
(N.C.)
OE Capture
Register
Input
Capture
Register
Output
Update
Register
OE Update
Register
Input
Update
Register
Comments
OEJ
PIN_IN
PIN_OUT
PIN_OE
INJ
—
N.C.
PIN_IN
N.C.
N.C.
N.C.
PIN_IN drives
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IEEE Std. 1149.6 Boundary-Scan Register
Captures
Output
Capture
Register
Pin Type
Drives
OE Capture
Register
Input
Capture
Register
Output
Update
Register
OE Update
Register
Input
Update
Register
Comments
Dedicated
input
N.C.
N.C.
PIN_IN
N.C.
N.C.
N.C.
PIN_IN drives
to the control
logic
Dedicated
bidirectional
(open drain)
0
OEJ
PIN_IN
N.C.
N.C.
N.C.
PIN_IN drives
OUTJ
OEJ
N.C.
N.C.
N.C.
PIN_IN drives
N.C.
N.C.
N.C.
(32)
Dedicated
bidirec‐
tional(33)
Dedicated
output(34)
OUTJ
0
PIN_IN
0
to the
configuration
control
to the
configuration
control and
OUTJ drives to
the output
buffer
OUTJ drives to
the output
buffer
IEEE Std. 1149.6 Boundary-Scan Register
The BSCs for HSSI transmitters (GXB_TX[p,n]) and receivers/input clock buffers
(GXB_RX[p,n])/(REFCLK[p,n]) in Arria 10 devices are different from the BSCs for the I/O pins.
Note: You have to use the EXTEST_PULSE JTAG instruction for AC-coupling on HSSI transceiver. Do not
use the EXTEST JTAG instruction for AC-coupling on HSSI transceiver. You can perform AC JTAG
on the Arria 10 device before, after, and during configuration.
(32)
(33)
(34)
This includes the CONF_DONE and nSTATUS pins.
This includes the DCLK pin.
This includes the nCEO pin.
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IEEE Std. 1149.6 Boundary-Scan Register
Figure 9-3: HSSI Transmitter BSC with IEEE Std. 1149.6 BST Circuitry for Arria 10 Devices
PMA
SDOUT
BSCAN
AC JTAG
Output Buffer
0
BSTX1
0
D
D
Q
Q
OE
1
1
Pad
Mission
0
D
D
Q
Q
(DATAOUT)
0
1
BSOEB
1
TX_BUF_OE
Tx Output
Buffer
nOE
Pad
OE Logic
MORHZ
ACJTAG_BUF_OE
0
0
D
Q
D
OE
BSTX0
Q
1
1
MEM_INIT SDIN
AC JTAG
Output Buffer
SHIFT
CLK
UPDATE
Capture
Registers
HIGHZ
AC_TEST
AC_MODE
MODE
Update
Registers
Figure 9-4: HSSI Receiver/Input Clock Buffer with IEEE Std. 1149.6 BST Circuitry for Arria 10 Devices
SDOUT
BSCAN
PMA
BSRX1
AC JTAG Test
Receiver
Hysteretic
Memory
0
D
BSOUT1
Q
Pad
Mission (DATAIN)
Optional INTEST/RUNBIST
not supported
1
RX Input
Buffer
Pad
BSRX0
0
D
AC JTAG Test
Receiver
Hysteretic
Memory
BSOUT0
Q
1
HIGHZ
SDIN
SHIFT
CLK
UPDATE
AC_TEST
MODE
Capture
Registers
AC_MODE
Update
Registers
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Document Revision History
Document Revision History
Date
Version
Changes
December
2015.12.14
• Updated User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Arria
10 Devices figure.
• Added SHIFT_EDERROR_REG in Supported JTAG instruction table.
November
2015
2015.11.02
Added note to state that JTAG BST can be performed after nSTATUS
and nCONFIG are high.
August 2014
2014.08.18
• Updated the JTAG Private Instruction section to add a new instruc‐
tion code.
• Updated the I/O Voltage for JTAG Operation section to update the
TDO output buffer details.
• Updated the Performing BST section to add a note on performing
BST in user mode.
• Updated the Boundary-Scan Cells of an Arria 10 Device I/O Pin
section.
December
2013
2013.12.02
Initial release.
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Power Management in Arria 10 Devices
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This chapter describes the power consumption, power reduction techniques, power sense line feature, onchip voltage sensor, internal and external temperature sensing diode (TSD), power-on reset (POR)
requirements, power-up and power-down sequencing requirements, and power supply design.
Related Information
• Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
• PowerPlay Power Analysis chapter in volume 3 of the Quartus Prime Handbook
Provides more information about the Quartus Prime PowerPlay Power Analyzer tool.
• Recommended Operating Conditions
Provides more information about the recommended operating conditions of each power supply.
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides detailed information about power supply pin connection guidelines and power regulator
sharing.
• Board Design Resource Center
Provides detailed information about power supply design requirements.
• PowerPlay Early Power Estimators (EPE) and Power Analyzer
Provides more information about the power supplies and the current requirements for each power rail.
• Altera Power Management PowerSoC Solutions
Provides more information about Altera's Power Management IC and PowerSoC solutions designed
for powering FPGAs.
Power Consumption
The total power consumption of an Arria 10 device consists of the following components:
• Static power—the power that the configured device consumes when powered up but no user clocks are
operating.
• Dynamic power— the additional power consumption of the device due to signal activity or toggling.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Dynamic Power Equation
Figure 10-1: Dynamic Power
The following equation shows how to calculate dynamic power where P is power, C is the load
capacitance, and V is the supply voltage level. The frequency refers to the clock frequency and data toggles
once every clock cycle.
The equation shows that power is design-dependent and is determined by the operating frequency of your
design. Arria 10 devices minimize static and dynamic power using advanced process optimizations. These
optimizations allow Arria 10 designs to meet specific performance requirements with the lowest possible
power.
Power Reduction Techniques
Arria 10 devices leverage on advanced 20nm process technology, an enhanced core architecture, and
optimization to reduce total power consumption. The optional power reduction techniques listed below
are offered and supported in the Arria 10 PowerPlay Early Power Estimator (EPE), which can be used to
estimate the power reduction impact by enabling each of them in an Arria 10 design.
•
•
•
•
SmartVID
VCC PowerManager
Programmable Power Technology
Low Static Power Device Grades
SmartVID
The SmartVID feature allows a power regulator to provide the Arria 10 device with a lower VCC and VCCP
voltage level while maintaining the performance of the specific device speed grade. Operating the Arria 10
device at lower than nominal VCC and VCCP voltage levels reduces total power consumption. The
minimum voltage level required by Arria 10 devices is programmed into a fuse block during device
manufacturing. Altera provides an IP core to read these values and communicate them to an external
power regulator or system power controller. This feature is supported in –2 and –3 speed grades devices
with –V power option only.
When the SmartVID feature is used, Arria 10 devices need to be powered up at nominal voltage level.
During configuration and partial reconfiguration modes, Arria 10 devices continue to operate at nominal
voltage level. Upon entering user mode, the Arria 10 device can operate at a lower voltage as in the fuse
block. The error detection cyclic redundancy check (EDCRC) feature is supported for –2 speed grade
devices even when the SmartVID feature is used. However, for other speed grades, Arria 10 devices need
to operate at nominal voltage when performing the EDCRC feature. The scrubbing and partial reconfigu‐
ration features are supported only when the device is operated at nominal voltage.
Related Information
• Power Reduction Features in Arria 10 Devices
• SmartVID Controller IP Core User Guide
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VCC PowerManager
10-3
VCC PowerManager
The VCC PowerManager feature allows Arria 10 devices to run at the lowest VCC and VCCP voltage levels
by trading off performance for great power savings. This feature is only offered for selected fast speed
grade devices with the power option 'M'. When supplying the lowest voltage level, these Arria 10 devices
operate at a performance level similar to a –3 speed grade device to achieve lower total power. When
supplying the nominal voltage level, Arria 10 devices operate at the fastest speed grade (–1 speed grade)
and consume lower static power similar to the low static power device grades feature.
Arria 10 devices need to be powered up and configured at nominal voltage level. Upon entering user
mode, the Arria 10 device can operate at the lowest voltage level. The scrubbing, EDCRC, and partial
reconfiguration features are not supported unless the device is operating at nominal voltage.
The VCC PowerManager feature in Arria 10 devices supports the following voltage levels:
• Nominal voltage level for VCC and VCCP power supplies—0.9 V.
• Lowest voltage level for VCC and VCCP power supplies—0.83 V.
Programmable Power Technology
Arria 10 devices offer the ability to configure portions of the core, called tiles, for high-speed or lowpower mode of operation. This configuration is performed by the Quartus Prime software automatically
and without the need for user intervention. Setting a tile to high-speed or low-power mode is
accomplished with on-chip circuitry and does not require extra power supplies. In a design compilation,
the Quartus Prime software determines whether a tile should be in high-speed or low-power mode based
on the timing constraints of the design.
Arria 10 tiles consist of the following:
• Memory logic array block (MLAB)/ logic array block (LAB) pairs with routing to the pair
• MLAB/LAB pairs with routing to the pair and to adjacent digital signal processing (DSP)/ memory
block routing
• TriMatrix memory blocks
• DSP blocks
All blocks and routing associated with the tile share the same setting of either high-speed or low-power
mode. By default, tiles that include DSP blocks or memory blocks are set to high-speed mode for
optimum performance. Unused DSP blocks and memory blocks are set to low-power mode to minimize
static power. Unused M20K blocks are set to sleep mode by disabling VCCERAM to reduce static power.
Clock networks do not support programmable power technology.
With programmable power technology, faster speed grade FPGAs may require less static power compared
with FPGA devices without programmable power technology. For device with programmable power
technology, critical path is a small portion of the design. Therefore, there are fewer high-speed MLAB and
LAB pairs in high-speed mode. For device without programmable power technology, the whole FPGA has
to be over designed to meet the timing at critical path.
The Quartus Prime software sets unused device resources in the design to low-power mode to reduce the
static power. It also sets the following resources to low-power mode when they are not used in the design:
• LABs and MLABs
• TriMatrix memory blocks
• DSP blocks
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Low Static Power Device Grades
If a phase-locked loop (PLL) is instantiated in the design, you may assert the areset pin high to keep the
PLL in low-power mode.
Table 10-1: Programmable Power Capabilities for Arria 10 Devices
This table lists the available Arria 10 programmable power capabilities. Speed grade considerations can add to the
permutations to give you flexibility in designing your system.
Feature
Programmable Power Technology
LAB
Yes
Routing
Yes
Memory Blocks
Fixed setting (35)
DSP Blocks
Fixed setting (35)
Clock Networks
No
Related Information
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides more information about the required voltage levels for each power rail.
Low Static Power Device Grades
Altera offers some Arria 10 device grades that consume lower static power than standard power devices
while maintaining performance. The low static power device grades feature is only offered for selected
devices with the power option 'L'.
Related Information
Arria 10 Device Variants and Packages
Provides more information about the ordering code.
SmartVID and VCC PowerManager Features Implementation
The implementation of the SmartVID and VCC PowerManager features are identical. Both features
consist of 7-bit VID that are programmed into a fuse block during device manufacturing.
The 7-bit VID represents a voltage level in the range of 0.83 V to 0.9 V. Each device has its own specific 7bit VID. You can read the 7-bit VID using the Altera-provided IP core. You have the option to enable or
disable the VID bit reading.
The 7-bit VID is read from the fuse block and sent to the external regulator or system power controller
through the Altera-supported interface. Upon receiving the 7-bit VID value, an adjustable regulator tunes
down the VCC and VCCP voltage levels to a lower voltage as specified by the 7-bit VID. Multiple interface
methods are supported for the Arria 10 device to communicate the VID value to an external regulator or
system power controller. The first method to be available is the 7-bit parallel interface.
Altera offers external regulators and system power controllers that support the SmartVID feature and are
compatible with the multiple interfaces methods utilized by the Arria 10 device.
(35)
Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By
default, unused DSP blocks and memory blocks are set to low-power mode.
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SmartVID and VCC PowerManager Features Implementation
10-5
The 7-Bit Parallel Interface Solution
The 7-bit parallel solution is a parallel VID bit interface that is supported by Altera. This interface requires
seven I/O pins for seven parallel VID bits and one pin for the VID_EN to communicate with the external
regulator.
Altera recommends you to use the RZQ_2A pin for the VID_EN function. If bank 2A is used for DDR
interface, and the RZQ_2A pin must be used for calibration purpose, you can use other available generalpurpose I/O pins for the VID_EN pin function. Before the VID_EN pin is asserted, you need to ensure the
I/O bank that hosts the VID_EN pin and VID pins are powered up. Connect the VID_EN pin to a 1-kΩ pulldown resistor.
The VID pins need to be tri-stated during power-up and before the VID_EN pin is asserted. Altera
recommends using a level shifter to isolate the VID signals and voltage regulator controller. This is because
some of the VID bit settings may exceed the maximum VCC and VCCP values.
Figure 10-2: External Interface Connection for the 7-Bit Parallel Solution
7-bit parallel VID
IP Core
Regulator
VCC and VCCP
power supplies
RZQ_2A pin
Fuse
FPGA
The following table lists the regulator requirement to meet the Altera SmartVID and VCC PowerManager
solution.
Table 10-2: Regulator Requirement for Altera SmartVID and VCC PowerManager Solution
Specification
Voltage range
Voltage step
VCC power supply
VID input
Nominal voltage
(36)
(37)
Value
0.80 V – 0.93 V (36)
10 mV step
10 W – 100 W
7-bit VID
0.83 V – 0.9 V (37)
Ramp time
0.5 mV/us
VID_EN pin
1
This voltage range is the output of the regulator to the Arria 10 device, inclusive of tolerance.
The nominal device power-up voltage is 0.9 V.
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Power Sense Line
Power Sense Line
Arria 10 devices support the power sense line feature. VCCLSENSE and GNDSENSE pins are differential
remote sense pins to monitor the VCC power supply.
Altera recommends connecting the VCCLSENSE and GNDSENSE pins for regulators that support the power
sense line feature. The following lists the required conditions to connect VCCLSENSE and GNDSENSE lines to
the regulator's remote sense inputs:
• The VCC or VCCP current is > 30A.
• The SmartVID or VCC PowerManager features are used.
Voltage Sensor
Arria 10 supports an on-chip voltage sensor. The voltage sensor provides a 6-bit digital representation of
the analog signal being observed. The voltage sensor monitors two external differential inputs and six
internal power supplies as shown in the following figure. To get the ADC input, the VCCPT voltage value is
divided by two. To get the actual VCCPT voltage value, multiply the ADC output by two.
Figure 10-3: Voltage Sensor
Two External
Differential
Inputs
Six Internal
Power
Supplies
VSIGP_0
VSIGN_0
VSIGP_1
VSIGN_1
V CC
V CCP
V CCPT
V CCERAM
V CCL_HPS
ADCGND
V REFP_ADC
6-Bit ADC
500 ksps
6-Bit Output
Channel
Status
Register
FPGA Core
V REFN_ADC
ADCGND
Note: The IP core will only be available in the future release of the Quartus Prime software.
The conversion speed of the ADC is 500 ksps cumulative. When multiple channels are used, the speed per
channel is reduced accordingly.
Note: VREFP_ADC pins consume very little current, most of the current drawn is attributed to the leakage
current, which is less than 10 µA. For VREFN_ADC pins, the current is less than 0.1 mA.
For better ADC performance, tie VREFP_ADC and VREFN_ADC pins to an external 1.25 V accurate reference
source (±0.2%). An on-chip reference source (±10%) is activated by connecting the VREFP_ADC pin to GND.
Treat VREFN_ADC as an analog signal together with the VREFP_ADC signal provides a differential 1.25 V
voltage.
Connect both VREFP_ADC and VREFN_ADC pins to GND if no external reference is supplied.
Related Information
• Altera Voltage Sensor IP Core User Guide
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Input Signal Range for External Analog Signal
• myAltera Support
For more information about the voltage sensor transfer function for the unipolar mode, contact
myAltera Support.
Input Signal Range for External Analog Signal
You can configure the ADC to measure unipolar analog external input signal.
Unipolar Input Mode
In unipolar input mode, the voltage on the VSIGP pin which is measured with respect to the VSIGN pin
must always be positive. The VSIGP input must always be driven by an external analog signal. The VSIGN
pin is connected to a local ground or common mode signal.
Using Voltage Sensor in Arria 10 Devices
You can use the voltage sensor feature to monitor critical on-chip power supplies and external analog
voltage. The voltage sensor block for Arria 10 devices supports access from the FPGA core. The following
sections describe the flow in using the voltage sensor for Arria 10 devices.
Figure 10-4: Voltage Sensor Components
confin
clk
Configuration
Register
ch_sel[3:0]
corectl
reset
clk
Signals from
Control Block
Logic
CONV_BEGIN
Internal ADCCLK
2 External
Inputs
6 Internal
Power Supplies
V sigp/n_0
V sigp/n_1
VCC
VCCP
VCCPT
VCCERAM
VCCHPS
ADCGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Multiplexer
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eos
State Machine
6 Bits
500 KSPS
ADC
Register Address
eoc
6 Bits Output
Result0
Result1
Result2
Result3
Result4
Result5
Result6
Result7
ch_sel[3:0]
dataout[5:0]
Multiplexer
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Accessing the Voltage Sensor Using FPGA Core Access
Accessing the Voltage Sensor Using FPGA Core Access
During user mode, you can implement a soft IP to access the voltage sensor block. To access the voltage
sensor block from the core fabric, you need to include the following WYSIWYG atom in your Quartus
Prime project:
Example 10-1: WYSIWYG Atom to Access the Voltage Sensor Block
twentynm_vsblock<name>
(
.clk (<input>, clock signal from core),
.reset(<input>, reset signal from core),
.corectl(<input>, core enable signal from core),
.coreconfig(<input>, config signal from core),
.confin(<input>, config data signal from core),
.chsel(<input>, 4 bits channel selection signal from core),
.eoc(<output>, end of conversion signal from vsblock),
.eos(<output>, end of sequence signal from vsblock),
.dataout(<output>, 6 bits data out of vsblock)
);
Table 10-3: Description for the Voltage Sensor Block WYSIWYG
Port Name
Type
clk
Input
Clock signal from the core. The voltage sensor
supports up to 20-MHz clock.
reset
Input
Active high reset signal. The reset signal has to
asynchronously transition from high-to-low for the
voltage sensor to start conversion. All registers are
cleared and the internal voltage sensor clock is gated
off when the reset signal is high.
corectl
Input
Active high signal. "1" indicates the voltage sensor is
enabled for core access. "0" indicates the voltage
sensor is disabled for core access.
coreconfig
Input
Serial configuration signal. Active high.
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Configuration Registers for the Core Access Mode
Port Name
Type
confin
Input
Serial input data from the core to configure the
configuration register. The configuration register for
the core access mode is 8-bit wide. LSB is the first bit
shifted in.
chsel[3:0]
Input
4-bit channel address. Specifying the channel to be
converted.
eoc
Output
Indicates the end of the conversion. This signal is
asserted after the conversion of each channel data.
eos
Output
Indicates the end of sequence. This signal is asserted
after the completion of the conversion in one cycle of
the selected sequence.
dataout[5:0]
Output
6-bit output data.
10-9
Description
Configuration Registers for the Core Access Mode
The core access configuration register is an 8-bit register.
Figure 10-5: Core Access Configuration Register
D7
D6
D5
D4
D3
D2
D1
D0
NA
CAL
NA
NA
BU1
BU0
MD1
MD0
Table 10-4: Description for the Core Access Configuration Register
Bit Number
Bit Name
D0
MD0
D1
MD1
Description
Mode select for channel sequencer:
• MD[1:0]=2'b00—channel sequencer cycles from
channel 2 to channel 7
• MD[1:0]=2'b01—channel sequencer cycles from
channel 0 to channel 7
• MD[1:0]=2'b10—channel sequencer cycles from
channel 0 to channel 1
• MD[1:0]=2'b11—controlled by IP core. Specify
the channel to be converted on chsel[3:0].
D2
BU0
Bipolar or unipolar selection for channel 0—"0"
indicates unipolar selection, "1" indicates bipolar
selection.
D3
BU1
Bipolar or unipolar selection for channel 1—"0"
indicates unipolar selection, "1" indicates bipolar
selection.
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Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is...
Bit Number
Bit Name
Description
D4
NA
Reserved. Set to "0".
D5
NA
Reserved. Set to "0".
D6
CAL
Calibration enable bit. "0" indicates calibration is
off, "1" indicates calibration is on. The calibration
result is not included in the final 12-bit converted
data when calibration is off.
D7
NA
Reserved. Set to "0".
Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11
The following timing diagram shows the requirement of the IP core to access the voltage sensor in the
core access mode when MD[1:0] is not equal to 2'b11.
Figure 10-6: Timing Diagram when MD[1:0] is not Equal to 2'b11
clk
corectl
Minimum 2 Clock Pulse
reset
Minimum 2 Clock Pulse
22 Cycles
coreconfig
confin
22 Cycles
22 Cycles
Core Sample Data
Core Sample Data
Configuration Data (8 bit)
eos
eoc
dataout[5:0]
Core Sample Data
Previous Data
First Converted Data
1
2
3
4
5
Second Converted Data
6
Last Converted Data
7
1. Low-to-high transition for the corectl signal enables the core access mode.
a. Wait for a minimum of two clock pulses before proceeding to step 2.
2. De-asserting the reset signal releases the voltage sensor from the reset state.
a. Wait for a minimum two clock pulses before proceeding to step 3.
3. Configure the voltage sensor by writing into the configuration registers and asserting the coreconfig
signal for eight clock cycles. The configuration register for the core access mode is 8-bit wide and
configuration data is shifted in serially into the configuration register.
4. The coreconfig signal going low indicates the start of the conversion based on the configuration
defined in the configuration register.
5. Poll the eoc and eos status signals to check if conversion for the first channel defined by MD[1:0] is
completed. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
6. Poll the eoc and eos status signals to check if conversion for the subsequent channels defined by
MD[1:0] are completed. Latch the output data on the dataout[5:0] signal at the falling edge of the
eoc signal.
7. Repeat step 6 until the eos signal is asserted, indicating the completion of the conversion of one cycle
on the channels specified by MD[1:0].
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10-11
a. Both the eoc and eos signals are asserted on the same clock cycle when the voltage sensor
completes the conversion for the last channel.
b. To interrupt the operation of the voltage sensor by writing into the configuration register can only
be done after one cycle of the eos signal is over.
8. When is sequence is completed, and if the corectl and reset signals remain unchanged, the
conversion will repeat the same sequence again until corectl is 0 and reset is 1. If you want to
measure other sequence, repeat step 2 to step 7.
Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
The following timing diagram shows the requirement of the IP core to access the voltage sensor in the
core access mode when MD[1:0] is equal to 2'b11.
Figure 10-7: Timing Diagram when MD[1:0] is Equal to 2'b11
clk
corectl
Minimum 2 Clock Pulse
Minimum 2 Clock Pulse
reset
22 Cycles
coreconfig
confin
22 Cycles
22 Cycles
Configuration Data (8 bit)
chsel[3:0]
First chsel
Second chsel
Subsequent chsel
eoc/eos
Core Sample Data
Core Sample Data
Core Sample Data
dataout[5:0]
Converted Data
for First chsel
1
2
3
4
5
6
Converted Data
for Second chsel
7
Converted Data
for Subsequent chsel
8
1. Low-to-high transition for the corectl signal enables the core access mode.
a. Wait for a minimum of two clock pulses before proceeding to step 2.
2. De-asserting the reset signal releases the voltage sensor from the reset state.
a. Wait for a minimum two clock pulses before proceeding to step 3.
3. Configure the voltage sensor by writing into the configuration registers and asserting the coreconfig
signal for eight clock cycles. The configuration register for the core access mode is 8-bit wide and
configuration data is shifted in serially into the configuration register.
4. Specify the channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal needs to
be ready before the coreconfig signal is de-asserted.
5. The coreconfig signal going low indicates the start of the conversion based on the configuration
defined in the configuration register and the chsel[3:0] signal.
6. Specify the next channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal
needs to be ready one cycle before the eoc signal asserts. Poll the eoc and eos status signals to check if
conversion for the first channel defined by the chsel[3:0] signal in step 4 is completed. Latch the
output data on the dataout[5:0] signal at the falling edge of the eoc signal.
7. Repeat step 6 for all the subsequent channels.
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Temperature Sensing Diode
Temperature Sensing Diode
The Arria 10 temperature sensing diode (TSD) uses the characteristics of a PN junction diode to
determine die temperature. Knowing the junction temperature is crucial for thermal management. You
can calculate junction temperature using ambient or case temperature, junction-to-ambient (ja) or
junction-to-case (jc) thermal resistance, and device power consumption. Arria 10 devices monitor its die
temperature with the internal TSD with built-in analog-to-digital converter (ADC) circuitry or the
external TSD with an external temperature sensor. This allows you to control the air flow to the device.
Related Information
Altera Temperature Sensor IP Core User Guide
Internal Temperature Sensing Diode
The Arria 10 device supports an internal TSD with a built-in 10-bit ADC circuitry to monitor die
temperature. The Arria 10 device uses a set of NPN transistors to sense the temperature and generates its
own reference voltage for conversion. The conversion speed of the internal TSD is around 1 ksps.
Figure 10-8: Internal TSD Block Diagram
This power is sourced
from VCCA_PLL
VCCADC
Temperature
Sensor Diode
Using NPN
Transistors
10-Bit ADC
Circuitry
1 ksps
10-Bit Output
Temperature
Data
Registers
FPGA Core
ADCGND
To read the temperature of the die during user mode, assert the CORECTL signal from low to high. Active
high RESET signal is used to reset the registers at any time. The ADC circuitry takes 1,024 clock cycles to
complete one conversion. The EOC signal goes high for one clock cycle indicating completion of the
conversion. The FPGA core reads out the data on the TEMPOUT[9:0] signal at the falling edge of the EOC
signal.
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Transfer Function for Internal TSD
10-13
Figure 10-9: Internal TSD Timing Diagram
1,024 Cycles
ADCCLK
POR
EOC
Previous Data
TEMPOUT[9:0]
Current Data
Core
Samples
Data
RESET
CORECTL
Related Information
• Internal Temperature Sensing Diode Specifications
Provides more information about the Arria 10 internal TSD specification.
• Altera Temperature Sensor IP Core User Guide
Transfer Function for Internal TSD
The following figure shows the transfer function for internal TSD.
Figure 10-10: ADC Transfer Function
576
431
10 Bit
Output
(Dec)
337
-40 -39.4
25
124.4 125
Temperature (° C)
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External Temperature Sensing Diode
You can calculate the temperature from tempout[9:0] value using this formula:
Temperature = {(AxC)÷1024} - B
Where:
• A = 693
• B = 265
• C = decimal value of tempout[9..0]
External Temperature Sensing Diode
The Arria 10 external TSD requires two pins for voltage reference. The following figure shows how to
connect the external TSD with an external temperature sensor device to allow external sensing of the
Arria 10 die temperature.
Figure 10-11: TSD External Pin Connections
External TSD
TEMPDIODEP
External
Temperature
Sensor
FPGA
TEMPDIODEN
The TSD is a very sensitive circuit that can be influenced by noise coupled from other traces on the board
or within the device package itself, depending on your device usage. The interfacing signal from the Arria
10 device to the external temperature sensor is based on millivolts (mV) of difference, as seen at the
external TSD pins. Switching the I/O near the TSD pins can affect the temperature reading. Altera
recommends taking temperature readings during periods of inactivity in the device or use the internal
TSD with built-in ADC circuitry.
The following are board connection guidelines for the TSD external pin connections:
• The maximum trace lengths for the TEMPDIODEP/TEMPDIODEN traces must be less than eight
inches.
• Route both traces in parallel and place them close to each other with grounded guard tracks on each
side.
• Altera recommends 10-mils width and space for both traces.
• Route traces through a minimum number of vias and crossunders to minimize the thermocouple
effects.
• Ensure that the number of vias are the same on both traces.
• Ensure both traces are approximately the same length.
• Avoid coupling with toggling signals (for example, clocks and I/O) by having the GND plane between
the diode traces and the high frequency signals.
• For high-frequency noise filtering, place an external capacitor (close to the external chip) between the
TEMPDIODEP/TEMPDIODEN trace. For Maxim devices, use an external capacitor between 2200 pF
and 3300 pF.
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Power-On Reset Circuitry
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• Place a 0.1 uF bypass capacitor close to the external device.
• You can use the internal TSD with built-in ADC circuitry and external TSD at the same time.
• If you only use internal ADC circuitry, the external TSD pins (TEMPDIODEP/TEMPDIODEN) can be
connected to GND because the external TSD pins are not used.
For details about device specification and connection guidelines, refer to the external temperature sensor
device datasheet from the device manufacturer.
Related Information
• External Temperature Sensing Diode Specifications
Provides details about the external TSD specification.
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides details about the TEMPDIODEP/TEMPDIODEN pin connection when you are not using an
external TSD.
Power-On Reset Circuitry
The POR circuitry keeps the Arria 10 device in the reset state until the power supply outputs are within
the recommended operating range.
A POR event occurs when you power up the Arria 10 device until all power supplies reach the
recommended operating range within the maximum power supply ramp time, tRAMP. If tRAMP is not met,
the Arria 10 device I/O pins and programming registers remain tri-stated, during which device configura‐
tion could fail.
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Power-On Reset Circuitry
Figure 10-12: Relationship Between tRAMP and POR Delay
Volts
POR trip level
first power
supply
last power
supply
Time
POR delay
tRAMP
configuration
time
The Arria 10 POR circuitry uses an individual detecting circuitry to monitor each of the
configuration-related power supplies independently. The main POR circuitry is gated by the outputs of all
the individual detectors. The main POR signal is asserted when the power starts to ramp up. This signal is
released after the last ramp-up power reaches the POR trip level followed by a POR delay. You can select
the fast or standard POR delay time by setting the MSEL pin.
For the configuration via protocol (CvP) configuration scheme, the tRAMP must be less than 10 ms, from
the first power supply ramp-up to the last power supply ramp-up. You must select fast POR to allow
sufficient time for the PCIe link initialization and configuration.
In user mode, the main POR signal is asserted when any of the monitored power supplies go below its
POR trip level. Asserting the POR signal forces the device into the reset state.
The POR circuitry checks the functionality of the I/O level shifters powered by the VCCPT and VCCPGM
power supplies during power-up mode. The main POR circuitry waits for all the individual POR
circuitries to release the POR signal before allowing the control block to start programming the device.
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Power Supplies Monitored and Not Monitored by the POR Circuitry
10-17
Figure 10-13: Simplified POR Diagram for Arria 10 Devices
V CC
V CC POR
V CCBAT
Modular
Main POR
V CCBAT POR
Main POR
V CCPGM
Related Information
• POR Specifications
Provides more information about the POR delay specification.
• MSEL Pin Settings
Provides more information about the MSEL pin settings for each POR delay.
• Recommended Operating Conditions
Provides more information about the power supply ramp time.
Power Supplies Monitored and Not Monitored by the POR Circuitry
Table 10-5: Power Supplies Monitored and Not Monitored by the Arria 10 POR Circuitry
Power Supplies Monitored
•
•
•
•
•
•
•
•
VCCBAT
VCC
VCCIO (38)
VCCERAM
VCCP
VCCPT
VCCPGM
VCCL_HPS(40)(39)
Power Supplies Not Monitored
•
•
•
•
•
•
VCCH_GXB
VCCR_GXB
VCCT_GXB
VCCA_PLL
VCCIO_HPS(40)
VCCPLL_HPS (40)
Note: For the device to exit POR, you must power the VCCBAT power supply even if you do not use the
volatile key.
(38)
(39)
(40)
Only for VCCIO of bank 2A.
VCCL_HPS is a power supply monitored for the HPS block only and does not gate the main POR. If you do
not use the HPS block, connect VCCL_HPS to GND.
These are only supported by system-on-a-chip (SoC) FPGA.
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Power-Up and Power-Down Sequences
Power-Up and Power-Down Sequences
Arria 10 devices require power-up and power-down sequences. The power sequence is divided into three
power groups.
Figure 10-14: Power-Up and Power-Down Sequences Requirement for Arria 10 Devices
Power-Up
Sequence Requirement
Group 1
V CC , V CCP ,
V CCR_GXB ,
V CCT_GXB ,
V CCERAM ,
V CCL_HPS
Group 2
V CCPT ,
V CCH_GXB ,
V CCA_PLL ,
V CCPLL_HPS ,
V CCIOREF_HPS
These are only
supported by
system-on-a-chip
(SoC) FPGA
Group 3
0.81V
Group 1
1.62V
Group 2
V CCPGM ,
V CCIO ,
V CCIO_HPS
Group 3
*Power-down sequence
requirement is the reverse
of the power-up sequence
requirement.
Note: Group 3 can be combined with Group 2 as per condition with the following table.
Note: VCCBAT can be powered up or powered down at any order during the power-up or power-down
sequence.
All power rails must ramp monotonically. Ramp all the power rails to the nominal voltage level within the
tRAMP time as specified in the device datasheet. The power-up sequence must meet either the standard or
fast POR delay time.
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Power Supply Design
10-19
Table 10-6: Power Groups Ramping Sequence
Power Group
Order to
Ramp
Conditions
Group 1
First
• All power rails in Group 1 must ramp to a minimum of 0.81 V before
any other power rails may start.
• VCC, VCCP, and VCCERAM must be tied to the same regulator unless you
are using the SmartVID feature, where VCCERAM must be sourced from
a separate regulator.
• If the VCC and VCCP voltage levels are different from VCCT_GXB,
VCCR_GXB, and/or VCCERAM, ramp VCC and VCCP first to 90% of the
voltage level. Next, ramp VCCT_GXB, VCCR_GXB, and VCCERAM in any
order.
Group 2
Second
• All power rails in Group 2 must ramp to a minimum of 1.62 V before
any other power rails may start.
• Power rails within Group 2 can ramp in any order.
• If VCCIO, VCCPGM, and VCCIO_HPS are 1.8V, sharing the same regulator
as Group 2, VCCIO, VCCPGM, and VCCIO_HPS may ramp together with the
other power rails in Group 2.
Group 3
Third
Power rails within Group 3 can ramp in any order.
The power-down sequence is the reverse of the power-up sequence. When the proper power sequence is
followed, I/O pins are tri-stated during power-up or power-down.
Note: Do not drive I/O pins externally during this power-up and power-down time, or excess I/O pin
current can result in the I/O pin. Excess I/O pin current in 3V I/O pin can lead to the damage of
the device.
During the power-up and power-down sequences, ensure VCCIO – VCCPT < 1.92 V to avoid damage to the
device.
For power-down, ensure that all power rails are powered down within 100 ms from the start of the powerdown sequence.
All power rails in Group 3 must ramp down to 10% of the nominal before any other power rails from
Group 2 can start to ramp down. All power rails in Group 2 must ramp down to 10% of the nominal
before any other power rails from Group 1 can start to ramp down. Power rails in Group 1 can ramp
down in any order.
Power Supply Design
The power supply requirements for Arria 10 devices will vary depending on the static and dynamic power
for each specific use case. Altera’s Enpirion® portfolio of power management solutions, combined with
comprehensive design tools, enable optimized Arria 10 device power supply design. The Enpirion
portfolio includes power management solutions that are compatible with the multiple interface methods
utilized by the Arria 10 device and designed to support Arria 10 power reduction features such as the
SmartVID feature.
Arria 10 devices have multiple input voltage rails that require a regulated power supply in order to
operate. Multiple input rail requirements may be grouped according to system considerations such as
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Document Revision History
voltage requirements, noise sensitivity, and sequencing. The Arria 10 GX, GT, and SX Device Family Pin
Connection Guidelines provides a more detailed recommendation about which input rails may be
grouped. The PowerPlay Early Power Estimators (EPE) tool for Arria 10 devices also seamlessly and
automatically provides input rail power requirements and specific device recommendations based on each
specific Arria 10 use case. Individual input rail voltage and current requirements are summarized on the
“Report” tab while input rail groupings and specific power supply recommendations can be found on the
“Main” and “Enpirion” tabs, respectively.
Related Information
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Provides detailed information about power supply pin connection guidelines and power regulator
sharing.
• PowerPlay Early Power Estimators (EPE) and Power Analyzer
Provides more information about the power supplies and the current requirements for each power rail.
• Altera Power Management PowerSoC Solutions
Provides more information about Altera's Power Management IC and PowerSoC solutions designed
for powering FPGAs.
• Power Delivery Network (PDN) Tool for Arria 10 and MAX 10 Devices
Document Revision History
Date
Version
Changes
December 2015
2015.12.14
• Added a note to VCCIO and VCCL_HPS power rails in the Power
Supplies Monitored and Not Monitored by the Arria 10 POR
Circuitry table.
• Updated the RESET and CORECTL signals of the Internal TSD
Timing Diagram figure.
• Updated the formula for the ADC Transfer Function.
• Updated the supported speed grades devices for the SmartVID
feature.
• Updated the conditions for Group 1 in the Power Groups Ramping
Sequence table.
• Updated the Power-Up and Power-Down Sequences section.
• Updated the Voltage Sensor section.
• Updated the External Temperature Sensing Diode section.
• Removed the Bipolar Input Mode support from the Voltage Sensor
feature.
• Removed the JTAG Access Mode support from the Voltage Sensor
feature.
• Removed the Voltage Sensor Transfer Function section.
November 2015
2015.11.02
• Updated the ADC Transfer Function figure.
• Changed instances of Quartus II to Quartus Prime.
Altera Corporation
Power Management in Arria 10 Devices
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A10-PWR
2015.12.16
Document Revision History
Date
Version
10-21
Changes
June 2015
2015.06.15
• Added a note to describe the current for the VREFP_ADC and VREFN_
ADC pins in the Voltage Sensor section.
• Updated the ADC Transfer Function figure.
May 2015
2015.05.04
• Updated the Power-Up and Power-Down Sequences with require‐
ments for the power-down sequence for each group of power rails.
• Updated the description of the config port in Table 10-4.
• Updated the Transfer Function for Internal TSD section with the
formula to calculate temperature from the tempout[9:0] value.
• Updated the supported parallel VID bit interface to 7 bit in the
SmartVID and VCC PowerManager Features Implementation
section.
• Updated the note to the voltage range of the SmartVID and VCC
PowerManager, in which the range includes tolerance.
• Updated the on-chip reference source to ±10%.
January 2015
2015.01.23
• Updated the Unipolar Input Mode section.
• Updated the on-chip reference source for the VREFP_ADC pin in the
Voltage Sensor section.
• Updated the steps in the Accessing the Voltage Sensor Using JTAG
Access section.
• Updated the description for reset and corectl ports in the
Description for the Voltage Sensor Block WYSIWYG table.
• Updated the Internal Temperature Sensing Diode section on how
to read the temperature of the die during user mode.
• Updated the Timing Diagram when MD[1:0] is not Equal to 2'b11
figure.
• Updated the Timing Diagram when MD[1:0] is Equal to 2'b11
figure.
• Updated the Internal TSD Timing Diagram figure.
August 2014
2014.08.18
• Added the SmartVID and VCC PowerManager Features Implemen‐
tation section.
• Added the Using Voltage Sensor in Arria 10 Devices section.
• Added the Transfer Function for Internal TSD section.
• Added the Power Supply Design section.
• Updated the Dynamic Power Equation section.
• Updated the Power Reduction Techniques section.
• Updated the SmartVID section.
• Updated the Programmable Power Technology section.
• Updated the Voltage Sensor section.
• Updated the Power-Up and Power-Down Sequence section.
December 2013
2013.12.02
Initial release.
Power Management in Arria 10 Devices
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