Silicon Laboratories | SI5325 | Si5325 Data Sheet

Si5325
µ P - P ROGRAMMABLE P RECISION C L O C K M ULTIPLIER
Features





Optical modules
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
Description
CLKOUT1–

CLKOUT1+
SONET/SDH OC-48/STM-16 and
OC-192/STM-64
line cards
 GbE/10GbE, 1/2/4/8/10GFC line
cards
 ITU G.709 and custom FEC line
cards

CMODE
Applications
NC
Pin Assignments
GND

Ordering Information:
See page 56.
NC

I2C or SPI programmable
On-chip voltage regulator for
1.8 ±5%, 2.5 or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead
QFN
Pb-free, ROHS compliant
VDD

Dual clock outputs with
selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and
custom FEC ratios (255/238,
255/237, 255/236)
LOS, FOS alarm outputs
CKOUT2–

Not recommended for new

designs. For alternatives, see the
Si533x family of products.
Generates frequencies from

2 kHz to 945 MHz and select
frequencies to 1.4 GHz from an
input frequency of 10 to 710 MHz 
Low jitter clock outputs with jitter 
generation as low as 0.5 ps rms

(12 kHz–20 MHz)
Integrated loop filter with
selectable loop bandwidth

(150 kHz to 2 MHz)
Dual clock inputs w/manual or

automatically controlled
switching
CKOUT2+

36 35 34 33 32 31 30 29 28
RST
1
27 SDI
NC
2
26 A2_SS
INT_C1B
3
25 A1
C2B
4
VDD
5
GND
6
NC
7
GND
8
20 GND
NC
9
19 GND
24 A0
GND
Pad
23 SDA_SDO
22 SCL
21 CS_CA
Rev. 1.0 9/14
Copyright © 2014 by Silicon Laboratories
NC
CLKIN1–
VDD
CLKIN1+
NC
CLKIN2–
CLKIN2+
VDD
VDD
10 11 12 13 14 15 16 17 18
The Si5325 is a low jitter, precision clock multiplier for applications requiring clock
multiplication without jitter attenuation. The Si5325 accepts dual clock inputs
ranging from 10 to 710 MHz and generates two clock outputs ranging from 2 kHz
to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down
separately from a common source. The device provides frequency translation
combinations across this operating range. The Si5325 input clock frequency and
clock multiplication ratio are programmable through an I2C or SPI interface. The
Si5325 is based on Silicon Laboratories' 3rd-generation DSPLL® technology,
which provides frequency synthesis in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter components. The DSPLL
loop bandwidth is digitally programmable. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5325 is ideal for providing clock multiplication in high
performance timing applications.
Si5325
Si5325
Functional Block Diagram
CKIN1
CKIN2
÷ N31
®
÷ N32
DSPLL
÷ NC1_LS
CKOUT1
÷ NC2_LS
CKOUT2
N1_HS
÷ N2
Alarms
VDD (1.8, 2.5, or 3.3 V)
Control
Signal Detect
GND
I2C/SPI Port
Clock Select
Device Interrupt
2
Rev. 1.0
Si5325
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5. Pin Descriptions: Si5325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8. Land Pattern: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1. Si5325 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Rev. 1.0
3
Si5325
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Ambient Temperature
TA
Supply Voltage during
Normal Operation
VDD
Test Condition
Min
Typ
Max
Unit
–40
25
85
C
3.3 V Nominal
2.97
3.3
3.63
V
2.5 V Nominal
2.25
2.5
2.75
V
1.8 V Nominal
1.71
1.8
1.89
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
SIGNAL +
Differential I/Os VICM , VOCM
V
VISE , VOSE
SIGNAL –
(SIGNAL +) – (SIGNAL –)
Differential Peak-to-Peak Voltage
VID,VOD
VICM, VOCM
Single-Ended
Peak-to-Peak Voltage
t
SIGNAL +
VID = (SIGNAL+) – (SIGNAL–)
SIGNAL –
Figure 1. Differential Voltage Characteristics
80%
CKIN, CKOUT
20%
tF
tR
Figure 2. Rise/Fall Time Characteristics
4
Rev. 1.0
Si5325
Table 2. DC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
IDD
LVPECL Format
622.08 MHz Out
Both CKOUTs Enabled
—
251
279
mA
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
—
217
243
mA
CMOS Format
19.44 MHz Out
Both CKOUTs Enabled
—
204
234
mA
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
—
194
220
mA
Disable Mode
—
165
—
mA
1.8 V ± 5%
0.9
—
1.4
V
2.5 V ± 10%
1
—
1.7
V
3.3 V ± 10%
1.1
—
1.95
V
CKNRIN
Single-ended
20
40
60
k
Single-Ended Input
Voltage Swing
(See Absolute Specs)
VISE
fCKIN < 212.5 MHz
See Figure 1.
0.2
—
—
VPP
fCKIN > 212.5 MHz
See Figure 1.
0.25
—
—
VPP
Differential Input
Voltage Swing
(See Absolute Specs)
VID
fCKIN < 212.5 MHz
See Figure 1.
0.2
—
—
VPP
fCKIN > 212.5 MHz
See Figure 1.
0.25
—
—
VPP
Supply Current1
CKINn Input Pins2
Input Common Mode
Voltage (Input Threshold Voltage)
Input Resistance
VICM
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
5
Si5325
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CKOVCM
LVPECL 100  load
line-to-line
VDD –1.42
—
VDD –1.25
V
Differential Output
Swing5
CKOVD
LVPECL 100  load lineto-line
1.1
—
1.9
VPP
Single-Ended Output
Swing5
CKOVSE
LVPECL 100  load lineto-line
0.5
—
0.93
VPP
Differential Output
Voltage
CKOVD
CML 100  load line-toline
350
425
500
mVPP
CKOVCM
CML 100  load line-toline
—
VDD-0.36
—
V
CKOVD
LVDS
100  load line-to-line
500
700
900
mVPP
Low Swing LVDS
100  load line-to-line
350
425
500
mVPP
CKOVCM
LVDS 100 load line-toline
1.125
1.2
1.275
V
CKORD
CML, LVPECL, LVDS
—
200
—

Output Voltage Low
CKOVOLLH
CMOS
—
—
0.4
V
Output Voltage High
CKOVOHLH
VDD = 1.71 V
CMOS
0.8 x VDD
—
—
V
Output Clocks (CKOUTn)3
Common Mode
Common Mode Output
Voltage
Differential Output
Voltage
Common Mode Output
Voltage
Differential Output
Resistance
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6
Rev. 1.0
Si5325
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Output Drive Current
(CMOS driving into
CKOVOL for output low
or CKOVOH for output
high. CKOUT+ and
CKOUT– shorted
externally)
Symbol
Test Condition
Min
Typ
Max
Unit
CKOIO
ICMOS[1:0] =11
VDD = 1.8 V
—
7.5
—
mA
ICMOS[1:0] =10
VDD = 1.8 V
—
5.5
—
mA
ICMOS[1:0] =01
VDD = 1.8 V
—
3.5
—
mA
ICMOS[1:0] =00
VDD = 1.8 V
—
1.75
—
mA
ICMOS[1:0] =11
VDD = 3.3 V
—
32
—
mA
ICMOS[1:0] =10
VDD = 3.3 V
—
24
—
mA
ICMOS[1:0] =01
VDD = 3.3 V
—
16
—
mA
ICMOS[1:0] =00
VDD = 3.3 V
—
8
—
mA
VDD = 1.71 V
—
—
0.5
V
VDD = 2.25 V
—
—
0.7
V
VDD = 2.97 V
—
—
0.8
V
VDD = 1.89 V
1.4
—
—
V
VDD = 2.25 V
1.8
—
—
V
VDD = 3.63 V
2.5
—
—
V
2-Level LVCMOS Input Pins
Input Voltage Low
Input Voltage High
VIL
VIH
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
7
Si5325
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3-Level Input Pins4
Input Voltage Low
VILL
—
—
0.15 x VDD
V
Input Voltage Mid
VIMM
0.45 x VDD
—
0.55 x VDD
V
Input Voltage High
VIHH
0.85 x VDD
—
—
V
Input Low Current
IILL
See Note 4
–20
—
—
µA
Input Mid Current
IIMM
See Note 4
–2
—
+2
µA
Input High Current
IIHH
See Note 4
—
—
20
µA
VOL
IO = 2 mA
VDD = 1.71 V
—
—
0.4
V
IO = 2 mA
VDD = 2.97 V
—
—
0.4
V
IO = –2 mA
VDD = 1.71 V
VDD – 0.4
—
—
V
IO = –2 mA
VDD = 2.97 V
VDD – 0.4
—
—
V
RSTb = 0
–100
—
100
µA
LVCMOS Output Pins
Output Voltage Low
Output Voltage Low
Output Voltage High
VOH
Output Voltage High
Disabled Leakage
Current
IOZ
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
8
Rev. 1.0
Si5325
Table 3. AC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10
—
710
MHz
40
—
60
%
2
—
—
ns
—
—
3
pF
—
—
11
ns
N1  6
0.002
—
945
MHz
N1 = 5
970
—
1134
MHz
N1 = 4
1.213
—
1.4
GHz
—
—
212.5
MHz
CKINn Input Pins
Input Frequency
CKNF
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC
Input Capacitance
CKNCIN
Input Rise/Fall Time
CKNTRF
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
20–80%
See Figure 2
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not configured for CMOS or
Disabled)
Maximum Output
Frequency in CMOS
Format
CKOF
CKOF
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKOTRF
Output not configured for
CMOS or Disabled
See Figure 2
—
230
350
ps
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD = 1.71
CLOAD = 5 pF
—
—
8
ns
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD = 2.97
CLOAD = 5 pF
—
—
2
ns
Output Duty Cycle
Uncertainty @
622.08 MHz
CKODC
100  Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
—
—
+/-40
ps
Rev. 1.0
9
Si5325
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LVCMOS Input Pins
Minimum Reset Pulse
Width
tRSTMN
1
—
—
µs
Reset to Microprocessor Access Ready
tREADY
—
—
10
ms
Cin
—
—
3
pF
Input Capacitance
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD = 20 pF
See Figure 2
—
25
—
ns
LOSn Trigger Window
LOSTRIG
From last CKINn to 
Internal detection of LOSn
N3 ≠ 1
—
—
4.5 x N3
TCKIN
Time to Clear LOL
after LOS Cleared
tCLRLOL
LOS to LOL
Fold = Fnew
Stable Xa/XB reference
—
10
—
ms
Output Clock Skew
tSKEW
 of CKOUTn to  of
CKOUT_m, CKOUTn
and CKOUT_m at same
frequency and signal
format
PHASEOFFSET = 0
CKOUT_ALWAYS_ON = 1
SQ_ICAL = 1
—
—
100
ps
Phase Change due to
Temperature Variation
tTEMP
Max phase changes from
–40 to +85 °C
—
300
500
ps
Device Skew
10
Rev. 1.0
Si5325
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
35
1200
ms
—
0.05
0.1
dB
Jitter Frequency Loop
Bandwidth
5000/BW
—
—
ns pk-pk
1 kHz Offset
—
–90
—
dBc/Hz
10 kHz Offset
—
–113
—
dBc/Hz
100 kHz Offset
—
–118
—
dBc/Hz
1 MHz Offset
—
–132
—
dBc/Hz
PLL Performance
(fin = fout = 622.08 MHz; BW = 120 Hz; LVPECL)
Lock Time
tLOCKMP
Closed Loop Jitter
Peaking
JPK
Jitter Tolerance
JTOL
Phase Noise
fout = 622.08 MHz
CKOPN
Start of ICAL to of LOL
Subharmonic Noise
SPSUBH
Phase Noise @ 100 kHz
Offset
—
–88
—
dBc
Spurious Noise
SPSPUR
Max spur @ n x F3
(n  1, n x F3 < 100 MHz)
—
–93
—
dBc
Table 4. Microprocessor Control
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
I2C Bus Lines (SDA, SCL)
Input Voltage Low
VILI2C
—
—
0.25 x VDD
V
Input Voltage High
VIHI2C
0.7 x VDD
—
VDD
V
VDD = 1.8V
0.1 x VDD
—
—
V
VDD = 2.5 or 3.3 V
0.05 x VDD
—
—
V
VDD = 1.8 V
IO = 3 mA
—
—
0.2 x VDD
V
VDD = 2.5 or 3.3 V
IO = 3 mA
—
—
0.4
V
Hysteresis of Schmitt
trigger inputs
Output Voltage Low
VHYSI2C
VOLI2C
Rev. 1.0
11
Si5325
Table 4. Microprocessor Control (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Duty Cycle, SCLK
tDC
SCLK = 10 MHz
40
—
60
%
Cycle Time, SCLK
tc
100
—
—
ns
Rise Time, SCLK
tr
20–80%
—
—
25
ns
Fall Time, SCLK
tf
20–80%
—
—
25
ns
Low Time, SCLK
tlsc
20–20%
30
—
—
ns
High Time, SCLK
thsc
80–80%
30
—
—
ns
Delay Time, SCLK Fall
to SDO Active
td1
—
—
25
ns
Delay Time, SCLK Fall
to SDO Transition
td2
—
—
25
ns
Delay Time, SS Rise to
SDO Tri-state
td3
—
—
25
ns
Setup Time, SS to
SCLK Fall
tsu1
25
—
—
ns
Hold Time, SS to
SCLK Rise
th1
20
—
—
ns
Setup Time, SDI to
SCLK Rise
tsu2
25
—
—
ns
Hold Time, SDI to
SCLK Rise
th2
20
—
—
ns
Delay Time between
Slave Selects
tcs
25
—
—
ns
SPI Specifications
12
Rev. 1.0
Si5325
Table 5. Jitter Generation
Symbol
Parameter
Min
Typ
Max
Unit
0.02–80 MHz
—
.49
—
psrms
4–80 MHz
—
.23
—
psrms
0.05–80 MHz
—
.47
—
ps rms
0.12–20 MHz
—
.48
—
ps rms
Test Condition*
Measurement Filter
Jitter Gen
OC-192
JGEN
Jitter Gen
OC-48
JGEN
*Note: Test conditions:
1. fIN = fOUT = 622.08 MHz
2.
Clock input: LVPECL
3.
Clock output: LVPECL
4.
PLL bandwidth: 877 kHz
5.
VDD = 2.5 V
6.
TA = 85 °C
Table 6. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
JA
Still Air
32
C°/W
Thermal Resistance Junction to Case
JC
Still Air
14
C°/W
Table 7. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 3.8
V
LVCMOS Input Voltage
VDIG
–0.3 to (VDD + 0.3)
V
CKINn Voltage Level Limits
CKNVIN
0 to VDD
V
XA/XB Voltage Level Limits
XAVIN
0 to 1.2
V
Operating Junction Temperature
TJCT
–55 to 150
C
Storage Temperature Range
TSTG
–55 to 150
C
2
kV
ESD MM Tolerance; All pins except CKIN+/CKIN–
150
V
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
750
V
ESD MM Tolerance; CKIN+/CKIN–
100
V
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except
CKIN+/CKIN–
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Rev. 1.0
13
Si5325
622 MHz In, 622 MHz Out BW=877 kHz
Phase Noise (dBc/H
-50
-70
-90
-110
-130
-150
-170
1000
10000
100000
1000000
10000000
Offset Frequency (Hz)
Figure 3. Typical Phase Noise Plot
Table 8. Typical RMS Jitter Values
14
Jitter Bandwidth
RMS Jitter (fs)
OC-48, 12 kHz to 20 MHz
374
OC-192, 20 kHz to 80 MHz
388
OC-192, 4 MHz to 80 MHz
181
OC-192, 50 kHz to 80 MHz
377
Broadband, 800 Hz to 80 MHz
420
Rev. 1.0
100000000
Si5325
C4 1 µF
System
Power
Supply
C3 0.1 µF
Ferrite
Bead
C2 0.1 µF
VDD = 3.3 V
VDD
130 
CKIN1+
GND
130 
C1 0.1 µF
CKOUT1+
0.1 µF
+
100 
CKOUT1–
CKIN1–
82 
–
Clock Outputs
CKOUT2+
Input
Clock
Sources*
0.1 µF
82 
+
100 
VDD = 3.3 V
130 
0.1 µF
CKOUT2–
0.1 µF
–
130 
CKIN2+
Si5325
CKIN2–
82 
INT_C1B
82 
Interrupt/CKIN_1 Invalid Indicator
C2B
CMODE
Control Mode (L)
A[2:0]
RST
Reset
CKIN_2 Invalid Indicator
Serial Port Address
SDA
Serial Data
SCL
Serial Clock
I2C Interface
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 4. Si5325 Typical Application Circuit (I2C Control Mode)
C4 1 µF
System
Power
Supply
C3 0.1 µF
Ferrite
Bead
C2 0.1 µF
VDD = 3.3 V
CKIN1+
GND
130 
VDD
130 
C1 0.1 µF
CKOUT1–
Reset
0.1 µF
+
0.1 µF
–
130 
CKIN2–
Control Mode (H)
–
100 
CKOUT2–
CKIN2+
82 
0.1 µF
Clock Outputs
VDD = 3.3 V
130 
+
82 
CKOUT2+
Input
Clock
Sources*
0.1 µF
100 
CKIN1–
82 
CKOUT1+
Si5325
INT_C1B
C2B
Interrupt/CLKIN_1 Invalid Indicator
CLKIN_2 Invalid Indicator
82 
SS
CMODE
SDO
RST
SDI
SCLK
Slave Select
Serial Data Out
SPI Interface
Serial Data In
Serial Clock
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 5. Si5325 Typical Application Circuit (SPI Control Mode)
Rev. 1.0
15
Si5325
2. Functional Description
2.1. Further Documentation
The Si5325 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs
ranging from 10 to 710 MHz and generates two
synchronous clock outputs ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The device
provides frequency translation across this operating
range. Independent dividers are available for each input
clock and output clock, so the Si5325 can accept input
clocks at different frequencies and it can generate
output clocks at different frequencies. The Si5325 input
clock frequency and clock multiplication ratio are
programmable through an I2C or SPI interface. Silicon
Laboratories offers a PC-based software utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from http://www.silabs.com/timing (click on
Documentation).
Consult the Silicon Laboratories Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5325. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
The Si5325 is based on Silicon Laboratories' thirdgeneration DSPLL® technology, which provides
frequency synthesis in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The Si5325 PLL loop bandwidth is
digitally programmable and supports a range from
150 kHz to 1.3 MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5325 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
For system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
16
Rev. 1.0
Si5325
3. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, such as Register 64, should never be written to.
Register
D7
D6
D5
0
D4
D3
D2
D1
CKOUT_ALWAYS_ON
BYPASS_REG
1
CK_PRIOR2[1:0]
2
CK_PRIOR[1:0]
BWSEL_REG[3:0]
3
CKSEL_REG[1:0]
4
AUTOSEL_REG[1:0]
5
ICMOS[1:0]
SQ_ICAL
6
SFOUT2_REG[2:0}
SFOUT1_REG[2:0]
7
8
FOSREFSEL[2:0]
HLOG_2[1:0]
HLOG_1[1:0]
10
DSBL2_ REG
DSBL1_ REG
11
19
D0
PD_CK2
FOS_EN
FOS_THR[1:0]
VALTIME[1:0]
20
CK2_BAD_PIN
CK1_ BAD_ PIN
21
INT_PIN
CK1_ACTV_PIN
22
CK_ACTV_ POL
CK_BAD_ POL
LOS2_MSK
LOS1_MSK
24
FOS2_MSK
FOS1_MSK
N1_HS[2:0]
31
NC1_LS[19:16]
32
NC1_LS[15:8]
33
NC1_LS[7:0]
34
NC2_LS[19:16]
35
NC2_LS[15:8]
36
NC2_LS[7:0]
40
N2_LS[19:16]
41
N2_LS[15:8]
42
N2_LS[7:0]
43
N31[18:16]
44
N31[15:8]
45
N31[7:0]
46
N32[18:16]
47
N32[15:8]
48
N32[7:0]
55
CKSEL_PIN
INT_POL
23
25
PD_CK1
CLKIN2RATE[2:0]
128
CLKIN1RATE[2:0]
CK2_ACTV_REG
Rev. 1.0
CK1_ACTV_REG
17
Si5325
Register
D7
D6
D5
D4
D2
D1
129
LOS2_INT
LOS1_INT
130
FOS2_INT
FOS1_INT
131
LOS2_FLG
LOS1_FLG
132
D3
FOS2_FLG
134
D0
FOS1_FLG
PARTNUM_RO[11:4]
135
PARTNUM_RO[3:0]
136
RST_REG
REVID_RO[3:0]
ICAL
138
139
LOS2_EN[0:0]
LOS1_EN[0:0]
142
INDEPENDENTSKEW1[7:0]
143
INDEPENDENTSKEW2[7:0]
18
Rev. 1.0
LOS2_EN [1:1]
LOS1_EN [1:1]
FOS2_EN
FOS1_EN
Si5325
4. Register Descriptions
Register 0.
Bit
D7
D6
D4
D3
D2
CKOUT_ALWAYS_ON
Name
Type
D5
R
R
R/W
D1
D0
BYPASS_REG
R
R
R
R/W
R
Reset value = 0001 0100
Bit
Name
7:6
Reserved
5
Function
CKOUT_ALWAYS_ON CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on and ICAL is not complete or successful. See Table 9 on page 51.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output. Note: The frequency may be significantly off until the
part is calibrated.
4:2
Reserved
1
BYPASS_REG
0
Reserved
Bypass Register.
This bit enables or disables the PLL bypass mode. Use only when the device
is in VCO freeze or before the first ICAL. Bypass mode is not supported for
CMOS output clocks.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers,
bypassing PLL. Bypass mode is not supported for CMOS outputs.
Rev. 1.0
19
Si5325
Register 1.
Bit
D7
D6
D5
D4
D3
Name
R
Type
R
R
D2
D1
D0
CK_PRIOR2 [1:0]
CK_PRIOR1 [1:0]
R/W
R/W
R
Reset value = 1110 0100
Bit
Name
Function
7:4
Reserved
3:2
CK_PRIOR2 [1:0]
CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state
machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: Reserved
11: Reserved
1:0
CK_PRIOR1 [1:0]
CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state
machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: Reserved
11: Reserved
Register 2.
Bit
D7
D6
D5
Name
BWSEL_REG [3:0]
Type
R/W
D4
D3
D2
D1
D0
R
R
R
R
Reset value = 0100 0010
Bit
7:4
3:0
20
Name
Function
BWSEL_REG [3:0] BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to take
effect.
Reserved
Rev. 1.0
Si5325
Register 3.
Bit
D7
D6
D5
Name
CKSEL_REG [1:0]
Type
R/W
D4
D3
D2
D1
D0
R
R
R
R
SQ_ICAL
R
R/W
Reset value = 0000 0101
Bit
7:6
Name
Function
CKSEL_REG [1:0] CKSEL_REG.
If the device is operating in register-based manual clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input
clock will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00,
the CS_CA input pin continues to control clock selection and CKSEL_REG is of no
consequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: Reserved
11: Reserved
5
Reserved
4
SQ_ICAL
3:0
Reserved
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. See Table 9 on page 51.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
Rev. 1.0
21
Si5325
Register 4.
Bit
D7
D6
Name
AUTOSEL_REG [1:0]
Type
R/W
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
Reset value = 0001 0010
Bit
7:6
Name
Function
AUTOSEL_REG [1:0] AUTOSEL_REG [1:0].
Selects method of input clock selection to be used.
00: Manual (either register or pin controlled, see CKSEL_PIN)
01: Automatic Non-Revertive
10: Automatic Revertive
11: Reserved
5:0
Reserved
Register 5.
Bit
D7
D6
Name
ICMOS [1:0]
Type
R/W
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
Reset value = 1110 1101
22
Bit
Name
Function
7:6
ICMOS [1:0]
ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buffer drive
strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation.
These values assume CKOUT+ is tied to CKOUT-.
00: 8 mA/2 mA.
01: 16 mA/4 mA
10: 24 mA/6 mA
11: 32 mA/8 mA
5:0
Reserved
Rev. 1.0
Si5325
Register 6.
Bit
D7
D6
Name
Type
R
R
D5
D4
D3
D2
D1
SFOUT2_REG [2:0]
SFOUT1_REG [2:0]
R/W
R/W
D0
Reset value = 0010 1101
Bit
Name
Function
7:6
Reserved
5:3
SFOUT2_REG [2:0]
SFOUT2_REG [2:0].
Controls output signal format and disable for CKOUT2 output buffer. Bypass
mode is not supported for CMOS output clocks.
000: Reserved
001: Disable
010: CMOS (Bypass mode is not supported for CMOS outputs)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0
SFOUT1_REG [2:0]
SFOUT1_REG [2:0].
Controls output signal format and disable for CKOUT1 output buffer. Bypass
mode is not supported for CMOS output clocks.
000: Reserved
001: Disable
010: CMOS (Bypass mode is not supported for CMOS outputs)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Rev. 1.0
23
Si5325
Register 7.
Bit
D7
D6
D5
D4
D3
D1
D0
FOSREFSEL [2:0]
Name
Type
D2
R
R
R
R
R
R/W
Reset value = 0010 1010
24
Bit
Name
7:3
Reserved
2:0
FOSREFSEL [2:0]
Function
FOSREFSEL [2:0].
Selects which input clock is used as the reference frequency for Frequency Off-Set
(FOS) alarms.
000: XA/XB (External reference)
001: CKIN1
010: CKIN2
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Rev. 1.0
Si5325
Register 8.
Bit
D7
D6
D5
D4
Name
HLOG_2[1:0]
HLOG_1[1:0]
Type
R/W
R/W
D3
D2
D1
D0
R
R
R
R
Reset value = 0000 0000
Bit
Name
Function
7:6
HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10:Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
5:4
HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
3:0
Reserved
Rev. 1.0
25
Si5325
Register 10.
Bit
D7
D6
D5
D4
Name
R
Type
R
R
D3
D2
D1
D0
DSBL2_REG
DSBL1_REG
Reserved
Reserved
R/W
R/W
R
R
R
Reset value = 0000 0000
Bit
Name
7:4
Reserved
Function
3
DSBL2_REG DSBL2_REG.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
2
DSBL1_REG DSBL1_REG.
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
1:0
Reserved
Register 11.
Bit
D7
D6
D5
D4
D3
D2
Name
Type
R
R
R
R
R
R
Reset value = 0100 0000
26
Bit
Name
Function
7:2
Reserved
1
PD_CK2
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
0
PD_CK1
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
Rev. 1.0
D1
D0
PD_CK2
PD_CK1
R/W
R/W
Si5325
Register 19.
Bit
D7
D6
D5
D4
D3
Name
FOS_EN
FOS_THR [1:0]
VALTIME [1:0]
Type
R/W
R/W
R/W
D2
D1
D0
R
R
R
Reset value = 0010 1100
Bit
Name
Function
7:5
FOS_EN
6:5
FOS_THR [1:0]
FOS_THR [1:0].
Frequency Offset at which FOS is declared:
00: ± 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK
01: ± 48 to 49 ppm (SMC)
10: ± 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
4:3
VALTIME [1:0]
VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is
removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 seconds
2:0
Reserved
FOS_EN.
Frequency Offset Enable globally disables FOS. See the individual FOS enables
(FOSX_EN, register 139).
0: FOS disable
1: FOS enabled by FOSx_EN
Rev. 1.0
27
Si5325
Register 20.
Bit
D7
D6
D5
D4
D2
D1
CK2_BAD_PIN CK1_BAD_PIN
Name
Type
D3
R
R
R
R
R/W
R/W
D0
INT_PIN
R
R/W
Reset value = 0011 1110
28
Bit
Name
Function
7:4
Reserved
3
CK2_BAD_PIN
CK2_BAD_PIN.
The CK2_BAD status can be reflected on the C2B output pin.
0: C2B output pin tristated
1: C2B status reflected to output pin
2
CK1_BAD_PIN
CK1_BAD_PIN.
The CK1_BAD status can be reflected on the C1B output pin.
0: C1B output pin tristated
1: C1B status reflected to output pin
1
Reserved
0
INT_PIN
INT_PIN.
Reflects the interrupt status on the INT_C1B output pin.
0: Interrupt status not displayed on INT_C1B output pin. If CK1_BAD_PIN = 0,
INT_C1B output pin is tristated.
1: Interrupt status reflected to output pin. Instead, the INT_C1B pin indicates when
CKIN1 is bad.
Rev. 1.0
Si5325
Register 21.
Bit
D7
D6
D5
D4
D3
D2
Name
Type
R
Force 1
R
R
R
R
D1
D0
CK1_ACTV_PIN
CKSEL_ PIN
R/W
R/W
Reset value = 1111 1111
Bit
Name
7:2
Reserved
1
0
Function
CK1_ACTV_PIN CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin
controlled clock selection is not being used.
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
CKSEL_PIN
CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.
Rev. 1.0
29
Si5325
Register 22.
Bit
D7
D6
D5
D4
Name
Type
R
R
R
R
D3
D2
CK_ACTV_POL
CK_BAD_ POL
R/W
R/W
D1
D0
INT_POL
R
R/W
Reset value = 1101 1111
Bit
Name
7:4
Reserved
3
30
Function
CK_ACTV_ POL CK_ACTV_POL.
Sets the active polarity for the CS_CA signals when reflected on an output pin.
0: Active low
1: Active high
2
CK_BAD_ POL
1
Reserved
0
INT_POL
CK_BAD_POL.
Sets the active polarity for the INT_C1B and C2B signals when reflected on output
pins.
0: Active low
1: Active high
INT_POL.
Sets the active polarity for the interrupt status when reflected on the INT_C1B output
pin.
0: Active low
1: Active high
Rev. 1.0
Si5325
Register 23.
Bit
D7
D6
D5
D4
D3
Name
Type
R
R
R
R
D2
D1
D0
LOS2_ MSK
LOS1_ MSK
Reserved
R/W
R/W
R
R
Reset value = 0001 1111
Bit
Name
Function
7:3
Reserved
2
LOS2_MSK
LOS2_MSK.
Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS2_FLG register.
0: LOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOS2_FLG ignored in generating interrupt output.
1
LOS1_MSK
LOS1_MSK.
Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS1_FLG register.
0: LOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOS1_FLG ignored in generating interrupt output.
0
Reserved
Rev. 1.0
31
Si5325
Register 24.
Bit
D7
D6
D5
D4
D3
Name
Type
R
R
R
R
D2
D1
FOS2_MSK
FOS1_MSK
R/W
R/W
R
D0
R
Reset value = 0011 1111
32
Bit
Name
Function
7:3
Reserved
2
FOS2_MSK
FOS2_MSK.
Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this
register do not change the value held in the FOS2_FLG register.
0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS2_FLG ignored in generating interrupt output.
1
FOS1_MSK
FOS1_MSK.
Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this register do not change the value held in the FOS1_FLG register.
0: FOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS1_FLG ignored in generating interrupt output.
0
Reserved
Rev. 1.0
Si5325
Register 25.
Bit
D7
D6
Name
N1_HS [2:0]
Type
R/W
D5
D4
D3
D2
D1
D0
R
R
R
R
R
Reset value = 0010 0000
Bit
Name
Function
7:5
N1_HS [2:0]
N1_HS [2:0].
Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider.
000: N1 = 4 Note: Changing the coarse skew via the INC pin is disabled for this value.
001: N1 = 5
010: N1 = 6
011: N1 = 7
100: N1 = 8
101: N1 = 9
110: N1 = 10
111: N1 = 11
4:0
Reserved
Register 31.
Bit
D7
D6
D5
D4
D3
D1
D0
NC1_LS [19:16]
Name
Type
D2
R
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:4
Reserved
3:0
NC1_LS
[19:16]
Function
NC1_LS [19:16].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220]
Rev. 1.0
33
Si5325
Register 32.
Bit
D7
D6
D5
D4
D3
Name
NC1_LS [15:8]
Type
R/W
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
NC1_LS [15:8]
Function
NC1_LS [15:8].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220]
Register 33.
Bit
D7
D6
D5
D4
D3
Name
NC1_LS [7:0]
Type
R/W
D2
D1
D0
Reset value = 0011 0001
34
Bit
Name
Function
7:0
NC1_LS [19:0]
NC1_LS [7:0].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220]
Rev. 1.0
Si5325
Register 34.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
NC2_LS [19:16]
Name
R
Type
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:4
Reserved
3:0
NC2_LS [19:16]
Function
NC2_LS [19:16].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220]
Register 35.
Bit
D7
D6
D5
D4
D3
Name
NC2_LS [15:8]
Type
R/W
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
NC2_LS [15:8]
Function
NC2_LS [15:8].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220]
Rev. 1.0
35
Si5325
Register 36.
Bit
D7
D6
D5
D4
D3
Name
NC2_LS [7:0]
Type
R/W
D2
D1
D0
Reset value = 0011 0001
Bit
7:0
Name
Function
NC2_LS [7:0] NC2_LS [7:0].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [1, 2, 4, 6, ..., 220]
Register 40.
Bit
D7
D6
D5
D4
D3
D1
N2_LS [19:16]
Name
Type
D2
R
R/W
Reset value = 1100 0000
Bit
Name
7:4
Reserved
3:0
Function
N2_LS [19:16] N2_LS [19:16].
Sets the value for the N2 low-speed divider, which drives the phase detector.
Must be an even number ranging from 32 to 512 (inclusive).
00000000000000100000 = 32
00000000000000100010 = 34
00000000000000100100 = 36
...
00000000001000000000 = 512
Valid divider values = [32, 34, 36...512]
36
Rev. 1.0
D0
Si5325
Register 41.
Bit
D7
D6
D5
D4
D3
Name
N2_LS [15:8]
Type
R/W
D2
D1
D0
Reset value = 0000 0000
Bit
7:0
Name
Function
N2_LS [15:8] N2_LS [15:8].
Sets the value for the N2 low-speed divider, which drives the phase detector.
Must be an even number ranging from 32 to 512 (inclusive).
00000000000000100000 = 32
00000000000000100010 = 34
00000000000000100100 = 36
...
00000000001000000000 = 512
Valid divider values = [32, 34, 36...512]
Register 42.
Bit
D7
D6
D5
D4
D3
Name
N2_LS [7:0]
Type
R/W
D2
D1
D0
Reset value = 1111 1001
Bit
Name
7:0
N2_LS [7:0]
Function
N2_LS [7:0].
Sets the value for the N2 low-speed divider, which drives the phase detector.
Must be an even number ranging from 32 to 512 (inclusive).
00000000000000100000 = 32
00000000000000100010 = 34
00000000000000100100 = 36
...
00000000001000000000 = 512
Valid divider values = [32, 34, 36...512]
Rev. 1.0
37
Si5325
Register 43.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
N31 [18:16]
Name
R
Type
R
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:3
Reserved
2:0
N31 [18:16]
Function
N31 [18:16].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values = [1, 2, 3, ..., 219]
Register 44.
Bit
D7
D6
D5
D4
D3
Name
N31_[15:8]
Type
R/W
Reset value = 0000 0000
38
Bit
Name
7:0
N31_[15:8]
Function
N31_[15:8].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values = [1, 2, 3, ..., 219]
Rev. 1.0
D2
D1
D0
Si5325
Register 45.
Bit
D7
D6
D5
D4
D3
Name
N31_[7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 1001
Bit
Name
7:0
N31_[7:0
Function
N31_[7:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]
Register 46.
Bit
D7
D6
D5
D4
D3
N32_[18:16]
Name
Type
R
R
R
R
R
R/W
Reset value = 0000 0000
Bit
Name
7:3
Reserved
2:0
N32_[18:16]
Function
N32_[18:16].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values = [1, 2, 3, ..., 219]
Rev. 1.0
39
Si5325
Register 47.
Bit
D7
D6
D5
D4
D3
Name
N32_[15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 0000 0000
Bit
Name
7:0
N32_[15:8]
Function
N32_[15:8].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]
Register 48.
Bit
D7
D6
D5
D4
D3
Name
N32_[7:0]
Type
R/W
Reset value = 0000 1001
40
Bit
Name
7:0
N32_[7:0]
Function
N32_[7:0].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values = [1, 2, 3, ..., 219]
Rev. 1.0
Si5325
Register 55h.
Bit
D7
D6
Name
Type
R
R
D5
D4
D3
D2
D1
CLKIN2RATE_[2:0]
CLKIN1RATE[2:0]
R/W
R/W
D0
Reset value = 0000 0000
Bit
Name
Function
7:6
Reserved
5:3
CLKIN2RATE[2:0]
CLKIN2RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
2:0
CLKIN1RATE [2:0]
CLKIN1RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
Rev. 1.0
41
Si5325
Register 128.
Bit
D7
D6
D5
D4
D3
D2
D0
CK2_ACTV_REG CK1_ACTV_REG
Name
Type
D1
R
R
R
R
R
R
R
R
Reset value = 0010 0000
Bit
Name
Function
7:2
Reserved
1
CK2_ACTV_REG
CK2_ACTV_REG.
Indicates if CKIN2 is currently the active clock for the PLL input.
0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
1: CKIN2 is the active input clock.
0
CK1_ACTV_REG
CK1_ACTV_REG.
Indicates if CKIN1 is currently the active clock for the PLL input.
0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.
1: CKIN1 is the active input clock.
Register 129.
Bit
D7
D6
D5
D4
D3
Name
Type
R
R
R
R
R
Reset value = 0000 0110
42
Bit
Name
Function
7:3
Reserved
2
LOS2_INT
LOS2_INT.
Indicates the LOS status on CKIN2.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN2 input.
1
LOS1_INT
LOS1_INT.
Indicates the LOS status on CKIN1.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN1 input.
0
Reserved
Rev. 1.0
D2
D1
LOS2_INT
LOS1_INT
R
R
D0
R
Si5325
Register 130.
Bit
D7
D6
D5
D4
D3
D1
D0
FOS2_INT FOS1_INT
Name
Type
D2
R
R
R
R
R
R
R
R
Reset value = 0000 0001
Bit
Name
Function
7:3
Reserved
2
FOS2_INT
CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
1
FOS1_INT
CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
0
Reserved
Rev. 1.0
43
Si5325
Register 131.
Bit
D7
D6
D5
D4
D3
D1
D0
LOS2_FLG LOS1_FLG
Name
Type
D2
R
R
R
R
R
R/W
R/W
R
Reset value = 0001 1111
44
Bit
Name
Function
7:3
Reserved
2
LOS2_FLG
CKIN2 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to
this bit.
1
LOS1_FLG
CKIN1 Loss-of-Signal Flag.
0: Normal operation
1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to
this bit.
0
Reserved
Rev. 1.0
Si5325
Register 132.
Bit
D7
D6
D5
D4
D2
D1
D0
R
R
FOS2_FLG FOS1_FLG
Name
Type
D3
R
R
R
R
R/W
R/W
Reset value = 0000 0010
Bit
Name
Function
7:4, 0
Reserved
3
FOS2_FLG
CLKIN_2 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to
this bit.
2
FOS1_FLG
CLKIN_1 Frequency Offset Flag.
0: Normal operation
1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to
this bit.
1
Reserved
Rev. 1.0
45
Si5325
Register 134.
Bit
D7
D6
D5
D4
D3
Name
PARTNUM_RO [11:4]
Type
R
D2
D1
D0
D2
D1
D0
Reset value = 0000 0001
Bit
7:0
Name
Function
PARTNUM_RO [11:0] Device ID (1 of 2).
0000 0001 1001: Si5325
Register 135.
Bit
D7
D6
D5
D4
D3
Name
PARTNUM_RO [3:0]
REVID_RO [3:0]
Type
R
R
Reset value = 1010 0010
Bit
7:4
3:0
46
Name
Function
PARTNUM_RO [11:0] Device ID (2 of 2).
0000 0001 1001: Si5325
REVID_RO [3:0]
Indicates Revision Number of Device.
0000: Revision A
0001: Revision B
0010: Revision C
Others: Reserved
Rev. 1.0
Si5325
Register 136.
Bit
D7
D6
Name
RST_REG
ICAL
Type
R/W
R/W
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
Reset value = 0000 0000
Bit
Name
7
RST_REG
Function
Internal Reset (Same as Pin Reset).
Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
6
ICAL
5:0
Reserved
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is
complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be
present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take
effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibration, LOL will go low.
Rev. 1.0
47
Si5325
Register 138.
Bit
D7
D6
D5
D4
D3
D2
D0
LOS2_EN [1:1] LOS1_EN [1:1]
Name
Type
D1
R
R
R
R
R
R
R/W
R/W
Reset value = 0000 1111
Bit
Name
Function
7:2
Reserved
1
LOS2_EN [1:0]
Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. SEe the Family Reference Manual for details.
0
LOS1_EN [1:0]
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual for details.
48
Rev. 1.0
Si5325
Register 139.
Bit
D7
D6
D4
D3
D2
LOS2_EN [0:0] LOS1_EN [0:0]
Name
Type
D5
R
R
R/W
R/W
R
R
D1
D0
FOS2_EN
FOS1_EN
R/W
R/W
Reset value = 1111 1111
Bit
Name
7:6,
3:2
Reserved
5
LOS2_EN [1:0]
Function
Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details
4
LOS1_EN [1:0]
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details.
1
FOS2_EN
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
0
FOS1_EN
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
Rev. 1.0
49
Si5325
Register 142.
Bit
D7
D6
D5
D4
D3
D2
Name
INDEPENDENTSKEW1 [7:0]
Type
R/W
D1
D0
Reset value = 0000 0000
Bit
7:0
Name
Function
INDEPENDENTSKEW1 [7:0] INDEPENDENTSKEW1.
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider. Default = 0.
Register 143.
Bit
D7
D6
D5
D4
D3
D2
Name
INDEPENDENTSKEW2 [7:0]
Type
R/W
D1
D0
Reset value = 0000 0000
50
Bit
Name
7:0
INDEPEND-ENTSKEW2 [7:0]
Function
INDEPENDENTSKEW2.
8 bit field that represents a twos complement of the phase offset in
terms of clocks from the high speed output divider. Default = 0.
Rev. 1.0
Si5325
Table 9. CKOUT_ALWAYS_ON and SQICAL Truth Table
CKOUT_ALWAYS_ON
SQICAL
Results
Output to Output
Skew Preserved?
0
0
CKOUT OFF until after the first ICAL
N
0
1
CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
Y
1
0
CKOUT always ON, including during an ICAL
N
1
1
CKOUT always ON, including during an ICAL
Y
Table 10 lists all of the register locations that should be followed by an ICAL after their contents are changed.
Table 10. Register Locations Requiring ICAL
Addr
Register
0
BYPASS_REG
0
CKOUT_ALWAYS_ON
1
CK_PRIOR2
1
CK_PRIOR1
2
BWSEL_REG
4
HIST_DEL
5
ICMOS
7
FOSREFSEL
9
HIST_AVG
10
DSBL2_REG
10
DSBL1_REG
11
PD_CK2
11
PD_CK1
19
FOS_EN
19
FOS_THR
19
VALTIME
19
LOCKT
25
N1_HS
31
NC1_LS
34
NC2_LS
40
N2_HS
40
N2_LS
43
N31
46
N32
55
CLKIN2RATE
55
CLKIN1RATE
Rev. 1.0
51
Si5325
CLKOUT1+
CLKOUT1–
NC
GND
NC
VDD
CKOUT2–
CKOUT2+
CMODE
5. Pin Descriptions: Si5325
36 35 34 33 32 31 30 29 28
RST
1
27 SDI
NC
2
26 A2_SS
INT_C1B
3
25 A1
C2B
4
VDD
5
GND
6
NC
7
GND
8
20 GND
NC
9
19 GND
24 A0
GND
Pad
23 SDA_SDO
22 SCL
21 CS_CA
NC
CLKIN1–
CLKIN1+
VDD
NC
CLKIN2–
CLKIN2+
VDD
VDD
10 11 12 13 14 15 16 17 18
Table 11. Si5325 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1
RST
I
LVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces
the device registers to their default value. Clock outputs are
tristated during reset. The part must be programmed after a
reset or power-on to get a clock output. See Family Reference Manual for details.
This pin has a weak pull-up.
2, 7, 9, 14,
18, 30, 33
NC
3
INT_C1B
No Connect.
This pin must be left unconnected for normal operation.
O
LVCMOS
Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm
output for CKIN1. If used as an interrupt output, INT_PIN
must be set to 1. The pin functions as a maskable interrupt
output with active polarity controlled by the INT_POL register
bit.
If used as an alarm output, the pin functions as a LOS (and
optionally FOS) alarm indicator for CKIN1. Set
CK1_BAD_PIN = 1 and INT_PIN = 0.
0 = CKIN1 present.
1 = LOS (FOS) on CKIN1.
The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.
52
Rev. 1.0
Si5325
Table 11. Si5325 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
4
C2B
O
LVCMOS
CKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indicator for CKIN2 if CK2_BAD_PIN = 1.
0 = CKIN2 present.
1 = LOS (FOS) on CKIN2.
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
5, 10, 11,
15, 32
VDD
VDD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following VDD pins:
5
0.1 µF
10
0.1 µF
32
0.1 µF
A 1.0 µF should also be placed as close to device as is practical.
6, 8, 19,
20 31
GND
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
12
13
CKIN2+
CKIN2–
I
Multi
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency range is 10 to 710 MHz.
16
17
CKIN1+
CKIN1–
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency range is 10 to 710 MHz.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.
Rev. 1.0
53
Si5325
Table 11. Si5325 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
21
CS_CA
I/O
LVCMOS
Input Clock Select/Active Clock Indicator.
Input: In manual clock selection mode, this pin functions as
the manual input clock selector if the CKSEL_PIN is
set to 1.
0 = Select CKIN1.
1 = Select CKIN2.
If CKSEL_PIN = 0, the CKSEL_REG register bit
controls this function. If configured as input, must be
set high or low.
Output: In automatic clock selection mode, this pin indicates
which of the two input clocks is currently the active
clock. If alarms exist on both clocks, CA will indicate
the last active clock that was used before entering
the VCO freeze state. The CK_ACTV_PIN register
bit must be set to 1 to reflect the active clock status
to the CA output pin.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
If CK_ACTV_PIN = 0, this pin will tristate. The CA
status will always be reflected in the CK_ACTV_REG read only register bit.
22
SCL
I
LVCMOS
Serial Clock/Serial Clock.
This pin functions as the serial clock input for both SPI and
I2C modes.
This pin has a weak pulldown.
23
SDA_SDO
I/O
LVCMOS
Serial Data.
In I2C control mode (CMODE = 0), this pin functions as the
bidirectional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the
serial data output.
25
24
A1
A0
I
LVCMOS
Serial Port Address.
In I2C control mode (CMODE = 0), these pins function as
hardware controlled address bits. The I2C address is 1101
[A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
This pin has a weak pulldown.
26
A2_SS
I
LVCMOS
Serial Port Address/Slave Select.
In I2C control mode (CMODE = 0), this pin functions as a
hardware controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the
slave select input.
This pin has a weak pulldown.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.
54
Rev. 1.0
Si5325
Table 11. Si5325 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
27
SDI
I
LVCMOS
29
28
CKOUT1–
CKOUT1+
O
Multi
Output Clock 1.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs.
34
35
CKOUT2–
CKOUT2+
O
Multi
Output Clock 2.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs.
36
CMODE
I
LVCMOS
GND PAD
GND
GND
Supply
Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the
serial data input.
This pin has a weak pulldown.
Control Mode.
Selects I2C or SPI control mode for the Si5325.
0 = I2C Control Mode.
1 = SPI Control Mode.
Must not float.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.
Rev. 1.0
55
Si5325
6. Ordering Guide
Ordering Part
Number
Output Clock
Frequency Range
Package
ROHS6,
Pb-Free
Temperature Range
Si5325A-C-GM*
.002–945 MHz
970–1134 MHz
1.213–1.4 GHz
36-Lead 6 x 6 mm QFN
Yes
–40 to 85 °C
Si5325B-C-GM*
.002–808 MHz
36-Lead 6 x 6 mm QFN
Yes
–40 to 85 °C
Si5325C-C-GM*
.002–346 MHz
36-Lead 6 x 6 mm QFN
Yes
–40 to 85 °C
*Note: Not recommended for new designs. For alternatives, see the Si533x family.
56
Rev. 1.0
Si5325
7. Package Outline: 36-Pin QFN
Figure 6 illustrates the package details for the Si5325. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 6. 36-Pin Quad Flat No-lead (QFN)
Table 12. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05

—
—
12º
b
0.18
0.25
0.30
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
D
D2
L
6.00 BSC
3.95
4.10
4.25
Min
Nom
Max
0.50
0.60
0.70
e
0.50 BSC
ddd
—
—
0.10
E
6.00 BSC
eee
—
—
0.05
E2
3.95
4.10
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
57
Si5325
8. Land Pattern: 36-Pin QFN
Figure 7. 36-Pin QFN Land Pattern
58
Rev. 1.0
Si5325
Table 13. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
E
5.42 REF.
D
5.42 REF.
E2
4.00
4.20
D2
4.00
4.20
GE
4.53
—
GD
4.53
—
X
—
0.28
Y
0.89 REF.
ZE
—
6.31
ZD
—
6.31
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.0
59
Si5325
9. Top Marking
9.1. Si5325 Top Marking (QFN)
9.2. Top Marking Explanation
Mark Method:
Laser
Font Size:
0.80 mm
Right-Justified
Line 1 Marking:
Si5325Q
Customer Part Number
Q = Speed Code: A, B, C
See Ordering Guide for options.
Line 2 Marking:
C-GM
C = Product Revision
G = Temperature Range –40 to 85 °C (RoHS6)
M = QFN Package
Line 3 Marking:
YYWWRF
YY = Year
WW = Work Week
R = Die Revision
F = Internal code
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
Line 4 Marking:
Pin 1 Identifier
Circle = 0.75 mm Diameter
Lower-Left Justified
XXXX
Internal Code
60
Rev. 1.0
Si5325
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 0.5

Clarified that the two outputs have a common, higher
frequency source on page 1.
 Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 5.
 Added Figure 1, “Typical Phase Noise Plot,” on page
4.
 Updated “5. Pin Descriptions: Si5325”.

Removed
Changed
references to latency control, INC, and DEC.
font for register names to underlined italics.
Updated "6. Ordering Guide" on page 56.
 Added “8. Land Pattern: 36-Pin QFN”.

Added
“not recommended for new designs” language.
Updated Table 5 on page 52.
Updated "6. Ordering Guide" on page 56.
 Removed note from "5. Pin Descriptions: Si5325" on
page 52.


Revision 0.5 to Revision 1.0
Updated logo.
 Transitioned to full production.

Revision 0.24 to Revision 0.25

Expanded electrical specification tables 1 through 7.
Removed support for CMOS outputs in Bypass
mode.
 Corrected minor errors in register map section.
 Updated " Features" on page 1“.

Revision 0.23 to Revision 0.24
Updated Section "5. Pin Descriptions: Si5325" on
page 52.
Revision 0.25 to Revision 0.26


Removed Figure 1. “Typical Phase Noise Plot.”
Changed pins 11 and 15 from NC to VDD in “5. Pin
Descriptions: Si5325”.
Revision 0.26 to Revision 0.3






Changed 1.8 V operating range to ±5%.
Updated Table 1 on page 4.
Updated Table 2 on page 5.
Added page 14.
Updated "2. Functional Description" on page 16.
Clarified "5. Pin Descriptions: Si5325" on page 52
including pull-up/pull-down.
Revision 0.3 to Revision 0.4
Added register map
Lowered minimum CKOUT frequency
 Updated spec tables


ESD
tolerance, Table 2 on page 5
input and output clock frequencies, Table 1 on
page 4
Absolute maximum VDD voltage, Table 2 on page 5
Minimum

Added to spec table
CKIN
voltage limits, Table 2 on page 5
jitter and phase noise values, Table 1 on page 4
Typical

No bypass mode with CMOS outputs
Rev. 1.0
61
Si5325
CONTACT INFORMATION
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Tel: 1+(512) 416-8500
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Toll Free: 1+(877) 444-3032
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the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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62
Rev. 1.0
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