CYP | RXC | WirelessUSB™ LP 2.4GHz Radio SoC

CYRF6936
WirelessUSB™ LP 2.4GHz Radio SoC
1.0
Features
2.0
• 2.4-GHz Direct Sequence Spread Spectrum (DSSS) radio
transceiver
• Operates in the unlicensed worldwide Industrial, Scientific
and Medical (ISM) band (2.400 GHz–2.483 GHz)
• 21mA operating current (Transmit @ –5 dBm)
• Transmit power up to +4 dBm
• Receive sensitivity up to –97 dBm
• Sleep Current <1 µA
• Operating range: 10m+
• DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps
• Low external component count
• Auto Transaction Sequencer (ATS) - no MCU intervention
• Framing, Length, CRC16, and Auto ACK
• Power Management Unit (PMU) for MCU/Sensor
• Fast Startup and Fast Channel Changes
• Separate 16-byte Transmit and Receive FIFOs
• AutoRate™ - dynamic data rate reception
• Receive Signal Strength Indication (RSSI)
• Serial Peripheral Interface (SPI) control while in sleep mode
• 4-MHz SPI microcontroller interface
• Battery Voltage Monitoring Circuitry
• Supports coin-cell operated applications
• Operating voltage from 1.8V to 3.6V
• Operating temperature from 0 to 70°C
• Space saving 40-pin QFN 6x6 mm package
•
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•
•
•
•
•
•
•
Applications
Wireless Keyboards and Mice
Wireless Gamepads
Remote Controls
Toys
VOIP and Wireless Headsets
White Goods
Consumer Electronics
Home Automation
Automatic Meter Readers
Personal Health & Entertainment
3.0
Applications Support
See www.cypress.com for development tools, reference
designs, and application notes.
4.0
Functional Description
The CYRF6936 WirelessUSB™ LP radio is a second generation member of Cypress’s WirelessUSB Radio System-OnChip (SoC) family. The CYRF6936 is interoperable with the
first generation CYWUSB69xx devices. The CYRF6936 IC
adds a range of enhanced features, including increased
operating voltage range, reduced supply current in all
operating modes, higher data rate options, and reduced
crystal start-up, synthesizer settling and link turn-around
times.
Figure 4-1. CYRF6936 Simplified Block Diagram
VIO
VBAT
VREG
L/D
VDD VCC
Power Management
IRQ
SS
SCK
MISO
MOSI
SPI
Data
Interface
and
Sequencer
PACTL
RFP
GFSK
Modulator
RFN
RFBIAS
DSSS
Baseband
& Framer
GFSK
Demodulator
RSSI
Xtal Osc
Synthesizer
RST
Block Diagram
XTAL
XOUT
GND
Cypress Semiconductor Corporation
Document #: 38-16015 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 18, 2006
CYRF6936
5.0
Pin Descriptions
Pin #
Name
Type Default
13
RFN
I/O
11
RFP
10
RFBIAS
30
PACTL
1
XTAL
29
XOUT
25
SCK
28
MISO
27
MOSI
24
Description
I
Differential RF signal to/from antenna
I/O
I
Differential RF signal to/from antenna
O
O
RF I/O 1.8V reference voltage
I/O
O
Control signal for external PA, T/R switch, or GPIO
I
I
12-MHz crystal
I/O
O
Buffered 0.75, 1.5, 3, 6 or 12 MHz clock, PACTL, or GPIO.
Tristates in sleep mode (recommend configure as GPIO drive low).
I
I
SPI clock
I/O
Z
SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tristates when SPI 3PIN=0 and SS deasserted.
I/O
I
SPI data input pin (Master Out Slave In), or SDAT
SS
I
I
SPI enable, active low assertion - enables and frames transfers.
26
IRQ
I/O
O
Interrupt output (configurable active high or low), or GPIO
34
RST
I
I
Device reset. Internal 10k-ohm pull-down resistor. Active HIGH,
typically connect via 0.1-µF capacitor to VBAT
37
L/D
O
40
VREG
Pwr
PMU boosted output voltage feedback
35
VDD
Pwr
Decoupling pin for 1.8V logic regulator, connect via 0.47-µF capacitor
to GND
6, 8, 38
VBAT
Pwr
VBAT = 1.8V to 3.6V. Main supply.
3, 7, 16
VCC
Pwr
VCC = 2.4V to 3.6V. Typically connected to VREG
33
VIO
Pwr
I/O interface voltage, 1.8–3.6V
19
RESV
2, 4, 5, 9, 14, 15, 18, 17, 20,
21, 22, 23, 32, 36, 39, 31
NC
12
GND
GND
Ground
E-PAD
GND
GND
Ground
PMU inductor/diode connection
I
Must be connected to GND
NC
Recommend to connect to GND
Figure 5-1. CYRF6936, 40 QFN – Top Vie
CYRF6936
Top View*
NC 31
33
NC 32
V
IO
35
RST 34
V
DD
NC 36
L/D 37
NC 39
VBAT 38
VREG 40
XTAL 1
30 PACTL / GPIO
NC 2
29 XOUT / GPIO
V CC 3
28 MISO / GPIO
NC 4
27 MOSI / SDAT
CYRF6936
40-lead QFN
NC 5
V BAT 6
26 IRQ / GPIO
25 SCK
V CC 7
24 SS
V BAT 8
23 NC
NC 9
22 NC
RF BIAS 10
21 NC
20 NC
19 RESV
18 NC
17 NC
16 VCC
15 NC
14 NC
13 RFN
12 GND
11 RFP
* E-PAD BOTTOM SIDE
Document #: 38-16015 Rev. *F
Page 2 of 39
CYRF6936
6.0
Functional Overview
The CYRF6936 IC provides a complete WirelessUSB SPI to
antenna wireless MODEM. The SoC is designed to implement
wireless device links operating in the worldwide 2.4-GHz ISM
frequency band. It is intended for systems compliant with
world-wide regulations covered by ETSI EN 301 489-1 V1.41,
ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15
(USA and Industry Canada) and TELEC ARIB_T66_March,
2003 (Japan).
The SoC contains a 2.4-GHz 1-Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband
controller, Received Signal Strength Indication (RSSI), and
SPI interface for data transfer and device configuration.
The radio supports 98 discrete 1-MHz channels (regulations
may limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start
of Packet (SOP), End of Packet (EOP) detection and CRC16
generation and checking. The baseband may also be
configured to automatically transmit Acknowledge (ACK)
handshake packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the
device is always ready to receive data transmitted at any of the
supported bit rates enabling the implementation of mixed-rate
systems in which different devices use different data rates.
This also enables the implementation of dynamic data rate
systems, which use high data rates at shorter distances and/or
in a low-moderate interference environment, and change to
lower data rates at longer distances and/or in high interference
environments.
In addition, the CYRF6936 IC has a Power Management Unit
(PMU) which allows direct connection of the device to any
battery voltage in the range 1.8V to 3.6V. The PMU conditions
the battery voltage to provide the supply voltages required by
the device, and may supply external devices.
Data Transmission Modes
The SoC supports four different data transmission modes:
• In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
• In 8DR mode, 8 bits are encoded in each derived code
symbol transmitted.
• In DDR mode, 2-bits are encoded in each derived code
symbol transmitted. (As in the CYWUSB6934 DDR mode).
• In SDR mode, 1 bit is encoded in each derived code symbol
transmitted. (As in the CYWUSB6934 standard modes.)
Both 64-chip and 32-chip Pseudo-Noise (PN) Codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduce
packet error rate in any given environment.
Link Layer Modes
The CYRF6936 IC device supports the following data packet
framing features:
SOP – Packets begin with a 2-symbol Start of Packet (SOP)
marker. This is required in GFSK and 8DR modes, but is
optional in DDR mode and is not supported in SDR mode; if
framing is disabled then an SOP event is inferred whenever
two
successive
correlations
are
detected.
The
SOP_CODE_ADR code used for the SOP is different from that
used for the “body” of the packet, and if desired may be a
different length. SOP must be configured to be the same
length on both sides of the link.
Length – There are two options for detecting the end of a
packet. If SOP is enabled, then the length field should be
enabled. GFSK and 8DR must enable the length field. This is
the first 8-bits after the SOP symbol, and is transmitted at the
payload data rate. When the length field is enabled, an End of
Packet (EOP) condition is inferred after reception of the
number of bytes defined in the length field, plus two bytes for
the CRC16 (when enabled—see below). The alternative to
using the length field is to infer an EOP condition from a configurable number of successive non-correlations; this option is
not available in GFSK mode and is only recommended to
enable when using SDR mode.
CRC16 – The device may be configured to append a 16-bit
CRC16 to each packet. The CRC16 uses the USB CRC
polynomial with the added programmability of the seed. If
enabled, the receiver will verify the calculated CRC16 for the
payload data against the received value in the CRC16 field.
The seed value for the CRC16 calculation is configurable, and
the CRC16 transmitted may be calculated using either the
loaded seed value or a zero seed; the received data CRC16
will be checked against both the configured and zero CRC16
seeds.
CRC16 detects the following errors:
• Any one bit in error
• Any two bits in error (no matter how far apart, which column,
and so on)
• Any odd number of bits in error (no matter where they are)
• An error burst as wide as the checksum itself
Figure 6-1 shows an example packet with SOP, CRC16 and
lengths fields enabled, and Figure 6-2 shows a standard ACK
packet.
Figure 6-1. Example Packet Format
2 n d F ra m in g
S y m b o l*
P re a m b le
n x 16us
P
SOP 1
SOP 2
1 s t F ra m in g
S y m b o l*
Document #: 38-16015 Rev. *F
L e n g th
Packet
le n g th
1 B y te
P e rio d
P a y lo a d D a ta
C R C 16
*N o te :3 2 o r 6 4 u s
Page 3 of 39
CYRF6936
Figure 6-2. Example ACK Packet Format
2 n d F r a m in g
S y m b o l*
P r e a m b le
n x 16us
P
SOP 1
1 s t F r a m in g
S y m b o l*
SOP 2
C R C 16
C R C f ie ld f r o m
r e c e iv e d p a c k e t .
2 B y t e p e r io d s
Packet Buffers
All data transmission and reception utilizes the 16-byte packet
buffers—one for transmission and one for reception.
The transmit buffer allows a complete packet of up to 16-bytes
of payload data to be loaded in one burst SPI transaction, and
then transmitted with no further MCU intervention. Similarly,
the receive buffer allows an entire packet of payload data up
to 16 bytes to be received with no firmware intervention
required until packet reception is complete.
The CYRF6936 IC supports packets up to 255 bytes, however,
actual maximum packet length will depend on accuracy of the
clock on each end of the link and the data mode; interrupts are
provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16-bytes initially, and add further
bytes to the transmit buffer as transmission of data creates
space in the buffer. Similarly, when receiving packets longer
than 16 bytes, the MCU must fetch received data from the
FIFO periodically during packet reception to prevent it from
overflowing.
Auto Transaction Sequencer (ATS)
The CYRF6936 IC provides automated support for transmission and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
• starts the crystal and synthesizer
• enters transmit mode
• transmits the packet in the transmit buffer
• transitions to receive mode and waits for an ACK packet
• transitions to the transaction end state when either an ACK
packet is received, or a timeout period expires
Similarly, when receiving in transaction mode, the device
automatically:
• waits in receive mode for a valid packet to be received
• transitions to transmit mode, transmits an ACK packet
• transitions to the transaction end state (receive mode to
await the next packet, etc.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (providing packets of 16
bytes or less are used); to transmit data the MCU simply needs
to load the data packet to be transmitted, set the length, and
set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware simply needs to retrieve the fully
Document #: 38-16015 Rev. *F
* N o te :3 2 o r 6 4 u s
received packet in response to an interrupt request indicating
reception of a packet.
Backward Compatibility
The CYRF6936 IC is fully interoperable with the main modes
of the first generation devices. The 62.5-kbps mode is
supported by selecting 32-chip DDR mode. Similarly, the
15.675-kbps mode is supported by selecting 64-chip SDR
mode.
In this way, a suitably configured CYRF6936 IC device may
transmit data to and/or receive data from a first generation
device. Disabling the SOP, length, and CRC16 fields is
required for backwards compatibility.
Data Rates
By combining the PN code lengths and data transmission
modes described above, the CYRF6936 IC supports the
following data rates:
• 1000-kbps (GFSK)
• 250-kbps (32-chip 8DR)
• 125-kbps (64-chip 8DR)
• 62.5-kbps (32-chip DDR)
• 31.25-kbps (64-chip DDR)
• 15.625-kbps (64-chip SDR)
7.0
Functional Block Overview
2.4-GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 7-1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
7
+4
6
0
5
–5
4
–13
3
–18
2
–24
1
–30
0
–35
Page 4 of 39
CYRF6936
• Six bits of address.
• Eight bits of data.
Table 7-2. Typical Range Observed Table
Environment
Typical Range (meters)
Outdoor
30
Office
20
Home
15
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO
pin. The active-low Slave Select (SS) pin must be asserted to
initiate an SPI transfer.
Frequency Synthesizer
The application MCU can initiate SPI data transfers via a multibyte transaction. The first byte is the Command/Address byte,
and the following bytes are the data bytes as shown in
Figure 7-1 through Figure 7-4.
Before transmission or reception may commence, it is
necessary for the frequency synthesizer to settle. The settling
time varies depending on channel; 25 fast channels are
provided with a maximum settling time of 100-µs.
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
desired. A burst transaction is terminated by deasserting the
slave select (SS = 1).
The “fast channels” (<100-µs settling time) are every 3rd
channel, starting at 0 up to and including 72 (i.e.,
0,3,6,9…….69 & 72).
The SPI communications interface single read and burst read
sequences are shown in Figure 7-2 and Figure 7-3, respectively.
Baseband and Framer
The SPI communications interface single write and burst write
sequences are shown in Figure 7-4 and Figure 7-5, respectively.
Note: Range observed with CY4636 WirelessUSB LP KBM v1.0 (Keyboard)
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, as well as EOP detection and length
field.
Packet Buffers and Radio Configuration
Registers
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet (as in
the CYWUSB6934). Configuration registers are provided to
allow configuration of DSSS PN codes, data rate, operating
mode, interrupt masks, interrupt status, etc.
SPI Interface
The CYRF6936 IC has a SPI interface supporting communications between an application MCU and one or more slave
devices (including the CYRF6936). The SPI interface supports
single-byte and multi-byte serial transfers using either 4-pin or
3-pin interfacing. The SPI communications interface consists
of Slave Select (SS), Serial Clock (SCK), and Master OutSlave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
The SPI communications is as follows:
• Command Direction (bit 7) = “1” enables SPI write transaction. A “0” enables SPI read transactions.
• Command Increment (bit 6) = “1” enables SPI auto address
increment. When set, the address field automatically increments at the end of each data byte in a burst access,
otherwise the same address is accessed.
Document #: 38-16015 Rev. *F
This interface may optionally be operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional data pin (SDAT). When using 3-pin mode, user firmware
should ensure that the MOSI pin on the MCU is in a highimpedance state except when MOSI is actively transmitting
data.
The device registers may be written to or read from 1 byte at
a time, or several sequential register locations may be
written/read in a single SPI transaction using incrementing
burst mode. In addition to single byte configuration registers,
the device includes register files; register files are FIFOs
written to and read from using non-incrementing burst SPI
transactions.
The IRQ pin function may optionally be multiplexed onto the
MOSI pin; when this option is enabled the IRQ function is not
available while the SS pin is low. When using this configuration, user firmware should ensure that the MOSI pin on the
MCU is in a high impedance state whenever the SS pin is high.
The SPI interface is not dependent on the internal 12-MHz
clock, and registers may therefore be read from or written to
while the device is in sleep mode, and the 12-MHz oscillator
disabled.
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (VIO), enabling the device to interface
directly to MCUs operating at voltages below the CYRF6936
IC supply voltage.
Page 5 of 39
CYRF6936
Figure 7-1. SPI Transaction Format
Byte 1
Byte 1+N
Bit #
7
6
[5:0]
[7:0]
Bit Name
DIR
INC
Address
Data
Figure 7-2. SPI Single Read Sequence
SCK
SS
cmd
MOSI
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu
MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7-3. SPI Incrementing Burst Read Sequence
SCK
SS
MOSI
cmd
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu1+N
data to mcu1
MISO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
Figure 7-4. SPI Single Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
Figure 7-5. SPI Incrementing Burst Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu1
A1
A0
D7
D6
D5
D4
D3
D2
data from mcu1+N
D1
D0
D7
D6
D5
D4
D3
D2
MISO
Document #: 38-16015 Rev. *F
Page 6 of 39
CYRF6936
Interrupts
The device provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events.
The IRQ pin may be programmed to be either active high or
active low, and be either a CMOS or open drain output. A full
description of all the available interrupts can be found in
Section 9.0.
The CYRF6936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled/disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is
necessary to read the relevant status register to determine
which event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate status register. It is therefore possible
to use the devices without making use of the IRQ pin by polling
the status register(s) to wait for an event, rather than using the
IRQ pin.
Clocks
A 12-MHz crystal (30-ppm or better) is directly connected
between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable
output frequencies of 0.75-, 1.5-, 3-, 6-, or 12-MHz. This output
may be used to clock an external microcontroller (MCU) or
ASIC. This output is enabled by default, but may be disabled.
Below are the requirements for the crystal to be directly
connected to XTAL pin and GND:
• Nominal Frequency: 12 MHz
• Operating Mode: Fundamental Mode
• Resonance Mode: Parallel Resonant
• Frequency Initial Stability: ±30 ppm
• Series Resistance: <60 ohms
• Load Capacitance: 10 pF
• Drive Level: 10 µW–100 µW
Power Management
The operating voltage of the device is 1.8V to 3.6V DC, which
is applied to the VBAT pin. The device can be shutdown to a
fully static sleep mode by writing to the FRC END = 1 and END
STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device will enter sleep mode within 35-µs
after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing packet transmission
or reception. When in sleep mode, the on-chip oscillator is
stopped, but the SPI interface remains functional. The device
will wake from sleep mode automatically when the device is
Document #: 38-16015 Rev. *F
commanded to enter transmit or receive mode. When
resuming from sleep mode, there is a short delay while the
oscillator restarts. The device may be configured to assert the
IRQ pin when the oscillator has stabilized.
The output voltage (VREG) of the Power Management Unit
(PMU) is configurable to several minimum values between
2.4V and 2.7V. VREG may be used to provide up to 15 mA
(average load) to external devices. It is possible to disable the
PMU, and to provide an externally regulated DC supply
voltage to the device’s main supply in the range 2.4V to 3.6V.
The PMU also provides a regulated 1.8V supply to the logic.
The PMU has been designed to provide high boost efficiency
(74–85% depending on input voltage, output voltage and load)
when using a Schottky diode and power inductor, eliminating
the need for an external boost converter in many systems
where other components require a boosted voltage. However,
reasonable efficiencies (69-82% depending on input voltage,
output voltage and load) may be achieved when using low cost
components such as SOT23 diodes and 0805 inductors.
The PMU also provides a configurable low battery detection
function which may be read over the SPI interface. One of
seven thresholds between 1.8V and 2.7V may be selected.
The interrupt pin may be configured to assert when the voltage
on the VBAT pin falls below the configured threshold. LV IRQ
is not a latched event. Battery monitoring is disabled when the
device is in sleep mode.
Low Noise Amplifier (LNA) and Received
Signal Strength Indication (RSSI)
The gain of the receiver may be controlled directly by clearing
the AGC EN bit and writing to the Low Noise Amplifier (LNA)
bit of the RX_CFG_ADR register. When the LNA bit is cleared,
the receiver gain is reduced by approximately 20 dB, allowing
accurate reception of very strong received signals (for
example when operating a receiver very close to the transmitter). Approximately 30 dB of receiver attenuation can be
added by setting the Attenuation (ATT) bit; this allows data
reception to be limited to devices at very short ranges.
Disabling AGC and enabling LNA is recommended unless
receiving from a device using external PA.
When the device is in receive mode the RSSI_ADR register
returns the relative signal strength of the on-channel signal
power.
When receiving, the device will automatically measure and
store the relative strength of the signal being received as a 5bit value. An RSSI reading is taken automatically when the
SOP is detected. In addition, a new RSSI reading is taken
every time the previous reading is read from the RSSI_ADR
register, allowing the background RF energy level on any
given channel to be easily measured when RSSI is read when
no signal is being received. A new reading can occur as fast
as once every 12 µs.
Page 7 of 39
A
B
C
NEG2
NEG1
POS
3
"-"
2
"+"
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KB 26 Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
J1
5
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
ROW8
COL18
COL17
COL16
COL15
COL14
COL13
COL12
COL11
COL10
COL9
COL8
COL7
COL6
COL5
COL4
COL3
COL2
COL1
Keyboard Interface
BATT CON 2xAA
BH1
VBAT
1A
2A
1B
2B
R1 is a zero ohm
resistor that should
be installed for
production units
only, following
programming.
A 2-pin jumper
installed from J3.1
to J2.1 enables the
radio to power the
processor. Jumper
removal is required
when programming U2
to disconnect the
radio from the
Miniprog 5V source.
VCC
Serial debug
header
SW PUSHBUTTON
S1
BIND
3
2
1
COL17
COL18
P4_0
P4_1
P4_2
P4_3
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
P1_0
P1_1
P1_2
P1_3 / SSEL
P1_4 / SCLK
P1_5 / SMOSI
P1_6 / SMISO
P1_7
EVCC
P1_0
P1_1
4
0402
XRES
SCLK
SDATA
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P0_0 / CLKIN
P0_1 / CLKOUT
P0_2 / INT0
P0_3 / INT1
P0_4 / INT2
P0_5 / TIO0
P0_6 / TIO1
P0_7
5 PIN HDR
1
2
3
4
5
J2
ISSP
CY7C60123-PVXC
7
6
42
43
34
35
36
37
38
39
40
41
25
26
28
29
30
31
32
33
Layout J3 and J2.1 in a
0.100" spacing
configuration
1 PIN HDR
1
J3
NO LOAD
R1
3 PIN HDR
J4
COL9
COL10
COL11
COL12
COL13
COL14
COL15
COL16
P1_0
P1_1
SW1
nSS
SCK
MOSI
MISO
IRQ
U2
EVCC
1
2
3
4
45
46
47
48
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
0.01 uFd
C19
0402
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
ROW8
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
E
3
100 uFd 10v
+ C18
VBAT
0.01 uFd
C20
1210
No Load
C6
For reference design part numbers, please
refer to the Bill of Materials file
121-26504.xls.
L3
10 uH
An alternate decoupling configuration is
the following:
C6=47uF ceramic
R2=0ohm
C7=.047uF.
For this configuration, it is not required
to load C18.
TV8
VBAT
0402
0402
D1
1
BAT400D
SOT23
IRQ
TV7
2
nSS
SCK
MOSI
MISO
RST
TV2
TV3
TV4
TV5
0805
10 uFd 6.3V
C7
2
4
5
9
14
15
17
18
37
26
24
25
27
28
34
0805
VCC
TP2
10 uFd 6.3V
C12
TP1
VCC
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
L/D
IRQ
SS
SCK
MOSI
MISO
RST
RF VCO
and VCO
Buffer
Filter
U1
CYRF6936
0.047 uFd
C13
0.1 uFd
C17
VBAT
0402
C8
1 uFd 6.3V
47
R3
1 1%
R2
2
2
C15
0402
C16
0.047 uFd
C11
0.047 uFd
0402
The power supply decoupling shown for VBAT0
is a recommended cost effective
configuration:
C6=No Load
R2= 1ohm
C7=10uF ceramic.
For this configuration, it is required that
C18 be installed.
27
5
C9
0.047 uFd
C10
0.047 uFd
C5
0.047 uFd
0402
3
8
6
38
VBAT2
VBAT1
VBAT0
Power Supply
0603
D
4
33
VIO
GND1
12
VDD2
VDD1
VSS2
VSS1
44
24
40
VREG
0402
19
20
21
22
23
31
32
36
39
29
1
30
13
11
TV6
CLKOUT TV1
PACTL
L2
1.8 nH
IND0402
L1
22 nH
IND0603
15 pFd
12 MHz Crystal
Y1
2.0 pFd
C3
C1
Radio Decoupling Caps
Date:
Size
C
Title
0402
1.5 pFd
C4
1
ANT1
WIGGLE 63
Thursday, April 13, 2006
Document Number
REF-13288
LP KEYBOARD
1
Sheet
1
of
CYPRESS SEMICONDUCTOR © 2005
PCB: PDC-9265
E-PAD must be soldered to ground.
RESV
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
XOUT
XTAL
PACTL
RFn
RFp
10
0.47 uFd
RFbias
3
7
16
VCC1
VCC2
VCC3
0402
0402
35
VDD
E-PAD
0402
0402
Document #: 38-16015 Rev. *F
41
0402
1
Rev
*C
A
B
C
D
8.0
1
2
0805
5
CYRF6936
Application Examples
Figure 8-1. Recommended circuit for systems where VBAT may fall below 2.4V.
Page 8 of 39
CYRF6936
Figure 8-2. Recommended bill of materials for systems where VBAT may fall below 2.4V.
Bill of Materials
TITLE
PCA #
SCH #
DATE
LP RDK Keyboard
121-26504
REF-13288
3/17/2005
Item Qty
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
1
1
1
1
1
2
1
6
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
Revision **
Revision *C
CY Part Number
NA
200-?????
730-10012
730-11955
730-11398
730-13322
730-13037
730-13400
730-13404
730-11952
710-13201
730-10794
800-13317
NA
420-11496
420-11964
800-13401
800-11651
800-10594
630-11356
610-13402
800-13368
CYRF6936-40LFC
CY7C60123-PVXC
1 800-13259
1 PDC-9265-*B
1
1
Reference
Description
ANT1
BH1
C1
C3
C4
C5
C12,C7
C8
C9,C10,C11,C13,C15,C16
C17
C18
C20,C19
D1
J1
J2
J3
L1
L2
L3
R2
R3
S1
U1
U2
Y1
PCB
LABEL1
LABEL2
NO LOAD COMPONENTS - DO NOT INSTALL
1 730-13403
C6
29
1 630-10242
R2
30
1 730-13404
C7
31
1 420-10921
J4
32
1 620-10519
R1
33
Cypress Semiconductor Corporation
Document #: 38-16015 Rev. *F
2.5GHZ H-STUB WIGGLE ANTENNA FOR
63MIL PCB
BATTERY CLIPS 2AA CELL CHICONY KB
CAP 15PF 50V CERAMIC NPO 0402
CAP 2.0 PF 50V CERAMIC NPO 0402
CAP 1.5PF 50V CERAMIC NPO 0402 SMD
CAP 0.47 uF 50V CERAMIC X5R 0402
CAP CERAMIC 10UF 6.3V X5R 0805
CAP 1 uF 6.3V CERAMIC X5R 0402
CAP 0.047 uF 16V CERAMIC X5R 0402
CAP 0.1 uF 50V CERAMIC X5R 0402
CAP 100UF 10V ELECT FC
CAP 10000PF 16V CERAMIC 0402 SMD
DIODE SCHOTTKY 0.5A 40V SOT23
PCB COPPER PADS
CONN HDR BRKWAY 5POS STR AU PCB
HEADER 1 POS 0.230 HT MODII .100CL
INDUCTOR 22NH 2% FIXED 0603 SMD
INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD
COIL 10UH 1100MA CHOKE 0805
RES 1.00 OHM 1/8W 1% 0805 SMD
RES 47 OHM 1/16W 5% 0402 SMD
LT SWITCH 6MM 100GF H=7MM TH
IC, LP 2.4 GHz RADIO SoC QFN-40
IC WIRELESS EnCore II CONTROLLER
SSOP48
CRYSTAL 12.00MHZ HC49 SMD
PRINTED CIRCUIT BOARD
Serial Number
PCA #
CAP 47UF 6.3V CERAMIC X5R 1210
RES CHIP 0.0 OHM 1/10W 5% 0805 SMD
CAP 0.047 uF 50V CERAMIC X5R 0402
HEADER 3POS FRIC STRGHT MTA 100
RES ZERO OHM 1/16W 5% 0603 SMD
•
3901 North First Street
•
San Jose
•
CA 95134
•
Manufacturer
Mfr Part Number
NA
CHICONY
Panasonic
Kamet
PANASONIC
Murata
Kamet
Panasonic
AVX
Kamet
Panasonic - ECG
Panasonic - ECG
DIODES INC
NONE
AMP Division of TYCO
AMP/Tyco
Panasonic - ECG
Panasonic - ECG
Newark
Yageo
Panasonic - ECG
Panasonic - ECG
Cypress Semiconductor
Cypress Semiconductor
NA
KBR0108
ECJ-0EC1H150J
C0402C209C5GACTU
ECJ-0EC1H1R5C
GRM155R60J474KE19D
C0805C106K9PACTU
ECJ-0EB0J105M
0402YD473KAT2A
C0402C104K8PACTU
EEU-FC1A101S
ECJ-0EB1C103K
BAT400D-7-F
eCERA
Cypress Semiconductor
XXXXXX
121-26504 **
GF-1200008
PDC-9265-*B
Panasonic
Phycomp USA Inc
AVX
AMP/Tyco
Panasonic - ECG
ECJ-4YB0J476M
9C08052A0R00JLHFT
0402YD473KAT2A
644456-3
ERJ-3GEY0R00V
408-943-2600
103185-5
103185-1
ELJ-RE22NGF2
ELJ-RF1N8DF
30K5421
9C08052A1R00FKHFT
ERJ-2GEJ470X
EVQ-PAC07K
CYRF6936 Rev A5
CY7C60123-PVXC
Page 1 of 1
Page 9 of 39
A
B
C
5
VBUS
DM
DP
GND
S1
S2
1
2
3
4
5
6
USB A SMT PLUG
J1
R1
zero
VBUS
DM
DP
5V
5V
R2
620
0805
5V
SSEL/P1_3
SCLK/P1_4
MOSI/P1_5
MISO/P1_6
CY7C63803-SXC
13
14
15
16
DM/P1_1
DP/P1_0
S1
2A
2B
4.7 uFd
C13
C
C
0805
VCC
Power Supply
SW RA PUSH
1A
1B
D1
4
3
SW1
nLED2
nLED1
2.2 uFd
C14
LED Green Red
RD
GR
"BIND"
2
1
"CONNECT/ACTIVITY"
nSS
SCK
MOSI
MISO
10
9
U2
4
0402
P0_0
P0_1
P0_2/INT0
P0_3/INT1
P0_4/INT2
P0_5/TIO0
P0_6/TIO1
VREG
7
6
5
4
3
2
1
12
1500 pFd
C12
RST
nLED2
nLED1
IRQ
SW1
VCC
3
IRQ
nSS
SCK
MOSI
MISO
RST
U1
CYRF6936
0402
0.047 uFd
C6
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
L/D
IRQ
SS
SCK
MOSI
MISO
RST
VCC
2
4
5
9
14
15
17
18
37
26
24
25
27
28
34
VCC
0402
8
6
38
5V
3
0.047 uFd
C7
0402
19
20
21
22
23
31
32
36
39
29
1
30
13
11
10
TV1
2
1.8 nH
IND0402
22 nH
IND0603
TV-20R
L2
L1
15 pFd
C1
0.047 uFd
C8
0402
0.047 uFd
C9
2
0402
0.047 uFd
C10
0402
0.047 uFd
C11
0402
12 MHz Crystal
Y1
2.0 pFd
C3
0402
E-PAD must be soldered to ground.
RESV
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
XOUT
XTAL
PACTL
RFn
RFp
0402
0.47 uFd
C5
RFbias
40
11
VCC
VSS
8
33
VIO
VBAT2
VBAT1
VBAT0
GND1
12
3
7
16
VCC1
VCC2
VCC3
VREG
E-PAD
35
VDD
4
1.5 pFd
C4
ANT1
WIGGLE 32
1
Date:
Size
C
Title
1
Wednesday, April 12, 2006
Document Number
REF-13287
LP Dongle II
CYPRESS SEMICONDUCTOR © 2005
PCB: PDC - 9263
1
2
D
0402
Document #: 38-16015 Rev. *F
41
0402
5
Sheet
1
of
1
Rev
*A
A
B
C
D
CYRF6936
Figure 8-3. Recommended circuit for systems where VBAT is 2.4V to 3.6V (PMU disabled).
Page 10 of 39
0402
CYRF6936
Figure 8-4. Recommended bill of materials for systems where VBAT is 2.4V to 3.6V (PMU disabled).
Bill of Materials
TITLE
PCA #
SCH #
DATE
LP RDK Dongle II
121-26305
REF-13287
3/24/2005
Item Qty
Revision **
Revision *A
CY Part Number
Reference
1
2
3
4
5
6
7
8
1
1
1
1
1
6
1
1
NA
730-10012
730-11955
730-11398
730-13322
730-13404
730-11953
730-13400
ANT1
C1
C3
C4
C5
C6,C7,C8,C9,C10,C11
C12
C13
9
10
11
12
13
14
15
16
17
1
1
1
1
1
1
1
1
1
730-12003
800-13333
420-13046
800-13401
800-11651
610-10343
610-13472
200-13471
CYRF6936-40LFC
C14
D1
J1
L1
L2
R1
R2
S1
U1
18
19
20
21
22
1 CY7C63803-SXC
1 800-13259
1 PDC-9263-*B
1
1
Document #: 38-16015 Rev. *F
CAP CER 2.2UF 10V 10% X7R 0805
LED GREEN/RED BICOLOR 1210 SMD
CONN USB PLUG TYPE A PCB SMT
INDUCTOR 22NH 2% FIXED 0603 SMD
INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD
RES ZERO OHM 1/16W 0402 SMD
RES CHIP 620 OHM 1/16W 5% 0402 SMD
SWITCH LT 3.5MMX2.9MM 160GF SMD
IC, LP 2.4 GHz RADIO SoC QFN-40
IC LOW-SPEED USB ENCORE II
CONTROLLER SOIC16
CRYSTAL 12.00MHZ HC49 SMD
PRINTED CIRCUIT BOARD
Serial Number
PCA #
U2
Y1
PCB
LABEL1
LABEL2
Cypress Semiconductor Corporation
Description
2.5GHZ H-STUB WIGGLE ANTENNA FOR
32MIL PCB
CAP 15PF 50V CERAMIC NPO 0402
CAP 2.0 PF 50V CERAMIC NPO 0402
CAP 1.5PF 50V CERAMIC NPO 0402 SMD
CAP 0.47 uF 50V CERAMIC X5R 0402
CAP 0.047 uF 50V CERAMIC X5R 0402
CAP 1500PF 50V CERAMIC X7R 0402
CAP CERAMIC 4.7UF 6.3V XR5 0805
•
3901 North First Street
•
San Jose
•
CA 95134
•
Manufacturer
Mfr Part Number
NA
Panasonic
Kemet
PANASONIC
Murata
AVX
Kemet
Kemet
Murata Electronics North
America
LITEON
ACON
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
Cypress Semiconductor
NA
ECJ-0EC1H150J
C0402C209C5GACTU
ECJ-0EC1H1R5C
GRM155R60J474KE19D
0402YD473KAT2A
C0402C152K5RACTU
C0805C475K9PACTU
Cypress Semiconductor
eCERA
Cypress Semiconductor
XXXXXX
121-26305 **
CY7C63803-SXC
GF-1200008
PDC-9263-*B
408-943-2600
GRM21BR71A225KA01L
LTST-C155KGJRKT
UAR72-4N5J10
ELJ-RE22NGF2
ELJ-RF1N8DF
ERJ-2GE0R00X
ERJ-2GEJ621X
EVQ-P7J01K
CYRF6936 Rev A5
Page 1 of 1
Page 11 of 39
CYRF6936
9.0
Register Descriptions
All registers are read and writable, except where noted. Registers may be written to or read from either individually or in sequential
groups.
Table 9-1. Register Map Summary
Address
0x00
0x01
Mnemonic
CHANNEL_ADR
TX_LENGTH_ADR
b7
Not Used
b6
0x02
b5
TX_CTRL_ADR
TX GO
TX CLR
0x03
TX_CFG_ADR
0x04
TX_IRQ_STATUS_ADR
Not Used
OS
IRQ
Not Used
LV
IRQ
0x05
0x06
RX_CTRL_ADR
RX GO
RSVD
TXB15
IRQEN
DATA CODE
LENGTH
TXB15
IRQ
RXB16
IRQEN
RX_CFG_ADR
AGC EN
RXOW
IRQ
RX ACK
LNA
SOPDET
IRQ
PKT ERR
ATT
RXB16
IRQ
EOP ERR
PMU EN
LVIRQ EN
XOUT FN
IRQ OD
IRQ POL
XOUT OP
MISO OP
ACK EN
Not Used
SOP EN
SOP LEN
Not Used
Not Used
Not Used
Not Used
SOP
Not Used
HEN
PMU SEN
XSIRQ EN
MISO OD
PACTL OP
FRC END
LEN EN
Not Used
Not Used
LNA
HINT
Not Used
RSVD
Not Used
RSVD
Not Used
FRC SEN
b4
b3
Channel
TX Length
TXB8
TXB0
IRQEN
IRQEN
RX_IRQ_STATUS_ADR
RX_STATUS_ADR
RX_COUNT_ADR
RX_LENGTH_ADR
PWR_CTRL_ADR
XTAL_CTRL_ADR
IO_CFG_ADR
GPIO_CTRL_ADR
XACT_CFG_ADR
FRAMING_CFG_ADR
DATA32_THOLD_ADR
DATA64_THOLD_ADR
RSSI_ADR
EOP_CTRL_ADR
CRC_SEED_LSB_ADR
CRC_SEED_MSB_ADR
TX_CRC_LSB_ADR
TX_CRC_MSB_ADR
RX_CRC_LSB_ADR
RX_CRC_MSB_ADR
TX_OFFSET_LSB_ADR
TX_OFFSET_MSB_ADR
MODE_OVERRIDE_ADR
0x1E
RX_OVERRIDE_ADR
ACK RX
RXTX DLY
MAN RXACK
0x1F
0x26
TX_OVERRIDE_ADR
XTAL_CFG_ADR
ACK TX
RSVD
FRC PRE
RSVD
RSVD
RSVD
0x27
CLK_OVERRIDE_ADR
RSVD
RSVD
RSVD
0x28
CLK_EN_ADR
RSVD
RSVD
RSVD
RSVD
RSVD
0x29
RX_ABORT_ADR
RSVD
RSVD
ABORT EN
RSVD
RSVD
0x32
AUTO_CAL_TIME_ADR
0x35
AUTO_CAL_OFFSET_ADR
0x39
ANALOG_CTRL_ADR
RSVD
RSVD
b1
b0
TXBERR
IRQEN
TXC
IRQEN
TXE
IRQEN
DATA MODE
PA SETTING
TXB8
TXB0
TXBERR
TXC
TXE
IRQ
IRQ
IRQ
IRQ
IRQ
RXB8
RXB1
RXBERR
RXC
RXE
IRQEN
IRQEN
IRQEN
IRQEN
IRQEN
FAST TURN
HILO
EN
Not Used
RXOW EN
VLD EN
RXB8
RXB1
RXBERR
RXC
RXE
IRQ
IRQ
IRQ
IRQ
IRQ
CRC0
Bad CRC
RX Code
RX Data Mode
RX Count
RX Length
Not Used
LVI TH
PMU OUTV
Not Used
Not Used
FREQ
XOUT OD PACTL OD PACTL GPIO
SPI 3PIN
IRQ GPIO
IRQ OP
XOUT IP
MISO IP
PACTL IP
IRQ IP
END STATE
ACK TO
SOP TH
Not Used
TH32
TH64
RSSI
EOP
CRC SEED LSB
CRC SEED MSB
CRC LSB
CRC MSB
CRC LSB
CRC MSB
STRIM LSB
Not Used
STRIM MSB
FRC AWAKE
Not Used
Not Used
RST
FRC
RXDR
DIS CRC0 DIS RXCRC
ACE
Not Used
MAN
TXACK
OVRD ACK DIS TXCRC
RSVD
TX INV
RSVD
START DLY
RSVD
RSVD
RSVD
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
RSVD
b2
RSVD
RSVD
RSVD
Default[1]
-1001000
00000000
00000011
Access[1]
-bbbbbbb
bbbbbbbb
bbbbbbbb
--000101
--bbbbbb
--------
rrrrrrrr
00000111
bbbbbbbb
10010-10
bbbbb-bb
--------
brrrrrrr
-------00000000
00000000
10100000
000--100
00000000
0000---1-000000
10100101
----0100
---01010
0-100000
10100100
00000000
00000000
--------------11111111
11111111
00000000
----0000
00000--0
0000000-
rrrrrrrr
rrrrrrrr
rrrrrrrr
bbb-bbbb
bbb--bbb
bbbbbbbb
bbbbrrrr
b-bbbbbb
bbbbbbbb
----bbbb
---bbbbb
r-rrrrrr
bbbbbbbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
rrrrrrrr
rrrrrrrr
rrrrrrrr
bbbbbbbb
----bbbb
wwwww--w
bbbbbbb-
00000000
bbbbbbbb
00000000
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
RXF
RSVD
00000000
RSVD
RXF
RSVD
00000000
RSVD
RSVD
RSVD
00000000
AUTO_CAL_TIME
00000011
AUTO_CAL_OFFSET
00000000
RSVD
RSVD
RSVD
RX INV
ALL SLOW
00000000
Register Files
0x20
TX_BUFFER_ADR
TX Buffer File
--------
0x21
RX_BUFFER_ADR
RX Buffer File
--------
wwwwwww
w
rrrrrrrr
0x22
0x23
0x24
0x25
SOP_CODE_ADR
DATA_CODE_ADR
PREAMBLE_ADR
MFG_ID_ADR
SOP Code File
Data Code File
Preamble File
MFG ID File
Note 2
Note 3
Note 4
NA
bbbbbbbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
Notes
1. b = read/write, r = read only, w = write only, - = not used, default value is undefined.
2. SOP_CODE_ADR default = 0x17FF9E213690C782.
3. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.
4. PREAMBLE_ADR default = 0x333302.
Document #: 38-16015 Rev. *F
Page 12 of 39
CYRF6936
Mnemonic
CHANNEL_ADR
Address
0x00
Bit
7
6
5
4
3
2
1
0
Default
-
1
0
0
1
0
0
0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Function
Not Used
Channel
Bit 7
Bits 6:0
Not Used.
This field selects the channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 are not valid. The default channel
is a fast channel above the frequency typically used in non-overlapping WiFi systems. Any write to this register will impact the
time it takes the synthesizer to settle.
fast (100-µs) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96
medium (180−µs) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94
slow (270-µs) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97
Usable channels subject to regulation.
Mnemonic
TX_LENGTH_ADR
Address
0x01
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Function
Bits 7:0
TX Length
This register sets the length of the packet to be transmitted. A length of zero is valid, and will transmit a packet with SOP, length
and CRC16 fields (if enabled), but no data field. Packet lengths of more than 16 bytes will require that some data bytes be written after transmission of the packet has begun. Typically, length is updated prior to setting TX GO. The maximum packet length
for all packets is 40 bytes except for framed 64-chip DDR where the maximum packet length is 16 bytes.
Maximum packet length is limited by the delta between the transmitter and receiver crystals of 60-ppm or better.
Mnemonic
TX_CTRL_ADR
Address
0x02
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TX CLR
TXB15
IRQEN
TXB8
IRQEN
TXB0
IRQEN
TXBERR
IRQEN
TXC
IRQEN
TXE
IRQEN
Read/Write
Function
TX GO
Bit 7
Start Transmission. Setting this bit triggers the transmission of a packet. Writing a 0 to this flag has no effect. This bit is cleared
automatically at the end of packet transmission. The transmit buffer may be loaded either before or after setting this bit. If data
is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth),
the length of the SOP code, the length of preamble, and the packet data rate. For example, if starting from idle mode on a fast
channel in 8DR mode with 32 chip SOP codes the time available is 100 µs (synth start) + 32 µs (preamble) + 64 µs (SOP
length) + 32 µs (length byte) = 228 µs. If there are no bytes in the TX buffer at the end of transmission of the length field, a
TXBERR IRQ will occur and transmission will abort.
Bit 6
Clear TX Buffer. Writing a 1 to this register clears the transmit buffer. Writing a 0 to this bit has no effect. The previous packet
(16 or fewer bytes) may be retransmitted by setting TX GO and not setting this bit. If a new transmit packet is to be loaded
before/after the TX GO bit has been set, then this bit should be set before loading a new transmit packet to the buffer.
Bit 5
Buffer Not Full Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 4
Buffer Half Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 3
Buffer Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 2
Buffer Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 1
Transmission Complete Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for
description.
Bit 0
Transmit Error Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for description.
Document #: 38-16015 Rev. *F
Page 13 of 39
CYRF6936
Mnemonic
TX_CFG_ADR
4
3
2
0x03
7
6
Default
-
-
0
0
0
1
0
1
Read/Write
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Not Used
Not Used
Data Code
Length
Function
5
Address
Bit
Data Mode
1
0
PA Setting
Bit 5
Data Code Length. This bit selects the length of the DATA_CODE_ADR code for the data portion of the packet. This bit is
ignored when the data mode is set to GFSK. 1 = 64 chip codes. 0 = 32 chip codes.
Bits 4:3
Data Mode. This field sets the data transmission mode. 00 = 1-Mbps GFSK. 01 = 8DR Mode. 10 = DDR Mode. 11 = SDR Mode.
It is recommended that firmware sets the ALL SLOW bit in register ANALOG_CTRL_ADR when using GFSK data rate mode.
Bits 2:0
PA Setting. This field sets the transmit signal strength. 0 = –30 dBm, 1 = –25 dBm, 2 = –20 dBm, 3 = –15 dBm, 4 = –10 dBm,
5 = –5 dBm, 6 = 0 dBm, 7 = +4 dBm.
Mnemonic
Bit
TX_IRQ_STATUS_ADR
7
6
5
Address
4
3
2
0x04
1
0
Default
-
-
-
-
-
-
-
-
Read/Write
R
R
R
R
R
R
R
R
OS IRQ
LV IRQ
TXB15 IRQ
TXB8 IRQ
TXB0 IRQ
TXBERR IRQ
TXC IRQ
TXE IRQ
Function
The state of all IRQ status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state
whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags
may change value at different times in response to a single event).
Bit 7
Oscillator Stable IRQ Status. This bit is set when the internal crystal oscillator has settled (synthesizer sequence starts).
Bit 6
Low Voltage Interrupt Status. This bit is set when the voltage on VBAT is below the LVI threshold (see PWR_CTL_ADR). This
interrupt is automatically disabled whenever the PMU is disabled. When enabled, this bit reflects the voltage on VBAT.
Bit 5
Buffer Not Full Interrupt Status. This bit is set whenever there are 15 or fewer bytes remaining in the transmit buffer.
Bit 4
Buffer Half Empty Interrupt Status. This bit is set whenever there are 8 or fewer bytes remaining in the transmit buffer.
Bit 3
Buffer Empty Interrupt Status. This bit is set at any time that the transmit buffer is empty.
Bit 2
Buffer Error Interrupt Status. This IRQ is triggered by either of two events: (1) When the transmit buffer (TX_BUFFER_ADR) is
empty and the number of bytes remaining to be transmitted is greater than zero. (2) When a byte is written to the transmit buffer
and the buffer is already full. This IRQ is cleared by setting bit TX CLR in TX_CTRL_ADR.
Bit 1
Transmission Complete Interrupt Status. This IRQ is triggered when transmission is complete. If transaction mode is not
enabled then this interrupt is triggered immediately after transmission of the last bit of the CRC16. If transaction mode is
enabled, this interrupt is triggered at the end of a transaction. Reading this register clears this bit. TXC IRQ and TXE IRQ flags
may change value at different times in response to a single event. If transaction mode is enabled and the first read of this register returns TXC IRQ=1 and TXE IRQ=0 then firmware must execute a second read to this register to determine if an error
occurred by examining the status of TXE. There can be a case when this bit is not triggered when ACK EN = 1 and there is an
error in transmission. If the first read of this register returns TXC IRQ = 1 and TXE IRQ = 1 then the firmware must not execute
a second read to this register for a given transaction. If an ACK is received RXC IRQ and RXE IRQ may be asserted instead of
TXC IRQ and TXE IRQ.
Bit 0
Transmit Error Interrupt Status. This IRQ is triggered when there is an error in transmission. This interrupt is only applicable to
transaction mode. It is triggered whenever no valid ACK packet is received within the ACK timeout period. Reading this register
clears this bit. See TXC IRQ, above.
Document #: 38-16015 Rev. *F
Page 14 of 39
CYRF6936
Mnemonic
RX_CTRL_ADR
Address
0x05
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RSVD
RXB16
IRQEN
RXB8
IRQEN
RXB1
IRQEN
RXBERR
IRQEN
RXC
IRQEN
RXE
IRQEN
Read/Write
Function
RX GO
Bit 7
Start Receive. Setting this bit causes the device to transition to receive mode. If necessary, the crystal oscillator and synthesizer
will start automatically after this bit is set. Firmware must never clear this bit. This bit must not be set again until after it self
clears. The recommended method to exit receive mode when an error has occurred is to force END STATE and then dummy
read all RX_COUNT_ADR bytes from RX_BUFFER_ADR or poll RSSI_ADR.SOP (bit 7) until set. See XACT_CFG_ADR and
RX_ABORT_ADR for description.
Bit 6
Bit 5
Reserved. Must be zero.
Buffer Full Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 4
Buffer Half Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 3
Buffer Not Empty Interrupt Enable. RXB1 IRQEN must not be set when RXB8 IRQEN is set and vice versa. See
RX_IRQ_STATUS_ADR for description.
Bit 2
Buffer Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 1
Packet Reception Complete Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 0
Receive Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Document #: 38-16015 Rev. *F
Page 15 of 39
CYRF6936
Mnemonic
RX_CFG_ADR
Address
0x06
Bit
7
6
5
4
3
2
1
0
Default
1
0
0
1
0
-
1
0
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
AGC EN
LNA
ATT
HILO
FAST TURN
EN
Not Used
RXOW EN
VLD EN
Read/Write
Function
Status bits are non-atomic (different flags may change value at different times in response to a single event).
Bit 7
Automatic Gain Control (AGC) Enable. When this bit is set, AGC is enabled, and the LNA is controlled by the AGC circuit.
When this bit is cleared the LNA is controlled manually using the LNA bit. Typical applications will clear this bit during initialization. It is recommended that this bit be cleared and bit 6 (LNA) be set unless the device will be used in a system where it may
receive data from a device using an external PA to transmit signals at >+4 dBm.
Bit 6
Low Noise Amplifier (LNA) Manual Control. When AGC EN (Bit 7) is cleared, this bit controls the state of the receiver LNA;
when AGC EN is set, this bit has no effect. Setting this bit enables the LNA; clearing this bit disables the LNA. Device current in
receive mode is slightly lower when the LNA is disabled. Typical applications will set this bit during initialization.
Bit 5
Receive Attenuator Enable. Setting this bit enables the receiver attenuator. The receiver attenuator may be used to de-sensitize the receiver so that only very strong signals may be received. This bit should only be set when the AGC EN is disabled and
the LNA is manually disabled.
Bit 4
HILO. When FAST TURN EN is set, this bit is used to select whether the device will use the high frequency for the channel
selected, or the low frequency. 1 = hi; 0 = lo. When FAST TURN EN is not enabled this also controls the highlow bit to the
receiver and should be left at the default value of 1 for high side receive injection. Typical applications will clear this bit during
initialization.
Bit 3
Fast Turn Mode Enable. When this bit is set, the HILO bit determines whether the device receives data transmitted 1MHz
above the RX Synthesizer frequency or 1 MHz below the receiver synthesizer frequency. Use of this mode allows for very fast
turn-around, because the same synthesizer frequency may be used for both transmit and receive, thus eliminating the synthesizer resettling period between transmit and receive. Note that when this bit is set, and the HILO bit is cleared, received data
bits are automatically inverted to compensate for the inversion of data received on the “image” frequency. Typical applications
will set this bit during initialization.
Bit 1
Overwrite Enable. When this bit is set, if an SOP is detected while the receive buffer is not empty, then the existing contents of
receive buffer are lost, and the new packet is loaded into the receive buffer. When this bit is set, the RXOW IRQ is enabled. If
this bit is cleared, then the receive buffer may not be over-written by a new packet, and whenever the receive buffer is not
empty SOP conditions are ignored, and it is not possible to receive data until the previously received packet has been completely read from the receive buffer.
Bit 0
Valid Flag Enable. When this bit is set, the receive buffer can store up to 8 bytes of data interleaved with valids (data0, valids0,
data1, valids1,...). Typically, this bit is set only when interoperability with first generation devices is desired. See
RX_BUFFER_ADR for more detail.
Document #: 38-16015 Rev. *F
Page 16 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
RX_IRQ_STATUS_ADR
7
6
5
Address
4
3
2
1
0x07
0
-
-
-
-
-
-
-
-
R/W
R
R
R
R
R
R
R
RXOW IRQ
SOPDET IRQ
RXB16 IRQ
RXB8 IRQ
RXB1 IRQ
RXBERR IRQ
RXC IRQ
RXE IRQ
The state of all IRQ Status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state
whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags
may change value at different times in response to a single event). In particular, standard error handling is only effective if the premature
termination of a transmission due to an exception does not leave the device in an inconsistent state.
Bit 7
Bit 6
Receive Overwrite Interrupt Status. This IRQ is triggered when the receive buffer is over-written by a packet being received
before the previous packet has been read from the buffer. This bit is cleared by writing any value to this register. This condition
is only possible when the RXOW EN bit in RX_CFG_ADR is set. This bit must be written “1” by firmware before the new packet
may be read from the receive buffer.
Start of packet detect. This bit is set whenever the start of packet symbol is detected.
Bit 5
Receive Buffer Full Interrupt Status. This bit is set whenever the receive buffer is full, and cleared otherwise.
Bit 4
Receive Buffer Half Full Interrupt Status. This bit is set whenever there are 8 or more bytes remaining in the receive buffer.
Firmware must read exactly eight bytes when reading RXB8 IRQ.
Receive Buffer Not Empty Interrupt Status. This bit is set at any time that there are 1 or more bytes in the receive buffer., and
cleared when the receive buffer is empty. It is possible, in rare cases, that the last byte of a packet may remain in the buffer
even though the RXB1 IRQ flag has cleared. This can ONLY happen on the last byte of a packet and only if the packet data is
being read out of the buffer while the packet is still being received. The flag is trustworthy under all other conditions, and for all
bytes prior to the last. When using RXB1 IRQ and unloading the packet data during reception, the user should be sure to check
the RX_COUNT_ADR value after the RXC IRQ/RXE IRQ is set and unload the last remaining bytes if the number of bytes
unloaded is less than the reported count, eventhough the RXB1 IRQ is not set.
Bit 3
Bit 2
Receive Buffer Error Interrupt Status. This IRQ is triggered in one of two ways: (1) When the receive buffer is empty and there
is an attempt to read data. (2) When the receive buffer is full and more data is received. This flag is cleared when RX GO is set
and a SOP is received.
Bit 1
Packet Receive Complete Interrupt Status. This IRQ is triggered when a packet has been received. If transaction mode is
enabled, then this bit is not set until after transmission of the ACK. If transaction mode is not enabled then this bit is set as soon
as a valid packet is received. This bit is cleared when this register is read. RXC IRQ and RXE IRQ flags may change value at
different times in response to a single event. There are cases when this bit is not triggered when ACK EN = 1 and there is an
error in reception. Therefore, firmware should examine RXC IRQ, RXE IRQ, and CRC 0 to determine receive status. If the first
read of this register returns RXC IRQ = 1 and RXE IRQ = 0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of RXE IRQ. If the first read of this register returns RXC IRQ = 1 and RXE IRQ
= 1 then the firmware must not execute a second read to this register for a given transaction.
Bit 0
Receive Error Interrupt Status. This IRQ is triggered when there is an error in reception. It is triggered whenever a packet is
received with a bad CRC16, an unexpected EOP is detected, a packet type (data or ACK) mismatch, or a packet is dropped
because the receive buffer is still not empty when the next packet starts. The exact cause of the error may be determined by
reading RX_STATUS_ADR. This bit is cleared when this register is read.
Document #: 38-16015 Rev. *F
Page 17 of 39
CYRF6936
Mnemonic
Bit
RX_STATUS_ADR
7
6
5
Address
4
3
2
1
0x08
0
Default
-
-
-
-
-
-
-
-
Read/Write
R
R
R
R
R
R
R
R
RX ACK
PKT ERR
EOP ERR
CRC0
Bad CRC
RX Code
Function
RX Data Mode
It is expected that firmware does not read this register until after RX GO self clears. Status bits are non-atomic (different flags may change
value at different times in response to a single event).
Bit 7
RX Packet Type. This bit is set when the received packet is an ACK packet, and cleared when the received packet is a standard
packet.
Bit 6
Receive Packet Type Error. This bit is set when the packet type received is what not was expected and cleared when the
packet type received was as expected. For example, if a data packet is expected and an ACK is received, this bit will be set.
Bit 5
Unexpected EOP. This bit is set when an EOP is detected before the expected data length and CRC16 fields have been
received. This bit is cleared when SOP pattern for the next packet has been received. This includes the case where there are
invalid bits detected in the length field and the length field is forced to 0.
Bit 4
Zero-seed CRC16. This bit is set whenever the CRC16 of the last received packet has a zero seed.
Bit 3
Bad CRC16. This bit is set when the CRC16 of the last received packet is incorrect.
Bit 2
Receive Code Length. This bit indicates the DATA_CODE_ADR code length used in the last correctly received packet. 1 = 64chip code, 0 = 32-chip code.
Bits 1:0
Receive Data Mode. These bits indicate the data mode of the last correctly received packet. 00 = 1-Mbps GFSK 01 = 8DR 10 =
DDR. 11 = Not Valid. These bits do not apply to unframed packets.
Mnemonic
RX_COUNT_ADR
Address
0x09
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Function
RX Count
Count bits are non-atomic (updated at different times).
Bits 7:0
This register contains the total number of payload bytes received during reception of the current packet. After packet reception
is complete, this register will match the value in RX_LENGTH_ADR unless there was a packet error. This register is cleared
when RX_LENGTH_ADR is automatically loaded, if length is enabled, after the SOP. Count should not be read when
RX_GO=1 during a transaction.
Mnemonic
Bit
RX_LENGTH_ADR
7
6
5
Address
4
3
2
1
0x0A
0
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Function
RX Length
Length bits are non-atomic (different flags may change value at different times in response to a single event).
Bits 7:0
This register contains the length field which is updated with the reception of a new length field (shortly after start of packet
detected). If there is an error in the received length field, 0x00 is loaded instead, except when using GFSK datarate, and an
error is flagged.
Document #: 38-16015 Rev. *F
Page 18 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
PWR_CTRL_ADR
7
6
Address
5
4
3
2
0x0B
1
0
1
0
1
-
0
0
0
0
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
PMU EN
LVIRQ EN
PMU SEN
Not Used
LVI TH
PMU OUTV
Bit 7
Power Management Unit (PMU) Enable. Setting this bit enables the PMU. When the PMU is disabled, or if the PMU is enabled
and the VBAT voltage is above the value set in Bits 1:0 of this register, the VREG pin is internally connected to the VBAT pin. if the
PMU is enabled and the VBAT voltage is below the value set by PMU OUTV, then the PMU will boost the VREG pin to a voltage
not less than the value set by PMU OUTV.
Bit 6
Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the VBAT voltage
falls below the threshold set by LVI TH, then a low voltage interrupt will be generated. The LVI is not available when the device
is in sleep mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled.
Bit 5
PMU Sleep Mode Enable. If this bit is set, the PMU will continue to operate normally when the device is in sleep mode. If this bit
is not set, then the PMU is disabled when the device is in sleep mode. In this case, if VBAT is below the PMU OUTV voltage and
PMU EN is set, when the device enters sleep mode the VREG voltage falls to the VBAT voltage as the VREG capacitors discharge.
Bits 3:2
Low Voltage Interrupt Threshold. This field sets the voltage on VBAT at which the LVI is triggered. 11 = 1.8V; 10 = 2.0V;
01 = 2.2V; 00 = PMU OUTV voltage.
Bits 1:0
PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V; 10 = 2.5V; 01 = 2.6V; 00 = 2.7V. When
the PMU is active, the voltage output by the PMU on VREG will never be less than this voltage provided that the total load on the
VREG pin is less than the specified maximum value, and the voltage in VBAT is greater than the specified minimum value.
Mnemonic
Bit
Default
Read/Write
Function
XTAL_CTRL_ADR
7
6
Address
5
4
3
2
1
0x0C
0
0
0
0
-
-
1
0
0
R/W
R/W
R/W
-
-
R/W
R/W
R/W
XSIRQ EN
Not Used
Not Used
XOUT FN
FREQ
Bits 7:6
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT
FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire
mode then the MISO pin will output a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to
GPIO mode, and set the GPIO state in IO_CFG_ADR.
Bit 5
Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event
when the crystal has stabilized after the device has woken from sleep mode. This event is cleared by writing zero to this bit.
Bits 2:0
XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz; 1 = 6 MHz,
2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
Document #: 38-16015 Rev. *F
Page 19 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
IO_CFG_ADR
7
6
5
Address
4
3
2
0x0D
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ OD
IRQ POL
MISO OD
XOUT OD
PACTL OD
PACTL GPIO
SPI 3PIN
IRQ GPIO
To use a GPIO pin as an input, the output mode must be set to open drain, and a “1” written to the corresponding output register bit.
Bit 7
IRQ Pin Drive Strength. Setting this bit configures the IRQ pin as an open drain output. Clearing this bit configures the IRQ pin
as a standard CMOS output, with the output “1” drive voltage being equal to the VIO pin voltage.
Bit 6
IRQ Polarity. Setting this bit configures the IRQ signal polarity to be active HIGH. Clearing this bit configures the IRQ signal
polarity to be active low.
Bit 5
MISO Pin Drive Strength. Setting this bit configures the MISO pin as an open drain output. Clearing this bit configures the
MISO pin as a standard CMOS output, with the output “1” drive voltage being equal to the VIO pin voltage.
Bit 4
XOUT Pin Drive Strength. Setting this bit configures the XOUT pin as an open drain output. Clearing this bit configures the
XOUT pin as a standard CMOS output, with the output “1” drive voltage being equal to the VIO pin voltage.
Bit 3
PACTL Pin Drive Strength. Setting this bit configures the PACTL pin as an open drain output. Clearing this bit configures the
PACTL pin as a standard CMOS output, with the output “1” drive voltage being equal to the VIO pin voltage.
Bit 2
PACTL Pin Function. When this bit is set the PACTL pin is available for use as a GPIO.
Bit 1
SPI Mode. When this bit is cleared, the SPI interface acts as a standard 4-wire SPI Slave interface. When this bit is set, the SPI
interface operates in “3-Wire Mode” combining MISO and MOSI on the same pin (SDAT), and the MISO pin is available as a
GPIO pin.
Bit 0
IRQ Pin Function. When this bit is cleared, the IRQ pin is asserted when an IRQ is active; the polarity of this IRQ signal is configurable in IRQ POL. When this bit is set, the IRQ pin is available for use as a GPIO pin, and the IRQ function is multiplexed
onto the MOSI pin. In this case the IRQ signal state is presented on the MOSI pin whenever the SS signal is inactive (HIGH).
Mnemonic
Bit
Default
Read/Write
Function
GPIO_CTRL_ADR
7
6
5
Address
4
3
2
0x0E
1
0
0
0
0
0
-
-
-
-
R/W
R/W
R/W
R/W
R
R
R
R
XOUT OP
MISO OP
PACTL OP
IRQ OP
XOUT IP
MISO IP
PACTL IP
IRQ IP
To use a GPIO pin as an input, the output mode must be set to open drain, and a “1” written to the corresponding output register bit.
Bit 7
XOUT Output. When the XOUT pin is configured to be a GPIO, the state of this bit sets the output state of the XOUT pin.
Bit 6
MISO Output. When the MISO pin is configured to be a GPIO, the state of this bit sets the output state of the MISO pin.
Bit 5
PACTL Output. When the PACTL pin is configured to be a GPIO, the state of this bit sets the output state of the PACTL pin.
Bit 4
IRQ Output. When the IRQ pin is configured to be a GPIO, the state of this bit sets the output state of the IRQ pin.
Bit 3
XOUT Input. The state of this bit reflects the voltage on the XOUT pin.
Bit 2
MISO Input. The state of this bit reflects the voltage on the MISO pin.
Bit 1
PACTL Input. The state of this bit reflects the voltage on the PACTL pin.
Bit 0
IRQ Input. The state of this bit reflects the voltage on the IRQ pin.
Document #: 38-16015 Rev. *F
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CYRF6936
Mnemonic
XACT_CFG_ADR
Address
0x0F
Bit
7
6
5
4
3
2
1
0
Default
1
-
0
0
0
0
0
0
R/W
R/W
R/W
R/W
Read/Write
Function
R/W
-
R/W
ACK EN
Not Used
FRC END
END STATE
R/W
ACK TO
Bit 7
Acknowledge Enable. When this bit is set, an ACK packet is automatically transmitted whenever a valid packet is received; in
this case the device is considered to be in transaction mode. After transmission of the ACK packet, the device automatically
transitions to the END STATE. When this bit is cleared, the device transitions directly to the END STATE immediately after the
end of packet transmission. This bit affects both transmitting and receiving devices.
Bit 5
Force End State. Setting this bit forces a transition to the state set in END STATE. By setting the desired END STATE at the
same time as setting this bit the device may be forced to immediately transition from its current state to any other state. This bit
is automatically cleared upon completion. Firmware MUST never try to force END STATE while TX GO is set, nor when RX GO
is set and a SOP has already been received (packet reception already in progress).
Bits 4:2
Transaction End State. This field defines the mode to which the device transitions after receiving or transmitting a packet. 000
= Sleep Mode; 001 = Idle Mode; 010 = Synth Mode (TX); 011 = Synth Mode (RX); 100 = RX Mode. In normal use, this field will
typically be set to 000 or 001 when the device is transmitting packets, and 100 when the device is receiving packets. Note that
when the device transitions to receive mode as an END STATE, the receiver must still be armed by setting RX GO before the
device can begin receiving data. If the system only support packets <=16 bytes then firmware should examine RXC IRQ and
RXE IRQ to determine the status of the packet. If the system supports packets > 16 bytes ensure that END STATE is not sleep,
force RXF=1, perform receive operation, force RXF=0, and if necessary set END STATE back to sleep.
Bits 1:0
ACK Timeout. When the device is configured for transaction mode, this field sets the timeout period after transmission of a
packet during which an ACK must be correctly received in order to prevent a transmit error condition from being detected. This
timeout period is expressed in terms of a number of SOP_CODE_ADR code lengths; if SOP LEN is set, then the timeout period
is this value multiplied by 64 µs and if SOP LEN is cleared then the timeout is this value multiplied by 32 µs. 00 = 4x; 01 = 8x,
10 = 12x; 11 = 15x the SOP_CODE_ADR code length. ACK_TO must be set to greater than 30 + Data Code Length (only for
8DR) + Preamble Length + SOP Code Length (x2).
Mnemonic
Bit
Default
Read/Write
Function
FRAMING_CFG_ADR
7
6
5
Address
4
3
2
0x10
1
0
1
0
1
0
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SOP EN
SOP LEN
LEN EN
SOP TH
Bit 7
SOP Enable. When this bit is set, each transmitted packet begins with a SOP field, and only packets beginning with a valid
SOP field will be received. If this bit is cleared, no SOP field will be generated when a packet is transmitted, and packet reception will begin whenever two successive correlations against the DATA_CODE_ADR code are detected.
Bit 6
SOP PN Code Length. When this bit is set the SOP_CODE_ADR code length is 64 chips. When this bit is cleared the
SOP_CODE_ADR code length is 32 chips.
Bit 5
Packet Length Enable. When this bit is set the 8-bit value contained in TX_LENGTH_ADR is transmitted immediately after the
SOP field. In receive mode, the 8 bits immediately following the SOP field are interpreted as the length of the packet. When this
bit is cleared no packet length field is transmitted. 8DR always sends the packet length field (LEN EN setting is ignored). GFSK
requires user set LEN EN = 1.
Bits 4:0
SOP Correlator Threshold. This is the receive data correlator threshold used when attempting to detect a SOP symbol. There
is a single threshold for the SOP_CODE_ADR code. This threshold is applied independently to each of SOP1 and SOP2 fields.
When SOP LEN is set, all 5 bits of this field are used. When SOP LEN is cleared, the most significant bit is disregarded. Typical
applications configure SOP TH = 04h for SOP32 and SOP TH = 0Eh for SOP64.
Document #: 38-16015 Rev. *F
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CYRF6936
Mnemonic
DATA32_THOLD_ADR
Address
0x11
Bit
7
6
5
4
3
2
1
0
Default
-
-
-
-
0
1
0
0
R/W
R/W
R/W
R/W
Read/Write
Function
Bits 7:4
Bits 3:0
-
-
-
-
Not Used
Not Used
Not Used
Not Used
TH32
Not Used.
32 Chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when DATA
CODE LENGTH (see TX_CFG_ADR) is set to 32. Typical applications configure TH32 = 05h.
Mnemonic
DATA64_THOLD_ADR
Address
7
6
5
Default
-
-
-
0
1
0
1
0
Read/Write
-
-
-
R/W
R/W
R/W
R/W
R/W
Not Used
Not Used
Not Used
Function
Bits 7:5
Bits 4:0
3
2
1
0
TH64
Not Used.
64 Chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when the DATA
CODE LENGTH (see TX_CFG_ADR) is set to 64. Typical applications configure TH64 = 0Eh.
Mnemonic
Bit
4
0x12
Bit
RSSI_ADR
4
3
2
1
0x13
6
Default
0
-
1
0
0
0
0
0
Read/Write
R
-
R
R
R
R
R
R
SOP
Not Used
LNA
Function
5
Address
7
0
RSSI
A Received Signal Strength Indicator (RSSI) reading is taken automatically when an SOP symbol is detected. In addition, an RSSI reading is
taken whenever RSSI_ADR is read. The contents of this register are not valid after the device is configured for receive mode until either a SOP
symbol is detected, or the register is (re)read. The conversion can occur as often as once every 12-µs. The approximate slope of the curve is
1.9 dB/count, but is not guaranteed.
If it is desired to measure the background RF signal strength on a channel before a packet has been received then the MCU should perform
a “dummy” read of this register, the results of which should be discarded. This “dummy” read will cause an RSSI measurement to be taken,
and therefore subsequent readings of the register will yield valid data.
Bit 7
SOP RSSI Reading. When set, this bit indicates that the reading in the RSSI field was taken when a SOP symbol was
detected. When cleared, this bit indicates that the reading stored in the RSSI field was triggered by a previous SPI read of this
register.
Bit 5
LNA State. This bit indicates the LNA state when the RSSI reading was taken. When cleared, this bit indicates that the LNA
was disabled when the RSSI reading was taken; if set this bit indicates that the LNA was enabled when the RSSI reading was
taken.
Bits 4:0
RSSI Reading. This field indicates the instantaneous strength of the RF signal being received at the time that the RSSI reading
was taken. A larger value indicates a stronger signal. The signal strength measured is for the RF signal on the configured channel, and is measured after the LNA stage.
Document #: 38-16015 Rev. *F
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CYRF6936
Mnemonic
EOP_CTRL_ADR
Address
0x14
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
0
0
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
HEN
HINT
EOP
If the LEN EN bit is set, then the contents of this register have no effect. If the LEN EN bit is cleared, then this register is used to configure how
an EOP (end of packet) condition is detected.
Bit 7
EOP Hint Enable. When set, this bit will cause an EOP to be detected if no correlations have been detected for the number of
symbol periods set by the HINT field and the last two received bytes match the calculated CRC16 for all previously received
bytes. Use of this mode reduces the chance of non-correlations in the middle of a packet from being detected as an EOP condition.
Bits 6:4
EOP Hint Symbol Count. The minimum number of symbols of consecutive non-correlations at which the last two bytes are
checked against the calculated CRC16 to detect an EOP condition.
Bits 4:0
EOP Symbol Count. An EOP condition is deemed to exist when the number of consecutive non-correlations is detected.
Mnemonic
CRC_SEED_LSB_ADR
Address
0x15
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Function
CRC SEED LSB
The CRC16 seed allows different devices to generate or recognize different CRC16s for the same payload data. If a transmitter and receiver
use a randomly selected CRC16 seed, the probability of correctly receiving data intended for a different receiver is 1/65535, even if the other
transmitter/receiver are using the same SOP_CODE_ADR codes and channel.
Bits 7:0
CRC16 Seed Least Significant Byte. The LSB of the starting value of the CRC16 calculation.
Mnemonic
CRC_SEED_MSB_ADR
Address
0x16
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Function
Bits 7:0
CRC SEED MSB
CRC16 Seed Most Significant Byte. The MSB of the starting value of the CRC16 calculation.
Mnemonic
Bit
TX_CRC_LSB_ADR
7
6
5
Address
4
3
2
1
0x17
0
Default
-
-
-
-
-
-
-
-
Read/Write
R
R
R
R
R
R
R
R
Function
Bits 7:0
TX CRC LSB
Calculated CRC16 LSB. The LSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid after
packet transmission is complete.
Document #: 38-16015 Rev. *F
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CYRF6936
Mnemonic
TX_CRC_MSB_ADR
Address
0x18
Bit
7
6
5
4
3
2
1
0
Default
-
-
-
-
-
-
-
-
Read/Write
R
R
R
R
R
R
R
R
Function
Bits 7:0
TX CRC MSB
Calculated CRC16 MSB. The MSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid
after packet transmission is complete.
Mnemonic
RX_CRC_LSB_ADR
Address
0x19
Bit
7
6
5
4
3
2
1
0
Default
1
1
1
1
1
1
1
1
Read/Write
R
R
R
R
R
R
R
R
Function
Bits 7:0
RX CRC LSB
Received CRC16 LSB. The LSB of the CRC16 field extracted from the last received packet. This value is valid whether or not
the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic
Bit
RX_CRC_MSB_ADR
7
6
5
Address
4
3
2
1
0x1A
0
Default
1
1
1
1
1
1
1
1
Read/Write
R
R
R
R
R
R
R
R
Function
Bits 7:0
RX CRC MSB
Received CRC16 MSB. The MSB of the CRC16 field extracted from the last received packet. This value is valid whether or not
the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic
Bit
Default
Read/Write
TX_OFFSET_LSB_ADR
7
6
Address
4
3
2
1
0x1B
0
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
Function
Bits 7:0
5
STRIM LSB
The least significant 8 bits of the synthesizer offset value. This is a 12-bit 2’s complement signed number which may be used to
offset the transmit frequency of the device by up to ±1.5 MHz. A positive value increases the transmit frequency, and a negative
value reduces the transmit frequency. A value of +1 increases the transmit frequency by 732.6 Hz; a value of –1 decreases the
transmit frequency by 732.6 Hz. A value of 0x0555 increases the transmit frequency by 1 MHz; a value of 0xAAB decreases
the transmit frequency by 1 MHz. Typically, this register is loaded with 0x55 during initialization. Typically this feature is used to
avoid the need to change the synthesizer frequency when switching between TX and RX. As the IF = 1 MHz the RX frequency
is offset 1 MHz from the synthesizer frequency; therefore, transmitting with a 1 MHz offset allows the same synthesizer frequency to be used for both transmit and receive.
Synthesizer offset has no effect on receive frequency.
Document #: 38-16015 Rev. *F
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CYRF6936
Mnemonic
TX_OFFSET_MSB_ADR
Address
7
6
5
4
Default
-
-
-
-
0
0
0
0
Read/Write
-
-
-
-
R/W
R/W
R/W
R/W
Not Used
Not Used
Not Used
Not Used
Function
Bits 7:4
Bits 3:0
2
1
0
STRIM MSB
Not Used.
The most significant 4 bits of the synthesizer trim value. Typically, this register is loaded with 0x05 during initialization.
Mnemonic
Bit
3
0x1C
Bit
MODE_OVERRIDE_ADR
7
6
5
Address
4
3
2
1
0x1D
0
Default
0
0
0
0
0
-
-
0
Read/Write
W
W
W
W
W
-
-
W
RSVD
RSVD
FRC SEN
Not Used
Not Used
RST
Function
FRC AWAKE
Bits 7:6
Reserved. Must be zero.
Bit 5
Manually Initiate Synthesizer. Setting this bit forces the synthesizer to start. Clearing this bit has no effect. For this bit to operate
correctly, the oscillator must be running before this bit is set.
Bits 4:3
Bits 2:1
Force Awake. Force the device out of sleep mode. Setting both bits of this field forces the oscillator to keep running at all times
regardless of the END STATE setting. Clearing both of these bits disables this function.
Not Used.
Bit 0
Reset. Setting this bit forces a full reset of the device. Clearing this bit has no effect.
Mnemonic
Bit
Default
Read/Write
Function
RX_OVERRIDE_ADR
7
6
5
Address
4
3
2
0x1E
1
0
0
0
0
0
0
0
0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
ACK RX
RXTX DLY
MAN RXACK
FRC RXDR
DIS CRC0
DIS RXCRC
ACE
Not Used
This register provides the ability to over-ride some automatic features of the device.
Bit 7
When this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the
given channel when automatically entering receive mode.
Bit 6
When this bit is set and ACK EN is enabled, the transmission of the ACK packet is delayed by 20 µs.
Bit 5
Force Expected Packet Type. When this bit is set, and the device is in receive mode, the device is configured to receive an
ACK packet at the data rate defined in TX_CFG_ADR.
Bit 4
Force Receive Data Rate. When this bit is set, the receiver will ignore the data rate encoded in the SOP symbol, and will
receive data at the data rate defined in TX_CFG_ADR.
Bit 3
Reject packets with a zero-seed CRC16. Setting this bit causes the receiver to reject packets with a zero-seed, and accept only
packets with a CRC16 that matches the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR.
Bit 2
The RX CRC16 checker is disabled. If packets with CRC16 enabled are received, the CRC16 will be treated as payload data
and stored in the receive buffer.
Bit 1
Accept Bad CRC16. Setting this bit causes the receiver to accept packets with a CRC16 that do not match the seed in
CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. An ACK is to be sent regardless of the condition of the received CRC16.
Bit 0
Not Used.
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CYRF6936
Mnemonic
TX_OVERRIDE_ADR
Address
0x1F
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
Function
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ACK TX
FRC PRE
RSVD
MAN TXACK
OVRD ACK
DIS TXCRC
RSVD
TX INV
This register provides the ability to over-ride some automatic features of the device.
Bit 7
When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the
given channel when automatically entering transmit mode.
Bit 6
Force Preamble. When this bit is set, the device will transmit a continuous repetition of the preamble pattern (see
PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures. Firmware should set bit
RST of MODE_OVERRIDE_ADR to exit this mode.
Bit 5
Reserved. Must be zero.
Bit 4
Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set.
Bit 3
ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet.
Bit 2
Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets.
Bit 1
Reserved. Must be zero.
Bit 0
TX Data Invert. When this bit is set the transmit bitstream is inverted.
Mnemonic
XTAL_CFG_ADR
Address
0x26
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
Function
W
W
W
W
W
W
W
W
RSVD
RSVD
RSVD
RSVD
START DLY
RSVD
RSVD
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:4
Reserved. Must be zero.
Bit 3
Bits 2:0
Crystal Startup Delay. Setting this bit, sets the crystal startup delay to 150uSec to handle warm restarts of the crystal. Firmware
MUST set this bit during initialization.
Reserved. Must be zero.
Mnemonic
Bit
CLK_OVERRIDE_ADR
7
6
5
Address
4
3
2
0x27
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
Function
This register provides the ability to override some automatic features of the device.
Bits 7:2
Reserved. Must be zero.
Bit 1
Force Receive Clock. Streaming applications MUST set this bit during receive mode, otherwise this bit is cleared.
Bit 0
Reserved. Must be zero.
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CYRF6936
Mnemonic
CLK_EN_ADR
Address
0x28
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
Function
W
W
W
W
W
W
W
W
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:2
Reserved. Must be zero.
Bit 1
Force Receive Clock Enable. Streaming applications MUST set this bit during initialization.
Bit 0
Reserved. Must be zero.
Mnemonic
Bit
RX_ABORT_ADR
7
6
5
Address
4
3
2
1
0x29
0
Default
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
RSVD
RSVD
ABORT EN
RSVD
RSVD
RSVD
RSVD
RSVD
Function
This register provides the ability to override some automatic features of the device.
Bits 7:6
Reserved. Must be zero.
Bit 5
Receive Abort Enable. Typical applications will disrupt any pending receive by first setting this bit, otherwise this bit is cleared.
Bits 4:0
Reserved. Must be zero.
Mnemonic
Bit
AUTO_CAL_TIME_ADR
7
6
5
Address
4
3
2
1
0x32
0
Default
0
0
0
0
0
0
1
1
Read/Write
W
W
W
W
W
W
W
W
Function
AUTO_CAL_TIME
This register provides the ability to override some automatic features of the device.
Bits 7:0
Auto Cal Time. Firmware MUST write 3Ch to this register during initialization.
Mnemonic
Bit
AUTO_CAL_OFFSET_ADR
7
6
5
Address
4
3
2
1
0x35
0
Default
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Function
AUTO_CAL_OFFSET
This register provides the ability to override some automatic features of the device.
Bits 7:0
Auto Cal Offset. Firmware MUST write 14h to this register during initialization.
Document #: 38-16015 Rev. *F
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CYRF6936
Mnemonic
ANALOG_CTRL_ADR
Address
0x39
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
Function
W
W
W
W
W
W
W
W
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RX INV
ALL SLOW
This register provides the ability to override some automatic features of the device.
Bits 7:2
Bit 1
Reserved. Must be zero.
Receive Invert. When set, the incoming receive data is inverted. Firmware MUST set this bit when interoperability with first generation devices is desired.
Bit 0
All Slow. When set, the synth settling time for all channels is the same as for slow channels. It is recommended that firmware
set this bit when using GFSK data rate mode.
Document #: 38-16015 Rev. *F
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CYRF6936
Register Files
Files are written to or read from using non-incrementing burst read or write transactions. In most cases accessing a file may be
destructive; the file must be completely read/written, otherwise the contents may be altered. When accessing file registers, the
bytes are presented to the bus least significant byte first.
Mnemonic
TX_BUFFER_ADR
Address
0x20
Length
16 Bytes
R/W
W
Default
0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
The transmit buffer is a FIFO. Writing to this file adds a byte to the packet being sent. Writing more bytes to this file than the packet length in
TX_LENGTH_ADR will have no effect, and these bytes will be lost. The FIFO accumulates data until it is reset via TX CLR in TX_CTRL_ADR.
A previously sent packet, of 16 bytes or less, can be transmitted if TX_GO is set without resetting the FIFO. The contents of TX_BUFFER_ADR
is not affected by the transmission of an Auto ACK.
Mnemonic
RX_BUFFER_ADR
Address
0x21
Length
16 Bytes
R/W
R
Default
0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
The receive buffer is a FIFO. Received bytes may be read from this file register at any time that it is not empty, but when reading from this file
register before a packet has been completely received care must be taken to ensure that error packets (for example with bad CRC16) are
handled correctly.
When the receive buffer is configured to be overwritten by new packets (the alternative is for new packets to be discarded if the receive buffer
is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overwritten by a newly
received packet while this file register is being read.
When the VLD EN bit in RX_CFG_ADR is set, the bytes in this file register alternate—the first byte read is data, the second byte is a valid flag
for each bit in the first byte, the third byte is data, the fourth byte valid flags, etc. In SDR and DDR modes the valid flag for a bit is set if the
correlation coefficient for the bit exceeded the correlator threshold, and is cleared if it did not. In 8DR mode, the MSB of a valid flags byte
indicates whether or not the correlation coefficient of the corresponding received symbol exceeded the threshold. The seven LSBs contain the
number of erroneous chips received for the data.
Mnemonic
SOP_CODE_ADR
Address
0x22
Length
8 Bytes
R/W
R/W
Default
0x17FF9E213690C782
When using 32 chip SOP_CODE_ADR codes, only the first four bytes of this register are used; in order to complete the file write process, these
four bytes must be followed by four bytes of “dummy” data. However, a class of codes known as “multiplicative codes” may be used; there are
64 chip codes with good auto-correlation and cross-correlation properties where the least significant 32 chips themselves have good autocorrelation and cross-correlation properties when used as 32-chip codes. In this case the same eight-byte value may be loaded into this file
and used for both 32 chip and 64 chip SOP symbols.
When reading this file, all eight bytes must be read; if fewer than eight bytes are read from the file, the contents of the file will have been rotated
by the number of bytes read. This applies to writes, as well.
Recommended SOP Codes:
0x91CCF8E291CC373C
0x0FA239AD0FA1C59B
0x2AB18FD22AB064EF
0x507C26DD507CCD66
0x44F616AD44F6E15C
0x46AE31B646AECC5A
0x3CDC829E3CDC78A1
0x7418656F74198EB9
0x49C1DF6249C0B1DF
0x72141A7F7214E597
Document #: 38-16015 Rev. *F
Page 29 of 39
CYRF6936
Mnemonic
DATA_CODE_ADR
Address
0x23
Length
16 Bytes
R/W
R/W
Default
0x02F9939702FA5CE3012BF1DB0132BE6F
In GFSK mode, this file register is ignored.
In 64-SDR mode, only the first eight bytes are used.
In 32-DDR mode, only eight bytes are used. The format for these eight bytes: 0x00000000BBBBBBBB00000000AAAAAAAA, where “0”
represents unused locations. Example: 0x00000000B2BB092B00000000B86BC0DC; where “B86BC0DC” represents AAAAAAAA,
“00000000“ represents unused locations, “B2BB092B“ represents BBBBBBBB, and “00000000“ represents unused locations.
In 64-DDR and 8DR modes, all sixteen bytes are used.
When reading this file, all sixteen bytes must be read; if fewer than sixteen bytes are read from the file, the contents of the file will have been
rotated by the number of bytes read. This applies to writes, as well.
Certain sixteen-byte sequences have been calculated that provide excellent auto-correlation and cross-correlation properties, and it is recommended that such sequences be used; the default value of this register is one such sequence. In typical applications, all devices use the same
DATA_CODE_ADR codes, and devices and systems are addressed by using different SOP_CODE_ADR codes; in such cases it may never
be necessary to change the contents of this register from the default value.
Typical applications should use the default code.
Mnemonic
PREAMBLE_ADR
Address
0x24
Length
3 Bytes
R/W
R/W
Default
0x333302
1st byte – The number of repetitions of the preamble sequence that are to be transmitted. The preamble may be disabled by writing 0x00 to
this byte.
2nd byte – Least significant eight chips of the preamble sequence
3rd byte – Most significant eight chips of the preamble sequence
If using 64-SDR to communicate with CYWUSB69xx devices, set number of repetitions to four for optimum performance
When reading this file, all three bytes must be read; if fewer than three bytes are read from the file, the contents of the file will have been rotated
by the number of bytes read. This applies to writes, as well.
Mnemonic
MFG_ID_ADR
Address
0x25
Length
6 Bytes
R
R
Default
NA
To minimize ~190µA of current consumption (default), execute a “dummy” single-byte SPI write to this address with a zero data stage after the
contents have been read. Non-zero to enable reading of fuses. Zero to disable reading fuses.
Document #: 38-16015 Rev. *F
Page 30 of 39
CYRF6936
10.0
Static Discharge Voltage (RF)[6] ................................. 1100V
Absolute Maximum Ratings
Storage Temperature .................................. –65°C to +150°C
Latch-up Current......................................+200 mA, –200 mA
Ambient Temperature with Power Applied .. –55°C to +125°C
11.0
Supply Voltage on any power supply pin relative to VSS–0.3V
to +3.9V
VCC .....................................................................2.4V to 3.6V
DC Voltage to Logic Inputs[5] ................... –0.3V to VIO +0.3V
DC Voltage applied to Outputs in High-Z State .. –0.3V to VIO
+0.3V
Static Discharge Voltage
(Digital)[6]
............................>2000V
Operating Conditions
VIO ......................................................................1.8V to 3.6V
VBAT ....................................................................1.8V to 3.6V
TA (Ambient Temperature Under Bias) ............. 0°C to +70°C
Ground Voltage.................................................................. 0V
FOSC (Crystal Frequency)............................ 12MHz ±30 ppm
12.0
DC Characteristics(T = 25°C, VBAT = 2.4V, PMU disabled, fOSC = 12.000000MHz)
Parameter
Description
Conditions
Min.
Typ.
VBAT
Battery Voltage
0–70°C
1.8
VREG[7]
PMU Output Voltage
2.4V mode
2.4
2.43
VREG[7]
VIO[8]
PMU Output Voltage
2.7V mode
2.7
2.73
Max.
Unit
3.6
V
V
V
VIO Voltage
1.8
3.6
V
VCC
VCC Voltage
0–70°C
2.4[9]
3.6
V
VOH1
Output High Voltage condition 1
At IOH = –100.0 µA
VIO – 0.2
VIO
V
VOH2
Output High Voltage condition 2
At IOH = –2.0 mA
VIO – 0.4
VIO
V
VOL
Output Low Voltage
At IOL = 2.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
IIL
Input Leakage Current
0 < VIN < VIO
CIN
Pin Input Capacitance
except XTAL, RFN, RFP, RFBIAS
ICC (GFSK)[10]
Average TX Icc, 1Mbps, slow channel PA = 5, 2-way, 4-bytes/10 ms
0.87
ICC (32-8DR)[10] Average TX Icc, 250kbps, fast channel PA = 5, 2-way, 4-bytes/10 ms
1.2
ISB[11]
Sleep Mode Icc
0.8
ISB[11]
Sleep Mode Icc
PMU enabled
31.4
µA
IDLE ICC
Radio off, XTAL Active
XOUT disabled
1.0
mA
Isynth
ICC during Synth Start
8.4
mA
TX ICC
ICC during Transmit
PA = 5 (–5 dBm)
20.8
mA
TX ICC
ICC during Transmit
PA = 6 (0 dBm)
26.2
mA
TX ICC
ICC during Transmit
PA = 7 (+4 dBm)
34.1
mA
RX ICC
ICC during Receive
LNA off, ATT on
18.4
mA
RX ICC
ICC during Receive
LNA on, ATT off
21.2
mA
Boost Eff
PMU Boost Converter Efficiency
VBAT = 2.5V, VREG = 2.73V,
ILOAD = 20 mA
81
%
0
0.7VIO
0
–1
0.45
V
VIO
V
0.3VIO
V
0.26
+1
µA
3.5
10
pF
mA
mA
10
µA
Notes
5. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.
6. Human Body Model (HBM).
7. VREG depends on battery input voltage.
8. In sleep mode, the I/O interface voltage reference is VBAT.
9. In sleep mode, VCC min. can go as low as 1.8v
10. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving
ACK handshake. Device is in sleep except during this transaction.
11. ISB is not guaranteed if any I/O pin is connected to voltages higher than VIO.
Document #: 38-16015 Rev. *F
Page 31 of 39
CYRF6936
12.0
DC Characteristics(T = 25°C, VBAT = 2.4V, PMU disabled, fOSC = 12.000000MHz) (continued)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
ILOAD_EXT
Average PMU External Load current
VBAT = 1.8V, VREG = 2.73V,
0–50°C, RX Mode
15
mA
ILOAD_EXT
Average PMU External Load current
VBAT = 1.8V, VREG = 2.73V,
50–70°C, RX Mode
10
mA
AC Characteristics[12]
13.0
Table 13-1. SPI Interface[13]
Parameter
Description
tSCK_CYC
SPI Clock Period
tSCK_HI
tSCK_LO
Min.
Typ.
Max.
Unit
238.1
ns
SPI Clock High Time
100
ns
SPI Clock Low Time
100
ns
tDAT_SU
SPI Input Data Set-up Time
25
ns
tDAT_HLD
SPI Input Data Hold Time
10
tDAT_VAL
SPI Output Data Valid Time
0
tDAT_VAL_TRI
SPI Output Data Tri-state (MOSI from Slave Select Deassert)
SCK[14]
ns
50
ns
20
ns
tSS_SU
SPI Slave Select Set-up Time before first positive edge of
10
ns
tSS_HLD
SPI Slave Select Hold Time after last negative edge of SCK
10
ns
tSS_PW
SPI Slave Select Minimum Pulse Width
20
ns
tSCK_SU
SPI Slave Select Set-up Time
10
ns
tSCK_HLD
SPI SCK Hold Time
10
ns
tRESET
Minimum RST pin pulse width
10
ns
Figure 13-1. SPI Timing
tSCK_CYC
tSCK_HI
SCK
tSCK_LO
tSCK_HLD
tSCK_SU
nSS
tSS_SU
tDAT_SU
tSS_HLD
tDAT_HLD
MOSI input
tDAT_VAL
tDAT_VAL_TRI
MISO
MOSI output
Notes
12. AC values are not guaranteed if voltage on any pin exceed VIO.
13. CLOAD = 30 pF.
14. SCK must start low at the time SS goes low, otherwise the success of SPI transactions are not guaranteed.
Document #: 38-16015 Rev. *F
Page 32 of 39
CYRF6936
14.0
RF Characteristics
Table 14-1. Radio Parameters
Parameter Description
Conditions
RF Frequency Range
Note 15
Receiver (T = 25°C, VCC = 3.0V, fOSC = 12.000000MHz, BER < 1E-3)
Sensitivity 125kbps 64-8DR
BER 1E-3
Sensitivity 250-kbps 32-8DR
BER 1E-3
Sensitivity
CER 1E-3
Sensitivity GFSK
BER 1E-3, ALL SLOW = 1
Min.
2.400
–80
LNA gain
ATT gain
Maximum Received Signal
LNA On
RSSI value for PWRin –60 dBm
LNA On
Typ.
–15
RSSI slope
Max.
Unit
2.497
GHz
–97
dBm
–93
dBm
–87
dBm
–84
dBm
22.8
dB
–31.7
dB
–6
dBm
21
Count
1.9
dB/Count
Interference Performance (CER 1E-3)
Co-channel Interference rejection
Carrier-to-Interference (C/I)
C = –60 dBm
9
dB
Adjacent (±1 MHz) channel selectivity C/I 1 MHz
C = –60 dBm
3
dB
Adjacent (±2 MHz) channel selectivity C/I 2 MHz
C = –60 dBm
–30
dB
Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz
C = –67 dBm
–38
dB
Out-of-Band Blocking 30 MHz–12.75 MHz[16]
C = –67 dBm
–30
dBm
Intermodulation
C = –64 dBm, ∆f = 5,10 MHz
–36
dBm
800 MHz
100-kHz ResBW
–79
dBm
1.6 GHz
100-kHz ResBW
–71
dBm
3.2 GHz
100-kHz ResBW
–65
dBm
Receive Spurious Emission
Transmitter (T = 25°C, VCC = 3.0V)
Maximum RF Transmit Power
PA = 7
+2
4
+6
dBm
Maximum RF Transmit Power
PA = 6
Maximum RF Transmit Power
PA = 5
–2
0
+2
dBm
–7
–5
–3
dBm
Maximum RF Transmit Power
PA = 0
RF Power Control Range
–35
dBm
39
dB
RF Power Range Control Step Size
seven steps, monotonic
5.6
dB
Frequency Deviation Min
PN Code Pattern 10101010
270
kHz
Frequency Deviation Max
PN Code Pattern 11110000
323
kHz
Error Vector Magnitude (FSK error)
>0 dBm
10
%rms
Occupied Bandwidth
–6 dBc, 100-kHz ResBW
876
kHz
In-band Spurious Second Channel Power (±2 MHz)
–38
dBm
In-band Spurious Third Channel Power (>3 MHz)
–44
dBm
500
Transmit Spurious Emission (PA = 7)
Notes
15. Subject to regulation.
16. Exceptions F/3 & 5C/3.
Document #: 38-16015 Rev. *F
Page 33 of 39
CYRF6936
Table 14-1. Radio Parameters (continued)
Parameter Description
Conditions
Min.
Typ.
Max.
Unit
Non-Harmonically Related Spurs (800MHz)
–38
dBm
Non-Harmonically Related Spurs (1.6GHz)
–34
dBm
Non-Harmonically Related Spurs (3.2GHz)
–47
dBm
Harmonic Spurs (Second Harmonic)
–43
dBm
Harmonic Spurs (Third Harmonic)
–48
dBm
Fourth and Greater Harmonics
–59
dBm
Power Management (Crystal PN# eCERA GF-1200008)
Crystal start to 10ppm
0.7
1.3
0.6
ms
Crystal start to IRQ
XSIRQ EN = 1
Synth Settle
Slow channels
270
ms
µs
Synth Settle
Medium channels
180
µs
Synth Settle
Fast channels
100
µs
Link turn-around time
GFSK
30
µs
Link turn-around time
250 kbps
62
µs
Link turn-around time
125 kbps
94
µs
Link turn-around time
<125 kbps
31
µs
Max. packet length
<60ppm crystal-to-crystal
all modes except 64-DDR
40
bytes
Max. packet length
<60ppm crystal-to-crystal
64-DDR
16
bytes
Document #: 38-16015 Rev. *F
Page 34 of 39
CYRF6936
Typical Operating Characteristics[17]
15.0
Transmit Power vs. Temperature
(Vcc = 2.7v)
Transmit Power vs. Channel
Transmit Power vs. Vcc
(PMU off)
6
6
PA6
0
-2
-4
PA5
-6
-8
-10
PA4
-12
0
20
2
PA6
0
-2
-4
PA5
-6
-8
-10
PA4
-12
-14
40
-14
2.4
60
Output Power (dBm)
2
2.6
2.8
3
3.2
3.4
-8
-10
PA4
0
3.6
20
40
20
19
18
ATT ON
LNA OFF
RSSI Count
RSSI Count
LNA OFF
80
Average RSSI vs. Vcc
(Rx signal = -70dBm)
17
LNA ON
60
Channel
19
24
RSSI Count
PA5
-6
-12
18
16
15
17
16
15
14
13
14
12
13
11
10
2.4
12
-100
-80
-60
-40
0
-20
20
40
60
RSSI vs. Channel
(Rx signal = -70dBm)
12
10
8
6
4
2
0
40
60
-82
-84
-86
CER
-88
-90
8DR32
-92
-94
2.4
80
3.2
3.4
3.6
-80
Receiver Sensitivity (dBm)
Receiver Sensitivity (dBm)
14
3
Rx Sensitivity vs. Temperature
(1Mbps CER)
-80
16
20
2.8
Vcc
Rx Sensitivity vs. Vcc
(1Mbps CER)
18
0
2.6
Temp (deg C)
Input Power (dBm)
RSSI Count
-4
Average RSSI vs. Temperature
(Rx signal = -70dBm)
32
0
-120
PA6
0
-2
Vcc
Typical RSSI Count vs Input Power
8
2
-14
Temp (deg C)
16
PA7
4
PA7
4
Output Power (dBm)
Output Power (dBm)
6
PA7
4
-82
-84
-86
CER
-88
-90
8DR32
-92
-94
2.6
2.8
Channel
3
3.2
3.4
3.6
0
20
Vcc
Receiver Sensitivity vs. Frequency Offset
40
60
Temp (deg C)
Receiver Sensitivity vs Channel
(3.0v, Room Temp)
Carrier to Interferer
(Narrow band, LP modulation)
-82
-84
GFSK
-86
-88
-90
DDR32
-92
-94
8DR64
-96
-98
-150
-100
-50
0
50
Crystal Offset (ppm)
100
150
-81
20.0
GFSK
-83
10.0
0.0
-85
C/I (dB)
Receiver Sensitivity (dBm)
Receiver Sensitivity (dBm)
-80
CER
-87
-89
-91
20
-30.0
-50.0
8DR32
-95
0
-20.0
-40.0
DDR32
-93
-10.0
40
Channel
60
80
-60.0
-10
-5
0
5
10
Channel Offset (MHz)
Note
17. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read, cross-checking RSSI with LNA off/on is recommended for accurate readings.
Document #: 38-16015 Rev. *F
Page 35 of 39
CYRF6936
10
10
3
1
1
GFSK vs. BER
(SOP Threshold = 5, C38 slow)
BER vs. Data Threshold (32-8DR)
(SOP Threshold = 5, C38 slow)
BER vs. Data Threshold (32-DDR)
(SOP Threshold = 5, C38 slow)
0
100
0 Thru 7
10
1
6
0.01
0.01
0.001
0.0001
0.0001
0.00001
-100
-95
-90
-85
-80
-75
0.0001
0.00001
-100
-70
ICC RX
(LNA OFF)
-85
-80
-75
-70
19.5
19
18.5
18
17.5
OPERATING CURRENT (mA)
3.3V
3.0V
2.7V
2.4V
20
3.3V
3.0V
2.7V
2.4V
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
17
19
5
10 15 20 25 30 35 40 45 50 55 60 65 70
0
5
0
5
15.5
15
14.5
16.5
16
15.5
15
14.5
5
0
10 15 20 25 30 35 40 45 50 55 60 65 70
ICC TX @ PA4
ICC TX @ PA3
20.5
3.3V
3.0V
2.7V
2.4V
18.5
18
17.5
17
16.5
16
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Document #: 38-16015 Rev. *F
3.3V
3.0V
2.7V
2.4V
20
19.5
19
18.5
18
17.5
17
15.5
15
OPERATING CURRENT (mA)
15.5
OPERATING CURRENT (mA)
16
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
19
16.5
5
TEMPERATURE (C)
18
17
3.3V
3.0V
2.7V
2.4V
17
14
0
ICC TX @ PA2
3.3V
3.0V
2.7V
2.4V
10 15 20 25 30 35 40 45 50 55 60 65 70
ICC TX @ PA1
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
16
10 15 20 25 30 35 40 45 50 55 60 65 70
0
17.5
3.3V
3.0V
2.7V
2.4V
16.5
TEMPERATURE (C)
17.5
5
ICC TX @ PA0
14
0
-20
TEMPERATURE (C)
17
3.3V
3.0V
2.7V
2.4V
-40
3.3V
3.0V
2.7V
2.4V
TEMPERATURE (C)
ICC TX SYNTH
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
-60
ICC RX SYNTH
24.5
20.5
-80
Input Power (dBm)
ICC RX
(LNA ON)
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
-90
25
21
OPERATING CURRENT (mA)
-95
GFSK
0.00001
-100
Input Power (dBm)
Input Power (dBm)
OPERATING CURRENT (mA)
0.01
0.001
0.001
0
0.1
%BER
%BER
%BER
1
0.1
0.1
16.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Page 36 of 39
CYRF6936
ICC TX @ PA5
29.5
3.3V
3.0V
2.7V
2.4V
22.5
22
21.5
21
20.5
20
3.3V
3.0V
2.7V
2.4V
29
28.5
28
OPERATING CURRENT (mA)
23
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
ICC TX @ PA7
ICC TX @ PA6
30
23.5
27.5
27
26.5
26
25.5
25
19.5
24.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
0
3.3V
3.0V
2.7V
2.4V
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
16.0
40.5
40
39.5
39
38.5
38
37.5
37
36.5
36
35.5
35
34.5
34
33.5
33
32.5
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
TEMPERATURE (C)
AC Test Loads and Waveforms for Digital Pins
Figure 16-1. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
DC Test Load
OUTPUT
OUTPUT
5 pF
30 pF
INCLUDING
JIG AND
SCOPE
VCC
R1
OUTPUT
INCLUDING
JIG AND
Typical
SCOPE
Max
R2
ALL INPUT PULSES
Parameter
R1
R2
RTH
VTH
VCC
17.0
1071
937
500
1.4
3.00
Unit
Ω
Ω
Ω
V
V
VCC
GND
90%
10%
Rise time: 1 V/ns
90%
10%
Fall time: 1 V/ns
THÉVENIN EQUIVALENT
RTH
VTH
OUTPUT
Equivalent to:
Ordering Information
Table 17-1. Ordering Information
Part Number
CYRF6936-40LFXC
Radio
Transceiver
Document #: 38-16015 Rev. *F
Package Name
Package Type
40 QFN
40 Quad Flat Package No Leads Lead-Free
Operating Range
Commercial
Page 37 of 39
CYRF6936
18.0
Package Description
Figure 18-1. 40-pin Lead-Free QFN 6x6 mm LY40
BOTTOM VIEW
SIDE VIEW
TOP VIEW
0.08[0.003]
5.90[0.232]
6.10[0.240]
A
C
1.00[0.039] MAX.
0.05[0.002] MAX.
0.80[0.031] MAX.
5.70[0.224]
5.80[0.228]
0.18[0.007]
0.28[0.011]
0.20[0.008] REF.
0.60[0.024]
DIA.
PIN1 ID
0.20[0.008] R.
N
N
1
1
2
2
0.45[0.018]
0.30[0.012]
0.50[0.020]
4.45[0.175]
4.55[0.179]
5.90[0.232]
6.10[0.240]
5.70[0.224]
5.80[0.228]
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
0°-12°
0.50[0.020]
C
SEATING
PLANE
4.45[0.175]
4.55[0.179]
0.24[0.009]
0.60[0.024]
(4X)
51-85190-**
The recommended dimension of the PCB pad size for the EPAD underneath the QFN is 3.5 mm × 3.5 mm (width x length).
This document is subject to change, and may be found to contain errors of omission or changes in parameters. For feedback or
technical support regarding Cypress WirelessUSB products please contact Cypress at www.cypress.com. WirelessUSB, PSoC,
and enCoRe are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-16015 Rev. *F
Page 38 of 39
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYRF6936
Document History Page
Description Title: CYRF6936 WirelessUSB™ LP 2.4GHz Radio SoC
Document Number: 38-16015
REV.
ECN NO.
Issue Date
Orig. of
Change
**
307437
See ECN
TGE
New data sheet
*A
377574
See ECN
TGE
Preliminary release–
- updated Section 1.0 - Features
- updated Section 2.0 - Applications
- added Section 3.0 - Applications Support
- updated Section 4.0 - Functional Descriptions
- updated Section 5.0 - Pin Description
- added Figure 5-1
- updated Section 6.0 - Functional Overview
- added Section 7.0 - Functional Block Overview
- added Section 9.0 - Register Descriptions
- updated Section 10.0 - Absolute Maximum Ratings
- updated Section 11.0 - Operating Conditions
- updated Section 12.0 - DC Characteristics
- updated Section 13.0 - AC Characteristics
- updated Section 14.0 - RF Characteristics
- added Section 16.0 - Ordering Information
*B
398756
See ECN
TGE
ES-10 update- changed part no.
- updated Section 9.0 - Register Descriptions
- updated Section 12.0 - DC Characteristics
- updated Section 14.0 - RF Characteristics
*C
412778
See ECN
TGE
ES-10 update- updated Section 4.0 - Functional Descriptions
- updated Section 5.0 - Pin Descriptions
- updated Section 6.0 - Functional Overview
- updated Section 7.0 - Functional Block Overview
- updated Section 9.0 - Register Descriptions
- updated Section 10.0 - Absolute Maximum Ratings
- updated Section 11.0 - Operating Conditions
- updated Section 14.0 - RF Characteristics
*D
435578
See ECN
TGE
- updated Section 1.0 - Features
- updated Section 5.0 - Pin Descriptions
- updated Section 6.0 - Functional Overview
- updated Section 7.0 - Functional Block Overview
- updated Section 9.0 - Register Descriptions
- added Section 10.0 - Recommended Radio Circuit Schematic
- updated Section 11.0 - Absolute Maximum Ratings
- updated Section 12.0 - Operating Conditions
- updated Section 13.0 - DC Characteristics
- updated Section 14.0 - AC Characteristics
- updated Section 15.0 - RF Characteristics
*E
460458
See ECN
BOO
Final data sheet - removed “Preliminary” notation
*F
487261
See ECN
TGE
- updated Section 1.0 - Features
- updated Section 5.0 - Pin Descriptions
- updated Section 6.0 - Functional Overview
- updated Section 7.0 - Functional Block Overview
- updated Section 8.0 - Application Example
- updated Section 9.0 - Register Descriptions
- updated Section 12.0 - DC Characteristics
- updated Section 13.0 - AC Characteristics
- updated Section 14.0 - RF Characteristics
- added Section 15.0 - Typical Operating Characteristics
Document #: 38-16015 Rev. *F
Description of Change
Page 39 of 39
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