Improving the Measurement Speed and Overall Test Time of the Model 4200-SCS

Improving the Measurement Speed and Overall Test Time of the Model 4200-SCS
technical note
A
G R E A T E R
M E A S U R E
O F
C O N F I D E N C E
Improving the Measurement
Speed and Overall Test
Time of the Model
4200-SCS Semiconductor
Characterization System
Introduction
Electronic device test and characterization isn’t what it used to be. Whether they’re
at work at a giant semiconductor manufacturing plant or a small research facility,
today’s engineers are making more complex, high precision measurements than
ever before. Equipped with leading-edge measurement instruments, they use the
best of today’s technology to produce the technology of tomorrow. Paradoxically,
unleashing the full power of the modern instruments isn’t always that critical.
Quite often, the data is being acquired in higher volumes and with higher accuracy
than necessary. In the realm of high impedance, ultra-low current measurements,
accuracy inevitably comes at the price of time. While it may not be possible to
avoid a compromise between the two, there are plenty of other factors, often overlooked, that can help boost the overall system performance.
This Tech Note offers users of the Model 4200-SCS Semiconductor Characterization System guidance on avoiding the most common pitfalls, achieving better test
speeds, and reducing overall measurement times.
Optimizing the number of measurement points
The most common task performed on a semiconductor parameter analyzer is a
current-voltage (I-V) sweep across a device under test (DUT), resulting in some
device characteristic. A simple linear sweep is programmed by establishing the
start and stop values and the step size ((Figure 1). The system then calculates the
number of measurement points based on this formula:
Stop Value – Start Value
Number of points = _____________________
Step Size + 1
The overall sweep time is directly proportional to the number of measurement
points, so reducing the sweep range and increasing the step size will result in a
faster overall measurement. To illustrate the test time gains this technique allows,
we modified a standard 4200-SCS test called Vgs-Id. In this test, the gate of an nMOSFET is swept from 0V to 5V, while the current through the drain under a 0.5V
bias is measured. Using built-in analysis tools, the 4200-SCS then determines the
transistor’s threshold voltage (Vth) ((Figure 2). The default sweep had 101 points,
and the overall test time was 18 seconds. Simply doubling the sweep step size
reduced the sweep to 51 points, and the test took 13 seconds to complete, while
the Vth stayed within 0.22% of the previous reading. An even more spectacular improvement was achieved by subsequently reducing the sweep range to 0.5 – 2.5V.
At 21 sweep points, the test time was reduced to four seconds, while the Vth was
1
technical note
Improving the Measurement Speed and Overall Test Time of
the Model 4200-SCS Semiconductor Characterization System
Figure 1
Figure 2
within 0.24% ((Figure 3). In this way, we reduced the
overall test time by 450% without sacrificing the essential accuracy of the result.
Removing unneeded measurements
When a user configures a new interactive test module
(ITM) in the 4200-SCS, the natural tendency is to accept as many of the default settings as possible. While
this may seem like an intuitive choice, it can lead to
measuring too many parameters, and consequently,
to a longer test.
Figure 3
For example, using the same Vgs-Id test optimized
to run in four seconds, note that the only measurements enabled are the drain current (DrainI) and
the gate voltage (GateV), which are necessary for
calculating the threshold voltage. However, if this
test were configured with all available measurements turned on (DrainI, DrainV,
GateI, GateV, SourceI, SourceV are all enabled by default), the total test time would
be 31 seconds. An increase of almost 800% is a high price to pay for information
that adds no particular value. In this case, the culprit is the gate current measurements, which are set by default at Limited Auto 100pA range. The actual gate
leakage current of 5–25fA forced the source-measure unit (SMU) assigned to the
gate terminal to stay on the lowest allowed range of 100pA for the duration of the
sweep, thereby acting as a pace limiter for the entire test.
Going over each SMU setting and turning off unwanted measurements takes just a
few extra seconds, but may save hours or even days in the long run.
Optimizing measurement precision
In the previous example, we witnessed how unnecessary ultra-low current measurements led to significantly longer test times. But what if the test does actually
require the SMU to perform a measurement in the low current region? To return
to our Vgs-Id test example, the SMU making drain current (DrainI) measurements
2
technical note
goes through several current ranges, beginning from the
lowest (and slowest) allowed range of 100pA. If that SMU
were set to the Auto range, the sweep would start on an
even slower 1pA range, returning data with the ultimate
resolution of 0.1fA. Note, however, that the DrainI values
at which Vth extraction takes place are in the hundreds
of microamperes. Therefore, the low current “tail” of the
sweep has little value, other than to show that the transistor
has no anomalies in that region.
Further optimizing the test settings, we then chose to set
the drain terminal SMU to measure current on the Limited Auto 100nA range, which provides a 100fA resolution,
which is more than sufficient for the task at hand. As the
comparison table in Figure 4 shows, this technique produced test time improvements of 100% to 300%, depending
on the number of sweep points, with Vth values staying
within a fraction of a percent of each other.
Figure 4
Using an SMU as a voltmeter
Some test setups require a SMU to perform the voltmeter function. This can be
achieved by programming the SMU to force a constant zero current ((Figure 5 ).
Sourcing zero current is done by default on the “Best Fixed” range, and most
often, this setting is left unchanged. The best fi xed range to source (and measure)
zero current happens to be the 1pA range (on systems with PreAmps). As we have
already seen, selecting such a low range slows the SMU significantly. In most cases,
however, the SMU can perform the voltmeter function quite well while sourcing
the zero current on a higher fi xed range (for example, 1µA).
Taking advantage of the timing controls
Figure 5
Every ITM (Interactive Test Module) in the 4200-SCS allows a user to select the
desired test speed. The three settings—Fast, Normal, and Quiet—can be selected
directly from the Definition page of the ITM. While those settings provide a quick
and easy way to change measurement speed, selecting Custom in the ITM Timing
dialog window offers a further opportunity to optimize the test.
Taking a closer look at the ITM Timing dialog reveals that every
speed setting is a combination of the following three components:
Delay Factor, Filter Factor, and the A/D Integration Time ((Figure
Figure 6
6).
).
Figure 6
The Delay Factor allows the user to control settling time, which is
the time necessary for both the SMU and the DUT to stabilize after
a change in current or voltage, such as during a sweep. The actual
applied delay time is a multiple of the pre-programmed, rangedependent default delay time, and the value of the Delay Factor. An
additional delay (compared to a normal value of 1.0) may be required for highly
capacitive devices, especially in low current measurements. The Delay Factor may be
set to a value anywhere from zero to 100, with a zero setting resulting in no delay.
3
technical note
Improving the Measurement Speed and Overall Test Time of
the Model 4200-SCS Semiconductor Characterization System
The Filter Factor controls the degree of filtering or averaging of multiple readings to
make one measurement. Filtering is often necessary to deal with noise, which is
present to some degree in all measurements. As a rule of thumb, doubling the Filter
Factor halves the measurement noise. A user can specify the Filter Factor to be any
value from zero to 100, with zero resulting in no filtering.
The A/D Integration Time reflects the time that the analog-to-digital converter on
board the SMU has to “look” at the signal. A short integration time for each A/D
conversion results in a relatively fast measurement speed at the expense of noise.
Conversely, a long integration time results in a relatively low noise reading at the
expense of speed. The integration time setting is based on the number of power
line cycles (PLCs). A user can specify a custom A/D Integration Time (between 0.01
and 10 PLC), or leave it on the Auto setting (recommended), which allows the
system to optimize its value based on the range and other conditions.
For many users, these timing controls represent an advanced level of measurement optimization, and may be discarded as not worth the time needed to learn
how to use them. However, depending on the scope of the task, the time invested
in optimizing measurement timing settings might be paid back with significant
speed improvements. It’s important to note, however, that increasing SMU measurement speed generally results in reduced measurement accuracy; at some point,
speed increases may be restricted by fundamental theoretical limits.
Specifications are subject to change without notice.
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