Synchronous Switch-Mode Battery Charge Controller for Solar Power bq24650 FEATURES

Synchronous Switch-Mode Battery Charge Controller for Solar Power bq24650 FEATURES
bq24650
www.ti.com
SLUSA75 – JULY 2010
Synchronous Switch-Mode Battery Charge Controller for Solar Power
With Maximum Power Point Tracking
Check for Samples: bq24650
FEATURES
1
•
APPLICATIONS
•
•
•
•
•
Solar Powered Applications
Remote Monitoring Stations
Portable Handheld Instruments
12V to 24V Automotive Systems
Current-Limited Power Source
LODRV
•
•
16
15
14
13
VCC 1
12 REGN
PAS
MPPSET 2
11 GND
bq24650
STAT1 3
10 SRP
TS 4
9 SRN
5
6
7
8
VFB
•
The bq24650 supports a battery from 2.1V to 26V
with VFB set to a 2.1V feedback reference. The
charge current is programmed by selecting an
appropriate sense resistor. The bq24650 is available
in a 16 pin, 3.5×3.5 mm2 thin QFN package.
PH
•
The bq24650 charges the battery in three phases:
pre-conditioning, constant current, and constant
voltage. Charge is terminated when the current
reaches 1/10 of the fast charge rate. The pre-charge
timer is fixed at 30 minutes. The bq24650
automatically restarts the charge cycle if the battery
voltage falls below an internal threshold and enters a
low quiescent current sleep mode when the input
voltage falls below the battery voltage.
TERM_EN
•
The
bq24650
offers
a
constant-frequency
synchronous PWM controller with high accuracy
current
and
voltage
regulation,
charge
preconditioning, charge termination, and charge
status monitoring.
HIDRV
•
The bq24650 is a highly integrated switch-mode
battery charge controller. It provides input voltage
regulation, which reduces charge current when input
voltage falls below a programmed level. When the
input is powered by a solar panel, the input regulation
loop lowers the charge current so that the solar panel
can provide maximum power output.
VREF
•
•
DESCRIPTION
BTST
•
•
•
Maximum Power Point Tracking (MPPT)
Capability by Input Voltage Regulation
Programmable MPPT Setting
5V-28V Input Solar Panel
600kHz NMOS-NMOS Synchronous Buck
Controller
Resistor Programmable Float Voltage
Accommodates Li-Ion/Polymer, LiFePO4, Lead
Acid Chemistries
Accuracy
– ±0.5% Charge Voltage Regulation
– ±3% Charge Current Regulation
– ±0.6% Input Voltage Regulation
High Integration
– Internal Loop Compensation
– Internal Digital Soft Start
Safety
– Input Over-Voltage Protection
– Battery Temperature Sensing
– Battery Absent Detection
– Thermal Shutdown
Charge Status Outputs for LED or Host
Processor
Charge Enable on MPPSET Pin
Automatic Sleep Mode for Low Power
Consumption
– <15mA Off-State Battery Discharge Current
Small 3.5 × 3.5 mm2 QFN-16 Package
STAT2
•
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq24650
SLUSA75 – JULY 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION
Solar Cell
Half Panel
VIN
D1
R6: 10Ω
R5
2Ω
C1
2.2µF
VCC
bq24650
VREF
C3
R3 1µF
499kΩ
R9
5.23kΩ
C2
1uF
C4:1µF
REGN
D2
MPPSET
Pack
Thermistor
TS
R10
30.1kΩ
Q3
CE
R4
36kΩ
BTST
Q1
HIDRV
C5
100nF
PH
TERM_EN
C6
10uF
D3
SRP
STAT1
R7:10kΩ
STAT2 Thermal
R8:10k Ω
Pad
D4
SRN
Battery Pack
Q2
LODRV
C9
4.7µF
C8
10µF
GND
VIN
RSR
L: 10µH 20mΩ
R2
499kΩ
C7
0.1µF
C10
22pF
R1
100kΩ
VFB
Solar Panel 21 V, MPPT = 18 V, 2-cell, ICHARGE = 2 A, IPRECHARGE = ITERM = 0.2 A, TS = 0 - 45°C
Figure 1. Typical System Schematic
ORDERING INFORMATION
2
ORDERING
NUMBER
(Tape and Reel)
PART NUMBER
PACKAGE
bq24650
16-Pin 3.5×3.5 mm
QFN
PART MARKING
bq24650RVAR
bq24650RVAT
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PAS
QUANTITY
3000
250
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
VALUE
VCC, STAT1, STAT2, SRP, SRN
Voltage range (with respect to GND)
UNIT
–0.3 to 33
PH
–2 to 36
VFB
–0.3 to 16
REGN, LODRV, TS, MPPSET, TERM_EN
–0.3 to 7
V
BTST, HIDRV with respect to GND
–0.3 to 39
VREF
–0.3 to 3.6
SRP–SRN
–0.5 to 0.5
V
Junction temperature range, TJ
–40 to 155
°C
Storage temperature range, Tstg
–55 to 155
°C
Maximum difference voltage
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
Must have a series resistor between battery pack to VFB if battery pack voltage is expected to be greater than 16V. Usually the resistor
divider top resistor takes care of this.
THERMAL INFORMATION
bq24650
THERMAL METRIC (1)
QFN
UNITS
16 PINS
qJA
Junction-to-ambient thermal resistance (2)
yJT
Junction-to-top characterization parameter (3)
yJB
Junction-to-board characterization parameter (4)
(1)
(2)
(3)
(4)
43.8
0.6
°C/W
15.77
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
RECOMMENDED OPERATING CONDITIONS
VALUE
VCC, STAT1, STAT2, SRP, SRN
PH
Voltage range (with respect to GND)
–2 to 30
VFB
–0.3 to 14
REGN, LODRV, TS, MPPSET, TERM_EN
–0.3 to 6.5
BTST, HIDRV with respect to GND
–0.3 to 34
VREF
Maximum difference voltage
UNIT
–0.3 to 28
V
3.3
SRP–SRN
–0.2 to 0.2
V
Junction temperature range, TJ
–40 to 125
°C
Storage temperature range, Tstg
–55 to 155
°C
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ELECTRICAL CHARACTERISTICS
5.0V ≤ VVCC ≤ 28V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range
5
28
V
15
µA
VCC > VBAT, VCC > VUVLO, CE = LOW
5
µA
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charge done
5
µA
0.7
1
mA
2
3
mA
QUIESCENT CURRENTS
Total battery discharge current (sum of
currents into VCC, BTST, PH, SRP, SRN,
VFB), VFB ≤ 2.1V
IBAT
Battery discharge current (sum of currents
into BTST, PH, SRP, SRN, VFB), VFB ≤
2.1V
VCC < VBAT, VCC > VUVLO (SLEEP)
VCC > VBAT, VCC > VUVLO, CE = LOW
Adapter supply current (sum of current into
VCC pin)
IAC
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, charge done
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charging, Qg_total = 10nC [1]
25
mA
CHARGE VOLTAGE REGULATION
VREG
Feedback regulation voltage
2.1
Charge voltage regulation accuracy
IVFB
Leakage current into VFB pin
V
TJ = 0°C to 85°C
–0.5%
0.5%
TJ = –40°C to 125°C
-0.7%
0.7%
VFB = 2.1 V
100
nA
CURRENT REGULATION – FAST CHARGE
VIREG_CHG
SRP-SRN current sense voltage range
VIREG_CHG = VSRP – VSRN
Charge current regulation accuracy
VIREG_CHG = 40 mV
40
–3%
mV
3%
CURRENT REGULATION – PRE-CHARGE
VPRECHG
Precharge current sense voltage range
VIREG_PRCHG = VSRP – VSRN
Precharge current regulation accuracy
VIREG_PRECH = 4 mV
4
–25%
mV
25%
CHARGE TERMINATION
VTERMCHG
Termination current sense voltage range
VITERM = VSRP – VSRN
Termination current accuracy
VITERM = 4 mV
4
–25%
Deglitch time for termination (both edges)
mV
25%
100
tQUAL
Termination qualification time
VBAT > VRECH and ICHG < ITERM
IQUAL
Termination qualification current
Discharge current once termination is detected
ms
250
ms
2
mA
INPUT VOLTAGE REGULATION
VMPPSET
MPPSET regulation voltage
1.2
Input voltage regulation accuracy
IMPPSET
Leakage current into MPPSET pin
VMPPSET_CD
MPPSET shorted to disable charge
VMPPSET_CE
MPPSET released to enable charge
–0.6%
V
0.6%
VMPPSET = 7 V, TA = 0 – 85°C
1
µA
75
mV
175
mV
INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)
VUVLO
AC under-voltage rising threshold
VUVLO_HYS
AC under-voltage hysteresis, falling
Measure on VCC
3.65
3.85
4
V
350
mV
4.1
V
4.35
V
VCC LOWV COMPARATOR
VVCC LOWV_fall
Falling threshold, disable charge
VVCC LOWV_rise
Rising threshold, resume charge
Measure on VCC
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
VSLEEP_HYS
4
SLEEP falling threshold
VVCC – VSRN to enter SLEEP
40
SLEEP hysteresis
SLEEP rising shutdown deglitch
VCC falling below SRN
SLEEP falling powerup deglitch
VCC rising above SRN, Delay to exit SLEEP
mode
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100
150
mV
500
mV
100
ms
30
ms
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ELECTRICAL CHARACTERISTICS (continued)
5.0V ≤ VVCC ≤ 28V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
1.54
1.55
1.56
V
BAT LOWV COMPARATOR
VLOWV
Precharge to fast charge transition (LOWV
threshold)
VLOWV_HYS
LOWV hysteresis
Measure on VFB pin
100
mV
LOWV rising deglitch
VFB falling below VLOWV
25
ms
LOWV falling deglitch
VFB rising above VLOWV + VLOWV_HYS
25
ms
RECHARGE COMPARATOR
VRECHG
Recharge threshold (with respect to VREG)
Measure on VFB pin
Recharge rising deglitch
VFB decreasing below VRECHG
35
50
10
65
mV
ms
Recharge falling deglitch
VFB increasing above VRECHG
10
ms
BAT OVER-VOLTAGE COMPARATOR
VOV_RISE
Over-voltage rising threshold
As percentage of VFB
104%
VOV_FALL
Over-voltage falling threshold
As percentage of VFB
102%
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV
AC over-voltage rising threshold on VCC
VACOV_HYS
AC over-voltage falling hysteresis
31
32
33
V
1
V
1
ms
AC over-voltage deglitch (both edges)
Delay to changing the STAT pins
AC over-voltage rising deglitch
Delay to disable charge
1
ms
AC over-voltage falling deglitch
Delay to resume charge
20
ms
Temperature increasing
145
°C
15
°C
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
TSHUT_HYS
Thermal shutdown hysteresis
Thermal shutdown rising deglitch
Temperature increasing
100
µs
Thermal shutdown falling deglitch
Temperature decreasing
10
ms
THERMISTOR COMPARATOR
VLTF
Cold temperature rising threshold
VLTF_HYS
Rising hysteresis
VHTF
Hot temperature rising threshold
VTCO
Cut-off temperature rising threshold
As percentage to VVREF
Deglitch time for temperature out of range
detection
VTS < VLTF, or VTS < VTCO, or
VTS < VHTF
Deglitch time for temperature in valid range
detection
72.5%
73.5%
0.2%
0.4%
74.5%
0.6%
46.7%
47.5%
48.3%
44.3%
45%
45.7%
400
ms
VTS > VLTF – VLTF_HYS or VTS >VTCO, or VTS >
VHTF
20
ms
Current rising, in synchronous mode measure
(VSRP – VSRN)
80
mV
CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
VOC
Charge over-current rising threshold
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
Charge under-current falling threshold
Switch from CCM to DCM, VSRP > 2.2V
1
5
9
mV
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT
BAT short falling threshold, forced
non-synchronous mode
VBATSHT_HYS
BAT short rising hysteresis
tBATSHT_DEG
Deglitch on both edges
VSRP falling
2
V
200
mV
1
µs
1.25
mV
1.25
mV
1
µs
LOW CHARGE CURRENT COMPARATOR
VLC
Low charge current falling threshold
VLC_HYS
Low charge current rising hysteresis
tLC_DEG
Deglitch on both edges
Measure V(SRP-SRN)
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO, 0 – 35 mA load
IVREF_LIM
VREF current limit
VVREF = 0 V, VVCC > VUVLO
3.267
3.3
3.333
35
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mA
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ELECTRICAL CHARACTERISTICS (continued)
5.0V ≤ VVCC ≤ 28V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.0
6.3
UNITS
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VVCC > 10 V, MPPSET > 175 mV
5.7
IREGN_LIM
REGN current limit
VREGN = 0 V, VVCC > VUVLO, MPPSET < 75 mV
40
V
mA
BATTERY DETECTION
tWAKE
Wake timer
Max time charge is enabled
IWAKE
Wake current
RSENSE = 10 mΩ
500
tDISCHARGE
Discharge timer
Max time discharge current is applied
1
sec
IDISCHARGE
Discharge current
6
mA
IFAULT
Fault current after a timeout fault
2
mA
IQUAL
Termination qualification current
2
mA
tQUAL
Termination qualification time
50
VWAKE
Wake threshold (with respect to VREG)
Voltage on VFB to detect battery absent during
wake
VDISCH
Discharge threshold
Voltage on VFB to detect battery absent during
discharge
125
ms
200
mA
250
ms
50
mV
1.55
V
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High side driver (HSD) turn-on resistance
RDS_HI_OFF
High side driver turn-off resistance
VBTST_REFRESH
Bootstrap refresh comparator threshold
Voltage
VBTST – VPH = 5.5 V
VBTST – VPH when low side refresh pulse is
requested
4.0
3.3
6
Ω
1
1.4
Ω
4.2
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver (LSD) turn-on resistance
RDS_LO_OFF
Low side driver turn-off resistance
4.1
7
Ω
1
1.4
Ω
PWM DRIVERS TIMING
Driver dead-time
Dead time when switching between LSD and
HSD, No load at LSD and HSD
PWM ramp height
As percentage of VCC
30
ns
PWM OSCILLATOR
VRAMP_HEIGHT
7%
PWM switching frequency
510
600
690
kHz
INTERNAL SOFT START (8 steps to regulation current ICHG)
Soft start steps
Soft start step time
8
step
1.6
ms
1.5
s
CHARGER SECTION POWER-UP SEQUENCING
Delay from MPPSET > 175 mV to charger is
allowed to turn on
Charge-enable delay after power-up
LOGIC IO PIN CHARACTERISTICS (STAT1, STAT2, TERM_EN)
VOUT_LOW
STAT1, STAT2 output low saturation
voltage
Sink current = 5 mA
0.5
V
IOUT_HI
Leakage current
V = 32 V
1.2
µA
VIN_LOW
TERM_EN input low threshold voltage
0.4
V
VIN_HI
TERM_EN input high threshold voltage
IIN_BIAS
TERM_EN bias current
60
µA
6
1.6
VTERM_EN = 0.5 V
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TYPICAL CHARACTERISTICS
VCC = 25V, bq24650 Application Circuit, TA = 25°C unless otherwise noted
MPPSET
1V/div
VCC
10V/div
LODRV
5V/div
VREF
2V/div
PH
20V/div
REGN
5V/div
STAT1
20V/div
IBAT
1A/div
400 ms/div
800 ms/div
Figure 2. Power Up on VCC
Figure 3. Charge Start on MPPSET
MPPSET
1V/div
MPPSET
1V/div
LODRV
5V/div
LODRV
5V/div
PH
20V/div
PH
20V/div
IBAT
1A/div
IBAT
1A/div
10 ms/div
4 ms/div
Figure 4. Charge Soft Start on MPPSET
Figure 5. Charge Stop on MPPSET
HIDRV
20V/div
HIDRV
20V/div
PH
20V/div
PH
20V/div
LODRV
5V/div
LODRV
5V/div
IL
1A/div
IL
1A/div
100 ns/div
Figure 6. Switching in Continuous Conduction Mode
200 ns/div
Figure 7. Switching in Discontinuous Conduction Mode
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TYPICAL CHARACTERISTICS (continued)
VCC = 25V, bq24650 Application Circuit, TA = 25°C unless otherwise noted
HIDRV
20V/div
HIDRV
20V/div
PH
20V/div
PH
20V/div
LODRV
5V/div
LODRV
5V/div
IL
1A/div
IL
1A/div
400 ms/div
100 ns/div
Figure 8. Switching at 100% Duty Cycle
VIN
5V/div
MPPT Regulation Point
Figure 9. Recharge the BTST-PH Capacitor
VIN
20V/div
VBAT
5V/div
PH
20V/div
IBAT
0.5A/div
IL
1A/div
10 ms/div
1 s/div
Figure 11. Battery Insertion and Removal
Figure 10. MPPT Regulation During Soft Start
VIN
20V/div
VIN
20V/div
VBAT
5V/div
VBAT
5V/div
PH
20V/div
PH
20V/div
IL
1A/div
IL
1A/div
400 ms/div
10 ms/div
Figure 12. Short Battery Response
8
Figure 13. Charge Reset During Battery Short
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TYPICAL CHARACTERISTICS (continued)
VCC = 25V, bq24650 Application Circuit, TA = 25°C unless otherwise noted
100
95
Efficiency - %
ICHG 2A
ICHG 1A
90
85
80
0
5
10
VO - Output Voltage - V
15
20
Figure 14. Efficiency vs Output Voltage (VCC = 25V)
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PIN FUNCTIONS
PIN
NO.
NAME
DESCRIPTION
1
VCC
P
IC power positive supply. Place a 1-mF ceramic capacitor from VCC to GND and place it as close as
possible to IC. Place a 10-Ω resistor from input side to VCC pin to filter the noise.
2
MPPSET
I
Input voltage set point. Use a voltage divider from input source to GND to set voltage on MPPSET to
1.2V. To disable charge, pull MPPSET below 75mV.
3
STAT1
O
Open drain charge status output to indicate various charger operation. Connect to the cathode of LED
with 10kΩ to the pull-up rail. LOW or LED light up indicates charge in progress. Otherwise stays HI or
LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off.
4
TS
I
Temperature qualification voltage input. Connect to a negative temperature coefficient thermistor.
Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. A
103AT-2 thermister is recommended.
5
STAT2
O
Open drain charge status output to indicate various charger operation. Connect to the cathode of LED
with 10kΩ to the pull-up rail. LOW or LED light up indicates charge is complete. Otherwise, stays HI or
LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off.
6
VREF
P
3.3V reference voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC.
This voltage could be used for programming voltage on TS and the pull-up rail of STAT1 and STAT2.
7
TERM_EN
I
Charge termination enable. Pull TERM_EN to GND to disable charge termination. Pull TERM_EN to
VREF to allow charge termination. TERM_EN must be terminated and cannot be left floating.
8
VFB
I
Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered from the
battery terminals to this node to adjust the output battery voltage regulation.
9
SRN
I
Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. An optional 0.1-mF ceramic capacitor is placed from SRN to GND for
common-mode filtering.
10
SRP
P/I
Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. A 0.1-mF ceramic capacitor is placed from SRP to GND for
common-mode filtering.
11
GND
P
Power ground. Ground connection for high-current power converter node. On PCB layout, connect
directly to source of low-side power MOSFET, to ground connection of input and output capacitors of the
charger. Only connect to GND through the thermal pad underneath the IC.
12
REGN
P
PWM low-side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to GND,
close to the IC. Use to drive low-side driver and high-side driver bootstrap Schottky diode from REGN to
BTST.
13
LODRV
O
PWM low-side driver output. Connect to the gate of the low-side N-channel power MOSFET with a short
trace.
14
PH
P
Switching node, charge current output inductor connection. Connect the 0.1-mF bootstrap capacitor from
PH to BTST.
15
HIDRV
O
PWM high-side driver output. Connect to the gate of the high-side N-channel power MOSFET with a short
trace.
16
BTST
P
PWM high-side driver positive supply. Connect the 0.1-uF bootstrap capacitor from PH to BTST.
Thermal
Pad
10
TYPE
Exposed pad beneath the IC. The thermal pad must always be soldered to the board and have the vias
on the thermal pad plane star-connecting to GND and ground plane for high-current power converter. It
also serves as a thermal pad to dissipate heat.
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BLOCK DIAGRAM
bq24650
VREF
VOLTAGE
REFERENCE
VCC
-
SRN+100 mV
+
SLEEP
VREF
3.3V
LDO
UVLO
VCC
VCC
-
VUVLO
+
SLEEP
UVLO
VCC
175 mV
+
FBO
MPPSET
1.2 V
COMP
ERROR
AMPLIFIER
+
-
EAI
2.1 V
CE
+
+
1V
+
VFB
BTST
EAO
PWM
-
LEVEL
SHIFTER
-
BAT_OVP
20uA
SRP
SRP-SRN
+
SYNCH
PH
+
20X
-
V(SRP-SRN)
0.8V
PWM
CONTROL
LOGIC
+
5 mV -
+
-
SRN
BTST
_+
PH
20 uA
VCC
6V LDO
REFRESH
-
CE
4V
LODRV
V(SRP-SRN)
-
200% X IBAT_REG
+
2 mA
CHG_OCP
GND
8 mA
FAULT
30 Minute
Precharge
Timer
CHARGE
DISCHARGE
TERM_EN
0.8V
STAT 1
IC Tj
+
145°C
-
TSHUT
CHARGE
STAT1
VFB
-
104% X 2.1V
+
BAT_OVP
STATE
MACHINE
LOGIC
IBAT_ REG
0.8V
10
STAT2
STAT 2
LOWV
1.5V +-
-
LOWV
BATTERY
DETECTION
LOGIC
DISCHARGE
VREF
+
VCC
+
LTF
ACOV
+
-
TS
+
VFB
REGN
+
FAULT
VFB
HIDRV
-
32V -
SUSPEND
RCHRG
HTF
+
+
-
2.05V +RCHRG
V(SRP - SRN)
0.8V
10
+
TERM
TERM
TCO
+
-
TERMINATE CHARGE
Figure 15. Functional Block Diagram
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DETAILED DESCRIPTION
Regulation Voltage
VRECH
Regulation Current
Precharge
Current
Regulation
Phase
Fastcharge Current
Regulation Phase
Fastcharge Voltage
Regulation Phase
Termination
Charge
Current
Charge
Voltage
VLOWV
IPRECH & ITERM
Figure 16. Typical Charging Profile
BATTERY VOLTAGE REGULATION
The bq24650 uses a high accuracy voltage regulator for the charging voltage. The charge voltage is
programmed via a resistor divider from the battery to ground, with the midpoint tied to the VFB pin. The voltage
at the VFB pin is regulated to 2.1V, giving the following equation for the regulation voltage:
é R2 ù
VBAT = 2.1 V ´ ê1+
ë R1 úû
(1)
where R2 is connected from VFB to the battery and R1 is connected from VFB to GND.
Li-Ion, LiFePO4, and sealed lead acid are widely used battery chemistries. Most commercial Li-ion cells can now
be charged to 4.2V/cell. A LiFePO4 battery allows a much higher charge and discharge rate, but the energy
density is lower. The typical cell voltage is 3.6V. The charge profile of both Li-Ion and LiFePO4 is
preconditioning, constant current, and constant voltage. For maximum cycle life, the end-of-charge voltage
threshold could be lowered to 4.1V/cell.
Although it's energy density is much lower than Li-based chemistry, lead acid is still popular due to its low
manufacturing cost and high discharge rates. The typical voltage limit is from 2.3V to 2.45V. After the battery has
been fully charged, a float charge is required to compensate for the self-discharge. The float charge limit is
100mV-200mV below the constant voltage limit.
INPUT VOLTAGE REGULATION
A solar panel has a unique point on the V-I or V-P curve, called the Maximum Power Point (MPP), at which the
entire photovoltaic (PV) system operates with maximum efficiency and produces its maximum output power. The
constant voltage algorithm is the simplest Maximum Power Point Tracking (MPPT) method. The bq24650
automatically reduces charge current so the maximum power point is maintained for maximum efficiency.
12
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If the solar panel or other input source cannot provide the total power of the system and bq24650 charger, the
input voltage drops. Once the voltage sensed on the MPPSET pin drops below 1.2V, the charger maintains the
input voltage by reducing the charge current. If the MPPSET pin voltage is forced below 1.2V, the bq24650 stays
in the input voltage regulation loop while the output current is zero. The STAT1 pin is LOW and STAT2 pin is
HIGH.
The voltage at the MPPSET pin is regulated to 1.2V, giving Equation 2 for the regulation voltage:
é R3 ù
VMPPSET = 1.2 V ´ ê1+
ú
ë R4 û
(2)
The MPPSET pin is also used as charge enable control. If the voltage on MPPSET is pulled down below 75mV,
charge is disabled. Charge resumes if the voltage on MPPSET goes back above 175mV.
BATTERY CURRENT REGULATION
Battery current is sensed by resistor RSR connected between SRP and SRN. The full-scale differential voltage
between SRP and SRN is fixed at 40mV. Thus, for a 20-mΩ sense resistor, the charging current is 2A. For
charging current, refer to Equation 3:
40 mV
ICHARGE =
RSR
(3)
BATTERY PRECHARGE
On power-up, if the battery voltage is below the VLOWV threshold, the bq24650 applies the precharge current to
the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within
30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
The precharge current is determined as 1/10 of the fast charge current according to the following equation:
4 mV
IPRECHARGE =
RSR
(4)
CHARGE TERMINATION AND RECHARGE
The bq24650 monitors the charging current during the voltage regulation phase. Termination is detected while
the voltage on the VFB pin is higher than the VRECH threshold and the charge current is less than the ITERM
threshold (1/10 of fast charge current), as calculated in Equation 5:
4 mV
ITERM =
RSR
(5)
A
•
•
•
new charge cycle is initiated when one of the following conditions occurs:
The battery voltage falls below the recharge threshold
A power-on-reset (POR) event occurs
MPPSET falls below 75mV to reset charge enable
The TERM_EN pin may be taken LOW to disable termination. If TERM_EN is pulled above 1.6V, the bq24650
allows termination.
POWER UP
The bq24650 uses a SLEEP comparator to determine the source of power on the VCC pin, since VCC can be
supplied either from a battery or an adapter. If the VCC voltage is greater than the SRN voltage, and all other
conditions are met for charging, the bq24650 then attempts to charge a battery (see the Enabling and
Disabling Charging section). If SRN voltage is greater than VCC, indicating that a battery is the power source,
the bq24650 enters low quiescent current (<15µA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, and VREF LDO turns off.
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ENABLE AND DISABLE CHARGING
The following conditions have to be valid before charging is enabled:
• Charge is allowed (MPPSET > 175mV)
• Device is not in Under-Voltage-Lock-Out (UVLO) mode and VCC is above the VCCLOWV threshold
• Device is not in SLEEP mode (i.e. VCC > SRN)
• VCC voltage is lower than AC over-voltage threshold (VCC < VACOV)
• 30ms delay is complete after initial power-up
• REGN LDO and VREF LDO voltages are at correct levels
• Thermal Shut (TSHUT) is not valid
• TS fault is not detected
One of the following conditions stops on-going charging:
• Charge is disabled (MPPSET < 75mV)
• Adapter is removed, causing the device to enter VCCLOWV or SLEEP mode
• Adapter voltage is less than 100mV above battery
• Adapter is over voltage
• REGN or VREF LDO voltage is not valid
• TSHUT IC temperature threshold is reached
• TS voltage goes out of range indicating the battery temperature is too hot or too cold
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts approximately 1.6ms, for a typical rise time of 13ms. No external components are needed for this
function.
CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A
type III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter must be selected to give a resonant frequency of 12 kHz – 17 kHz for the bq24650,
where resonant frequency, fo, is given by:
1
fo =
2p L o Co
(6)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage and simplifies the loop
compensation. The ramp is offset by 300mV in order to allow zero percent duty-cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100%
duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the
N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below
4.2V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side
n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the
high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again
due to leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region.
14
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SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5-A inductor current for
a 10-mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is
break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where
both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the
low-side FET turn on keeps power dissipation low, and allows safe charging at high currents. During
synchronous mode the inductor current is always flowing and the converter operates in continuous conduction
mode (CCM), creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5-A inductor
current for a 10-mΩ sense resistor). In addition, the charger is forced into non-synchronous mode when battery
voltage is lower than 2V or when the average SRP-SRN voltage is lower than 1.25mV.
During non-synchronous operation, the body-diode of the low-side MOSFET can conduct the positive inductor
current after the low-side n-channel power MOSFET turns off. When the load current decreases and the inductor
current drops to zero, the body diode is naturally turned off and the inductor current becomes discontinuous. This
mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side n-channel power MOSFET
turns on when the bootstrap capacitor voltage drops below 4.2V, then the low-side power MOSFET turns off and
stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The
low-side MOSFET on time is required to ensure the bootstrap capacitor is always recharged and able to keep the
high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular
dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current. The
low-side pulse pulls the PH node (connection between high and low-side MOSFETs) down, allowing the
bootstrap capacitor to recharge up to the REGN LDO value. After the refresh pulse, the low-side MOSFET is
kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the recharge pulse. The charge should be low enough to be absorbed by the input capacitance.
Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the
low-side MOSFET does not turn on (except for recharge pulse) either, and there is almost no discharge from the
battery.
During DCM mode the loop response automatically changes and has a single pole system at which the pole is
proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
CYCLE-BY-CYCLE CHARGE UNDER CURRENT
In the bq24650, if the SRP-SRN voltage decreases below 5mV, the low side FET is turned off for the remainder
of the switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on when the
bootstrap capacitor voltage drops below 4.2V to provide refresh charge for the bootstrap capacitor. This is
important to prevent negative inductor current from causing a boost effect in which the input voltage increases as
power is transferred from the battery to the input capacitors and lead to an over-voltage stress on the VCC node
and potentially cause damage to the system.
INPUT OVER-VOLTAGE PROTECTION (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled.
INPUT UNDER-VOLTAGE LOCK OUT (UVLO)
The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either input adapter or battery, since a conduction path exists from the battery to VCC through the high-side
NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC, including VREF LDO, are
disabled.
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BATTERY OVER-VOLTAGE PROTECTION
The converter does not allow the high-side FET to turn on until the BAT voltage goes below 102% of the
regulation voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load
is removed or the battery is disconnected. A current sink from SRP to GND is on to discharge the stored energy
on the output capacitors.
CYCLE-BY-CYCLE CHARGE OVER-CURRENT PROTECTION
The charger has a secondary cycle-to-cycle over-current protection. It monitors the charge current and prevents
the current from exceeding 200% of the programmed charge current. The high-side gate drive turns off when
over-current is detected and automatically resumes when the current falls below the over-current threshold.
THERMAL SHUTDOWN PROTECTION
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C.
TEMPERATURE QUALIFICATION
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. If battery
temperature is outside of this range, the controller suspends charge and waits until the battery temperature is
within the VLTF to VHTF range. During the charge cycle the battery temperature must be within the VLTF to VTCO
thresholds. If battery temperature is outside of this range, the controller suspends charge and waits until the
battery temperature is within the VLTF to VHTF range. The controller suspends charge by turning off the PWM
charge FETs. Figure 17 summarizes the operation.
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTFH
VLTF
VLTFH
TEMPERATURE RANGE
TO INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE
CYCLE
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
GND
GND
Figure 17. TS Pin, Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 1, the values of RT1 and RT2 can be
determined by using Equation 7 and Equation 8:
æ 1
1 ö
VVREF ´ RTHCOLD ´ RTHHOT ´ ç
÷
è VLTF VTCO ø
RT2 =
æV
ö
æV
ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
è VLTF
ø
è VTCO
ø
(7)
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VVREF
-1
VLTF
RT1 =
1
1
+
RT2
RTHCO LD
(8)
VREF
RT1
bq24650
TS
RTH
103AT
RT2
Figure 18. TS Resistor Network
CHARGE ENABLE
MPPSET is used to disable or enable the charge process. A voltage above 175mV on this pin enables charge,
provided all other conditions for charge are met (see the Enabling and Disabling Charge section). A voltage
below 75mV on this pin also resets all timers and fault conditions.
INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES
The bq24650 provides internal loop compensation. With this scheme, the best stability occurs when the LC
resonant frequency, fo, is approximately 12kHz – 17kHz for the bq24650.
Table 1 provides a summary of typical LC components for various charge currents.
Table 1. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current
CHARGE CURRENT
0.5A
1A
2A
4A
8A
10A
Output inductor low
22 µH
15 µH
10 µH
6.8 µH
3.3 µH
3.3 µH
Output capacitor CO
7 µF
10 µF
15 µF
20 µF
40 µF
40 µF
Sense resistor
80 mΩ
40 mΩ
20 mΩ
10 mΩ
5 mΩ
4 mΩ
CHARGE STATUS OUTPUTS
The open-drain STAT1 and STAT2 outputs indicate various charger operations as listed in Table 2. These status
pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates that the
open-drain transistor is turned off.
Table 2. STAT Pin Definition for bq24650
CHARGE STATE
STAT1
STAT2
Charge in progress
ON
OFF
Charge complete
OFF
ON
Charge suspend, over-voltage, sleep mode, battery absent
OFF
OFF
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BATTERY DETECTION
For applications with removable battery packs, the bq24650 provides a battery absent detection scheme to
reliably detect insertion or removal of battery packs.
POR or RECHARGE
The battery detection routine runs on
power up, or if VFB falls below VRECH
due to removing a battery or
discharging a battery
Apply 8mA discharge
current, start 1s timer
VFB < VLOWV
No
Yes
1s timer
expired
No
Yes
Battery Present,
Begin Charge
Disable 6mA
discharge current
Enable 125mA Charge,
Start 0.5s timer
VFB > VRECH
Yes
Disable 125mA
Charge
No
0.5s timer
expired
No
Yes
Battery Present,
Begin Charge
Battery Absent
Figure 19. Battery Detection Flowchart
Once the device has powered up, a 6-mA discharge current is applied to the SRN terminal. If the battery voltage
falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on
at low charge current (125mA). If the battery voltage gets up above the recharge threshold within 500ms, there is
no battery present and the cycle restarts. If either the 500ms or 1 second timer time out before the respective
thresholds are hit, a battery is detected and a charge cycle is initiated.
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Battery not detected
VREG
VRECH
(VWAKE)
Battery
inserted
VLOWV
(VDISCH)
Battery detected
tLOWV_DEG
tWAKE
tRECH_DEG
Figure 20. Battery Detect Timing Diagram
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the VFB voltage below the LOWV threshold during the 1 second discharge time. The
maximum output capacitance can be calculated according to Equation 9:
´ tDISCH
I
CMAX = DISCH
é R ù
0.5 ´ ê1+ 2 ú
ë R1 û
(9)
Where CMAX is the maximum output capacitance, IDISCH is the discharge current, tDISCH is the discharge time, and
R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. The 0.5 factor is the difference
between the RECHARGE and the LOWV thresholds at the VFB pin.
Example
For a 3-cell Li+ charger, with R2 = 500kΩ, R1 = 100kΩ (giving 12.6V for voltage regulation), IDISCH = 6mA, tDISCH
= 1 second.
6 mA ´ 1 sec
CMAX =
= 2000 μF
é 500 kW ù
0.5 ´ ê1+
ú
ë 100 kW û
(10)
Based on these calculations, no more than 2000 µF should be allowed on the battery node for proper operation
of the battery detection circuit.
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Component List for the Typical System Circuit in Figure 1
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2
2
N-channel MOSFET, 40 V, 10 A, PowerPAK SO-8, Vishay-Siliconix, Si7288
D2
1
Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D3, D4
2
LED Diode, Green, 2.1V, 20mA, LTST-C190GKT
RSR
1
Sense Resistor, 20 mΩ, Vishay-Dale, WSL1206R0200DEA
L1
1
Inductor, 10 µH, 7A, Vishay-Dale IHLP-2525CZ
C6, C8
2
Capacitor, Ceramic, 10 mF, 35 V, 20%, X7R, 1210, Panasonic
C9
1
Capacitor, Ceramic, 4.7 mF, 35 V, 20%, X7R, 1210, Panasonic
C2, C3, C4
3
Capacitor, Ceramic, 1 mF, 35 V, 10%, X7R, 0805, Kemet
C5, C7
2
Capacitor, Ceramic, 0.1 mF, 35 V, 10%, X7R, 0805, Kemet
C1
1
Capacitor, Ceramic, 2.2 mF, 35V, 10%, X7R, 1210, Kemet
C10
1
Capacitor, Ceramic, 22 pF, 35V, 10%, X7R, 0603 Kemet
R1
1
Resistor, Chip, 100 kΩ, 1/16W, 0.5%, 0402
R2, R3
2
Resistor, Chip, 499 kΩ, 1/16W, 0.5%, 0402
R4
1
Resistor, Chip, 36 kΩ, 1/16W, 0.5%, 0402
R9
1
Resistor, Chip, 5.23 kΩ, 1/16W, 1%, 0402
R10
1
Resistor, Chip, 30.1 kΩ, 1/16W, 1%, 0402
R7, R8
2
Resistor, Chip, 10 kΩ, 1/16W, 5%, 0402
R6
1
Resistor, Chip, 10 Ω, 1/4W, 5%, 1206
R5
1
Resistor, Chip, 2 Ω, 1W, 5%, 2012
D1
1
Diode, Schottky Rectifier, 40V, 10A, PDS1040
Q3
1
N-Channel MOSFET, 60V, 115mA, SOT-23, 2N7002DICT
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APPLICATION INFORMATION
INDUCTOR SELECTION
The bq24650 has a 600-kHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG +(1/2)IRIPPLE
(11)
Inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs), and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fs × L
(12)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of 20% to 40% of the maximum charging current as a trade-off between inductor size and efficiency for
a practical design.
INPUT CAPACITOR
The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst
case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate
at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50%
and can be estimated by the following equation:
ICIN = ICHG ´ D ´ (1 - D)
(13)
A low ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be
placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25V rating or higher
capacitor is preferred for a 20V input voltage. A 20mF capacitance is suggested for a typical 3A to 4A charging
current.
OUTPUT CAPACITOR
The output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given as:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(14)
The output capacitor voltage ripple can be calculated as follows:
DVO =
VOUT æ
V
ç 1 - OUT
2 ç
VIN
8LCfs è
ö
÷
÷
ø
(15)
At certain input/output voltages and switching frequencies, the voltage ripple can be reduced by increasing the
output filter inductor and capacitor values.
The bq24650 has an internal loop compensator. To achieve good loop stability, the resonant frequency of the
output inductor and output capacitor should be designed between 12 kHz and 17 kHz. The preferred ceramic
capacitor has a 35V or higher rating, X7R or X5R.
Ceramic capacitors show a de-bias effect. This effect reduces the effective capacitance when a dc-bias voltage
is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a
significant capacitance drop, especially for high voltages and small capacitor packages. See the manufacturer’s
datasheet about performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to achieve the required value at the operating point.
POWER MOSFETS SELECTION
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are
preferred for 20V input voltage, and 40V or higher rating MOSFETs are preferred for 20V to 28V input voltage.
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Figure-of-merit (FOM) is usually used for selecting a proper MOSFET based on a tradeoff between conduction
loss and switching loss. For a top-side MOSFET, FOM is defined as the product of the MOSFET's on-resistance,
RDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(on), and the total gate charge, QG.
FOMtop = RDS(on) ´ QGD ; FOMbottom = RDS(ON) ´ QG
(16)
The lower the FOM value, the lower the total power loss. Usually a lower RDS(on) has a higher cost with the same
package size.
Top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D = VOUT/VIN),
charging current (ICHG), the MOSFET's on-resistance RDS(on), input voltage (VIN), switching frequency (F), turn-on
time (ton) and turn-off time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(ON) + ´ VIN ´ ICHG ´ (t on + t off ) ´ F
2
(17)
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction
temperature rise. The second term represents switching loss. The MOSFET turn-on and turn-off times are given
by:
Q
Q
t on = SW ; t off = SW
Ion
Ioff
(18)
where QSW is the switching charge, Ion is the turn-on gate driving current, and Ioff is the turn-off gate driving
current. If the switching charge is not given in the MOSFET datasheet, it can be estimated by gate-to-drain
charge (QGD) and gate-to-source charge (QGS):
1
QSW = QGD + ´ QGS
2
(19)
The gate driving current total can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (VPLT),
total turn-on gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:
VREGN - Vplt
Vplt
Ion =
; Ioff =
Ron
Roff
(20)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) ´ ICHG2 ´ RDS(ON)
(21)
If the SRP-SRN voltage decreases below 5mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all of the freewheeling current goes through the body diode of the bottom-side MOSFET. The
maximum charging current in non-synchronous mode can be up to 0.9A (0.5A typ) for a 10-mΩ charging current
sensing resistor, considering the IC tolerance. Choose a bottom-side MOSFET with either an internal Schottky or
body diode capable of carrying the maximum non-synchronous mode charging current.
MOSFET gate driver power loss contributes to dominant losses on the controller IC, when the buck converter is
switching. Choosing a MOSFET with a small Qg_total reduces power loss to avoid thermal shutdown.
PICLOSS_Driver = VIN ´ Qg_total ´ fs
(22)
Where Qg_total is the total gate charge for both the upper and lower MOSFETs at 6V VREGN.
INPUT FILTER DESIGN
During adapter hot plug-in, the parasitic inductance and the input capacitor from the adapter cable form a second
order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the
IC. The input filter must be carefully designed and tested to prevent an over-voltage event on the VCC pin.
22
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There are several methods to damping or limiting the over-voltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the over-voltage spike well below the IC
maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over-voltage level to an
IC safe level. However, these two solutions may not be lowest cost or smallest size.
A cost effective and small size solution is shown in Figure 21. R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result, the over-voltage spike is limited to a safe level. D1 is
used for reverse voltage protection for the VCC pin. C2 is the VCC pin decoupling capacitor and it should be
placed as close as possible to the VCC pin. R2 and C2 form a damping RC network to further protect the IC from
high dv/dt and high voltage spike. The C2 value should be less than the C1 value so R1 can dominant the
equivalent ESR value to get enough damping effect for hot plug-in. R1 and R2 must be sized enough to handle
in-rush current power loss according to the resistor manufacturer’s datasheet. The filter component values
always need to be verified with a real application.
D1
Adapter
Connector
R2(1206)
4.7 - 30 W
R1(2010)
2W
VCC pin
C1
2.2 mF
C2
0.1 - 1 mF
Figure 21. Input Filter
MPPT TEMPERATURE COMPENSATION
A typical solar panel comprises of alot of cells in a series connection, and each cell is a forward-biased p-n
junction. So, the open-circuit voltage (VOC) of a solar cell has a temperature coefficient that is similar to a
common p-n diode, or about –2mV/°C. A crystalline solar panel specification always provides both open-circuit
voltage VOC and peak power point voltage VMP. The difference between VOC and VMP can be approximated as
fixed and temperature-independent, so the temperature coefficient for the peak power point is similar to that of
VOC. Normally, panel manufacturers specify the 25°C values for VOC and VMP, and the temperature coefficient for
VOC, as shown in the following figure.
Panel Voltage - V
VOC
VMP
5
15
25
35
45
55
TA - Free-Air Temperature - °C
Figure 22. Solar Panel Output Voltage Temperature Characteristics
The bq24650 employs a feedback network to the MPPSET pin to program the input regulation voltage. Because
the temperature characteristic for a typical solar panel VMP voltage is almost linear, a simple solution for tracking
this characteristic can be implemented by using an LM234 3-terminal current source, which can create an easily
programmable, linear temperature dependent current to compensate the negative temperature coefficient of the
solar panel output voltage.
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bq24650
SLUSA75 – JULY 2010
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R21: 20Ω
VIN
Solar
Panel
R20
2Ω
C21
2.2mF
C21
0.47mF
LM234
VCC
R3
I1
RSET
ISET
VREG
R4
I2
MPPSET
bq24650
Figure 23. Feedback Network
In the circuit shown in Figure 23, for the LM234 temperature sensor,
227 μV/ °K
ISET =
´ Temp
RSET
(23)
Thus,
0.0677V
RSET
(24)
The current node equation is,
V
V - VREG
I2 = REG = I1 + ISET = IN
+ ISET
R4
R3
(25)
To have a zero temperature coefficient on VREG,
d(VIN - VREG )
dI
dI2
1
=
×
+ SET = 0
dT
dT
R3
dT
(26)
ISET (25°C) =
æ -dVIN /dT ö
2mV × number of solar cells in series
R3 = ç
÷ = RSET ×
dI
/dT
227μV
è SET
ø
VREG × R3
VMPPSET × R3
R4 =
=
æ
(VIN + R3 × ISET ) - VREG
0.0677V ö
ç VMP (25°C) + R3 ×
÷ - VMPPSET
RSET ø
è
(27)
(28)
For example, given a common 18-cell solar panel that has the following specified characteristics:
Open circuit voltage (VOC) = 10.3V
Maximum power voltage (VMP) = 9V
Open-circuit voltage temperature coefficient (VOC) = –38mV/°C
Appling the following parameters into the equations of R3 and R4:
1. Temperature coefficient for VMP (same as that of VOC) of –38mV/°C
2. Peak power voltage of 9V
3. MPPSET regulation voltage of 1.2V
And choosing RSET = 1000Ω.
The resistor values are RSET = 1kΩ, R3 = 167.4kΩ, and R4=10.6kΩ. Selecting standard 1% accuracy resistors
and RSET = 1kΩ, R3 = 169kΩ, and R4=10.7kΩ.
24
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bq24650
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SLUSA75 – JULY 2010
PCB LAYOUT
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high frequency current path loop (see Figure 24) is important to prevent electrical
and magnetic field radiation and high frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place input capacitor as close as possible to the switching MOSFET supply and ground connections and use
the shortest copper trace connection. These parts should be placed on the same layer of the PCB instead of
on different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals, and the gate drive signal traces
kept short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize
loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection
for best current accuracy). Place decoupling capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route analog ground separately from power ground and use a single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Connect analog ground to the GND pin. Use the thermal
pad as a single ground connection point to connect analog ground and power ground together, or use a 0-Ω
resistor to tie analog ground to power ground (thermal pad should tie to analog ground in this case). A
star-connection under the thermal pad is highly recommended.
8. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
10. The number and physical size of the vias should be enough for a given current path.
SW
L1
R1
High
Frequency
VIN
C1
Current
Path
VBAT
BAT
PGND
C2
C3
Figure 24. High Frequency Current Path
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bq24650
SLUSA75 – JULY 2010
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Charge Current Direction
R SNS
To Inductor
To Battery
Current Sensing Direction
To SRP and SRN pin
Figure 25. Sensing Resistor PCB Layout
26
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
BQ24650RVAR
ACTIVE
VQFN
RVA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PAS
BQ24650RVAT
ACTIVE
VQFN
RVA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PAS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24650RVAR
VQFN
RVA
16
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24650RVAT
VQFN
RVA
16
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24650RVAR
VQFN
RVA
16
3000
367.0
367.0
35.0
BQ24650RVAT
VQFN
RVA
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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