Cypress Semiconductor | Perform STK12C68 | STK12C68 64 Kbit (8K x 8) AutoStore nvSRAM

STK12C68
64 Kbit (8 K x 8) AutoStore nvSRAM
Features
Functional Description
■
25 ns, 35 ns, and 45 ns access times
■
Hands off automatic STORE on power-down with external
68 µF capacitor
■
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
■
RECALL to SRAM initiated by software or power-up
■
Unlimited read, write, and recall cycles
■
1,000,000 STORE cycles to QuantumTrap
■
100 year data retention to QuantumTrap
The Cypress STK12C68 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
■
Single 5 V + 10% operation
■
Commercial and industrial temperatures
■
28-pin (330 mil) SOIC, 28-pin (300 mil) PDIP, 28-pin (600 mil)
PDIP packages
■
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
■
RoHS compliance
Logic Block Diagram
A5
A7
A8
A9
A 11
STATIC RAM
ARRAY
128 X 512
RECALL
STORE/
RECALL
CONTROL
DQ 0
DQ 4
DQ 5
DQ 6
A0
- A 12
COLUMN I/O
INPUT BUFFERS
DQ 2
DQ 3
HSB
SOFTWARE
DETECT
A 12
DQ 1
VCAP
POWER
CONTROL
STORE
ROW DECODER
A6
VCC
Quantum Trap
128 X 512
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-51027 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 21, 2014
STK12C68
Contents
Pin Configurations ...........................................................
Pin Definitions ..................................................................
Device Operation ..............................................................
SRAM Read .......................................................................
SRAM Write .......................................................................
AutoStore Operation ........................................................
AutoStore Inhibit Mode ....................................................
Hardware STORE (HSB) Operation.................................
Hardware RECALL (Power-up)........................................
Software STORE ...............................................................
Software RECALL.............................................................
Data Protection .................................................................
Noise Considerations.......................................................
Hardware Protect..............................................................
Low Average Active Power..............................................
Preventing Store...............................................................
Best Practices...................................................................
Maximum Ratings.............................................................
Operating Range...............................................................
DC Electrical Characteristics ..........................................
Document Number: 001-51027 Rev. *G
3
3
4
4
4
4
5
5
5
5
6
6
6
6
6
6
7
8
8
8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance.......................................................... 9
AC Test Conditions .......................................................... 9
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle..................................................... 11
AutoStore or Power-up RECALL................................... 12
Software Controlled STORE/RECALL Cycle................ 13
Hardware STORE Cycle ................................................. 14
Switching Waveform ...................................................... 14
Part Numbering Nomenclature...................................... 15
Ordering Information...................................................... 15
Package Diagrams.......................................................... 16
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Page 2 of 22
STK12C68
Pin Configurations
Figure 1. 28-Pin SOIC/DIP and LLC
Pin Definitions
Pin Name
Alt
A0–A12
I/O Type
Input
DQ0-DQ7
Description
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Input or Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
OE
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-51027 Rev. *G
Page 3 of 22
STK12C68
Device Operation
The STK12C68 nvSRAM is made up of two functional
components paired in the same physical cell. These are an
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK12C68 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL
operations from the nonvolatile cells and up to one million
STORE operations.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage capacitor
between 68 µF and 220 µF (+20%) rated at 6 V should be
provided. The voltage on the VCAP pin is driven to 5 V by a
charge pump internal to the chip. A pull-up is placed on WE to
hold it inactive during power-up.
Figure 2. AutoStore Mode
Vcc
WE
10k Ohm
VCAP
0.15 F
Bypass
HSB
68 5F
6v, +20%
The STK12C68 performs a Read cycle whenever CE and OE are
LOW while WE and HSB are HIGH. The address specified on
pins A0–12 determines the 8,192 data bytes accessed. When the
Read is initiated by an address transition, the outputs are valid
after a delay of tAA (Read cycle 1). If the Read is initiated by CE
or OE, the outputs are valid at tACE or at tDOE, whichever is later
(Read cycle 2). The data outputs repeatedly respond to address
changes within the tAA access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
10k Ohm
SRAM Read
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ0–7 are written into the memory if it has valid tSD, before
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
AutoStore Operation
The STK12C68 stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power-down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK12C68.
Document Number: 001-51027 Rev. *G
Vss
In system power mode, both VCC and VCAP are connected to the
+5 V power supply without the 68 F capacitor. In this mode, the
AutoStore function of the STK12C68 operates on the stored
system charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6 V during the 10 ms
STORE cycle.
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations are ignored, unless at least one Write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a Write operation has taken place. An
optional pull-up resistor is shown connected to HSB. The HSB
signal is monitored by the system to detect if an AutoStore cycle
is in progress.
Page 4 of 22
STK12C68
Vcc
WE
10k Ohm
VCAP
10k Ohm
0.15 F
Bypass
Figure 3. AutoStore Inhibit Mode
HSB
the STK12C68 continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM Read operations take place. If a Write is
in progress when HSB is pulled LOW, it allows a time, tDELAY to
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK12C68 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK12C68 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power-up)
During power-up or after any low power condition (VCC <
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Vss
If the STK12C68 is in a Write state at the end of power-up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 k resistor is connected either between WE and
system VCC or between CE and system VCC.
Software STORE
If the power supply drops faster than 20 us/volt before Vcc
reaches VSWITCH, then a 2.2  resistor should be connected
between VCC and the system supply to avoid momentary excess
of current between VCC and VCAP.
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then VCC
is tied to ground and +5 V is applied to VCAP (Figure 3). This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the STK12C68 is operated in this configuration,
references to VCC are changed to VCAP throughout this data
sheet. In this mode, STORE operations are triggered through
software control or the HSB pin. To enable or disable Autostore
using an I/O port pin see Preventing Store on page 6. It is not
permissible to change between these three options “on the fly”.
Hardware STORE (HSB) Operation
The STK12C68 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK12C68 conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a Write to the
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress.
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
Document Number: 001-51027 Rev. *G
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK12C68 software STORE
cycle is initiated by executing sequential CE controlled Read
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of Reads from specific addresses is used
for STORE initiation, it is important that no other Read or Write
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following Read
sequence is performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
The software sequence is clocked with CE controlled Reads or
OE controlled Reads. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that Read cycles and not Write cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is again activated for Read and Write operation.
Page 5 of 22
STK12C68
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled Read operations is
performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
■
The duty cycle of chip enable
■
The overall cycle rate for accesses
■
The ratio of Reads to Writes
■
CMOS versus TTL input levels
■
The operating temperature
■
The VCC level
■
I/O loading
Figure 4. Current Versus Cycle Time (Read)
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Data Protection
The STK12C68 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when VCC is
less than VSWITCH. If the STK12C68 is in a Write mode (both CE
and WE are low) at power-up after a RECALL or after a STORE,
the Write is inhibited until a negative transition on CE or WE is
detected. This protects against inadvertent writes during
power-up or brown out conditions.
Figure 5. Current Versus Cycle Time (Write)
Noise Considerations
The STK12C68 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK12C68 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage
conditions. When VCAP<VSWITCH, all externally initiated STORE
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5 V
to VCAP. This is the AutoStore Inhibit mode; in this mode,
STOREs are only initiated by explicit request using either the
software sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK12C68 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 shows the relationship between ICC and
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial
temperature range, VCC = 5.5 V, 100% duty cycle on chip
enable). Only standby current is drawn when the chip is disabled.
The overall average current drawn by the STK12C68 depends
on the following items:
Document Number: 001-51027 Rev. *G
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a VOH of at least 2.2 V,
because it must overpower the internal pull-down device. This
device drives HSB LOW for 20 s at the onset of a STORE.
When the STK12C68 is connected for AutoStore operation
(system VCC connected to VCC and a 68 F capacitor on VCAP)
and VCC crosses VSWITCH on the way down, the STK12C68
attempts to pull HSB LOW. If HSB does not actually get below
VIL, the part stops trying to pull HSB LOW and abort the STORE
attempt.
Page 6 of 22
STK12C68
Best Practices
manufacturing test to ensure these system routines work
consistently.
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that an NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration,
cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
■
Power-up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. The best practice is to meet this
requirement and not exceed the maximum VCAP value because
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers who want to use a larger
VCAP value to make sure there is extra store charge should
discuss their VCAP size selection with Cypress.
Table 1. Hardware Mode Selection
CE
WE
HSB
A12–A0
Mode
I/O
Power
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active[3]
L
L
H
X
Write SRAM
Input Data
Active
X
X
L
X
Nonvolatile STORE
Output High Z
ICC2[1]
L
H
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[2, 3]
L
H
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[2, 3]
Notes
1. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby
mode, inhibiting all operations until HSB rises.
2. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
3. I/O state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE.
Document Number: 001-51027 Rev. *G
Page 7 of 22
STK12C68
Maximum Ratings
Voltage on DQ0-7 or HSB .................... –0.5 V to VCC + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Power Dissipation......................................................... 1.0 W
DC output Current (1 output at a time, 1s duration) .... 15 mA
Operating Range
Temperature under Bias ........................... –55 C to +125 C
Range
Voltage on Input Relative to GND...................–0.5 V to 7.0 V
Commercial
Voltage on Input Relative to VSS ......... –0.6 V to VCC + 0.5 V
Industrial
Ambient Temperature
VCC
0 C to +70C
4.5 V to 5.5 V
–40 C to +85 C
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V) [4]
Parameter
Description
Test Conditions
Min
Max
Unit
ICC1
Average VCC current
tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate. Values obtained
without output loads.
IOUT = 0 mA.
–
85
75
65
mA
mA
mA
ICC2
Average VCC current
during STORE
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
–
3
mA
ICC3
Average VCC current at WE > (VCC – 0.2 V). All other inputs cycling.
tRC= 200 ns, 5 V, 25 °C Dependent on output loading and cycle rate. Values obtained
without output loads.
Typical
–
10
mA
ICC4
Average VCAP Current All Inputs Do Not Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
–
2
mA
ISB1[5]
VCC standby current
(standby, cycling TTL
input levels)
tRC = 25 ns, CE > VIH
tRC = 35 ns, CE > VIH
tRC = 45 ns, CE > VIH
–
27
24
20
mA
mA
mA
ISB2 [5]
VCC standby current
CE > (VCC – 0.2 V). All others VIN < 0.2 V or > Commercial
(VCC – 0.2 V). Standby current level after
nonvolatile cycle is complete.
Industrial
Inputs are static. f = 0 MHz.
–
1.5
mA
–
2.5
mA
IIX
Input leakage current
VCC = Max, VSS < VIN < VCC
–1
+1
A
IIX
Input leakage current
VCC = Max, VSS < VIN < VCC
–1
+1
A
IOZ
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
–-5
+5
A
VIH
Input HIGH voltage
2.2
VCC +
0.5
V
VIL
Input LOW voltage
VSS – 0.5
0.8
V
VOH
Output HIGH voltage
IOUT = –4 mA
2.4
VOL
Output LOW voltage
IOUT = 8 mA
–
0.4
V
VBL
Logic ‘0’ voltage on
HSB output
IOUT = 3 mA
–
0.4
V
VCAP
Storage capacitor
Between VCAP pin and VSS, 6 V rated. 68 µF +20% nominal
54
260
µF
V
Notes
4. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
5. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
Document Number: 001-51027 Rev. *G
Page 8 of 22
STK12C68
Data Retention and Endurance
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
100
Years
1,000
K
Capacitance
In the following table, the capacitance parameters are listed.[6]
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VCC = 0 to 3.0 V
Max
Unit
8
pF
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[6]
Parameter
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA /
JESD51.
28-PDIP
28-SOIC (300
mil)
28-PDIP
(600 mil) 28-CDIP 28-LCC
Unit
46.55
45.16
55.84
46.1
95.31
C/W
27.95
31.62
25.74
5.01
9.01
C/W
Figure 6. AC Test Loads
R1 963  For Tristate Specs
R1 963 
5.0 V
5.0 V
Output
Output
30 pF
R2
512 
5 pF
R2
512 
AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V
Input rise and fall times (10% to 90%).......................... <5 ns
Input and output timing reference levels ...........................1.5
Note
6. These parameters are guaranteed by design and are not tested.
Document Number: 001-51027 Rev. *G
Page 9 of 22
STK12C68
AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Alt
Parameter
tELQV
tACE
tAVAV, tELEH
tRC [7]
tAVQV
tAA [8]
tGLQV
tDOE
tAXQX
tOHA [8]
tELQX
tLZCE [9]
tEHQZ
tHZCE [9]
[9]
tGLQX
tLZOE
tGHQZ
tHZOE [9]
tELICCH
tPU [6]
[6]
tEHICCL
tPD
25 ns
Description
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
35 ns
45 ns
Min
Max
Min
Max
Min
Max
–
25
–
–
5
5
–
0
–
0
–
25
–
25
10
–
–
10
–
10
–
25
–
35
–
–
5
5
–
0
–
0
–
35
–
35
15
–
–
10
–
10
–
35
–
45
–
–
5
5
–
0
–
0
–
45
–
45
20
–
–
12
–
12
–
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled [7, 8]
tRC
ADDRESS
t AA
tOHA
DQ (DATA OUT)
DATA VALID
Figure 8. SRAM Read Cycle 2: CE and OE Controlled [7]
tRC
ADDRESS
tLZCE
CE
tACE
tPD
tHZCE
OE
tLZOE
DQ (DATA OUT)
t PU
ICC
tHZOE
tDOE
DATA VALID
ACTIVE
STANDBY
Notes
7. WE and HSB must be High during SRAM Read cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
Document Number: 001-51027 Rev. *G
Page 10 of 22
STK12C68
SRAM Write Cycle
Parameter
Cypress
Parameter
25 ns
Description
Alt
tAVAV
tWLWH, tWLEH
tELWH, tELEH
tDVWH, tDVEH
tWHDX, tEHDX
tAVWH, tAVEH
tAVWL, tAVEL
tWHAX, tEHAX
tWLQZ
tWHQX
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE [9,10]
tLZWE [9]
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
35 ns
45 ns
Min
Max
Min
Max
Min
Max
25
20
20
10
0
20
0
0
–
5
–
–
–
–
–
–
–
–
10
–
35
25
25
12
0
25
0
0
–
5
–
–
–
–
–
–
–
–
13
–
45
30
30
15
0
30
0
0
–
5
–
–
–
–
–
–
–
–
14
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Figure 9. SRAM Write Cycle 1: WE Controlled [11, 12]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tSD
tHD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 10. SRAM Write Cycle 2: CE Controlled [11, 12]
tWC
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Notes
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
11. HSB must be high during SRAM Write cycles.
12. CE or WE must be greater than VIH during address transitions.
Document Number: 001-51027 Rev. *G
Page 11 of 22
STK12C68
AutoStore or Power-up RECALL
Parameter
Alt
tHRECALL [13]
tSTORE [14, 15, 16]
tDELAY [9, 15]
VSWITCH
VRESET
tVCCRISE
tVSBL[11]
tRESTORE
tHLHZ
tHLQZ , tBLQZ
Description
Power-up RECALL duration
STORE cycle duration
Time allowed to complete SRAM cycle
Low voltage trigger level
Low voltage reset level
VCC rise time
Low voltage trigger (VSWITCH) to HSB Low
STK12C68
Min
Max
–
550
–
10
1
–
4.0
4.5
–
3.9
150
–
–
300
Unit
s
ms
s
V
V
s
ns
Switching Waveform
Figure 11. AutoStore/Power-up RECALL
WE
Notes
13. tHRECALL starts from the time VCC rises above VSWITCH.
14. CE and OE low for output behavior.
15. CE and OE low and WE high for output behavior.
16. HSB is asserted low for 1us when VCAP drops through VSWITCH. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store
takes place.
Document Number: 001-51027 Rev. *G
Page 12 of 22
STK12C68
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [18]
Parameter
Alt
Description
25 ns
35 ns
45 ns
Min
Max
Min
Max
Min
Max
Unit
tRC[14]
tAVAV
STORE/RECALL initiation cycle time
25
–
35
–
45
–
ns
tSA[17]
tCW[17]
tHACE[17]
tAVEL
Address setup time
0
–
0
–
0
–
ns
tELEH
Clock pulse width
20
–
25
–
30
–
ns
tELAX
Address hold time
20
–
20
–
20
–
ns
RECALL duration
–
20
–
20
–
20
s
tRECALL
Switching Waveform
Figure 12. CE Controlled Software STORE/RECALL Cycle [18]
tRC
ADDRESS # 1
ADDRESS
tSA
tRC
ADDRESS # 6
tSCE
CE
tHACE
OE
t STORE / t RECALL
DQ (DATA)
DATA VALID
DATA VALID
HIGH IMPEDANCE
Notes
17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
18. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
Document Number: 001-51027 Rev. *G
Page 13 of 22
STK12C68
Hardware STORE Cycle
Parameter
tSTORE [9, 14]
tDHSB
tPHSB
[14, 19]
Alt
tHLHZ
Description
STK12C68
Min
STORE Cycle duration
10
tRECOVER, tHHQX Hardware STORE High to inhibit off
tHLHX
tHLBL
Hardware STORE pulse width
Hardware STORE Low to STORE busy
Max
700
15
Unit
ms
ns
ns
300
ns
Switching Waveform
Figure 13. Hardware STORE Cycle
Note
19. tDHSB is only applicable after tSTORE is complete.
Document Number: 001-51027 Rev. *G
Page 14 of 22
STK12C68
Part Numbering Nomenclature
STK12C68 - S F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
Temperature Range:
C - Commercial (0 to 70 °C)
I - Industrial (–40 to 85 °C)
Lead Finish
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
F = 100% Sn (Matte Tin)
Package:
S = Plastic 28-pin 330 mil SOIC
P = Plastic 28-pin 300 mil DIP
W = Plastic 28-pin 600 mil DIP
C = Ceramic 28-pin 300 mil DIP
L = Ceramic 28-pin LLC
Ordering Information
These parts are not recommended for new designs. They are in production to support ongoing production programs only.
Speed (ns)
25
45
Ordering Code
Package Diagram
Package Type
STK12C68-SF25TR
51-85058
28-pin SOIC (330 mil)
STK12C68-SF25
51-85058
28-pin SOIC (330 mil)
STK12C68-SF25ITR
51-85058
28-pin SOIC (330 mil)
STK12C68-SF25I
51-85058
28-pin SOIC (330 mil)
STK12C68-PF25I
51-85014
28-pin PDIP (300 mil)
STK12C68-SF45TR
51-85058
28-pin SOIC (330 mil)
STK12C68-SF45
51-85058
28-pin SOIC (330 mil)
STK12C68-SF45ITR
51-85058
28-pin SOIC (330 mil)
STK12C68-SF45I
51-85058
28-pin SOIC (330 mil)
STK12C68-C45I
001-51695
28-pin CDIP (300 mil)
Operating Range
Commercial
Industrial
Commercial
Industrial
All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts
Document Number: 001-51027 Rev. *G
Page 15 of 22
STK12C68
Package Diagrams
Figure 14. 28-Pin (330 Mil) SOIC (51-85058)
51-85058 *C
Document Number: 001-51027 Rev. *G
Page 16 of 22
STK12C68
Package Diagrams (continued)
Figure 15. 28-Pin (300 Mil) PDIP (51-85014)
51-85014 *G
Document Number: 001-51027 Rev. *G
Page 17 of 22
STK12C68
Package Diagrams (continued)
Figure 16. 28-Pin (600 Mil) PDIP (51-85017)
51-85017 *E
Document Number: 001-51027 Rev. *G
Page 18 of 22
STK12C68
Package Diagrams (continued)
Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695)
001-51695 *B
Document Number: 001-51027 Rev. *G
Page 19 of 22
STK12C68
Package Diagrams (continued)
Figure 18. 28-Pad (350 Mil) LCC (001-51696)
001-51696 *B
Document Number: 001-51027 Rev. *G
Page 20 of 22
STK12C68
Document History Page
Document Title: STK12C68 64 Kbit (8 K x 8) AutoStore nvSRAM
Document Number: 001-51027
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
2606744
GVCH
01/30/2009
New data sheet
*A
2826441
GVCH
12/11/2009
Added following text in the Ordering Information section: “These parts are
not recommended for new designs. In production to support ongoing production programs only.”
Added watermark in PDF stating “Not recommended for new designs. In
production to support ongoing production programs only.”
Added Contents on page 2.
*B
3054694
GVCH
10/12/2010
Removed the following prune parts from the document;
STK12C68-C35I
STK12C68-C45
STK12C68-L35
STK12C68-L35I
STK12C68-L45
STK12C68-L45I
STK12C68-PF25
STK12C68-PF45
STK12C68-PF45I
STK12C68-WF45
STK12C68-WF45I
STK12C68-WF25
*C
3189527
GVCH
03/07/2011
Added watermark in PDF stating “Not recommended for new designs. In
production to support ongoing production programs only.”
*D
3208949
GVCH
03/30/11
Removed pruned part “STK12C68-C35” from the ordering code information.
*E
3229103
GVCH
04/15/11
Added missing watermark “Not Recommended for New Designs.
In production to support ongoing production programs only.” that was found
in *C revision.
*F
3402039
GVCH
10/12/2011
Removed pruned device STK12C68-WF25I from Ordering Information.
Updated Package Diagrams and Table of Contents.
*G
4303589
GVCH
03/21/2014
Figure 17: Updated Package diagram from *A to *B revision
Figure 18: Updated Package diagram from *A to *B revision
Sunset review
Document Number: 001-51027 Rev. *G
Page 21 of 22
STK12C68
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51027 Rev. *G
Revised March 21, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 22 of 22
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