IRL3715ZSPBF

IRL3715ZSPBF
PD - 95581
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l Lead-Free
Benefits
l Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
IRL3715ZPbF
IRL3715ZSPbF
IRL3715ZLPbF
HEXFET® Power MOSFET
VDSS RDS(on) max
11m:
20V
D2Pak
IRL3715ZS
TO-220AB
IRL3715Z
Qg
7.0nC
TO-262
IRL3715ZL
Absolute Maximum Ratings
Parameter
Max.
Units
20
V
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
50
A
36
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
VDS
Drain-to-Source Voltage
VGS
ID @ TC = 25°C
ID @ TC = 100°C
c
h
h
200
PD @TC = 25°C
Maximum Power Dissipation
45
PD @TC = 100°C
Maximum Power Dissipation
23
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
W
0.30
-55 to + 175
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
f
W/°C
°C
300 (1.6mm from case)
y
y
10 lbf in (1.1N m)
Thermal Resistance
Parameter
RθJC
Junction-to-Case
RθCS
Case-to-Sink, Flat Greased Surface
RθJA
Junction-to-Ambient
RθJA
Junction-to-Ambient (PCB Mount)
f
f
g
Typ.
Max.
Units
–––
3.33
°C/W
0.50
–––
–––
62
–––
40
Notes  through † are on page 12
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1
07/20/04
IRL3715Z/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
∆ΒVDSS/∆TJ
RDS(on)
20
–––
–––
Breakdown Voltage Temp. Coefficient
–––
0.014
–––
Static Drain-to-Source On-Resistance
–––
9.2
11
–––
12.4
15.5
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 15A
VGS = 4.5V, ID = 12A
VGS(th)
Gate Threshold Voltage
1.65
2.1
2.55
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-5.2
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = 16V, VGS = 0V
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
IGSS
gfs
Qg
Forward Transconductance
e
e
VDS = VGS, ID = 250µA
VDS = 16V, VGS = 0V, TJ = 125°C
VGS = -20V
S
VDS = 10V, ID = 12A
31
–––
–––
Total Gate Charge
–––
7.0
11
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.1
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.9
–––
Qgd
Gate-to-Drain Charge
–––
2.3
–––
ID = 12A
Qgodr
–––
1.7
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
3.2
–––
Qoss
Output Charge
–––
3.7
–––
td(on)
Turn-On Delay Time
–––
7.1
–––
tr
Rise Time
–––
44
–––
td(off)
Turn-Off Delay Time
–––
11
–––
tf
Fall Time
–––
4.6
–––
Ciss
Input Capacitance
–––
870
–––
Coss
Output Capacitance
–––
270
–––
Crss
Reverse Transfer Capacitance
–––
140
–––
VDS = 10V
nC
nC
VGS = 4.5V
VDS = 10V, VGS = 0V
VDD = 10V, VGS = 4.5V
e
ID = 12A
ns
Clamped Inductive Load
pF
VDS = 10V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
Max.
44
Units
mJ
–––
12
A
–––
4.5
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
ISM
(Body Diode)
Pulsed Source Current
–––
–––
VSD
(Body Diode)
Diode Forward Voltage
–––
trr
Reverse Recovery Time
–––
Qrr
Reverse Recovery Charge
–––
2
c
50
h
Conditions
MOSFET symbol
A
D
200
showing the
integral reverse
–––
1.0
V
p-n junction diode.
TJ = 25°C, IS = 12A, VGS = 0V
9.1
14
ns
2.2
3.3
nC
G
S
e
TJ = 25°C, IF = 12A, VDD = 10V
di/dt = 100A/µs
e
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IRL3715Z/S/LPbF
1000
1000
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
100
10
3.0V
60µs PULSE WIDTH
Tj = 25°C
100
1
10
3.0V
60µs PULSE WIDTH
Tj = 175°C
1
0.1
1
10
0.1
VDS, Drain-to-Source Voltage (V)
1
10
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
T J = 25°C
100
T J = 175°C
VDS = 10V
60µs PULSE WIDTH
10
3.0
4.0
5.0
6.0
7.0
8.0
9.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
ID, Drain-to-Source Current (Α)
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
ID = 30A
VGS = 10V
1.5
1.0
0.5
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRL3715Z/S/LPbF
12
10000
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 12A
C, Capacitance (pF)
C oss = C ds + C gd
1000
Ciss
Coss
VDS= 20V
VDS= 10V
10
8
6
4
2
Crss
0
100
0
1
10
4
8
12
16
100
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000
1000.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100.0
100
T J = 175°C
10.0
T J = 25°C
1.0
100µsec
10
VGS = 0V
1
0.1
0.0
0.5
1.0
1.5
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
2.0
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
0
10msec
1
10
100
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL3715Z/S/LPbF
60
2.6
VGS(th) Gate threshold Voltage (V)
LIMITED BY PACKAGE
ID , Drain Current (A)
50
40
30
20
10
2.2
1.8
ID = 250µA
1.4
0
25
50
75
100
125
150
1.0
175
-75 -50 -25
T C , Case Temperature (°C)
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
τJ
SINGLE PULSE
( THERMAL RESPONSE )
0.01
R1
R1
τJ
τ1
τ1
R2
R2
τ2
τ2
R3
R3
τ3
τC
τ
Ri (°C/W) τi (sec)
0.942
0.000145
0.982
0.406
τ3
Ci= τi/Ri
Ci= τi/Ri
0.000805
0.004757
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL3715Z/S/LPbF
200
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
VGS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
15V
ID
3.9A
5.4A
BOTTOM 12A
TOP
160
120
80
40
0
25
50
75
100
125
150
175
Starting T J, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
I AS
LD
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
.3µF
Fig 14a. Switching Time Test Circuit
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
10%
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
VGS
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
6
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IRL3715Z/S/LPbF
D.U.T
Driver Gate Drive
P.W.
+
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
V DD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRL3715Z/S/LPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgd
+⎜I ×
× Vin ×
ig
⎝
⎞
⎞ ⎛
Qgs 2
f⎟ + ⎜ I ×
× Vin × f ⎟
ig
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRL3715Z/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
10.54 (.415)
10.29 (.405)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
LEAD ASSIGNMENTS
IGBTs, CoPACK
1 - GATE
2 - DRAIN
1- GATE
1- GATE
3 - SOURCE 2- COLLECTOR
2- DRAIN
3- SOURCE
3- EMITTER
4 - DRAIN
HEXFET
3
4- DRAIN
14.09 (.555)
13.47 (.530)
3X
1.40 (.055)
3X
1.15 (.045)
4- COLLECTOR
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IRF 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
RE CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
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PART NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
9
IRL3715Z/S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IR F 530S WIT H
L OT CODE 8024
AS S EMB L ED ON WW 02, 2000
IN T HE AS S E MBL Y L INE "L "
INT E R NAT IONAL
R E CT IFIER
L OGO
Note: "P" in as s embly line
pos ition indicates "L ead-F ree"
PAR T NU MB ER
F 530S
AS S E MB L Y
L OT CODE
DAT E CODE
YE AR 0 = 2000
WEE K 02
L INE L
OR
INT E R NAT IONAL
RE CT IF IE R
L OGO
AS S E MB LY
LOT CODE
10
PART NU MB E R
F 530S
DAT E CODE
P = DE S IGNAT E S LE AD-F RE E
PR ODUCT (OPT IONAL )
YE AR 0 = 2000
WE E K 02
A = AS S E MB LY S IT E CODE
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IRL3715Z/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPLE : T HIS IS AN IRL3103L
LOT CODE 1789
AS S EMB LE D ON WW 19, 1997
IN THE AS S EMB LY LINE "C"
Note: "P" in as sembly line
pos ition indicates "Lead-Free"
INT E RNATIONAL
RE CT IF IER
LOGO
AS S EMBLY
LOT CODE
PART NUMB ER
DATE CODE
YE AR 7 = 1997
WE E K 19
LINE C
OR
INT ERNAT IONAL
RECT IFIE R
LOGO
AS S E MB LY
LOT CODE
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PART NUMBE R
DAT E CODE
P = DE S IGNAT E S LEAD-FREE
PRODUCT (OPT IONAL)
YE AR 7 = 1997
WE EK 19
A = AS S EMB LY S IT E CODE
11
IRL3715Z/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.61mH, RG = 25Ω,
IAS = 12A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
3
4
„ This is only applied to TO-220AB pakcage.
… This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
† Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
12
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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