TVS Diode Array SPA SP721 Lead Free/Green Datasheet

TVS Diode Arrays

(SPA ® Diodes)

General Purpose ESD Protection - SP721 Series

SP721 Series 3pF 4kV Diode Array

Pinout

SP721 (PDIP, SOIC)

TOP VIEW

IN 1

IN

IN

2

3

V4

Functional Block Diagram

V+ 8

IN 1

V4

IN 2 IN

3, 5-7

8 V+

7 IN

6 IN

5 IN

Additional Information

Datasheet Resources Samples

RoHS Pb GREEN

Description

The SP721 is an array of SCR/Diode bipolar structures for

ESD and over-voltage protection to sensitive input circuits.

The SP721 has 2 protection SCR/Diode device structures per input. There are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. Overvoltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7) to V+ or V-.

The SCR structures are designed for fast triggering at a threshold of one +V a -V

BE

diode threshold above V+ (Pin 8) or

BE

diode threshold below V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one

V

BE

above V+. A similar clamp to V- is activated if a negative pulse, one V

BE

less than V-, is applied to an IN input.

Standard ESD Human Body Model (HBM) Capability is:

Features

• ESD Interface Capability for HBM Standards

- MIL STD 3015.7 ................................................. 15kV

- IEC 61000-4-2, Direct Discharge,

- Single Input .......................................... 4kV (Level 2)

- Two Inputs in Parallel ............................ 8kV (Level 4)

- IEC 61000-4-2, Air Discharge ...............15kV (Level 4)

• High Peak Current Capability

- IEC 61000-4-5 (8/20µs) ....................................... ±3A

- Single Pulse, 100µs Pulse Width ........................ ±2A

- Single Pulse, 4µs Pulse Width ............................ ±5A

• Designed to Provide Over-Voltage Protection

- Single-Ended Voltage Range to ........................ +30V

- Differential Voltage Range to ............................ ±15V

• Fast Switching .............................................2ns Rise Time

• Low Input Leakages ............................1nA at 25ºC Typical

• Low Input Capacitance .....................................3pF Typical

• An Array of 6 SCR/Diode Pairs

• Operating Temperature Range....................-40ºC to 105ºC

Applications

• Microprocessor/Logic

Input Protection

• Data Bus Protection

• Analog Device Input

Protection

• Voltage Clamp

© 2013 Littelfuse, Inc.

Specifications are subject to change without notice.

Revised: 12/20/13

TVS Diode Arrays (SPA ® Diodes)


Absolute Maximum Ratings

Parameter

Continuous Supply Voltage, (V+) - (V-)

Forward Peak Current, I

IN

(Refer to Figure 5)

to V

CC

, I

IN

to GND

Rating

+35

±2, 100µs

Units

V

A

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Note:

ESD Ratings and Capability (Figure 1, Table 1)

Load Dump and Reverse Battery (Note 2)

Thermal Information

Parameter

Thermal Resistance (Typical, Note 1)

PDIP Package

SOIC Package

Maximum Storage Temperature Range

Maximum Junction Temperature (Plastic

Package)

Maximum Lead Temperature

(Soldering 20-40s)(SOIC Lead Tips Only)

Rating

θ

JA

160

170

-65 to 150

150

260

Units o C/W o C/W o C/W o C o C o C

1. θ

JA

is measured with the component mounted on an evaluation PC board in free air.

Electrical Characteristics

T

A

= -40 o C to 105 o C, V

IN

= 0.5V

CC

, Unless Otherwise Specified

Parameter

Operating Voltage Range,

V

SUPPLY

= [(V+) - (V-)]

Forward Voltage Drop

IN to V-

IN to V+

Input Leakage Current

Quiescent Supply Current

Equivalent SCR ON Threshold

Equivalent SCR ON Resistance

Input Capacitance

Input Switching Speed

I

Symbol

V

V

V

SUPPLY

FWDL

FWDH

I

IN

QUIESCENT

I

IN

Test Conditions

= 1A (Peak Pulse)

V

FWD

Note 3

/I

FWD

; Note 3

Min

-

-

-

-

-

-20

-

-

-

Typ

2 to 30

1.1

1

3

2

5

50

2

2

Max

-

-

-

-

-

-

-

+20

200

Units

V

V

Ω pF ns nA nA

V

V

C

IN t

ON

Notes:

2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- Pins are connected to het same supply voltage source as the device or control line under protection, a current limiti ng resistor should be connected in series between the external supply and the SP721 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger romf the V+ and V- Pins to ground are recommended.

3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance”. These characteristics are given here for thumb-rule nformation to determine peak current and dissipation under EOS conditions.

Typical Application of the SP721

(Application as an Input Clamp for Over-voltage, Greater than 1V

BE

Above V+ or less than -1V

BE

below V-)

+V

CC

+V

CC

INPUT

DRIVERS

OR

SIGNAL

SOURCES

LINEAR OR

DIGITAL IC

INTERFACE

IN 1 - 3 IN 5 - 7 TO +V CC

V+

SP721

V-

SP721 INPUT PROTECTION CIRCUIT (1 OF 6 SHO WN)

FIGURE 4. TYPICAL APPLICATION OF THE SP721 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1V

BE

LESS THAN -1V

BE

BELOW V-

ABOVE V+ OR



Revised: 12/20/13


(SPA ® Diodes)


ESD Capability

ESD capability is dependent on the application and defined test standard.The evaluation results for various test standards and methods based on Figure 1 are shown in

Table 1.

For the “Modified”MIL-STD-3015.7 condition that is defined as an “in-circuit” method of ESD testing, the V+ and V- pins have a return path to ground and the SP721 ESD capability is typically greater than 15kV from 100pF through 1.5kΩ.By strict definition of MIL-STD-3015.7 using “pin-to-pin”device testing, the ESD voltage capability is greater than 6kV.The

MIL-STD-3015.7 results were determined from AT&T ESD

Test Lab measurements.

The HBM capability to the IEC 61000-4-2 standard is greater than 15kV for air discharge (Level 4) and greater than 4kV for direct discharge (Level 2).Dual pin capability (2 adjacent pins in parallel) is well in excess of 8kV (Level 4).

For ESD testing of the SP721 to EIAJ IC121 Machine

Model (MM) standard, the results are typically better than

1kV from 200pF with no series resistance.

Figure 1: Electrostatic Discharge Test

R

1

R

D

H.V.

SUPPLY

V

D

CHARGE

SWITCH

C

D

DISCHARGE

SWITCH

IN

DUT

IEC 1000-4-2: R

1

50 to 100M

MIL-STD-3015.7: R

1

1 to 10M

Table 1: ESD Test Conditions

Standard

MIL STD 3015.7

IEC 61000-4-2

EIAJ IC121

Type/Mode

Modified HBM

R

D

C

D

±V

D

1.5kΩ 100pF 15kV

Standard HBM

HBM, Air Discharge

1.5kΩ 100pF 6kV

330Ω 150pF 15kV

HBM, Direct Discharge 330Ω 150pF 4kV

HBM, Direct Discharge,

Two Parallel Input Pins

Machine Model

330Ω 150pF

0kΩ 200pF

8kV

1kV

Figure 2: Low Current SCR Forward Voltage Drop Curve

100

80

T

A

100

= 25ºC

T

A

= 25ºC

SINGLE PULSE

80

60

60

40

20

40

20

0

600

0

600 800 800

1000 1000

Figure 3: High Current SCR Forward Voltage Drop Curve

2.5

2

2.5

T

A

= 25ºC

2

T

A

= 25ºC

SINGLE PULSE

1.5

1.5

1

0.5

1

0.5

EQUIV. SAT. ON

THRESHOLD ~ 1.1V

1200 1200

0

0

0

0

1

1

V FWD

IFWD

V FWD

IFWD

2

2

3 3



Revised: 12/20/13



Peak Transient Current Capability of the SP721

The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP721’s ability to withstand a wide range of peak current pulses vs time. The circuit used to generate current pulses is shown in Figure 4.

The test circuit of Figure 4 is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP721 ‘IN’ input pin and the (+) current pulse input goes to the SP721 V- pin. The V+ to V- supply of the

SP721 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure

5 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits.

The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of 25ºC and 105ºC and a 15V power supply condition. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of Figure 5.

Note that adjacent input pins of the SP721 may be paralleled to improve current (and ESD) capability. The sustained peak current capability is increased to nearly twice that of a single pin.

Figure 4: Typical SP721 Peak Current Test Circuit with a Variable Pulse Width Input

-

+

V

X

R

1

VARIABLE TIME DURATION

CURRENT PULSE GENERA TOR

CURRENT

SENSE

(-)

VOLTAGE

PROBE

(+)

1 IN

4 V-

V+ 8

2 IN

3 IN

SP721

IN 7

IN 6

IN 5

C1

+

-

R

V

1

X

~ 10 TYPICAL

ADJ. 10V/A TYPICAL

C1 ~ 100 µF

Figure 5: SP721 Typical Single Peak Current Pulse

Capability

Showing the Measured Point of Overstress in Amperes vs pulse width time in milliseconds

7

6

5

4

3

2

1

0

0.001

T

A

= 105°C

0.01

T

A

= 25°C

0.1

CAUTION: SAFE OPERATING CONDITIONS LIMIT

THE MAXIMUM PEAK CURRENT FOR A GIVEN

PULSE WIDTH TO BE NO GREATER THAN 75%

OF THE VALUES SHOWN ON EACH CURVE.

V+ TO V-SUPPLY = 15V

1

PULSE WIDTH TIME (ms)

10 100 1000



Revised: 12/20/13


(SPA ® Diodes)


Soldering Parameters

Reflow Condition Pb – Free assembly

Pre Heat

- Temperature Min (T s(min)

)

- Temperature Max (T s(max)

)

- Time (min to max) (t s

)

Average ramp up rate (Liquidus) Temp

(T

L

) to peak

5°C/second max

T

S(max)

to T

L

- Ramp-up Rate

Reflow

- Temperature (t

L

)

5°C/second max

- Temperature (T

L

) (Liquidus) 217°C

60 – 150 seconds

Peak Temperature (T

P

) 260 +0/-5 °C

Time within 5°C of actual peak

Temperature (t p

)

Ramp-down Rate

150°C

200°C

60 – 180 secs

20 – 40 seconds

5°C/second max

Time 25°C to peak Temperature (T

P

)

Do not exceed

8 minutes Max.

260°C

T

P

T

L

T

S(max)

T

S(min)

25 t

S time to peak temperature t

P

Critical Zone

T L to T P t

L

Time

Package Dimensions — Dual-In-Line Plastic Packages (PDIP)

N

1 2 3 N/2

E1

INDEX

AREA

-B-

-A-

D E

BASE

PLANE

SEATING

PLANE

D1

B1

B

-C-

A2

A

L e

D1

A

1 e

C

0.010 (0.25) M C A B S

CL e

A

C e

B

Notes: NOTES:

1. Controlling Dimensions: INCH. In case of conflict between

English and Metric dimensions, the inch dimensions control.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No.

95.

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru-

6. E and e sions. Mold flash or protrusions shall not exceed 0.010 inch

(0.25mm).

7. e

B

and e or greater.

e

A pendicular to datum -C.

are measured at the lead tips with the leads uncon7. e

B

and e

C strained. e

C

must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.

Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,

E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch

(0.76 - 1.14mm).

Package

Pins

JEDEC

C

D

D1

E

E1 e e

A e

B

L

N

A

A1

A2

B

B1

PDIP

8 Lead Dual-in-Line

MS-001

Millimeters

Min

-

Max

5.33

0.39

2.93

0.356

1.15

0.204

-

4.95

0.558

1.77

0.355

9.01

0.13

7.62

6.10

2.54 BSC

10.16

-

8.25

7.11

-

2.93

7.62 BSC

10.92

3.81

8

Inches

Min

-

Max

0.210

0.015

0.115

0.014

0.045

0.008

-

0.195

0.022

0.070

0.014

0.355

0.005

0.300

0.240

0.400

0.325

0.280

0.100 BSC

-

-

0.300 BSC

0.430

0.115

0.150

8

Notes

4

9

6

7

6

5

5

5

-

4

4

-

-

8, 10

-



Revised: 12/20/13



Package Dimensions — Small Outline Plastic Packages (SOIC)

N

INDEX

AREA

H 0.25(0.010) M B M

E

-B-

1 2 3

L

-A-

D

SEATING PLANE

A h x 45o

-Ce

B

0.25(0.010) M C A M B S

A1

μ

0.10(0.004)

C

Notes:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication

Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Publication Number 95.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

Package

Pins

JEDEC

N

µ h

L

E e

H

A

A1

B

C

D

Millimeters

Min Max

1.35

1.75

0.10

0.33

0.19

0.25

0.51

0.25

4.80

3.80

1.27 BSC

5.00

4.00

5.80

0.25

0.40

6.20

0.50

1.27

8

0º 8º

SOIC

8

MS-012

Min

Inches

Max

0.0532

0.0688

0.0040

0.0098

0.013

0.020

0.0075

0.0098

0.1890

0.1497

0.1968

0.1574

0.050 BSC

0.2284

0.2440

0.0099

0.0196

0.016

0.050

8

0º 8º

Notes

3

4

-

-

-

9

-

6

7

-

5

-

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension:MILLIMETER. Converted inch dimensions

Part Numbering System

SP 721 ** **

TVS Diode Arrays

(SPA ® Diodes)

Series

G = Green

P = Lead Free

TG= Tape and Reel

Package

AB = 8 Ld SOIC

AP = 8 Ld PDIP

Product Characteristics

Lead Plating

Lead Material

Lead Coplanarity

Substitute Material

Body Material

Flammability

Matte Tin

Copper Alloy

0.004 inches (0.102mm)

Silicon

Molded Epoxy

UL 94 V-0

Ordering Information

Part Number Temp. Range (ºC) Package

Environmental

Informaton

Lead-free

Marking

SP721APP -40 to 105 8 Ld PDIP SP721AP(P) 1

SP721ABG -40 to 105 8 Ld SOIC Green SP721A(B)G 2

SP721ABTG -40 to 105

8 Ld SOIC Tape and Reel

Green SP721A(B)G

Notes:

1. SP721AP(P) means device marking either SP721AP or SP721APP.

2. SP721A(B)G means device marking either SP721AG or SP721ABG which are good for types SP721ABG and SP721ABTG.

2

Min. Order

2000

1960

2500



Revised: 12/20/13

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