MCP37231/21-200 MCP37D31/21-200 Features

MCP37231/21-200 MCP37D31/21-200 Features
MCP37231/21-200
MCP37D31/21-200
200 Msps, 16-/14-Bit Low-Power ADC with 8-Channel MUX
Features
• Sample Rates:
- 200 Msps for single-channel mode
- 200 Msps/number of channels used
• SNR with fIN = 15 MHz and -1 dBFS:
- 74.7 dBFS (typical) at 200 Msps
• SFDR with fIN = 15 MHz and -1 dBFS:
- 90 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 490 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 436 mW at 200 Msps, Output Clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 390 mW at 200 Msps
• Power-Saving Modes:
- 80 mW during Standby
- 33 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 VP-P
• Input Channel Bandwidth: 500 MHz
• Channel-to-Channel Crosstalk in Multi-Channel
Mode (Input = 15 MHz, -1 dBFS): >95 dB
• Output Data Format:
- Parallel CMOS, DDR LVDS
- Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
• Serial Peripheral Interface (SPI)
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Fractional Delay Recovery (FDR) for timedelay corrections in multi-channel operations
(dual-/octal-channel modes)
- Phase, Offset and Gain adjust of individual
channels
- Digital Down-Conversion (DDC) with I/Q or
fS/8 output (MCP37D31/21-200)
- Continuous wave beamforming for octalchannel mode (MCP37D31/21-200)
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• Package Options:
- VTLA-124 (9 mm x 9 mm x 0.9 mm)
- TFBGA-121 (8 mm x 8 mm x 1.08 mm)
• No external reference decoupling capacitor
required for TFBGA Package
• Industrial Temperature Range: -40°C to +85°C
Typical Applications
•
•
•
•
•
•
Communication Instruments
Cellular Base Stations
Radar
Ultrasound and Sonar Imaging
Scanners and Low-Power Portable Instruments
Industrial and Consumer Data Acquisition System
MCP372XX/MCP37DXX Family Comparison (1, 2):
Digital
CW
Digital
Decimation(3) Down-Conversion(4) Beamforming(5)
Noise-Shaping
Requantizer(3)
Part Number
Sample Rate
Resolution
MCP37231-200
200 Msps
16
Yes
No
No
MCP37221-200
200 Msps
14
Yes
No
No
No
MCP37211-200
200 Msps
12
Yes
No
No
Yes
MCP37D31-200
200 Msps
16
Yes
Yes
Yes
No
MCP37D21-200
200 Msps
14
Yes
Yes
Yes
No
MCP37D11-200
200 Msps
12
Yes
Yes
Yes
Yes
Note 1:
2:
3:
4:
5:
No
For TFBGA package, contact Microchip Technology Inc. for availability.
Devices in the same package type are pin-to-pin compatible.
Available in single- and dual-channel mode.
Available in single- and dual-channel mode, and octal-channel mode when CW beamforming is enabled.
Available in octal-channel mode.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 1
MCP37231/21-200 AND MCP37D31/21-200
Functional Block Diagram
AVDD12
CLK+
AVDD18
DVDD12
Duty Cycle
Correction
Clock
Selection
CLK-
GND
DVDD18
DLL
PLL
AIN0+
AIN0-
AIN7+
AIN7-
Input Multiplexer
Output Clock Control
DCLK+
DCLK-
Digital Signal Post-Processing:
Pipelined
ADC
- FDR, Decimation
- Phase/Offset/Gain Adj.
- DDC, CW Beamforming
(MCP37D31/21-200)
VREF+
WCK
VREF-
OVR
Output Control:
VCM
- CMOS, DDR LVDS
- Serialized LVDS
Reference
Generator
SENSE
Q[15:0]
Internal Registers
VBG
REF1+
DS20005322C-page 2
REF1-
REF0+
REF0-
SDIO
SCLK
CS
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Description
The MCP37231/21-200 is Microchip's baseline 16-/14bit 200 Msps pipelined ADC family, featuring built-in
high-order digital decimation filters, gain and offset
adjustment per channel and fractional delay recovery.
The MCP37D31/21-200 device family features digital
down-conversion and CW beamforming capability, in
addition to the features offered by the MCP37231/21-200.
All devices feature harmonic distortion correction and
DAC noise cancellation that enable high-performance
specifications with SNR of 74.7 dBFS (typical), and
SFDR of 90 dBc (typical).
These A/D converters exhibit industry-leading lowpower performance with only 490 mW operation while
using the LVDS interface at 200 Msps. This superior
low-power operation coupled with high dynamic
performance makes these devices ideal for various
high-performance, high-speed data acquisition
systems, including communications equipment, radar
and portable instrumentation.
The output decimation filter option improves SNR
performance up to 93.5 dBFS with the 512x decimation
setting. The digital down-conversion option, in
conjunction with the decimation and quadrature output
options, offers great flexibility in digital communication
system design, including cellular base-stations and
narrow-band communications. Gain, phase and DC
offset can be adjusted independently for each input
channel, allowing for simplified implementation of CW
beamforming and ultrasound Doppler imaging
applications.
These devices can have up to eight differential input
channels through an input MUX. The sampling rate is up
to 200 Msps when a single channel is used, or 25 Msps
per channel when all eight input channels are used.
These devices also include various features designed
to maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment and
programmable digital pattern generation. The device’s
operational modes and feature sets are configured by
setting up the user-programmable registers.
The device is available in Pb-free VTLA-124 and
TFBGA-121 packages. The device operates over the
commercial temperature range of -40°C to +85°C.
Package Types
Bottom View
Dimension: 9 mm x 9 mm x 0.9 mm
(a) VTLA-124 Package.
Bottom View
In dual or octal-channel mode, the Fractional Delay
Recovery (FDR) feature digitally corrects the difference
in sampling instance between different channels, so
that all inputs appear to have been sampled at the
same time.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after 28
clock cycles of data latency. Latency will increase if any
of the digital signal post-processing (DSPP) options are
enabled.
The differential full-scale analog input range is
programmable up to 2.975 VP-P. The ADC output data
can be coded in two's complement or offset binary
representation, with or without the data randomizer
option. The output data is available as full-rate CMOS
or Double-Data-Rate (DDR) LVDS. Additionally, a
serialized LVDS option is also available for the 16-bit
octal-channel mode.
 2014-2015 Microchip Technology Inc.
Dimension: 8 mm x 8 mm x 1.08 mm
Ball Pitch: 0.65 mm
Ball Diameter: 0.4 mm
(b) TFBGA-121 Package.
(Contact Microchip Technology Inc. for availability)
DS20005322C-page 3
MCP37231/21-200 AND MCP37D31/21-200
NOTES:
DS20005322C-page 4
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
1.0
PACKAGE PIN CONFIGURATIONS
AND FUNCTION DESCRIPTIONS
Top View
(Not to Scale)
AVDD18 GND AVDD12 REF0- REF0+ AVDD12 VBG
NC
A68
A66
A67
A1
B56
A65
B55
A64
B54
A63
B52
B53
B1
A60
A61
B50
B51
A58
A59
B48
B49
AVDD18 REF0- REF0+
Note 2
A2
A62
REF1- REF1+
B47
AVDD12 V
CM
A57
A56
B46
A54
A55
B45
NC
SCLK SDIO
B43
CS
DVDD18
A49
A48
B2 AIN6-
B40
B3 AIN2-
DVDD12 B39
AIN2+ A4
VTLA-124
(9 mm x 9 mm x 0.9 mm)
AIN4+ A5
B4 AIN4-
WCK/OVR+
(OVR)
B38
AIN0+ A6
B5 AIN0-
Q15/Q7+ B37
VCMIN A7
B6
AIN1-
DVDD18 B36
AIN1+
EP
(GND)
A8
B7 AIN7+
AIN7- A9
AIN3- A10
Q12/Q6- B35
A47
A46
A45 WCK/OVR(WCK)
A44 Q14/Q7A43 Q13/Q6+
A42 Q11/Q5+
Note 3
B8 AIN3+
Q10/Q5- B34
B9 AIN5+
Q9/Q4+ B33
B10
Q7/Q3+
AIN5- A11
A41 DVDD18
A40 Q8/Q4-
B32
A12
A39 Q6/Q3B11
A13
DVDD18 B31
AVDD12
A38 Q5/Q2+
B12
Q4/Q2- B30
B13
B29
A37
A14
A15
AVDD12
NC
B14
A16
A17
Note 2
B41
AVDD18
AIN6+ A3
A51
A50
B42
B44
SENSE REF1- REF1+
A52
A53
A18
Note 2
B15
A19
CLK-
B16
A20
B17
A21
Note 1
ADR0 SYNC GND
B18
A22
B19
A23
CLK+ AVDD18 SLAVE
B20
A24
A36
RESET DCLK+ DM2/DM- DVDD18 Q1/Q0+ Q2/Q1- DVDD18
B21
A25
B22
A26
B23
A27
B24
A28
B25
A29
B26
A30
A31
DVDD12 CAL DCLK- DM1/DM+ Q0/Q0- DVDD12 Q3/Q1+
NC
B28
B27
A32
A33
A35
A34
Note 2
Note 1: Tie to GND or DVDD18. ADR1 is internally bonded to GND.
2: NC – Not connected pins. These pins can float or be tied to ground.
3: Exposed pad (EP – back pad of the package) is the common ground (GND) for analog and digital
supplies. Connect this pad to a clean ground reference on the PCB.
FIGURE 1-1:
VTLA-124 Package. See Table 1-1 for the pin descriptions and Table 1-3 for active
and inactive ADC output pins for various ADC resolution modes.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 5
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-1:
PIN FUNCTION TABLE FOR VTLA-124
Pin No.
Name
I/O Type
Description
A2, A22, A65, B1,
B52
AVDD18
Supply
A12, A56, A60,
A63, B10, B11, B12,
B13, B15, B16,
B45, B49, B53
AVDD12
Supply voltage input (1.2V) for analog section
A25, A30, B39
DVDD12
Supply voltage input (1.2V) for digital section
A41, B24, B27,
B31, B36, B43
DVDD18
Supply voltage input (1.8V) for digital section and all digital I/O
EP
GND
Power Supply Pins
Supply voltage input (1.8V) for analog section
Exposed pad: Common ground pin for digital and analog sections
ADC Analog Input Pins
A3
AIN6+
B2
AIN6-
Analog
Input
Channel 6 differential analog input (+)
A4
AIN2+
Channel 2 differential analog input (+)
B3
AIN2-
Channel 2 differential analog input (-)
A5
AIN4+
Channel 4 differential analog input (+)
B4
AIN4-
Channel 4 differential analog input (-)
A6
AIN0+
Channel 0 differential analog input (+)
B5
AIN0-
Channel 0 differential analog input (-)
B6
AIN1+
Channel 1 differential analog input (+)
A8
AIN1-
Channel 1 differential analog input (-)
B7
AIN7+
Channel 7 differential analog input (+)
A9
AIN7-
Channel 7 differential analog input (-)
Channel 6 differential analog input (-)
B8
AIN3+
Channel 3 differential analog input (+)
A10
AIN3-
Channel 3 differential analog input (-)
B9
AIN5+
Channel 5 differential analog input (+)
A11
AIN5-
Channel 5 differential analog input (-)
A21
CLK+
Differential clock input (+)
B17
CLK-
Differential clock input (-)
Reference Pins(1)
A57, B46
REF1+
Analog
Output
Differential reference 1 (+) voltage
A58, B47
REF1-
A61, B50
REF0+
Differential reference 0 (+) voltage
Differential reference 1 (-) voltage
A62, B51
REF0-
Differential reference 0 (-) voltage
SENSE, Bandgap and Common-Mode Voltage Pins
B48
SENSE
Analog
Input
Analog input full-scale range selection. See Table 4-2 for SENSE
voltage settings.
A59
VBG
Analog
Output
Internal bandgap output voltage
Connect a decoupling capacitor (2.2 µF)
A7
VCMIN
Analog
Input
Common-mode voltage input for auto-calibration
Connect VCM voltage(2)
A55
VCM
DS20005322C-page 6
Common-mode output voltage (900 mV) for analog input signal
Connect a decoupling capacitor (0.1 µF)(3)
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-1:
PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)
Pin No.
Name
I/O Type
Description
Digital I/O Pins
Digital Input SPI address selection pin (A0 bit). Tie to GND or DVDD18.(4)
B18
ADR0
A23
SLAVE
B19
SYNC
Digital Input/ Not used. Leave this pin floating(11)
Output
B21
RESET
Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(5)
A26
CAL
B22
DCLK+
LVDS: Differential digital clock output (+)
CMOS: Digital clock output(7)
A27
DCLK-
LVDS: Differential digital clock output (-)
CMOS: Unused (leave floating)
Not used. Tie to GND(11).
Digital
Output
Calibration status flag digital output:
High: Calibration is complete
Low: Calibration is not complete(6)
ADC Output Pins(8)
DM2/DM-
A28
DM1/DM+
A29
Q0/Q0-
Digital data output: CMOS = Q0
DDR LVDS = Q0- (Even bit first), Q8- (MSb byte first)
Serialized LVDS = Q- for the last selected channel (n) = 8
B25
Q1/Q0+
Digital data output: CMOS = Q1
DDR LVDS = Q0+ (Even bit first), Q8+ (MSb byte first)
Serialized LVDS = Q+ for the last selected channel (n) = 8
B26
Q2/Q1-
Digital data output: CMOS = Q2
DDR LVDS = Q1- (Even bit first), Q9- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 7
A31
Q3/Q1+
Digital data output: CMOS = Q3
DDR LVDS = Q1+ (Even bit first), Q9+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 7
B30
Q4/Q2-
Digital data output: CMOS = Q4
DDR LVDS = Q2- (Even bit first), Q10- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 6
A38
Q5/Q2+
Digital data output: CMOS = Q5
DDR LVDS = Q2+ (Even bit first), Q10+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 6
A39
Q6/Q3-
Digital data output: CMOS = Q6
DDR LVDS = Q3- (Even bit first), Q11- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 5
B32
Q7/Q3+
Digital data output: CMOS = Q7
DDR LVDS = Q3+ (Even bit first), Q11+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 5
A40
Q8/Q4-
Digital data output: CMOS = Q8
DDR LVDS = Q4- (Even bit first), Q12- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 4
B33
Q9/Q4+
Digital data output: CMOS = Q9
DDR LVDS = Q4+ (Even bit first), Q12+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 4
B34
Q10/Q5-
Digital data output: CMOS = Q10
DDR LVDS = Q5- (Even bit first), Q13- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 3
 2014-2015 Microchip Technology Inc.
Digital
Output
18-bit mode: Digital data output (last two LSb bits)(9)
Other modes: Not used
B23
DS20005322C-page 7
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-1:
PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)
Pin No.
Name
I/O Type
Description
A42
Q11/Q5+
Digital
Output
B35
Q12/Q6-
Digital data output: CMOS = Q12
DDR LVDS = Q6- (Even bit first), Q14- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 2
A43
Q13/Q6+
Digital data output: CMOS = Q13
DDR LVDS = Q6+ (Even bit first), Q14+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 2
A44
Q14/Q7-
Digital data output: CMOS = Q14
DDR LVDS = Q7- (Even bit first), Q15- (MSb byte first)
Serialized LVDS = Q- for the first selected channel (n) = 1
B37
Q15/Q7+
Digital data output: CMOS = Q15
DDR LVDS = Q7+ (Even bit first), Q15+ (MSb byte first)
Serialized LVDS = Q+ for the first selected channel (n) = 1
B38
WCK/OVR+
(OVR)
A45
WCK/OVR(WCK)
Digital data output: CMOS = Q11
DDR LVDS = Q5+ (Even bit first), Q13+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 3
WCK: Word clock sync digital output
OVR: Input overrange indication digital output(11)
SPI Interface Pins
A53
SDIO
A54
SCLK
B44
CS
Digital Input/ SPI data input/output
Output
Digital
Input
SPI serial clock input
SPI Chip Select input
Not Connected Pins
A1, A13 - A20, A32
- A37, A46 - A52,
A66 - A68, B14,
B28, B29, B40,
B41, B42, B55, B56
NC
These pins can be tied to ground or left floating.
Pins that need to be grounded
A24, A64, B20, B54
DS20005322C-page 8
GND
These pins are not supply pins, but need to be tied to ground.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Notes:
1.
These pins are for the internal reference voltage outputs. They should not be driven. External decoupling circuits
are required. See Section 4.5.3, "Decoupling Circuits for Internal Voltage Reference and Bandgap Output"
for details.
2. VCMIN is used for Auto-Calibration only. VCMIN+ and VCMIN- should be tied together always. There should be no
voltage difference between the two pins. Typically both VCMIN+ and VCMIN- are tied to the VCM output pin
together, but they can be tied to another common-mode voltage if external VCM is used. This pin has High Z input
in Shutdown, Standby and Reset modes.
3. When the VCM output is used for the common-mode voltage of analog inputs (i.e. by connecting to the centertap of a balun), the VCM pin should be decoupled with a 0.1 µF capacitor, and should be directly tied to the VCMIN+
and VCMIN- pins.
4. ADR1 (for A1 bit) is internally bonded to GND (‘0’). If ADR0 is dynamically controlled, ADR0 must be held
constant while CS is "Low”
5. The device is in Reset mode while this pin stays "Low". On the rising edge of RESET, the device exits Reset
mode, initializes all internal user registers to default values, and begins power-up calibration.
6. CAL pin stays "Low" at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has "High" output. It stays "High" until the internal calibration is restarted by hardware or a
soft reset command. In Reset mode, this pin is "Low". In Standby and Shutdown modes, this pin will maintain the
prior condition.
7. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing, PLL and/or DLL. See
also Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.
8. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The
even data bits (Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14) appear when DCLK+ is "High". The odd data bits (Q1, Q3,
Q5, Q7, Q9, Q11, Q13, Q15) appear when DCLK+ is "Low”. See Addresses 0x65 (Register 5-23) and 0x68
(Register 5-26) for output polarity control. See Figures 2-2 to 2-6 for LVDS output timing diagrams.
9. Available for the MCP37231-200 and MCP37D31-200 devices only.
Leave these pins floating (No Connect) if not used.
10. 18-bit mode: DM1/DM+ and DM2/DM- are the last LSb bits. DM2/DM- is the LSb. In LVDS output, DM1/DM+ and
DM2/DM- are the LSb pair. DM1/DM+ appears at the falling edge and DM2/DM- is at the rising edge of the DCLK+.
Other than 18-bit mode: DM1/DM+ and DM2/DM- are High Z in LVDS mode.
11. CMOS output mode: WCK/OVR- is WCK and WCK/OVR+ is OVR.
DDR LVDS output mode: The rising edge of DCLK+ is WCK and the falling edge is OVR.
OVR: OVR will be held “High”’ when analog input overrange is detected. Digital signal post-processing will cause
OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: WCK is normally “Low”. WCK is “High” while data from the first channel is sent out. In single-channel
mode, WCK stays “High” except when in I/Q output mode. In serialized LVDS (octal) output mode, the WCK output is asserted “High” on the MSb bit. See Section 4.12.5 “Word Clock (WCK)” for further WCK description.
12. This pin function is not released yet.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 9
MCP37231/21-200 AND MCP37D31/21-200
Top View
(Not to Scale)
1
2
A
SDIO
VCM
B
SCLK
CS
C
WCK/ WCK/
OVR- OVR+
(WCK) (OVR)
3
4
REF1+ REF1-
5
VBG
6
7
REF0+ REF0-
8
9
10
11
GND
GND
AIN4-
AIN2+
GND
GND
SENSE AVDD12 AVDD12 AVDD18 AVDD18 AIN4+
AIN2-
GND
GND
AVDD12 AVDD12 AVDD12 GND
GND
AIN6-
AIN0+
D
Q14/Q7- Q15/Q7+ GND
GND
AVDD12 AVDD12 AVDD12 GND
GND
AIN6+
AIN0-
E
Q12/Q6- Q13/Q6+ GND
GND
AVDD12 AVDD12 AVDD12 GND
GND
AIN5+
AIN1+
F
Q10/Q5- Q11/Q5+ DVDD18 DVDD18 AVDD12 AVDD12 AVDD12
GND
AIN5-
AIN1-
G
Q8/Q4- Q9/Q4+ DVDD18 DVDD18
GND
GND
GND
AIN7-
AIN3+
H
Q6/Q3- Q7/Q3+ DVDD12 DVDD12
GND
GND
GND
GND
GND
AIN7+
AIN3-
J
Q4/Q2- Q5/Q2+ DVDD12 DVDD12
GND
GND
GND
GND
GND
K
Q2/Q1- Q3/Q1+ DM1/DM+ DCLK-
CAL
GND
SLAVE ADR0
ADR1
GND
L
Q0/Q0- Q1/Q0+
GND
CLK-
GND AVDD18
DM2/DM-
DCLK+ RESET SYNC
All others:
GND
AVDD12 AVDD12
CLK+
VCMIN+ VCMINGND
Analog
Digital
Supply Voltage
Notes:
•
•
•
•
Die dimension: 8 mm x 8 mm x 1.08 mm.
Ball dimension: (a) Ball Pitch = 0.65 mm, (b) Ball Diameter = 0.4 mm.
Flip-chip solder ball composition: Sn with Ag 1.8%.
Solder sphere composition: SAC-405 (Sn/Au 4%/Cu 0.5%).
FIGURE 1-2:
TFBGA-121 Package. See Table 1-2 for the pin descriptions and Table 1-3 for active
and inactive ADC output pins for various ADC resolution modes.
DS20005322C-page 10
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-2:
PIN FUNCTION TABLE FOR TFBGA-121
Ball No.
Name
A1
SDIO
A2
VCM
A3
A4
A5
REF1+
REF1VBG
A6
A7
A8
A9
REF0+
REF0GND
A10
AIN4-
Analog Input Channel 4 differential analog input (-)
A11
B1
AIN2+
SCLK
Channel 2 differential analog input (+)
Digital Input SPI serial clock input
B2
B3
B4
B5
CS
GND
B6
B7
B8
B9
SENSE
AVDD12
AIN4+
B11
C1
AIN2WCK/OVR(WCK)
WCK/OVR+
(OVR)
GND
C3
C4
C5
C6
C7
C8
C9
Supply
Analog
Input
Supply
Analog Input
C11
D1
AIN0+
Q14/Q7-
D2
Q15/Q7+
D3
D4
GND
Analog input range selection. See Table 4-2 for SENSE voltage settings.
Supply voltage input (1.2V) for analog section
Channel 4 differential analog input (+)
Digital
Output
Channel 2 differential analog input (-)
WCK: Word clock sync digital output
OVR: Input overrange indication digital output(2)
Supply
Common ground for analog and digital sections
Supply voltage input (1.2V) for analog section
GND
AIN6-
SPI Chip Select input
Common ground for analog and digital sections
Supply voltage input (1.8V) for analog section
AVDD12
C10
Description
Digital Input/ SPI data input/output
Output
Analog
Common-mode output voltage (900 mV) for analog input signal
Output
Connect a decoupling capacitor (0.1 µF)(1)
Differential reference voltage 1 (+/-). Decoupling capacitors are embedded in
the TFBGA package. Leave these pins floating.
Internal bandgap output voltage
A decoupling capacitor (2.2 μF) is embedded in the TFBGA package. Leave
this pin floating.
Differential reference 0 (+/-) voltage. Decoupling capacitors are embedded in
the TFBGA package. Leave these pins floating.
Supply
Common ground for analog and digital sections
AVDD18
B10
C2
I/O Type
Common ground pin for analog and digital sections
Analog Input
Digital
Output
Supply
 2014-2015 Microchip Technology Inc.
Channel 6 differential analog input (-)
Channel 0 differential analog input (+)
Digital data output(3)
CMOS = Q14
DDR LVDS = Q7- (Even bit first), Q15- (MSb byte first)
Serialized LVDS = Q- for the first selected channel (n = 1)
Digital data output(3)
CMOS = Q15
DDR LVDS = Q7+ (Even bit first), Q15+ (MSb byte first)
Serialized LVDS = Q+ for the first selected channel (n = 1)
Common ground for analog and digital sections
DS20005322C-page 11
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-2:
PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No.
Name
I/O Type
D5
D6
D7
D8
D9
AVDD12
Supply
D10
AIN6+
D11
E1
AIN0Q12/Q6-
E2
Q13/Q6+
E3
E4
E5
E6
E7
E8
E9
GND
GND
Analog Input
Digital
Output
Supply
E11
F1
AIN1+
Q10/Q5-
F2
Q11/Q5+
F3
F4
F5
F6
F7
F8
F9
DVDD18
F10
AIN5-
F11
G1
AIN1Q8/Q4-
G2
Q9/Q4+
Channel 0 differential analog input (-)
Digital data output(3)
CMOS = Q12
DDR LVDS = Q6- (Even bit first), Q14- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 2
Digital data output(3)
CMOS = Q13
DDR LVDS = Q6+ (Even bit first), Q14+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 2
Common ground for analog and digital sections
Common ground for analog and digital sections
Analog Input
Digital
Output
Supply
AVDD12
GND
DS20005322C-page 12
Channel 6 differential analog input (+)
Supply voltage input (1.2V) for analog section
GND
AIN5+
Supply voltage input (1.2V) for analog section
Common ground for analog and digital sections
AVDD12
E10
Description
Channel 5 differential analog input (+)
Channel 1 differential analog input (+)
Digital data output(3)
CMOS = Q10
DDR LVDS = Q5- (Even bit first), Q13- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 3
Digital data output(3)
CMOS = Q11
DDR LVDS = Q5+ (Even bit first), Q13+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 3
Supply voltage input (1.8V) for digital section.
All digital input pins are driven by the same DVDD18 potential.
Supply voltage input (1.2V) for analog section
Common ground for analog and digital sections
Analog Input
Digital
Output
Channel 5 differential analog input (-)
Channel 1 differential analog input (-)
Digital data output(3)
CMOS = Q8
DDR LVDS = Q4- (Even bit first), Q12- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 4
Digital data output(3)
CMOS = Q9
DDR LVDS = Q4+ (Even bit first), Q12+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 4
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-2:
PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No.
Name
I/O Type
G3
G4
G5
G6
G7
G8
G9
DVDD18
Supply
Supply voltage input (1.8V) for digital section
All digital input pins are driven by the same DVDD18 potential
Common ground for analog and digital sections
Supply
Supply voltage input (1.2V) for analog section
G10
AIN7-
G11
H1
AIN3+
Q6/Q3-
H2
Q7/Q3+
H3
H4
H5
H6
H7
H8
H9
DVDD12
H10
AIN7+
H11
J1
AIN3Q4/Q2-
J2
Q5/Q2+
J3
J4
J5
J6
J7
J8
J9
DVDD12
J10
VCMIN+
J11
VCMIN-
GND
AVDD12
GND
Analog Input
Digital
Output
Supply
GND
Description
Common ground for analog and digital sections
Channel 7 differential analog input (-)
Channel 3 differential analog input (+)
Digital data output(3)
CMOS = Q6
DDR LVDS = Q3- (Even bit first), Q11- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 5
Digital data output(3)
CMOS = Q7
DDR LVDS = Q3+ (Even bit first), Q11+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 5
Supply voltage input (1.2V) for digital section
Common ground for analog and digital sections
Analog Input
Digital
Output
Supply
GND
Channel 7 differential analog input (+)
Channel 3 differential analog input (-)
Digital data output(3)
CMOS = Q4
DDR LVDS = Q2- (Even bit first), Q10- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 6
Digital data output(3)
CMOS = Q5
DDR LVDS = Q2+ (Even bit first), Q10+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 6
DC supply voltage input pin for digital section (1.2V)
Common ground for analog and digital sections
Analog Input Common-mode voltage input for auto-calibration(4)
These two pins should be tied together and connected to VCM voltage.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 13
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-2:
PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No.
Name
K1
Q2/Q1-
K2
Q3/Q1+
K3
DM1/DM+
K4
DCLK-
K5
CAL
K6
K7
GND
SLAVE
K8
K9
K10
K11
L1
ADR0
ADR1
GND
Q0/Q0-
L2
Q1/Q0+
L3
DM2/DM-
L4
DCLK+
L5
RESET
L6
SYNC
L7
L8
L9
L10
GND
CLK+
CLKGND
L11
AVDD18
DS20005322C-page 14
I/O Type
Description
Digital data output(3)
CMOS = Q2
DDR LVDS = Q1- (Even bit first), Q9- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 7
Digital data output(3)
CMOS = Q3
DDR LVDS = Q1+ (Even bit first), Q9+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 7
18-bit mode: Digital data output. DM1 and DM2 are the last two LSb bits(5)
Other modes: Not used
LVDS: Differential digital clock output (-)
CMOS: Not used (leave floating)
Digital
Calibration status flag digital output(6)
High: Calibration is complete
Output
Low: Calibration is not complete
Supply
Common ground pin for analog and digital sections
Digital Input Not used. Tie this pin to GND(10)
SPI address selection pin (A0 bit). Tie to GND or DVDD18(7)
SPI address selection pin (A1 bit). Tie to GND or DVDD18(7)
Supply
Common ground for analog and digital sections
Digital
Output
Digital
Output
Digital data output(3)
CMOS = Q0
DDR LVDS = Q0- (Even bit first), Q8- (MSb byte first)
Serialized LVDS = Q- for the last selected channel (n=8)
Digital data output(8)
CMOS = Q1
DDR LVDS = Q0+ (Even bit first), Q8+ (MSb byte first)
Serialized LVDS = Q+ for the last selected channel (n=8)
18-bit mode: Digital data output. DM1 and DM2 are the last two LSb bits(5)
Other modes: Not used
LVDS: Differential digital clock output (+)
CMOS: Digital clock output(8)
Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(9)
Digital Input/
Not used. Leave this pin floating(10)
Output
Supply
Common ground for analog and digital sections
Analog Input Differential clock input (+)
Differential clock input (-)
Supply
Common ground for analog and digital sections
Analog Input Supply voltage input (1.8V) for analog section
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Notes:
1.
When the VCM output is used for the common-mode voltage of analog inputs (i.e. by connecting to the center-tap of a
balun), the VCM pin should be decoupled with a 0.1 µF capacitor, and should be directly tied to the VCMIN+ and VCMIN- pins.
2. CMOS output mode: WCK/OVR- is WCK and WCK/OVR+ is OVR.
DDR LVDS output mode: The rising edge of DCLK+ is WCK and the falling edge is OVR.
OVR: OVR will be held “High”’ when analog input overrange is detected. Digital signal post-processing will cause
OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: WCK is normally “Low”. WCK is “High” while data from the first channel is sent out. In single-channel
mode, WCK stays “High” except when in I/Q output mode. In serialized LVDS (octal) output mode, the WCK output is asserted “High” on the MSb bit. See Section 4.12.5 “Word Clock (WCK)” for further WCK description.
3. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The
even data bits (Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14) appear when DCLK+ is “High”. The odd data bits (Q1, Q3,
Q5, Q7, Q9, Q11, Q13, Q15) appear when DCLK+ is "Low". See Addresses 0x65 (Register 5-23) and 0x68
(Register 5-26) for output polarity control. See Figures 2-2 to 2-6 for LVDS output timing diagrams.
4. VCMIN is used for Auto-Calibration only. VCMIN+ and VCMIN- should be tied together always. There should be no
voltage difference between the two pins. Typically both VCMIN+ and VCMIN- are tied to the VCM output pin
together, but they can be tied to another common-mode voltage if external VCM is used. This pin has High Z input
in Shutdown, Standby and Reset modes.
5. Available for the MCP37231-200 and MCP37D31-200 devices only.
Leave these pins floating (No Connect) if not used.
18-bit mode: DM1/DM+ and DM2/DM- are the last LSb bits. DM2/DM- is the LSb. In LVDS output, DM1/DM+ and
DM2/DM- are the LSb pair. DM1/DM+ appears at the falling edge and DM2/DM- is at the rising edge of the DCLK+.
Other than 18-bit mode: DM1/DM+ and DM2/DM- are High Z in LVDS mode.
6. CAL pin stays "Low" at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has "High" output. It stays "High" until the internal calibration is restarted by hardware or a
soft reset command. In Reset mode, this pin is "Low". In Standby and Shutdown modes, this pin will maintain the
prior condition.
7. If the SPI address is dynamically controlled, the Address pin must be held constant while CS is "Low”.
8. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing, PLL and/or DLL. See
also Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.
9. The device is in Reset mode while this pin stays "Low". On the rising edge of RESET, the device exits Reset
mode, initializes all internal user registers to default values, and begins power-up calibration.
10. This pin function is not released yet.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 15
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-3:
ADC
Resolution
DATA OUTPUT PINS FOR EACH RESOLUTION OPTION
Output Pin Name
Q15/ Q14/
Q7+ Q7-
18-bit mode
16-bit mode
(1)
14-bit mode
12-bit mode
10-bit mode
Note 1:
2:
Q13/
Q6+
Q12/ Q11/ Q10/ Q9/
Q6- Q5+ Q5- Q4+
Q8/
Q4-
Q7/
Q3+
Q6/
Q3-
Q5/
Q2+
Q4/
Q2-
Q3/
Q1+
Q2/
Q1-
Q1/
Q0+
Q0/
Q0-
DM1/
DM+
DM2
/DM-
Q15 pin is MSb (bit 17), and DM2 is LSb (bit 0)
Not used (2)
Q15 pin is MSb, and Q0 is LSb
Not used(2)
Q15 pin is MSb, and Q2 is LSb
Q15 pin is MSb, and Q4 is LSb
Q15 pin is MSb, and Q6 is LSb
Not used(2)
Not used(2)
The MCP37221-200 and MCP37D21-200 devices have the 14-bit mode option only, while the MCP37231200 and MCP37D31-200 have all listed resolution options.
Output condition at “not-used” output pin:
- ‘0’ in CMOS mode. Leave these pins floating.
- High Z state in LVDS mode
DS20005322C-page 16
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
2.0
ELECTRICAL SPECIFICATIONS
2.1
Absolute Maximum Ratings†
Analog and digital supply voltage (AVDD12, DVDD12) .............. ......................................................................................... -0.3V to 1.32V
Analog and digital supply voltage (AVDD18, DVDD18) .............. ......................................................................................... -0.3V to 1.98V
All inputs and outputs with respect to GND ............................ ........................................................................... –0.3V to AVDD18 + 0.3V
Differential input voltage.......................................................... ........................................................................................|AVDD18 - GND|
Current at input pins................................................................ ...................................................................................................... ±2 mA
Current at output and supply pins .......................................... .................................................................................................. ±250 mA
Storage temperature ............................................................... ...................................................................................... -65°C to +150°C
Ambient temperature with power applied (TA) ........................ ...................................................................................... -55°C to +125°C
Maximum junction temperature (TJ)........................................ .................................................................................................... +150°C
ESD protection on all pins....................................................... ................................................................................................ 2 kV HBM
Solder reflow profile ................................................................ ................................ See Microchip Application Note AN233 (DS00233)
Notice†: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2.2
Electrical Specifications
TABLE 2-1:
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Min.
Typ.
Max.
Units
Analog Supply Voltage
AVDD18
1.71
1.8
1.89
V
AVDD12
1.14
1.2
1.26
V
Digital Supply Voltage
DVDD18
1.71
1.8
1.89
V
DVDD12
1.14
1.2
1.26
V
Conditions
Power Supply Requirements
Note 1
Analog Supply Current
Analog Supply Current
During Conversion
IDD_A18
—
27
46
mA
at AVDD18 pin
IDD_A12
—
185
252
mA
at AVDD12 pin
Digital Supply Current
During Conversion
IDD_D12
—
97
226
mA
at DVDD12 pin
Digital I/O Current in
CMOS Output Mode
IDD_D18
—
27
—
mA
at DVDD18 pin
DCLK = 100 MHz
Digital I/O Current in
LVDS Mode
IDD_D18
3.5 mA mode
Digital Supply Current
Measured at DVDD18 Pin
—
55
81
mA
39
—
mA
69
1.8 mA mode
5.4 mA mode
Supply Current during Power-Saving Modes
During Standby Mode
During Shutdown Mode
ISTANDBY_AN
—
21
—
ISTANDBY_DIG
—
41
—
IDD_SHDN
—
25
—
 2014-2015 Microchip Technology Inc.
mA
Address 0x00<4:3> = 1,1(2)
mA
Address 0x00<7,0> = 1,1(3)
DS20005322C-page 17
MCP37231/21-200 AND MCP37D31/21-200
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
IDD_PLL
—
21
—
mA
PDISS_ADC
—
387
—
mW
Total Power Dissipation
During Conversion with
CMOS Output Mode
PDISS_CMOS
—
436
—
mW
fS = 200 Msps,
DCLK = 100 MHz
Total Power Dissipation
During Conversion with
LVDS Output Mode
PDISS_LVDS
mW
3.5 mA mode
PLL Circuit
PLL Circuit Current
PLL enabled. Included in
analog supply current
specification.
Total Power Dissipation(4)
Power Dissipation
During Conversion,
Excluding Digital I/O
486
—
—
457
—
1.8 mA mode
511
5.4 mA mode
During Standby Mode
PDISS_STANDBY
—
80.4
—
mW
Address 0x00<4:3> = 1,1(2)
During Shutdown Mode
PDISS_SHDN
—
33
—
mW
Address 0x00<7,0> = 1,1(3)
Power-on Reset (POR) Voltage
Threshold Voltage
Hysteresis
SENSE
VPOR
—
800
—
mV
Applicable to AVDD12 only
VPOR_HYST
—
40
—
mV
(POR tracks AVDD12)
VSENSE
GND
—
AVDD12
V
VSENSE selects reference
RIN_SENSE
—
500
—

To virtual ground at 0.55V.
400 mV < VSENSE < 800 mV
ISENSE
—
500
—
µA
SENSE = 0.8V
—
0.74
—
V
VSENSE = GND
—
1.49
—
Input(5,7)
SENSE Input Voltage
SENSE Pin Input
Resistance
Current Sink into SENSE
Pin
Reference and Common-Mode Voltages
Internal Reference Voltage
(Selected by VSENSE)
VREF
—
1.86 x VSENSE
—
Common-Mode
Voltage Output
VCM
—
0.9
—
V
Available at VCM pin
VREF1
—
0.4
—
V
VSENSE = GND
—
0.8
—
—
0.4 - 0.8
—
—
0.7
—
Reference Voltage
Output(7,8)
VREF0
Bandgap Voltage Output
DS20005322C-page 18
VBG
VSENSE = AVDD12
400 mV < VSENSE < 800 mV
VSENSE = AVDD12
400 mV < VSENSE < 800 mV
V
VSENSE = GND
—
1.4
—
VSENSE = AVDD12
—
0.7 - 1.4
—
400 mV < VSENSE < 800 mV
—
0.55
—
V
Available at VBG pin
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Min.
Typ.
Max.
Units
AFS
—
1.4875
—
VP-P
Conditions
Analog Inputs
Full-Scale Differential
Analog Input Range(5,7)
VSENSE = GND
—
2.975
—
VSENSE = AVDD12
—
3.71875 x
VSENSE
—
400 mV < VSENSE < 800 mV
fIN_3dB
—
500
—
MHz
AIN = -3 dBFS
CIN
5
6
7
pF
Note 5, Note 9
Analog Input Channel
Cross-Talk
XTALK
—
100
—
dBc
Note 10
Analog Input Leakage
Current (AIN+, AIN- pins)
ILI_AH
—
—
+1
µA
VIH = AVDD12
ILI_AL
-1
—
—
µA
VIL = GND
fS
40
—
200
Msps
Tested at 200 Msps
fCLK
—
—
250
MHz
Note 5
VCLK_IN
300
—
800
CLKJITTER
—
175
—
fSRMS
49
50
51
%
Duty cycle correction
disabled
30
50
70
%
Duty cycle correction
enabled
ILI_CLKH
—
—
+110
µA
VIH = AVDD12
ILI_CLKL
-20
—
—
µA
VIL = GND
ADC Resolution
(with no missing code)
—
—
16
bits
MCP37231/MCP37D31
—
—
14
bits
MCP37221/MCP37D21
Offset Error
—
±5
±61
MCP37231/MCP37D31
Analog Input Bandwidth
Differential Input
Capacitance
ADC Conversion
Rate(11)
Conversion Rate
Clock Inputs (CLK+,
CLK-)(12)
Clock Input Frequency
Differential Input Voltage
Clock Jitter
Clock Input Duty
Cycle(5)
Input Leakage Current at
CLK input pin
Converter
mVP-P Note 5
Note 5
Accuracy(6)
—
±1.25
±15.25
LSb
LSb
Gain Error
GER
—
±0.5
—
% of FS
Integral Nonlinearity
INL
—
±2
—
LSb
MCP37231/MCP37D31
—
±0.5
—
LSb
MCP37221/MCP37D21
—
±0.4
—
LSb
MCP37231/MCP37D31
—
±0.1
—
LSb
MCP37221/MCP37D21
—
70
—
dB
DC measurement
Differential Nonlinearity
Analog Input
Common-Mode
Rejection Ratio
DNL
CMRRDC
 2014-2015 Microchip Technology Inc.
MCP37221/MCP37D21
DS20005322C-page 19
MCP37231/21-200 AND MCP37D31/21-200
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Dynamic Accuracy
Sym.
Min.
Typ.
Max.
Units
Conditions
SFDR
78
90
—
dBc
fIN = 15 MHz
dBc
fIN = 70 MHz
(6,15)
Spurious Free Dynamic
Range
77
85
—
SNR
fIN = 15 MHz
73.3
74.7
—
dBFS MCP37231/MCP37D31
—
74.2
—
dBFS MCP37221/MCP37D21
SNR
fIN = 70 MHz
—
74.2
—
dBFS MCP37231/MCP37D31
—
73.7
—
dBFS MCP37221/MCP37D21
ENOB
fIN = 15 MHz
—
12.1
—
bits
MCP37231/MCP37D31
—
12
—
bits
MCP37221/MCP37D21
ENOB
fIN = 70 MHz
—
12
—
bits
MCP37231/MCP37D31
—
11.7
—
bits
MCP37221/MCP37D21
Total Harmonic Distortion
(for all resolutions, first 13
harmonics)
THD
78
89
—
dBc
fIN = 15 MHz
77
82
—
dBc
fIN = 70 MHz
Worst Second or
Third Harmonic Distortion
HD2 or HD3
—
90
—
dBc
fIN = 15 MHz
—
83
—
dBc
fIN = 70 MHz
Two-Tone Intermodulation
Distortion
fIN1 = 15 MHz,
fIN2 = 17 MHz
IMD
—
90.5
—
dBc
Signal-to-Noise Ratio
Effective Number of Bits
(ENOB)(13)
AIN = -7 dBFS,
with two input frequencies
Digital Logic Input and Output (Except LVDS Output)
Schmitt Trigger High-Level
Input Voltage
VIH
0.7 DVDD18
—
DVDD18
V
Schmitt Trigger Low-Level
Input Voltage
VIL
GND
—
0.3 DVDD18
V
VHYST
—
0.05 DVDD18
—
V
Hysteresis of Schmitt
Trigger Inputs
(All digital inputs)
Low-Level Output Voltage
VOL
—
—
0.3
V
IOL = -3 mA, all digital I/O pins
High-Level Output Voltage
VOH
DVDD18 – 0.5
1.8
—
V
IOL = +3 mA, all digital I/O pins
Digital Data Output (CMOS Mode)
Maximum External Load
Capacitance
CLOAD
—
10
—
pF
From output pin to GND
Internal I/O Capacitance
CINT
—
4
—
pF
Note 5
DS20005322C-page 20
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Digital Data Output (LVDS Mode)
Min.
Typ.
Max.
Units
Conditions
(5)
LVDS High-Level
Differential Output Voltage
VH_LVDS
200
300
400
mV
100 differential termination,
LVDS bias = 3.5 mA
LVDS Low-Level
Differential Output Voltage
VL_LVDS
-400
-300
-200
mV
100 differential termination,
LVDS bias = 3.5 mA
LVDS Common-Mode
Voltage
VCM_LVDS
1
1.15
1.4
V
Output Capacitance
CINT_LVDS
—
4
—
pF
Internal capacitance from
output pin to GND
Differential Load
Resistance (LVDS)
RLVDS
—
100
—

Across LVDS output pairs
ILI_DH
—
—
+1
µA
VIH = DVDD18
ILI_DL
-1
—
—
µA
VIL = GND
ILI_DH
—
—
+6
µA
VIH = DVDD18
ILI_DL
-35
—
—
µA
VIL = GND(14)
Input Leakage Current on Digital I/O Pins
Data Output Pins
I/O Pins except Data
Output Pins
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
This 1.8V digital supply voltage is used for the digital I/O circuit, including SPI, CMOS and LVDS data output drivers.
Standby Mode: Most of the internal circuits are turned off, except the internal reference, clock, bias circuits and
SPI interface.
Shutdown Mode: All circuits including reference and clock are turned off except the SPI interface.
The total power dissipation (typical) is calculated by using the following equation:
PDISS = 1.8V x (IDD_A18 + IDD_D18) + 1.2V x (IDD_A12 + IDD_D12), where IDD_D18 is the digital I/O current for
LVDS or CMOS output.
This parameter is ensured by design, but not 100% tested in production.
This parameter is ensured by characterization, but not 100% tested in production.
See Table 4-2 for details.
Differential reference voltage output at REF1+/- and REF0+/- pins. VREF1 = VREF1+ – VREF1-.
VREF0 = VREF0+ – VREF0-. These references should not be driven.
Input capacitance refers to the effective capacitance between one differential input pin pair.
Channel cross-talk is measured when AIN = -1 dBFS at 12 MHz is applied on one channel while other channel(s)
are terminated with 50. See Figure 3-39 for details.
The ADC core conversion rate. In multi-channel mode, the conversion rate of an individual channel is fS/N, where
N is the number of input channels used.
See Figure 4-8 for the details of the clock input circuit.
ENOB = (SINAD - 1.76)/6.02.
This leakage current is due to the internal pull-up resistor.
Dynamic performance is characterized with CH(n)_DIG_GAIN<7:0> = 0011-1000.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 21
MCP37231/21-200 AND MCP37D31/21-200
TABLE 2-2:
TIMING REQUIREMENTS - LVDS AND CMOS OUTPUTS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Aperture Delay
Out-of-Range Recovery Time
Symbol
Min.
Typ.
Max.
Units
tA
—
1
—
ns
tOVR
Conditions
Note 1
—
1
—
—
50
—
TLATENCY
—
28
—
Clocks Note 2, Note 4
Power-Up Calibration Time
TPCAL
—
227
—
Clocks First 227 sample clocks
after power-up
Background Calibration Update Rate
TBCAL
—
230
—
Clocks Per 230 sample clocks
after TPCAL
TRESET
5
—
—
ns
Input Clock to
Output Clock Propagation Delay
tCPD
—
—
3.2
ns
Output Clock to
Data Propagation Delay
tDC
-0.25
—
+0.25
ns
Input Clock to
Output Data Propagation Delay
tPD
—
—
3.25
ns
Rise Time (20% to 80% of
output amplitude)(2,3)
tRISE_DATA
—
0.25
0.5
ns
tRISE_CLK
—
0.25
0.5
ns
Fall Time (80% to 20% of
output amplitude)(2,3)
tFALL_DATA
—
0.25
0.5
ns
tFALL_CLK
—
0.25
0.5
ns
Output Clock Duty Cycle
Pipeline Latency
System Calibration
Clocks Note 1
%
Note 1
(1 )
RESET Low Time
See Figure 2-8 for
details(1)
LVDS Data Output Mode
Note 1
CMOS Data Output Mode
Input Clock to
Output Clock Propagation Delay
tCPD
6
ns
DCLK=100 MHz,
fs = 200 Msps
Output Clock to
Data Propagation Delay
tDC
0.25
ns
DCLK=100 MHz,
fs = 200 Msps
Input Clock to
Output Data Propagation Delay
tPD
6.25
ns
DCLK=100 MHz,
fs = 200 Msps
tRISE_DATA
TBD
ns
DCLK=100 MHz,
fs = 200 Msps
tRISE_CLK
TBD
ns
DCLK=100 MHz,
fs = 200 Msps
tFALL_DATA
TBD
ns
DCLK=100 MHz,
fs = 200 Msps
tFALL_CLK
TBD
ns
DCLK=100 MHz,
fs = 200 Msps
Rise Time (20% to 80% of
output amplitude)
Fall Time (80% to 20% of
output amplitude)
Note 1:
2:
3:
4:
This parameter is ensured by design, but not 100% tested in production.
This parameter is ensured by characterization, but not 100% tested in production.
tRISE = approximately less than 10% of duty cycle.
Output latency is measured without using fractional delay recovery (FDR), decimation filter or digital
down-converter options.
DS20005322C-page 22
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
S-1
Input Signal:
S+1
S
*S = Sample Point
S+L-1
S+L
tA
Latency = L Cycles
Input Clock:
CLKCLK+
tCPD
Digital Clock Output:
DCLK
tDC
tPD
Output Data:
Q<N:0>
S-L-1
S-L
S-L+1
S-1
S
S-L-1
S-L
S-L+1
S-1
S
Over-Range Output:
OVR
Note:
FIGURE 2-1:
If the output resolution is selected for less than 16-bit, unused bits are ‘0’s.
Timing Diagram - CMOS Output.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 23
MCP37231/21-200 AND MCP37D31/21-200
S-1
Input Signal:
S+1
*S = Sample Point
S+L
S+L-1
S
tA
Latency = L Cycles
Input Clock:
CLKCLK+
tCPD
Digital Clock Output:
DCLKDCLK+
tDC
tPD
Output Data:
Q-[N:0]
Q+[N:0]
EVEN
S-L-1
ODD
S-L-1
EVEN
S-L
ODD
S-L
EVEN
S-L+1
EVEN
S-1
ODD
S-1
EVEN
S
WCK
S-L-1
OVR
S-L-1
WCK
S-L
OVR
S-L
WCK
S-L+1
WCK
S-1
OVR
S-1
WCK
S
Word-CLK/
Over-Range Output:
WCK/OVRWCK/OVR+
Note:
FIGURE 2-2:
If the output resolution is selected for less than 16-bit, unused bits are High Z.
Timing Diagram - LVDS Output with Even Bit First Option.
S-1
Input Signal:
S+1
S+L-1
S
S+L
tA
Latency = L Cycles
Input Clock:
CLKCLK+
tCPD
CLK Output:
DCLKDCLK+
tDC
tPD
Output Data:
Q-[N:0]
b[15:8]
S-L-1
b[7:0]
S-L-1
b[15:8]
S-L
b[7:0]
S-L
b[15:8]
S-L+1
b[15:8]
S-1
b[7:0]
S-1
b[15:8]
S
WCK
S-L-1
OVR
S-L-1
WCK
S-L
OVR
S-L
WCK
S-L+1
WCK
S-1
OVR
S-1
WCK
S
Q+[N:0]
Word-CLK/
Over-Range Output:
WCK/OVRWCK/OVR+
FIGURE 2-3:
Timing Diagram - LVDS Output with MSb Byte First Option. This output option is
available for 16-bit mode only.
DS20005322C-page 24
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Ch.7
Input Signal:
Ch.1
Ch.0
Ch.7
Ch.0
tA
Latency = L Cycles
Input Clock:
CLKCLK+
tCPD
CLK Output:
DCLKDCLK+
tDC
tPD
Output Data:
Q-[0]
b[1]
Ch.0
b[0]
Ch.0
b[15]
Ch.0
b[14]
Ch.0
b[13]
Ch.0
b[1]
Ch.0
b[0]
Ch.0
b[15]
Ch.0
b[1]
Ch.1
b[0]
Ch.1
b[15]
Ch.1
b[14]
Ch.1
b[13]
Ch.1
b[1]
Ch.1
b[0]
Ch.1
b[15]
Ch.1
b[1]
Ch.7
b[0]
Ch.7
b[15]
Ch.7
b[14]
Ch.7
b[13]
Ch.7
b[1]
Ch.7
b[0]
Ch.7
b[15]
Ch.7
“0”
OVR
WCK
“1”
OVR
“0”
“0”
OVR
WCK
“1”
Q+[0]
Q-[1]
Q+[1]
Q-[7]
Q+[7]
Word-CLK/
Over-Range Output:
WCK/OVRWCK/OVR+
Note: Q+/Q-[7] is the first channel selected data, and Q+/Q-[0] is the last channel selected data.
FIGURE 2-4:
Timing Diagram - LVDS Serial Output in Octal-Channel Mode. This output is available
for octal-channel with 16-bit mode only. Note that although the eight input channels are sampled
sequentially (auto-scan with 1 cycle separation), all channels are output simultaneously with the MSb (bit
15) synchronized with the rising edge of WCK.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 25
MCP37231/21-200 AND MCP37D31/21-200
TABLE 2-3:
SPI SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value. All timings are measured at 50%.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Serial Clock frequency, fSCK = 50 MHz
CS Setup Time
tCSS
10
—
—
ns
CS Hold Time
tCSH
20
—
—
ns
CS Disable Time
tCSD
20
—
—
ns
Data Setup Time
tSU
2
—
—
ns
Data Hold Time
tHD
4
—
—
ns
Serial Clock High Time
tHI
8
—
—
ns
Serial Clock Low Time
tLO
8
—
—
ns
Serial Clock Delay Time
tCLD
20
—
—
ns
Serial Clock Enable Time
tCLE
20
—
—
ns
Output Valid from SCK Low
tDO
—
—
20
ns
Output Disable Time
tDIS
—
—
10
ns
Note 1:
Note 1
Note 1
This parameter is ensured by design, but not 100% tested.
tCSD
CS
tSCK
tHI
tLO
tCSS
tCLE
tCSH
tCLD
SCLK
tSU
SDIO
(SDI)
FIGURE 2-5:
tHD
MSb in
LSb in
SPI Serial Input Timing Diagram.
CS
tSCK
tHI
tLO
tCSH
SCLK
tDO
SDIO
(SDO)
FIGURE 2-6:
DS20005322C-page 26
MSb out
tDIS
LSb out
SPI Serial Output Timing Diagram.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Power-on Reset (POR)
AVDD12
227 cycles
(TPCAL)
Power-Up calibration complete.
• Registers are initialized
• Device is ready for correct conversion
FIGURE 2-7:
POR Related Events: Register Initialization and Power-Up Calibration.
RESET Pin
tRESET
Power-Up Calibration Time
(TPCAL)
Stop ADC conversion
Start register initialization
and ADC recalibration
Recalibration complete:
• CAL Pin: High
• ADC_CAL_STAT = 1
RESET Pin Timing Diagram.
FIGURE 2-8:
TABLE 2-4:
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Temperature
Operating Temperature Range
Thermal Package
Min.
Typ.
Max.
Units
TA
-40
—
+85
°C
JA
—
40.2
—
°C/W
Conditions
Resistances(2)
121L Ball-TFBGA Junction-to-Ambient Thermal Resistance
(8 mm x 8 mm)
Junction-to-Case Thermal Resistance
124L – VTLA
(9 mm x 9 mm)
Note 1:
2:
Sym.
Ranges(1)
JC
—
8.4
—
°C/W
Junction-to-Ambient Thermal Resistance
JA
—
21
—
°C/W
Junction-to-Case (top) Thermal Resistance
JC
—
8.7
—
°C/W
Maximum allowed power-dissipation (PDMAX) = (TJMAX - TA)/JA.
This parameter value is achieved by package simulations.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 27
MCP37231/21-200 AND MCP37D31/21-200
NOTES:
DS20005322C-page 28
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
3.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 = DVDD18 = 1.8V, AVDD12 = DVDD12 = 1.2V, GND = 0V,
SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS, fIN = 70 MHz, Clock
Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation filters are disabled.
$PSOLWXGHG%)6
)UHTXHQF\0+]
)UHTXHQF\0+]
6)'5 G%F
7+' G%F
+' G%F
+' G%F
)UHTXHQF\0+]
)UHTXHQF\0+]
0RGH 6LQJOH
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
FIGURE 3-3:
FFT for 149 MHz Input
Signal: fS = 200 Msps/Ch., AIN = -1 dBFS.
 2014-2015 Microchip Technology Inc.
$PSOLWXGHG%)6
615 G%G%)6
FIGURE 3-5:
FFT for 69.5 MHz Input
Signal: fS = 200 Msps/Ch., AIN = -4 dBFS.
0RGH 6LQJOH
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
FIGURE 3-2:
FFT for 69.5 MHz Input
Signal: fS = 200 Msps/Ch., AIN = -1 dBFS.
$PSOLWXGHG%)6
0RGH 6LQJOH
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
)UHTXHQF\0+]
0RGH 6LQJOH
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
FIGURE 3-4:
FFT for 14.7 MHz Input
Signal: fS = 200 Msps/Ch., AIN = -4 dBFS.
$PSOLWXGHG%)6
$PSOLWXGHG%)6
FIGURE 3-1:
FFT for 14.7 MHz Input
Signal: fS = 200 Msps/Ch., AIN = -1 dBFS.
0RGH 6LQJOH
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
$PSOLWXGHG%)6
0RGH 6LQJOH
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
)UHTXHQF\0+]
FIGURE 3-6:
FFT for 149 MHz Input
Signal: fS = 200 Msps/Ch., AIN = -4 dBFS.
DS20005322C-page 29
MCP37231/21-200 AND MCP37D31/21-200
$PSOLWXGHG%)6
)UHTXHQF\0+]
FIGURE 3-7:
FFT for 14.7 MHz Input
Signal: fS = 100 Msps/Ch., Dual, AIN = -1 dBFS.
)UHTXHQF\0+]
)UHTXHQF\0+]
FIGURE 3-11:
FFT for 14.7 MHz Input
Signal: fS = 50 Msps/Ch., Quad, AIN = -4 dBFS.
)UHTXHQF\0+]
FIGURE 3-9:
FFT for 3.8 MHz Input
Signal: fS = 25 Msps/Ch., Octal, AIN = -1 dBFS.
DS20005322C-page 30
0RGH 2FWDO
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
$PSOLWXGHG%)6
0RGH 2FWDO
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
$PSOLWXGHG%)6
)UHTXHQF\0+]
0RGH 4XDG
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
FIGURE 3-8:
FFT for 14.7 MHz Input
Signal: fS = 50 Msps/Ch., Quad, AIN = -1 dBFS.
0RGH 4XDG
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
FIGURE 3-10:
FFT for 14.7 MHz Input
Signal: fS = 100 Msps/Ch., Dual, AIN = -4 dBFS.
$PSOLWXGHG%)6
$PSOLWXGHG%)6
0RGH 'XDO
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
$PSOLWXGHG%)6
0RGH 'XDO
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
)UHTXHQF\0+]
FIGURE 3-12:
FFT for 3.8 MHz Input
Signal: fS = 25 Msps/Ch., Octal, AIN = -4 dBFS.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
0RGH 2FWDO
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5 G%F
7+' G%F
+' G%F
+' G%F
)UHTXHQF\0+]
I
I
II
II
II
II
II
II
$PSOLWXGHG%)6
)UHTXHQF\0+]
FIGURE 3-15:
FFT for 14.7 MHz Input
Signal: fS = 25 Msps/Ch., Octal, AIN = -4 dBFS.
I&/. 0+]
I 0+]#G%)6
I 0+]#G%)6
II G%F
II G%F
6)'5 G%F
0RGH 6LQJOH
FIGURE 3-13:
FFT for 14.7 MHz Input
Signal: fS = 25 Msps/Ch., Octal, AIN = -1 dBFS.
0RGH 2FWDO
I&/. 0+]
I6 0VSV&+
I,1 0+]#G%)6
615 G%G%)6
6)'5
G%F
7+' G%F
+' G%F
+' G%F
6)'5#$,1 G%)6
6)'5#$,1 G%)6
615#$,1 G%)6
6)'5G%)6
$PSOLWXGHG%)6
615G%)6
$PSOLWXGHG%)6
615#$,1 G%)6
)UHTXHQF\0+]
FIGURE 3-14:
Two-Tone FFT:
fIN1 = 17.6 MHz and fIN2 = 20.6 MHz,
AIN = -7 dBFS per Tone, fS = 200 Msps.
 2014-2015 Microchip Technology Inc.
FIGURE 3-16:
Frequency.
,QSXW)UHTXHQF\0+]
SNR/SFDR vs. Input
DS20005322C-page 31
MCP37231/21-200 AND MCP37D31/21-200
6)'5G%F
615G%
,QSXW$PSOLWXGHG%)6
615G%)6
FIGURE 3-17:
SNR/SFDR vs. Analog Input
Amplitude: fS = 200 Msps, fIN = 70 MHz.
6)'5G%F
615G%
,QSXW$PSOLWXGHG%)6
6)'5G%)6
6)'5G%)6
6)'5G%)6
I,1 0+]
$,1 G%)6
6DPSOH5DWH0VSV
FIGURE 3-18:
SNR/SFDR vs. Sample
Rate (Msps): fIN = 70 MHz.
I,1 0+]
$,1 G%)6
6DPSOH5DWH0VSV
6)'5G%)6
615G%)6
I6 0VSV
I,1 0+]
$,1 G%)6
%*/2:
FIGURE 3-19:
SNR/SFDR vs. SENSE Pin
Voltage: fS = 200 Msps, fIN = 68 MHz.
6)'5G%)6 615G%)6
%*+,*+
6(16(3LQ9ROWDJH9
DS20005322C-page 32
615G%)6
6)'5G%)6
FIGURE 3-21:
SNR/SFDR vs. Sample
Rate (Msps): fIN = 15 MHz.
615G%)6
615G%)6
6)'5G%)6
615G%)6
615G%)6
615G%)6
FIGURE 3-20:
SNR/SFDR vs. Analog Input
Amplitude: fS = 200 Msps, fIN = 15 MHz.
615G%6)'5G%FG%)6
6)'5G%)6
%*/2:
6)'5G%)6
615G%)6
615G%)6
615G%)6
6)'5G%)6
615G%6)'5G%FG%)6
I6 0VSV
I,1 0+]
$,1 G%)6
6(16(3LQ9ROWDJH9
%*+,*+
FIGURE 3-22:
SNR/SFDR vs. SENSE Pin
Voltage: fS = 200 Msps, fIN = 15 MHz.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
615G%)6
6)'5G%)6
([WHUQDO9&09
615G%)6
6)'5G%)6
FIGURE 3-26:
HD2/HD3 vs. Supply
Voltage: fS = 200 Msps, fIN = 15 MHz.
$9'' 9
$9'' 9
5HVROXWLRQ %LW
7HPSHUDWXUHƒ&
$9'' 9
96(16( $9''
I6 0VSV
I,1 0+]
$,1 G%)6
FIGURE 3-24:
SNR/SFDR vs.Temperature:
fS = 200 Msps, fIN = 15 MHz.
I6 0VSV
I,1 0+]
$,1 G%)6
6XSSO\9ROWDJH9
FIGURE 3-25:
SNR/SFDR vs. Supply
Voltage: fS = 200 Msps, fIN = 15 MHz.
 2014-2015 Microchip Technology Inc.
*DLQ(UURUG%
6)'5G%)6
6)'5G%)6
615G%)6
VREF0 Vs. Temperature.
2IIVHW(UURU
615G%)6
7HPSHUDWXUHƒ&
FIGURE 3-27:
6XSSO\9ROWDJH9
6)'5G%)6
615G%)6
+'G%)6
+'G%)6
FIGURE 3-23:
SNR/SFDR vs. VCM Voltage
(Externally Applied): fS = 200 Msps,
fIN = 15 MHz.
I6 0VSV
I,1 0+]
$,1 G%)6
95()9
615G%)6
5HVROXWLRQ %LW
96(16( $9''
I6 0VSV
I,1 0+]
$,1 G%)6
*DLQ(UURU
7HPSHUDWXUHƒ&
2IIVHW(UURU/6%
+'1G%)6
6)'5G%)6
FIGURE 3-28:
Gain and Offset Error Drifts
Vs. Temperature Using Internal Reference, with
Respect to 25°C: fS = 200 Msps.
DS20005322C-page 33
MCP37231/21-200 AND MCP37D31/21-200
'1/(UURU/6%
,1/(UURU/6%
I&/. 0+] I,1 0+]
,1/ /6% $,1 )6
%LW0RGH&RGHV
I&/. 0+] I,1 0+]
'1/ /6% $,1 )6
%LW0RGH&RGHV
2XWSXW&RGH
FIGURE 3-29:
INL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 16-bit Mode.
I&/. 0+] I,1 0+]
,1/ /6% $,1 )6
%LW0RGH&RGHV
2XWSXW&RGH
FIGURE 3-32:
DNL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 16-bit Mode.
'1/(UURU/6%
,1/(UURU/6%
I&/. 0+]
I,1 0+]
'1/ /6% $,1 )6
%LW0RGH&RGHV
2XWSXW&RGH
FIGURE 3-30:
INL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 14-bit Mode.
I&/. 0+] I,1 0+]
,1/ /6% $,1 )6
%LW0RGH&RGHV
'1/(UURU/6%
2XWSXW&RGH
FIGURE 3-33:
DNL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 14-bit Mode.
,1/(UURU/6%
I&/. 0+]
I,1 0+]
'1/ /6% $,1 )6
%LW0RGH&RGHV
2XWSXW&RGH
FIGURE 3-31:
INL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz,12-bit Mode.
DS20005322C-page 34
2XWSXW&RGH
FIGURE 3-34:
DNL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 12-bit Mode.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
160k
140k
Resolution = 16-Bit
fS = 200 Msps
$PSOLWXGHG%
Occurences
120k
100k
80k
60k
40k
20k
0
-20
-15
-10
-5
0
5
Output Code
10
15
20
FIGURE 3-35:
Shorted Input Histogram:
fS = 200 Msps, Resolution = 16-Bit Shorted
Input.
)UHTXHQF\0+]
FIGURE 3-38:
I6 0VSV
$,1 G%)6
400k
&URVVWDONG%
Occurrences
Resolution = 14-Bit
fS = 200 Msps
300k
200k
Input Bandwidth.
500k
&+WR&+
&+WR&+
100k
-15
-10
-5
0
5
Output Code
10
15
20
FIGURE 3-36:
Shorted Input Histogram:
fS = 200 Msps, Resolution = 14-Bit.
,QSXW)UHTXHQF\0+]
FIGURE 3-39:
1.5M
Input Channel Cross-Talk.
240
Resolution = 12-Bit
fS = 200 Msps
500
AIN = -1 dBFS
450
IDD_A12
re
Co
C )
D
O
I/
rA
fo DS
er LV
w
t
o ep
lP
ta (exc
To
1.0M
Current (mA)
Occurrences
200
500k
160
120
80
400
IDD_D12
350
300
Power (mW)
0
-20
IDD_D18
40
0
-20
250
IDD_A18
-15
-10
-5
0
5
Output Code
10
15
20
FIGURE 3-37:
Shorted Input Histogram:
fS = 200 Msps, Resolution = 12-bit.
 2014-2015 Microchip Technology Inc.
0
0
50
100
150
200
250
Sampling Frequency (MHz)
00
FIGURE 3-40:
Power Consumption vs.
Sampling Frequency (LVDS Mode).
DS20005322C-page 35
MCP37231/21-200 AND MCP37D31/21-200
NOTES:
DS20005322C-page 36
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.0
THEORY OF OPERATION
4.1
ADC Core Architecture
Figure 4-1 shows the simplified block diagram of the
ADC core. The first stage consists of a 17-level flash
ADC, multi-level Digital-to-Analog Converter (DAC)
and a residue amplifier with a gain of 8. Stages 2 to 6
consist of a 9-level (3-bit) flash ADC, multi-level DAC
and a residue amplifier with a gain of 4. The last stage
is a 9-level 3-bit flash ADC. Dither is added in each of
the first three stages.The digital outputs from all seven
stages are combined in a digital error correction logic
block and digitally processed for the final output.
The MCP37231/21-200 and MCP37D31/21-200
device family is a low-power, 16-/14-bit, 200 Msps
Analog-to-Digital Converter (ADC) with built-in features
including Harmonic Distortion Correction (HDC), DAC
Noise Cancellation (DNC), Dynamic Element Matching
(DEM) and flash error calibration.
Depending on the product number selection, the device
offers various built-in digital signal post-processing
features, such as FIR decimation filters, Digital DownConversion (DDC), Fractional Delay Recovery (FDR),
continuous CW beamforming and digital gain and
offset correction. These built-in advanced digital signal
post-processing sub-blocks, which are individually
controlled, can be used for various special applications
such as I/Q demodulation, digital down-conversion,
and ultrasound imaging.
The first three stages include patented digital
calibration features:
• Harmonic Distortion Correction (HDC) algorithm
that digitally measures and cancels ADC errors
arising from distortions introduced by the residue
amplifiers
• DAC Noise Cancellation (DNC) algorithm that
corrects DAC’s nonlinearity errors
• Dynamic Element Matching (DEM) which
randomizes DAC errors, thereby converting
harmonic distortion to white noise
When the device is first powered-up, it performs internal calibrations by itself and runs with default settings.
From this point, the user can configure the device registers using the SPI command.
In multi-channel mode, the input channel selection and
MUX scan order are user-configurable, and the inputs
are sequentially multiplexed by the input MUX defined
by the scan order.
These digital correction algorithms are first applied
during the Power-on Reset sequence and then operate
in the background during normal operation of the
pipelined ADC. These algorithms automatically track
and correct any environmental changes in the ADC.
More details of the system correction algorithms are
shown in Section 4.13 “System Calibration”.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after
28 clock cycles of data latency. Latency will increase if
any of the various digital signal post-processing
(DSPP) options are enabled.
The output data can be coded in two’s complement or
offset binary format, and randomized using the user
option. Data can be output using either the CMOS or
LVDS (Low-Voltage Differential Signaling) interface.
Serialized LVDS output is also available in 16-bit octalchannel mode. In this mode, each input channel is output
serially over a unique LVDS pair.
Reference Generator
REF0
REF0
REF1
REF1
Clock Generation
REF1
REF1
REF1
REF1
REF1
AIN0+
AIN0Input
MUX
AIN7+
AIN7 -
Pipeline
Stage 1
(3-bit)
Pipeline
Stage 2
(2-bit)
Pipeline
Stage 3
(2-bit)
HDC1, DNC1
HDC2, DNC2
HDC3, DNC3
Pipeline
Stage 4
(2-bit)
Pipeline
Stage 5
(2-bit)
Pipeline
Stage 6
(2-bit)
3-bit Flash
Stage 7
(3-bit)
Digital Error Correction
User-Programmable Options
Programmable Digital Signal Post-Processing (DSPP)
16-Bit Digital Output
FIGURE 4-1:
ADC Core Block Diagram.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 37
MCP37231/21-200 AND MCP37D31/21-200
4.2
Supply Voltage (DVDD, AVDD, GND)
The device operates from two sets of supplies and a
common ground:
EQUATION 4-1:
SAMPLE RATE PER
CHANNEL
Full ADC Sample Rate  fs 
Sample Rate/Channel = --------------------------------------------------------------------Number of Channel Used
• Digital Supplies (DVDD) for the digital section:
1.8V and 1.2V
• Analog Supplies (AVDD) for the analog section:
1.8V and 1.2V
• Ground (GND): Common ground for both digital
and analog sections.
4.4
The supply pins require an appropriate bypass
capacitor (ceramic) to attenuate the high-frequency
noise present in most application environments. The
ground pins provide the current return path. These
ground pins must connect to the ground plane of the
PCB through a low-impedance connection. A ferrite
bead can be used to separate analog and digital supply
lines if a common power supply is used for both analog
and digital sections.
• SEL_NCH<2:0> in Address 0x01 (Register 5-2):
Select the total number of input channels to be
used.
• Addresses 0x7D – 0x7F (Registers 5-37 – 5-39):
Select auto-scan channel order.
The voltage regulators for each supply need to have
sufficient output current capabilities to support a stable
ADC operation.
4.3
Input Sample Rate
In single-channel mode, the device samples the input
at full speed. In multi-channel mode, the core ADC is
multiplexed between the selected channels. The resulting effective sample rate per channel is shown in
Equation 4-1.
For example, with 200 Msps operation, the input is
sampled at the full 200 Msps rate if a single channel is
used, or at 25 Msps per channel if all eight channels
are used.
TABLE 4-1:
No. of
Channels
(1)
Analog Input Channel Selection
The analog input is auto-multiplexed sequentially as
defined by the channel-order selection bit setting. The
user can configure the input MUX using the following
registers:
The user can select up to eight input channels. If all
eight input channels are to be used, SEL_NCH<2:0> is
set to 000 and the input channel sampling order is set
using Addresses 0x7D – 0x7F (Registers 5-37 – 5-39).
Regardless of how many channels are selected, all
eight channels must be programmed in Addresses
0x7D – 0x7F (Registers 5-37 – 5-39) without duplication. Program the addresses of the selected channels
in sequential order, followed by the unused channels.
The order of the unused channels has no effect. The
device samples the first N-Channels listed in
Addresses 0x7D – 0x7F (Registers 5-37 – 5-39)
sequentially, where N is the total number of channels to
be used, defined by the SEL_NCH<2:0>. Table 4-1
shows examples of input channel selection using
Addresses 0x7D – 0x7F (Registers 5-37 – 5-39).
EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
Selected
Channels
Channel
Order(2)
Address 0x7F
b
7
Address 0x7E
b
0
b
7
Address 0x7D
b
0
b
7
b
0
Channel Order Bit Settings
5th Ch.
8
4th Ch.
6th Ch.
3rd Ch.
7th Ch. 2nd Ch.
8th Ch.
1st Ch.
[0 1 2 3 4 5 6 7] [0 1 2 3 4 5 6 7]
(Default)
1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0
[7 6 5 4 3 2 1 0] [7 6 5 4 3 2 1 0]
0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1
[0 2 4 6 1 3 5 7] [0 2 4 6 1 3 5 7]
0 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0
[1 3 5 7 0 2 4 6] [1 3 5 7 0 2 4 6]
0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0 1
Channel Order Bit Settings
7
Note 1:
2:
Unused 4th Ch.
5th Ch.
3rd Ch.
6th Ch. 2nd Ch.
7th Ch.
1st Ch.
[0 1 2 3 4 5 6]
[0 1 2 3 4 5 6 7]
1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0
[0 2 4 6 1 3 5]
[0 2 4 6 1 3 5 7]
1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0
Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.
DS20005322C-page 38
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-1:
No. of
Channels
(1)
EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
Selected
Channels
Channel
Order(2)
Address 0x7F
b
7
Address 0x7E
b
0
b
7
Address 0x7D
b
0
b
7
b
0
Channel Order Bit Settings
6
Unused Unused 4th Ch.
3rd Ch.
5th Ch. 2nd Ch.
6th Ch.
1st Ch.
[0 1 2 3 4 5]
[0 1 2 3 4 5 6 7]
1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0
[0 2 4 6 1 3]
[0 2 4 6 1 3 5 7]
1 1 1 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0
Channel Order Bit Settings
5
Unused Unused Unused 3rd Ch.
4th Ch. 2nd Ch.
5th Ch.
1st Ch.
[0 1 2 3 4]
[0 1 2 3 4 5 6 7]
1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0
[0 2 4 6 1]
[0 2 4 6 1 3 5 7]
1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0
Channel Order Bit Settings
Unused Unused Unused Unused 3rd Ch. 2nd Ch.
4
4th Ch.
1st Ch.
[0 1 2 3 ]
[0 1 2 3 4 5 6 7]
1 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0
[4 5 6 7]
[4 5 6 7 0 1 2 3]
0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0
[0 2 4 6]
[0 2 4 6 1 3 5 7]
1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 1 0 0 0 0
[1 3 5 7]
[1 3 5 7 0 2 4 6]
1 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1
Channel Order Bit Settings
3
Unused Unused Unused Unused Unused 2nd Ch.
3rd Ch.
1st Ch.
[0 1 2]
[0 1 2 3 4 5 6 7]
1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0
[0 2 4]
[0 2 4 6 1 3 5 7]
0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 0
Channel Order Bit Settings
Unused Unused Unused Unused Unused Unused 2nd Ch.
2
1st Ch.
[0 1]
[0 1 2 3 4 5 6 7]
1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 0
[2 3]
[2 3 0 1 4 5 6 7]
1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0
[4 5]
[4 5 0 1 2 3 6 7]
0 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0
[6 7]
[6 7 0 1 2 3 4 5]
0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 0
Channel Order Bit Settings
Unused Unused Unused Unused Unused Unused Unused 1st Ch.
1
Note 1:
2:
[0]
[0 1 2 3 4 5 6 7]
1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0
[1]
[1 0 2 3 4 5 6 7]
1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1
[2]
[2 0 1 3 4 5 6 7]
1 0 0 0 1 1 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0
[3]
[3 0 1 2 4 5 6 7]
1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1
[4]
[4 0 1 2 3 5 6 7]
0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0
[5]
[5 0 1 2 3 4 6 7]
0 1 1 0 1 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1
[6]
[6 0 1 2 3 4 5 7]
0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 0
[7]
[7 0 1 2 3 4 5 6]
0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 1 1
Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 39
MCP37231/21-200 AND MCP37D31/21-200
Analog Input Circuit
The analog input (AIN) of all MCP37XXX devices is a
differential, CMOS switched capacitor sample-and-hold
circuit. Figure 4-2 shows the equivalent input structure
of the device.
The input impedance of the device is mostly governed
by the input sampling capacitor (CS = 6 pF) and input
sampling frequency (fS). The performance of the
device can be affected by the input signal conditioning
network (see Figure 4-3). The analog input signal
source must have sufficiently low output impedance to
charge the sampling capacitors (CS = 6 pF) within one
clock cycle. A small external resistor (e.g., 5Ω) in series
with each input is recommended, as it helps reduce
transient currents and dampens ringing behavior. A
small differential shunt capacitor at the chip side of the
resistors may be used to provide dynamic charging
currents and may improve performance. The resistors
form a low-pass filter with the capacitor and their values
must be determined by application requirements and
input frequency.
The VCM pin provides a common-mode voltage
reference (0.9V), which can be used for a center-tap
voltage of an RF transformer or balun. If the VCM pin
voltage is not used, the user may create a commonmode voltage at mid-supply level (AVDD18/2).
4.5.1
4.5.1.1
ANALOG INPUT DRIVING CIRCUIT
Differential Input Configuration
The device achieves optimum performance when the
input is driven differentially, where common-mode
noise immunity and even-order harmonic rejection are
significantly improved. If the input is single-ended, it
must be converted to a differential signal in order to
properly drive the ADC input. The differential
conversion and common-mode application can be
accomplished by using an RF transformer or balun with
a center-tap. Additionally, one or more anti-aliasing
filters may be added for optimal noise performance and
should be tuned such that the corner frequency is
appropriate for the system.
Figure 4-3 shows an example of the differential input
circuit with transformer. Note that the input-driving
circuits are terminated by 50 near the ADC side
through a pair of 25 resistors from each input to the
common-mode (VCM) from the device. The RF
transformer must be carefully selected to avoid
artificially high harmonic distortion. The transformer
can be damaged if a strong RF input is applied or an RF
input is applied while the MCP37XXX is powered-off.
The transformer has to be selected to handle sufficient
RF input power.
Figure 4-4 shows an input configuration example when
a differential output amplifier is used.
1
MCP37XXX
Hold
Sample
AIN+
50
CS = 6 pF
3 pF
MABAES0060
6
1
1
4
6
MABAES0060
3
3
VCM
AVDD18
5
Analog
Input
4
25
0.1 µF
25
5
Hold
Sample
50
3 pF
CS = 6 pF
FIGURE 4-3:
Configuration.
AIN+
50
3.3 pF
50
AIN-
Transformer Coupled Input
50
VCM
0.1 µF
FIGURE 4-2:
Equivalent Input Circuit.
High-Speed
Differential
Amplifier
Analog
Input
MCP37XXX
0.1 µF
AVDD18
AIN-
VCM
100
+
CM
-
AIN+
6.8 pF
100
MCP37XXX
4.5
AIN-
FIGURE 4-4:
DC-Coupled Input
Configuration with Preamplifier: the external
signal conditioning circuit and associated
component values are for reference only.
Typically, the amplifier manufacturer provides
reference circuits and component values.
DS20005322C-page 40
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Single-Ended Input Configuration
4.5.2
Figure 4-5 shows an example of a single-ended input
configuration. This single-ended input configuration is
not recommended for the best performance. SNR and
SFDR performance degrades significantly when the
device is operated in a single-ended configuration. The
unused negative side of the input should be
AC-coupled to ground using a capacitor.
The device has a bandgap-based differential internal
reference voltage. The SENSE pin voltage is used to
select the reference voltage source and configure the
input full-scale range. A comparator detects the
SENSE pin voltage and configures the full-scale input
range into one of the three possible modes which are
summarized in Table 4-2. Figure 4-6 shows an
example of how the SENSE pin should be driven.
VCM
50
0.1 µF
1 k
R
AIN+
VCM
C
1 k
10 µF
FIGURE 4-5:
Configuration.
0.1 µF
The SENSE pin can sink or source currents as high as
500 µA across all operational conditions. Therefore, it
may require a driver circuit, unless the SENSE
reference source provides sufficient output current.
0.1 µF
R
MCP37XXX
Analog
Input
10 µF
SENSE VOLTAGE AND INPUT
FULL-SCALE RANGE
MCP1700
0.1 µF
AIN-
R1
SENSE
R2
Singled-Ended Input
(Note 1)
Note
1:
This voltage buffer can be removed if the SENSE
reference is coming from a stable source (such as
MCP1700) which can provide a sufficient output
current to the SENSE pin.
FIGURE 4-6:
TABLE 4-2:
SENSE Pin Voltage Setup.
SENSE PIN VOLTAGE AND INPUT FULL-SCALE RANGE
SENSE Pin
Voltage
(VSENSE)
Selected
Reference Voltage
(VREF)
Full-Scale Input Voltage
Range (AFS)
Tied to GND
0.7V
1.4875 VP-P(1)
LSb Size
(Calculated with AFS)
16-bit mode: 22.7 µV
14-bit mode: 90.8 µV
0.4V – 0.8V
Tied to AVDD12
0.7V – 1.4V
1.4V
1.4875 VP-P to 2.975 VP-P(2)
2.975
VP-P(3)
Adjustable
16-bit mode: 45.4 µV
14-bit mode: 181.6 µV
Note 1:
2:
3:
4:
5:
0.1 µF
MCP37XXX
4.5.1.2
Condition
Low-Reference
Mode(4)
Sense Mode(5)
High-Reference
Mode(4)
AFS = (17/16) x 1.4 VP-P = 1.487 VP-P.
AFS = (17/16) x 2.8 VP-P x (VSENSE)/0.8 = 1.4875 VP-P to 2.975 VP-P.
AFS = (17/16) x 2.8 VP-P = 2.975 VP-P.
Based on internal bandgap voltage.
Based on VSENSE.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 41
MCP37231/21-200 AND MCP37D31/21-200
4.5.2.1
SENSE Selection Vs. SNR/SFDR
Performance
The SENSE pin is used to configure the full-scale input
range of the ADC. Depending on the application
conditions, the SNR, SFDR and dynamic range
performance are affected by the SENSE pin
configuration. Table 4-3 summarizes these settings.
• High-Reference Mode
This mode is enabled by setting the SENSE pin to AVDD12
(1.2V). This mode provides the highest input full-scale
range (2.975 VP-P) and the highest SNR performance.
Figure 3-17 and Figure 3-20 show SNR/SFDR versus
input amplitude in High-Reference mode.
TABLE 4-3:
• Low-Reference Mode
This mode is enabled by setting the SENSE pin to
ground. This mode is suitable for applications which have
a smaller input full-scale range. This mode provides
improved SFDR characteristics, but SNR is reduced by
-6 dB compared to the High-Reference Mode.
• SENSE Mode
This mode is enabled by driving the SENSE pin with an
external voltage source between 0.4V and 0.8V. This
mode allows the user to adjust the input full-scale
range such that SNR and dynamic range are optimized
in a given application system environment.
SENSE VS. SNR/SFDR PERFORMANCE
SENSE
Descriptions
High-Reference Mode
(SENSE pin = AVDD12)
High-input full-scale range (2.975 VP-P) and optimized SNR
Low-Reference Mode
(SENSE pin = ground)
Low-input full-scale range (1.4875 VP-P) and reduced SNR, but optimized SFDR
Sense Mode
(SENSE pin = 0.4V to 0.8V)
Adjustable-input full-scale range (1.4875 VP-P - 2.975 VP-P). Dynamic trade-off
between High-Reference and Low-Reference modes can be used.
DS20005322C-page 42
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
DECOUPLING CIRCUITS FOR
INTERNAL VOLTAGE REFERENCE
AND BANDGAP OUTPUT
4.5.3.1
Decoupling Circuits for REF1 and
REF0 Pins
4.6
External Clock Input
For optimum performance, the MCP37XXX requires a
low-jitter differential clock input at the CLK+ and CLK−
pins. Figure 4-8 shows the equivalent clock input circuit.
The device has two internal voltage references, and
these references are available at pins REF0 and REF1.
REF0 is the internal voltage reference for the ADC
input stage, while REF1 is for all remaining stages.
VTLA-124 Package Device: Figure 4-7 shows the
recommended circuit for the REF1 and REF0 pins for
the VTLA-124 package. Placing a 2.2 µF ceramic
capacitor with two additional optional capacitors (22 nF
and 220 nF) between the positive and negative
reference pins is recommended. The negative reference
pin is then grounded through a 220 nF capacitor. The
capacitors should be placed as close to the ADC as
possible with short and thick traces. Vias on the PCB are
not recommended for this reference pin circuit.
MCP37XXX
~300 fF
CLK+
300
AVDD12
Decoupling Circuit for VBG Pin
The bandgap circuit is a part of the reference circuit and
the output is available at the VBG pin.
VTLA-124 Package Device: VBG pin needs an external
decoupling capacitor (2.2 µF) as shown in Figure 4-7.
TFBGA-121 Package Device: The decoupling capacitor is embedded in the package. Therefore, no external
circuit is required on the PCB.
REF1+
REF1-
REF0+ REF0- VBG
2.2 µF
2.2 µF
22 nF
22 nF
220 nF
(optional)
2 pF
Clock
Buffer
300
~300 fF
FIGURE 4-8:
Circuit.
Equivalent Clock Input
The clock input amplitude range is between 300 mVP-P
and 800 mVP-P. When a single-ended clock source is
used, an RF transformer or balun can be used to
convert the clock into a differential signal for the best
ADC performance. Figure 4-9 shows an example clock
input circuit. The common-mode voltage is internally
generated and a center-tap is not required. The
back-to-back Schottky diodes across the transformer’s
secondary current limit the clock amplitude to
approximately 0.8 VP-P differential. This limiter helps
prevent large voltage swings of the input clock while
preserving the high slew rate that is critical for low jitter.
2.2 µF
220nF
CLK+
220 nF
Coilcraft
WBC1-1TL
6
1
4
3
50
FIGURE 4-7:
External Circuit for Voltage
Reference and VBG pins for the VTLA-124
Package. Note that this external circuit is not
required for the TFBGA-121 package.
 2014-2015 Microchip Technology Inc.
100 fF
100 fF
Clock
Source
220 nF
12 k
CLK-
TFBGA-121 Package Device: The decoupling capacitor is embedded in the package. Therefore, no external
circuit is required on the PCB.
4.5.3.2
AVDD12
AVDD12
0.1 µF
Schottky
Diodes
(HSMS-2812)
MCP37XXX
4.5.3
CLK-
FIGURE 4-9:
Transformer-Coupled
Differential Clock Input Configuration.
DS20005322C-page 43
MCP37231/21-200 AND MCP37D31/21-200
4.6.1
CLOCK JITTER AND SNR
PERFORMANCE
In a high-speed pipelined ADC, the SNR performance is
directly limited by thermal noise and clock jitter. Thermal
noise is independent of input clock and dominant term at
low-input frequency. On the other hand, the clock jitter
becomes a dominant term as input frequency increases.
Equation 4-2 shows the SNR jitter component, which is
expressed in terms of the input frequency (fIN) and the
total amount of clock jitter (TJitter), where TJitter is a sum
of the following two components:
• Input clock jitter (phase noise)
• Internal aperture jitter (due to noise of the clock
input buffer).
EQUATION 4-2:
SNR VS.CLOCK JITTER
SNR Jitter  dBc  = – 20  log 10  2   f IN  T Jitter 
where the total jitter term (Tjitter) is given by:
T Jitter =
2
2
 t Jitter , Clock Input  +  t Aperture , ADC 
The clock jitter can be minimized by using a high-quality clock source and jitter cleaners, as well as a bandpass filter at the external clock input while a faster clock
slew rate improves the ADC aperture jitter.
With a fixed amount of clock jitter, the SNR degrades
as the input frequency increases. This is illustrated in
Figure 4-10. If the input frequency increases from
10 MHz to 20 MHz, the maximum achievable SNR
degrades about 6 dB. For every decade (e.g. 10 MHz
to 100 MHz), the maximum achievable SNR due to
clock jitter is reduced by 20 dB.
160
Jitter = 0.0625 ps
140
Jitter = 0.125 ps
SNR (dBc)
120
Jitter = 0.25 ps
Jitter = 0.5 ps
Jitter = 1 ps
100
80
60
40
20
0
1
10
100
Input Frequency (fIN, MHz)
FIGURE 4-10:
DS20005322C-page 44
1000
SNR vs. Clock Jitter.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.7
ADC Clock Selection
This section describes the ADC clock selection and
how to use the built-in Delay-Locked Loop (DLL) and
Phase-Locked Loop (PLL) blocks.
When the device is first powered-up, the external clock
input (CLK+/-) is directly used for the ADC timing as
default. After this point, the user can enable the DLL or
PLL circuit by setting the register bits. Figure 4-11
shows the clock control blocks. Table 4-4 shows an
example of how to select the ADC clock depending on
the operating conditions.
TABLE 4-4:
ADC CLOCK SELECTION (EXAMPLE)
Features
Control Bit Settings(1)
Operating Conditions
Input Clock Duty
Cycle Correction
DCLK Output Phase
Delay Control
EN_DLL = 0
EN_DLL_DCLK = 0
EN_PHDLY = 0
Not Available
Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 0
Available
• DLL output is used
• Decimation is not used
EN_DLL = 1
EN_DLL_DCLK = 1
EN_PHDLY = 1
Available
• DLL output is not used
• Decimation is used(4)
EN_DLL = 0
EN_DLL_DCLK = X
EN_PHDLY = 1
Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 1
Available
CLK_SOURE = 0 (Default)(2)
• DLL output is not used
• Decimation is not used
(Default)(3)
Available
CLK_SOURCE = 1(5)
• Decimation is not used
EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 0
• Decimation is used(4)
EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 1
Note 1:
2:
3:
4:
5:
Not Available
Available
See Addresses 0x52, 0x53, and 0x64 for bit settings.
The sampling frequency (fS) of the ADC core comes directly from the input clock buffer
Output data is synchronized with the output data clock (DCLK), which comes directly from the input clock buffer.
While using decimation, output clock rate and phase delay are controlled by the digital clock output control block
The sampling frequency (fS) is generated by the PLL circuit. The external clock input is used as the reference input
clock for the PLL block.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 45
MCP37231/21-200 AND MCP37D31/21-200
fS
EN_DLL
Clock Input (fCLK): < 250 MHz
RESET_DLL
EN_DLL_DCLK = 0
EN_DLL = 0
EN_CLK
Input Clock Buffer
DLL Circuit
EN_PHDLY
DCLK
if CLK_SOURCE = 0
DCLK
Phase Delay
Duty Cycle Correction (DCC)
DCLK_PHDLY_DLL<2:0>
EN_DLL_DCLK
EN_DUTY
DLL Block
See Address 0x52 and 0x64<7> for details
if digital decimation is used
See Address 0x7A, 0x7B, 0x7C, and 0x81
if CLK_SOURCE = 1
EN_PHDLY
DCLK_PHDLY_DEC<2:0>
Digital Output
Clock Phase Delay Control
(when decimation filter is used)
DCLK
Digital Output
Clock Rate Control
OUT_CLKRATE<3:0>
Digital Clock Output Control Block
See Address 0x64 and 0x02
for control parameters
fREF
(5 MHz to 250 MHz)
EN_PLL
EN_PLL_BIAS
Loop Filter Control Parameters:
C1: PLL_CAP1<4:0>
C3
C2
C1
C3: PLL_CAP3<4:0>
R1
PLL_REFDIV<9:0>
R1: PLL_RES<4:0>
÷R
EN_PLL_REFDIV
C2: PLL_CAP2<4:0>
if digital decimation is used
See Address 0x7A, 0x7B, 0x7C, and 0x81
fS
(80 MHz - 250 MHz)
EN_PLL_OUT
fQ
Phase/Freq.
Detector
Current
Charge
Pump
Loop Filter
(3rd Order)
fVCO
Output/Div
DCLK
DCLK Delay
VCO
Loop Filter Control
PLL_CHAGPUMP<3:0>
÷N
PLL_PRE<11:0>
EN_PLL_CLK
DCLK_DLY_PLL<2:0>
PLL_OUTDIV<3:0>
PLL Output Control Block
See Address 0x55 and 0x6D
for control parameters
PLL Block
See Address 0x54 - 0x5D for Control Parameters
Note:
VCO output range is 1.075 GHz – 1.325 GHz by setting PLL_REFDIV<10:0> and PLL_PRE<11:0>, with fREF = 5 MHz - 250 MHz range.
N
= ----  f
=  1.075 – 1.325  GHz
VCO
R REF
f
FIGURE 4-11:
DS20005322C-page 46
Timing Clock Control Blocks.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.7.1
USING DLL MODE
Using the DLL block is the best option when output
clock phase control is needed while the clock multiplication and digital decimation are not required. When
the DLL block is enabled, the user can control the input
clock Duty Cycle Correction (DCC) and the output
clock phase delay.
See the DLL block in Figure 4-11 for details. Table 4-5
summarizes the DLL control register bits. In addition,
see Table 4-21 for the output clock phase control.
TABLE 4-5:
DLL CONTROL REGISTER BITS
Control Parameter
Register
Descriptions
CLK_SOURCE
0x53
CLK_SOURCE = 0: external clock input becomes input of the DLL block
EN_DUTY
0x52
Input clock duty cycle correction control bit(1)
EN_DLL
0x52
EN_DLL =1: enable DLL block
EN_DLL_DCLK
0x52
DLL output clock enable bit
EN_PHDLY<2:0>
0x52
Phase delay control bits of digital output clock (DCLK) when DLL or
decimation filter is used(2)
RESET_DLL
0x52
Reset control bit for the DLL block
Note 1:
2:
4.7.1.1
Duty cycle correction is not recommended when a high-quality external clock is used.
If decimation is used, the output clock phase delay is controlled using DCLK_PHDLY_DEC<2:0> in
Address 0x64.
Input Clock Duty Cycle Correction
4.7.1.2
DLL Block Reset Event
The ADC performance is sensitive to the clock duty
cycle. The ADC achieves optimum performance with
50% duty cycle, and all performance characteristics are
ensured when the duty cycle is 50% with ±1% tolerance.
The DLL must be reset if the clock frequency is
changed. The DLL reset is controlled by using the
RESET_DLL bit in Address 0x52 (Register 5-7). The
DLL has an automatic reset with the following events:
When CLK_SOURCE = 0, the external clock is used
as the sampling frequency (fS) of the ADC core. When
the external input clock is not high-quality (for example,
duty cycle is not 50%), the user can enable the internal
clock duty cycle correction circuit by setting the
EN_DUTY bit in Address 0x52 (Register 5-7). When
duty cycle correction is enabled (EN_DUTY=1), only
the falling edge of the clock signal is modified (rising
edge is unaffected).
• During power-up: Stay in reset until the
RESET_DLL bit is cleared.
• When a SOFT_RESET command is issued while
the DLL is enabled: the RESET_DLL bit is
automatically cleared after reset.
Because the duty cycle correction process adds additional jitter noise to the clock signal, this option is recommended only when an asymmetrical input clock
source causes significant performance degradation or
when the input clock source is not stable.
Note: The clock duty cycle correction is only
applicable when the DLL block is enabled
(EN_DLL = 1). It is not applicable for the PLL
output.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 47
MCP37231/21-200 AND MCP37D31/21-200
4.7.2
USING PLL MODE
The PLL block is mainly used when clock multiplication
is needed. When CLK_SOURCE = 1, the sampling frequency (fS) of the ADC core is coming from the internal
PLL block.
The recommended PLL output clock range is from
80 MHz to 250 MHz. The external clock input is used
as the PLL reference frequency. The range of the clock
input frequency is from 5 MHz to 250 MHz.
Note:
4.7.2.1
The PLL mode is only supported for
sampling frequencies between 80 MHz
and 250 MHz.
PLL Output Frequency and Output
Control Parameters
The internal PLL can provide a stable timing output
ranging from 80 MHz to 250 MHz. Figure 4-11 shows the
PLL block using a charge-pump-based integer N PLL
and the PLL output control block. The PLL block
includes various user control parameters for the desired
output frequency. Table 4-6 summarizes the PLL control
register bits and Table 4-7 shows an example of register
bit settings for the PLL charge pump and loop filter.
The PLL block consists of:
•
•
•
•
•
•
Reference Frequency Divider (R)
Prescaler - which is a feedback divider (N)
Phase/Frequency Detector (PFD)
Current Charge Pump
Loop Filter - a 3rd order RC low-pass filter
Voltage-Controlled Oscillator (VCO)
The external clock at the CLK+ and CLK- pins is the
input frequency to the PLL. The range of input frequency
(fREF) is from 5 MHz to 250 MHz. This input frequency is
divided by the reference frequency divider (R) which is
controlled by the 10-bit-wide PLL_REFDIV<9:0> setting.
In the feedback loop, the VCO frequency is divided by
the prescaler (N) using PLL_PRE<11:0>.
The ADC core sampling frequency (fS), ranging from
80 MHz to 250 MHz, is obtained after the output
frequency divider (PLL_OUTDIV<3:0>). For stable
operation, the user needs to configure the PLL with
the following limits:
• Input clock frequency (fREF)
= 5 MHz to 250 MHz
• Charge pump input frequency
= 4 MHz to 50 MHz
(after PLL reference divider)
• VCO output frequency
= 1.075 to1.325 GHz
• PLL output frequency after
output divider
= 80 MHz to 250 MHz
The charge pump is controlled by the PFD, and forces
sink (DOWN) or source (UP) current pulses onto the loop
filter. The charge pump bias current is controlled by the
PLL_CHAGPUMP<3:0> bits, approximately 25 µA per
step. The loop filter consists of a 3rd order passive RC filter. Table 4-7 shows the recommended settings of the
DS20005322C-page 48
charge pump and loop filter parameters, depending on
the charge pump input frequency range (output of the reference frequency divider).
When the PLL is locked, it tracks the input frequency
(fREF) with the ratio of dividers (N/R). The PLL operating
status is monitored by the PLL status indication bits:
<PLL_VCOL_STAT> and <PLL_VCOH_STAT> in
Address 0xD1 (Register 5-80).
Equation 4-3 shows the VCO output frequency (fVCO) as
a function of the two dividers and reference frequency:
EQUATION 4-3:
VCO OUTPUT
FREQUENCY
N
f VCO =  ---- f REF = 1.075  GHz  to 1.325  GHz 
R
Where:
N = 1 to 4095 controlled by PLL_PRE<11:0>
R = 1 to 1023 controlled by PLL_REFDIV<9:0>
See Addresses 0x54 to 0x57 (Registers 5-9 – 5-12) for
these bits settings.
The tuning range of the VCO is 1.075 GHz to 1.325 GHz.
N and R values must be chosen so the VCO is within this
range. In general, lower values of the VCO frequency
(fVCO) and higher values of the charge pump frequency
(fQ) should be chosen to optimize the clock jitter. Once the
VCO output frequency is determined to be within this
range, set the final ADC sampling frequency (fS) with the
PLL output divider using PLL_OUTDIV<3:0>. Equation 44 shows how to obtain the ADC core sampling frequency:
EQUATION 4-4:
SAMPLING FREQUENCY
f VCO
f S =  -------------------------------------- = 80 MHz to 250 MHz
PLL_OUTDIV
Table 4-8 shows an example of generating
fS = 200 MHz output using the PLL control parameters.
4.7.2.2
PLL Calibration
The PLL should be recalibrated following a change in
clock input frequency or in the PLL configuration
register bit settings (Addresses 0x54 - 0x57;
Registers 5-9 – 5-12).
The PLL can be calibrated by toggling the PLL_CAL_TRIG bit in Address 0x6B (Register 5-27) or by
sending a SOFT_RESET command (See Address 0x00,
Register 5-1). The PLL calibration status is observed by
the PLL_CAL_STAT bit in Address 0xD1 (Register 5-80).
4.7.2.3
Monitoring of PLL Drifts
The PLL drifts can be monitored using the status monitoring bits in Address 0xD1 (Register 5-80). Under normal operation, the PLL maintains a lock across all
temperature ranges. It is not necessary to actively monitor the PLL unless extreme variations in the supply voltage are expected or if the input reference clock
frequency has been changed.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-6:
PLL CONTROL REGISTER BITS
Control Parameter
Register
Descriptions
PLL Global Control Bits
EN_PLL
0x59
Master enable bit for the PLL circuit
EN_PLL_OUT
0x5F
Master enable bit for the PLL output
EN_PLL_BIAS
0x5F
Master enable bit for the PLL bias
EN_PLL_REFDIV
0x59
Master enable bit for the PLL reference divider
PLL Block Setting Bits
PLL_REFDIV<9:0>
0x54-0x55 PLL reference divider (R) (See Table 4-8)
PLL_PRE<11:0>
0x56-0x57 PLL prescaler (N) (See Table 4-8)
PLL_CHAGPUMP<3:0>
0x58
PLL charge pump bias current control: from 25 µA to 375 µA, 25 µA per step
PLL_RES<4:0>
0x5A
PLL loop filter resistor value selection (See Table 4-7)
PLL_CAP3<4:0>
0x5B
PLL loop filter capacitor 3 value selection (See Table 4-7)
PLL_CAP2<4:0>
0x5D
PLL loop filter capacitor 2 value selection (See Table 4-7)
PLL_CAP1<4:0>
0x5C
PLL loop filter capacitor 1 value selection (See Table 4-7)
PLL Output Control Bits
PLL_OUTDIV<3:0>
0x55
PLL output divider (See Table 4-8)
DCLK_DLY_PLL<2:0>
0x6D
Delay DCLK output up to 15 cycles of VCO clocks
EN_PLL_CLK
0x6D
EN_PLL_CLK = 1 enable PLL output clock to the ADC circuits
PLL Drift Monitoring Bits
PLL_VCOL_STAT
0xD1
PLL drift status monitoring bit
PLL_VCOH_STAT
0xD1
PLL drift status monitoring bit
0x6B
Forcing recalibration of the PLL
PLL Block Calibration Bits
PLL_CAL_TRIG
SOFT_RESET
0x00
PLL is calibrated when exiting soft reset mode
PLL_CAL_STAT
0xD1
PLL auto-calibration status indication
 2014-2015 Microchip Technology Inc.
DS20005322C-page 49
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-7:
RECOMMENDED PLL CHARGE PUMP AND LOOP FILTER BIT SETTINGS
PLL Charge Pump and Loop Filter
Parameter
fQ = fREF/PLL_REFDIV
fQ<5 MHz
5 MHz ≤ fQ < 25 MHz
fQ ≥ 25 MHz
PLL_CHAGPUMP<3:0>
0x04
0x04
0x04
PLL_RES<4:0>
0x1F
0x1F
0x07
PLL_CAP3<4:0>
0x07
0x02
0x07
PLL_CAP2<4:0>
0x07
0x01
0x08
PLL_CAP1<4:0>
0x07
0x01
0x08
TABLE 4-8:
EXAMPLE OF PLL CONTROL BIT SETTINGS FOR fS = 200 MHz WITH fREF = 100 MHz
PLL Control Parameter
fREF
Target
Value
100 MHZ
fS(1)
Descriptions
fREF is coming from the external clock input
200 MHZ
ADC sampling frequency
Target fVCO(2)
1.2 GHZ
Range of fVCO = 1.0375 GHz – 1.325 GHz
Target fQ(3)
10 MHZ
fQ = fREF/PLL_REFDIV (See Table 4-7)
PLL Reference Divider (R)
10
PLL_REFDIV<9:0> = 0x0A
PLL Prescaler (N)
120
PLL_PRE<11:0> = 0x78
PLL Output Divider
6
Note 1:
2:
3:
PLL_OUTDIV<3:0> = 0x06
fS = fVCO/PLL_OUTDIV = 1.2 GHz/6 = 200 MHz
fVCO = (N/R) x fREF = (12) x 100 MHz = 1.2 GHz
fQ should be maximized for the best noise performance.
DS20005322C-page 50
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.8
Digital Signal Post-Processing
(DSPP) Options
While the device converts the analog input signals to
digital output codes, the user can enable various digital
signal post-processing (DSPP) options for special
applications. These options are individually enabled or
disabled by setting the configuration bits. Table 4-9
summarizes the digital signal post-processing (DSPP)
options that are available for each device family.
TABLE 4-9:
DIGITAL SIGNAL POST PROCESSING (DSPP) OPTIONS
Digital Signal Post Processing Option
Available Operating Mode
Fractional Delay Recovery (FDR)
Dual and octal-channel modes
FIR Decimation Filters
Single and dual-channel modes
CW octal-channel mode
Offering Device
MCP37231/21-200
MCP37D31/21-200
DDC for I and Q data
Digital Gain and Offset correction per channel Available for all channels
Digital-Down Conversion (DDC)
Single and dual-channel modes
MCP37D31/21-200
CW octal-channel mode
Continuous Wave (CW) Beamforming
4.8.1
CW octal-channel mode
FRACTIONAL DELAY RECOVERY
FOR DUAL- AND OCTAL-CHANNEL
MODES
The FDR feature is available in dual and octal-channel
modes only. When FDR is enabled, the built-in highorder, band-limited interpolation filter compensates for
the time delay between input samples of different
channels. Due to the finite bandwidth of the interpolation
filter, the fractional delay recovery is not guaranteed for
input frequencies near the Nyquist frequency (fS/2). For
example, in dual-channel mode, FDR can operate
correctly for input frequencies in the range from 0 to
0.45*fS (or from 0.55*fs to fS if the input is in the 2nd
Nyquist band). In octal-channel mode, FDR can operate
correctly for input frequencies in the range from 0 to
0.38*fS. See Table 4-11 for the summary of the input
bandwidth requirement for FDR. The FDR process takes
place in the digital domain and requires 59 clock cycles
of processing time. Therefore, the output data latency is
also increased by 59 clock periods.
ADC Output for
dual- or octal-channel
FIR
Decimation Filters
Fractional Delay
Recovery
(FDR)
Digital
Down-Conversion (DDC)
FDR Control
CW
Beamforming
(MCP37D31/21-200)
(MCP37D31/21-200)
ADC data after
sampling time delay between
channels is removed
FIGURE 4-12:
Simplified Block Diagram for
ADC Output Data Path with Fractional Delay
Recovery Option. Note that Fractional Delay
Recovery occurs prior to other DSPP features.
Figure 4-12 shows the simplified block diagram for the
ADC output data path with FDR. The related configuration
register bits are listed in Table 4-10. Table 4-11 shows
the input bandwidth limits of the FDR feature for
distortion less than 0.1 mdB (0.1 × 10-3 dB), where fS
is the sampling frequency per channel. Figures 4-13
and 4-14 show the responses of the dual-channel and
octal-channel FDRs, respectively.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 51
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-10:
CONTROL PARAMETERS FOR FRACTIONAL DELAY RECOVERY (FDR)
Channel Operation
Control Parameter Register
Descriptions
Global control for both
dual and octal-channel
modes
EN_FDR = 1
0x7A
Enable FDR features
FDR_BAND
0x81
Select 1st or 2nd Nyquist band
Dual-channel
SEL_FDR = 0
0x81
Select FDR for dual-channel mode
EN_DSPP_8 = 0
0x81
Select digital signal post-processing feature for
dual-channel mode
EN_DSPP_2 = 1
0x79
Enable all digital post-processing functions for
dual-channel operation
SEL_FDR = 1
0x81
Select FDR for octal-channel mode
EN_DSPP_8 = 1
0x81
Select digital signal post-processing feature for
octal-channel operation
Octal-channel
TABLE 4-11:
INPUT BANDWIDTH
REQUIREMENT FOR FDR
0
Bandwidth
in percentage
of fS(1)
Nyquist Band (2)
-0.0005
0
2nd
45 – 55%
Nyquist Band (FDR_BAND = 1)
Avoid
Octal-Channel Mode
0 – 38%
Note 1:
2:
1st
Amplitude (dBc)
55 – 100%
1st Nyquist Band (FDR_BAND = 0)
fS/2
Interpolation Filter Frequency Response
fS
0
Dual-Channel Mode
0 – 45%
In-Band Ripple
0.0005
-30
-60
-90
Nyquist Band (FDR_BAND = 0)
fs is sampling frequency per channel.
Distortion is less than 0.1 mdB.
See Address 0x81 for FDR_BAND bit
setting
-120
0
fS/2
Frequency
fS
FIGURE 4-13:
Response of the DualChannel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.
In-Band Ripple
0.0005
0
-0.0005
0
fS/2
fS
2×fS
Frequency
3×fS
4×fS
fS/2
fS
2×fS
Frequency
3×fS
4×fS
Amplitude (dBc)
0
-30
-60
-90
-120
0
FIGURE 4-14:
Response of the OctalChannel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.
DS20005322C-page 52
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.8.2
DECIMATION FILTERS
The decimation feature is available in single and dualchannel modes and CW octal-channel mode.
Figure 4-15 shows a simplified decimation filter block,
and Table 4-13 shows the register settings. The
decimation rate is controlled by FIR_A<8:0> and
FIR_B<7:0> register settings (Addresses 0x7A –
0x7C: Registers 5-34 - ). These registers are
thermometer encoded.
In single-channel mode, FIR B is disabled and only
FIR A is used. In this mode, the maximum programmable decimation rate is 512x using nine cascaded
decimation stages.
In dual-channel mode or when using the Digital DownConversion (DDC) in I/Q mode, both FIR A and FIR B
are used (see Figure 4-15). In this case, both channels
are set to the same decimation rate. Note that stage 1A
in FIR A is unused: the user must clear FIR_A<0> in
Address 0x7A (Register 5-34). In dual-channel mode, the
maximum programmable decimation rate is up to 256x,
which is half the single-channel decimation rate (512x).
TABLE 4-12:
Decimation
Rate
DECIMATION RATE VS. SNR
PERFORMANCE
SNR (dBFS)
16-Bit Output
Mode
18-Bit Output
Mode(1)
8x
82.3
—
16x
84.8
—
32x
87.1
87.4
64x
89.2
89.7
128x
91.0
91.8
256x
92.0
93.2
512x
92.3
93.5
Note 1:
DM1DM2 bit is enabled.
The overall SNR performance can be improved with
higher decimation rate. In theory, 3 dB improvement is
expected with each successive stage of decimation
(2x per stage), but the actual improvement is approximately 2.5 dB per stage due to finite attenuation in the
FIR filters.
When using a high decimation rate option (128x or
above) in 16-bit mode, the user may consider enabling
two additional LSb output bits using the DM1DM2 bit
setting in Address 0x68 (Register 5-26). This results in
18-bit resolution. The recommended decimation rates
for adding these two additional bits are 128x or above.
This option is available for 16-bit devices only
(MCP37231-200 and MCP37D31-200).
Table 4-12 summarizes the decimation rate versus
SNR performance in 16-bit and 18-bit output modes.
The results indicate that the SNR is marginally
improved with higher decimation rates. Therefore, the
user may benefit from the 18-bit output mode when a
high decimation rate is used. When a low decimation
rate is used, there is no benefit to SNR or SFDR performance although the 18-bit output is enabled.
Table 4-13 summarizes the related control parameters
for using decimation filters.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 53
MCP37231/21-200 AND MCP37D31/21-200
4.8.2.1
Output Data Rate and Clock Phase
Control When Decimation is Used
When decimation is used, it also reduces the output
clock rate and output bandwidth by a factor equal to
the decimation rate applied: the output clock rate is
therefore no longer equal to the ADC sampling clock.
The user needs to adjust the output clock and data
rates in Address 0x02 (Register 5-3) based on the
decimation applied. This allows the output data to be
synchronized to the output data clock.
Phase shifts in the output clock can be achieved using
DCLK_PHDLY_DEC<2:0>
in
Address
0x64
(Register 5-22). Only four output sampling phases are
available when a decimation rate of 2x is used, while
all eight clock phases are available for other
decimation rates. See Section 4.12.9 “Output Data
and Clock Rates” for more details.
4.8.2.2
Using Decimation with CW
Beamforming and Digital DownConversion
Decimation can be used in conjunction with CW octalchannel mode or DDC. In CW octal-channel mode
operation, the eight input channels are summed into a
single channel prior to entering the decimation filters.
When DDC is enabled, the I and Q outputs can be
decimated using the same signal path for the dualchannel mode: I and Q data are fed into Channel A
and B, respectively.
In DDC mode, the half-band filter already includes a
2x decimation rate. Therefore, the maximum
decimation rate setting for I/Q filtering is 128x for the
FIR_A<8:1> and FIR_B<7:0>. See Section 4.8.3
“Digital
Down-Conversion
(MCP37D31/21-200
only)” for details.
Note:
Fractional Delay Recovery, Digital
Gain/Offset adjustment and DDC for I/Q
data options occur prior to the decimation
filters if they are enabled.
DS20005322C-page 54
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-13:
REGISTER CONTROL PARAMETERS FOR USING DECIMATION FILTERS
Control Parameter
Register
Descriptions
Decimation Filter Settings
FIR_A<8:0>
0x7A, 0x7B
Channel A FIR configuration for single- or dual-channel mode
FIR_B<7:0>
0x7C
Channel B FIR configuration for single- or dual-channel mode
(1 )
Output Data Rate and Clock Rate Settings
OUT_DATARATE<3:0>
0x02
Output data rate: Equal to decimation rate
OUT_CLKRATE<3:0>
0x02
Output clock rate: Equal to decimation rate
Output Clock Phase Control Settings(2)
EN_PHDLY
0x64
Enable digital output phase delay when decimation filter is used
DCLK_PHDLY_DEC<2:0>
0x64
Digital output clock phase delay control
Digital Signal Post-Processing (DSPP) Function Block Settings
EN_DSPP_2 = 1
Note 1:
2:
0x79
Enable dual-channel decimation
The output data and clock rates must be updated when decimation rates are changed.
Output clock (DCLK) phase control is used when the output clock is divided by OUT_CLKRATE<3:0>
bit settings.
I
Single-channel operation
Single
Ch.
Input
Stage 1A
FIR
D2
Single
Stage 2A
FIR
2
D4
Single
2
D8
Single
Stage 3A
FIR
2
Stage 9A
FIR
2
Stage 9B
FIR
(Note 1)
(Note 3)
Ch. A
Dual
Input
Ch.
DeMUX
Ch. B
Input
Dual-channel operation
Input for DDC
Input
DeMUX
D512
Single
2
Stage 2B
FIR
2
Stage 3B
FIR
(Note 2)
Ch. A
Output
MUX
D2
Dual
Output
MUX
D4
Dual
2
Output
MUX D256
Dual
Output
MUX D128
I/Q
Ch. B
DDC I/Q filtering
Note 1:
Stage 1A FIR is the first stage of the FIR A filter.
2:
(a) Single-channel mode: Only Channel A is used and controlled by FIR_A<8:0>.
(b) Dual-channel mode or I/Q filtering in DDC mode: Both Channel A and Channel B are used: Channel A is used for
the first channel or I data, and Channel B is used for the second channel or Q data.
3:
Maximum decimation rate:
(a) When I/Q filtering in DDC mode is not used: 512x for single-channel and 256x for dual-channel mode.
(b) I/Q filtering in DDC mode: 128x each for FIR_A<8:1> and FIR_B<7:0>.
FIGURE 4-15:
Simplified Block Diagram of Decimation Filters.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 55
MCP37231/21-200 AND MCP37D31/21-200
4.8.3
DIGITAL DOWN-CONVERSION
(MCP37D31/21-200 ONLY)
Example:
If the ADC is sampling an input at 200 Msps, but the
user is only interested in a 5 MHz span which is
centered at 67 MHz, the digital down-conversion may
be used to mix the sampled ADC data with 67 MHz to
convert it to DC. The resulting signal can then be
decimated by 16x such that the bandwidth of the ADC
output is 6.25 MHz (200 Msps/16x decimation gives
12.5 Msps with 6.25 MHz Nyquist bandwidth). If fS/8
mode is selected, then a single 25 Msps channel is
output, where 6.25 MHz in the output data
corresponds to 67 MHz at the ADC input. If I/Q mode
is selected, then two 12.5 Msps channels are output,
where DC corresponds to 67 MHz and the channels
represent in-phase (I) and quadrature (Q) components
of the down-conversion.
The Digital Down-Conversion (DDC) feature is available in single-, dual- and CW octal-channel modes in
the MCP37D31/21-200. This feature can be optionally
combined with the decimation filter and used to:
• translate the input frequency spectrum to a lower
frequency band
• remove the unwanted out-of-band portion
• output the resulting signal as either I/Q data or as a
real signal centered at 25% of the output data rate.
Figure 4-16 and Figure 4-17 show the DDC
configuration for single- and dual-channel DDC mode,
respectively. The DDC includes a 32-bit, complex
numerically controlled oscillator (NCO), a selectable
(high/low) half-band filter, optional decimation, and two
output modes (I/Q or fS/8).
4.8.3.1
Single-Channel DDC
Figure 4-16
shows
the
single-channel
DDC
configuration. Each of these processing sub-blocks are
individually controlled. Examples of setting registers for
selected output type are shown in Tables 4-14 and 4-15.
Frequency translation is accomplished with the NCO.
The NCO frequency is programmable from 0 Hz to fS.
Phase and amplitude dither can be enabled to improve
spurious performance of the NCO.
This DDC feature can be used in a variety of highspeed signal-processing applications, including digital
radio, wireless base stations, radar, cable modems,
digital video, MRI imaging, etc.
I or IDEC
(Note 5)
Q or QDEC
FIR_A<8:1>
(Note 3)
I
CH. A
ADC DATA
Q
COS
SIN
NCO (32-bit)
(Note 2)
Half-Band Filter A
LP/HP
HBFILTER_A
FIR A
Decimation Filter
FIR B
Decimation Filter
NCO (
fS/8
DER
)
EN_DDC_FS/8
FIR_B<7:0>
(Note 4)
Real
or
RealDEC
EN_DDC2
EN_NCO
EN_DDC1
Down-Converting and Decimation
(Note 1)
Decimation and Output Frequency Translation
(Note 1)
Note 1: See Address 0x80 - 0x81 (Registers 5-40 – 5-41) for the control parameters.
2: See Figure 4-18 for details of NCO control block.
3: Half-band Filter A includes a single- stage decimation filter.
4: See Figure 4-15 for details.
5: Switches are closed if decimation filter is not used, and open if decimation filter is used.
FIGURE 4-16:
Simplified DDC Block Diagram for Single-Channel Mode. See Tables 4-14 and 4-15
for Using This DDC Block.
DS20005322C-page 56
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.8.3.2
Dual-Channel DDC
output after the half-band filter is up-converted by fS/8
for each channel. Otherwise, I/Q of each channel will be
output separately, similar to a four-channel input device
with the WCK output pin toggling synchronously with
the I-data of Channel A. Note that the NCO phase can
be adjusted uniquely for each of the two input channels
(see Figure 4-18). Examples of setting registers for
selected output type are shown in Tables 4-16 and 4-17.
Figure 4-17 shows the dual-channel DDC configuration.
Each channel includes the same processing elements
as shown in the single-channel DDC, however the I/Q
outputs cannot be separately decimated since the
device only supports two channels of decimation (four
would be required for I/Q of Channel A and I/Q of Channel B). The decimation option can be used if the DDC
IA
ADC
Data:
IA
CH. A
QA
EN_NCO
(Note 2)
SIN
CH. B
RealA
HBFILTER_A
NCO (32-bit)
COS
Half-Band Filter A
LP/HP
SIN
COS
QA
(Note 3)
EN_DDC_FS/8
NCO (fS/8)
EN_DDC2
(Note 3)
QB
IB
RealB
Half-Band Filter B
LP/HP
IB
HBFILTER_B
EN_DDC1
QB
Down-Converting and Decimation (Note 1)
Output Frequency Translation and Decimation (Note 1)
Note 1: See Address 0x80 – 0x81 for the Control Parameters.
2: See Figure 4-18 for details of NCO control block.
3: Half-band Filter A and B include a single-stage decimation filter.
FIGURE 4-17:
Simplified DDC Block Diagram for Dual-Channel Mode. See Tables 4-16 and 4-17 for
Using this DDC Block.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 57
MCP37231/21-200 AND MCP37D31/21-200
4.8.3.3
Numerically Controlled Oscillator
(NCO)
The on-board Numerically Controlled Oscillator (NCO)
provides the frequency reference for the in-phase and
quadrature mixers in the digital down-converter (DDC).
The NCO serves as a quadrature local oscillator,
capable of producing an NCO frequency of between 0
Hz and fS with a resolution of fS/232, where fS is the
ADC core sampling frequency.
Phase Offset Control
CH(n) NCO_PHASE<15:0>
Phase Dither
Note: The NCO is only used for DDC or CW octalchannel mode. It should be disabled when
not in use.
EN_PHSDITH
Amplitude Dither
EN_LFSR
Sine/Cosine
Signal Generator
NCO Tuning
EN_NCO
Figure 4-18 shows the control signals associated with
the NCO. In octal- or dual-channel mode, the NCO
allows the output phase to be adjusted on a
per-channel basis.
EN_AMPDITH
EN_LFSR
NCO Output
NCO_TUNE<31:0>
FIGURE 4-18:
NCO block diagram
4.8.3.4
• NCO Frequency Control:
The NCO frequency is programmed from 0 Hz to fS,
using the 32-bit-wide unsigned register variable
NCO_TUNE<31:0> in Addresses 0x82 – 0x85
(Registers 5-42 – 5-45).
The following equation is
NCO_TUNE<31:0> register:
EQUATION 4-5:
used
to
set
the
NCO FREQUENCY
NCO_TUNE<31:0> = round  2

Where:
32
Mod  f NCO f S 
 ----------------------------------
fS
fS = sampling frequency (Hz)
fNCO = desired NCO frequency (Hz)
Mod (fNCO, fS) = gives the remainder of fNCO/fS
Mod() is a remainder function. For
Mod(5,2) = 1 and Mod(1.999, 2) = 1.999.
example,
Example 1:
If fNCO is 100 MHz and fS is 200 MHz:
Mod  f NCO f S  = Mod  100 200  = 100
32 Mod  100 200 
NCO_TUNE<31:0> = round  2  --------------------------------------


200
= 0x8000 0000
Example 2:
If fNCO is 199.99999994 MHz and fS is 200 MHz:
Mod  f NCO f S  = Mod  199.99999994 200  = 199.99999994
32 Mod  199.99999994 200 
NCO_TUNE<31:0> = round  2  ---------------------------------------------------------------


200
= 0xFFFF FFFF
DS20005322C-page 58
NCO Amplitude and Phase Dither
The EN_AMPDITH and EN_PHSDITH parameters in
Address 0x80 (Register 5-40) can be used for
amplitude and phase dithering, respectively. In
principle, these will dither the quantization error created
by the use of digital circuits in the mixer and local
oscillator, thus reducing spurs at the expense of noise.
In practice, the DDC circuitry has been designed with
sufficient noise and spurious performance for most
applications. In the worst-case scenario, the NCO has
an SFDR of greater than 116 dB when the amplitude
dither is enabled, and 112 dB when disabled. Although
the SNR (≈ 93 dB) of the DDC is not significantly
affected by the dithering option, using the NCO with
dithering options enabled is always recommended for
the best performance.
4.8.3.5
NCO for fS/8 and fS/(8xDER)
The output of the first down-conversion block (DDC1)
is a complex signal (comprising I and Q data) which can
then be optionally decimated further up to 128x to
provide both a lower output data rate and input channel
filtering. If fS/8 mode is enabled, a second mixer stage
(DDC2) will convert the I/Q signals to a real signal
centered at half of the current Nyquist frequency; i.e., if
the output data rate in I/Q mode is 25 Msps per channel
(12.5 MHz Nyquist), then in fS/8 mode the output data
rate would be 50 Msps (25 Msps each for I and Q), and
the signal would be re-centered around 12.5 MHz. In
single-channel mode, this is done at the output of the
decimation filters (if used). In dual-channel mode, this
must be done prior to the decimation.
When decimation is enabled, the I/Q outputs are upconverted by fS/(8xDER), where DER is the additional
decimation rate added by the FIR decimation filters.
This provides a decimated output signal centered at
fS/8 or fS/(8xDER) in the frequency domain.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.8.3.6
NCO Phase Offset Control
4.8.3.8
The user can add phase offset to the NCO frequency
using the NCO phase offset control registers
(Addresses 0x86 to 0x95, Registers 5-46 – 5-61).
CH(n)_NCO_PHASE<15:0> is the 16-bit-wide NCO
phase offset control parameter for Channel n. A
0x0000 value in the register corresponds to no offset,
and a 0xFFFF corresponds to an offset of 359.995°.
The phase offset can be controlled with 0.005° per
step. The following equation is used to program the
NCO phase offset register:
EQUATION 4-6:
NCO PHASE OFFSET
CH(n)_NCO_PHASE<15:0> = 2
16
Offset Value (  
 ---------------------------------------
Where:
360
n = channel number
Offset Value () = desired phase offset value in
degrees
A decimal number is used for the binary contents of
CH(n)_NCO_PHASE<15:0>.
4.8.3.7
Half-Band Filter
The frequency translation is followed by a half-band
digital filter, which is used to reduce the sample rate by
a factor of two while rejecting aliases that fall into the
band of interest.
The user can select high- or low-pass half-band filter
using the HBFILTER_A and HBFILTER_B bits in
Address 0x80 (Register 5-40). These filters provide
greater than 90 dB of attenuation in the attenuation
band and less than 1 mdB (10-3 dB) of ripple in the
passband region of 20% of the input sampling rate.
For example, for an ADC sample rate of 200 MSPS,
these filters provide less than 1 mdB of ripple over a
bandwidth of 40 MHz.
The filter responses shown in Figures 4-15 and 4-16 indicate a ripple of 0.5 mdB and an alias rejection of 90 dB.
The output of the half-band filter is a DC-centered complex signal (I and Q). This I and Q signal is then carried to
the next down-conversion stage (DDC2) for frequency
translation (up-conversion), if the DDC is enabled.
Note:
The half-band filter delays the data output
by 80 clock cycles: 2 (due to decimation) x
40 cycles (due to group delay)
In-Phase and Quadrature Signals
When the first down-conversion is enabled, it produces
In-phase (I) and Quadrature (Q) components as shown
in Equation 4-7:
0
-0.0005
0
I AND Q SIGNALS
I = ADC  COS  2  f NCO t +  
Q = ADC  SIN  2  f NCO t +  
(a)
(b)
where:
CH(n)_NCO_PHASE<15:0>
 = 360  ---------------------------------------------------------------------16
0.1
0.2
0.3
0.4
Half-Band Filter Frequency Response
0.5
0.1
0.5
0
(c)
Amplitude (dBc)
EQUATION 4-7:
In-Band Ripple
0.0005
2
= 0.005493164   CH(n)_NCO_PHASE<15:0>
where:
ADC = output of the ADC block
-60
-90
-120
0
0.2
0.3
0.4
Fraction of Input Sample Rate
FIGURE 4-19:
High-Pass (HP) Response
of Half-Band Filter.
 = NCO phase offset of selected channel, which
is defined by CH(n)_NCO_PHASE<15:0> in
Addresses 0x86 - 0x95
t = k/fS, with k =1, 2, 3,..., n
-30
In-Band Ripple
0.0005
0
-0.0005
0
fNCO = NCO frequency
0.1
0.2
0.3
0.4
Half-Band Filter Frequency Response
0.5
0.1
0.5
I and Q outputs are interleaved where I data is output
on the rising edge of the WCK. If I and Q outputs are
selected in dual-channel mode with DDC enabled, I
data of Channel 0 is output at the rising edge of WCK,
followed by Q data of Channel 0, then I and Q data of
Channel 1 in the same way.
Amplitude (dBc)
0
-30
-60
-90
-120
0
FIGURE 4-20:
Half-Band Filter.
 2014-2015 Microchip Technology Inc.
0.2
0.3
0.4
Fraction of Input Sample Rate
Low-Pass (LP) Response of
DS20005322C-page 59
MCP37231/21-200 AND MCP37D31/21-200
4.8.4
EXAMPLES OF REGISTER
SETTINGS FOR USING DDC AND
DECIMATION
The following tables show examples of setting registers
for using decimation and digital down-conversion (DDC)
depending on the output type selection. This feature is
available in the MCP37D31/21-200 device only.
DDC
Mode
Addr.
0x02(2)
0x7A<6>
(FIR_A<0>)
0x7B
(FIR_A<8:1>)
0x7C
(FIR_B<7:0>)
0x80<5,1,0>(3)
0x81<6,3,2>(4)
0x79<7>
(EN_DSPP_2)
REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS
FOR SINGLE-CHANNEL MODE – EXAMPLE
Decimation Rate
(by FIR A and FIR B)(1)
TABLE 4-14:
0
Disabled
0x00
0
0x00
0x00
0,0,0
0,0,0
0
ADC
8
Disabled
0x33
1
0x03
0x00
0,0,0
0,0,0
0
ADC with decimation
(÷8)
512
Disabled
0x99
1
0xFF
0x00
0,0,0
0,0,0
0
ADC with decimation
(÷512)
0
I/Q
0x00(5)
0
0x00
0x00
1,0,1
0,0,0
0
I/Q Data
8
I/Q
0x33
0
0x07
0x07
1,0,1
0,0,0
0
Decimated I/Q (÷8)
0
0x00
0x00
1,1,1
0,0,0
0
Real without
additional decimation
0
0x07
0x07
1,0,1
1,0,0
0
Real with decimation
(÷16)
FIR A Filter
0
fS/8
8
fS/8
Note 1:
2:
3:
4:
5:
6:
0x11
(6)
0x44
FIR B Filter
DDC1
DDC2
Dual-Channel
DSPP Control
Output
When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-I/Q option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
Output data and clock rate control register.
0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate
adjustment is not needed.
The Half-Band Filter A includes decimation of 2.
DS20005322C-page 60
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-15:
OUTPUT TYPE VS. CONTROL PARAMETERS FOR SINGLE-CHANNEL DDC
(EXAMPLE)
Output Type
Complex: I and Q
Decimated I and
Q:IDEC, QDEC
Control Parameter
Register
Descriptions
EN_DDC1 = 1
0X80
Enable DDC1 block
EN_NCO = 1
0X80
Enable 32-bit NCO
HBFILTER_A = 1
0X80
Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 0
0X80
NCO(fS/8/DER) is disabled
EN_DDC2 = 0
0X81
DDC2 is disabled
FIR_A<8:1> = 0x00
0X7B
FIR A decimation filter is disabled
FIR_B<7:0> = 0x00
0X7C
FIR B decimation filter is disabled
OUT_CLKRATE<3:0>
0X02
Output clock rate is not affected (no need to change)
EN_DDC1 = 1
0X80
Enable DDC1 block
EN_NCO = 1
0X80
Enable 32-bit NCO
HBFILTER_A = 1
0X80
Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 0
0X80
NCO(fS/8/DER) is disabled
EN_DDC2 = 0
0X81
DDC2 is disabled
FIR_A<8:1>
0X7B
Program FIR A filter for extra decimation(1)
FIR_B<7:0>
0X7C
Program FIR B filter for extra decimation(1)
OUT_CLKRATE<3:0>
0X02
Adjust the output clock rate to the decimation rate
EN_DDC1 = 1
0X80
Enable DDC1 block
EN_NCO = 1
0X80
Enable 32-bit NCO
HBFILTER_A = 1
0X80
Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 1
0X80
NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8(2)
EN_DDC2 = 1
0X81
DDC2 is enabled
FIR_A<8:1> = 0x00
0X7B
Decimation filter FIR A is disabled
FIR_B<7:0> = 0x00
0X7C
Decimation filter FIR B is disabled
OUT_CLKRATE<3:0>
= 0001
0X02
Adjust the output clock rate to divided by 2(3)
Decimated Real:
EN_DDC1 = 1
0X80
Enable DDC1 block
RealA_DEC
EN_NCO = 1
0X80
Enable 32-bit NCO
HBFILTER_A = 1
0X80
Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 1
0X80
NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8/DER(2)
Real: RealA after
DDC(fS/8/DER)
without using
Decimation Filter
after Decimation
Filter and
DDC(fS/8/DER)
Note 1:
2:
3:
4:
EN_DDC2 = 1
0X81
DDC2 is enabled
FIR_A<8:1>
0X7B
Program FIR B filter for extra decimation(4)
FIR_B<7:0>
0X7C
Program FIR B filter for extra decimation(4)
OUT_CLKRATE<3:0>
0X02
Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
For I/Q decimation, the maximum decimation rate for the FIR A and FIR B filters is 128x each since the
input is already decimated by 2x in the Half-Band Filter. See Figure 4-15 for details.
DER is the decimation rate setting of the FIR A and FIR B filters.
Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).
 2014-2015 Microchip Technology Inc.
DS20005322C-page 61
MCP37231/21-200 AND MCP37D31/21-200
REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS FOR DUAL-CHANNEL
MODE EXAMPLE
0x7B
(FIR_A<8:1>)
0x7C
(FIR_B<7:0>)
0x80<5,1,0>(3)
0x81<6,3,2>(4)
0x79<7>
(EN_DSPP_2)
Dual-Channel
DSPP
Control
0x7A<6>
(FIR_A<0>)
DDC2
Address 0x02(2)
DDC1
DDC-Mode
FIR B Filter
Decimation Rate
(by FIR A and FIR B)(1)
TABLE 4-16:
0
Disabled
0x00
0
0x00
0x00
0,0,0
0,0,0
0
8
Disabled
0x33
0
0x07
0x07
0,0,0
0,0,0
0
ADC with decimation (÷8)
256
Disabled
0x88
0
0xFF
0xFF
0,0,0
0,0,0
0
ADC with decimation (÷256)
0
I/Q
0x00(5)
0
0x00
0x00
1,0,1
0,0,0
1
I/Q data
0
fS/8
(6)
0
0x00
0x00
1,1,1
0,0,0
1
Real without additional
decimation
8
fS/8
0
0x0E
0x0E(7)
1,1,1
0,0,0
1
Real with decimation filter
(÷16)
Note 1:
2:
3:
4:
5:
6:
7:
0x11
0x44
FIR A Filter
Output
ADC
When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-fS/2 option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
Output data and clock rate control register.
0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate
adjustment is not needed.
The Half-Band Filter A/B includes decimation of 2.
0x0E takes into account the stages 1 and 2 are bypassed. See Figure 4-15 for “dual-channel Input” for DDC.
DS20005322C-page 62
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-17:
OUTPUT TYPE VS. CONTROL PARAMETERS FOR DUAL-CHANNEL DDC EXAMPLE
Output Type
Complex: I and Q
Real: RealA for
Channel A
and RealB for
Channel B after
NCO(fS/8/DER)
Without Using
Decimation Filter
Decimated Real:
RealA_DEC for
Channel A and
RealB_DEC for
Channel B after
NCO(fS/8/DER) and
Decimation Filter
Note 1:
2:
3:
Control Parameter
Register
Descriptions
EN_DSPP_2 = 1
0X79
Enable all digital post-processing functions for dual-channel
operations
EN_DDC1 = 1
0X80
Enable DDC1 block
EN_NCO = 1
0X80
Enable 32-bit NCO
HBFILTER_A = 1
0X80
Enable Half-Band Filter A, includes 2x decimation
HBFILTER_B = 1
0X80
Enable Half-Band Filter B, includes 2x decimation
EN_DDC_FS/8 = 0
0X80
NCO(fS/8/DER) is disabled
EN_DDC2 = 0
0X81
DDC2 is disabled
FIR_A<8:1> = 0x00
0X7B
FIR A decimation filter is disabled
FIR_B<7:0> = 0x00
0X7C
FIR B decimation filter is disabled
OUT_CLKRATE<3:0>
0X02
Output clock rate is not affected (no need to change)
EN_DSPP_2 = 1
0X79
Enable all digital post-processing functions for dual-channel
operations
EN_DDC1 = 1
0X80
Enable DDC1 block
EN_NCO = 1
0X80
Enable 32-bit NCO
HBFILTER_A = 1
0X80
Enable Half-Band Filter A, includes 2x decimation
HBFILTER_B = 1
0X80
Enable Half-Band Filter B, includes 2x decimation
EN_DDC_FS/8 = 1
0X80
NCO(fS/8/DER) is enabled. This translates the input signal
from DC to fS/8(1)
EN_DDC2 = 1
0X81
DDC2 is enabled
FIR_A<8:1> = 0x00
0X7B
Decimation filter FIR A is disabled
FIR_B<7:0> = 0x00
0X7C
Decimation filter FIR B is disabled
OUT_CLKRATE<3:0>
= 0001
0X02
Adjust the output clock rate to divided by 2(2)
EN_DSPP_2 = 1
0X79
Enable all digital signal post-processing functions for dualchannel operation
EN_DDC1 = 1
0X80
Enable DDC1 block
EN_NCO = 1
0X80
Enable 32-bit NCO
HBFILTER_A = 1
0X80
Enable Half-Band Filter A, includes 2x decimation
HBFILTER_B = 1
0X80
Enable Half-Band Filter B, includes 2x decimation
EN_DDC_FS/8 = 1
0X80
NCO(fS/8/DER) is enabled. This translates the input signal
from DC to fS/8/DER(1)
EN_DDC2 = 1
0X81
DDC2 is enabled
FIR_A<8:1>
0X7B
Program FIR A filter for extra decimation(3)
FIR_B<7:0>
0X7C
Program FIR B filter for extra decimation(3)
OUT_CLKRATE<3:0>
0X02
Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
DER is the decimation rate setting of the FIR A and FIR B filters.
Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).
 2014-2015 Microchip Technology Inc.
DS20005322C-page 63
MCP37231/21-200 AND MCP37D31/21-200
4.9
Digital Offset and Digital Gain
Settings
4.9.2
Figure 4-21 shows a simplified block diagram of the
digital offset and gain settings. Offset is applied prior to
the gain. Offset and gain adjustments occur prior to
DDC, Decimation or FDR when these features are
used.
4.9.1
DIGITAL GAIN SETTINGS
CH(N)_DIG_GAIN<7:0> in Addresses 0x96 – 0x9D
(Registers 5-62 – 5-69) is used to adjust the digital gain
per channel.
Note 1: Digital Offset Setting: Register mapping
(0x9E – 0xA7) to the corresponding
channel is not sequential to the channel
order defined by CH_ORDER<23:0>,
except for the octal-channel mode. See
Table 4-18 for details.
DIGITAL OFFSET SETTINGS
The offset can be corrected using a 16-bit-wide global
offset correction register (0x66) for all channels, offset
correction registers for individual channels (0x9E0xA7) or by combining both global and individual offset
correction registers. The offset control for individual
channels can be used with DIG_OFFSET_WEIGHT
<1:0> in 0xA7. The corresponding registers for each
correction are shown in Figure 4-21.
2: Gain and NCO Phase Offset: Register
mapping to the corresponding channel is
sequential to the channel order defined
by CH_ORDER<23:0>.
Note that, except for the octal-channel mode, the offset
setting registers for individual channels, 0x9E-0xA7
(Registers 5-70 – 5-78),
do
not
sequentially
correspond to the channel order defined by
CH_ORDER<23:0>. Table 4-18 shows the details of
the offset registers that correspond to the actual
channels, depending on the number of channels used.
Corrected
ADC Output
ADC
Output
Global Digital Offset Control
for all channels
Digital Offset Control
for individual channel
DIG_OFFSET_GLOBAL<15:0>
Digital Gain Control
for individual channel
CH(n)_DIG_GAIN<7:0>
CH(n)_DIG_OFFSET<7:0>
(See Address 0x66)
(See Addresses 0x96 – 0x9D)
(See Addresses 0x9E – 0xA5)
DIG_OFFSET_WEIGHT<1:0>
(See Address 0xA7)
FIGURE 4-21:
Number of
Channel Used
TABLE 4-18:
Simplified Block Diagram for Digital Offset and Gain Settings.
REGISTER ASSIGNMENT FOR OFFSET SETTING
Register Address for Offset Setting
1st Channel 2nd Channel 3rd Channel
4th Channel
5th Channel 6th Channel 7th Channel 8th Channel
1
0x9F
─
─
─
─
─
─
─
2
0xA0
0x9F
─
─
─
─
─
─
3
0xA1
0x9F
0xA0
─
─
─
─
─
4
0xA2
0x9F
0xA0
0xA1
─
─
─
─
5
0xA3
0x9F
0xA0
0xA1
0xA2
─
─
─
6
0xA4
0x9F
0xA0
0xA1
0xA2
0xA3
─
─
7
0xA5
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
─
8
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
DS20005322C-page 64
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.10
Continuous Wave (CW)
Beamforming and Ultrasound
Doppler Signal Processing Using
CW Octal-Channel Mode
(MCP37D31/21-200 only)
In modern ultrasound medical applications, large numbers of transducers are often used. The signals from
these sensors are then coherently combined for higher
transducer gain and directivity. The signals from each
sensor arrive at the detection device with a different
time delay. Also, in multi-channel scanning operations
using the MUX, there is a time delay between acquiring
input signals (see Section 4.8.1 “Fractional Delay
Recovery for Dual- and Octal-Channel Modes”).
These time delays may need to be corrected before all
input signals are combined for the signal processing.
Digital beamforming is a digital signal processing
technique that requires summing all input signals from
different channels after correcting for time delay. The
time-delay correction involves the phase alignment of
the detected signals with respect to a reference.
HV
Amp
DAC
Along with beamforming, many modern medical
ultrasound devices support Doppler imaging, which
processes phase information in addition to the classical
magnitude detection (for brightness imaging).
Ultrasound Doppler signal processing is used to
determine movement in the body as represented by
blood flow, which can help diagnose the functioning of
a heart valve or blood vessel, etc. In a traditional
ultrasound system, all of these functions are typically
accomplished with discrete components. Figure 4-23
shows an example of an ultrasound system
implementation using various specialized components.
The MCP37D31/21-200 device has a built-in feature
that can perform some of the functions that are done
traditionally using extra components. Continuous wave
(CW) digital beamforming and Doppler signal
processing features are available, but these are offered
in octal-channel operation only.
Figure 4-22 shows a simplified block diagram for the
ultrasound CW beamforming with DDC I/Q decimation.
Note that the sub-blocks shown after the MUX are
commonly used for all input channels.
Beamformer Central
Control Processor
Isolation
LNA-VGA-ADC Array (up to 256 Channels)
AAF
HV MUX and
T/R Switches
T/R
Switcher
ADC
VGA
LNA
Digital RX Beamformer
Clocks
Transducer
Array
Amp
ADC
I/Q
Processing
Amp
ADC
CW
Doppler
Processing
Image and
Motion
Processing
(B Mode)
Color
Doppler
Processing
(F Mode)
Video DAC/
Video Encoder
Amp/
Filter
Audio
DAC
FIGURE 4-22:
Video
Compression
Amp
Example of Ultrasound System Building Block.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 65
MCP37231/21-200 AND MCP37D31/21-200
4.10.1
BEAMFORMING
Beamforming is achieved by scanning all inputs while
correcting the phase of each channel with respect to a
reference. This can be done using:
• Fractional Delay Recovery (FDR)
• Phase offset settings of each individual channel
• Gain setting per channel
While the CW input channel is multiplexed sequentially,
the phase offset can be added to the NCO output (each
channel individually). CH(n)_NCO_PHASE<15:0>, in
Addresses 0x86 to 0x95 (Registers 5-46 – 5-61),
corrects the time delay of the incoming signals with
respect to the reference.
The phase-compensated input signal is then downconverted by a wide dynamic range I/Q demodulator.
The digital beamforming of the inputs is then obtained
by summing I and Q data from individual channels. The
combined I and Q data toals are fed to the half-band
filter. Equation 4-8 shows the I and Q data of an
individual channel with phase correction (phase offset),
and the resulting digital beamforming signal.
The processing blocks after the digital beamforming
are the same as the sub-blocks used in single-channel
operation described in Section 4.8.3.1 “SingleChannel DDC”, except only limited decimation rates of
the FIR A and FIR B filters are used due to the
processing time requirement for summing the input
signals from all channels.
EQUATION 4-8:
BEAMFORMING SIGNALS
I CH  n  = ADC  COS  2  f NCO t +   n  
Q CH  n  = ADC  SIN  2  f NCO t +   n  
N
I =
 ICH  n 
4.10.2
ULTRASOUND DOPPLER SIGNAL
PROCESSING
Doppler shift measurement requires summing the input
signals from multiple transducer channels and mixing
them with a phase-controlled local oscillator frequency.
The resulting low-frequency output is then centered
near DC and can measure a Doppler shift produced by
moving objects, such as blood flow and changes in
blood pressure in arteries, etc. In traditional Doppler
measurement, many discrete analog components are
typically used along with a high-resolution ADC
(~18-bit range).
This device has unique built-in features that are suitable
for ultrasound Doppler shift measurements. By utilizing
these features, system engineers can reduce many
discrete components which are otherwise necessary for
an ultrasound Doppler measurement system.
The following built-in digital signal post-processing
(DSPP) features in the MCP37D31/21-200 can be
effectively used for the ultrasound Doppler signal processing applications:
• Fractional Delay Recovery (FDR): Correct the
time delay of signal sampled between channels.
See details in Section 4.8.1 “Fractional Delay
Recovery for Dual- and Octal-Channel
Modes”.
• Digital Gain and Offset adjustment for each
channel: See details in Section 4.9 “Digital
Offset and Digital Gain Settings”.
• Down-Conversion for each channel with a unique
phase of the same NCO frequency prior to summing
the eight channels as shown in Figure 4-23.
• After down-conversion by the DDC, the resulting
signal can then be decimated to achieve very high
SNR in a narrow bandwidth.
n=0
N
Q =
 QCH  n 
n=0
CH(n)_NCO_PHASE<15:0>
  n  = 360   ---------------------------------------------------------------------16
2
= 0.005493164   CH(n)_NCO_PHASE<15:0>
Where:
(n) = NCO phase offset of channel n
ADC = the output of the ADC block
The NCO phase offset can be controlled by
0.005493164° per step. See Section 4.8.3.6 “NCO
Phase Offset Control” for details.
DS20005322C-page 66
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
I
I or IDEC
Q or QDEC
(Note 1)
MUX
HBFILTER_A
ICH(n)
ADC
Data:
Half-Band Filter A
CH. 0
COS
QCH(n)
SIN
NCO Amplitude Dither
CH. 2
NCO (
fS/8
DER
)
EN_DDC_FS/8
FIR_B<7:0>
Real
or
RealDEC
EN_DDC2
EN_AMPDITH
EN_LFSR
Decimation and Output Frequency Translation
Sine/Cosine
Signal Generator
NCO Phase Dither
CH. 7
FIR A
Decimation Filter
FIR B
Decimation Filter
LP/HP
CH. 1
FIR_A<8:1>
EN_PHSDITH
EN_LFSR
NCO Phase Offset Control
NCO (32-bit)
CH(n) NCO_PHASE<15:0>
EN_NCO
NCO_TUNE<31:0>
EN_DDC1
Channel Multiplexing/Down-Converting/Digital Beamforming/Decimation (2x)
Note 1:
2:
(2)
Switches are closed if a decimation filter is not used, and open if a decimation filter is used.
Digital Gain and Offset adjustments are applied prior to the Digital Down-Converter and
are not shown here.
FIGURE 4-23:
Simplified Block Diagram of CW Beamforming and I/Q Signal Processing - Available
in MCP37D31/21-200 Only.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 67
MCP37231/21-200 AND MCP37D31/21-200
4.11
Output Data format
Table 4-19 shows the relationship between the analog
input voltage, the digital data output bits and the
overrange bit. By default, the output data format is
two’s complement.
The device can output the ADC data in offset binary or
two’s complement. The data format is selected by the
DATA_FORMAT bit in Address 0x62 (Register 5-20).
TABLE 4-19:
ADC OUTPUT CODE VS. INPUT VOLTAGE (16-BIT MODE)
Input Range
Offset Binary(1)
Two’s Complement(1)
Overrange (OVR)
AIN > AFS
1111-1111-1111-1111
0111-1111-1111-1111
1
AIN = AFS
1111-1111-1111-1111
0111-1111-1111-1111
0
AIN = AFS – 1 LSb
1111-1111-1111-1110
0111-1111-1111-1110
0
AIN = AFS – 2 LSb
1111-1111-1111-1100
0111-1111-1111-1100
0
•
•
AIN = AFS/2
1100-0000-0000-0000
0100-0000-0000-0000
0
AIN = 0
1000-0000-0000-0000
0000-0000-0000-0000
0
AIN = -AFS/2
0011-1111-1111-1111
1011-1111-1111-1111
0
•
•
AIN = -AFS + 2 LSb
0000-0000-0000-0010
1000-0000-0000-0010
0
AIN = -AFS + 1 LSb
0000-0000-0000-0001
1000-0000-0000-0001
0
AIN = -AFS
0000-0000-0000-0000
1000-0000-0000-0000
0
AIN < -AFS
0000-0000-0000-0000
1000-0000-0000-0000
1
Note 1:
4.12
MSb is sign bit
Digital Output
The device can operate in one of the following three
digital output modes:
• Full-Rate CMOS
• Double-Data-Rate (DDR) LVDS
• Serialized DDR LVDS: Available in octal-channel
with 16-bit mode only)
The outputs are powered by DVDD18 and GND. LVDS
mode is recommended for data rates above 80 Msps.
The digital output mode is selected by the
OUTPUT_MODE<1:0> bits in Address 0x62
(Register 5-20). Figures 2-1 – 2-6 show the timing
diagrams of the digital output.
4.12.1
FULL RATE CMOS MODE
In full-rate CMOS mode, the data outputs (Q15 to Q0,
DM1 and DM2), overrange indicator (OVR), word
clock (WCK) and the data output clock (DCLK+,
DCLK–) have CMOS output levels. The digital output
should drive minimal capacitive loads. If the load
capacitance is larger than 10 pF, a digital buffer should
be used.
DS20005322C-page 68
4.12.2
DOUBLE DATA RATE LVDS MODE
In double-data-rate LVDS mode, the output is a parallel
data stream which changes on each edge of the output
clock. See Figure 2-2 for details.
• Even-bit first option: Available for all resolution
options including 18-bit option. See Figure 2-2 for
details.
• MSb-first option: Available for the 16-bit option only.
See Figure 2-3 for details.
In multi-channel configuration, the data is output
sequentially with the WCK that is synchronized to the
first sampled channel.
The device outputs the following LVDS output pairs:
• Output Data:
- 16-/18-bit mode: Q7+/Q7- through Q0+/Q0- DM+/DM- (18-bit mode only)
- 14-bit mode: Q6+/Q6- through Q0+/Q0• OVR/WCK
• DCLK+/DCLKA 100Ω differential termination resistor is required for
each LVDS output pin pair. The termination resistor
should be located as close as possible to the LVDS
receiver. By default, the outputs are standard LVDS
levels: 3.5 mA output current with a 1.15V output common-mode voltage on a 100 differential load. See
Address 0x63 (Register 5-21) for more details of the
LVDS mode control.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Note:
Output Data Rate in LVDS Mode: In octalchannel mode, the input sample rate per
channel is fS/8. Therefore, the output data
rate required to shift out all 16 bits in DDR is
still equivalent to fS. For example, if fS =
200 Msps, each channel’s sample rate is
fS/8 = 25 Msps, and the output clock rate
(DCLK) for 16-bit DDR output is 200 MHz.
multiplexed with the OVR bit. See Address 0x07
(Register 5-5) and Address 0x68 (Register 5-26) for
OVR and WCK control options.
4.12.6
LVDS OUTPUT POLARITY
CONTROL
In LVDS mode, the output polarity can be controlled
independently for each LVDS pair. Table 4-20
summarizes the LVDS output polarity control register bits.
TABLE 4-20:
4.12.3
SERIALIZED LVDS MODE
This output mode is only available for octal-channel
operation with 16-bit data output, and uses eight output
lanes: a single LVDS pair for each channel output as
shown in Figure 2-6.
LVDS OUTPUT POLARITY
CONTROL
Control
Parameter
Register
POL_LVDS<7:0>
0x65
Control polarity of LVDS
data pairs
POL_WCK_OVR
0x68
Control polarity of WCK
and OVR bit pair
POL_DM1DM2
0x68
Control polarity of DM+
and DM- pair
Descriptions
Each channel’s data is serialized by the data serializer,
and the outputs are available through eight LVDS
output lanes. Each differential LVDS output pair holds
a single input channel's data, and clocks out data with
double data rate (DDR), which is synchronized with
WCK/OVR bit:
4.12.7
• Q7+/Q7- pair: 1st channel selected
• Q6+/Q6- pair: 2nd channel selected
•
•
• Q0+/Q0- pair: last channel selected
In LVDS mode, the default output driver current is
3.5 mA. This current can be adjusted by using the
LVDS_IMODE<2:0> bit setting in Address 0x63
(Register 5-21). Available output drive currents are
1.8 mA, 3.5 mA, 5.4 mA and 7.2 mA.
4.12.4
OVERRANGE BIT (OVR)
The input overrange status bit is asserted (logic high)
when the analog input has exceeded the full-scale
range of the ADC in either the positive or negative
direction. In LVDS DDR Output mode, the OVR bit is
multiplexed with the word clock (WCK) output bit such
that OVR is output on the falling edge of the data output
clock and WCK on the rising edge.
The OVR bit has the same pipeline latency as the
ADC data bits. In multi-channel mode, the OVR is output independently for each input channel and is synchronized to the data. In serialized LVDS mode (for
16-bit octal channel), the MSb is asserted coincident
with the WCK rising edge. OVR will be asserted if any
of the channels are overranged, but it does not specify
which channel is overranged. See Address 0x68
(Register 5-26) for OVR and WCK control options.
If DSPP options are enabled, OVR pipeline latency will
be unaffected; however, the data will incur additional
delay. This has the effect of allowing the OVR indicator
to precede the affected data.
4.12.5
WORD CLOCK (WCK)
The word clock output bit indicates the start of a new
data set. In single-channel mode, this bit is disabled
except for I/Q output mode. In DDR output with multichannel mode, it is always asserted coincidentally with
the data from the first sampled channel, and
 2014-2015 Microchip Technology Inc.
4.12.8
PROGRAMMABLE LVDS OUTPUT
OPTIONAL LVDS DRIVER
INTERNAL TERMINATION
In most cases, using an external 100Ω termination
resistor will give excellent LVDS signal integrity. In
addition, an optional internal 100Ω termination resistor
can be enabled by setting the LVDS_LOAD bit in
Address 0x63 (Register 5-21). The internal termination
helps absorb any reflections caused by imperfect
impedance termination at the receiver.
4.12.9
OUTPUT DATA AND CLOCK RATES
The user can reduce output data and output clock rates
using Address 0x02 (Register 5-3). When decimation
or digital down-conversion (DDC) is used, the output
data rate has to be reduced to synchronize with the
reduced output clock rate.
4.12.10
PHASE SHIFTING OF OUTPUT
CLOCK (DCLK)
In full-rate CMOS mode, the data output bit transition
occurs at the rising edge of DCLK+, so the falling edge
of DCLK+ can be used to latch the output data.
In double-data-rate LVDS mode, the data transition
occurs at both the rising and falling edges of DCLK+.
For adequate setup and hold time when latching the
data into the external host device, the user can shift the
phase of the digital clock output (DCLK+/DCLK-)
relative to the data output bits.
DS20005322C-page 69
MCP37231/21-200 AND MCP37D31/21-200
The output phase shift (delay) is controlled by each
unique register depending on which timing source is
used or if decimation is used. Table 4-21 shows the
output clock phase control registers for each configuration mode: (a) when DLL is used, (b) when decimation
is used, and (c) when PLL is used.
TABLE 4-21:
Figure 4-24 shows an example of the output clock
phase delay control using the DCLK_PHDLY_DLL<2:0> when DLL is used.
OUTPUT CLOCK (DCLK) PHASE CONTROL PARAMETERS
Control Parameter
Register
Operating Condition(1)
When DLL is used:
EN_PHDLY
0x64
EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DLL<2:0>
0x52
DCLK phase delay control when DLL is used. Decimation is not used.
EN_PHDLY
0x64
EN_PHDLY = 1: Enable output clock phase delay control
When decimation is used:
DCLK_PHDLY_DEC<2:0>
DCLK phase delay control when decimation filter is used. The phase delay
is controlled in digital clock output control block.
When PLL is used:
DCLK_DLY_PLL<2:0>
Note 1:
0x6D
DCLK delay control when PLL is used.
See Figure 4-11 for details.
LVDS Data Output:
Phase Shift:
0° (Default)
Output Clock
(DCLK+)
(1)
DCLK_PHDLY_DLL<2:0>
=
0
0
0
45° + Default
0
0
1
90° + Default
0
1
0
135° + Default
0
1
1
180° + Default
1
0
0
225° + Default
1
0
1
270° + Default
1
1
0
315° + Default
1
1
1
Note 1: Default value may not be 0° in all operations.
FIGURE 4-24:
DS20005322C-page 70
Example of Phase Shifting of Digital Output Clock (DCLK+) when DLL is used.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.12.11
DIGITAL OUTPUT RANDOMIZER
Depending on PCB layout considerations and power
supply coupling, SFDR may be improved by decorrelating the ADC input from the ADC digital output data. The
device includes an output data randomizer option.
When this option is enabled, the digital output is randomized by applying an exclusive-OR logic operation
between the LSb (D0) and all other data output bits.
To decode the randomized data, the reverse operation
is applied: an exclusive-OR operation is applied
between the LSb (D0) and all other bits. The DCLK,
OVR, WCK, DM1, DM2 and LSb (D0) outputs are not
affected. Figure 4-25 shows the block diagram of the
data randomizer and decoder logic. The output randomizer is enabled by setting the EN_OUT_RANDOM
bit in Address 0x07 (Register 5-5).
MCP37XXX
DCLK
OVR
WCK
Data Acquisition Device
DCLK
OVR
DCLK
OVR
WCK
Q15
Q15
Q0
Q14
Q14
Q0
WCK
Q15
Q14
Q2
Q2
Q0
Q1
Q1
Q0
Q2
Q1
EN_OUT_RANDOM
Q0
Q0
(a) Data Randomizer
FIGURE 4-25:
4.12.12
Q0
(b) Data Decoder
Logic Diagram for Digital Output Randomizer and Decoder (16-bit mode).
OUTPUT DISABLE
The digital output can be disabled by setting
OUTPUT_MODE<1:0> = 00 in Address 0x62
(Register 5-20). All digital outputs are disabled,
including OVR, WCK, DCLK, etc.
4.12.13
OUTPUT TEST PATTERNS
To facilitate testing of the I/O interface, the device can
produce various predefined or user-defined patterns on
the digital outputs. See TEST_PATTERNS<2:0> in
Address 0x62 (Register 5-20) for the predefined test
patterns. For the user-defined patterns, Addresses
0x74 – 0x77
(Registers 5-29 – 5-32)
can
be
programmed using the SPI interface. When an output
test mode is enabled, the ADC’s analog section can still
be operational, but does not drive the digital outputs. The
outputs are driven only with the selected test pattern.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 71
MCP37231/21-200 AND MCP37D31/21-200
4.12.13.1
Pseudo-random Number (PN)
Sequence Output
When TEST_PATTERNS<2:0> = 111, the device outputs a pseudo-random number (PN) sequence which is
defined by the polynomial of degree 16, as shown in
Equation 4-9. Figure 4-26 shows the block diagram of
a 16-bit Linear Feedback Shift Register (LFSR) for the
PN sequence.
EQUATION 4-9:
POLYNOMIAL FOR PN
4
13
15
Px= 1 + x + x + x + x
16
• 16-Bit Mode:
The output PN[15:0] is directly applied to the output pins
Qn[15:0]. In addition to the output at the Qn[15:0] pins, the
two MSbs, PN[15] and PN[14], are copied to OVR and
WCK pins, respectively. The two LSbs, PN[1] and PN[0],
are also copied to DM1 and DM2 pins, respectively.
• 14-Bit Mode:
The output PN[15:2] is directly applied to the output
pins Qn[13:0]. In addition to the output at the Qn[13:0]
pins, the two MSbs, PN[15] and PN[14], are copied to
OVR and WCK pins, respectively.
In CMOS output mode, the pattern is always applied to
all CMOS I/O pins, regardless whether or not they are
enabled. In LVDS output mode, the pattern is only
applied to the LVDS pairs that are enabled.
PN[3]
Z-4
PN[12]
Z-9
PN[14]
Z-2
PN[15]
Z-1
XOR
FIGURE 4-26:
Block Diagram of 16-bit LFSR
for Pseudo-Random Number (PN) Sequence for
Output Test Pattern.
4.13
System Calibration
The built-in system calibration algorithm includes:
• Harmonic Distortion Correction (HDC)
• DAC Noise Cancellation (DNC)
• Dynamic Element Matching (DEM)
HDC and DNC correct the nonlinearity in the residue
amplifier and DAC, respectively. The system
calibration is performed by:
• Power-up calibration, which takes place during
the Power-on Reset sequence (requires 227 clock
cycles)
• Background calibration, which takes place during
normal operation (per 230 clock cycles).
Background calibration time is invisible to the user,
and primarily affects the ADC's ability to track
variations in ambient temperature.
The calibration status is monitored by the CAL pin or
the ADC_CAL_STAT bit in Address 0xC0 (Register 579). See Address 0x07 (Register 5-5) and 0x1E
(Register 5-6) for time delay control of the autocalibration. Table 4-22 shows the calibration time for
various ADC core sample rates.
TABLE 4-22:
CALIBRATION TIME VS. ADC
CORE SAMPLE RATE
fS (Msps)
200
150
100
70
50
Power-Up
Calibration Time (s)
0.67
0.9
1.34
1.92
2.68
Background
Calibration Time (s)
5.37
7.16 10.73 15.34 21.48
4.13.1
RESET COMMAND
Although the background calibration will track changes
in temperature or supply voltage, changes in clock
frequency or register configuration should be followed
by a recalibration of the ADC. This can be accomplished
via either the Hard or Soft Reset command. The
recalibration time is the same as the power-up
calibration time (227 clock cycles). Resetting the device
is highly recommended when exiting from Shutdown or
Standby mode after an extended amount of time. During
the reset, the device has the following state:
• No ADC output
• No change in power-on condition of internal
reference
• Most of the internal clocks are not distributed
• Contents of internal user registers:
- Not affected by Soft Reset
- Reset to default values by Hardware Reset
• Current consumption of the digital section is
negligible, but no change in the analog section.
DS20005322C-page 72
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
4.13.1.1
Hardware Reset
A hard reset is triggered by toggling the RESET pin. On
the rising edge, all internal calibration registers and
user registers are initialized to their default states and
recalibration of the ADC begins. The recalibration time
is the same as the power-up calibration time. See
Figure 2-8 for the timing details of the hardware
RESET pin.
4.13.1.2
Soft Reset
The user can issue a Soft Reset command for a fast
recalibration of the ADC by setting the SOFT_RESET
bit to ‘0’ in Address 0x00 (Register 5-1). During Soft
Reset, all internal calibration registers are initialized to
their initial default states. User registers are unaffected.
When exiting the Soft Reset (changing from ‘0’ to ‘1’),
an automatic device calibration takes place.
4.14
Power Dissipation and Power
Savings
The power dissipation of the ADC core is proportional
to the sample rate (fS). The digital power dissipation of
the CMOS outputs are determined primarily by the
strength of the digital drivers and the load condition on
each output pin. The maximum digital load current
(ILOAD) can be calculated as:
EQUATION 4-10:
4.14.1
POWER-SAVING MODES
This device has two power-saving modes:
• Shutdown
• Standby
They are set by the SHUTDOWN and STANDBY bits in
Address 0x00 (Register 5-1).
In Shutdown mode, most of the internal circuitry,
including the reference and clock, are turned off with
the exception of the SPI interface. During Shutdown,
the device consumes 25 mA (typical), primarily due to
digital leakage. When exiting from Shutdown, issuing a
Soft Reset at the same time is highly recommended.
This will perform a fast recalibration of the ADC. The
contents of the internal registers are not affected by the
Soft Reset.
In Standby mode, most of the internal circuitry is
disabled except for the reference, clock and SPI
interface. If the device has been in standby for an
extended period of time, the current calibration value
may not be accurate. Therefore, when exiting from
Standby mode, executing the device Soft Reset at the
same time is highly recommended.
CMOS OUTPUT LOAD
CURRENT
I LOAD = DV DD1.8  f DCLK  N  C LOAD
Where:
N = Number of bits
CLOAD = Capacitive load of output pin
The capacitive load presented at the output pins needs
to be minimized to minimize digital power consumption.
The output load current of the LVDS output is constant,
since it is set by LVDS_IMODE<2:0> in Address 0x63
(Register 5-21).
 2014-2015 Microchip Technology Inc.
DS20005322C-page 73
MCP37231/21-200 AND MCP37D31/21-200
NOTES:
DS20005322C-page 74
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
5.0
SERIAL PERIPHERAL
INTERFACE (SPI)
The user can configure the ADC for specific functions
or optimized performance by setting the device’s
internal registers through the serial peripheral interface
(SPI). The SPI communication uses three pins: CS,
SCLK and SDIO. Table 5-1 summarizes the SPI pin
functions. The SCLK is used as a serial timing clock
and can be used up to 50 MHz. SDIO (Serial Data
Input/Output) is a dual-purpose pin that allows data to
be sent or read from the internal registers. The Chip
Select pin (CS) enables SPI communication when
active-low. The falling edge of CS followed by a rising
edge of SCLK determines the start of the SPI
communication. When CS is tied to high, SPI
communication is disabled and the SPI pins are placed
in high-impedance mode. The internal registers are
accessible by their address.
Figures 5-1 and 5-2 show the SPI data communication
protocols for this device with MSb-first and LSb-first
options, respectively. It consists of:
TABLE 5-1:
Pin
Name
Descriptions
CS
Chip Select pin. SPI mode is initiated at
the falling edge. It needs to maintain
active-low for the entire period of the
SPI communication. The device exits the
SPI communication at the rising edge.
SCLK
Serial clock input pin.
• Writing to the device: Data is latched
at the rising edge of SCLK
• Reading from the device: Data is
latched at the falling edge of SCLK
SDIO
Serial data input/output pin. This pin is
initially an input pin (SDI) during the first
16-bit instruction header. After the
instruction header, its I/O status can be
changed depending on the R/W bit:
• if R/W = 0: Data input pin (SDI) for
writing
• if R/W = 1: Data output pin (SDO) for
reading
• 16-bit wide instruction header + Data byte 1 +
Data byte 2 + . . . + Data Byte N
Table 5-2 summarizes the bit functions. The R/W bit of
the instruction header indicates whether the command
is a read (‘1’) or a write (‘0’):
• If the R/W bit is ‘1’, the SDIO pin changes
direction from an input (SDI) to an output (SDO)
after the 16-bit wide instruction header.
By selecting the R/W bit, the user can write the register
or read back the register contents. The W1 and W2 bits
in the instruction header indicate the number of data
bytes to transmit or receive in the following data frame.
Bits A2 – A0 are the SPI device address bits. These
bits are used when multiple devices are used in the
same SPI bus. A2 is internally hardcoded to ‘0’. Bits A1
and A0 correspond to the logic level of the ADR1 and
ADR0 pins, respectively.
Note:
In the VTLA-124 package, ADR1 is
internally bonded to ground (logic ‘0’).
The R9 – R0 bits represent the starting address of the
configuration register to write or read. The data bytes
following the instruction header are the register data.
All register data is eight bits wide. Data can be sent in
MSb-first mode (default) or in LSb-first mode, which is
determined by the <LSb_ FIRST> bit setting in Address
0x00 (Register 5-1). In Write mode, the data is clocked
in at the rising edge of the SCLK. In the Read mode, the
data is clocked out at the falling edge of the SCLK.
 2014-2015 Microchip Technology Inc.
SPI PIN FUNCTIONS
TABLE 5-2:
SPI DATA PROTOCOL BIT
FUNCTIONS
Bit Name
Descriptions
R/W
1 = Read Mode
0 = Write Mode
W1, W0
(Data
Length)
00 = Data for one register (1 byte)
01 = Data for two registers (2 bytes)
10 = Data for three registers (3 bytes)
11 = Continuous reading or writing by
clocking SCLK(1)
A2 - A0
Device SPI Address for multiple
devices in SPI bus
A2: Internally hardcoded to ‘0’
A1: Logic level of ADR1 pin
A0: Logic level of ADR0 pin
R9 - R0
Address of starting register
D7 - D0
Note 1:
Register data. MSb or LSb first,
depending on the LSb_FIRST bit
setting in 0x00
The register address counter is incremented
by one per step. The counter does not
automatically reset to 0x00 after reaching the
last address (0x15D). Be aware that the user
registers are not sequentially allocated.
DS20005322C-page 75
MCP37231/21-200 AND MCP37D31/21-200
CS
SCLK
SDIO
R/W W1 W0 A2 A1 A0 R9 R8 R7 R6 R5 R4 R3
Device Address
R2 R1 R0
D7 D6 D5 D4 D3 D2 D1 D0
Address of
Starting Register
D7 D6 D5 D4 D3
D2 D1 D0
Register Data 2
Register Data of
starting register
defined by R9 - R0
16-Bit Instruction Header
D2 D1 D0
Register Data N
Register Data
FIGURE 5-1:
SPI Serial Data Communication Protocol with MSb-first. See Figures 2-5 and 2-6 for
Timing Specifications.
CS
SCLK
SDIO
R0
R1 R2
R3 R4 R5 R6 R7 R8 R9 A0
A1 A2 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0
Address of
Starting Register
D1 D2 D3 D4 D5 D6 D7
Register Data 2
Device Address
16-Bit Instruction Header
D5 D6 D7
Register Data N
Register Data of
starting register
defined by R9 - R0
Register Data
FIGURE 5-2:
SPI Serial Data Communication Protocol - with LSb-First. See Figures 2-5 and 2-6 for
Timing Specifications.
5.1
Register Initialization
The internal configuration registers are initialized to
their default values under two different conditions:
• After 220 clock cycles of delay from the power-on
reset (POR).
• Resetting the hardware reset pin (RESET).
Note 1: All address and bit locations that are not
included in the following register map
table should not be written or modified by
the user.
2: Some registers include factory-controlled
bits (FCB). Do not overwrite these bits.
Figures 2-5 and 2-6 show the timing details.
5.2
Configuration Registers
The internal registers are mapped from Addresses
0x00 – 0x15D. These user registers are not
sequentially located. Some user configuration registers
include factory-controlled bits. The factory-controlled
bits should not be overwritten by the user.
All user configuration registers are read/write, except
for the last four registers, which are read-only. Each
register is made of an 8-bit-wide volatile memory, and
their default values are loaded during the power-up
sequence or by using the hardware RESET pin. All
registers are accessible by the SPI command using the
register address. Table 5-3 shows the user-register
memory map, and Registers 5-1 – 5-82 show the
details of the register bit functions.
DS20005322C-page 76
 2014-2015 Microchip Technology Inc.
REGISTER MAP TABLE
Bits
Addr.
Register Name
b7
0x00
SPI Bit Ordering and ADC
Mode Selection
SHUTDOWN
1 = Shutdown
0x01
No. of Channel Selection and
Independency Control of
Output Data and Clock Divider
0x02
Output Data and
Clock Rate Control
0x04
SPI SDO Timing Control
SDO_TIME
0x07
Output Randomizer
and WCK Polarity Control
POL_WCK
0x1E
Auto-Calibration
Time Delay Control
0x52
DLL Control
0x53
Clock Source Selection
0x54
PLL Reference Divider
0x55
PLL Output and
Reference Divider
0x56
PLL Prescaler (LSb)
0x57
PLL Prescaler (MSb)
EN_DATCLK_IND
b6
b5
LSb-FIRST
b4
STANDBY
SOFT_RESET
1 = LSb first
0 = MSb first
0 = Soft Reset
FCB<3> = 0
b3
b2
STANDBY
1 = Standby
1 = Standby
b1
SOFT_RESET
0=Soft Reset
b0
LSb-FIRST
1 = LSb first
0 = MSb first
SEL_NCH<2:0>
SHUTDOWN
0x0F
OUT_CLKRATE<3:0>
0x00
FCB<6:0> = 0011111
EN_AUTOCAL_
TIMEDLY
0x9F
FCB<4:0> = 10001
EN_OUT_
RANDOM
AUTOCAL_TIMEDLY<7:0>
EN_DUTY
DCLK_PHDLY_DLL<2:0>
FCB<6:4>= 010
0x62
0x80
EN_DLL_DCLK
EN_DLL
CLK_SOURCE
EN_CLK
RESET_DLL
FCB<3:0>= 0101
0x0A
0x45
PLL_REFDIV<7:0>
PLL_OUTDIV<3:0>
0x24
1 = Shutdown
FCB<2:0> = 111
OUT_DATARATE<3:0>
Default
Value
0x00
FCB<1:0> = 10
PLL_REFDIV<9:8>
PLL_PRE (LSB)<7:0>
0x48
0x78
FCB<3:0> = 0100
PLL_PRE (MSB)<11:8>
0x40
0x58
PLL Charge Pump
0x59
PLL Enable Control 1
U
FCB<4:3> = 10
0x5A
PLL Loop Filter Resistor
U
FCB<1:0> = 01
PLL_RES<4:0>
0x2F
FCB<2:0> = 000
PLL_BIAS
PLL_CHAGPUMP<3:0>
EN_PLL_REFDIV
FCB<2:1> = 00
EN_PLL
0x12
FCB<0> = 1
0x41
DS20005322C-page 77
0x5B
PLL Loop Filter Cap3
U
FCB<1:0> = 01
PLL_CAP3<4:0>
0x27
0x5C
PLL Loop Filter Cap1
U
FCB<1:0> = 01
PLL_CAP1<4:0>
0x27
0x5D
PLL Loop Filter Cap2
U
FCB<1:0> = 01
PLL_CAP2<4:0>
0x5F
PLL Enable Control 2
0x62
Output Data Format and
Output Test Pattern
0x63
ADC Output Bits
(Resolution) and LVDS
Output Load
0x64
Output Clock Phase
Control when Decimation
Filter is used
0x65
LVDS Output Polarity Control
Legend:
2:
FCB<5:2> = 1111
U
LVDS_8CH
EN_PLL_OUT
DATA_FORMAT
OUTPUT_MODE<1:0>
OUTPUT_BIT<3:0>
EN_PHDLY
U = Unimplemented bit, read as ‘0’
FCB = Factory-Controlled bits. Do not program
Read-only register. Preprogrammed at the factory for internal use.
FCB<1:0> = 01
0x10
LVDS_IMODE<2:0>
0x01
FCB<3:0> = 0011
POL_LVDS<7:0>
1 = bit is set
0 = bit is cleared
0xF1
TEST_PATTERNS<2:0>
LVDS_LOAD
DCLK_PHDLY_DEC<2:0>
0x27
EN_PLL_BIAS
0x03
0x00
x = bit is unknown
MCP37231/21-200 AND MCP37D31/21-200
 2014-2015 Microchip Technology Inc.
TABLE 5-3:
REGISTER MAP TABLE (CONTINUED)
Bits
Addr.
Register Name
b7
b6
b5
b4
b3
b2
b1
b0
Default
Value
0x66
Digital Offset
Correction - Lower Byte
DIG_OFFSET_GLOBAL<7:0>
0x00
0x67
Digital Offset
Correction - Upper Byte
DIG_OFFSET_GLOBAL<15:8>
0x00
0x68
WCK/OVR and DM1/DM2
0x6B
PLL Calibration
FCB<3:0> = 0010
POL_WCK_OVR
0x6D
PLL Output and Output Clock
Phase
0x74
User-Defined Output
Pattern A - Lower Byte
PATTERN A<7:0>
0x00
0x75
User-Defined Output
Pattern A - Upper Byte
PATTERN A<15:8>
0x00
0x76
User-Defined Output
Pattern B - Lower Byte
PATTERN B<7:0>
0x00
0x77
User-Defined Output
Pattern B - Upper Byte
PATTERN B<15:8>
0x00
FCB<6:2> = 00001
U<1:0>
0x79
Dual-Channel DSPP Control
EN_DSPP_2
0x7A
FDR and FIR_A0
FCB<5> = 0
0x7B
FIR A Filter
EN_PLL_CLK
EN_WCK_OVR
PLL_CAL_TRIG
FCB<1> = 0
DM1DM2
POL_DM1DM2
FCB<1:0> = 00
DCLK_DLY_PLL<2:0>
FCB<0> = 0
FCB<6:0> = 000 0000
FIR_A<0>
EN_FDR
0x24
0x08
0x00
0x00
FCB<4:0> = 00000
0x00
FIR_A<8:1>
0x00
 2014-2015 Microchip Technology Inc.
0x7C
FIR B Filter
FIR_B<7:0>
0x00
0x7D
Auto-Scan Channel Order Lower Byte
CH_ORDER<7:0>
0x78
0x7E
Auto-Scan Channel Order Middle Byte
CH_ORDER<15:8>
0xAC
0x7F
Auto-Scan Channel Order Upper Byte
CH_ORDER<23:16>
0x8E
0x80
Digital Down-Converter
Control 1
HBFILTER_B
HBFILTER_A
EN_NCO
EN_AMPDITH
EN_PHSDITH
EN_LFSR
0x81
Digital Down-Converter
Control 2
FDR_BAND
EN_DDC2
GAIN_HBF_DDC
SEL_FDR
EN_DSPP_8
8CH_CW
0x82
Numerically Controlled
Oscillator (NCO) Tuning Lower Byte
NCO_TUNE<7:0>
0x00
0x83
Numerically Controlled
Oscillator (NCO) Tuning Middle Lower Byte
NCO_TUNE<15:8>
0x00
0x84
Numerically Controlled
Oscillator (NCO) Tuning Middle Upper Byte
NCO_TUNE<23:16>
0x00
Legend:
2:
U = Unimplemented bit, read as ‘0’
FCB = Factory-Controlled bits. Do not program
Read-only register. Preprogrammed at the factory for internal use.
1 = bit is set
0 = bit is cleared
x = bit is unknown
EN_DDC_FS/8
EN_DDC1
GAIN_8CH<1:0>
0x00
0x00
MCP37231/21-200 AND MCP37D31/21-200
DS20005322C-paage 78
TABLE 5-3:
REGISTER MAP TABLE (CONTINUED)
Bits
Addr.
Register Name
b7
0x85
Numerically Controlled
Oscillator (NCO) Tuning Upper Byte
0x86
b6
b5
b4
b3
b2
b1
b0
Default
Value
DS20005322C-page 79
NCO_TUNE<31:24>
0x00
CH0 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH0_NCO_PHASE<7:0>
0x00
0x87
CH0 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH0_NCO_PHASE<15:8>
0x00
0x88
CH1 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH1_NCO_PHASE<7:0>
0x00
0x89
CH1 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH1_NCO_PHASE<15:8>
0x00
0x8A
CH2 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH2_NCO_PHASE<7:0>
0x00
0x8B
CH2 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH2_NCO_PHASE<15:8>
0x00
0x8C
CH3 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH3_NCO_PHASE<7:0>
0x00
0x8D
CH3 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH3_NCO_PHASE<15:8>
0x00
0x8E
CH4 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH4_NCO_PHASE<7:0>
0x00
0x8F
CH4 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH4_NCO_PHASE<15:8>
0x00
0x90
CH5 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH5_NCO_PHASE<7:0>
0x00
0x91
CH5 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH5_NCO_PHASE<15:8>
0x00
0x92
CH6 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH6_NCO_PHASE<7:0>
0x00
0x93
CH6 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH6_NCO_PHASE<15:8>
0x00
0x94
CH7 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH7_NCO_PHASE<7:0>
0x00
0x95
CH7 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH7_NCO_PHASE<15:8>
0x00
0x96
CH0 Digital Gain
CH0_DIG_GAIN<7:0>
0x3C
0x97
CH1 Digital Gain
CH1_DIG_GAIN<7:0>
0x3C
0x98
CH2 Digital Gain
CH2_DIG_GAIN<7:0>
0x3C
0x99
CH3 Digital Gain
CH3_DIG_GAIN<7:0>
Legend:
2:
U = Unimplemented bit, read as ‘0’
FCB = Factory-Controlled bits. Do not program
Read-only register. Preprogrammed at the factory for internal use.
1 = bit is set
0 = bit is cleared
0x3C
x = bit is unknown
MCP37231/21-200 AND MCP37D31/21-200
 2014-2015 Microchip Technology Inc.
TABLE 5-3:
REGISTER MAP TABLE (CONTINUED)
Bits
Addr.
Register Name
b7
b6
b5
b4
b3
b2
b1
b0
Default
Value
0x9A
CH4 Digital Gain
CH4_DIG_GAIN<7:0>
0x3C
0x9B
CH5 Digital Gain
CH5_DIG_GAIN<7:0>
0x3C
0x9C
CH6 Digital Gain
CH6_DIG_GAIN<7:0>
0x3C
0x9D
CH7 Digital Gain
CH7_DIG_GAIN<7:0>
0x3C
0x9E
CH0 Digital Offset
CH0_DIG_OFFSET<7:0>
0x00
0x9F
CH1 Digital Offset
CH1_DIG_OFFSET<7:0>
0x00
0xA0
CH2 Digital Offset
CH2_DIG_OFFSET<7:0>
0x00
0xA1
CH3 Digital Offset
CH3_DIG_OFFSET<7:0>
0x00
0xA2
CH4 Digital Offset
CH4_DIG_OFFSET<7:0>
0x00
0xA3
CH5 Digital Offset
CH5_DIG_OFFSET<7:0>
0x00
0xA4
CH6 Digital Offset
CH6_DIG_OFFSET<7:0>
0x00
0xA5
CH7 Digital Offset
CH7_DIG_OFFSET<7:0>
0xA7
Digital Offset Weight Control
0xC0
Calibration Status
Indication (Read only)
0xD1
PLL Calibration Status
and PLL Drift Status Indication
(Read only)
0x15C
CHIP ID - Lower Byte(2)
(Read only)
CHIP_ID<7:0>
─
0x15D
CHIP ID - Upper Byte(2)
(Read only)
CHIP_ID<15:8>
─
Legend:
2:
FCB<5:3> = 010
ADC_CAL_STAT
FCB<4:3> = xx
0x00
DIG_OFFSET_WEIGHT<1:0>
FCB<2:0> = 111
0x47
FCB<6:0> = 000-0000
PLL_CAL_STAT
U = Unimplemented bit, read as ‘0’
FCB = Factory-Controlled bits. Do not program
Read-only register. Preprogrammed at the factory for internal use.
FCB<2:1> = xx
1 = bit is set
0 = bit is cleared
─
PLL_VCOL_STAT
x = bit is unknown
PLL_VCOH_STAT
FCB<0> = x
─
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322C-paage 80
TABLE 5-3:
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-1:
ADDRESS 0X00 – SPI BIT ORDERING AND ADC MODE SELECTION(1)
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
SHUTDOWN
LSb_FIRST
SOFT_RESET
STANDBY
STANDBY
SOFT_RESET
LSb_FIRST
SHUTDOWN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SHUTDOWN: Shutdown mode setting for power-saving(2)
1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
bit 6
LSb_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 5
SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 4
STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 3
STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 2
SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 1
LSb_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 0
SHUTDOWN: Shutdown mode setting for power-saving(2)
1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
Note
1:
2:
3:
4:
x = Bit is unknown
Upper and lower nibble are mirrored, which makes the MSb- or LSb-first mode interchangeable. The lower nibble (bit <3:0>)
has a higher priority when the mirrored bits have different values.
During Shutdown mode, most of the internal circuits including the reference and clock are turned-off except for the SPI
interface. When exiting from Shutdown (changing from ‘1’ to ‘0’), executing the device Soft Reset simultaneously is highly
recommended for a fast recalibration of the ADC. The internal user registers are not affected.
This bit forces the device into Soft Reset mode, which initializes the internal calibration registers to their initial default states.
The user-registers are not affected. When exiting Soft Reset mode (changing from ‘0’ to ‘1’), the device performs an automatic
device calibration including PLL calibration if PLL is enabled. DLL is reset if enabled. During Soft Reset, the device has the
following states:
- no ADC output
- no change in power-on condition of internal reference
- most of the internal clocks are not distributed
- power consumption: (a) digital section - negligible, (b) analog section - no change
During Standby mode, most of the internal circuits are turned off except for the reference, clock and SPI interface. When exiting
from Standby mode (changing from ‘1’ to ‘0’) after an extended amount of time, executing Soft Reset simultaneously is highly
recommended. The internal user registers are not affected.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 81
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-2:
ADDRESS 0X01 – NUMBER OF CHANNELS, INDEPENDENCY CONTROL OF OUTPUT
DATA AND CLOCK DIVIDER
R/W-0
R/W-0
EN_DATCLK_IND
FCB<3>
R/W-0
R/W-0
R/W-1
R/W-1
SEL_NCH<2:0>
R/W-1
R/W-1
FCB<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EN_DATCLK_IND: Enable data and clock divider independently(1)
1 = Enabled
0 = Disabled (Default)
bit 6
FCB<3>: Factory-Controlled bit. This is not for the user. Do not change default setting.
bit 5-3
SEL_NCH<2:0>: Select the total number of input channels to be used(2)
111 = 7 inputs
110 = 6 inputs
101 = 5 inputs
100 = 4 inputs
011 = 3 inputs
010 = 2 inputs
001 = 1 input (Default)
000 = 8 inputs
bit 2-0
Note
FCB<2:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
1:
2:
EN_DATCLK_IND = 1 enables OUT_CLKRATE<3:0> settings in Address 0x02 (Register 5-3).
See Addresses 0x7D – 0x7F (Registers 5-37 – 5-39) for selecting the input channel order.
DS20005322C-page 82
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-3:
R/W-0
ADDRESS 0X02 – OUTPUT DATA AND CLOCK RATE CONTROL(1)
R/W-0
R/W-0
R/W-0
R/W-0
OUT_DATARATE<3:0>
R/W-0
R/W-0
R/W-0
OUT_CLKRATE<3:0>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
OUT_DATARATE<3:0>: Output data rate control bits
1111 = Output data is all 0’s
1110 = Output data is all 0’s
1101 = Output data is all 0’s
1100 = Internal test only(2)
1011 = Internal test only(2)
1010 = Internal test only(2)
1001 = Full speed divided by 512
1000 = Full speed divided by 256
0111 = Full speed divided by 128
0110 = Full speed divided by 64
0101 = Full speed divided by 32
0100 = Full speed divided by 16
0011 = Full speed divided by 8
0010 = Full speed divided by 4
0001 = Full speed divided by 2
0000 = Full-speed rate (Default)
bit 3-0
OUT_CLKRATE<3:0>: Output clock rate control bits(3,4)
1111 = Full-speed rate
1110 = No clock output
1101 = No clock output
1100 = No clock output
1011 = No clock output
1010 = No clock output
1001 = Full speed divided by 512
1000 = Full speed divided by 256
0111 = Full speed divided by 128
0110 = Full speed divided by 64
0101 = Full speed divided by 32
0100 = Full speed divided by 16
0011 = Full speed divided by 8
0010 = Full speed divided by 4
0001 = Full speed divided by 2
0000 = No clock output (Default)
Note
1:
2:
3:
4:
x = Bit is unknown
This register should be used to realign the output data and clock when the decimation or digital down-conversion (DDC) option
is used.
1100 - 1010: Do not reprogram. These settings are used for the internal test only. If these bits are reprogrammed with different settings, the outputs will be in an undefined state.
Bits <3:0> become active if EN_DATCLK_IND = 1 in Address 0x01 (Register 5-2).
When no clock output is selected (Bits 1110 - 1010): clock output is not available at the DCLK+/DCLK- pins.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 83
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-4:
ADDRESS 0X04 – SPI SDO OUTPUT TIMING CONTROL
R/W-1
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FCB<6:0>
SDO_TIME
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SDO_TIME: SPI SDO output timing control bit
1 = SDO output at the falling edge of clock (Default)
0 = SDO output at the rising edge of clock
bit 6-0
FCB<6:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-5:
ADDRESS 0X07 – OUTPUT RANDOMIZER AND WCK POLARITY CONTROL
R/W-0
R/W-1
POL_WCK
EN_AUTOCAL_TIMEDLY
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
FCB<4:0>
R/W-0
EN_OUT_RANDOM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
POL_WCK: WCK polarity control bit(1)
1 = Inverted
0 = Not inverted (Default)
bit 6
EN_AUTOCAL_TIMEDLY: Auto-calibration starter time delay counter control bit(2)
1 = Enabled (Default)
0 = Disabled
bit 5-1
FCB<4:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 0
EN_OUT_RANDOM: Output randomizer control bit
1 = Enabled: ADC data output is randomized
0 = Disabled (Default)
Note
1:
2:
See Address 0x68 (Register 5-26) for WCK/OVR pair control.
This bit enables the AUTOCAL_TIMEDLY<7:0> settings. See Address 0x1E (Register 5-6).
DS20005322C-page 84
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
ADDRESS 0X1E – AUTOCAL TIME DELAY CONTROL(1)
REGISTER 5-6:
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AUTOCAL_TIMEDLY<7:0>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note
x = Bit is unknown
AUTOCAL_TIMEDLY<7:0>: Auto-calibration start time delay control bits
1111-1111 = Maximum value
•••
1000-0000 = (Default)
•••
0000-0000 = Minimum value
1:
EN_AUTOCAL_TIMEDLY in Address 0x07 (Register 5-5) enables this register setting. This register controls the time delay
before the auto-calibration starts. The value increases linearly with the bit settings, from minimum to maximum values.
REGISTER 5-7:
R/W-0
ADDRESS 0X52 – DLL CONTROL
R/W-0
EN_DUTY
R/W-0
R/W-0
DCLK_PHDLY_DLL<2:0>
R/W-1
R/W-0
R/W-1
R/W-0
EN_DLL_DCLK
EN_DLL
EN_CLK
RESET_DLL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EN_DUTY: Enable DLL circuit for duty cycle correction (DCC) of input clock
1 = Correction is ON
0 = Correction is OFF (Default)
bit 6-4
DCLK_PHDLY_DLL<2:0>: Select the phase delay of the digital clock output when using DLL(1)
111 = +315° phase-shifted from default
110 = +270° phase-shifted from default
101 = +225° phase-shifted from default
100 = +180° phase-shifted from default
011 = +135 phase-shifted from default
010 = +90° phase-shifted from default
001 = +45° phase-shifted from default
000 = (Default)
bit 3
EN_DLL_DCLK: Enable DLL digital clock output
1 = Enabled (Default)
0 = Disabled: DLL digital clock is turned off. ADC output is not available when DLL is used.
bit 2
EN_DLL: Enable DLL circuitry to provide a selectable phase clock to digital output clock.
1 = Enabled
0 = Disabled. DLL block is disabled (Default)
bit 1
EN_CLK: Enable clock input buffer
1 = Enabled (Default).
0 = Disabled. No clock is available to the internal circuits, ADC output is not available.
bit 0
RESET_DLL: DLL circuit reset control(2)
1 = DLL is active
0 = DLL circuit is held in reset (Default)
Note
1:
2:
These bits have an effect only if EN_PHDLY = 1 and decimation is not used.
DLL reset control procedure: Set this bit to ‘0’ (reset) and then to ‘1’.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 85
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-8:
R/W-0
ADDRESS 0X53 – CLOCK SOURCE SELECTION
R/W-1
R/W-0
FCB<6:4>
R/W-0
R/W-0
R/W-1
CLK_SOURCE
R/W-0
R/W-1
FCB<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
FCB<6:4>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4
CLK_SOURCE: Select internal timing source
1 = PLL output is selected as timing source
0 = External clock input is selected as timing source (Default)
bit 3-0
FCB<3:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-9:
R/W-0
ADDRESS 0X54 – PLL REFERENCE DIVIDER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLL_REFDIV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PLL_REFDIV<7:0>: PLL Reference clock divider control bits(1)
1111-1111 = PLL reference divided by 255 (if PLL_REFDIV<9:8> = 00)
1111-1110 = PLL reference divided by 254 (if PLL_REFDIV<9:8> = 00)
•••
0000-0011 = PLL reference divided by 3 (if PLL_REFDIV<9:8> = 00)
0000-0010 = Do not use (No effect)
0000-0001 = PLL reference divided by 1 (if PLL_REFDIV<9:8> = 00)
0000-0000 = PLL reference not divided (if PLL_REFDIV<9:8> = 00) (Default)
bit 7-0
Note
x = Bit is unknown
1:
PLL_REFDIV is a 10-bit wide setting. See Address 0x55 (Register 5-10) for the upper two bits and Table 5-4 for PLL_REFDIV<9:0> bit settings. This setting controls the clock division ratio of the PLL reference clock (external clock input at the CLK
pin) before the PLL phase-frequency detector circuitry. Note that the divider value of 2 is not supported. EN_PLL_REFDIV in
Address 0x59 (Register 5-14) must be set.
DS20005322C-page 86
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-10:
R/W-0
ADDRESS 0X55 – PLL OUTPUT AND REFERENCE DIVIDER
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
FCB<1:0>
PLL_OUTDIV<3:0>
R/W-0
PLL_REFDIV<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
PLL_OUTDIV<3:0>: PLL output divider control bits(1)
1111 = PLL output divided by 15
1110 = PLL output divided by 14
•••
0100 = PLL output divided by 4 (Default)
0011 = PLL output divided by 3
0010 = PLL output divided by 2
0001 = PLL output divided by 1
0000 = PLL output not divided
bit 7-4
bit 3-2
FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 1-0
PLL_REFDIV<9:8>: Upper two MSb bits of PLL_REFDIV<9:0>(2)
00 = see Table 5-4. (Default)
Note
1:
2:
PLL_OUTDIV<3:0> controls the PLL output clock divider: VCO output is divided by the PLL_OUTDIV<3:0> setting.
See Address 0x54 (Register 5-9) and Table 5-4 for PLL_REFDIV<9:0> settings. EN_PLL_REFDIV in Address 0x59
(Register 5-14) must be set.
TABLE 5-4:
EXAMPLE – PLL REFERENCE DIVIDER BIT SETTINGS VS. PLL REFERENCE INPUT
FREQUENCY
PLL_REFDIV<9:0>
PLL Reference Frequency
11-1111-1111
Reference frequency divided by 1023
11-1111-1110
Reference frequency divided by 1022
─
─
00-0000-0011
Reference frequency divided by 3
00-0000-0010
Do not use (not supported)
00-0000-0001
Reference frequency divided by 1
00-0000-0000
Reference frequency divided by 1
 2014-2015 Microchip Technology Inc.
DS20005322C-page 87
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-11:
R/W-0
ADDRESS 0X56 – PLL PRESCALER (LSB)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
PLL_PRE<7:0>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PLL_PRE<7:0>: PLL prescaler selection(1)
1111-1111 = VCO clock divided by 255 (if PLL_PRE<11:8> = 0000)
•••
0111-1000 = VCO clock divided by 120 (if PLL_PRE<11:8> = 0000) (Default)
•••
0000-0010 = VCO clock divided by 2 (if PLL_PRE<11:8> = 0000)
0000-0001 = VCO clock divided by 1 (if PLL_PRE<11:8> = 0000)
0000-0000 = VCO clock not divided (if PLL_PRE<11:8> = 0000)
bit 7-0
Note
x = Bit is unknown
1:
PLL_PRE is a 12-bit-wide setting. The upper four bits (PLL_PRE<11:8>) are defined in Address 0x57. See Table 5-5 for the
PLL_PRE<11:0> settings. The PLL Prescaler is used to divide down the VCO output clock in the PLL phase-frequency detector
loop circuit.
REGISTER 5-12:
R/W-0
ADDRESS 0X57 – PLL PRESCALER (MSB)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
FCB<3:0>
R/W-0
R/W-0
PLL_PRE<11:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
FCB<3:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 3-0
PLL_PRE<11:8>: PLL prescaler selection(1)
1111 = 212 - 1 (max), if PLL_PRE<7:0> = 0xFF
•••
0000 = Default)
Note
1:
PLL_PRE is a 12-bit-wide setting. See the lower eight bit settings (PLL_PRE<7:0>) in Address 0x56 (Register 5-11). See
Table 5-5 for the PLL_PRE<11:0> settings for PLL feedback frequency.
TABLE 5-5:
Example: PLL Prescaler Bit Settings and PLL Feedback Frequency
PLL_PRE<11:0>
PLL Feedback Frequency
1111-1111-1111
VCO clock divided by 4095 (212 - 1)
1111-1111-1110
VCO clock divided by 4094 (212 - 2)
─
─
0000-0000-0011
VCO clock divided by 3
0000-0000-0010
VCO clock divided by 2
0000-0000-0001
VCO clock divided by 1
0000-0000-0000
VCO clock divided by 1
DS20005322C-page 88
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-13:
R/W-0
ADDRESS 0X58 – PLL CHARGE-PUMP
R/W-0
R/W-0
R/W-1
FCB<2:0>:
R/W-0
R/W-0
PLL_BIAS
R/W-1
R/W-0
PLL_CHAGPUMP<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
FCB<2:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4
PLL_BIAS: PLL charge-pump bias source selection bit
1 = Self-biasing coming from AVDD (Default)
0 = Bandgap voltage from the reference generator (1.2V)
bit 3-0
PLL_CHAGPUMP<3:0>: PLL charge pump bias current control bits(1)
1111 = Maximum current
•••
0010 = (Default)
•••
0000 = Minimum current
Note
1:
PLL_CHAGPUMP<3:0> should be set based on the phase detector comparison frequency. The bias current amplitude
increases linearly with increasing the bit setting values. The increase is from approximately 25 µA to 375 µA, 25 µA per step.
See Section 4.7.2.1, "PLL Output Frequency and Output Control Parameters" for more details of the PLL block.
REGISTER 5-14:
U-0
ADDRESS 0X59 – PLL ENABLE CONTROL 1
R/W-1
—
R/W-0
FCB<4:3>
R/W-0
EN_PLL_REFDIV
R/W-0
R/W-0
FCB<2:1>
R/W-0
R/W-1
EN_PLL
FCB<0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
FCB<4:3>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4
EN_PLL_REFDIV: Enable PLL Reference Divider (PLL_REFDIV<9:0>).
1 = Enabled
0 = Reference divider is bypassed (Default)
bit 3-2
FCB<2:1>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 1
EN_PLL: Enable PLL circuit.
1 = Enabled
0 = Disabled (Default)
bit 0
FCB<0>: Factory-Controlled bit. This is not for the user. Do not change default setting.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 89
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-15:
U-0
ADDRESS 0X5A – PLL LOOP FILTER RESISTOR
R/W-0
—
R/W-1
R/W-0
R/W-1
R/W-1
FCB<1:0>
R/W-1
R/W-1
PLL_RES<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0
PLL_RES<4:0>: Resistor value selection bits for PLL loop filter(1)
11111 = Maximum value
•••
01111= (Default)
•••
00000 = Minimum value
Note
1:
PLL_RES<4:0> should be set based on the phase detector comparison frequency. The resistor value increases linearly with the
bit settings, from minimum to maximum values. See the PLL loop filter section in Section 4.7, "ADC Clock Selection".
REGISTER 5-16:
U-0
ADDRESS 0X5B – PLL LOOP FILTER CAP3
R/W-0
—
R/W-1
FCB<1:0>
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
PLL_CAP3<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0
PLL_CAP3<4:0>: Capacitor 3 value selection bits for PLL loop filter(1)
11111 = Maximum value
•••
00111= (Default)
•••
00000 = Minimum value
Note
1:
This capacitor is in series with the shunt resistor, which is set by PLL_RES<4:0>. The capacitor value increases linearly with the
bit settings, from minimum to maximum values. This setting should be set based on the phase detector comparison frequency.
DS20005322C-page 90
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-17:
U-0
ADDRESS 0X5C – PLL LOOP FILTER CAP1
R/W-0
—
R/W-1
R/W-0
R/W-0
FCB<1:0>
R/W-1
R/W-1
R/W-1
PLL_CAP1<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0
PLL_CAP1<4:0>: Capacitor 1 value selection bits for PLL loop filter(1)
11111 = Maximum value
•••
00111= (Default)
•••
00000 = Minimum value
Note
1:
This capacitor is located between the charge pump output and ground, and in parallel with the shunt resistor which is defined by
the PLL_RES<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting
should be set based on the phase detector comparison frequency.
REGISTER 5-18:
U-0
ADDRESS 0X5D – PLL LOOP FILTER CAP2
R/W-0
—
R/W-1
FCB<1:0>
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
PLL_CAP2<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0
PLL_CAP2<4:0>: Capacitor 2 value selection bits for PLL loop filter(1)
11111 = Maximum value
•••
00111= (Default)
•••
00000 = Minimum value
Note
1:
This capacitor is located between the charge pump output and ground, and in parallel with CAP1 which is defined by the PLL_CAP1<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting should
be set based on the phase detector comparison frequency.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 91
MCP37231/21-200 AND MCP37D31/21-200
ADDRESS 0X5F – PLL ENABLE CONTROL 2(1)
REGISTER 5-19:
R/W-1
R/W-1
R/W-1
FCB<5:2>
R/W-1
R/W-0
R/W-0
R/W-0
EN_PLL_OUT EN_PLL_BIAS
R/W-1
FCB<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
FCB<5:2>: Factory-Controlled bits. This is not for the user. Do not change the default settings.
bit 3
EN_PLL_OUT: Enable PLL output.
1 = Enabled
0 = Disabled (Default)
bit 2
EN_PLL_BIAS: Enable PLL bias
1 = Enabled
0 = Disabled (Default)
bit 1-0
Note
FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
1:
To enable PLL output, EN_PLL_OUT, EN_PLL_BIAS and EN_PLL in Address 0x59 (Register 5-14) must be set.
DS20005322C-page 92
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-20:
ADDRESS 0X62 – OUTPUT DATA FORMAT AND OUTPUT TEST PATTERN
U-0
R/W-0
R/W-0
—
LVDS_8CH
DATA_FORMAT
R/W-1
R/W-0
OUTPUT_MODE<1:0>
R/W-0
R/W-0
R/W-0
TEST_PATTERNS<2:0>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6
LVDS_8CH: LVDS data stream type selection for octal-channel mode(1)
1 = Serialized data stream(2)
0 = Interleaved with parallel data stream(3)(Default)
bit 5
DATA_FORMAT: Output data format selection
1 = Offset binary (unsigned)
0 = Two’s complement (Default)
bit 4-3
OUTPUT_MODE<1:0>: Output mode selection(4)
11 = DDR LVDS output mode with MSb byte first(5)
10 = DDR LVDS output mode with even bit first(6)(Default)
01 = CMOS output mode
00 = Output disabled
bit 2-0
TEST_PATTERNS<2:0>: Test output data pattern selection
111 = Output data is pseudo-random number (PN) sequence(7)
110 = Sync Pattern for LVDS output.
18-bit mode: '11111111 00000000 10'
16-bit mode: '11111111 00000000'
14-bit mode: '11111111 000000'
12-bit mode: '11111111 0000'
10-bit mode: '11111111 00'
101 = Alternating Sequence for LVDS mode
16-bit mode: ‘01010101 10101010’
14-bit mode: ‘01010101 101010’
100 = Alternating Sequence for CMOS.
Output: ‘11111111 11111111’ alternating with ‘00000000 00000000’
011 = Alternating Sequence for CMOS.
Output: ‘01010101 01010101’ alternating with ‘10101010 10101010’
010 = Ramp Pattern. Output is incremented by:
18-bit mode: 1 LSb per clock cycle
16-bit mode: 1 LSb per 4 clock cycles
14-bit mode: 1 LSb per 16 clock cycles
001 = Double Custom Patterns.
Output: Alternating custom pattern A (see Addresses 0X74 – 0X75 - Registers 5-29 – 5-30) and custom
pattern B (see Address 0X76 - 0X77 - Registers 5-31 – 5-32)(8)
000 = Normal Operation. Output: ADC data (Default)
Note
1:
2:
3:
4:
5:
6:
7:
8:
This bit setting is valid for the octal-channel mode only. See Addresses 0x7D-0x7F (Registers 5-37 – 5-39) for channel order selection.
Serialized LVDS is available in octal-channel with 16-bit mode only: Each LVDS output pair holds a single input channel's data
and outputs in a serial data stream (synchronized with WCK): Q7+/Q7- is for the first channel’s selected data, and Q0+/Q0- is for
the last channel’s selected data. This bit function is enabled only when EN_DSPP_8 = 1 in Address 0x81 (Register 5-41). See
Figure 2-4 for the timing diagram.
The output is in parallel data stream. The first sampled data bit is clocked out first in parallel LVDS output pins, followed by the
next sampled channel data bit. See Figures 2-2 and2-3 for the timing diagram.
See Figures 2-1 – 2-4 for the timing diagram.
Only 16-bit mode is available for this option.
Rising edge: Q15 - Q8.
Falling edge: Q7 - Q0
Rising edge: Q14, Q12, Q10,.... Q0.
Falling edge: Q15, Q13, Q11,... Q1.
Pseudo-random number (PN) code is generated by the linear feedback shift register (LFSR).
The alternating patterns A and B are applied to Q<15:0>. Pattern A<15:14> and Pattern B<15:14> are also applied to OVR and
WCK pins, respectively. Pattern A<1:0> and Pattern B<1:0> are also applied to DM1/DM+ and DM2/DM-.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 93
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-21:
R/W-0
ADDRESS 0X63 – ADC OUTPUT BIT (RESOLUTION) AND LVDS LOAD
R/W-0
R/W-0
R/W-0
OUTPUT_BIT
R/W-0
LVDS_LOAD
R/W-0
R/W-0
R/W-1
LVDS_IMODE<2:0>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
16-Bit Device (MCP37231/D31-200):
OUTPUT_BIT<3:0>: Select number of output data bits(1)
1111 = 15
1110 = 14
1101 = 13
1100 = 12
1011 = 11
1010 = 10
1001 = 9
1000 = 8
0111 = 7
0110 = 6
0101 = 5
0100 = 4
0011 = 3
0010 = 2
0001 = 1
0000 = 16-bit (Default)
14-Bit Device (MCP37221/D21-200):
OUTPUT_BIT<3:0>: These bits have no effect(2)
bit 3
LVDS_LOAD: Internal LVDS load termination
1 = Enable internal load termination
0 = Disable internal load termination (Default)
bit 2-0
LVDS_IMODE<2:0>: LVDS driver current control bits
111 = 7.2 mA
011 = 5.4 mA
001 = 3.5 mA (Default)
000 = 1.8 mA
Do not use the following settings(3):
110, 101, 100, 010
Note
1:
2:
3:
x = Bit is unknown
These bits are applicable for the 16-bit device only. See Address 0x68 (Register 5-26) for additional DM1 and DM2 bits.
In the 14-bit device, ADC resolution is not user selectable.
These settings can result in unknown output currents.
DS20005322C-page 94
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-22:
R/W-0
ADDRESS 0X64 – OUTPUT CLOCK PHASE CONTROL WHEN DECIMATION FILTER IS USED
R/W-0
EN_PHDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
FCB<3:0>
DCLK_PHDLY_DEC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EN_PHDLY: Enable digital output clock phase delay control when DLL or decimation filter is used.
1 = Enabled
0 = Disabled (Default)
bit 6-4
DCLK_PHDLY_DEC<2:0>: Digital output clock phase delay control when decimation filter is used(2)
111 = +315° phase-shifted from default(2)
110 = +270° phase-shifted from default
101 = +225° phase-shifted from default(2)
100 = +180° phase-shifted from default
011 = +135° phase-shifted from default(2)
010 = +90° phase-shifted from default
001 = +45° phase-shifted from default(2)
000 = Default(3)
bit 3-0
Note
FCB<3:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
1:
2:
3:
These bits have an effect only if EN_PHDLY = 1. See Address 0x52 (Register 5-7) for the same feature when DLL is used.
Only available when the decimation filter setting is greater than 2. When FIR_A/B <8:1> = 0’s (default) and FIR_A<6> = 0, only 4phase shifts are available (+45°, +135°, +225°, +315°) from default. See Addresses 0x7A, 0x7B and 0x7C (Registers 5-34 – 5-36).
See Addresses 0x6D and 0x52 (Registers 5-28 and 5-7) for DCLK phase shift for other modes.
The phase delay for all other settings is referenced to this default phase.
REGISTER 5-23:
R/W-0
ADDRESS 0X65 – LVDS OUTPUT POLARITY CONTROL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POL_LVDS<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
POL_LVDS<7:0>: Control polarity of LVDS data pairs (Q7+/Q7- – Q0+/Q0-)(1)
1111-1111 = Invert all LVDS pairs
1111-1110 = Invert all LVDS pairs except the LSb pair
•••
1000-0000 = Invert MSb LVDS pair
•••
0000-0001 = Invert LSb LVDS pair
0000-0000 = No inversion of LVDS bit pairs (Default)
bit 7-0
Note
x = Bit is unknown
1:
(a) 14-bit mode: The LSb bit has no effect. (b) 12-bit mode: The last two LSb bits have no effect.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 95
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-24:
R/W-0
ADDRESS 0X66 – DIGITAL OFFSET CORRECTION (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIG_OFFSET_GLOBAL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
DIG_OFFSET_GLOBAL<7:0>: Lower byte of DIG_OFFSET_GLOBAL<15:0> for all channels(1)
0000-0000 = Default
bit 7-0
Note
x = Bit is unknown
1:
Offset is added to the ADC output. Setting is two’s complement using two combined registers (16-bits wide).
Setting range: (-215 to 215 - 1) x step size. Step size of each bit setting:
- 12-bit mode: 0.125 LSb
- 14-bit mode: 0.25 LSb
- 16-bit mode: 0.5 LSb
- 18-bit mode: 1 LSb.
REGISTER 5-25:
R/W-0
ADDRESS 0X67 – DIGITAL OFFSET CORRECTION (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIG_OFFSET_GLOBAL<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
DIG_OFFSET_GLOBAL<15:8>: Upper byte of DIG_OFFSET_GLOBAL<15:0> for all channels(1)
0000-0000 = Default
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 in Address 0x66 (Register 5-24)
DS20005322C-page 96
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-26:
R/W-0
ADDRESS 0X68 – WCK/OVR AND DM1/DM2
R/W-0
R/W-1
FCB<3:0>
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
POL_WCK_OVR
EN_WCK_OVR
DM1DM2
POL_DM1DM2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
FCB<3:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 3
POL_WCK_OVR: Polarity control for WCK and OVR bit pair in LVDS mode
1 = Inverted
0 = Not inverted (Default)
bit 2
EN_WCK_OVR: Enable WCK and OVR output bit pair
1 = Enabled (Default)
0 = Disabled
bit 1
DM1DM2: Add two additional LSb bits (DM1/DM+ and DM2/DM- bits) to the output(1)
1 = Added
0 = Not added (Default)
bit 0
POL_DM1DM2: Polarity control for DM1/DM+ and DM2/DM- pair in LVDS mode(1)
1 = Inverted
0 = Not inverted (Default)
Note
1:
Applicable for 16-bit mode only: When this bit is set and the decimation is used, two additional LSb bits (DM1/DM+ and DM2/DM-,
DM2/DM- is the LSb) can be added and result in 18-bit resolution. See Addresses 0x7B and 0x7C (Registers 5-35 and 5-36) for the
decimation filter settings. See Address 0x63 (Register 5-21) for the output bit control.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 97
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-27:
R/W-0
R/W-0
ADDRESS 0X6B – PLL CALIBRATION
R/W-0
R/W-0
R/W-1
R/W-0
FCB<6:2>
R/W-0
PLL_CAL_TRIG
R/W-0
FCB<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
FCB<6:2>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 2
PLL_CAL_TRIG: Manually force recalibration of the PLL at the state of bit transition(1)
Toggle from “1” to “0”, or “0” to “1” = Start PLL calibration
bit 1-0
Note
FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not program.
1:
See PLL_CAL_STAT in Address 0xD1 (Register 5-80) for calibration status indication.
REGISTER 5-28:
U-0
U-0
─
ADDRESS 0X6D – PLL OUTPUT AND OUTPUT CLOCK PHASE(1)
R/W-0
R/W-0
EN_PLL_CLK
FCB<1>
R/W-0
R/W-0
R/W-0
DCLK_DLY_PLL<2:0>
R/W-0
FCB<0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Not used
bit 5
EN_PLL_CLK: Enable PLL output clock
1 = PLL output clock is enabled to the ADC core
0 = PLL clock output is disabled (Default)
bit 4
FCB<1>: Factory-Controlled bit. This is not for the user. Do not change default settings.
bit 3-1
DCLK_DLY_PLL<2:0>: Output clock is delayed by the number of VCO clock cycles from the nominal PLL output(2)
111 = Delay of 15 cycles
110 = Delay of 14 cycles
•••
001 = Delay of one cycle
000 = No delay (Default)
bit 0
FCB<0>: Factory-Controlled bit. This is not for the user. Do not change default setting.
Note 1:
2:
This register has effect only when the PLL clock is selected by the CLK_SOURCE bit in Address 0x53
(Register 5-8) and PLL circuit is enabled by EN_PLL bit in Address 0x59 (Register 5-14).
This bit setting enables the output clock phase delay. This phase delay control option is applicable when PLL is
used as the clock source and the decimation is not used.
DS20005322C-page 98
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-29:
R/W-0
ADDRESS 0X74 – USER-DEFINED OUTPUT PATTERN A (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_A<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PATTERN_A<7:0>: Lower byte of PATTERN_A<15:0>(1)
bit 7-0
Note
x = Bit is unknown
1:
See PATTERN_A<15:8> in Address 0x75 (Register 5-30) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20). If ADC
resolution is less than 16-bit, some LSbs are not used. Unused LSb = 16-n, where n = resolution. Leave the unused LSb bits as 0s.
REGISTER 5-30:
R/W-0
ADDRESS 0X75 – USER-DEFINED OUTPUT PATTERN A (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_A<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PATTERN_A<15:8>: Upper byte of PATTERN_A<15:0>(1)
bit 7-0
Note
x = Bit is unknown
1:
See PATTERN_A<7:0> in Address 0x74 (Register 5-29) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
REGISTER 5-31:
R/W-0
ADDRESS 0X76 – USER-DEFINED OUTPUT PATTERN B (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_B<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PATTERN_B<7:0>: Lower byte of PATTERN_B<15:0>(1)
bit 7-0
Note
x = Bit is unknown
1:
See PATTERN_B<15:8> in Address 0x77 (Register 5-32) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20). If ADC
resolution is less than 16-bit, some LSbs are not used. Unused LSb = 16-n, where n = resolution. Leave the unused LSb bits as 0s.
REGISTER 5-32:
R/W-0
ADDRESS 0X77 – USER-DEFINED OUTPUT PATTERN B (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_B<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PATTERN_B<15:8>: Upper byte of PATTERN_B<15:0>(1)
bit 7-0
Note
x = Bit is unknown
1:
See PATTERN_B<7:0> in Address 0x76 (Register 5-31) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
 2014-2015 Microchip Technology Inc.
DS20005322C-page 99
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-33:
ADDRESS 0X79 – DUAL-CHANNEL DIGITAL SIGNAL POST-PROCESSING CONTROL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FCB<6:0>
EN_DSPP_2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EN_DSPP_2: Enable all digital post-processing functions for dual-channel operations
1 = Enabled
0 = Disabled (Default)
bit 6-0
FCB<6:0>: Factory-controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-34:
ADDRESS 0X7A – FRACTIONAL DELAY RECOVERY AND FIR_A0(1)
R/W-0
R/W-0
R/W-0
FCB<5>
FIR_A<0>
EN_FDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FCB<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
FCB<5>: Factory-Controlled bit. This is not for the user. Do not change default setting.
bit 6
FIR_A<0>: Enable the first 2x decimation (Stage 1A in FIR A) in single-channel mode(2)
1 = Enabled
0 = Disabled (Default)
bit 5
EN_FDR: Enable fractional delay recovery (FDR) option
1 = Enabled (with delay of 59 clock cycles).
0 = Disabled (Default)
bit 4-0
FCB<4:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
Note
1:
2:
This register is used only for single and dual-channel modes.
This is the LSb for the FIR A filter settings. For the first 2x decimation, set FIR_A<0> = 1 for single-channel operation, and
FIR_A<0> = 0 for dual-channel operation. See Address 0x7B (Register 5-35) for FIR_A<8:1> settings.
DS20005322C-page 100
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-35:
R/W-0
R/W-0
ADDRESS 0X7B – FIR A FILTER(1,5)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIR_A<8:1>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
FIR_A<8:1>: Decimation Filter FIR A settings for Channel A (or I)(2)
Single-Channel Mode:(3)
FIR_A<8:0> =
1-1111-1111 = Stage 1 - 9 filters (decimation rate: 512)
0-1111-1111 = Stage 1 - 8 filters
0-0111-1111 = Stage 1 - 7 filters
0-0011-1111 = Stage 1 - 6 filters
0-0001-1111 = Stage 1 - 5 filters
0-0000-1111 = Stage 1 - 4 filters
0-0000-0111 = Stage 1 - 3 filters (decimation rate = 8)
0-0000-0011 = Stage 1 - 2 filters (decimation rate = 4)
0-0000-0001 = Stage 1 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
Dual-Channel Mode:(4)
FIR_A<8:0> =
1-1111-1110 = Stage 2 - 9 filters (decimation rate: 256)
0-1111-1110 = Stage 2 - 8 filters
0-0111-1110 = Stage 2 - 7 filters
0-0011-1110 = Stage 2 - 6 filters
0-0001-1110 = Stage 2 - 5 filters
0-0000-1110 = Stage 2 - 4 filters
0-0000-0110 = Stage 2 - 3 filters
0-0000-0010 = Stage 2 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
bit 7-0
Note
x = Bit is unknown
1:
2:
3:
4:
5:
This register is used only for single and dual-channel modes. The register values are thermometer encoded.
FIR_A<0> is placed in Address 0x7A (Register 5-34).
In single-channel mode, the 1st stage filter is selected by FIR_A<0> = 1 in Address 0x7A (Register 5-34).
In dual-channel mode, the 1st stage filter is disabled by setting FIR_A<0> = 0 in Address 0x7A.
SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation rate for the single-channel mode is 512, and 256 for the dual-channel mode.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 101
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-36:
R/W-0
R/W-0
ADDRESS 0X7C – FIR B FILTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIR_B<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
FIR_B<7:0>:Decimation Filter FIR B settings for Channel B (or Q)(3)
1111-1111 = Stage 2 - 9 filters (decimation rate = 256)
0111-1111 = Stage 2 - 8 filters
0011-1111 = Stage 2 - 7 filters
0001-1111 = Stage 2 - 6 filters
0000-1111 = Stage 2 - 5 filters
0000-0111 = Stage 2 - 4 filters
0000-0011 = Stage 2 - 3 filters
0000-0001 = Stage 2 filter (decimation rate = 2)
0000-0000 = Disabled all FIR B Filters. (Default)
bit 7-0
Note
x = Bit is unknown
1:
2:
3:
This register is used for the dual-channel mode only. The register values are thermometer encoded.
EN_DSPP_2 bit in Address 0x79 (Register 5-34) must be set when using decimation in dual-channel mode.
SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation factor for the dual-channel mode is 256.
REGISTER 5-37:
R/W-0
R/W-1
ADDRESS 0X7D – AUTO-SCAN CHANNEL ORDER (LOWER BYTE)
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
CH_ORDER<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH_ORDER<7:0>: Lower byte of CH_ORDER<31:0>(1)
0111-1000 = Default
bit 7-0
Note
x = Bit is unknown
1:
See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
REGISTER 5-38:
R/W-1
R/W-0
ADDRESS 0X7E – AUTO-SCAN CHANNEL ORDER (MIDDLE BYTE)
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
CH_ORDER<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH_ORDER<15:8>: Middle byte of CH_ORDER<31:0>(1)
1010-1100 = Default
bit 7-0
Note
x = Bit is unknown
1:
See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
DS20005322C-page 102
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-39:
R/W-1
ADDRESS 0X7F – AUTO-SCAN CHANNEL ORDER (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
CH_ORDER<23:16>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH_ORDER<23:16>: Upper byte of CH_ORDER<31:0>(1)
1000-1110 = Default
bit 7-0
Note
x = Bit is unknown
1:
See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
REGISTER 5-40:
ADDRESS 0X80 – DIGITAL DOWN-CONVETER CONTROL 1(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HBFILTER_B
HBFILTER_A
EN_NCO
EN_AMPDITH
EN_PHSDITH
EN_LFSR
EN_DDC_FS/8
EN_DDC1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
HBFILTER_B: Select half-bandwidth filter at DDC output of channel B in dual-channel mode(2)
1 = Select High-Pass filter at DDC output
0 = Select Low-Pass filter at DDC output (Default)
bit 6
HBFILTER_A: Select half-bandwidth filter at DDC output of channel A(2)
1 = Select High-Pass filter at DDC output
0 = Select Low-Pass filter at DDC output (Default)
bit 5
EN_NCO: Enable NCO of DDC1
1 = Enabled
0 = Disabled (Default)
bit 4
EN_AMPDITH: Enable amplitude dithering for NCO(3, 4)
1 = Enabled
0 = Disabled (Default)
bit 3
EN_PHSDITH: Enable phase dithering for NCO(3, 4)
1 = Enabled
0 = Disabled (Default)
bit 2
EN_LFSR: Enable linear feedback shift register (LFSR) for amplitude and phase dithering for NCO
1 = Enabled
0 = Disabled (Default)
bit 1
EN_DDC_FS/8: Enable NCO for the DDC2 to center the DDC output signal to be around fS/8/DER(5)
1 = Enabled
0 = Disabled (Default)
bit 0
EN_DDC1: Enable digital down converter 1 (DDC1)
1 = Enabled(6)
0 = Disabled (Default)
Note
1:
2:
3:
4:
5:
6:
This register is used for single-, dual- and octal-channel modes when CW feature is enabled (8CH_CW = 1).
This filter includes a decimation of 2.
-Single-channel mode: HBFILTER_A is used.
-Dual-channel mode: Both HBFILTER_A and HBFILTER_B are used.
This requires the LFSR to be enabled: EN_LFSR=1
EN_AMPDITH = 1 and EN_PHSDITH = 1 are recommended for the best performance.
DER is the decimation rate defined by FIR A or FIR B filter. If up-converter is not enabled (disabled), output is I/Q data.
DDC and NCO are enabled. For DDC function, bits 0, 2 and 5 need to be enabled all together.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 103
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-41:
ADDRESS 0X81 – DIGITAL DOWN-CONVERTER CONTROL 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FDR_BAND
EN_DDC2
GAIN_HBF_DDC
SEL_FDR
EN_DSPP_8
8CH_CW
R/W-0
R/W-0
GAIN_8CH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
FDR_BAND: Select 1st or 2nd Nyquist band
1 = 2nd Nyquist band
0 = 1st Nyquist band (Default)
bit 6
EN_DDC2: Enable DDC2 after the digital half-band filter (HBF) in DDC.
1 = Enabled
0 = Disabled (Default)
bit 5
GAIN_HBF_DDC: Gain selection for the output of the digital half-band filter (HBF) in DDC(1)
1 = x2
0 = x1 (Default)
bit 4
SEL_FDR: Select fractional delay recovery (FDR)
1 = FDR for 8-channel
0 = FDR for dual-channel (Default)
bit 3
EN_DSPP_8: Enable digital signal post-processing (DSPP) features for 8-channel operation(2)
1 = Enabled
0 = Disabled (Default)
bit 2
8CH_CW: Enable CW mode in octal-channel mode(2, 3)
1 = Enabled
0 = Disabled (Default)
bit 1-0
GAIN_8CH<1:0>: Select gain factor for CW signal in octal-channel modes.
11 = x8, 10 = x4, 01 = x2, 00 = x1 (Default)
Note
1:
2:
3:
See Section 4.8.2, "Decimation Filters".
By enabling this bit, the phase offset corrections in Addresses 0x086 – 0x095 (Registers 5-46 – 5-61) are also enabled.
EN_DSPP_8 is a global setting bit to enable SEL_FDR and LVDS_8CH bits (Address 0x62 - Register 5-20).
When CW mode is enabled, the ADC output is the result of the summation (addition) of all eight channels’ data after each
channel’s digital phase offset, digital gain, and digital offset are controlled using the Addresses 0x86 - 0xA7 (Registers 5-46 to
5-78). The result is similar to the beamforming in the phased-array sensors.
DS20005322C-page 104
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-42:
R/W-0
R/W-0
ADDRESS 0X82 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
NCO_TUNE <7:0>: Lower byte of NCO_TUNE<31:0>(1)
0000-0000 = DC (0 Hz) when NCO_TUNE<31:0> = 0x00000000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 and Note 2 in Address 0x85 (Register 5-45).
REGISTER 5-43:
R/W-0
R/W-0
ADDRESS 0X83 – NUMERICALLY CONTROLLED OSCILLATOR TUNING
(MIDDLE-LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
NCO_TUNE<15:8>: Middle lower byte of NCO_TUNE<31:0>(1)
0000-0000 = Default
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 and Note 2 in Address 0x85 (Register 5-45).
REGISTER 5-44:
R/W-0
R/W-0
ADDRESS 0X84 – NUMERICALLY CONTROLLED OSCILLATOR TUNING
(MIDDLE-UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<23:16>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
NCO_TUNE<23:16>: Middle upper byte of NCO_TUNE<31:0>(1)
0000-0000 = Default
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 and Note 2 in Address 0x85 (Register 5-45).
 2014-2015 Microchip Technology Inc.
DS20005322C-page 105
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-45:
R/W-0
R/W-0
ADDRESS 0X85 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<31:24>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
NCO_TUNE<31:24>: Upper byte of NCO_TUNE<31:0>(1,2)
1111-1111 = fS if NCO_TUNE<31:0> = 0xFFFF FFFF
•••
0000-0000 = Default
bit 7-0
Note
x = Bit is unknown
1:
2:
This Register is used only when DDC is enabled: EN_DDC1 = 1 in Address 0x80 (Register 5-40). See Section 4.8.3.3,
"Numerically Controlled Oscillator (NCO)" for the details of NCO.
NCO frequency = (NCO_TUNE<31:0>/232) x fS, where fS is the sampling clock frequency.
REGISTER 5-46:
R/W-0
R/W-0
ADDRESS 0X86 – CH0 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH0_NCO_PHASE<7:0>: Lower byte of CH0_NCO_PHASE<15:0>(1,2,3)
1111-1111 = 1.4° when CH0_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
2:
3:
This register is not used in the MCP37231/21. In the MCP37D31/D21, this register has an effect when the following modes are
used:
- CW with DDC mode in octal-channel mode
- Single and dual-channel mode with DDC.
CH0 is the 1st channel selected by CH_ORDER<23:0>.
CH(n)_NCO_PHASE<15:0> = 216 x Phase Offset Value/360.
DS20005322C-page 106
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-47:
R/W-0
R/W-0
ADDRESS 0X87: CH0 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH0_NCO_PHASE<15:8>: Upper byte of CH0_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH0_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46.
REGISTER 5-48:
R/W-0
R/W-0
ADDRESS 0X88 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH1_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH1_NCO_PHASE<7:0>: Lower byte of CH1_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH1_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-49:
R/W-0
R/W-0
ADDRESS 0X89 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH1_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH1_NCO_PHASE <15:8>: Upper byte of CH1_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH1_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 107
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-50:
R/W-0
R/W-0
ADDRESS 0X8A – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH2_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH2_NCO_PHASE<7:0>: Lower byte of CH2_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH2_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH2_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-51:
R/W-0
R/W-0
ADDRESS 0X8B – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH2_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH2_NCO_PHASE <15:8>: Upper byte of CH2_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH2_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH2_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-52:
R/W-0
R/W-0
ADDRESS 0X8C – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH3_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH3_NCO_PHASE<7:0>: Lower byte of CH3_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH3_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH3_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
DS20005322C-page 108
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-53:
R/W-0
ADDRESS 0X8D – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH3_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH3_NCO_PHASE <15:8>: Upper byte of CH3_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH3_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH3_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-54:
R/W-0
ADDRESS 0X8E – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH4_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH4_NCO_PHASE<7:0>: Lower byte of CH4_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH4_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH4_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH4 is the 5th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-55:
R/W-0
ADDRESS 0X8F – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH4_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH4_NCO_PHASE <15:8>: Upper byte of CH4_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH4_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH4_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH4 is the 5th channel selected by CH_ORDER<23:0> bits.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 109
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-56:
R/W-0
ADDRESS 0X90 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH5_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH5_NCO_PHASE<7:0>: Lower byte of CH5_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH5_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-57:
R/W-0
ADDRESS 0X91 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH5_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH5_NCO_PHASE <15:8>: Upper byte of CH5_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH5_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-58:
R/W-0
ADDRESS 0X92 – CH6 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH6_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH6_NCO_PHASE<7:0>: Lower byte of CH6_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH6_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH6_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH6 is the 7th channel selected by CH_ORDER<23:0> bits.
DS20005322C-page 110
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-59:
R/W-0
ADDRESS 0X93 – CH6 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH6_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH6_NCO_PHASE <15:8>: Upper byte of CH6_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH6_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH6_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH6 is the 7th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-60:
R/W-0
ADDRESS 0X94 – CH7 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH7_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH7_NCO_PHASE<7:0>: Lower byte of CH7_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH7_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH7_NCO_PHASE<15:0> = 0x0000 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 - Note 3 in Register 5-46. CH7 is the 8th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-61:
R/W-0
ADDRESS 0X95 – CH7 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH7_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
CH7_NCO_PHASE <15:8>: Upper byte of CH7_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH7_NCO_PHASE<15:0> = 0xFFFF
•••
0000-0000 = 0° when CH7_NCO_PHASE<15:0> = 0x0000 (Default)
See Note 1 - Note 3 in Register 5-46. CH7 is the 8th channel selected by CH_ORDER<23:0> bits.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 111
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-62:
R/W-0
R/W-0
ADDRESS 0X96 – CH0 DIGITAL GAIN
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH0_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH0_DIG_GAIN<7:0>: Digital gain setting for channel 0(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
bit 7-0
Note
x = Bit is unknown
1:
2:
CH0 is the 1st channel selected by CH_ORDER<23:0>.
Max = 0x7F(3.96875), Min = 0x80 (-4), Step size = 0x01 (0.03125). Bits from 0x81-0xFF are two’s complementary of 0x000x80. Negative gain setting inverts output. See Addresses 0x7D - 0x7F (Registers 5-37 – 5-39) for channel selection.
DS20005322C-page 112
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-63:
R/W-0
R/W-0
ADDRESS 0X97 – CH1 DIGITAL GAIN
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH1_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH1_DIG_GAIN<7:0>: Digital gain setting for channel 1(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
bit 7-0
Note
x = Bit is unknown
1:
2:
CH1 is the 2nd channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 113
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-64:
R/W-0
R/W-0
ADDRESS 0X98 – CH2 DIGITAL GAIN
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH2_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH2_DIG_GAIN<7:0>: Digital gain setting for channel 2(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
bit 7-0
Note
x = Bit is unknown
1:
2:
CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
See Note 2 in Register 5-62.
DS20005322C-page 114
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-65:
R/W-0
R/W-0
ADDRESS 0X99 – CH3 DIGITAL GAIN
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH3_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
2:
x = Bit is unknown
CH3_DIG_GAIN<7:0>: Digital gain setting for channel 3(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
See Note 2 in Register 5-62.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 115
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-66:
R/W-0
R/W-0
ADDRESS 0X9A – CH4 DIGITAL GAIN
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH4_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH4_DIG_GAIN<7:0>: Digital gain setting for channel 4(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
bit 7-0
Note
x = Bit is unknown
1:
2:
CH4 is the 5th channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
DS20005322C-page 116
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-67:
R/W-0
ADDRESS 0X9B – CH5 DIGITAL GAIN
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH5_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH5_DIG_GAIN<7:0>: Digital gain setting for channel 5(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
bit 7-0
Note
x = Bit is unknown
1:
2:
CH5 is the 6th channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 117
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-68:
R/W-0
R/W-0
ADDRESS 0X9C – CH6 DIGITAL GAIN
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH6_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH6_DIG_GAIN<7:0>: Digital gain setting for channel 6(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
bit 7-0
Note
x = Bit is unknown
1:
2:
CH6 is the 7th channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
DS20005322C-page 118
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-69:
R/W-0
ADDRESS 0X9D – CH7 DIGITAL GAIN
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH7_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH7_DIG_GAIN<7:0>: Digital gain setting for channel 7(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
bit 7-0
Note
x = Bit is unknown
1:
2:
CH7 is the 8th channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 119
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-70:
R/W-0
R/W-0
ADDRESS 0X9E – CH0 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH0_DIG_OFFSET <7:0>: Digital offset setting bits for channel 0(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Table 4-18 for the corresponding channel. Offset value is two’s complement. This value is multiplied by DIG_OFFSET_WEIGHT<1:0> in Address 0xA7 (Register 5-78).
REGISTER 5-71:
R/W-0
R/W-0
ADDRESS 0X9F – CH1 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH1_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH1_DIG_OFFSET <7:0>: Digital offset setting bits for channel 1(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 in Register 5-70.
REGISTER 5-72:
R/W-0
R/W-0
ADDRESS 0XA0 – CH2 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH2_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH2_DIG_OFFSET <7:0>: Digital offset setting bits for channel 2(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 in Register 5-70.
DS20005322C-page 120
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-73:
R/W-0
R/W-0
ADDRESS 0XA1 – CH3 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH3_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH3_DIG_OFFSET <7:0>: Digital offset setting bits for channel 3(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 in Register 5-70.
REGISTER 5-74:
R/W-0
R/W-0
ADDRESS 0XA2 – CH4 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH4_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
CH4_DIG_OFFSET <7:0>: Digital offset setting bits for channel 4(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
See Note 1 in Register 5-70.
REGISTER 5-75:
R/W-0
R/W-0
ADDRESS 0XA3 – CH5 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH5_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
CH5_DIG_OFFSET <7:0>: Digital offset setting bits for channel 5(1)
1111-1111 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
See Note 1 in Register 5-70.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 121
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-76:
R/W-0
ADDRESS 0XA4 – CH6 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH6_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH6_DIG_OFFSET <7:0>: Digital offset setting bits for channel 6(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 in Register 5-70.
REGISTER 5-77:
R/W-0
ADDRESS 0XA5 – CH7 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH7_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CH7_DIG_OFFSET <7:0>: Digital offset setting bits for channel 7(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 in Register 5-70.
REGISTER 5-78:
R/W-0
ADDRESS 0XA7 – DIGITAL OFFSET WEIGHT CONTROL
R/W-1
R/W-0
FCB<5:3>
R/W-0
R/W-0
R/W-1
DIG_OFFSET_WEIGHT<1:0>
R/W-1
R/W-1
FCB<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
FCB<5:3>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-3
DIG_OFFSET_WEIGHT<1:0>: Control the weight of the digital offset settings(1)
11 = 2 LSb x Digital Gain
10 = LSb x Digital Gain
01 = LSb/2 x Digital Gain
00 = LSb/4 x Digital Gain, (Default)
bit 2-0
FCB<2:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
Note
1:
This bit setting is used for the digital offset setting registers in Addresses 0x9E - 0xA7 (Registers 5-70 – 5-78).
DS20005322C-page 122
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-79:
R-0
ADDRESS 0XC0 – CALIBRATION STATUS INDICATION
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FCB<6:0>
ADC_CAL_STAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ADC_CAL_STAT: Power-up auto-calibration status indication flag bit
1 = Device power-up calibration is completed
0 = Device power-up calibration is not completed
bit 6-0
FCB<6:0>: Factory-Controlled bits. These bits are read only, and have no meaning for the user.
REGISTER 5-80:
R-x
R-x
FCB<4:3>
ADDRESS 0XD1 – PLL CALIBRATION STATUS AND PLL DRIFT STATUS INDICATION
R-x
PLL_CAL_STAT
R-x
R-x
FCB<2:1>
R-x
R-x
R-x
PLL_VCOL_STAT
PLL_VCOH_STAT
FCB<0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
FCB<4:3>: Factory-Controlled bits. These bits are read only, and have no meaning for the user.
bit 5
PLL_CAL_STAT: PLL auto-calibration status indication flag bit(1)
1=
Complete: PLL auto-calibration is completed
0=
Incomplete: PLL auto-calibration is not completed
bit 4-3
FCB<2:1>: Factory-Controlled bits. These bits are read only, and have no meaning for the user.
bit 2
PLL_VCOL_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with low VCO frequency
0 = PLL operates as normal
bit 1
PLL_VCOH_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with high VCO frequency
0 = PLL operates as normal
bit 0
Note 1:
FCB<0>: Factory-Controlled bit. This bit is readable, but has no meaning for the user.
See PLL_CAL_TRIG bit setting in Address 0x6B (Register 5-27).
 2014-2015 Microchip Technology Inc.
DS20005322C-page 123
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-81:
R-x
ADDRESS 0X15C – CHIP ID (LOWER BYTE)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
CHIP_ID<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CHIP_ID<7:0>: Device identification number. Lower byte of the CHIP ID<15:0>(1)
bit 7-0
Note
x = Bit is unknown
1:
Read-only register. Preprogrammed at the factory for internal use.
Example:
MCP37231-200: ‘0000 1000 0111 0000’
MCP37221-200: ‘0000 1000 0101 0000’
MCP37D31-200: ‘0000 1010 0111 0000’
MCP37D21-200: ‘0000 1010 0101 0000’
REGISTER 5-82:
R-x
ADDRESS 0X15D – CHIP ID (UPPER BYTE)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
CHIP_ID<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
CHIP_ID<15:8>: Device identification number. Lower byte of the CHIP ID<15:0>(1)
bit 7-0
Note
x = Bit is unknown
1:
See Note 1 in Register 5-81.
DS20005322C-page 124
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
6.0
DEVELOPMENT SUPPORT
Microchip offers a high-speed ADC evaluation platform
which can be used to evaluate Microchip’s high-speed
ADC products. The platform consists of an MCP37XXX
evaluation board, an FPGA-based data capture card
board, and PC-based Graphical User Interface (GUI)
software for ADC configuration and evaluation.
Figure 6-1 and Figure 6-2 show this evaluation tool.
This evaluation platform allows users to quickly
evaluate the ADC’s performance for their specific
application requirements. More information is available
at http://www.microchip.com.
(a) MCP37XXX-200 Evaluation Board
FIGURE 6-1:
MCP37XXX Evaluation Kit.
FIGURE 6-2:
PC-Based Graphical User Interface Software.
 2014-2015 Microchip Technology Inc.
(b) Data Capture Board
DS20005322C-page 125
MCP37231/21-200 AND MCP37D31/21-200
NOTES:
DS20005322C-page 126
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
7.0
TERMINOLOGY
Analog Input Bandwidth (Full-Power
Bandwidth)
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty
The sample-to-sample variation in aperture delay.
Aperture Delay Jitter
The variation in the aperture delay time from
conversion to conversion. This random variation will
result in noise when sampling an AC input. The
signal-to-noise ratio due to the jitter alone will be:
EQUATION 7-1:
SNR JITTER = – 20 log  2   f IN  t JITTER 
Calibration Algorithms
This device utilizes two patented analog and digital
calibration algorithms, Harmonic Distortion Correction
(HDC) and DAC Noise Cancellation (DNC), to improve
the ADC performance. The algorithms compensate
various sources of linear impairments such as
capacitance mismatch, charge injection error and finite
gain of operational amplifiers. These algorithms
execute in both power-up sequence (foreground) and
background mode:
• Power-Up Calibration: The calibration is
conducted within the first 227 clock cycles after
power-up. The user needs to wait this Power-Up
Calibration period after the device is powered-up
for an accurate ADC performance.
• Background Calibration: This calibration is
conducted in the background while the ADC
performs conversions. The update rate is about
every 230 clock cycles.
Pipeline Delay (LATENCY)
LATENCY is the number of clock cycles between the
initiation of conversion and when that data is presented
to the output driver stage. Data for any given sample is
available after the pipeline delay plus the output delay
after that sample is taken. New data is available at
every clock cycle, but the data lags the conversion by
the pipeline delay plus the output delay. Latency is
increased if digital signal post-processing is used.
Clock Pulse Width and Duty Cycle
The clock duty cycle is the ratio of the time the clock
signal remains at a logic high (clock pulse width) to one
clock period. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock
results in a 50% duty cycle.
Differential Nonlinearity
(DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly
1 LSb apart. DNL is the deviation from this ideal value. No
missing codes to 16-bit resolution indicates that all 65,536
codes must be present over all the operating conditions.
Integral Nonlinearity (INL)
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
EQUATION 7-2:
 PS 
SNR = 10 log  -------
 P N
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of
the fundamental is extrapolated to the converter
full-scale range.
Channel Crosstalk
This is a measure of the internal coupling of a signal
from an adjacent channel into the channel of interest in
the multi-channel mode. It is measured by applying a
full-scale input signal in the adjacent channel.
Crosstalk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest)
to the power of the signal applied at the adjacent
channel input. It is typically expressed in dBc.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 127
MCP37231/21-200 AND MCP37D31/21-200
Signal-to-Noise and Distortion (SINAD)
Maximum Conversion Rate
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
The maximum clock rate at which parametric testing is
performed.
EQUATION 7-3:
The minimum clock rate at which parametric testing is
performed.
 PS 
SINAD = 10 log  ----------------------
 P D + P N
= – 10 log 10
SNR
– ----------10
– 10
Minimum Conversion Rate
Spurious-Free Dynamic Range (SFDR)
THD
– -----------10
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Effective Number of Bits (ENOB)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 7-5:
 PS 
THD = 10 log  --------
 P D
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
EQUATION 7-4:
SINAD – 1.76
ENOB = ---------------------------------6.02
Gain Error
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Gain error is usually expressed in LSb or as a
percentage of full-scale range (%FSR).
Gain-Error Drift
Gain-error drift is the variation in gain-error due to a
change in ambient temperature, typically expressed in
ppm/°C.
Offset Error
The major carry transition should occur for an analog
value of 50% LSb below AIN+ = AIN−. Offset error is
defined as the deviation of the actual transition from that
point.
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value across the TMIN to TMAX range.
DS20005322C-page 128
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 7-6:
2
2
2
2
V2 + V3 + V4 +  + Vn
THD = – 20 log -----------------------------------------------------------------2
V1
Where:
V1 = RMS amplitude of the
fundamental frequency
V1 through Vn = Amplitudes of the second
through nth harmonics
Two-Tone Intermodulation Distortion
(Two-Tone IMD, IMD3)
Two-tone IMD is the ratio of the power of the fundamental
(at frequencies fIN1 and fIN2) to the power of the worst
spectral component at either frequency 2fIN1 – fIN2 or
2fIN2 – fIN1. Two-tone IMD is a function of the input
amplitudes and frequencies (fIN1 and fIN2). It is either
given in units of dBc (dB to carrier) when the absolute
power of the fundamental is used as the reference, or
dBFS (dB to full-scale) when the power of the
fundamental is extrapolated to the ADC full-scale range.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The common-mode signal can be
an AC or DC signal or a combination of the two. CMRR
is measured using the ratio of the differential signal
gain to the common-mode signal gain and expressed in
dB with the following equation:
EQUATION 7-7:
Where:
 A DIFF
CMRR = 20 log  ------------------
 A CM 
ADIFF = Output Code/Differential Voltage
ADIFF = Output Code/Common Mode Voltage
 2014-2015 Microchip Technology Inc.
DS20005322C-page 129
MCP37231/21-200 AND MCP37D31/21-200
NOTES:
DS20005322C-page 130
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
8.0
PACKAGING INFORMATION
8.1
Package Marking Information
124-Lead VTLA (9x9x0.9 mm)
Example
A1
A1
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
MCP37231
200-I/TL
^^
e3
1417256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 131
MCP37231/21-200 AND MCP37D31/21-200
DS20005322C-page 132
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
 2014-2015 Microchip Technology Inc.
DS20005322C-page 133
MCP37231/21-200 AND MCP37D31/21-200
124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E/2
G4
X1
X2
G3
E
T2 C2
G1
G5
X4
G2
SILK SCREEN
W3
W2
C1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Pad Clearance
G1
Pad Clearance
G2
Pad Clearance
G3
Pad Clearance
G4
Contact to Center Pad Clearance (X4)
G5
Optional Center Pad Width
T2
Optional Center Pad Length
W2
W3
Optional Center Pad Chamfer (X4)
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X124)
X1
Contact Pad Length (X124)
X2
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
0.20
0.20
0.20
0.20
0.30
6.60
6.60
0.10
8.50
8.50
0.30
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2193A
DS20005322C-page 134
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
APPENDIX A:
REVISION HISTORY
Revision C (July 2015)
• Updated some default settings for register bits
and input leakage current specification (ILI_CKLI).
Revision B (September 2014)
• Removed the non-availability notes related to the
14-bit option.
Revision A (July 2014)
• Original release of this document.
 2014-2015 Microchip Technology Inc.
DS20005322C-page 135
MCP37231/21-200 AND MCP37D31/21-200
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
[X](1)
Device
Tape and Reel
Option
-XXX
X
Sample Temperature
Rate
Range
/XX
Package
Device:
MCP37231-200: 16-Bit Low-Power ADC with 8-Channel MUX
MCP37D31-200: 16-Bit Low-Power ADC with 8-Channel MUX,
Digital Down-Converter and CW Beamforming
MCP37221-200: 14-Bit Low-Power ADC with 8-Channel MUX
MCP37D21-200: 14-Bit Low-Power ADC with 8-Channel MUX,
Digital Down-Converter and CW Beamforming
Tape and
Reel Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Sample Rate
200
= 200 Msps
Temperature
Range:
I
= -40C to +85C (Industrial)
Examples:
a)
b)
c)
MCP37D31-200I/TL: 124LD VTLA, 200 Msps
MCP37D31-200I/TE*: 121LD TFBGA, 200 Msps
MCP37231T-200I/TL: Tape and Reel,
Industrial temperature,
124LD VTLA, 200 Msps
* Contact Microchip Technology Inc. for availability.
Note 1:
Package:
TL
=
Terminal Very Thin Leadless Array Package 9x9x0.9 mm Body (VTLA), 124-Lead
TE*
= Ball Plastic Thin Profile Fine Pitch Ball Grid Array 8x8x1.08 mm Body (TFBGA), 121-Lead
* Contact Microchip Technology Inc. for availability.
DS20005322C-page 136
Tape and Reel identifier appears only in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the
Tape and Reel option.
 2014-2015 Microchip Technology Inc.
MCP37231/21-200 AND MCP37D31/21-200
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-615-0
QUALITYMANAGEMENTSYSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
 2014-2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20005322C-page 137
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
07/14/15
DS20005322C-page 138
2014-2015 Microchip Technology Inc.
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