MB 1517 A
DS04–21325–1aE
DATA SHEET
MB1517A ASSP
2.0 GHz High–Speed Tuning PLL Frequency Synthesizer
The Fujitsu MB1517A is a serial input phase-locked loop (PLL) frequency synthesizer with
a pulse-swallow function. MB1517A achieves the low noise performance as well as the
high–speed lock-up which is required for digital mobile communications.
The MB1517A can operate from a single +3 V supply. Fujitsu’s advanced technology
achieves an Icc of 12 mA (typical) as well as 100 µA (typical) at power down mode.
Plastic SSOP, 16 pin
FEATURES
•
•
•
•
•
•
•
•
•
•
High operating frequency
Pulse-swallow function
: fIN = 2.0 GHz (PIN = –10 dBm)
: High-speed two-modulus prescaler with selectable
64/65 and 128/129 divide ratios
Low supply current
: ICC = 12 mA typ. at 3 V
Power saving funtion
: IPS = 100 µA typ.
Serial input, 18-bit programmable divider consisting of:
Binary 7-bit swallow counter
: 0 to 127
Binary 11-bit programmable counter : 5 to 2,047
Serial input 17-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter: 6 to 16,383
1-bit switch counter sets prescaler divide ratio
1-bit power saving function control
1-bit LD/font switch
On-chip high performance charge pump circuit and phase comparator, achieving
high-speed lock-up and low phase noise
Two types of phase comparator outputs selectable
On-chip charge pump output
Output for an external charge pump
Wide operating temperature range: –40 to +85°C
Plastic 16–pin SSOP (shrink small outline) package
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Parameters
Supply voltage
Output voltage
Symbol
(TOP VIEW)
OSCIN
1
16
ΦR
OSCOUT
2
15
ΦP
VP
3
14
LD/fOUT
VCC
4
13
NC
DO
5
12
FC
Unit
VCC
–0.5 to +5.0
V
VP
VCC to 5.5
V
GND
6
11
LE
VO
–0.5 to VCC +0.5
V
XfIN
7
10
Data
fIN
8
9
Clock
VOOP
Output current
IO
Storage temperature
Tstg
NOTE:
PIN ASSIGNMENT
Rating
Open drain voltage
–0.5 to 6.0
V
±10
mA
–55 to +125
°C
Remark
(FPT–16P–M05)
ΦP, LD/fout
Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
(FPT–16P–M05)
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken
to avoid application of any voltage higher than maximum
rated voltages to this high impedance circuit.
1
MB1517A
BLOCK DIAGRAM
OSCIN
1
Crystal
Oscillator
circuit
OSCOUT
Programmable
reference divider
2
Binary 14-bit
reference counter
16
ΦR
15
ΦP
12
FC
14
LD
/fOUT
Phase
comparator
fR
fp
LD
Intermittent
mode control
(power save)
PS
fR
17-bit latch
FC
fR/fP
selector
17-bit latch
LE
LDS
LE
FC
LD/fout
selector
fp
11
19-bit shift register
Data
Clock
10
1-bit
control
latch
19-bit shift register
DATA
9
18-bit latch
LE
7-bit latch
11-bit latch
SW
Programmable divider
2
XfIN
7
fIN
8
GND
6
VCC
4
Prescaler
64/65,
128/129
Binary 7-bit
swallow
counter
MC
Binary 11-bit
programmable
counter
Control circuit
fp
Charge
pump
3
VP
Super
charger II
5
DO
MB1517A
PIN DESCRIPTION
Pin No. Pin name
I/O
Description
1
OSCIN
I
Programmable reference divider input
Oscillator input
Connection for external crystal or TCXO.
2
OSCOUT
O
Oscillator output
Connection for external crystal.
3
VP
–
Power supply input for the internal charge pump
4
VCC
–
Power supply
5
DO
O
Charge pump output
Phase characteristics of the charge pump can be reversed by FC input.
6
GND
–
Ground
7
Xfin
I
Complementary input of the prescaler
Xfin pin should be grounded via a capacitor.
8
fIN
I
Prescaler input
Connection with an external VCO should be done AC coupled.
9
Clock
I
Clock input for 19-bit shift register
Data is shifted into the shift register on the rising edge of the clock.
10
Data
I
Serial data input using binary code
The last bit of the data is a control bit.
When the control bit is high, data is transmitted to the 17-bit latch.
When it is low, data is transmitted to the 18-bit latch.
11
LE
I
Load enable signal input
When LE is high, the data of the shift register are transferred to a latch, according to the
control bit in the serial data.
12
FC
I
Phase switch input for phase comparator
When FC is low, the characteristics of the charge pump and phase comparator are reversed
The FC input signal is also used to control the fOUT pin (test pin) output (fR or fP).
13
NC
–
No connection
14
LD/fOUT
O
Lock detector output / Phase comparator monitoring output
This is a N-ch open drain output.
Either of the outputs is selected by LDS bit of the serial data.
a)Lock detector output : at lock state .... LD = ”H”
at unlock stae .. LD = ”L”
b)Monitoring output : Phase comparator input signals (fP, fR) can be monitored.
15
ΦP
O
Phase comparator output for an external charge pump
Phase of the output is reversed according to FC input.
ΦP pin is a N-ch open drain output.
16
ΦR
O
Phase comparator output for an external charge pump
Phase of the output is reversed depending on FC input.
3
MB1517A
FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fVCO = [(P x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (6 to 16,383)
P
: Preset divide ratio of modules prescaler (64 or 128)
Serial data input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the 17-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high, stored data is
latched according to the control data as follows:
Control data
(a)
Destination of serial data
H
17 bit latch
L
18 bit latch
Programmable reference divider ratio
The programmable reference divider consists of a 18-bit shift register, a 17-bit latch and a 14-bit reference counter. The serial
18-bit data format is shown below:
Direction of data shift
C
R
1
R
2
R
3
R
4
R
5
LD/fout select bit
(MSB)
Divide ratio setting bit for
the prescaler
Control bit(LSB)
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
SW PS LDS
Divide ratio setting bit for the programmable reference counter
Power saving control bit
4
MB1517A
•
14-bit programmable reference counter divide ratio
Divide ratio
R
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
7
0
0
0
0
0
0
0
0
0
0
0
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Divide ratio = 6 to 16,383)
Notes: 1. Divide ratios less than 6 are prohibited.
2. SW : This bit selects the divide ratio of the prescaler.
Low: 128 or 129
High: 64 or 65
3. R1 to R14: These bits select the divide ratio of the programmable reference counter (6 to 16,383).
4. C: Control bit: Set high.
5. PS: This bit controls power saving mode.
High : Nomal operation
Low : Power saving mode
6. LDS: This bit controls LD/fout output signal
High : fout signal (fR or fP) is selected and output via LD/fout pin.
Low : Lock detect signal is selected and output via LD/fout pin.
7. Start data input with MSB first .
(b)
Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, a 18-bit latch, a 7-bit swallow counter, and a 11-bit programmable
counter. The serial 19-bit data format is shown below:
Direction of data shift
Control bit
LSB
C
S
1
S
2
S
3
S
4
MSB
S
5
S
6
Divide ratio setting bit for
swallow counter
S
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
Divide ratio setting bit for programmable counter
5
MB1517A
•
•
7-bit swallow counter divide ratio
11-bit programmable counter divide ratio
Divide
ratio
A
S
7
S
6
S
5
S
4
S
3
S
2
S
1
Divide
ratio
N
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
6
0
0
0
0
0
0
0
0
1
1
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
2047
1
1
1
1
1
1
1
1
1
1
1
(Divide ratio = 0 to 127)
Notes: 1.
2.
3.
4.
5.
(Divide ratio = 5 to 2,047)
Divide ratios less than 5 are prohibited for the 11–bit programmable counter.
S1 to S7: These bits select the divide ratio of the swallow counter (0 to 127).
N1 to N11: These bits select the divide ratio of the programmable counter (5 to 2,047).
C: Control bit: (Set low)
Start data input with MSB first.
Serial data input timing
t1, t2, t3, t4 ≥ 30ns, t5, t6 ≥ 100ns, t7, t8 ≥ 200ns
Data
MSB
LSB
Clock
LE
t1
t8
t2
t3
t5
t7
t6
t4
Note:
6
One bit of data is shifted into the shift register on the rising edge of the clock.
MB1517A
Power saving mode (Intermittent operation control circuit)
Setting PS bit to Low, MB1517A enters into power saving mode resultatly current sonsumption can be limited to 100µA (typ.).
Setting PS bit to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from power saving mode. The power
consumption can be reduced by the intermittent operation that powering down or waking up parts of the PLL circuitry. If a PLL is
powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fR) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power
up, thus keeping the loop locked.
Relation between the FC input and phase characteristics
The FC pin changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the
phase comparator output (ΦR, ΦP) are reversed depending on the FC pin input level. Also, the monitor pin (fOUT) output is controlled
by the FC pin. The relationship between the FC input level and each of DO, ΦR, and ΦP is shown below:
FC = High
FC = Low
Do
ΦR
ΦP
fOUT
Do
ΦR
ΦP
fOUT
fR > fP
H
L
L
(fR)
L
H
Z(∗1)
(fP)
fR < fP
L
H
Z(∗1)
(fR)
H
L
L
(fP)
fR = fP
Z(∗1)
L
Z (∗1)
(fR)
Z(∗1)
L
Z(∗1)
(fP)
∗1: High impedance
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
1
∗: When the LPF and VCO characteristics are
similar to 1 , set FC high.
∗: When the VCO characteristics are similar to
2 , set FC low.
VCO
output
frequency
2
PLL
LPF
VCO
LPF input voltage
7
MB1517A
Phase comparator output waveforms
fr
fp
tWU
tWL
LD
[ FC = ”H” ]
ΦP
ΦR
H
Do
Z
L
[ FC = ”L” ]
ΦP
ΦR
H
Do
L
Z
Notes: 1. Phase difference detection range: –2π to +2π
2. LD output becomes low when phase error is tWU or more. LD output becomes high when phase error is
tWL or less and continues to be so for three cysles or more.
3. tWU and tWL depend on OSCin input frequency.
tWU ≥ 8/fosc (e. g. tWU ≥ 625ns, foscin = 12.8 MHz)
tWL ≤ 16/fosc (e. g. tWL ≤ 1250ns, foscin = 12.8 MHz)
8
MB1517A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Value
Typ
Max
Unit
VCC
2.7
3.0
3.6
V
Vp
Vcc
–
5.0
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Remark
Supply voltage
Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
–
Store and transport devices in conductive containers.
–
Use properly grounded workstations, tools, and equipment.
–
Turn off power before inserting or removing this device into or from a socket.
–
Protect leads with conductive sheet, when transporting a board mounted device.
9
MB1517A
ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Min
Value
Typ
Max
ICC
–
12
IPS
–
100
Symbol
Supply current
Stand by current
fIN
fIN
OSCIN
Unit
Condition
–
mA
With fIN = 2.0 GHz, OSCIN =
12 MHz, VCC = 3.0 V. In
locked state.
–
µA
PS bit = ”L”
AC coupling. The minimum
operating frequency is measured with a 1000pF capacitor connected.
1000
–
2000
MHz
fOSC
–
12
23
MHz
fIN
Pf IN
–10
–
6
dBm
OSCIN
VOSC
0.5
–
–
Vp–p
VIH
VCC x 0.7
–
–
V
VIL
–
–
VCC x 0.3
V
IIH
–
–
1.0
µA
IIL
–1.0
–
–
µA
IOSC
–100
+100
µA
VOH
2.1
–
–
V
VCC = 3 V, IOH = –1.0mA
VOL
–
–
0.4
V
Vcc = 3V, IOL = 1.0mA
IOFF
–
–
1.1
µA
VCC = 3.6V, VP = 5 .0V
VOOP = GND to 6 .0V
–1.0
–
–
mA
Vcc = 3V
–
–
1.0
mA
Vcc = 3V
Operating frequency
50Ω System
Input sensitivity
High-level input voltage
Low-level input voltage
Except fIN and
OSCIN
High-level input current
Low-level input current
Data, Clock,
LE, FC
Input current
OSCIN
High-level output voltage
10
Low-level output voltage
Except DO and
OSCOUT
High-impedance
Cut off current
DO, LD/fout,
ΦP
Output current
IOH
Except DO and
OSCOUT
IOL
MB1517A
TEST CIRCUIT
(for Measuring Input Sensitivity fin/OSCin)
VCC = VP = 3V
0.1 µ
0.1 µ
1000 p
1000 p
P·G
P·G
50 Ω
8
7
6
5
4
3
2
1
9 10 11 12 13 14 15 16
50 Ω
VCC
2kΩ
Frequency counter
Controller
(setting divide ratio)
Select fout monitor output
11
MB1517A
TYPICAL CHARACTERISTIC CURVES
Charge pump current vs. Do voltage
Charge pump current vs. Do voltage
Vcc =3.0V
Vcc =3.0V
5
5
4
Vp = 5v
VOL (V)
VOH (V)
4
3
2
3
2
Vp = 3v
1
1
0
–5
–10
–15
–20
0
–25
5
10
IOH (mA)
15
IOL (mA)
Input sensitivity vs. Input frequency
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
CATALOG–SPEC
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
Ta=+25C°
[dBm]
+10
+5
x
+0
–5
x
PIN (dBm)
–10
x
–15
x
–20
x
x
x
x
x
–25
x
–30
x
–35
–40
1000
1200
1400
1600 1800
2000
2200
2400 2600
fin(MHz)
Vcc = 2.7
MHz = x
12
3
3.6
2800
3000
3200
3400
3600
20
25
MB1517A
TYPICAL CHARACTERISTIC CURVES (Continued)
Prescaler Input Impedance
4
fIN [MHz]
3
1:
11.115
–45.209
1
2: 8.3428
–12.503
1.5
3: 9.2764
–7.1001
1.6
4: 17.173
5.8379
2
Ω
Ω
GHz
Ω
Ω
GHz
Ω
Ω
GHz
Ω
Ω
GHz
1:
Ω
Ω
MHz
Ω
kΩ
MHz
2
1
Crystal Input Impedance
2.1155
–4.4665
10
2: 426.63
–2.201
25
2
OSCIN [MHz]
1
13
MB1517A
TYPICAL APPLICATION EXAMPLE
Output
Vpx (6V)
LPF
VCO
10 k
Vcc
2kΩ
12 k
Lock det.
12 k
10 k
From
controller
3V
ΦR
16
ΦP
15
NC
LD/fout
14
13
FC
12
LE
11
Data
10
Clock
9
47k 47k 47k
MB1517A
1
2
OSCIN
3
OSCOUT
4
5
VP
VCC
3V
3V
0.1 µ
0.1 µ
X’ tal
C1
VPX
:
C1, C2 :
ΦP, LD/fout
ΦR
:
14
C2
Maximum 6 V
Depend on the crystal oscillatar
: N-ch open drain output
C-MOS output
6
DO
7
GND
8
XfIN
fIN
1000 p
1000 p
MB1517A
REFERENCE INFORMATION
Typical plots measured
with the test circuit are
shown below.
Each plot shows lock up
time, phase noise, and
reference leakage.
Test Circuit
S.G
OSC in
Do
fin
LPF
•
•
•
•
•
fvco= 1651.2 MHz
K v= 10 MHz/v
f r= 300 KHz
f osc= 19.2 MHz
LPF :
15k
1.5k
Spectrum
Analyzer
4700p
VCO
330 p
0.047µ
PLL Lock Up Time
PLL lock UP Time = 584.99597 µs
PLL Phase Noise
REF 10.0 dBm
10 dB/
ATT 10 dB
30.00150
MHz
RBW
100Hz
500
Hz/div
VBW
30 Hz
29.99900
MHz
7.6452 µs
1.4928952 µs
SPAN 20 kHz
PLL Phase Noise
REF 10.0 dBm
10 dB/
ATT 10 dB
PLL Reference Leakage
REF 10.0 dBm
10 dB/
RBW
RBW
30 Hz
10 kHz
VBW
VBW
10 Hz
30 Hz
SPAN 2.0 kHz
CENTER 1651.20 MHz
CENTER 1651.20000 MHz
ATT 10 dB
SPAN 1.0 MHz
CENTER 1651.20 MHz
15
MB1517A
ORDERING INFORMATION
Part number
MB1517APFV1
16
Package
Plastic ⋅ SSOP, 16–pin
(FPT–16P–M05)
Remarks
MB1517A
PACKAGE DIMENSION
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)
+.008
.049 –.004
+0.20
(1.25 –0.10 )
∗.197±.004
(5.00±0.10)
(MOUNTING HEIGHT)
.004(0.10)
.252±.008
(6.40±0.20)
INDEX
∗.173±.004
(4.40±0.10)
.213(5.40) NOM
”A”
.009 +.004
–.002
+0.10
(0.22
)
–0.05
.0256±.0047
(0.65±0.12)
.006 +.002 (0.15 +0.05 )
–.001
–0.02
Details of ”A” part
.004±.004
(0.10±0.10)
(STAND OFF
HEIGHT)
.179(4.55)
REF
0°to10°
.020±.008
(0.50±0.20)
∗:This dimension does not include resin protruction.
1991 FUJITSU LIMITED F16013S-2C
Dimensions in
inches (millimeters)
17
MB1517A
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical
semiconductor applications. Complete Information sufficient for construction purposes
is not necessarily given.
The Information contained in this document has been carefully checked and is believed
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The Information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
18
MB1517A
Notes
19
MB1517A
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 1015 Kamikodanaka,
Nakahara–ku, Kawasaki–shi,
Kanagawa 211, Japan
Tel: (044) 754–3753
FAX: (044) 754–3332
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134–1804, USA
Tel: (408) 922–9000
FAX: (408) 432–9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6–10
63303 Dreieich–Buchschlag,
Germany
Tel: (06103) 690–0
FAX: (06103) 690–122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06–04 to #06–07
Singapore 0718
Tel: 336–1600
FAX: 336–1609
I9505
 FUJITSU LIMITED Printed in Japan
20
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