16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential ADC in MSOP/QFN AD7693

16-Bit, ±0.5 LSB, 500 kSPS PulSAR  Differential ADC in MSOP/QFN AD7693
16-Bit, ±0.5 LSB, 500 kSPS PulSAR®
Differential ADC in MSOP/QFN
AD7693
APPLICATION DIAGRAM
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL/DNL: ±0.25 LSB typ, ±0.5 LSB max (±8 ppm of FSR)
Dynamic range: 96.5 dB
SINAD: 96 dB @ 1 kHz
THD: −120 dB @ 1 kHz
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs, selectable busy indicator
Power dissipation: 40 nJ/conversion
40 μW @ 5 V/1 kSPS
4 mW @ 5 V/100 kSPS
18 mW @ 5 V/500 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the 16-bit AD7687 and AD7688
and the 18-bit AD7690 and AD7691
+2.5V TO +5V
IN+
+5V
REF VDD VIO
SDI
AD7693
±10V, ±5V, ...
IN–
+1.8V TO VDD
3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)
SCK
SDO
GND
ADA4941-1
CNV
06394-002
FEATURES
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
18-Bit
16-Bit True
Differential
16-Bit Pseudo
Differential/
Unipolar
14-Bit
100
kSPS
250
kSPS
AD7691
AD7684
AD7687
AD7683
AD7680
AD7685
AD7694
AD7940
AD7942
400 kSPS
to
500 kSPS
AD7690
AD7688
AD7693
AD7686
ADC
Driver
ADA4941-1
ADA4841-x
ADA4941-1
ADA4841-x
ADA4841-x
AD7946
ADA4841-x
APPLICATIONS
GENERAL DESCRIPTION
Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments
The AD7693 is a 16-bit, successive approximation analog-todigital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 16-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. The reference voltage, VREF, is
applied externally and can be set up to the supply voltage, VDD.
On the CNV rising edge, it samples the voltage difference
between the IN+ and IN− pins. The voltages on these pins
swing in opposite phase between 0 V and VREF about VREF/2.
1.0
POSITIVE INL = +0.17LSB
NEGATIVE INL = –0.17LSB
0.8
0.6
Its power scales linearly with throughput.
INL (LSB)
0.4
Using the SDI input, the SPI-compatible serial interface also
features the ability to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
0.2
0
–0.2
–0.4
The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
–0.6
–1.0
0
16384
32768
49152
CODE
65536
06394-001
–0.8
Figure 1. Integral Nonlinearity vs. Code
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
AD7693
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 14
Applications....................................................................................... 1
Single-Ended-to-Differential Driver ....................................... 15
Application Diagram........................................................................ 1
Voltage Reference Input ............................................................ 15
General Description ......................................................................... 1
Power Supply............................................................................... 15
Revision History ............................................................................... 2
Supplying the ADC from the Reference.................................. 16
Specifications..................................................................................... 3
Digital Interface.......................................................................... 16
Timing Specifications....................................................................... 5
CS Mode, 3-Wire Without Busy Indicator ............................. 17
Absolute Maximum Ratings............................................................ 6
CS Mode, 3-Wire with Busy Indicator .................................... 18
ESD Caution.................................................................................. 6
CS Mode, 4-Wire Without Busy Indicator ............................. 19
Pin Configurations and Function Descriptions ........................... 7
CS Mode, 4-Wire with Busy Indicator .................................... 20
Terminology ...................................................................................... 8
Chain Mode Without Busy Indicator ...................................... 21
Typical Performance Characteristics ............................................. 9
Chain Mode with Busy Indicator ............................................. 22
Theory of Operation ...................................................................... 12
Application Hints ........................................................................... 23
Circuit Information.................................................................... 12
Layout .......................................................................................... 23
Converter Operation.................................................................. 12
Evaluating AD7693 Performance............................................. 23
Typical Connection Diagram ................................................... 13
Outline Dimensions ....................................................................... 24
Analog Inputs.............................................................................. 14
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/11—Rev. 0 to Rev. A
Changes to Resolution Parameter and Common-Mode Input
Range Parameter in Table 2............................................................. 3
Changes to Figure 6 and Table 6..................................................... 7
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
12/06—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD7693
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance 1
THROUGHPUT
Conversion Rate
Transient Response
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error 3
Gain Error Temperature Drift
Zero Error3
Zero Temperature Drift
Power Supply Sensitivity
Conditions/Comments
Min
16
IN+ − (IN−)
IN+, IN−
IN+, IN−
fIN = 250 kHz
Acquisition phase
−VREF
−0.1
VREF/2 – 0.1
Typ
VREF/2
65
1
0
Full-scale step
16
−0.5
−0.5
REF = VDD = 5 V
−20
−5
VDD = 5 V ± 5%
±0.25
±0.25
0.35
±0.5
±0.3
±0.5
±0.3
±1
Max
Unit
Bits
+VREF
VREF + 0.1
VREF/2 + 0.1
V
V
V
dB
nA
500
400
kSPS
ns
+0.5
+0.5
+20
+5
Bits
LSB 2
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
ppm
4
AC ACCURACY
Dynamic Range
Signal-to-Noise
Signal-to-(Noise + Distortion)
Total Harmonic Distortion
Spurious-Free Dynamic Range
fIN = 1 kHz
fIN = 10 kHz
fIN = 100 kHz
fIN = 1 kHz, VREF = 2.5 V
fIN = 1 kHz
fIN = 10 kHz
fIN = 100 kHz
fIN = 1 kHz
fIN = 10 kHz
fIN = 100 kHz
fIN = 1 kHz
fIN = 10 kHz
fIN = 100 kHz
96
95.5
95.5
Intermodulation Distortion 6
1
96.5
96
95.5
93
93
96
95.5
90
−120
−113
−92
120
114
93.5
115
−108
dB 5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
See the Analog Inputs section.
LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 μV.
3
See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4
With VREF = 5 V, unless otherwise noted.
5
All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
6
fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale.
2
Rev. A | Page 3 of 24
AD7693
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay 1
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 2, 3
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 4
Specified Performance
Conditions/Comments
Min
Typ
0.5
Max
Unit
VDD + 0.3
500 kSPS, REF = 5 V
100
V
μA
VDD = 5V
9
2.5
MHz
ns
−0.3
0.7 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
μA
μA
0.4
V
V
5.5
VDD + 0.3
VDD + 0.3
50
V
V
V
nA
μW
mW
mW
nJ
Serial 16 bits, twos
complement
ISINK = +500 μA
ISOURCE = −500 μA
VIO − 0.3
Specified performance
Specified performance
4. 5
2.3
1.8
VDD and VIO = 5 V, 25°C
100 SPS throughput
100 kSPS throughput
500 kSPS throughput
TMIN to TMAX
1
5
4
18
40
−40
1
Conversion results available immediately after completed conversion.
With all digital inputs forced to VIO or GND as required.
3
During acquisition phase.
4
Contact an Analog Devices sales representative for the extended temperature range.
2
Rev. A | Page 4 of 24
21.5
+85
°C
AD7693
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
1
See Figure 3 and Figure 4 for load conditions.
Rev. A | Page 5 of 24
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
400
2.0
10
15
Typ
Max
1.6
17
18
19
20
7
7
4
Unit
μs
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
ns
ns
ns
ns
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
26
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
10
4
4
AD7693
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs
IN+, 1 IN−1
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (MSOP-10)
θJC Thermal Impedance (MSOP-10)
Lead Temperature Range
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
200°C/W
44°C/W
JEDEC J-STD-20
ESD CAUTION
See the Analog Inputs section.
500µA
IOL
1.4V
TO SDO
CL
50pF
500µA
06394-003
IOH
Figure 3. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
tDELAY
2V OR VIO – 0.5V1
2V OR VIO – 0.5V1
0.8V OR 0.5V2
0.8V OR 0.5V2
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. A | Page 6 of 24
06394-004
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
AD7693
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
IN+ 3
IN– 4
GND 5
10 VIO
VDD 2
AD7693
9
SDI
TOP VIEW
(Not to Scale)
8
SCK
7
SDO
6
CNV
IN+ 3
IN– 4
GND 5
AD7693
TOP VIEW
(Not to Scale)
9
SDI
8
SCK
7
SDO
6
CNV
NOTES
1. THE EXPOSED PAD IS CONNECTED
TO GND. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL
PERFORMANCES.
06394-005
REF 1
10 VIO
05793-006
VDD 2
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Figure 5. 10-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
7
8
SDO
SCK
DO
DI
9
SDI
DI
10
VIO
P
EPAD
Description
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This
pin should be decoupled closely to the pin with a 10 μF capacitor.
Power Supply.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part: chain or CS mode. In chain mode, the data should be
read when CNV is high. In CS mode, the SDO pin is enabled when CNV is low.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this
clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC
as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.
The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV
can enable the serial output signals when low and if SDI or CNV is low when the conversion is
complete, the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
Exposed Pad. The exposed pad is connected to GND. This connection is not required to meet
the electrical performances. The exposed pad is only on the 10-Lead QFN (LFCSP).
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. A | Page 7 of 24
AD7693
TERMINOLOGY
Least Significant Bit (LSB)
The LSB is the smallest increment that can be represented by a
converter. For a differential analog-to-digital converter with N
bits of resolution, the LSB expressed in volts is
LSB (V) =
2VREF
2N
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 26).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999847 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the ±5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Rev. A | Page 8 of 24
AD7693
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = 25C.
0.8
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
0.6
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
0
16384
32768
65536
49152
POSITIVE DNL = +0.22LSB
NEGATIVE DNL = –0.22LSB
0.8
CODE
–1.0
06394-007
INL (LSB)
1.0
POSITIVE INL = +0.17LSB
NEGATIVE INL = –0.17LSB
0
16384
32768
65536
49152
CODE
06394-010
1.0
Figure 10. Differential Nonlinearity vs. Code
Figure 7. Integral Nonlinearity vs. Code
300000
160000
258774
135054
140000
250000
126066
120000
100000
COUNTS
COUNTS
200000
150000
80000
60000
100000
40000
50000
7
8
0
0
A
B
C
9
0
CODE IN HEX
SNR (dB)
–80
–100
–120
–140
A
0
0
0
B
C
D
100
–80
99
–85
98
–90
–95
SNR
96
–100
95
–105
94
–110
93
–115
–120
92
–160
–180
9
97
–60
THD
91
0
20
40
60
80
100
120
FREQUENCY (kHz)
140
160
180
200
06394-009
AMPLITUDE (dB of Full Scale)
SNR = 96.4dB
THD = –121dB
SFDR = 124dB
SINAD = 96.4dB
–40
8
Figure 11. Histogram of a DC Input at the Code Transition
fS = 500kSPS
fIN = 0.95kHz
–20
0
7
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center
0
0
06394-011
6
441
90
–10
–125
–130
–8
–6
–4
–2
INPUT LEVEL (dB)
Figure 12. SNR, THD vs. Input Level
Figure 9. FFT Plot
Rev. A | Page 9 of 24
THD (dB)
1905
0
06394-012
0
06394-008
0
20000
0
20.0
–80
99
19.5
–85
98
19.0
–90
120
97
18.5
–95
115
18.0
–100
110
–105
105
–110
100
94
17.0
93
16.5
ENOB
91
90
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–115
16.0
–120
15.5
–125
15.0
5.5
REFERENCE VOLTAGE (V)
95
THD
85
–130
2.0
2.5
99
19.5
98
19.0
5.0
80
5.5
17.5
94
17.0
93
16.5
130
125
–105
SFDR
THD (dB)
95
16.0
ENOB
4.5
VDD = 5V
ENOB (Bits)
18.0
–110
120
–115
115
THD
–120
110
–125
105
15.5
–35
–15
5
25
45
65
85
105
15.0
125
06394-014
90
–55
TEMPERATURE (°C)
–130
–55
–35
–15
5
25
45
65
85
105
100
125
06394-017
91
TEMPERATURE (°C)
Figure 14. SNR, SINAD, and ENOB vs. Temperature
Figure 17. THD, SFDR vs. Temperature
100
–80
98
–85
VIN = –10dBFS
96
VIN = –1dBFS
–90
94
–95
THD (dB)
VIN = –1dBFS
90
88
–100
–105
86
–115
84
–120
82
–125
80
0
50
100
150
FREQUENCY (kHz)
200
Figure 15. SINAD vs. Frequency
VIN = –10dBFS
–110
–130
0
50
100
150
FREQUENCY (kHz)
Figure 18. THD vs. Frequency
Rev. A | Page 10 of 24
200
06394-018
92
06394-015
SNR, SINAD (dB)
SNR, SINAD (dB)
96
92
4.0
–100
18.5
SNR, SINAD
3.5
Figure 16. THD, SFDR vs. Reference Voltage
20.0
97
3.0
REFERENCE VOLTAGE (V)
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
100
90
SFDR (dB)
92
125
SFDR
SFDR (dB)
17.5
130
06394-016
SNR, SINAD
95
THD (dB)
96
ENOB (Bits)
100
06394-013
SNR, SINAD (dB)
AD7693
AD7693
1000
1000
800
POWER-DOWN CURRENT (nA)
VDD
600
400
200
800
600
400
200
VDD + VIO
VIO
4.75
5.00
5.25
5.50
SUPPLY (V)
0
–55
06394-019
0
4.50
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 19. Operating Currents vs. Supply
06394-022
OPERATING CURRENT (µA)
fS = 100kSPS
Figure 22. Power-Down Currents vs. Temperature
1000
1.0
fS = 100kSPS
ZERO, GAIN ERROR (LSB)
OPERATING CURRENT (µA)
VDD
800
600
400
200
0.5
ZERO ERROR
0
GAIN ERROR
–0.5
–15
–5
25
45
65
85
105
125
TEMPERATURE (°C)
–1.0
–55
06394-020
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 20. Operating Currents vs. Temperature
Figure 23. Zero Error and Gain Error vs. Temperature
25
10k
1k
20
VDD
10
tDSDO DELAY (ns)
100
VIO
1
VDD = 5V, 85°C
10
VDD = 5V, 25°C
100
1k
10k
100k
SAMPLING RATE (SPS)
1M
0
0
20
40
60
80
SDO CAPACITIVE LOAD (pF)
100
Figure 24. tDSDO Delay vs. Capacitance Load and Supply
Figure 21. Operating Currents vs. Sample Rate
Rev. A | Page 11 of 24
120
06394-031
0.1
0.01
10
15
5
06394-021
OPERATING CURRENT (µA)
–35
06394-023
VIO
0
–55
AD7693
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
REF
32,768C
LSB
16,384C
4C
2C
C
SW+
C
BUSY
COMP
GND
32,768C
4C
16,384C
2C
C
MSB
CONTROL
LOGIC
OUTPUT CODE
C
LSB
SW–
06394-024
CNV
IN–
Figure 25. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7693 is a fast, low power, single-supply, precise, 16-bit
ADC using a successive approximation architecture.
The AD7693 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 1 kSPS, for example, it consumes 40 μW
typically, ideal for battery-powered applications.
The AD7693 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.
The AD7693 is specified from 4.5 V to 5.5 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines
space savings and allows flexible configurations.
It is pin-for-pin compatible with the 16-bit AD7687 and
AD7688 and with the 18-bit AD7690 and AD7691.
CONVERTER OPERATION
The AD7693 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
IN+ and IN− inputs captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/32,768).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.
Because the AD7693 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. A | Page 12 of 24
AD7693
Transfer Functions
Table 7. Output Codes and Ideal Input Voltages
Analog Input
VREF = 5 V
+4.999847 V
+152.6 μV
0V
−152.6 μV
−4.999847 V
−5 V
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
011...111
011...110
011...101
1
2
Digital Output
Code (Hex)
0x7FFF1
0x0001
0x0000
0xFFFF
0x8001
0x80002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
100...010
Figure 27 shows an example of the recommended connection
diagram for the AD7693 when multiple supplies are available.
100...001
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
ANALOG INPUT
Figure 26. ADC Ideal Transfer Function
V+
REF1
5V
10µF2
100nF
V+
1.8V TO VDD
100nF
33Ω
REF
0 TO VREF
ADA4841-2 3
V–
V+
2.7nF
VDD
IN+
AD7693
4
IN–
33Ω
GND
VIO
SDI
SCK
SDO
3- OR 4-WIRE INTERFACE 5
CNV
VREF TO 0
ADA4841-2 3
V–
2.7nF
4
1SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3SEE TABLE 8 FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
Figure 27. Typical Application Diagram with Multiple Supplies
Rev. A | Page 13 of 24
06394-026
100...000
–FSR
06394-025
ADC CODE (TWOS COMPLEMENT)
The ideal transfer characteristic for the AD7693 is shown in
Figure 26 and Table 7.
AD7693
Figure 28 shows an equivalent circuit of the input structure of
the AD7693.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and to start conducting current. These diodes can handle
a forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, for
example, an input buffer with a short circuit, the current
limitation can be used to protect the part.
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
–80
VDD = 5V
–85
250Ω
–90
–95
THD (dB)
ANALOG INPUTS
100Ω
–100
50Ω
–105
33Ω
–110
–115
VDD
–120
IN+
OR IN–
–125
–130
D2
06394-027
CPIN
RIN
CIN
GND
0
10
20
30
40
50
60
70
80
90
FREQUENCY (kHz)
06394-047
D1
Figure 30. THD vs. Analog Input Frequency and Source Resistance
Figure 28. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
100
DRIVER AMPLIFIER CHOICE
Although the AD7693 is easy to drive, the driver amplifier must
meet the following requirements:
•
VREF = 5V
95
90
CMRR (dB)
85
80
75
70
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7693. The noise coming from
the driver is filtered by the AD7693 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of
the AD7693 is 56 μV rms, the SNR degradation due to the
amplifier is
65
60
SNR LOSS
50
1
10
100
1000
06394-028
55
10000
FREQUENCY (kHz)
where:
f−3 dB is the input bandwidth in megahertz of the AD7693
(9 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 600 Ω and is a lumped component made up of
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter that reduces undesirable aliasing effects and
limits the noise.
⎛
⎜
56
⎜
= 20 log ⎜
⎜⎜ 56 2 + π f −3 dB ( Ne N ) 2 + π f −3 dB ( Ne N ) 2
2
2
⎝
•
For ac applications, the driver should have a THD
performance commensurate with the AD7693.
•
For multichannel multiplexed applications, the driver
amplifier and the AD7693 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
When the source impedance of the driving circuit is low, the
AD7693 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
Rev. A | Page 14 of 24
⎞
⎟
⎟
⎟
⎟⎟
⎠
AD7693
Typical Application
Very low noise, low power single to differential
Very low noise, small, and low power
5 V single supply, low noise
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single supply, low power
SINGLE-ENDED-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-to-differential
driver allows for a differential input into the part. The
schematic is shown in Figure 31.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.
R3 and R4 set the common mode on the IN− input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to VREF/2; however, if single
supply is desired, it can be set slightly above VREF/2 to provide
some headroom for the ADA4941-1 output stage. For example,
for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 =
11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
R5
R6
R3
R4
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
POWER SUPPLY
The AD7693 uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and VDD. To
reduce the supplies needed, the VIO and VDD pins can be tied
together. The AD7693 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in Figure 32.
100
90
85
75
70
60
10µF
+5.2V
55
100nF
33Ω
2.7nF
2.7nF
100nF
33Ω
IN+
REF
50
VDD
AD7693
IN–
06394-029
CF
10
100
1000
10000
Figure 32. PSRR vs. Frequency
GND
R2
1
FREQUENCY (kHz)
ADA4941
R1
80
65
+5V REF
+5.2V
±10V, ±5V, ...
VREF = 5V
95
06394-030
Amplifier
ADA4941-1
ADA4841-x
AD8655
AD8021
AD8022
OP184
AD8605, AD8615
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using low temperature drift ADR43x and ADR44x
references.
PSRR (dB)
Table 8. Recommended Driver Amplifiers
The AD7693 powers down automatically at the end of each
conversion phase; therefore, the operating currents and power
scale linearly with the sampling rate (refer to Figure 21). This
makes the part ideal for low sampling rates (even of a few hertz)
and low battery-powered applications.
Figure 31. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7693 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031 or the AD8605),
a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate
for optimum performance.
Rev. A | Page 15 of 24
AD7693
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7693, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 33. The reference line can be driven by
•
The system power supply directly
•
A reference voltage with enough current output capability,
such as the ADR43x
•
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 33.
5V
5V
10Ω
5V
10kΩ
1µF
AD8031
10µF
1µF
1
REF
VDD
VIO
1OPTIONAL
REFERENCE BUFFER AND FILTER.
06394-032
AD7693
Figure 33. Example of an Application Circuit
DIGITAL INTERFACE
Generally, a user is interested in either minimizing the wiring
complexity of a multichannel ADC system or communicating
with the parts via a specific interface standard. Although the
ADC has only four digital pins (CNV, SCK, SDI, and SDO), it
offers a significantly flexible serial interface, including
compatibility with SPI, QSPI, digital hosts, and DSPs (such as
Blackfin® ADSP-BF53x or ADSP-219x). By configuring the
ADC into one of six modes, virtually any serial interface
scenario can be accommodated.
For wiring efficiency, the best way to configure a multichannel,
simultaneous-sampling system is to use the 3-wire chain mode.
This system is easily created by cascading multiple (M) ADCs
into a shift register structure. The CNV and CLK pins are
common to all ADCs, and the SDO of one part feeds the SDI of
the next part in the chain. The 3-wire interface is simply the
CNV, SCK, and SDO of the last ADC in the chain. For a system
containing M- and N-bit converters, the user needs to provide
M × N SCK transitions to read back all of the data. This 3-wire
interface is also ideally suited for isolated applications.
Additional flexibility is provided by optionally configuring the
ADCs to provide a busy indication. Without a busy indication,
the user must externally timeout the maximum ADC
conversion time before commencing readback. This
configuration is described in the Chain Mode Without Busy
Indicator section. With the busy indication enabled, external
timer circuits are not required because the SDO at the end of
the chain provides a low-to-high transition (that is, a start bit)
when all of the chain members have completed their
conversions and are ready to transmit data. However, one
additional SCK is required to flush the SDO busy indication
prior to reading back the data. This configuration is described
in the Chain Mode with Busy Indicator section.
The primary limitations of 3-wire chain mode are that all ADCs
are simultaneously sampled and the user cannot randomly
select an individual ADC for readback. This can be overcome
only by increasing the number of wires (for example, one chip
select wire per ADC). To operate with this increased
functionality, the part must be used in CS Mode. CS mode is
separated into two categories (3-wire and 4-wire) whereby
flexibility is traded off for wiring complexity. In CS 4-wire
mode, the user has independent control over the sampling
operation (via CNV) and the chip select operation (via SDI) for
each ADC. In CS 3-wire mode, SDI is unused (tied high) and
CNV is used to both sample the input and chip select the part
when needed. As with chain mode, the parts can optionally be
configured to provide a busy indication, but at the expense of
one additional SCK when reading back the data. So in total
there are four CS modes: 3-wire and 4-wire modes, each with
busy and without busy.
There is no elaborate writing of configuration words into the
part via the SDI pin. The mode in which the part operates is
defined by ensuring a specific relationship between the CNV,
SDI, and SCK inputs at key times. To select CS mode, ensure
that SDI is high at the rising edge of CNV; otherwise, chain
mode will be selected. Once in CS mode, selecting the part for
readback before the conversion is complete (by bringing either
SDI or CNV low) instructs the part to provide a busy indicator,
a high-to-low impedance transition on SDO, to tell the user
when the conversion has finished. If the part is selected after the
conversion has finished, SDO outputs the MSB when it is
selected. In chain mode, the busy indicator, a low-to-high
transition on SDO, is selected based on the state of SCK at the
rising edge of CNV. If SCK is high, the busy indicator is
enabled; otherwise, the busy indicator is not enabled.
The following sections provide specifics for each of the different
serial interface modes. Note that in the following sections, the
timing diagrams indicate digital activity (SCK, CNV) during
conversion. However, due to the possibility of performance
degradation, digital activity should only occur during the first
quarter of the conversion phase because the AD7693 provides
error correction circuitry that can correct for an incorrect bit
during this time. The user should initiate the busy indicator if
desired during this time. It is also possible to corrupt the sample
by having SCK or SDI transitions near the sampling instant.
Therefore, it is recommended to keep the digital pins quiet for
approximately 30 ns before and 10 ns after the rising edge of
CNV. The exception is when the device is in the chain mode
with busy configuration, where SDI is tied to CNV, because this
scenario does not yield a corrupted sample. To this extent, it is
recommended, to use a discontinuous SCK whenever possible to
avoid any potential performance degradation.
Rev. A | Page 16 of 24
AD7693
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7693 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when CNV goes high (whichever
occurs first), SDO returns to high impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7693
DATA IN
SDO
06394-033
SCK
CLK
Figure 34. CS Mode, 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
14
tHSDO
16
tSCKH
tDSDO
tEN
SDO
15
D15
D14
D13
tDIS
D1
D0
Figure 35. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Rev. A | Page 17 of 24
06394-034
SCK
AD7693
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7693 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
If multiple AD7693s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CONVERT
VIO
DIGITAL HOST
CNV
VIO
AD7693
DATA IN
SDO
SCK
IRQ
06394-035
SDI
CLK
Figure 36. CS Mode, 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
15
tHSDO
16
17
tSCKH
tDSDO
SDO
D15
D14
tDIS
D1
D0
Figure 37. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. A | Page 18 of 24
06394-036
SCK
AD7693
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7693 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance and another AD7693 can
be read.
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7693s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7693s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
CNV
SDI
AD7693
CNV
SDO
SDI
AD7693
SCK
DIGITAL HOST
SDO
SCK
06394-037
DATA IN
CLK
Figure 38. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
1
2
14
3
tHSDO
16
17
18
30
31
32
tDSDO
tEN
SDO
15
tSCKH
D15
D14
D13
tDIS
D1
D0
D16
D15
Figure 39. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. A | Page 19 of 24
D1
D0
06394-038
SCK
AD7693
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7693
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
or when SDI goes high (whichever occurs first), SDO returns to
high impedance.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host with an interrupt input and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
CS1
CONVERT
VIO
DIGITAL HOST
CNV
AD7693
DATA IN
SDO
SCK
IRQ
06394-039
SDI
CLK
Figure 40. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
2
3
tHSDO
15
16
17
tSCKH
tDSDO
tDIS
tEN
SDO
D15
D14
D1
Figure 41. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Rev. A | Page 20 of 24
D0
06394-040
SCK
AD7693
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7693 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7693s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7693s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7693s is shown in
Figure 42, and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
CONVERT
CNV
AD7693
A
SDO
AD7693
SDI
SDO
B
SCK
DATA IN
SCK
06394-041
SDI
DIGITAL HOST
CNV
CLK
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
tHSCKCNV
2
3
14
15
tSSDISCK
16
17
18
DA15
DA14
30
31
32
DA1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDIB
DA15
DA14
DA13
DA1
DA0
DB15
DB14
DB13
DB1
DB0
SDOB
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. A | Page 21 of 24
06394-042
tHSDO
tDSDO
AD7693
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7693 ADC labeled C in Figure 44) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7693 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7693s in the
chain, provided the digital host has an acceptable hold time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7693s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7693s is shown
in Figure 44, and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
CONVERT
SDI
AD7693
A
CNV
SDO
SDI
SCK
AD7693
B
DIGITAL HOST
CNV
SDO
SDI
AD7693
SCK
C
DATA IN
SDO
SCK
IRQ
06394-043
CNV
CLK
Figure 44. Chain Mode with Busy Indicator Connection Diagram
tCYC
ACQUISITION
tCONV
tACQ
ACQUISITION
CONVERSION
tSSCKCNV
SCK
tHSCKCNV
tSCKH
1
tEN
SDOA = SDIB
SDOB = SDIC
2
tSSDISCK
3
4
15
16
17
18
19
31
32
33
34
35
tSCKL
tHSDISCK
DA15 DA14 DA13
tDSDOSDI
tSCK
DA1
48
49
tDSDOSDI
DA0
tHSDO
tDSDO
tDSDOSDI
DB15 DB14 DB13
DB1
DB0 DA15 DA14
DA1
DA0
DC15 DC14 DC13
DC1
DC0 DB15 DB14
DB1
DB0 DA15 DA14
tDSDOSDI
SDOC
47
tDSDOSDI
Figure 45. Chain Mode with Busy Indicator Serial Interface Timing
Rev. A | Page 22 of 24
DA1
DA0
06394-044
CNV = SDIA
AD7693
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7693 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7693, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7693s.
06394-045
Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7693 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
Figure 46. Example Layout of the AD7693 (Top Layer)
The AD7693 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7693
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7693 and connected using short, wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
06394-046
An example of a layout following these rules is shown in
Figure 46 and Figure 47.
EVALUATING AD7693 PERFORMANCE
Other recommended layouts for the AD7693 are outlined
in the documentation of the evaluation board for the AD7693
(EVAL-AD7693CB). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
Rev. A | Page 23 of 24
Figure 47. Example Layout of the AD7693 (Bottom Layer)
AD7693
OUTLINE DIMENSIONS
3.10
3.00
2.90
3.10
3.00
2.90
10
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
6
PIN 1 INDEX
AREA
0.50
0.40
0.30
5
TOP VIEW
1.74
1.64
1.49
0.05 MAX
0.02 NOM
0.30
0.25
0.20
1
BOTTOM VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
121009-A
0.80
0.75
0.70
SEATING
PLANE
10
EXPOSED
PAD
Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD7693BCPZRL
AD7693BCPZRL7
AD7693BRMZ
AD7693BRMZRL7
EVAL-AD7693CBZ
EVAL-CONTROL BRD2
EVAL-CONTROL BRD3
Notes
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
2
3
3
Package Description
10-Lead QFN (LFCSP_WD)
10-Lead QFN (LFCSP_WD)
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Controller Board
Controller Board
1
Package Option
CP-10-9
CP-10-9
RM-10
RM-10
Branding
C4Y
C4Y
C4Y
C4Y
Ordering Quantity
Reel, 5,000
Reel, 1,500
Tube, 50
Reel, 1,000
Z = RoHS Compliant Part.
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
3
These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
2
©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05793-0-6/11(A)
Rev. A | Page 24 of 24
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