Alstom VPI II Vital Subsystem, CPU II, VRD, VSC, CRG, IOB, DI, SBO, DBO, DBO-50V, LDO, LDO2, ACO, FSVT Vital Vital Subsystem Manual

Vital Subsystem Manual

P2511B, Volume 3

VPI



II

Vital Processor

Interlocking Control

System

Vital Subsystem

Copyright © 2008, 2011, 2013 Alstom Signaling Inc.

VPI

 II

Vital Processor

Interlocking Control

System

Vital Subsystem

Copyright © 2008, 2011, 2013 Alstom Signaling Inc.

Vital Subsystem Manual

Alstom Signaling Inc.

P2511B, Volume 3, Rev. C, November 2013, Printed in U.S.A.

LIST OF EFFECTIVE PAGES

P2511B, Volume 3, VPI

®

II Vital Subsystem Manual

ORIGINAL ISSUE DATE: August 2008

CURRENT REVISION AND DATE:

PAGE

Cover

Title page

Rev C, November 2013

CHANGE OR REVISION LEVEL

Nov/13

Nov/13

Preface i through x

1–1 through 1-4

2–1 through 2-18

3–1 through 3-8

4–1 through 4-28

Nov/13

Nov/13

Nov/13

Nov/13

Nov/13

Nov/13

5–1 through 5-14

6–1 through 6-8

7–1 through 7-10

8–1 through 8-42

9–1 through 9-10

10–1 through 10-6

A–1 through A–4

B–1 through B–16

Nov/13

Nov/13

Nov/13

Nov/13

Nov/13

Nov/13

Nov/13

Nov/13

P2511B, Volume 3, Rev. C, Nov/13 Alstom Signaling Inc.

THIS PAGE INTENTIONALLY LEFT BLANK.


PREFACE

NOTICE OF CONFIDENTIAL INFORMATION

Information contained herein is confidential and is the property of Alstom Signaling Inc. Where furnished with a proposal, the recipient shall use it solely to evaluate the proposal. Where furnished to customer, it shall be used solely for the purposes of inspection, installation, or maintenance. Where furnished to a supplier, it shall be used solely in the performance of the contract. The information shall not be used or disclosed by the recipient for any other purposes whatsoever.

VPI

®

, WEE-Z

®

, and Microchron

®

are registered trademarks of Alstom Signaling Inc.

GM4000A™, iVPI™, microWIU™, and VCS™ are trademarks of Alstom Signaling Inc.

All other trademarks referenced herein are trademarks of their respective owners.

FOR QUESTIONS AND INQUIRIES, CONTACT CUSTOMER SERVICE AT

1–800–717–4477

OR

WWW.ALSTOMSIGNALINGSOLUTIONS.COM

ALSTOM SIGNALING INC.

1025 JOHN STREET

WEST HENRIETTA, NY 14586

REVISION LOG

Revision

0(A)

1(B)

C

Date Description By

August 2008 Original issue.

May 2011 Added CPU II Comm

Panel, updated DBO,

LDO, and LDO2 Boards.

November 2013 Updated manual reference numbers

MAS

MAS

SG

Checked Approved

KW

RIH

KW

NI

NI

MS




ABOUT THE MANUAL

This manual is intended to describe the Alstom Vital Processor Interlocking Control

System, (VPI



II) Vital subsystem (Vital boards). This manual is part of a 5 volume set of manuals. The set is summarized in Section 1.

The information in this manual is arranged into sections. The title and a brief description of each section follow:

Section 1 – VITAL PRINTED CIRCUIT BOARDS: This section summarizes the VPI



II

Vital subsystem boards.

Section 2 – CPU II (CENTRAL PROCESSING UNIT II) BOARD, P/N 31166-374-XX:

This section provides CPU II board detail, including discussion of the CPU2 Interface

Board (P/N 31166-499-XX).

Section 3 – VRD (VITAL RELAY DRIVER) BOARD, P/N 59473-740-02: This section provides VRD board detail.

Section 4 – VSC (VITAL SERIAL CONTROLLER) BOARD, P/N 59473-939-XX: This section provides VSC board detail.

Section 5 – CRG (CODE RATE GENERATOR) BOARD, P/N 31166-261-XX: This section provides CRG board detail.

Section 6 – IOB (I/O BUS INTERFACE) BOARD, P/N 59473-827-XX: This section provides IOB board detail.

Section 7 – DI (DIRECT INPUT) BOARD, P/N 59473-867-XX: This section provides DI board detail.

Section 8 – VITAL DC OUTPUT BOARDS, P/N 59473-739-XX, -747-XX, -977-XX,

-749-XX, 31166-340-XX: This section provides Vital DC output board detail.

Section 9 – ACO (AC OUTPUT) BOARD, P/N 59473-937-XX: This section provides

Vital ACO board detail.

Section 10 – FSVT (FIELD-SETTABLE VITAL TIMER) BOARD, P/N 59473-894-XX:

This section provides FSVT board detail.

Appendix A – SIGNATURE HEADERS AND PROMS: This appendix provides VPI circuit boards Signature Header and PROM information.

Appendix B – VITAL BOARD LAYOUT DRAWINGS: This appendix provides the layout drawings for each Vital board type.




MANUAL SPECIAL NOTATIONS

In the Alstom manuals, three methods are used to convey special informational notations. These notations are warnings, cautions, and notes. Both warnings and cautions are readily noticeable by boldface type and a box around the entire informational statement.

Warning

A warning is the most important notation to heed. A warning is used to tell the reader that special attention needs to be paid to the message because if the instructions or advice is not followed when working on the equipment then the result could be either serious harm or death. The sudden, unexpected operation of a switch machine, for example, or the technician contacting the third rail could lead to personal injury or death.

An example of a typical warning notice follows:

WARNING

Disconnect motor energy whenever working on switch layout or switch machine. Unexpected operation of machine could cause injury from open gears, electrical shock, or moving switch points.

Caution

A caution statement is used when an operating or maintenance procedure, practice, condition, or statement, which if not strictly adhered to, could result in damage to or destruction of equipment. A typical caution found in a manual is as follows:

CAUTION

Turn power off before attempting to remove or insert circuit boards into a module. Boards can be damaged if power is not turned off.

Note

A note is normally used to provide minor additional information to the reader to explain the reason for a given step in a test procedure or to just provide a background detail. An example of the use of a note follows:

Note: This step should be done first to validate the correct information is used.




TABLE OF CONTENTS

Topic Page

SECTION 1 – VITAL PRINTED CIRCUIT BOARDS .................................................... 1-1

1.1

INTRODUCTION ........................................................................................ 1-1

1.2

GENERAL ................................................................................................... 1-1

1.3

MANUAL SET ORGANIZATION ................................................................. 1-1

1.3.1

Vital Subsystem ............................................................................... 1-2

SECTION 2 – CPU II BOARD, P/N 31166-374-XX ...................................................... 2-1

2.1

INTRODUCTION ........................................................................................ 2-1

2.2

GENERAL ................................................................................................... 2-1

2.3

ASSEMBLY ................................................................................................ 2-1

2.4

FUNCTION ................................................................................................. 2-2

2.5

OPERATION ............................................................................................... 2-5

2.6

MEMORY ADDRESS DECODING ............................................................. 2-5

2.7

INTEGRATED DIAGNOSTICS ................................................................... 2-5

2.8

CONFIGURABLE SYSTEM IDS ................................................................. 2-6

2.8.1

Application Revision Signature......................................................... 2-6

2.8.2

Site ID .............................................................................................. 2-6

2.9

INDICATIONS ............................................................................................. 2-7

2.10

TEST POINTS ............................................................................................ 2-8

2.11

JUMPERS ................................................................................................. 2-10

2.12

CARD EDGE CONNECTORS .................................................................. 2-12

2.13

ADDITIONAL CONNECTORS .................................................................. 2-15

2.14

CPU2 INTERFACE BOARD (P/N 31166-499-XX) .................................... 2-16

2.14.1

Logic Processor Bit Designations ................................................... 2-17

2.15

SPECIFICATIONS/ASSEMBLY DIFFERENCES ..................................... 2-18

SECTION 3 – VRD BOARD, P/N 59473-740-02 .......................................................... 3-1

3.1

INTRODUCTION ........................................................................................ 3-1

3.2

GENERAL ................................................................................................... 3-1

3.3

OPERATION ............................................................................................... 3-1

3.4

STATUS OR ACTIVITY INDICATORS ....................................................... 3-3

3.5

TEST POINTS ............................................................................................ 3-5

3.6

SWITCHES ................................................................................................. 3-6

3.7

CARD EDGE CONNECTORS .................................................................... 3-7

3.8

SPECIFICATIONS ...................................................................................... 3-8

P2511B, Volume 3, Rev. C, Nov/13 i Alstom Signaling Inc.


Topic Page

SECTION 4 – VSC BOARD, P/N 59473-939-XX ......................................................... 4-1

4.1

INTRODUCTION ........................................................................................ 4-1

4.2

GENERAL ................................................................................................... 4-1

4.3

OPERATION ............................................................................................... 4-2

4.4

COMMUNICATION ..................................................................................... 4-3

4.4.1

VSC Board, VPI to VPI Communication ........................................... 4-3

4.4.2

4.4.3

VSC Board, VPI to AF Track Circuit Module Communication .......... 4-4

GVSC Board, VPI to Programmable Genrakode (PGK)

Board Communication ...................................................................... 4-4

4.4.4

GVSCE Board, VPI to PGK Board Communication ......................... 4-4

4.5

COMMUNICATION PROCESS .................................................................. 4-5

4.6

MEMORY TYPES ....................................................................................... 4-6

4.7

STATUS AND ACTIVITY INDICATORS ..................................................... 4-6

4.8

COMMUNICATION INTERFACES ............................................................. 4-8

4.9

DIRECT WIRE INTERFACE ....................................................................... 4-8

4.9.1

Serial Communication Controller - Manchester Encoder-

Decoder ........................................................................................... 4-8

4.9.2

Serial Link Interface ......................................................................... 4-8

4.10

DATA TRANSMISSION .............................................................................. 4-9

4.11

DATA RECEPTION .................................................................................... 4-9

4.12

APPLICATION WIRING ............................................................................ 4-10

4.13

DATA COMMUNICATIONS INTERFACE ................................................. 4-11

4.14

DATA TRANSMISSION AND RECEPTION .............................................. 4-11

4.15

EXTERNAL POWER ................................................................................ 4-12

4.16

TEST POINTS .......................................................................................... 4-12

4.17

ON-BOARD SWITCHES ........................................................................... 4-15

4.17.1

S1 ................................................................................................... 4-15

4.17.2

4.17.3

S2 ................................................................................................... 4-18

S4 ................................................................................................... 4-20

4.18


4.19

BOARD ASSEMBLY DIFFERENCES....................................................... 4-25

4.20

VSC DAUGHTER BOARD, P/N 31166-058-XX ........................................ 4-26

SECTION 5 – CRG BOARD, P/N 31166-261-XX ......................................................... 5-1

5.1

INTRODUCTION ........................................................................................ 5-1

5.2

GENERAL ................................................................................................... 5-1

P2511B, Volume 3, Rev. C, Nov/13 ii Alstom Signaling Inc.


Topic Page

5.3

OPERATION ............................................................................................... 5-1

5.4

INDICATIONS ............................................................................................. 5-3

5.5

ELECTRICAL RATINGS ............................................................................. 5-4

5.6

OUTPUTS ................................................................................................... 5-4

5.6.1

Solid State Relay Driver ................................................................... 5-4

5.6.2

B-Relay Driver .................................................................................. 5-5

5.7

COMMUNICATIONS .................................................................................. 5-6

5.8

TEST POINTS ............................................................................................ 5-7

5.9


5.10

BOARD ASSEMBLY DIFFERENCES....................................................... 5-12

5.11

BOARD ASSEMBLY CODE RATES – RATE TOLERANCE .................... 5-13

SECTION 6 – IOB BOARD, P/N 59473-827-XX .......................................................... 6-1

6.1

INTRODUCTION ........................................................................................ 6-1

6.2

GENERAL ................................................................................................... 6-1

6.3

OPERATION ............................................................................................... 6-1

6.4

VITAL CONTINUOUS OUTPUT VERIFICATION (50 MS

RECHECK CYCLE) .................................................................................... 6-3

6.5

INDICATORS .............................................................................................. 6-5

6.6


6.7

SPECIFICATIONS ...................................................................................... 6-8

SECTION 7 – DI BOARD, P/N 59473-867-XX ............................................................. 7-1

7.1

INTRODUCTION ........................................................................................ 7-1

7.2

GENERAL ................................................................................................... 7-1

7.3

OPERATION ............................................................................................... 7-3

7.4

INDICATORS .............................................................................................. 7-3

7.5

ADDRESS SIGNATURE HEADER ............................................................. 7-5

7.6

TEST POINTS ............................................................................................ 7-5

7.7


7.8

SPECIFICATIONS / ASSEMBLY DIFFERENCES ................................... 7-10

SECTION 8 – VITAL DC OUTPUT BOARDS, P/N 59473-739-XX, -747-XX, -

977-XX, -749-XX, 31166-340-XX .......................................................... 8-1

8.1

INTRODUCTION ........................................................................................ 8-1

8.2

GENERAL ................................................................................................... 8-1

8.3

OPERATION ............................................................................................... 8-2

P2511B, Volume 3, Rev. C, Nov/13 iii Alstom Signaling Inc.


Topic Page

8.4

INDICATORS .............................................................................................. 8-7

8.5

SBO DETAILS .......................................................................................... 8-12

8.5.1

8.5.2

8.5.3

8.5.4

SBO Board Test Points .................................................................. 8-12

Card Edge Connectors ................................................................... 8-14

Specifications ................................................................................. 8-16

Assembly ....................................................................................... 8-17

8.6

DBO AND DBO-50V DETAILS ................................................................. 8-18

8.6.1

DBO and DBO-50V Board Test Points ........................................... 8-18

8.6.2

8.6.3

8.6.4


Specifications ................................................................................. 8-25

Assemblies ..................................................................................... 8-26

8.7

LDO DETAILS .......................................................................................... 8-27

8.7.1

8.7.2

8.7.3

8.7.4

LDO Board Test Points .................................................................. 8-27


Specifications ................................................................................. 8-31

Assemblies ..................................................................................... 8-32

8.8

LDO2 DETAILS ........................................................................................ 8-33

8.8.1

8.8.2

8.8.3

8.8.4

8.8.5

LDO2 Board Test Points ................................................................ 8-34

LDO2 Board Switches .................................................................... 8-36

Card Edge Connections ................................................................. 8-38

Specifications/Assembly Differences ............................................. 8-40

Assemblies ..................................................................................... 8-41

SECTION 9 – ACO BOARD, P/N 59473-937-XX ......................................................... 9-1

9.1

INTRODUCTION ........................................................................................ 9-1

9.2

GENERAL ................................................................................................... 9-1

9.3

OPERATION ............................................................................................... 9-1

9.4

INDICATIONS ............................................................................................. 9-4

9.5

JUMPER CONFIGURATIONS .................................................................... 9-5

9.6

TRANSIENT PROTECTION ....................................................................... 9-5

9.7

TEST POINTS ............................................................................................ 9-5

9.8


9.9

SPECIFICATIONS ...................................................................................... 9-9

9.10

ASSEMBLY .............................................................................................. 9-10

SECTION 10 – FSVT BOARD, P/N 59473-894-XX.................................................... 10-1

10.1

INTRODUCTION ...................................................................................... 10-1

10.2

GENERAL ................................................................................................. 10-1

P2511B, Volume 3, Rev. C, Nov/13 iv Alstom Signaling Inc.


Topic Page

10.3

OPERATION ............................................................................................. 10-1

10.4

TEST POINTS .......................................................................................... 10-4

10.5


10.6

SPECIFICATIONS .................................................................................... 10-6

APPENDIX A – SIGNATURE HEADERS AND PROMS ............................................ A–1

A.1

INTRODUCTION ...................................................................................... A–1

A.2

GENERAL ................................................................................................. A–1

APPENDIX B – VITAL BOARD LAYOUT DRAWINGS ............................................. B–1

B.1

INTRODUCTION ...................................................................................... B–1

B.2

GENERAL ................................................................................................. B–1

P2511B, Volume 3, Rev. C, Nov/13 v Alstom Signaling Inc.

Figure No.

Figure 1–1.

Figure 2–1.

Figure 2–2.

Figure 2–3.

Figure 2–4.

Figure 2–5.

Figure 2–6.

Figure 2–7.

Figure 2–8.

Figure 3–1.

Figure 3–2.

Figure 3–3.

Figure 3–4.

Figure 4–1.

Figure 4–2.

Figure 4–3.

Figure 4–4.

Figure 4–5.

Figure 4–6.

Figure 4–7.

Figure 4–8.

Figure 4–9.

Figure 4–10.

Figure 5–1.

Figure 5–2.

Figure 5–3.

Figure 5–4.

Figure 5–5.

Figure 6–1.

Figure 6–2.

Figure 6–3.

LIST OF FIGURES

Title Page

Vital and Non-Vital Subsystems ....................................................... 1-2

CPU II Board .................................................................................... 2-1

CPU II Board Block Diagram ............................................................ 2-3

CPU II Board Main Processor Block Diagram .................................. 2-3

CPU II Board Communication Processor Block Diagram ................. 2-4

CPU II Board Edge ........................................................................... 2-7

CPU II Board Test Point, Jumper, and Flash Chip Locations ........... 2-9

CPU2 Interface Board .................................................................... 2-16

CPU2 Interface Board Logic Processor System ID

Designations .................................................................................. 2-17

VRD Board Block Diagram ............................................................... 3-2

VRD Board Edge .............................................................................. 3-4

VRD Board Switch and Test Point Locations ................................... 3-5

VRD Board SW1 Switch Setting ....................................................... 3-6

VSC Board Edge .............................................................................. 4-7

The Effect of Manchester Encoding on NRZ Data ........................... 4-8

VSC Link Cable and Shield Connections ....................................... 4-10

VSC Board Test Point, Switch, Jumper, and EPROM

Locations ........................................................................................ 4-13

VSC Board with T1 Adapter Board Test Point, Switch, and

EPROM Locations .......................................................................... 4-14

VSC Board DIP Switch S1 ............................................................. 4-16



Daughter Board Current vs Voltage ............................................... 4-26

VSC Daughter Board...................................................................... 4-27

CRG Board Block Diagram .............................................................. 5-3

CRG Board Edge ............................................................................. 5-3

Output Circuit Solid State Relay Driver ............................................ 5-4

Output Circuit B-Relay Driver ........................................................... 5-5

CRG Board Test Point and Switch Locations ................................... 5-8

IOB Board Block Diagram ................................................................ 6-1

IOB Board Edge ............................................................................... 6-5

IOB Board Interface Connections and Signature Header

Locations .......................................................................................... 6-6

P2511B, Volume 3, Rev. C, Nov/13 vi Alstom Signaling Inc.

Figure No.

Figure 7–1.

Figure 7–2.

Figure 7–3.

Figure 8–1.

Figure 8–2.

Figure 8–3.

Figure 8–4.

Figure 8–5.

Figure 8–6.

Figure 8–7.

Figure 8–8.

Figure 8–9.

Figure 8–9.

Figure 8–10.

Figure 8–11.

Figure 8–12.

Figure 8–13.

Figure 8–14.

Figure 8–15.

Figure 8–16.

Figure 9–1.

Figure 9–2.

Figure 9–3.

Figure 9–4.

Figure 10–1.

Figure 10–2.

Figure 10–3.

Figure A–1.

Figure B–1.

Figure B–2.

Figure B–3.

Figure B–4.

Figure B–5.

Figure B–6.

Figure B–7.

Figure B–8.

LIST OF FIGURES

Title Page

DI Board Block Diagram ................................................................... 7-2

DI Board Edge .................................................................................. 7-4

DI Board Test Points and Signature Header Locations .................... 7-6

Vital DC Output Board Block Diagram.............................................. 8-3

Vital Output SBO Board Edge .......................................................... 8-7

Vital Output DBO Board Edge .......................................................... 8-8

Vital Output DBO-50V Board Edge .................................................. 8-9

Vital Output LDO Board Edge ........................................................ 8-10

Vital Output LDO2 Board Edge ...................................................... 8-11

Single Break Output Block Diagram ............................................... 8-12

SBO Board Test Point and Signature PROM Locations ................. 8-13

DBO Board Block Diagram ............................................................. 8-18

DBO Board Test Point and Signature PROM Locations................. 8-19

DBO-50V Board Test Point and Signature PROM Locations ......... 8-20

LDO Board Port Interface ............................................................... 8-27

LDO Board Test Point and Signature PROM Locations ................. 8-28

LDO2 Board Port Interface ............................................................. 8-33

LDO2 Board Test Point and Switch Locations ............................... 8-35

LCTH Selection Dial ....................................................................... 8-36

AOCD Selection Dials .................................................................... 8-37

ACO Board Block Diagram ............................................................... 9-2

ACO Board Port Interface ................................................................ 9-3

ACO Board Edge ............................................................................. 9-4

ACO Board Test Point and PROM Locations ................................... 9-6

FSVT Board Timer Setting Examples............................................. 10-2

FSVT Board Edge .......................................................................... 10-3

FSVT Board Test Point and Timer Locations ................................. 10-5

Selectable Signature PROM Assembly ........................................... A–3

CPU II Board, P/N 31166-374-00 .................................................... B–2

CPU2 Interface Board, P/N 31166-499-00 ...................................... B–3

VRD Board, P/N 59473-740-00 ....................................................... B–4

VSC Board, P/N 59473-939-00 ....................................................... B–5

VSC Board with Daughterboard, P/N 59473-939-00 ....................... B–6

CRG Board, P/N 31166-261-00 ...................................................... B–7

IOB Board, P/N 59473-827-00 ........................................................ B–8

DI Board, P/N 59473-867-00 ........................................................... B–9

P2511B, Volume 3, Rev. C, Nov/13 vii Alstom Signaling Inc.

LIST OF FIGURES

Figure No. Title Page

Figure B–9. SBO Board, P/N 59473-739-00 ..................................................... B–10

Figure B–10. DBO Board, P/N 59473-747-00 ..................................................... B–11

Figure B–11. DBO-50V Board, P/N 59473-977-00 ............................................. B–12

Figure B–12. LDO Board, P/N 59473-749-00 ..................................................... B–13

Figure B–13. LDO2 Board, P/N 31166-340-00 ................................................... B–14

Figure B–14. ACO Board, P/N 59473-937-00 ..................................................... B–15

Figure B–15. FSVT Board, P/N 59473-894-00 ................................................... B–16

P2511B, Volume 3, Rev. C, Nov/13 viii Alstom Signaling Inc.

Table No.

Table 1–1.

Table 2–1.

Table 2–2.

Table 2–3.

Table 2–4.

Table 2–5.

Table 2–6.

Table 2–7.

Table 2–8.

Table 2–9.

Table 2–10.

Table 2–11.

Table 3–1.

Table 3–2.

Table 3–3.

Table 4–1.

Table 4–2.

Table 4–3.

Table 4–4.

Table 4–5.

Table 4–6.

Table 4–7.

Table 4–8.

Table 5–1.

Table 5–2.

Table 5–3.

Table 5–4.

Table 5–5.

Table 5–6.

Table 6–1.

Table 7–1.

Table 7–2.

Table 7–3.

Table 7–4.

LIST OF TABLES

Title Page

Vital PC Boards Index ...................................................................... 1-3

CPU II Board Assembly .................................................................... 2-1

CPU II Board Test Points ................................................................. 2-8

CPU II Board Battery Selection Jumper ......................................... 2-10

CPU II Board Watchdog Selection Jumper .................................... 2-10

CPU II Board Terminal Power Jumper ........................................... 2-10

CPU II Main Application Flash Programming Jumper .................... 2-10

CPU II Main System Flash Programming Jumper .......................... 2-11

CPU II Communication Flash Programming Jumper* .................... 2-11

CPU II Board 60-pin P3 Connections ............................................. 2-13

P2 and P3 Connections Used For Revision and Site

Identification ................................................................................... 2-14

CPU II Board Specifications/Assembly Differences ....................... 2-18

VRD Board Test Points .................................................................... 3-5

VRD Board P3 Power Connections .................................................. 3-7

VRD Board Specifications ................................................................ 3-8

VSC Board Test Points .................................................................. 4-12

VSC Board DIP Switch S1 Functions ............................................. 4-17

VSC Board DIP Switch S2 Functions ............................................. 4-19

VSC S4 Miscellaneous Functions .................................................. 4-20

Line Termination Jumpers for Copper Pair Interface ...................... 4-21

VSC Board 36-pin P3 Connections ................................................ 4-23

VSC Board Specifications .............................................................. 4-25

Daughter Board Terminal Block Operating Positions ..................... 4-27

CRG Board Communications Specifications .................................... 5-6

CRG Board Test Points .................................................................... 5-7

CRG Board 36-pin P3 Connections ................................................. 5-9

CRG Board 36-pin P1 Connections ............................................... 5-10

CRG Board Assembly Differences ................................................. 5-12

CRG Board Assembly Code Rate Tolerances ............................... 5-13

IOB Board Bus Interface Specifications ........................................... 6-8

DI Board Test Points ........................................................................ 7-5

DI Board 36-pin P3 Connections ...................................................... 7-7

DI Board 36-pin P1 Connections ...................................................... 7-8

DI Board Specifications/Assembly Differences .............................. 7-10

P2511B, Volume 3, Rev. C, Nov/13 ix Alstom Signaling Inc.

Table No.

Table 8–1.

Table 8–2.

Table 8–3.

Table 8–4.

Table 8–5.

Table 8–6.

Table 8–7.

Table 8–8.

Table 8–9.

Table 8–10.

Table 8–11.

Table 8–12.

Table 8–13.

Table 8–14.

Table 8–15.

Table 8–16.

Table 8–17.

Table 8–18.

Table 8–19.

Table 8–20.

Table 8–21.

Table 8–22.

Table 8–23.

Table 8–24.

Table 8–25.

Table 9–1.

Table 9–2.

Table 9–3.

Table 9–4.

Table 9–5.

Table 10–1.

Table 10–2.

Table A–1.

Table A–2.

LIST OF TABLES

Title Page

SBO Board Test Points .................................................................. 8-12

SBO Board 36-pin P3 Connections ................................................ 8-14

SBO Board 36-pin P1 Connections ................................................ 8-15

SBO Board Specifications .............................................................. 8-16

SBO Board Assembly..................................................................... 8-17

DBO Board Test Points .................................................................. 8-18

DBO-50V Board Test Points .......................................................... 8-18

DBO Board 36-pin P3 Connections ................................................ 8-21

DBO Board 36-pin P1 Connections ................................................ 8-22

DBO-50 Board 36-pin P3 Connections........................................... 8-23

DBO-50 Board 36-pin P1 Connections........................................... 8-24

DBO/DBO-50 Board Specifications ................................................ 8-25

DBO Board Assemblies .................................................................. 8-26

LDO Board Test Points .................................................................. 8-27

LDO Board 36-pin P3 Connections ................................................ 8-29

LDO Board 36-pin P1 Connections ................................................ 8-30

LDO Board Specifications .............................................................. 8-31

LDO Board Assemblies .................................................................. 8-32

LDO2 Board Test Points ................................................................ 8-34

LDO2 Board Switches .................................................................... 8-36

LCTH Switch Settings .................................................................... 8-37

LDO2 Board 36-pin P3 Connections .............................................. 8-38

LDO2 Board 36-pin P1 Connections .............................................. 8-39

LDO2 Board Specifications ............................................................ 8-40

LDO2 Board Assemblies ................................................................ 8-41

ACO Board Test Points .................................................................... 9-5

ACO Board 36-pin P3 Connections .................................................. 9-7

ACO Board 36-pin P1 Connections .................................................. 9-8

ACO Board Specifications/Assembly Differences .......................... 9-10

ACO Board Assembly .................................................................... 9-10

FSVT Board Test Points ................................................................. 10-4

FSVT Board Specifications/Assembly Differences: ........................ 10-6

Address Signature Headers (For Vital Inputs and I/O Bus

Boards) ............................................................................................ A–1

Address Signature PROMs ............................................................. A–2

P2511B, Volume 3, Rev. C, Nov/13 x Alstom Signaling Inc.

Vital Printed Circuit Boards

SECTION 1 – VITAL PRINTED CIRCUIT BOARDS

1.1 INTRODUCTION

This manual describes the Printed Circuit Boards used to provide Vital functionality in the VPI II System. It includes a brief description of the differences between board variations and the keying information for all variations of each board type.

1.2 GENERAL

This section summarizes the VPI



II Vital subsystem boards.

1.3 MANUAL SET ORGANIZATION

This manual is part of a five volume set supporting the VPI II system. The set is organized as follows:

• Volume 1, Installation, Operation, and Theory Manual, includes general overview of the field installation and setup of the VPI II system; including capacity guidelines and allowable VSC/CSEX board combinations, system operation, and theory of operation.

• Volume 2, Chassis Configuration, describes the chassis configuration including cables and power supplies.

• Volume 3, Vital Subsystem, is this document. It includes the Vital subsystem board drawings, signature headers and proms, and board reference data.

• Volume 4, Non-Vital Subsystem, includes non-vital subsystem board drawings and board reference data.

• Volume 5, Maintenance and Troubleshooting, describes system maintenance and troubleshooting, including discussion of diagnostics and references for the applicable software and hardware manuals.

P2511B, Volume 3, Rev. C, Nov/13 1-1 Alstom Signaling Inc.


1.3.1 Vital Subsystem

Figure 1–1 is a block diagram of the boards in the Vital and non-vital subsystems.

Vital Subsystem

Vital I/O Bus

CPU II IOB

CRG

Vital Inputs Vital Outputs

VRD

VSC

Non-Vital Subsystem

Non-Vital I/O Bus

CSEX

Non-Vital

Inputs

Figure 1–1. Vital and Non-Vital Subsystems

Non-Vital

Outputs



Table 1–1 lists the Vital printed circuit boards in the order that they are discussed. A

board’s 10 digit drawing number is also the part number to use for ordering the board.

Table 1–1. Vital PC Boards Index (Cont.)

IOB

DI

DI

DI

DI

DI

DI

SBO

Board Type

CPU II

CPU II

VRD

VSC

VSC

VSC

VSC

VSC

VSC

VSC

CRG

CRG

SBO

DBO

Comments Part Number

Vital Processor 31166-374-01

Vital Processor with Ethernet Network Communications 31166-374-02

Vital Relay Driver

Pt.-Pt. w/40025-322-00 VSC software

Pt.-Pt. w/ EIA232 Daughterboard w/40025-322-00 VSC software

59473-740-02

59473-939-10

59473-939-11

Multidrop w/40025-323-00 MVSC software 59473-939-12

Multidrop, half duplex w/40025-324-00 GVSC software 59473-939-13

Multidrop, half duplex w/40025-348-00 GVSCE software

Pt.-Pt. w/40025-406-00 VSC software

59473-939-14

59473-939-17

Pt.-Pt. w/ EIA232 Daughterboard w/40025-406-00 VSC software

Solid State Relay Driver w/40025-235-00 software, supports code rates 0, 50, 75, 120, 180 pulses per minute (PPM)

B-Relay Driver w/40025-325-00 software, supports code rates 0, 50, 75, 120, 180, 270, 420 pulses per minute (PPM), and steady ON

Vital I/O Bus Interface Board

(16) 9-15 VDC, low-pass filter

(16) 9-15 VDC, no low-pass filter

(16) 9-15 VDC, momentary input hold




(8) 9-30 VDC, 0.5 A

(8) 9-30 VDC, 0.5 A, , does not provide any filtering of the external output supply voltage

(8) 9-15 VDC, 0.6 A, Vout=Vin – 5*Iout,

(nominal 12 VDC source/12 VDC out)

59473-939-18

31166-261-03

31166-261-04

59473-827-01

59473-867-01

59473-867-02

59473-867-03

59473-867-04

59473-867-05

59473-867-07

59473-739-01

59473-739-02

59473-747-01



Table 1–1. Vital PC Boards Index (Cont.)

Board Type

Comments Part Number

DBO

DBO

(8) 9-15 VDC, 0.3 A, Vout=2.3*Vin – 10 *Iout

(nominal 12 VDC source/24 VDC out)

DBO-50V (8) 50 VDC @ 0.14 A out, 30-40 VDC in

DBO-50V (8) 50 VDC @ 0.14 A out, 45-55 VDC in

LDO

LDO

LDO

LDO2

LDO2

ACO

ACO

59473-747-01 with different keying than -747-01

(8) 9-18 VDC, 2.9 A, 100 mA Hot/Cold check

(8) 15-30 VDC, 2.9 A, 200 mA Hot/Cold check

(8) 9-18 VDC, 2.9 A, 100 mA without Cold check

59473-747-02

59473-747-03

59473-977-01

59473-977-02

59473-749-02

59473-749-03

59473-749-04

(8) 9-18VDC, 3.3A

(8) 9-18VDC, 3.3A (without current monitor)

31166-340-01

31166-340-02

(8) 90-130 VAC, 0.8 A, 40-150 HZ (superseded by -02) 59473-937-01

(8) 90-130 VAC, 0.8 A, 40-150 HZ (higher EMI protection)

59473-937-02

ACO

(8) 90-130 VAC, 0.5 A, 40-150 HZ (higher EMI protection)

(8) Field-Settable Vital Timers # 1-8

59473-937-03

FSVT 59473-894-01

FSVT (8) Field-Settable Vital Timers # 9-16 59473-894-02

Each board contains three card edge connectors, identified as P3, P2 and P1 from top to bottom. These connections are described for each system board in the sections that follow.

Refer to the .lvc output file generated by the system software CAAPE program for wire wrap specifications and the user defined inputs and outputs. For additional information on this program, refer to the following Alstom manuals:

• P2512A, CAAPE User Manual

• P2512B, AlsDload User Manual

• P2512D, VPI CAA Reference Manual

Note: A VPI II System performing non-vital functions can be configured with either a Code System Emulator Extended 3 or 4

(CSEX3 or CSEX4) non-vital processor board. This manual uses the generic term CSEX unless a function is specific to

CSEX3 or CSEX4. See P2511B, Volume 4 for discussions of the two boards.


CPU II Board, P/N 31166-374-XX

SECTION 2 – CPU II BOARD, P/N 31166-374-XX

2.1 INTRODUCTION

This section provides Central Processing Unit II (CPU II) board detail, including discussion of the CPU2 Interface Board (P/N 31166-499-XX).

2.2 GENERAL

The CPU II board is designed as a system board for VPI II incorporating Vital logic processing, Vital I/O control and monitoring, and an extended capacity for larger interlockings. The board includes vital communications, logic voltage monitoring, USB, on-board programming, and Ethernet connectivity. The board contains primarily SMT

(Surface Mount Technology) parts.

The CPU II contains two 32-bit 80386EX33 microprocessors that separately perform the

Vital processing and high-speed communications functions.

See P2511B, Volume 1, Table 2–3 for board limits / application criteria.

Figure 2–1. CPU II Board

2.3 ASSEMBLY

Table 2–1. CPU II Board Assembly

Description

Vital Processor

31166-374-01 with a Communications Processor for Ethernet

Network Communications

Part Number

31166-374-01

31166-374-02



2.4 FUNCTION

All control and monitoring functions for the VPI module go through the CPU II board.

Once each second:

• inputs are read

• all expressions are evaluated

• outputs are updated

In addition, Vital output status is verified every 50 ms.

Information is also passed to and from local or office code systems via the CSEX and

Non-Vital I/O boards. The CPU II board controls the main system bus over which the

VRD, CSEX, VSC and I/O bus interface boards communicate.

Each CPU II board contains a microprocessor to carry out VPI logic, timing, and data handling functions. By using a VT-100 Emulator, the VPI memory can be viewed and system diagnostics can be performed.

The CPU II board has the following features:

• Automatic Hardware Reset and

Watchdog Timer

• Integrated Diagnostics

• Software Revision and Site ID

Signature

• Polynomial Dividers

• Flash Memory for On-Board

Programming

• Main Processor for Vital Processing

• Maintenance Indications

• Logic Voltage Monitoring

The group -02 version of the CPU II board also contains a second microprocessor that allows multiple VPI II systems to communicate vitally with each other. A VPI II may communicate vitally with up to 40 other VPI II systems and non-vitally to the Alstom

MMS.

This group -02 board has the following additional features:

• Two USB 1.0/2.0 Controllers and

Type B Connectors

• Two 10/100 Base-T Ethernet

Network Controllers

• Communication Processor for

Ethernet Network Interface

• EEPROM for MAC Address Storage


P1

P2

P3

Backplane

Interfaces

Main Processor Section

Main

Processor

(80386EX)


Dual Port

RAM

Communication Processor Section

Networks To

External

Boards

Ethernet

Controller

NET CONN 1

Communication

Processor

(80386EX)

Ethernet

Controller

NET CONN 2

USB

Interface

USB

Interface

Figure 2–2. CPU II Board Block Diagram

COM

S1 Reset

WDT RESET

POR/

WDT/

RTC

Functions

J6/

PT1

P3

RESET/

WDT

RS232

Interfaces

TX2

RX2

VBAT

NVCE

66 MHz

Osc.

80386EX

PromJet

Interface

Connector

J 4 & J5

TX1

RX1

CLKIN INT2

SIO0

RESET BUS CTL

SIGNALS

WDOUT

A0-25

D0-15

TCLKIN0

RS422

Interfaces

SIO1

P1.6

INT1 INT0

ADDR/ DATA BUS

Decoder Logic

ASIC

&

PD

ASIC

128 K X 16

System

FLASH

USB PORT

J7

COMM PROC

AVAIL/

USB

UART

Bridge

USB Active

82C54

Counter/

Timer

Signature Inputs

P2

PU

P3

16 K X 16

Dual Port

RAM

1 MHz

Osc.

Input Buffer

To Communication

Processor

Signals

Internal

To Board

512 K X 16

ADS

FLASH

PD/ MISC.

ASIC

512 K X 16

SRAM

P 1 Output

Buffers

And Latches

XLA1-18

Bus

X Ctl s

Signal

XD0-15

WDI Reset

Signals

Internal

To Board

VCC

2. 5 V

Reference

Front

Panel

Intf

IN-

8- bit ADC

IN+

5 V IND Reset 1

Cycle

Figure 2–3. CPU II Board Main Processor Block Diagram



COM

J1/

S2 Reset

PT2

RESET/

POR

RS232

Interfaces

66 MHz

Osc.

TX3

RX3

PromJet

Interface

Connector

J 2 & J3

CLKIN RESET WDOUT

BUS CTL

SIGNALS

SIO0 A0-25

D0-15

ADDR /DATA BUS

ASIC

Decoder/

Logic

80386EX

USB Active INT1

USB PORT

J8

USB

UART

Bridge

SIO1

INT0

INT2

Signals

Internal

To Board

Ethernet

Controller

Interface

Linked 1

Lan 1

Ethernet

Controller

Interface

Linked 2

Lan 2

25 MHz

Osc.

COM

COMM PROC

AVAIL/

16 K X 16

Dual Port

RAM

512 K X 16

System

FLASH

512 K X 16

SRAM

Front

Panel

Intf

Reset 2

Cycle

To Main

Processor

Figure 2–4. CPU II Board Communication Processor Block Diagram



2.5 OPERATION

The Main Processor performs VPI timing and data handling functions for the VPI

System. The Communications Processor (only part of the -02 version of the board) performs network communication processing and interchanges data with the Main

Processor via a dual-ported RAM device.

2.6 MEMORY ADDRESS DECODING

Program memory includes:

• CPU II Task (VPI Vital System Software), Two 29F010 Flash

• Application Data (VPI Application Data Structures), Two 29F040 Flash

• Communications (System Software and Application Data), Two 29F040 Flash, on group-02 boards only

These six Flash devices are socketed PLCC devices that allow for on-board programming and external programming using a separate PROM burner.

2.7 INTEGRATED DIAGNOSTICS

Within the programming memory is a system diagnostic program that tests the operation of the CPU II board and, in addition, the functional operation of most other peripheral boards by choosing different diagnostic routines. Diagnostic software is run on-line. Most parameters generated during the controlling of an application are accessible in real time. In addition, error information is displayed to the user with any of the following:

• AlsDload

• MMS (Maintenance Management System)

• VT100 emulator connection via EIA232 port or USB port

• The VDP in a CSEX board



2.8 CONFIGURABLE SYSTEM IDS

The CPU II provides a 6-bit revision signature and a 10-bit site ID for configuration control purposes. These fields can be used separately or can be combined as a 16-bit system ID. A wire table is generated as a report from the CAAPE for configuring these inputs.

2.8.1 Application Revision Signature

On the Motherboard connector and on the P3 connector for the CPU II board, six programmed binary inputs are provided. These inputs can be programmed to 5V COM to yield a binary representation of a decimal number from 0 to 63. This number corresponds to the revision number of the current application data in the CPU Flash.

When the application is changed, the user can change this number via CAAPE.

2.8.2 Site ID

On connector P3 for the CPU II board, ten programmed binary inputs are provided.

These inputs can be programmed to 5VCOM to yield a binary representation of a decimal number from 0 to 1023. This number corresponds to the site ID of the VPI II system. A unique number can be assigned to each system for a customer.



2.9 INDICATIONS

LED indications are located on the CPU II board's front edge to indicate board functions.

Figure 2–5 shows the board edge with indications.

CPU II

31166-374-XX

THESE PORTIONS OF THE BOARD ARE ONLY

ON P/N 31166-374-02.

NORMAL PCB

INDICATION NOTATION

FUNCTION

TP2

PT2

+5V (+5 Volts Test Point)

PT2 (Communication MAC Port)

ON, OFF

ON, OFF

ON, OFF

ON

ON, OFF

ON, OFF

ON, OFF

ON, OFF

ON, OFF

DS2

DS3

DS4

J8

DS5

J7

DS6

DS7

DS8

DS9

DS10

S3

DS11

S4

S1

DS1

S2

COMM DIAG (Communication Diagnostics Selection Switch)

COMM DSPY (Communication Diagnostics Display)

COMM RST ( Communication Processor Reset Pushbutton)

MUSB / CUSB (Main Processor USB /

Communication Processor USB)

LNK 2 / LAN 2 (Ethernet Link 2 Good / LAN 2 Activity)

LNK 1 / LAN 1 (Ethernet Link 1 Good / LAN 1 Activity)

COMM USB (USB Port, Communication)

POWER (System +5 Volts)

MAIN USB (USB Port, Main)

RSTM / RSTC (Reset Main / Communication)

RXPT2 / TXPT2 (Communication Mac Receive / Transmit)

RXP3 / TXP3 (Main CRG Receive / Transmit)

RXPT1 / TXPT1 (Main Mac Receive / Transmit)

MP / CP (Cycle Communication / Main)

MAIN RST ( Main Processor Reset Pushbutton)

MAIN DSPY (Main Diagnostics Display)

MAIN DIAG (Main Diagnostics Selection Switch)

PT1

TP8

PT1 (Main MAC Port)

COM (Common Test Point)

Figure 2–5. CPU II Board Edge



2.10 TEST POINTS

Table 2–2 describes the test points on the CPU II board. Oscilloscope and clip leads

may be temporarily attached to the board using the test points. TP2 and TP8 are always

accessible, even when the board is in a system. See Figure 2–6 for an illustration of the

CPU II board including test point locations.

Table 2–2. CPU II Board Test Points

Test Point Connection

TP2

TP1, TP3, TP4, TP5, TP6, TP7, TP8

+5V, power

COM, common

TB2, TB3, TB4, TB8, TB11, TB12, TB13 Normally open, used for factory test



THIS COMMUNICATION PORTION OF THE BOARD

IS PROVIDED ONLY ON P/N 31166-374-02

SYSTEM/

APPLICATION

SOFTWARE

SYSTEM/

APPLICATION

SOFTWARE COMMUNICATION

CPU

APPLICATION

DATA

APPLICATION

DATA

SYSTEM

SOFTWARE

SYSTEM

SOFTWARE

VITAL CPU

Figure 2–6. CPU II Board Test Point, Jumper, and Flash Chip Locations



2.11 JUMPERS

Table 2–3 through Table 2–8 show the configurable jumper assignments for the CPU II

board. All other TB locations are not user configurable. See Figure 2–6 for an illustration

of the CPU II board including jumper locations.

TB5

1-2

2-3

Table 2–3. CPU II Board Battery Selection Jumper

Function

Battery disconnected (use this position for shipping and storage, or if no battery is installed during operation)

Battery connected (do not use this position if no battery is installed)

(future use)

TB6

2-3

1-2

Table 2–4. CPU II Board Watchdog Selection Jumper

Function

Watchdog enabled, normal operation

Watchdog disabled (for emulator use only)

TB10

1-2

2-3

Table 2–5. CPU II Board Terminal Power Jumper

VT-100 Terminal power enabled

Function

VT-100 Terminal power disabled, normal operation for PC

TB7

1-2

2-3

Table 2–6. CPU II Main Application Flash Programming Jumper

Function

Main Application Flash On-Board Programming always enabled

Main Application Flash On-Board Programming always disabled



TB9

1-2

2-3

Table 2–7. CPU II Main System Flash Programming Jumper

Function

Main System Flash On-Board Programming always enabled

Main System Flash On-Board Programming always disabled

Table 2–8. CPU II Communication Flash Programming Jumper*

TB1 Function

1-2 Communication System Flash On-Board Programming always enabled

2-3 Communication System Flash On-Board Programming always disabled

* This jumper exists on group 2 (P/N 31166-374-02) boards only.



2.12 CARD EDGE CONNECTORS

The CPU II board (both -01 and -02) has three card edge connectors:

• P3, the top connector, is a 60-pin connector used to connect to Serial Data channel

0 and Data channel 1 of the Logic Processor; it also includes 16 input pins used to determine the system and site identification

–

See Table 2–9 for 60-pin configuration details

–

See Table 2–10 for a description of which P3 pins are used for system and site

identification

–

Positions not listed in Table 2–9 or Table 2–10 are not user configurable

– For CPU II group -02 boards, the P3 connector is also used to connect to the

CPU II Interface Board via ribbon cable at J1 on the CPU2 Motherboard.

• P2, the middle connector, is a 50-pin connector used for system voltage and common; it also includes 6 input pins used to determine the revision identification

–

See Table 2–10 for a description of which P2 pins are used for revision

identification

–

Positions not listed in Table 2–10 are not user configurable

• P1, the lower connector, is a 60-pin connector which interfaces with the VPI system bus; this connector is not user configurable

Note: P2-10, P2-15, P2-22, P2-31, P2-38, P2-48 and P3-2, P3-4, P3-

6, P3-8, P3-10, P3-12, P3-14, P3-16, P3-18, and P3-20 are common connections available for configuring the ID along with

the connections in Table 2–10.


P3-

36

37

38

39

40

27

29

33

35

42

49

50

51

52

53

54

55


Table 2–9. CPU II Board 60-pin P3 Connections

Name

COM

RS232-RX

TXIA

TX2+

TX2-

RX2+

RX2-

COM

RD1+

RD1-

TD+

TD-

TX1+

TX1-

RX1+

RX1-

COM

Function

Backplane MMS Connection Common

Backplane MMS Connection Receive

Backplane MMS Connection Transmit

Ethernet Channel 2 transmit +, group -02 board only

Ethernet Channel 2 transmit -, group -02 board only

Ethernet Channel 2 receive +, group -02 board only

Ethernet Channel 2 receive -, group -02 board only

Ethernet Channel 2 common, group -02 board only

CRG receive +

CRG receive -

CRG transmit +

CRG transmit -

Ethernet Channel 1 transmit +, group -02 board only

Ethernet Channel 1 transmit -, group -02 board only

Ethernet Channel 1 receive +, group -02 board only

Ethernet Channel 1 receive -, group -02 board only

Ethernet Channel 1 common, group -02 board only



Table 2–10. P2 and P3 Connections Used For Revision and Site Identification

System ID Name Rev or Site ID Name P3 Connection

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

ID10

ID11

ID12

ID13

ID14

ID15

Rev ID0

Rev ID1

Rev ID2

Rev ID3

Rev ID4

Rev ID5

Site ID0

Site ID1

Site ID2

Site ID3

Site ID4

Site ID5

Site ID6

Site ID7

Site ID8

Site ID9

P3-21

P3-22

P3-23

P3-24

P3-25

P3-26

P3-1

P3-3

P3-5

P3-7

P3-9

P3-11

P3-13

P3-15

P3-17

P3-19

P2 Connection

P2-42

P2-43

P2-44

P2-45

P2-46

P2-47

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A



2.13 ADDITIONAL CONNECTORS

Both the -01 and -02 versions of the board also include these connectors:

• Connector J6/PT1 is a 9-pin Main Processor EIA232 interface connector

• Connectors J5 & J4 are 38-pin Test Connectors for the Main Processor Databus, address bus and control signals; these are not user configurable

CPU II board -02 supports a communications interface with the following additional connectors:

• Connector J1/PT2 is a 9-pin Communication Processor EIA232 interface connector

• Connector J7/MAIN USB is a Main Processor USB Interface connector

• Connector J8/COMM USB is a Communication Processor USB Interface connector

• Connectors J2 & J3 are 38-pin Test connectors for the Communication Processor

Databus, address bus and control signals; these are not user configurable



2.14 CPU2 INTERFACE BOARD (P/N 31166-499-XX)

The CPU2 Interface Board is mounted on DIN rails at the rear of the rack. It is connected to the P3 board edge connector on the CPU2 motherboard through a ribbon cable at J1.

It is used in CPU II group -02 configurations and used to provide communication and site ID features, including:

• Bit selection for the Logic Processor section of the CPU board.

• 2 RJ45 Ethernet jacks (J2 and J3) with LEDs for the Ethernet channels on P3 of the

CPU2 motherboard.

• 1 RJ45, without LEDs, designated for serial data transmission, PrPT1_RXD and

PT1_TXD.

• 1 RJ25 for the +/- COMM_PROC_ALIVE signal to be recognized.

Figure 2–7. CPU2 Interface Board



2.14.1 Logic Processor Bit Designations

CPU2 Interface Board switches S1-S4 control the System ID selection for the Logic

Processor section of the CPU board. These inputs can be programmed to 5V or common to provide a binary representation of a hexadecimal number from 0-63. This number corresponds to the revision identification (Site ID and Revision ID) of the current application in the CPU FLASH. When the application is changed, the CAA changes this number in the FLASH memory. The hardware must be reprogrammed to tie a particular

CPU board to a specific application. Programming is completed by setting switches S1

through S4 appropriately. Figure 2–8 shows the appropriate system ID designations (x3

= S1, x-2 = S2, x1 = S3, x0 = S4; Most Significant Bit – Least Significant Bit).

MSB

Site ID

System ID

Revision ID

LSB

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x3 x2 x1 x0

Figure 2–8. CPU2 Interface Board Logic Processor System ID Designations



2.15 SPECIFICATIONS/ASSEMBLY DIFFERENCES

Table 2–11. CPU II Board Specifications/Assembly Differences

Maximum Number of Boards Per VPI II System

Board Slots Required

Maximum Board Logic Current Supply

Supports 29F010 Flash

Supports 29F040 Flash

VPI CAA Version

Ethernet Communications

Supports USB

Specifications

31166-374

-01 -02

-050 and later

No

No

1

1

1.5A

Yes

Yes

-100 and later

Yes

Yes


VRD Board, P/N 59473-740-02

SECTION 3 – VRD BOARD, P/N 59473-740-02

3.1 INTRODUCTION

This section provides Vital Relay Driver (VRD) board detail.

3.2 GENERAL

Figure 3–1 shows a block diagram of the VRD board. This board plays a key role in

assuring the vitality of the system. It produces an output voltage capable of operating a

100

Ω Alstom Type B relay (56001-787-05) if, and only if, the data sent to it by the main processing system is correct. The main processing system creates a set of data called

“main checkwords” once every second. These checkwords are used by the VRD board.

They allow it to continue operation for another 1-second period. In addition, the main processing system generates a set of recheck checkwords every 50 ms based on the status of all the system’s outputs. These checkwords are sent to the VRD board every

50 ms where they are used to produce 50 ms worth of output. If any of these checkwords are not precisely correct, the VRD output is shut off and the external relay de-energizes.

3.3 OPERATION

The processing portion of the VRD board is based on an 8085 microprocessor chip with

4K of EPROM program memory and 4K of RAM. The RAM is shared with the main processing system and is the means by which the checkwords are transferred from the

CPU II board to the VRD board.

Once every second the main processing system delivers a new set of data called main checkwords to the VRD board. The VRD board processes these main checkwords and converts them to “tokens.” The VRD requires 20 tokens to operate for the next onesecond period. Every 50 ms the main processing system delivers a set of data called

“recheck checkwords” to the VRD. The VRD uses one token and the set of recheck checkwords to create an output signal for 50 ms. If any of the checkwords is incorrect or if the new checkwords are not delivered on time, the VRD output is lost.

The output of the processing portion of the VRD board (when all checkwords are correct) is a 10 kHz square wave modulated at 500-Hz. This signal passes through a 10 kHz tuned circuit and then a 500-Hz tuned circuit. The output of the 500-Hz tuned circuit is rectified and filtered to produce an isolated DC voltage to energize an Alstom Type B

100

Ω relay. Front contacts of this relay or its repeater(s) are used to feed output power to the Vital output boards. When the isolated DC voltage is removed and this relay drops, all Vital outputs of the system are de-energized.


VRD Board, P/N 59473-740-02

Figure 3–1. VRD Board Block Diagram


VRD Board, P/N 59473-740-02

The VRD board gives the main processing system three chances to deliver the new checkwords before shutting down the outputs. This is to allow for clock variations and variations in system timing. As part of the recheck checkword set, three dummy checkwords are sent to the VRD. These three checkwords cause the VRD to look for a new set of checkwords. The VRD creates a 46 ms output if the set of recheck checkwords it received is correct. It then creates an additional 2 ms output, using the first of the dummy checkwords. However, during a portion of this period, the VRD allows the main processing system to deliver a new set of checkwords. If the main processing system does not deliver the new checkwords, then the VRD uses the second dummy checkword and tries again 2 ms later. If it still does not receive the new set of checkwords by the third try, it has run out of checkwords and no longer produces the proper output.

The VRD program uses Safety Assurance Logic that does not change from system to system and cannot produce the correct output without the checkwords being correct.

The VRD requires that the checkwords received from the main processing system be different on each cycle.

3.4 STATUS OR ACTIVITY INDICATORS

This board has three LED indicators for use as troubleshooting aids, as shown in

Figure 3–2. The top indicator illuminates whenever the signal produced by the

processing portion of this board passes through the 10 kHz tuned circuit. The remaining two indicators illuminate during the exchange of handshaking controls between the VRD board and the main processing system. These controls are REQ/ and RDY/. During normal operation, each of these indicators turns on or off each time that their respective control line changes state. Depending upon system timing, one of these indicators may appear to be on all the time while the other appears to be off most of the time or these

LEDs may appear to flash alternately. If neither indicator flashes, then it means the main processing system and the VRD are not communicating with each other.

A 16-position control switch is located along the front edge of this board. This switch must be set to position F to allow the system to attempt a restart if the VRD relay deenergizes. As part of the restart procedure, the board runs a 7-second delay before it accepts any checkwords from the main processing system. If the processor halts or tries to operate in memory locations outside the allocated memory space, it is automatically reset. The system removes power from the outputs immediately in the event of a failure.

Note: If the control switch is in any position other than F, the system does not attempt to restart.


VRD BOARD

59473-740-XX

VRD Board, P/N 59473-740-02

NORMAL PCB

INDICATION NOTATION

FUNCTION

ON, MOST OF

THE TIME

CR5

VRD Board Is Outputting Drive To Relay, Does Not Verify Relay Is Up

FLASHING

FLASHING, MOST

OF THE TIME

SW2

CR2

CR1

RESET (VRD Reset Pushbutton)

REQ/ (MAIN CPU Finished Filling The VRD's Dual-Ported RAM WIth Checkwords)

RDY/ (VRD released Dual-Ported RAM To Get New Message From CPU)

Figure 3–2. VRD Board Edge


VRD Board, P/N 59473-740-02

3.5 TEST POINTS

See Figure 3–3 for the VRD board test point locations.

Table 3–1. VRD Board Test Points

TP1, TP2, TP3, TP4, TP5

Test Points used for factory test

Figure 3–3. VRD Board Switch and Test Point Locations


VRD Board, P/N 59473-740-02

3.6 SWITCHES

See Figure 3–3 for the VRD board switch locations and Figure 3–4 for the VRD board

SW1 switch setting.

VRD Reset

Pushbutton

F

A

C

E

6

4

2

Place Rotary

Switch in Position

"F" for Auto

Restart

Figure 3–4. VRD Board SW1 Switch Setting


VRD Board, P/N 59473-740-02

P3-

3

6

32

36


The VRD board has three card edge connectors:

• P3, the top connector, is a 36 -pin connector used to interface to the Vital energy disconnect relay

–

See Table 3–2 for power connection pins details; the remaining P3 pins are not

user configurable

• P2, the middle connector, is a 50 -pin connector used for system voltage and common

– P2-43 through P2-47 are wired in a specific pattern to common P2-48 per the application .lvc CAAPE report for board addressing; the remaining P2 pins are not user configurable

• P1, the lower connector, is a 60-pin connector that connects to the system bus; this connector is not user configurable

Table 3–2. VRD Board P3 Power Connections

Name

-OUT

+OUT

12VCOM

+12V

Function

Relay Coil -

Relay Coil +

Common

12 Volt +


VRD Board, P/N 59473-740-02

3.8 SPECIFICATIONS

Table 3–3. VRD Board Specifications

Specification

Maximum Number of Boards Per VPI System



VRD Drive Output Isolation

Minimum VRD Supply Voltage

Maximum VRD Supply Voltage

Typical VRD Drive Current Draw @ 12.00 V

59473-740-02

1

2

300 mA

>3000 Vrms

9.00 VDC

15.00 VDC

40 mA

WARNING

VPI II contains special safety circuit components which must only be replaced by components specified by the Alstom part number.

These original-design replacement parts are manufactured to the same standards as the original parts; their performance being verified. The use of replacement parts that are not of the same Alstom part number could potentially impair the safe performance of the system.

The railroad or transit system authority and the manufacturer of an aftermarket (i.e., non-Alstom designated) part assume the responsibility that the part will not adversely affect the safe performance of the system. The authority and the manufacturer of the aftermarket part must analyze and certify in writing that use of the part will not result in a failure of the system to comply with safety regulations and safety performance. Completion of such an analysis and certification is considered due diligence and standard practice, will not be reviewed or approved by Alstom, and neither absolves the authority and aftermarket part manufacturer of responsibility nor implies approval by Alstom to use such an aftermarket part. The responsibility of any consequences resulting from using such a part remains with the authority and part manufacturer.

Every Vital system requires at least one B relay which is operated by the VRD and through whose front contacts all the energy for the Vital outputs is broken. This relay must be, and must only be replaced by, an Alstom VRD Relay, part number 100 ohm B relay 56001-787-05.


VSC Board, P/N 59473-939-XX

SECTION 4 – VSC BOARD, P/N 59473-939-XX

4.1 INTRODUCTION

This section provides Vital Serial Controller (VSC) board detail.

4.2 GENERAL

The VSC board is a microprocessor-based board that provides a means for exchanging the states of up to 200 Vital interlocking functions (in each direction) between interlocking systems in a Vital manner. This communication is used between Vital systems within the train control room and from room to room for limited distances.

This board family was first designed to provide VPI to VPI Vital communications more efficiently than line wires. There are two types of data transmission interfaces; one for private copper pairs and one for generic, EIA232, DCE connection. A daughter board is used to provide the EIA232 connection, so the number of chassis slots required for this interface board is two (2).

Two additional applications of the VSC were created to provide a means of communicating to and from

• VPI and AF Track Circuit modules (MVSC)

• VPI and Programmable Genrakode modules (GVSC and GVSCE)

The system software installed on the Vital Serial Controller board is associated with a particular version of system software on the CPU II board. Each type of board, MVSC,

GVSC, or VSC, has its own unique Vital system software that is not interchangeable,

see Table 4–7 VSC Board Specifications.

When used for MVSC up to 450 Vital parameters can be transmitted in each direction.

The GVSC sends and receives up to 30 Vital parameters of information in its messages to each of a maximum of two Genrakode modules. Up to ten VSC boards or combinations of VSC, MVSC, GVSC, GVSCE, CRG (Code Rate Generator), and CSEX boards can be supported by a single Vital subsystem.

The application software is programmed with CAAPE, generating programs for

EPROMs (EPROM U18 P/N 01169-646-ON) for the up to ten VSC boards mentioned above.



4.3 OPERATION

The VSC is a VPI II system board that resides on the VPI system bus. Link information, in the form of system parameter values and checkwords, is provided from the VPI CPU system RAM over the system bus to dual-ported RAM (DPRAM) memory on the VSC.

The block of data, or message packet, is then moved under VSC control to the transmit processing RAM memory.

The transmit process converts message packet contents into two serial message components; an image field and a check field. The image field represents the true/false

(or permissive/non-permissive) state of each system parameter in the provided message block. The check field incorporates a combination of all link processing checkwords created up to this point in the link transfer. These fields, plus transmit/receive protocol flags, are formed into a Synchronous Data Link Control

(SDLC) protocol-like message and transmitted. SDLC is a simplified data transmission protocol developed by IBM designed to optimize transmission of data bits.

The receive process uses the image field to reconstruct a receive message packet with parameter values resembling those passed from the CPU II board to the VSC board at the transmit end. This reconstructed block of data, along with a receive link checkword, is passed to the CPU upon request. The receive link checkword includes all link checkwords created along the data path to this point.



4.4 COMMUNICATION

There are multiple versions of the VSC board:

• VSC board providing communication between two VPI II Systems

• MVSC board providing communication between a VPI II and an AF Track Circuit

Module

• GVSC board providing communication between a VPI II and Programmable

Genrakode (PGK)

• GVSCE board providing communication between a VPI II and Programmable

Genrakode (PGK); this board supports 50 Vital parameters returning from each module, up to 25 parameters for each track; the other VSC board types support 30

Vital parameters/15 from each track

Each type of board, MVSC, GVSC, GVSCE or VSC, has its own unique Vital system software that is not interchangeable and must be matched with specific versions of the

CPU II system software. The basic difference in the system software is the message structure used by each board. The MVSC, GVSC or GVSCE transmits a message containing 450 Vital parameters that is sent simultaneously to the various addressable

AF modules or PGK boards on the serial line. It then listens for responses from the modules, with 30 (50 for GVSCE) Vital parameters returning from each module. The

VSC, used for VPI-to-VPI communications, sends and receives up to 200 Vital parameters of information in its message.

Note: In the descriptions that follow, the term VSC is used generically to describe a Vital serial communication board of any of the types (MVSC, GVSC, GVSCE or VSC).

4.4.1 VSC Board, VPI to VPI Communication

One version of the VSC board is used to provide Vital serial communication from VPIto-VPI via a transformer coupled, proprietary communications protocol (P/N 59473-939

-10, -17) over two twisted pairs. When using appropriate cable, it is possible to communicate reliably over distances of four miles.

To communicate from one train control room to another over the fiber optic system, a different assembly version of VSC board is used. This VSC board (P/N 59473-939-11,

-18) contains a special interface board (P/N 31166-058-01), referred to as a “daughter board”, that is mounted on the VSC board itself. This daughter board contains an

EIA232 converter that allows the VSC board to interface directly with compatible line cards in T1 multiplexers and other standard communications equipment that may be part of an existing copper or fiber optic data transmission system.



CAUTION

When planning to use a data communications backbone to pass VSC messages between interlockings, confirm that the backbone protocols are able to deliver the complete message at the receiving end in 400 milliseconds.

If the reception exceeds 400 ms, all the message parameters are forced false.

4.4.2 VSC Board, VPI to AF Track Circuit Module Communication

Another version of the VSC was created to provide a means of communicating to and from AF Track Circuit modules. This Multi-Drop Vital Serial Controller (MVSC) board is capable of communicating by using vitally addressable destinations. Up to 15 AFTC modules may be multi-dropped on one serial line. The MVSC board (59473-939-12) hardware and operation are almost identical to the VSC.

4.4.3 GVSC Board, VPI to Programmable Genrakode (PGK) Board Communication

A different multi-drop version of the VSC is the Genrakode Vital Serial Controller

(GVSC) board. It is capable of communicating with up to two Programmable Genrakode

(PGK) boards on a 2-wire half-duplex line. This application allows for the communication of up to 15 parameters for each track. The GVSC board (59473-939-13) hardware and operation are almost identical to MVSC.

4.4.4 GVSCE Board, VPI to PGK Board Communication

Another multi-drop version of the VSC is the Genrakode Vital Serial Controller Extended

(GVSCE) board. It is capable of communicating with up to two Programmable

Genrakode (PGK) boards on a 2-wire half-duplex line. This version allows for the communication of up to 25 parameters for each track. The GVSCE board (59473-939-

14) hardware and operation are almost identical to GVSC and is required when a full implementation of Code T™ is needed.



4.5 COMMUNICATION PROCESS

The VSC is a system board that must reside on the VPI System bus. Link information in the form of system parameter values and checkwords is provided from the VPI CPU system RAM over the system bus to Dual Ported RAM (DPRAM) memory located on the VSC. The block of data (or message packet) is then moved, under VSC control, to the transmit processing RAM area.

The transmit process converts message packet contents into two serial message components: an “image field” and a “check field.” The image field represents the

TRUE/FALSE (or PERMISSIVE/NON-PERMISSIVE) state of each system parameter in the provided message block. The check field incorporates a combination of all link processing checkwords created up to this point in the link transfer. These fields, plus transmit/receive protocol flags, are formed into a message and transmitted.

The receive process uses the image field to reconstruct a receive message packet with parameter values resembling those passed from the CPU II board to the VSC board at the transmit end. This reconstructed block of data, along with a receive link checkword, are passed to the CPU upon request. The receive link checkword includes all link checkwords created along the data path to this point.

The CPU then retrieves the input message packet from the VSC DPRAM and places it in its input matrix. Processing is performed to combine the receive end CPU link checkwords with those provided from the VSC board. If all checkwords are correct and the path of the data is correct (e.g. origin in SYSTEM 1 CPU to destination in CPU of

SYSTEM 3), parameters directed to be in a TRUE state by the transmit end are allowed to assume the correct TRUE parameter value within the receive end CPU memory.

Otherwise, failures along the link path have occurred and all link parameters are forced into a FALSE (restrictive) state. These parameters are subsequently used as required during expression evaluation at the receiving end.

A maximum of ten VSC boards may be used in a VPI system supported by CAA 31746-

025 and later. These may reside in both the SYSTEM MODULE and EXPANSION

MODULE. The maximum number is dependent on the number of CRG and CSEX boards being used.



4.6 MEMORY TYPES

The VSC program and application memory is designed to be one of two types; 16K or

32K

× 8 bits, which is DIP switch selectable (SW4) board functions allocated to SW4 are

shown in Figure 4–8.

4.7

Note: Only the 16K x 8 bit memory size is currently supported.

STATUS AND ACTIVITY INDICATORS

Eleven LED indicators are provided on the VSC. Eight are multipurpose indicators for use with diagnostic software. Another indicator is assigned as a power supply voltage level monitor. An output of the watchdog timer IC drives the LED when the VSC board supply is below 4.6 VDC. Another indicator illuminates when the VSC is in a reset condition. A final indicator driven by the SCC (Serial Controller Chip) is used to display

serial link activity. Refer to Figure 4–1 for an illustration of the VSC board edge.



VSC BOARD

59473-939-XX

NORMAL PCB

INDICATION NOTATION

FUNCTION

J2

FLASHING, 1X PER SECOND

OFF

CR8

CR9

LINK ACTIVE (Serial Message Transmitted)

PWR SUP LOW (5VDC Power Low)


OFF



FLASHING*


FLASHING*

ON, AFTER APPLICATION

DATA RECEIVED

OFF

CR10

CR11

CR12

CR13

CR14

CR15

CR16

CR17

TP8

CR18

S3

TP10

* Rate of flashing depends on the number of line drop points.

VSC = 1 per second

MVSC = up to 15 per second

GVSC = up to 2 per second

GVSCE = up to 2 per second

MI8 (VSC Cycles)

MI7 (Unused)

MI6 (Transmit Data Received from CPU II Board)

MI5 (Transmit Messages are Formed)

MI4 (Serial Message Received)

MI3 (Data is Being Sent to CPU II Board)

MI2 (Recieved Message Data Processed)

MI1 (Power Up Application Data Received from CPU II Board)

+5V (+5V Test Point)

RESET (Reset is Activated)

MAN RESET (Reset Switch)

5VCOM (5V Common Test Point)

Figure 4–1. VSC Board Edge



4.8 COMMUNICATION INTERFACES

There are two different physical communications interfaces available in this board series. A direct wire interface that requires two copper pairs and an industry standard

EIA232 signal level interface for use with data communications equipment. The choice of interface is primarily an economic one, the Vital operation of the VSC link is not altered by the choice of physical interface. However, reliability of the communication link may be affected depending upon the choice made and the electrical environment.

4.9

4.9.1

DIRECT WIRE INTERFACE

Serial Communication Controller - Manchester Encoder-Decoder

The VPI-VPI link is controlled by one channel of a serial communications controller

(SCC) IC (82530 or 85C30). Data is provided to and from the SCC under interrupt control. Its output and input data is converted between non-return-to-zero (NRZ) and

Manchester format by a Manchester encoder/decoder (MED) device (6409). Data is provided in synchronous mode. Synchronous data link control (SDLC) format is used for this link interface.

4.9.2 Serial Link Interface

The VSC contains a full duplex interface for linking VPI-to-VPI. Baud rate is 19.2 K for standard applications. The serial data stream is converted from NRZ to a Manchester coding format. This format is such that each data bit cell contains a logic transition.

Therefore, a continual stream of logic ‘0’ data bits is not a constant signal level but rather a series of cycles each with a low to high transition in the center of the data bit.

Similarly, a continual stream of logic ‘1’ data bits has a high to low transition in the

center of the data bit interval. Refer to Figure 4–2 for a comparison between NRZ and

Manchester encoding. This signal is twice the frequency of the data bit stream provided by the USART. The advantage of this data format is that due to its continuous transitions, the signal can be used to power a transformer without a DC component. The

Manchester Encoder/Decoder also provides the benefit of message synchronization, clock recovery and noise immunity.

Figure 4–2. The Effect of Manchester Encoding on NRZ Data



4.10 DATA TRANSMISSION

The signal supplied by the MED is provided to an EIA422 driver. The EIA422 driver drives a transformer in differential mode. The voltage swing of the driver is 4 Vp-p

(typical).

The transformer interfaces with twisted pair communication links having a characteristic impedance of about 100

Ω at a signal frequency of 19.2 kHz. It provides isolation of the system 5V supply from external references. The transformer has a center-tapped secondary that allows for a 1:1 or a 1:2 turns ratio. For the transmit direction the 1:1 configuration is used. The VPI-VPI link uses two transformers for full duplex operation.

The receiver transformer uses the 1:2 transformer configuration to step up the incoming signal.

Jumpers in the transformer secondary can be used to modify the turn's ratio later if necessary. The secondary of the transformer interfaces with the twisted pair link via a line termination, transient suppression and low-pass filter network. A 100

Ω resistor terminates the twisted pair link in its characteristic impedance to minimize line reflections. Back-to-back transient suppressors clamp the link at 12V in either polarity.

The L-C low-pass filter in each leg of the link has a cutoff frequency of 100 kHz. This filter arrangement provides common mode and differential mode filtering. Also, 68 uH inductors serve as series resistive elements with the transient suppressor to limit current surges.

4.11 DATA RECEPTION

The VPI-VPI link receiver section uses the same transformer as the transmitter but converts the 4Vp-p signal to an 8 Vp-p on the secondary side that feeds the EIA422 differential receiver. The EIA422 receiver output provides a 5V logic representation of the differential signal to the MED. In the receive circuit, resistors provide hysteresis to minimize the effect of interference on the message data. The receiver responds to receive signals >

± 800 mV.



4.12 APPLICATION WIRING

The VSC uses a transformer-coupled twisted pair link as the medium of data exchange.

Serial link transmission distances of up to four miles are possible given that a suitable variety of twisted shielded cable is used and cable runs are separated from high power transmission cables. The recommended minimum conductor size to achieve the four mile distance is 16 AWG. Primary lightning protection is necessary for link runs that are accessible to lightning strikes, e.g., aerial runs, above ground duct banks, etc. The protection should be located as close to where the cable enters the house as practical.

The recommended cabling scheme for the VSC link is shown in Figure 4–3. Shielded

cable is not required for all installations. However, if shielded cable is used, the shield must be connected to earth ground at only one point. This point need not be at the same location as one of the two VPI systems. If a better ground is available at some other point on the cable run, e.g., a junction box, the shield may be grounded at that point.

Interlocking

A

A

Transmit

B

A

Receive

B

Ground at one end only Cable Shield

Interlocking

B

A

Receive

B

A

Transmit

B

Figure 4–3. VSC Link Cable and Shield Connections



4.13 DATA COMMUNICATIONS INTERFACE

The data communications interface is provided through the addition of a daughter board. The daughter board, P/N 31166-058-01, provides a galvanically isolated interface (optical) to the data communication equipment. This reduces the likelihood that circulating currents in possible ground loops with other equipment effect the operation of

the VPI electronics. See Figure 4–10 for the layout of the daughter board.

WARNING

When using assembly versions that include the daughter board an external power source must be provided. This energy source must not be a Vital energy or a non-Vital energy that cannot be connected to earth ground. This is because the communication equipment that the daughter board connects to usually connects signal common, for example ISOCOM, P3-36 (plug coupler H1), to earth ground.

4.14 DATA TRANSMISSION AND RECEPTION

When the daughter board is installed on the VSC board, it establishes connections to the SCC serial data lines and the connections that the SCC had to the Manchester encoder-decoder are severed. The message format is changed from synchronous to asynchronous. The asynchronous message format is one start bit, 8 data bits, no parity bit and two stop bits. The data transmission rate may be at either 9600 or 19200 bits per second. The data communication equipment used with this interface must be able to support this format.

WARNING

The features and capabilities of the data communication equipment must be carefully reviewed to insure that any message buffering or error correcting protocols do not insert significant delays in the message.

The VSC receiver must receive the complete message within 400 milliseconds from the point at which it recognizes the beginning of a message. If the message is not completely received within this 400 millisecond interval, the message parameters are forced to FALSE. While this is a safe-side failure, it may create operational issues in the movement of trains.



4.15 EXTERNAL POWER

To provide the isolated interface a power source must be provided to power the isolated electronics of the daughter board. An on-board power supply regulates the applied voltage to five volts for the interface electronics. This power supply does not provide isolation between the external source and the daughter board electronics. When selecting a source of this external power application, the engineer should be aware that the typical data communications equipment ties the serial data signal common to earth ground. Therefore, an energy source that cannot be grounded for any reason should not be used for this power connection. Often, the data communications equipment power supply has sufficient power available to provide power to the daughter board.

4.16 TEST POINTS

Figure 4–4 shows the VSC board test point locations, while Figure 4–5 is a similar

drawing of the VSC board with daughter board (T1) installed.

TP1 through TP5 and TP7 are not available on VSC boards with the daughter board

(T1) installed.

Table 4–1. VSC Board Test Points

Test Points

TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP9,

TP11

TP8

TP10 used in factory test

+5V, power

COM, common



SYSTEM

EPROM

APPLICATION

EPROM

Figure 4–4. VSC Board Test Point, Switch, Jumper, and EPROM Locations



Figure 4–5. VSC Board with T1 Adapter Board Test Point, Switch, and EPROM

Locations



4.17 ON-BOARD SWITCHES

There are four VSC board DIP switches, identified as S1, S2, S3, and S4. The following describes the switches and gives the function associated with each setting.

Note: If a 31166-058-01 daughter board is installed, the switches S1 and S2 must be set for -11 and -18 VSC boards. If an attempt is made to operate the board through the copper wire pair interface with a daughter board installed, the board does not operate properly.

Figure 4–4 and Figure 4–5 show the VSC board switch locations, without and with the

daughter board (T1 adapter board) installed.

4.17.1 S1

S1 contains DIP switches to configure handshake signals to the SCC. Figure 4–6 lists

the DIP switch 1 settings for the VSC board groups used in the VPI II system.



ON OFF

Board Group Switches ON Switches OFF

-10 (PT-PT Sync) 1, 2, 5, 6, 7 3, 4, 8

-17 (PT-PT Sync) 1, 2, 5, 6, 7 3, 4, 8

1

Switch Section

Indicates Side of

Switch that is Down

Board Group

-11 (PT-PT Async)

Switches ON

ALL

-12 (Multidrop Sync) ALL



-18 (Pt-Pt Async) ALL

ON OFF

Figure 4–6. VSC Board DIP Switch S1



Table 4–2. VSC Board DIP Switch S1 Functions

Switch

Position

1

2

3

4

5

6

7

8

Off On

Transmit Data Out Disabled

MED Transmit Sync Disabled

Non-Valid Manchester Code To

SCC-CTS\ Disabled

Not Used

Transmit Data Out Enabled

MED Transmit Sync Enabled

Non-Valid Manchester Code To

SCC-CTS\ Enabled

Not Used

Receive Data From MED Disabled Receive Data From MED Enabled

Transmit Clock From MED

Disabled

Transmit Clock From MED Enabled

Receive Clock From MED Disabled Receive Clock From MED Enabled

Not Used Not Used



4.17.2 S2

This 8-position DIP switch is used for future diagnostics and operational functions.

Figure 4–7 lists the DIP switch 2 settings for the VSC board groups used in the VPI II

system.

OFF ON


-11 (PT-PT Async, 19.2 KBAUD) 3, 4, 5, 6, 7, 8 1, 2

-18 (PT-PT Async, 19.2 KBAUD) 3, 4, 5, 6, 7, 8 1, 2

1

Switch Section

Indicates Side of

Switch that is Down OFF ON


-11 (PT-PT Async, 9600 BAUD) 3, 4, 5, 6 1, 2, 7, 8

-18 (PT-PT Async, 9600 BAUD) 3, 4, 5, 6 1, 2, 7, 8

OFF ON

Board Group

-10 (PT-PT Sync)

Switches ON

ALL




-17 (PT-PT Sync) ALL




Table 4–3. VSC Board DIP Switch S2 Functions

Switch

Position

Off On

1

2

3

4

5

6

7

8

Async data 1 enabled

Async data 2 enabled

Not used

Not used

Not used

Not used

9600 Baud select 1

9600 Baud select 2

Sync data 1 enabled

Sync data 2 enabled

19.2 K Baud select 1

19.2 K Baud select 2

Note: When operating in asynchronous mode, the message format is one start bit, 8 data bits, no parity bit and two stop bits. The communication equipment selected must be able to support this format.

The BAUD rate is selectable for Async mode only.S3

S3 is a VSC board reset switch.



4.17.3 S4

Memory select, reset inhibit, etc. Figure 4–8 shows the DIP switch 4 settings used for all

VSC board groups used in the VPI II system.

1 Switch Section

Indicates Depressed

Side of Switch

OFF

1 2 3 4

ON


Table 4–4. VSC S4 Miscellaneous Functions

Switch

Position

1

2

3

4

Off

Enable Auto Watchdog Reset

Memory Select 16K X 8 EPROM

(System, U16)


(Application, U18)

Select Alternate Reset Vector

Disable Reset

On


(System, U16)


(Application, U18)

Select Normal Reset Vector

WARNING

Although the VSC Board assembly is equipped with a 9-pin connector that is similar to that used by other processors for diagnostic information and access to internal status, there are no diagnostics available with this Board assembly. Attempts to access diagnostics on this assembly may result in interruption to the operation of the VSC functions and VSC parameters. This in turn may affect the operation of the interlockings that depend upon the

VSC parameters.



The following jumpers affect the operation of the direct wire interface only. When using the P/N 31166-058-01 daughter board they have no effect on the board operation. Refer

to Table 4–5 and Figure 4–4 for the location of the VSC board jumpers.

Table 4–5. Line Termination Jumpers for Copper Pair Interface

Jumper Installed

JU10

JU11

JU12

JU13

Yes

Yes

No

Yes

Function/Explanation

Connects the back-to-back junction of suppressors CR6 & CR7 to the logic common. This provides transient protection for the direct wire transmitter.

Connects the back-to-back junction of suppressors CR4 & CR5 to the logic common. This provides transient protection for the direct wire receiver.

Transmitter output level 1:2 (JU13 not installed)

Transmitter output level 1:1 (JU12 not installed)




The VSC Board has three card edge connectors:

• P3, the top connector, 36-pin connector wired to the isolated serial I/O for both VPI-

VPI and VPI-OTHER links

–

See Table 4–6 for 36 -pin configuration details

• P2, the middle connector, is a 50-pin connector wired to the VPI Motherboard that contains 5V power and system address programming

– P2-42 through P2-47 are wired in a specific pattern to common on P2-48 per the application .lvc CAAPE report for board addressing; the remaining pins are not user configurable

• P1, the lower connector, is a 60-pin connector wired to the system bus; this connector is not user configurable

When applied with a plug-coupled VPI chassis, connector P3, a 36-pin discrete wire PC edge connector, is wired to a 50-way connector on the back panel of a VPI module to permit use of a VSC standard cable. VSC edge connector, name, standard cable

coordinate and function are shown in Table 4–6.

WARNING

Although the VSC board assembly is equipped with a 9-pin connector that is similar to that used by other processors for diagnostic information and access to internal status, there are no diagnostics available with this board assembly. Attempts to access diagnostics on this assembly may result in interruption to the operation of the VSC functions and VSC parameters. This in turn may affect the operation of the interlockings that depend upon the

VSC parameters.

WARNING

When using assembly versions that include the daughter board an external power source must be provided. This energy source must not be a Vital energy or a non-Vital energy that cannot be connected to earth ground. This is because the communication equipment that the daughter board connects to usually connects signal common, for example ISOCOM, P3-36 (plug coupler H1), to earth ground.



P3 Pin

27

28

29

30

31

21

22

23

24

25

26

16

17

18

19

20

5

6

7

8

9

1

2

3

4

10

11

12

13

14

15

Table 4–6. VSC Board 36-pin P3 Connections (Cont.)

Name

VPITXA

VPITXB

VPIRCVA

VPIRCVB

ALT.SERIAL1

ALT.SERIAL2

INTERFACE OPT 1

INTERFACE OPT 2

INTERFACE OPT 3

INTERFACE OPT 4

INTERFACE OPT 5

INTERFACE OPT 6

INTERFACE OPT 7

50-Way

A3

G2

A5

G3

B1

B2

F4

C4

F5

A2

G1

F1

C2

F2

A4

F3

C1

B5

C3

D1

C5

D3

D2

D5

E5

E2

E1

E3

A1

E4

D4

Signal Function

VPI to VPI link transmit wire A

VPI to VPI link transmit wire B

(not used)

(not used)

VPI To VPI link receive wire A

VPI To VPI link receive wire B

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

(not used)

VPI to other XMIT/RCV LINK WIRE1

VPI to other XMIT/RCV LINK WIRE 2

(not used)

(not used)

TXD *

RTS *

DTR *

RXD *

CTS *

CD *

DSR *



Table 4–6. VSC Board 36-pin P3 Connections (Cont.)

P3 Pin Name 50-Way Signal Function

32

33

G4

B3

(not used)

(not used)

34

35 INTERFACE OPT 8

G5

B4

(not used)

IVCC (9-35VDC) *

36 INTERFACE OPT 9 H1 ISOCOM (Isolated Signal Common) *

* Indicates EIA232 signals from daughter board interface assembly -11 or -18 VSC board. Note: RTS, DTR, CTS, CD and DSR signals are not supported by the VSC system software. These signals should not be wired to any external equipment.



4.19 BOARD ASSEMBLY DIFFERENCES

The five versions of the VSC board that can be used with the VPI II system are

summarized in Table 4–7. All assemblies have a maximum board logic current supply

value of 500 mA.

Table 4–7. VSC Board Specifications

Ass’y

No.

10

11

12

13

14

17

18

Type

Pt - Pt

Pt.-Pt. with daughter board

Multi-drop full duplex 4-wire

Multi-drop half duplex 2-wire

Multi-drop half duplex 2-wire

Pt - Pt

Pt.-Pt. with daughter board

Maximum

# of

Boards Per

VPI

System

Board

Slots

Required

10 (Note 1) 1

Baud Rate

10 (Note 1)

2 (Note 2)

2 (Note 2)

2 (Note 2)

10 (Note 1)

10 (Note 1)

2

1

1

1

1

2

19200

(Sync.)

9600 or

19200

(Async.)

19200

(Sync.)

19200

(Sync.)

19200

(Sync.)

19200

(Sync.)

9600 or

19200

(Async.)

System

Software

Note 1: This limit is 10 minus the sum of (#VSC + #MVSC + #GVSC +

#GVSCE + #CRG + #CSEX), where # indicates the total number of a particular VPI board type.

Note 2: The total number of GVSCE + GVSC + MVSC combinations must be less than or equal to 2.

Note 3: Supports 15 parameters per track.

Note 4: Supports 25 parameters per track.

40025-322-00

VSC

40025-322-00

VSC

40025-323-00

MVSC (Note 3)

40025-324-00

GVSC (Note 3)

40025-348-00

GVSCE

(Note 4)

40025-406-00

VSC

40025-406-00

VSC



4.20 VSC DAUGHTER BOARD, P/N 31166-058-XX

Figure 4–9 provides a graph of Daughter board current versus voltage, while

Figure 4–10 shows the board layout.

WARNING

When using assembly versions that include the daughter board an external power source must be provided. This energy source must not be a Vital energy or a non-Vital energy that cannot be connected to earth ground. This is because the communication equipment that the daughter board connects to usually connects signal common, For example ISOCOM, P3-36 (plug coupler H1), to earth ground.

Required Current (amperes)

0.050

0.045

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

0.000

9 14 19 24 29

Supply Voltage (volts)

34

Figure 4–9. Daughter Board Current vs Voltage

39


Pin 1 End

Terminal

Block ID


Shorting Jumper

1 Switch Section

Indicates Side of

Switch that is Down

S1

A

1

B

4

Figure 4–10. VSC Daughter Board

For normal operation of the daughter board, all sections of S1 should be set in the “A” position. There are five (5) terminal blocks on the daughter board. These terminal blocks support special manufacturing and development functions and should not be altered in applying this assembly.

For their operating positions, refer to Table 4–8.

Table 4–8. Daughter Board Terminal Block Operating Positions

Terminal Block

TB1

TB2

TB3

TB4

TB5

Jumper Position

1-2

2-3

2-3

1-2

1-2





CRG Board, P/N 31166-261-XX

SECTION 5 – CRG BOARD, P/N 31166-261-XX

5.1 INTRODUCTION

This section provides Code Rate Generator (CRG) board detail.

5.2 GENERAL

The CRG board is a Vital VPI board that receives Vital commands from the CPU II board, generates codes outputs based on the commands, and transmits non-vital output status back to the CPU II board.

5.3 OPERATION

The CRG board receives code rate commands from the VPI CPU II board. The received code rate commands are decoded and used to generate 8 coded outputs. The frequency and duty-cycle of the coded outputs are vitally verified by using an Absence

Of Current Detector (AOCD). Data is circulated through the AOCD. Data returned from the AOCD coupled with other NISAL processing verifications are used to generate a message that the CRG board sends to the VPI CPU II board. The message received by the CPU II board from the CRG is used as part of the generation of the VRD checkwords. All outputs are generated using a Double Break Output (DBO) DC-DC converter and as such, are isolated from each other by >2000Vrms and protected from

undetected single-fault failures. A system block diagram is shown in Figure 5–1.



Serial

Terminal

RS-232

MASTER

PROCESSOR

VPI

ROCKER

SWITCH

7-SEGMENT

DISPLAYS

RS-422

MASTER

CO-PROCESSOR

SUPPORT_PLD

MASTER

CO-PROCESSOR

MASTER_PLD

WIRE

WRAP

A

WIRE

WRAP

B

WIRE

WRAP

BUFFERS

SRAM

FLASH

SRAM

FLASH

SLAVE CO-

PROCESSOR

SLAVE_A_PLD

SLAVE

A

PROCESSOR

Serial AOCD Data (2) & Code Rate Control (1)

Wire Wrap and 7-Segment Data (8)

Communications Data: VPI (4) - Serial Terminal (3)

Interrupts[3:0]

Wire Wrap Return Data (8)

VITAL

POWER

SWITCHES

SLAVE CO-

PROCESSOR

SLAVE_B_PLD

SRAM

FLASH

SLAVE

B

PROCESSOR

Rocker Switch Up/Down (2)

Master: Address[19:8] - Address/Data[7:0] - Bus Control

Slave: Address[15:0] - Address/Data[7:0] - Bus Control

Vital Power Control Switch Bits (8)

Interrupt Line

Code Rate Output (2)

Latched Address[7:0]

AOCD-

DBO A

AOCD-

DBO B

AOCD-

DBO C

AOCD-

DBO D

PORT

1

PORT

2

PORT

3

PORT

4

AOCD-

DBO A

AOCD-

DBO B

AOCD-

DBO C

AOCD-

DBO D

PORT

5

PORT

6

PORT

7

PORT

8



Figure 5–1. CRG Board Block Diagram

5.4 INDICATIONS

The CRG board has two displays, a rocker switch, and a reset switch, as shown in

Figure 5–2.

CRG BOARD

31166-261-XX

PCB

NOTATION

FUNCTION

TP1

TP2

TP3

TP11

S1

J1

TB7



PORT (Port Display, Shows Selected Output Port Number)


CODE RATE (Code Rate Display, Scrolls Through 3- Digit

Code Rate In ppm, pulses per minute)


Rocker Switch For Port Display Select

Receptacle

RESET (Reset Switch)

P2511B, Volume 3, Rev. C, Nov/13

Figure 5–2. CRG Board Edge

5-3 Alstom Signaling Inc.


5.5 ELECTRICAL RATINGS

The +5V power supply has a voltage range of 4.75V to 5.25V and typical operating current of 1.15A.

The +12V power supply (VRD energy) has a voltage range of 8V to 16V and a typical operating current on 0.5A.

5.6 OUTPUTS

The code rate outputs are sent through the P3 connector from a Solid State Driver or a

B-Relay Driver.

5.6.1 Solid State Relay Driver

The output circuit on a solid state driver is designed to drive a CRYDOM D241xx type

Solid State Relay. Because the relay itself is non-vital, with an operating current in the range of the Vital detection threshold of the AOCD (3mA), a parallel, wire-wound, established reliability resistor, mounted in a four-terminal configuration, is used to guarantee a minimum current draw of 4mA at the minimum turn-off voltage of the

CRYDOM relay (1V).

Nominal Operating Conditions (load 1500

Ω):

• Output Voltage: ~4.64V

• Output Current: ~3.1mA

Vital Pwr+

Vital Pwr -

Control In

AOCD

Data In

DBO & AOCD

Module

31166-117-01

AOCD

Data Out

390

1500pf

3000V

Vital Pwr -

243

Ohms,

2W

1500 ohm

SSR

Figure 5–3. Output Circuit Solid State Relay Driver



The values listed below are calculated considering worst case conditions. Component values and power supply voltages are chosen to yield a result at the extreme of the condition in question.

Load Short-Circuit:

• Max Current (16V into DBO-AOCD): ~50mA

• Min Current (8V into DBO-AOCD): ~24mA

Load Open-Circuit:

• Max Voltage (16V into DBO-AOCD): ~7.38V

• Min Voltage (8V into DBO-AOCD): ~3.29V

5.6.2 B-Relay Driver

The output circuit on a relay driver is designed to drive a typical B-style code following relay. The equations listed below allow for the computation of the output voltage and current as function of Vital power supply voltage and relay coil impedance.

Nominal Operating Conditions (VS = Vital Power Supply Voltage; RL = Coil

Impedance):

• Output Voltage: VOUT = VS*(1.2) - (~0.7)

• Output Current: IOUT = VOUT/RL

Vital Pwr+

Vital Pwr -

Control In

AOCD

Data In

DBO & AOCD

Module

31166-117-01

AOCD

Data Out

1500pf

3000V

Vital Pwr -

CF

Relay

Figure 5–4. Output Circuit B-Relay Driver



5.7 COMMUNICATIONS

Table 5–1. CRG Board Communications Specifications

Specification

Mode of Operation

Total Number of Drivers and Receivers on 1

Line

Maximum Cable Length

Maximum Data Rate

Maximum Driver Output Voltage

Driver Output Signal Level (loaded minimum)

Driver Output Signal Level (unloaded maximum)

Driver Load Impedance

Maximum Driver Current in High Z State

(power off)

Maximum Slew Rate

Receiver Input Voltage Range

Receiver Input Sensitivity

Receiver Input Impedance

Serial Port 1

(EIA232)

Single-ended

1 Driver

1 Receiver

50 ft.

20kb/s

± 25V

5V to 15V

± 25V

3kΩ to 7kΩ

± 6mA @ ± 2V

30.0V/цs

± 15V

± 3V

3kΩ to 7kΩ

Serial Port 0

(EIA422)

Differential

1 Driver

10 Receivers

4000 ft.

10Mb/s

-0.25V to +6V

± 2V

± 6V

100Ω

± 100цA

N/A

-10V to +10V

± 200mV

4kΩ min.



5.8 TEST POINTS

Figure 5–5 shows the CRG board test points and switches.

Table 5–2. CRG Board Test Points

TP1, TP9

TP2, TP11

Test Points

COM, common

+5V, power

TP3, TP4, TP5, TP6, TP7, TP8, TP10,

TP12 through TP38 used in factory test



Figure 5–5. CRG Board Test Point and Switch Locations



P3-

14

15

16

17

18

8

9

10

11

12

13

1

2

3

4

5

6

7


The CRG board has three card edge connectors:

• P3, the top connector, is a 36-pin connector which contains wiring for code rates 1 through 8 and Vital power connections

–


• P2, the middle connector, is a 50-pin connector used for connections to the motherboard which supplies 5 Volt power and common; this connector is not user configurable

• P1, the lower connector, is a 36-pin connector which contains wiring for check ids and serial links

–


– The ID pins on P1 are wired in a specific pattern per the application .lvc CAAPE report for board addressing

Table 5–3. CRG Board 36-pin P3 Connections (Cont.)

Name

CODE_RATE_8-

CODE_RATE_8+

CODE_RATE_7-

CODE_RATE_7+

CODE_RATE_6-

CODE_RATE_6+

CODE_RATE_5-

CODE_RATE_5+

CODE_RATE_4-

CODE_RATE_4+

Function

Code Rate 8

Code Rate 8

(not used)

(not used)

Code Rate 7

Code Rate 7

(not used)

(not used)

Code Rate 6

Code Rate 6

(not used)

(not used)

Code Rate 5

Code Rate 5

(not used)

(not used)

Code Rate 4

Code Rate 4



P1-

1

2

3

4

5

6

7

P3-

23

24

25

26

27

19

20

21

22

28

29

30

31

32

33

34

35

36


Name

CODE_RATE_3-

CODE_RATE_3+

CODE_RATE_2-

CODE_RATE_2+

CODE_RATE_1-

CODE_RATE_1+

VPC+

VITAL_POWER-

VPC+

VITAL_POWER-

Function

(not used)

(not used)

Code Rate 3

Code Rate 3

(not used)

(not used)

Code Rate 2

Code Rate 2

(not used)

(not used)

Code Rate 1

Code Rate 1

(not used)

(not used)

Vital Power +

Vital Power Common

Vital Power +

Vital Power Common


Name

GEN_OUT_A0

GEN_OUT_A1

GEN_OUT_A2

GEN_OUT_A3

GEN_OUT_A4

GEN_OUT_A5

GEN_OUT_A6

Function

Generated Output A0

Generated Output A1

Generated Output A2

Generated Output A3

Generated Output A4

Generated Output A5

Generated Output A6



P1-

23

24

29

30

31

32

33

34

35

36

12

13

14

15

16

8

9

10

11

17

18

19

20

21

22


Name

GEN_OUT_A7

CHECK_ID2_0

CHECK_ID2_1

CHECK_ID2_2

CHECK_ID2_3

CHECK_ID2_4

CHECK_ID2_5

CHECK_ID2_6

CHECK_ID2_7

CHECK_ID1_0

CHECK_ID1_1

CHECK_ID1_2

CHECK_ID1_3

CHECK_ID1_4

CHECK_ID1_5

CHECK_ID1_6

CHECK_ID1_7

CRG_VPI-

CRG_VPI-

CRG_VPI+

CRG_VPI+

VPI_CRG-

VPI_CRG-

VPI_CRG+

VPI_CRG+

Function

Generated Output A7

ID Check 2_0

ID Check 2_1

ID Check 2_2

ID Check 2_3

ID Check 2_4

ID Check 2_5

ID Check 2_6

ID Check 2_7

ID Check 1_0

ID Check 1_1

ID Check 1_2

ID Check 1_3

ID Check 1_4

ID Check 1_5

ID Check 1_6

ID Check 1_7

CRG to VPI -

CRG to VPI -

CRG to VPI +

CRG to VPI +

VPI to CRG -

VPI to CRG -

VPI to CRG +

VPI to CRG +



5.10 BOARD ASSEMBLY DIFFERENCES

The maximum board logic current supply for all versions is 1200 mA.

Table 5–5. CRG Board Assembly Differences

Ass’ y No.

Output

Driver

Maximum # of

Boards per VPI

System

Board

Slots

Required

Program

Numbers

Code Rates

Supported

(Pulses Per Minute)

03 Solid State 3 1 40025-235

0, 50, 75, 120, 180

(Parameters 6-10 are not used)

0, 50, 75, 120, 180,

270, 420, Steady On

04 B-Relay 3 1 40025-325

(Parameters 9-10 are not used)

See Table A– 1 located in Appendix A (CRG Application Guidelines) of Alstom

Publication P2511B, Volume 5 for rate parameter assignment details.



5.11 BOARD ASSEMBLY CODE RATES – RATE TOLERANCE

The tolerance data summarized in Table 5–6 is required when applying the CRG board.

Nominal PPM

50

75

120

180

270

420

Table 5–6. CRG Board Assembly Code Rate Tolerances

Actual PPM

50.0

75.0

120.0

181.8

272.7

428.6

On-Time ms

600

400

250

165

110

70

Off-Time ms

600

400

250

165

110

70





IOB Board, P/N 59473-827-XX

SECTION 6 – IOB BOARD, P/N 59473-827-XX

6.1 INTRODUCTION

This section provides I/O Bus Interface (IOB) board detail.

6.2 GENERAL

The IOB board serves as a buffer between the system processing boards and Vital I/O.

It provides a storage medium for test data obtained during Vital input and output port checks. The board includes logic to control the continuous verification of Vital output port states.

6.3 OPERATION

Figure 6–1 shows the IOB interface block diagram.

P3 Expansion

Bus

P1 System

Bus

Expansion Bus

Buffers

Redundancy

Transfer Logic

Select

Expansion

Bus

Address, Control &

Data Buffers

Supergroup

Address Decoding

Read Shift Reg.

Controls

Input/Output Control

Decoder

16 x 18 Bit Serial to Parallel Shift

Register

Supergroup

Signature Header

2 MHz

XTAL

Crystal Controlled

Output Verification

Logic

Vital I/O Bus Buffers

(Motherboard)

Add (4), Data (16)

Control (11)

P2

Motherboad

I/O Bus

Figure 6–1. IOB Board Block Diagram



Address, control and data signals are buffered for use within the IOBUS logic. While address and control buffers are always enabled, the data buffers are only active when the IOBUS is specifically addressed.

A 7-bit address decoder compares a system bus address with that programmed for the slot in which the interface board resides (slot address inputs are labeled ADD SEL 0, 1,

2, 3). A particular bus interface board and its associated I/O are referred to as a supergroup. If bus and slot address agree, the SUPERGROUP SELECTED signal enables the data buffers. If the bus address for Vital I/O is greater than that programmed for the system module interface board, then the EN EXP DBUS control signal is generated to allow data to be obtained from expansion I/O modules in multimodule configurations.

The IOBUS logic provides buffering for links between the main system module and all expansion modules via five octal buffers and a 60-way cable. Actual data transfers occur only when the external data bus is enabled from the main system module, by jumpering P2-35 to P2-48 on the IOBUS board. The EN EXP DBUS signal is permanently disabled for interface boards in expansion modules by inserting a jumper between the proper pins on the Motherboard. The system module expansion bus can drive several expansion I/O modules.

Expansion bus buffer logic supports usage of redundant systems; that is, two sets of system electronics in a system module and Vital I/O in expansion modules. An opticallyisolated input (SEL EXP BUS), derived from redundancy transfer logic, activates either of the two sets of redundant system electronics, with each having an I/O bus interface board. A 24V signal at SEL EXP BUS allows one of the two sets of system redundant electronics to communicate with the expansion I/O bus via the buffered expansion bus.

When the SEL EXP BUS signal is removed, signaling a system failure, the SEL EXP

BUS input is energized on the spare interface board to allow the backup set of system electronics to communicate to the Vital I/O. Vital input and output functions are controlled through memory-mapped address operations. An input/output control decoder employs three address bits to perform four tasks. The first control (YIN) represents a signal that is later gated with a read or write control when operations involving Vital inputs are performed.

The second control (YADR-YSR), when gated with a write control, sets the I/O group address latch. It is also gated with a read control to enable the reading of the bank of 16 shift registers.

The third control (YOF) signifies a write operation to Vital output boards (output state control latches), while the fourth control (YSM) is used to clock the mode latch used in output state verification.

The Vital I/O group address latch is buffered and is used to address each Vital I/O slot on the Motherboard (I/O bus) bus.



6.4 VITAL CONTINUOUS OUTPUT VERIFICATION (50 MS RECHECK CYCLE)

Output state verification is performed by a crystal controlled logic sequence and a mode latch. Data representing a desired function are loaded into the mode latch with the YSM signal. The mode latch performs one of five functions:

1. Selects mode of output verification (recheck)

2. Initiates selected mode

3. Clears logic for subsequent operations

4. Enables the highest 8 sequence/counter stages

5. Selects between an even or an odd recheck cycle

The board contains a 2-MHz crystal that drives a 14-stage counter. Function timing is controlled using specific counter stages. One output, a 125 kHz signal, is used for data modulation and another is used for the output recheck clock. Outputs of the mode latch, gated with different counter outputs, perform these functions:

• Read mode 1: the data in output board RAM is read into the shift registers (SR

LOAD) as 8 serial bits, 16 bits wide and processed four times to obtain the 32-bit check data word for each output.

• Write mode 2: fills all RAM on the output boards with logic ones as an initialization process. Control signal CLR CNTR is generated in this mode while the recheck clock is disabled.

• Circulate mode 3: the circulate mode occurs 45 out of every 50 ms. The recheck clock is provided during this time to all output boards causing output port check data to be circulated and stored. Control signals C1 and C2 control this operation for even and odd recheck cycles.

• Circulate mode 4: this is the same as circulate mode 3 except that the circulation process is interrupted after 1 ms. At this time the output state may be changed to enforce special output checks, for example, hot and cold filament checks.

The 16-bit I/O data bus forwards data derived from input port tests, output port tests and

Vital timer operation to a serial input of each register, which is shifted in 8-bit blocks.

The registers are then accessed by the main CPU where the data is retrieved in parallel format.



Each register’s serial input is dedicated to an I/O data bus line. This allows the system to access 16 Vital inputs or Vital outputs. Data is loaded into the register either by a read operation (INTMRD) with YIN active or by the output verification logic. The registers are accessed by a memory read operation with YADR-YSR active. A 3-to-8 decoder provides a register pair output enable signal based on the state of three address bits, when registers are read by the CPU.

Data derived from outputs is connected directly to the register shift left input. Input test data, however, is obtained from the I/O bus and routed through a SIGNATURE header.

This header possesses 16 input-to-output path assignments, the output of which is connected to each of the 16 register shift right inputs. Each header takes as an input a certain data bus line and swaps it with another. For example, header input is data bus 1 and output is routed to data bus 9, which is tied to shift register 9. This scrambling of the data bus when reading Vital input data is used to verify correct Vital input addressing.

IOBUS logic controls the Vital I/O bus that communicates over the system Motherboard.

It provides buffered outputs for board addressing (IOAB1-4), data passage via bidirectional data bus (IODB0-F), read and write data controls, output recheck controls, and memory mapped controls for communicating with a Vital timer (T-OUTC3, TIMC4).

T-OUTC3 also accesses the low current output check circuitry on a lamp drive output board.



6.5 INDICATORS

The two IOB board LED indicators are shown in Figure 6–2.

IOB BOARD

59473-827-XX

NORMAL PCB

INDICATION NOTATION

FUNCTION

FLASHING

FLASHING

CR20

CR1

SR LOAD (Data From Inputs Or Outputs Is Loaded In Shift Registers)

SR READ (Data In Shift Registers Is Read By CPU)


Figure 6–2. IOB Board Edge



SIGNATURE HEADER

Figure 6–3. IOB Board Interface Connections and Signature Header Locations




The IOB Board has three card edge connectors.

• P3, the top connector, is a 60 pin connector containing the buffered main bus used to drive expansion I/O modules

• P2, the middle connector, is a 50-pin connector that carries board power and address selection signals; connects to the motherboard which supplies 5 Volt power and common

– P2-35 and P2-44 through P2-47 are wired in a specific pattern to common P2-

48 per the application .lvc CAAPE report for board addressing; the remaining

P2 pins are not user configurable

• P1, the lower connector, is a 60-pin connector containing the main address, data, and control bus for the VPI system

Note: The expansion bus is used in applications where more than one module is required to handle Vital or Non Vital I/O. It interfaces to either an I/O Interface Bus Board, VSC Board, or a CSEX board



6.7 SPECIFICATIONS

Table 6–1. IOB Board Bus Interface Specifications

Specification




Signature Header 59473-871-01




59473-827-01

4

1

300 mA

Board 1

Board 2

Board 3

Board 4


DI Board, P/N 59473-867-XX

SECTION 7 – DI BOARD, P/N 59473-867-XX

7.1 INTRODUCTION

This section provides Direct Input (DI) board detail.

7.2 GENERAL

DI boards contain 16 isolated Vital inputs, each requiring two connections to the field (-

IN and +IN). The inputs are DC current sensing and require a minimum of 12.8 mA. The maximum input current is 33 mA. Two inputs may be connected in parallel with opposite polarity (input A+ connected to input B-, and input A- connected to input B+) to form a bipolar input (except for board 59473-867-03).

Each input has an LED indicator that is on when the input is on (current flow from +IN to

-IN terminals). Input circuit indicators are placed in sequence from 1 to 16 corresponding to inputs 1 to 16 (counting from the top of the board down). The board has two other indicators: the first one (the top one of the two located in the middle of the board near the board edge) is on for about 100 ms when data is read from the board.

The second one (the lower of the two in the middle of the board) is on for about 100 ms when data is written to the board. These indicators flash once each second when the system is operating normally.

Each DI board interfaces with the data bus through a signature header. This signature header is created on the boards by a programming plug inserted in the socket labeled

IC35. When a system is configured, a specific signature is assigned to each input slot. If an input board is changed, the correct signature must be inserted in the new board for that slot. The correct signature for that slot is listed on the module cover. The Alstom drawing number for the signature header is 59473-871 (see Appendix A for more information).

Figure 7–1 shows a DI board block diagram. The input circuitry provides a means of

safely reading the presence of a DC voltage at the field terminals of the input and converting it to a form usable by the main processing system. In the same way that a

Vital relay makes its front contacts if, and only if, power is applied to its coil, this input circuitry allows its true, or on, status to be displayed to the main processor (via a digital word) if, and only if, power is applied to its input terminals. In this scheme, all circuit failures result in the input being interpreted as off (or false), which is the more restrictive condition.



ADDRESS

SELECT

ADDRESS

ADDRESS

DECODER

+IN

WRITE

LOGIC

A B

I/O

BUS

-IN

READ

LOGIC

16 ISOLATED INPUTS

1 OF 16 TYPICAL

SIGNATURE

Figure 7–1. DI Board Block Diagram

All 16 inputs on a DI board are read at once by sending a serial bit stream to each input, one bit at a time, and then reading the results. The system outputs the first bit of the serial bit stream to each of the 16 inputs. It then reads the result of these bits at the output of each of the 16 inputs. Then the system outputs the second bit until the entire bit stream has been sent to the inputs and the results read back. The resultant bit pattern, called a word, represents the status of that input. The serial bit streams sent to the inputs are unique for each input and, therefore, the word that results (when an input is on) is unique for that input. For an input that is off, the returned word contains all zeroes.

Since this is a serial process, the resultant data is presented to the main processor in a serial form. The main processor cannot efficiently use the data in this form. Therefore, the resultant data is stored in shift registers on the I/O bus interface board and then is read by the main processor in a parallel process. This process is done in 8-bit segments because the shift registers are 8 bits long. Thus, the first 8 bits of the serial-bit stream are transmitted to the inputs one bit at a time and the resultant bits are stored in the shift registers.



Special attention is given to the reading of input checkwords to prevent induced AC from causing incorrect input sensing. This AC noise immunity is obtained by vitally spacing the reading of adjacent 8-bit segments of the 32-bit checkwords. Spacings of 7,

12 and 7 ms between 8-bit segments 1-2, 2-3 and 3-4 (respectively) are used.

Each input is read twice using two different 32-bit words (one word for each of the two processing channels). At the completion of this operation, only those inputs that are sensing current produce the correct 32-bit word in both channels for the CPU to use in evaluating the expressions.

7.3 OPERATION

The presence of a ‘0’, or low, on the write logic output line(s) causes opto-isolator A to

turn on, see the block diagram in Figure 7–1. When this isolator turns on, its output

transistor effectively diverts the current away from the input of opto-isolator B, causing its output to turn off. This in turn places a ‘1’, or high, on the input to the read logic.

Similarly, if the write logic output is a ‘1’, the resultant input to the read logic is ‘0’. If there is no current flow (from the field) between the +IN and -IN terminals, then there is no current at the input of opto-isolator B to be diverted to the output transistor of isolator

A. Thus, the output of isolator B remains in a high ‘1’ state all the time. Because the circuit has additional transistor stages, the returned data for an “off” input contains all zeros. The field input for each of these inputs contains a low-pass filter comprised of a

22 mFd capacitor and a 267

Ω resistor. The purpose of this filter is to attenuate induced

AC signals.

7.4 INDICATORS

Figure 7–2 shows the 18 DI board LED indicators. The sixteen input indicators (IN#) are

driven directly from the voltage supplied to the input terminals. This provides a quick way to verify the state of an input.



DI BOARD

59473-867-XX

NORMAL PCB

INDICATION NOTATION

FUNCTION

OFF, ON

OFF, ON

CR3

CR5

IN#1 (Input #1)

IN#2 (Input #2)

OFF, ON

OFF, ON

CR6

CR8

IN#3 (Input #3)

IN#4 (Input #4)

OFF, ON

OFF, ON

CR10

CR11

OFF, ON

OFF, ON

CR13

CR15

IN#5 (Input #5)

IN#6 (Input #6)

IN#7 (Input #7)

IN#8 (Input #8)

FLASHING, BUT MOSTLY OFF

FLASHING, BUT MOSTLY OFF

OFF, ON

OFF, ON

CR17

CR18

TP4

TP5

CR21

CR23

RD (Data Is Being Read From Input Board)

WR (Data Is Being Written To The Input Board)


DR (Test Point)

IN#9 (Input #9)

IN#10 (Input #10)

IN#11 (Input #11)

IN#12 (Input #12)

OFF, ON

OFF, ON

CR24

CR26

OFF, ON

OFF, ON

CR28

CR29

OFF, ON

OFF, ON

CR31

CR33

IN#13 (Input #13)

IN#14 (Input #14)

IN#15 (Input #15)

IN#16 (Input #16)

The above LEDS light when energy is applied to external input.

Figure 7–2. DI Board Edge



7.5 ADDRESS SIGNATURE HEADER

Appendix A lists the address signature headers' drawing number and signature letter used for board address definition with the VPI system.

7.6 TEST POINTS

Table 7–1 lists the DI board test points and Figure 7–3 shows the test point locations.

TP1

TP2

TP3

TP4

TP5

Table 7–1. DI Board Test Points

Test Points

AD, board addressed for read or write function

SN, read operation to board

+5V, power

COM, common

DR, write operation to board



P3

AD

TP1

SN

TP2

+5V

TP3

COM

TP4

DR

TP5

SIGNATURE HEADER

P2

P1

Figure 7–3. DI Board Test Points and Signature Header Locations



P3-

12

13

14

15

16

17

18

19

1

2

3

4

5

6

7

8

9

10

11


The DI Board has three card edge connectors.

• P3, the top connector, is a 36-pin connector that connects inputs 1 through 8

–


• P2, the middle connector, is a 50-pin connector that carries power, address and

Vital I/O data

– P 2-44 through P2-47 are wired in a specific pattern to common P2-48 per the application .lvc CAAPE report for board addressing; the remaining P2 pins are not user configurable

• P1, the lower connector, is a 36-pin connector that connects inputs 9 through 16

–


Table 7–2. DI Board 36-pin P3 Connections (Cont.)

Name

IN-5

IN+5

IN-4

IN+4

IN-8

IN+8

IN-7

IN+7

IN-6

IN+6

Function

Input 8 - V

Input 8 +V

(not used)

(not used)

Input 7 - V

Input 7 +V

(not used)

(not used)

Input 6 - V

Input 6 +V

(not used)

(not used)

Input 5 - V

Input 5 +V

(not used)

(not used)

Input 4 - V

Input 4 +V

(not used)



P3-

24

25

26

27

28

20

21

22

23

29

30

31-36


Name

IN-3

IN+3

IN-2

IN+2

IN-1

IN+1

Function

(not used)

Input 3 - V

Input 3 +V

(not used)

(not used)

Input 2 - V

Input 2 +V

(not used)

(not used)

Input 1 - V

Input 1 +V

(not used)

P1-

7

8

9

10

11

12

13

1

2

3

4

5

6



Name

IN-16

IN+16

IN-15

IN+15

IN-14

IN+14

IN-13

Function

Input 16 - V

Input 16 +V

(not used)

(not used)

Input 15 - V

Input 15 +V

(not used)

(not used)

Input 14 - V

Input 14 +V

(not used)

(not used)

Input 13 - V


P1-

18

19

20

21

22

14

15

16

17

23

24

25

26

27

28

29

30

31-36



Name

IN+13

IN-12

IN+12

IN-11

IN+11

IN-10

IN+10

IN-9

IN+9

Function

Input 13 +V

(not used)

(not used)

Input 12 - V

Input 12 +V

(not used)

(not used)

Input 11 - V

Input 11 +V

(not used)

(not used)

Input 10 - V

Input 10 +V

(not used)

(not used)

Input 9 - V

Input 9 +V

(not used)



7.8 SPECIFICATIONS / ASSEMBLY DIFFERENCES

Table 7–4. DI Board Specifications/Assembly Differences

Specification

Maximum Number of Boards

Per VPI System


Maximum Board Logic

Current Supply

Minimum Input Voltage/Port

-867-

01

9.0

VDC

15.0

VDC

-867-

02

59473

-867-03

-867-

04

9.0

VDC

15.0

VDC

20

1

300 mA

9.0

VDC

15.0

VDC

1700 Vrms

45.0

VDC

55.0

VDC

-867-

05

9.0

VDC

22.0

VDC

Maximum Input Voltage/Port

Input Transient Protection

Voltage (Max Voltage)

Input Transient Protection

Energy (Max Energy)

Isolation Between Inputs

Address Signature Header

Required

Equipped with Low-Pass

Filter

Momentary Input Hold

Yes

No

No

No

3.6 Joules

> 3000 Vrms

Yes

No

Yes

(see

Warning

)

Yes

No

Yes

No

-867-

07

24.0

VDC

34.0

VDC

Yes

No

WARNING

The 59473-867-03 assembly input circuit possesses the ability to rectify AC signals and is intended for special situations only. Consult Alstom on its use.


Vital DC Output Boards, P/N 59473-739-XX, -747-XX, -977-XX, -749-XX, 31166-340-XX

SECTION 8 – VITAL DC OUTPUT BOARDS, P/N 59473-739-XX,

-747-XX, -977-XX, -749-XX, 31166-340-XX

8.1 INTRODUCTION

This section provides Vital DC output board detail.

8.2 GENERAL

There are five types of Vital DC Output boards: Single Break Output (SBO) P/N 59473-

739-XX, Double Break Output (DBO) P/N 59473-747-XX, Double Break Output 50 V

(DBO-50V) P/N 59473-977-XX, Lamp Driver Output (LDO) P/N 59473-749-XX, and

Lamp Driver Output 2 (LDO2) P/N 31166-340-XX. All are configured with 8 Vital outputs per board. The single break output is analogous to a single relay contact placed in the positive or feed side of the circuit. The equivalent to the relay contact in the solid state circuit is the FET switch. The double break output is analogous to a relay circuit with the contacts in both the feed and return sides of the circuit. With the solid-state equivalent, however, each output is completely isolated from all other outputs and/or power supplies.

WARNING

Board specification tables are provided in the individual output board discussions. Each table includes the minimum required application load current data specific to that board. This specification must be followed for the board to function properly.



8.3 OPERATION

Ten LED indicators are on each output board. The top indicator lights for about 50 ms every time data is read from the board. Under normal conditions, this indicator appears to be “on” all the time because the main processing system reads the output check data from the output boards every 50 ms. The second indicator lights for 50 ms every time data is written to this board. Since the system does this once per second (twice for flashing outputs), this indicator flashes once or twice per second under normal conditions. The remaining 8 indicators represent the status of the 8 outputs. Each indicator lights only when the system requests the associated output to turn on. The third indicator from the top of the board is for output number 1 and the last indicator on the board is for output number 8.

Eight outputs on each board are divided into two groups of four. Outputs 1-4 are connected to one power supply input, while outputs 5-8 are connected to a second power supply input. These power supply inputs may be connected to different power supplies or they may be tied together external to the VPI module. If the outputs are being used in a Vital application, the power supply must come from a source that can be vitally turned off (usually a contact of the VPI Vital relay or one of its repeaters).

Each output board is assigned a Signature PROM (see Appendix A for more information) that contains a unique set of data for each of the outputs on that board.

These data are tied into the board addressing and are used to prove that there are no addressing failures. They are also used by the output check circuitry to prove the status of the output. When an output board is changed, this PROM must be changed to the new board. If an output board is missing its PROM or contains a wrong PROM, the system does not operate.

Figure 8–1 shows a block diagram of the Vital DC Output boards.



ADDRESS

SELECT

ADDRESS

ADDRESS

DECODER

I/O

BUS

WRITE

LOGIC

READ

LOGIC

RECHECK

DRIVE LOGIC

+5 +V

8 OUTPUTS

AOCD

A

OUT

TYPICAL SINGLE BREAK

RECHECK

LOGIC (PD)

SEL

HI/LOW

BUS SELECT

AOCD

+V

+5

DC/DC

CONVERTER

TYPICAL DOUBLE BREAK

+

OUT

-

A

AOCD

OUT

+5

+5

FILAMENT CHECK

(1st RCK Cycle, 1mS)

TYPICAL LIGHT DRIVE

- BATT.

Figure 8–1. Vital DC Output Board Block Diagram



For these boards, the outputs are turned “on” by writing a ‘1’ to the output and turned

“off” by writing a ‘0’. The main processing system controls the status of the outputs by setting the data bus lines to the data pattern corresponding to the desired output on/off status and writing that data to the output board. Since the system has a 16-bit wide data bus, 16 outputs can be updated at once.

To accomplish this, two output boards are given the same address and:

• one board is connected to the lower half of the data bus

• one board is connected to the upper half

For the board on the lower half of the bus, output 1 corresponds to data bus line 0 and output 8 to data bus line 7. For the board on the upper half, output 1 corresponds to data line 8 and output 8 is data line F.

Besides turning the outputs on and off, the VPI system checks each output to ensure it is in the correct state. To do this, each output circuit monitors its output current flow.

This circuitry, called an Absence Of Current Detector (AOCD), passes a digital signal if, and only if, the current in its output winding is less than a specified level.

Each output board contains the necessary logic to circulate a digital word through the

AOCD, read the resultant word at the output of the AOCD, divide it by a preset polynomial, and store the result. Every 50 ms the main processor reads the result of this process. If the output is in the off state, the result indicates that there was no current flow for the entire 50 ms period.

WARNING

VPI users must confirm that output device current requirements are consistent with AOCD current threshold characteristics.



A systematic breakdown of this circuit's operation follows:

• Each output board has a unique signature header that is a 32 × 8 PROM

(39780-003-XX). The PROM contains 8 32-bit words arranged vertically. These words are clocked serially through the AOCD associated with each output at a rate of 1 bit every 128

µs.

• The 32-bit word is cycled through the output's AOCD 11 consecutive times. This requires 11

× 32 × 128 µs = 45,056 µs.

• All serial data streams circulated through each of the 8 AOCDs are compressed into

8 32-bit words in RAM (which is made up from two 256

× 4 RAMs). The compressed data appear vertically in the RAM.

• The data are compressed via 8 individual polynomial dividers that operate simultaneously; each polynomial has an even and an odd cycle, they alternate as a set between even and odd every 50 ms (they are all even or all odd at once)

• At the end of a verification cycle the value of a particular 32-bit vertical result in

RAM is the correct value if, and only if both of the following two statements are true:

– there were no failures in the AOCD circuitry

– the current in the AOCD output winding was below the specified threshold for the entire verification period

• For a given output, the unique 32-bit result depends on the polynomial used during the verification cycle:

– the polynomial used is pe(x) for even 50 ms recheck cycles and po(x) for odd

50 ms recheck cycles

– by using different polynomials on adjacent recheck cycles, it proves that the 32bit result was calculated during the current 50 ms and not left over from a previous recheck period

• The data compression in RAM is accomplished by manipulating the RAM to simulate a 32-bit feedback shift register that represents the desired polynomial

The RAM address PROM is 512

× 8 and it is divided into four 128 × 8 sections. Two of the sections contain the address sequences that represent the two diverse primitive polynomials. The remaining two sections contain the address sequences needed to read the collected compressed data from the RAM and the sequence needed to initialize the RAM to all “ones”. The RAM is initialized at the beginning of each recheck cycle.

Control logic for synchronizing and clocking this circuitry is contained on the I/O Bus

Interface board.



Operation of this circuitry is divided into four modes:

1. READ MODE: In the read mode, the data from the RAM is read. Since the read data is stored vertically in RAM, each group of 8 bits represents one bit of each of the 8 words. This data is serially clocked into shift registers on the I/O Bus Interface board. Each shift register receives one bit for each read operation. After 8 read operations, a particular shift register contains 8 of the 32 bits of a particular output's checkword. The shift register data is then stored in the CPU memory. This process continues until the entire 32-bit word is read and stored for all the outputs.

2. WRITE MODE: In this mode, the RAM is filled with all “ones”.

3. CIRCULATE MODE (11): In this mode, the even or odd polynomial is selected depending on which recheck cycle is in process and the 32-bit words are cycled through the AOCD circuitry 11 times.

4. CIRCULATE MODE (1): This mode circulates the first 8 bits of the 32-bit word through the AOCD circuitry and then stops. This allows the state of the output to be changed, after which circulate mode 11 is invoked to complete the recheck cycle.

Special tests can be run on selected outputs, such as a hot or cold lamp filament check. The returned 32-bit word obtained by this mode of operation is unique and indicates that the desired test was performed correctly.

Note: When this test is required for current and filament checking, a wire wrap jumper is installed between pins 35 and 36 on the

Motherboard in the slot for that output board.



8.4 INDICATORS

Figure 8–2 through Figure 8–6 show the SBO, DBO, DBO-50, LDO, and LDO2 board

edges, including LED indicators.

SBO BOARD

59473-739-XX

NORMAL PCB

INDICATION NOTATION

FUNCTION

FLASHING, MOSTLY OFF


OFF, ON, FLASHING

CR10

CR9

CR8

RD (Recheck data Is Being Read From The Board)

WR (Output Ports Are Being Updated)

CH1 (Output #1)

OFF, ON, FLASHING CR7 Output #2

OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

CR6

TP2

CR5

TP1

CR4

OFF, ON, FLASHING CR3

Output #3


Output #4


Output #5

Output #6


OFF, ON, FLASHING CR1 CH8 (Output #8)

CR1 - CR8 Light when output is commanded to be on by the CPU

Figure 8–2. Vital Output SBO Board Edge



DBO BOARD

59473-747-XX

NORMAL PCB

INDICATION NOTATION



OFF, ON, FLASHING

CR1

CR2

CR10

FUNCTION



CH1 (Output #1)






Output #5

Output #6


OFF, ON, FLASHING

TP7

TP8

CR3



CH8 (Output #8)

CR3 - CR10 Light when output is commanded to be on by the CPU.

Figure 8–3. Vital Output DBO Board Edge



DBO-50V BOARD

59473-977-XX

NORMAL PCB

INDICATION NOTATION



OFF, ON, FLASHING

CR1

CR2

CR3

FUNCTION



CH1 (Output #1)


OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

CR5

E1

CR6

E2

CR7


Output #3


Output #4


Output #5

Output #6




Figure 8–4. Vital Output DBO-50V Board Edge



LDO BOARD

59473-749-XX

NORMAL PCB

INDICATION NOTATION



OFF, ON, FLASHING

CR1

CR2

CR10

FUNCTION



CH1 (Output #1)



OFF, ON, FLASHING

OFF, ON, FLASHING

CR7

TP2

CR6

OFF, ON, FLASHING

OFF, ON, FLASHING

CR5

TP1

CR4

Output #4


Output #5

Output #6


Output #7



Figure 8–5. Vital Output LDO Board Edge



LDO2 BOARD

31166-340-XX

NORMAL PCB

INDICATION NOTATION

OFF DS1

S3

FUNCTION

ERROR (Error)

CLEAR (Clear Switch)

S5

DS2

Toggle Switch

Output Number Display

OFF,ON, FLASHING

OFF,ON, FLASHING

OFF,ON, FLASHING

OFF,ON, FLASHING

OFF,ON, FLASHING

OFF,ON, FLASHING

OFF,ON, FLASHING

OFF,ON, FLASHING

DS3

DS4

DS9

DS10

DS11

DS12

DS5

DS6

DS7

DS8

OFF when configuration is complete

S13

DS13

Parameter Data Display

Parameter Data Display

OUT1 (Output #1)

OUT2 (Output #2)

OUT3 (Output #3)

OUT4 (Output #4)

OUT5 (Output #5)

OUT6 (Output #6)

OUT7 (Output #7)

OUT8 (Output #8)

RESET (Reset Switch)

CONFIG (Config Is Being Accessed)

Figure 8–6. Vital Output LDO2 Board Edge



8.5 SBO DETAILS

The single break output is analogous to a single relay contact placed in the positive or feed side of the circuit. The equivalent of the relay contact in the solid-state circuit is the

FET switch. Figure 8–7 shows the SBO board block diagram.

Iout

+

V

IN

-

SBO

LOAD

Figure 8–7. Single Break Output Block Diagram

8.5.1 SBO Board Test Points

Table 8–2 lists the SBO board test points and Figure 8–8 shows the test point locations.

Table 8–1. SBO Board Test Points

Test Points

TP1

TP2

TP3, TP4, TP5 TP6, TP7, TP8, TP9

+5V, power

COM, common used for factory test



Figure 8–8. SBO Board Test Point and Signature PROM Locations



P3-

33

34

35

36

22

23

24

25

26

27 -

32

1

2

3 - 8

9

10

11 -

20

21

8.5.2 Card Edge Connectors

The SBO Board has three card edge connectors.

• P3, the top connector, is a 36-pin connector for Channels 1 through 4

–



Vital I/O data

– P2-42 or P2-43 are wired to P2-40 and P2-44 through P2-47 are wired in a specific pattern to common P2-48 per the application .lvc CAAPE report for board addressing; the remaining P2 pins are not user configurable

• P1, the lower connector, is a 36-pin connector for Channels 5 through 8

–


Table 8–2. SBO Board 36-pin P3 Connections

Name

OUTV1COM

+OUT4

OUTV1COM

+OUT3

Function

Vital Power Common

Output 4

(not used)

Vital Power Common

Output 3

(not used)

OUTV1COM

+OUT2

OUTV1COM

+OUT1

OUTV1COM

+V1

Vital Power Common

Output 2

(not used)

(not used)

Vital Power Common

Output 1

(not used)

Vital Power Common

Vital Power V+

(not used)

(not used)


P1-

1

2

3 - 8

9

10

33

34

35

36

24

25

26

27 -

32

11 -

20

21

22

23


Table 8–3. SBO Board 36-pin P1 Connections

Name

OUTV2COM

+OUT8

OUTV2COM

+OUT7

Function

Vital Power Common

Output 8

(not used)

Vital Power Common

Output 7

(not used)

OUTV2COM

+OUT6

OUTV2COM

+OUT5

Vital Power Common

Output 7

(not used)

(not used)

Vital Power Common

Output 7

(not used)

OUTV2COM

+V2

Vital Power Common

Vital Power V+

(not used)

(not used)



8.5.3 Specifications

Maximum Number of Boards Per VPI II System


Number of Ports per Board


Minimum Switched Output Supply Voltage (Vin)

Maximum Switched Output Supply Voltage (Vin)

Typical Output Voltage Drop

Maximum Switched Power

AOCD Current Threshold

Maximum Output Current Per Port (Iout)

Isolation Between Outputs and 5 Volt Logic

Address Signature PROM Required

Code Energy Switching

Group Energy Filtered

Table 8–4. SBO Board Specifications

Specification

59473-739

-01 -02

No

Yes

40

1

8

500 mA

9.0 VDC

30.0 VDC

1.0 VDC

15 watts

3 mA max

500 mA

> 3000 Vrms

Yes

Yes

No

WARNING

The SBO board may fail with up to 3 milliamperes of output leakage current with the system requesting the output to be in the de-energized state. To prevent a potential unsafe condition, any load device attached to a low current vital output circuit board must not operate and must de-activate above 3 milliamperes. This includes all environmental operating conditions and all operating values of the load device over its service life. Failure to follow this requirement may lead to unexpected operation of the load device.



8.5.4 Assembly

Table 8–5. SBO Board Assembly

Description

SBO Board Assembly, 8 outputs (9 - 15 VDC)

Group energy is filtered

SBO Board Assembly, 8 outputs (9 - 15 VDC)

Group energy is not filtered, supports use of coded energy

Signature PROM

(one for each output board in a system, determined by CAA)

Part Number

59473-739-01

59473-739-02

39780-003-01 through

39780-003-40



8.6 DBO AND DBO-50V DETAILS

The double break output is analogous to a relay circuit with the contacts in both the feed and return sides of the circuit. With the solid-state equivalent, however, each output is completely isolated from all other outputs and/or power supplies. Each output is isolated by using individual DC/DC converters that meet or exceed AREMA isolation

requirement. Figure 8–9 shows the DBO board block diagram.

+

Iout

V

IN

-

DBO

Vout

LOAD

Figure 8–9. DBO Board Block Diagram

8.6.1 DBO and DBO-50V Board Test Points

See Figure 8–10 for DBO board test point locations and Figure 8–11 for DBO-50V

board test point locations.

Table 8–6. DBO Board Test Points

TP1, TP2, TP3, TP4, TP5

TP7

TP8

Test Points used for factory test

+5V, power

COM, common

E1

E2

Table 8–7. DBO-50V Board Test Points

Test Points

+5V, power

COM, common



SIGNATURE

PROM

Figure 8–9. DBO Board Test Point and Signature PROM Locations



P3

P2

SIGNATURE PROM

P1

Figure 8–10. DBO-50V Board Test Point and Signature PROM Locations



P3-

1

2

3 - 8

9

10

11 - 20

21

22

23

24

25

26

27 - 32

33

34

35

36


The DBO and DBO-50 Boards have three card edge connectors.


–

See Table 8–8 for DBO 36-pin configuration details

–

See Table 8–10 for DBO-50 36-pin configuration details


Vital I/O data



–

See Table 8–9 for DBO 36-pin configuration details

–

See Table 8–11 for DBO-50 36-pin configuration details

Table 8–8. DBO Board 36-pin P3 Connections

Name

OUT4-

OUT4+

OUT3-

OUT3+

OUT2-

OUT2+

OUT1-

OUT1+

OUTCOM1

OUTV1

Function

Output 4 -V

Output 4

(not used)

Output 3 -V

Output 3

(not used)

Output 2 -V

Output 2

(not used)

(not used)

Output 1 -V

Output 1

(not used)

Vital Power Common

Vital Power V+

(not used)

(not used)


P1-

1

2

3 - 8

9

10

33

34

35

36

24

25

26

27 -

32

11 -

20

21

22

23


Table 8–9. DBO Board 36-pin P1 Connections

Name

OUT8-

OUT8+

OUT7-

OUT7+

Function

Output 8 -V

Output 8

(not used)

Output 7 -V

Output 7

(not used)

OUT6-

OUT6+

OUT5-

OUT5+

Output 6 -V

Output 6

(not used)

(not used)

Output 5 -V

Output 5

(not used)

OUTCOM3

OUTV3

Vital Power Common

Vital Power V+

(not used)

(not used)


P3-

1

2

3 - 8

9

10

33

34

35

36

24

25

26

27 -

32

11 -

20

21

22

23


Table 8–10. DBO-50 Board 36-pin P3 Connections

Name

OUT4-

OUT4+

OUT3-

OUT3+

Function

Output 4 -V

Output 4

(not used)

Output 3 -V

Output 3

(not used)

OUT2-

OUT2+

OUT1-

OUT1+

Output 2 -V

Output 2

(not used)

(not used)

Output 1 -V

Output 1

(not used)

50VCOM1

V1

Vital Power Common

Vital Power V+

(not used)

(not used)


P1-

1

2

3 - 8

9

10

33

34

35

36

24

25

26

27 -

32

11 -

20

21

22

23


Table 8–11. DBO-50 Board 36-pin P1 Connections

Name

OUT8-

OUT8+

OUT7-

OUT7+

Function

Output 8 -V

Output 8

(not used)

Output 7 -V

Output 7

(not used)

OUT6-

OUT6+

OUT5-

OUT5+

Output 6 -V

Output 6

(not used)

(not used)

Output 5 -V

Output 5

(not used)

50VCOM2

V2

Vital Power Common

Vital Power V+

(not used)

(not used)




Table 8–12. DBO/DBO-50 Board Specifications

59473-

Description

747-01 747-02 747-03 977-01 977-02

Maximum number of Output

Boards per VPI II System

Board slots required

Number of ports per board

Maximum Board Logic

Current Supply

Maximum Output Power per

Port

Typical AOCD operating threshold

9 W

3 mA

9 W

3 mA

40

1

8

500 mA

Minimum Input Voltage (Vin) 9 VDC 9 VDC 9 VDC 30 VDC 45 VDC

Maximum Input Voltage (Vin) 15 VDC 15 VDC 15 VDC 40 VDC 55 VDC

Minimum Output Voltage

(Vout)

Maximum Output Voltage

(Vout)

Maximum Output Current per Port (Iout)

6 VDC

15 VDC

600 mA

17.7

VDC

34.5

VDC

300 mA

6 VDC

15 VDC

600 mA

45 VDC

55 VDC

140 mA

45 VDC

55 VDC

140 mA

9 W

3 mA

7.7 W

3 mA

7.7 W

3 mA

Isolation Between Outputs

Signature PROM Required

> 3000

Vrms

Yes

> 3000

Vrms

Yes

> 3000

Vrms

Yes

> 3000

Vrms

Yes

> 3000

Vrms

Yes

WARNING

The DBO board may fail with up to 3 milliamperes of output leakage current with the system requesting the output to be in the de-energized state. To prevent a potential unsafe condition, any load device attached to a low current vital output circuit board must not operate and must de-activate above 3 milliamperes. This includes all environmental operating conditions and all operating values of the load device over its service life. Failure to follow this requirement may lead to unexpected operation of the load device.



8.6.4 Assemblies

Table 8–13. DBO Board Assemblies

Description

DBO Board Assembly, 8 outputs

(9 - 15 VDC operation)

Note: Not for new designs since board keying is the same as that for 747-02 assembly

DBO Board Assembly, 8 outputs with doubled output voltage

(9 - 15 VDC in with 18 - 30 VDC output)



Note Preferred for new designs since board keying is different than that for 747-02 assembly





Signature PROM


Part Number

59473-747-01

59473-747-02

59473-747-03

59473-977-01

59473-977-02

39780-003-01 through

39780-003-40



8.7 LDO DETAILS

The lamp drive output circuit handles high current to light signal lamps. Each output circuit can accommodate hot and cold filament checks. This output uses a FET switch in the common or return line of the circuit. Therefore, it is necessary to supply the positive

side of the battery or signal lighting supply to the signal lamps. Figure 8–12 shows the

LDO board port interface block diagram.

LOAD

Iout

+

V

IN

LDO

-

Figure 8–11. LDO Board Port Interface

8.7.1 LDO Board Test Points

Table 8–14 lists the LDO board test points and Figure 8–13 shows the test point

locations.

Table 8–14. LDO Board Test Points

Test Points

TP1

TP2

TP3, TP4, TP5, TP6, TP7, TP8, TP9

+5V, power

COM, common used for factory test



Figure 8–12. LDO Board Test Point and Signature PROM Locations



P3-

33

34

35

36

22

23

24

25

26

27 -

32

1

2

3 - 8

9

10

11 -

20

21


The LDO Board has three card edge connectors.


–



Vital I/O data; this connector is not user configurable

– P2-35, P2-36, P2-40, P2-42, P2-43 and P2-44 through P2-48 are wired in a specific pattern per the application .lvc CAAPE report for board addressing; the remaining P2 pins are not user configurable


–


Table 8–15. LDO Board 36-pin P3 Connections

Name

OUTV1COM

+OUT4

OUTV1COM

+OUT3

Function

Vital Power Common

Output 4

(not used)

Vital Power Common

Output 3

(not used)

OUTV1COM

+OUT2

OUTV1COM

+OUT1

OUTV1COM

+V1OUT

Vital Power Common

Output 2

(not used)

(not used)

Vital Power Common

Output 1

(not used)

Vital Power Common

Vital Power V+

(not used)

(not used)


P1-

1

2

3 - 8

9

10

33

34

35

36

24

25

26

27 -

32

11 -

20

21

22

23


Table 8–16. LDO Board 36-pin P1 Connections

Name

OUTV2COM

+OUT8

OUTV2COM

+OUT7

Function

Vital Power Common

Output 8

(not used)

Vital Power Common

Output 7

(not used)

OUTV2COM

+OUT6

OUTV2COM

+OUT5

Vital Power Common

Output 6

(not used)

(not used)

Vital Power Common

Output 5

(not used)

OUTV2COM

+V2OUT

Vital Power Common

Vital Power V+

(not used)

(not used)




Table 8–17. LDO Board Specifications

59473-

Description

749-02 749-03 749-04

Maximum number of Output Boards per

VPI II System




Minimum Switched Output Supply

Voltage (Vin)

Maximum Switched Output Supply

Voltage (Vin)


Typical Output Voltage Drop

Typical AOCD operating threshold

Isolation Between Outputs and 5 Volt

Logic

Hot/Cold Filament Check


9 VDC

18 VDC

2.0 A

40

1

8

500 mA

15 VDC

30 VDC

2.9 A

1.7 VDC

50 mA

> 3000 Vrms

Yes, 100 mA Yes, 200 mA

Yes

9 VDC

18 VDC

2.9 A

Hot 100 mA, no Cold

WARNING

The LDO board may fail with up to 50 milliamperes of output leakage current with the system requesting the output to be in the de-energized state. To prevent a potential unsafe condition, any load device attached to a high current vital output circuit board must not operate and must de-activate above 50 milliamperes. This includes all environmental operating conditions and all operating values of the load device over its service life. Failure to follow this requirement may lead to unexpected operation of the load device.



8.7.4 Assemblies

Table 8–18. LDO Board Assemblies

Description

LDO Board Assembly, 8 outputs

(9 - 18 VDC, 2.9 Amp. operation)





Signature PROM


Part Number

59473-749-02

59473-749-03

59473-749-04

39780-003-01 through

39780-003-40



8.8 LDO2 DETAILS

The lamp drive output 2 circuit handles high current to light signal lamps. Each output circuit can accommodate hot and cold filament checks. This output uses a FET switch in

the common or return line of the circuit. Figure 8–14 shows the board interface.

+

Iout

V

IN

LDO2

LOAD

-

Figure 8–13. LDO2 Board Port Interface

In addition to the LDO board features, the LDO2 board has the following features:

• A Cable Integrity Check that uses isolated voltage sensing at the output to determine if a potential exists across the output when the output is off. A separate switch for each output can be used to select the system reaction to this event (log the error or drop the VPI II Vital Relay).

Switch S4 switches 1-8 correspond to outputs 1-8 respectively. Enable position drops VRD if an external potential exists. Disable position does not drop VRD if an external potential exists.

• A Diagnostic Interface to VPI II CPU II board that registers all current readings and error conditions and can be read or cleared via the CPU II board.

• A Board Edge User Interface that registers all current readings and error conditions and can be read or cleared via a Board Edge User interface.

• A Current Monitor that reads the current through the output approximately every

200 milliseconds. This current can be compared to one of 8 different threshold levels (0.0, 0.55, 0.75, 0.95, 1.25, 1.55, 2.05, or 3.25 Amps) to turn the output off if it is not drawing the minimum required current. The use of the VPI II filament checking routines enables downgrading and prevents upgrading to signals that are not drawing the required current. The outputs are also guarded against overcurrent and short protection.

Note: The Current Monitor is not provided on P/N 31166-340-02.



8.8.1 LDO2 Board Test Points

TP1 though TP42 and TP44 are located on the front side of the board, while TP43 and

TP45 through TP78 are located on the back side of the board. See Figure 8–15 for

LDO2 board test points located on the front of the board.

Table 8–19. LDO2 Board Test Points

TP3, TP39

TP5, TP36

TP7, TP13, TP27, TP40

TP17

TP29

TP1, TP2, TP4, TP6,

TP8 - TP12, TP14 - TP16, TP18 - TP26,

TP28,

TP30 - TP35, TP37, TP38, TP40 - TP78

Test Points

+5V, power

-V1

COM, common

+V1

+V2 used in factory test



Figure 8–14. LDO2 Board Test Point and Switch Locations



8.8.2 LDO2 Board Switches

See Figure 8–15 for LDO2 board switch locations.

Table 8–20. LDO2 Board Switches

Switches

S7

S8

S9

S10

S11

S1

S2

S3

S4

S5

S6

LCTH-1

LCTH-2

Clear

CIC VRD Drop

Toggle Switch

LCTH-3

LCTH-4

LCTH-5

LCTH-6

Tens

Ones

S12

S13

LCTH-7

Reset

S14 LCTH-8

Switches 1, 2, 6, 7, 8, 9, 12, and 14 are used to select the Low Current Threshold

(LCTH). LCTH Switch locations are shown in Figure 8–15; an example selection dial is

shown in Figure 8–16. Table 8–21 summarizes the switch settings.

9

LCTH-1

0

1

8 2

7 3

6 4

5

Figure 8–15. LCTH Selection Dial



Table 8–21. LCTH Switch Settings

Threshold Switch Setting

0.0A

0.55A

0.75A

0.95A

SW=0 Low Current Detection Disabled

SW=1

SW=2

SW=3

1.25A

1.55A

SW=4

SW=5

2.05A

3.25A

0.0A

SW=6

SW=7

SW=8 Low Current Detection Disabled

0.55A SW=9 (same as SW=1)

Switches 10 and 11 are used to select the appropriate AOCD PROM Group as specified by the compiled application (group 01 through 40). The switch locations are shown in

Figure 8–15; selection dials are shown in Figure 8–16.

9

TENS

0

1 9

ONES

0

1

8 2 8 2

7 3 7

6

5

S10

4 6

5

S11

4

Figure 8–16. AOCD Selection Dials

3



P3-

33

34

35

36

22

23

24

25

26

27 -

32

1

2

3 - 8

9

10

11 -

20

21

8.8.3 Card Edge Connections

The LDO2 Board has three card edge connectors.


–



Vital I/O data

– P2-35, P2-36, P2-40, P2-42, P2-43 and P2-44 through P2-48 are wired in a specific pattern per the application .lvc CAAPE report for board addressing; the remaining P2 pins are not user configurable


–


Table 8–22. LDO2 Board 36-pin P3 Connections

Name

+V1OUT

OUT4

+V1OUT

OUT3

Function

Vital Power V+

Output 4+

(not used)

Vital Power V+

Output 3+

(not used)

+V1OUT

OUT2

+V1OUT

OUT1

-V1OUT

+V1OUT

Vital Power V+

Output 2+

(not used)

(not used)

Vital Power V+

Output 1+

(not used)

Vital Power Common

Vital Power V+

(not used)

(not used)


P1-

1

2

3 - 8

9

10

33

34

35

36

24

25

26

27 -

32

11 -

20

21

22

23


Table 8–23. LDO2 Board 36-pin P1 Connections

Name

+V2OUT

OUT8

+V2OUT

OUT7

Function

Vital Power V+

Output 8+

(not used)

Vital Power V+

Output 7+

(not used)

+V2OUT

OUT6

+V2OUT

OUT5

Vital Power V+

Output 6+

(not used)

(not used)

Vital Power V+

Output 5+

(not used)

-V2OUT

+V2OUT

Vital Power Common

Vital Power V+

(not used)

(not used)



8.8.4 Specifications/Assembly Differences

Table 8–24. LDO2 Board Specifications

31166-

Description

Maximum number of Output Boards per VPI II System




Minimum Switched Output Supply Voltage (Vin)

Maximum Switched Output Supply Voltage (Vin)


Maximum Output Current per 4-port group

Typical Output Voltage Drop on board

Cable Integrity Check Detection Voltage

Over Current Shutdown Threshold (t = 200 to 400 mS)

Low level current detection threshold range

AOCD operating threshold

Isolation Between Outputs and 5 Volt Logic

Hot/Cold Filament Check


340-01 340-02

40

1

8

350mA

8 VDC

18 VDC

3.3 A

7.5 A

1 V

2.0 ±0.3 V

4.0 A

0.55 to 3.25 in 7 steps

40

1

8

250mA

8 VDC

18 VDC

3.3 A

7.5 A

1 V

2.0 ±0.3 V none none

100 mA 100 mA

> 3000 Vrms > 3000 Vrms

Yes, 100 mA Yes, 100 mA

No No

WARNING

The LDO2 board may fail with up to 50 milliamperes of output leakage current with the system requesting the output to be in the de-energized state.

To prevent a potential unsafe condition, any load device attached to a high current vital output circuit board must not operate and must de-activate above 50 milliamperes. This includes all environmental operating conditions and all operating values of the load device over its service life. Failure to follow this requirement may lead to unexpected operation of the load device.



8.8.5 Assemblies

Table 8–25. LDO2 Board Assemblies

Description

LDO2 Board Assembly, 8 outputs


LDO2 Board Assembly, 8 outputs w/o current monitor


Part Number

31166-340-01

31166-340-02





ACO Board, P/N 59473-937-XX

SECTION 9 – ACO BOARD, P/N 59473-937-XX

9.1 INTRODUCTION

This section provides Vital AC Output (ACO) board detail.

9.2 GENERAL

The Vital ACO board operates in a manner similar to Vital Output boards. It is used for lighting signal lamps or for operating other AC loads requiring less than 0.8 ampere.

The board has 8 outputs divided into two groups of four. Outputs 1 through 4 are connected to one power supply input while outputs 5 through 8 are connected to a second power supply input. In Vital applications, these power supply inputs are connected to a source that can be vitally turned off (usually a contact of the VPI Vital relay or one of its repeaters).

9.3 OPERATION

The ACO board has three main modes of operation: READ, WRITE and CIRCULATE:

• READ MODE: in the read mode, the data from the RAM is read. Since data is stored vertically in the RAM, each group of 8-bits represents one bit of each of the 8 words. This data is serially clocked into shift registers on the I/O Bus Interface board. Each shift register receives one bit for each read operation. After 8 read operations, a particular shift register contains 8 of the 32-bits of a particular output checkword. The shift register data is then stored in CPU memory. This process continues until the entire 32-bit word is read and stored for all of the outputs.

• WRITE MODE: in the write mode, the RAM is filled with all “ones”.

• CIRCULATE MODE: In the circulate mode, the even or odd polynomial is selected depending on which recheck cycle is in process and the 32-bit words are cycled through the AOCD circuitry 11 times.

Figure 9–1 shows a block diagram of the Vital AC Output board. The outputs of this

board are turned on by writing a ‘1’ to the output and turned off by writing a ‘0’. The main processing system controls the status of the outputs by setting the data bus lines to the data pattern corresponding to the desired output on/off status and writing that data to the output board. Because the system has a 16-bit wide data bus, 16 outputs can be updated at once. To do this, two output boards are given the same address and

• one board is connected to the lower half of the data bus

• the other is connected to the upper half

For the board on the lower half of the bus, output 1 corresponds to data bus line 0 and output 8 is data line 7. For the board on the upper half, output 1 is data line 8 and output

8 is data line F.



Figure 9–1. ACO Board Block Diagram



Besides turning the outputs on and off, the circuit must verify each output is in the correct state. To check the outputs, each individual output contains PROM-defined

AOCD circuitry that monitors its output current flow. The AOCD PROM chip (see

Appendix A for more information) is designated U12. The AOCD passes a digital signal if, and only if, the current in its output winding is less than a specified level. Each output board contains the necessary logic to circulate a digital word through the AOCD, read the resultant word at the output of the AOCD, divide it by a preset polynomial and store the result. Every 50 ms the main processing system reads the result of this process. If the output was supposed to be in its off state, the result indicates there was current flow less than 50 mA for the entire 50 ms period.

WARNING

VPI users must confirm that output device current requirements are consistent with AOCD current threshold characteristics.

LAMP

VIN

(AC)

`

ACO

Iout

Figure 9–2. ACO Board Port Interface



9.4 INDICATIONS

Figure 9–3 shows the ACO board edge, including indications.

ACO BOARD

59473-937-XX

NORMAL PCB

INDICATION NOTATION

FUNCTION



OFF, ON, FLASHING

CR1

CR2

CR3



CH1 (Output #1)




OFF, ON, FLASHING

OFF, ON, FLASHING

CR7

E1

CR8

Output #5


Output #6


E2 5V COM (5V Common Test Point)



Figure 9–3. ACO Board Edge



9.5 JUMPER CONFIGURATIONS

In the system module, the ACO board's address is established by wire wrapping selected terminals P2-44, P2-45, P2-46 and/or P2-47 to 5V common.

When a wire wrap jumper is installed between PC2-40 and PC2-42, the board in that slot is connected to the lower data bus. When the jumper is installed between PC2-40 and PC2-43, the board is connected to the upper data bus.

9.6 TRANSIENT PROTECTION

To prevent interference from transients and other local noise, this board contains EMI and MOV filters on the outputs and capacitive filters in the power supply circuitry. These filters are very effective in combating interference when combined with good earth grounding of the VPI system.

9.7 TEST POINTS

See Figure 9–4 for ACO board test point locations.

E1

E2

Table 9–1. ACO Board Test Points

Test Points

+5V, power

COM, common



SIGNATURE PROM

Figure 9–4. ACO Board Test Point and PROM Locations



P3-

33

34

35

36

22

23

24

25

26

27 -

32

1

2

3 - 8

9

10

11 -

20

21


The ACO Board has three card edge connectors.


–



Vital I/O data



–


Table 9–2. ACO Board 36-pin P3 Connections

Name

OUTV1COM

+OUT4

OUTV1COM

+OUT3

Function

Vital Power Common

Output 4

(not used)

Vital Power Common

Output 3

(not used)

OUTV1COM

+OUT2

OUTV1COM

+OUT1

OUTV1COM

+V1OUT

Vital Power Common

Output 2

(not used)

(not used)

Vital Power Common

Output 1

(not used)

Vital Power Common

Vital Power V+

(not used)

(not used)


P1-

1

2

3 - 8

9

10

33

34

35

36

24

25

26

27 -

32

11 -

20

21

22

23


Table 9–3. ACO Board 36-pin P1 Connections

Name

OUTV2COM

+OUT8

OUTV2COM

+OUT7

Function

Vital Power Common

Output 8

(not used)

Vital Power Common

Output 7

(not used)

OUTV2COM

+OUT6

OUTV2COM

+OUT5

Vital Power Common

Output 6

(not used)

(not used)

Vital Power Common

Output 5

(not used)

OUTV2COM

+V2OUT

Vital Power Common

Vital Power V+

(not used)

(not used)



9.9 SPECIFICATIONS

WARNING

Low current Vital AC output boards may fail with up to 3 milliamperes of output leakage current with the system requesting the output to be in the deenergized state. To prevent a potential unsafe condition, any load device attached to a low current vital output circuit board must not operate and must de-activate above 3 milliamperes. This includes all environmental operating conditions and all operating values of the load device over its service life.

Failure to follow this requirement may lead to unexpected operation of the load device.

WARNING

High current Vital AC output boards may fail with up to 50 milliamperes of output leakage current with the system requesting the output to be in the deenergized state. To prevent a potential unsafe condition, any load device attached to a high current vital output circuit board must not operate and must de-activate above 50 milliamperes. This includes all environmental operating conditions and all operating values of the load device over its service life. Failure to follow this requirement may lead to unexpected operation of the load device.



Table 9–4. ACO Board Specifications/Assembly Differences

59473-937

Specification

-02 -03

Maximum Number of Boards Per VPI

System


Number of Ports Per Board


Minimum Switched Output Supply Voltage

Maximum Switched Output Supply

Voltage

Frequency Range

AOCD Operating Threshold

Maximum Output Current Per Port

Switched Power (max resistive)

Isolation Between Outputs

Special EMI Suppression

Address Signature PROM Required

9.10 ASSEMBLY

90 VAC

130 VAC

40 - 150 Hz

50 mA max

0.8 A rms

104 W

> 3000 Vrms

No

Yes

40

1

8

500mA

90 VAC

130 VAC

40 - 150 Hz

3 mA max

0.5 A rms

104 W

> 3000 Vrms

Yes

Yes

Table 9–5. ACO Board Assembly

Description

ACO Board Assembly, 8 channels with enhanced EMI protection

ACO Board Assembly, 8 channels with EMI suppression

Signature PROM


Part Number

59473-937-02

59473-937-03

39780-003-01 through

39780-003-40


FSVT Board, P/N 59473-894-XX

SECTION 10 – FSVT BOARD, P/N 59473-894-XX

10.1 INTRODUCTION

This section provides Field Settable Vital Timer (FSVT) board detail.

10.2 GENERAL

The FSVT board is located on the Vital I/O bus. It is used to provide Vital timing functions that can be changed without recompiling the application data.

10.3 OPERATION

Normal operation of the FSVT board includes detecting the timer's setting and then performing a Vital algorithm to verify the setting of that timer's switch is accurate.

The FSVT board contains provisions for the use of 8 field-settable Vital timing functions.

Time setting selection is accomplished through the programming of the time selection jumpers. Each of the 8 timers has four pin headers that allow setting of the desired time interval by positioning one jumper in each header. Time is specified in tens of minutes, units of minutes, tens of seconds and units of seconds. The correct times settings are typically included in a location's Book of Plans. A label on the board provides a means of listing the timer settings.

CAUTION

Failure to install all four jumpers for a timer or installing more than one on a header results in an infinite timing cycle, so the timer never times out.

Figure 10–1 shows two examples of FSVT board timer setting examples. See Figure

10–3 for the timer locations.



SET FOR

12 MINUTES, 45 SECONDS

ONE JUMPER MUST BE INSTALLED IN EACH COLUMN

JUMPER ORIENTATION:

TB1

50

40

30

20

10

0

T.MIN

4

3

2

1

0

7

6

5

9

8

TB2

U.MIN

TB3

50

40

30

20

10

0

T.SEC

4

3

2

1

0

7

6

5

9

8

TB4

U.SEC

(0 to 59 Min. & 59 Sec.)

SET FOR

4 MINUTES, 10 SECONDS

TB1

50

40

30

20

10

0

T.MIN

TB2

4

3

6

5

9

8

7

2

1

0

U.MIN

TB3

50

40

30

20

10

0

T.SEC

TB4

4

3

6

5

9

8

7

2

1

0

U.SEC

(0 to 59 Min. & 59 Sec.)

Figure 10–1. FSVT Board Timer Setting Examples

On the board front edge are LED indicators showing which of the 8 timing functions are active. In addition, test points useful in troubleshooting internal operation are available

at the board front edge. Figure 10–2 shows the FSVT board edge, including indicators.

Once the Vital timers have been programmed by installing the jumpers, the settings can be "sealed" under a clear plastic cover using sealing wire and plastic seals. The kit also contains an extra label for recording new timer settings. The label contains a pressure sensitive adhesive so it can be applied over the existing label. Extra sealing kits can be obtained by ordering Alstom P/N 59649-219-01.



FSVT BOARD

59473-894-XX

NORMAL PCB

INDICATION NOTATION

FUNCTION

TP3

TP2

TP1

(Test Point)



OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

OFF, ON, FLASHING

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR1

TIMER 8 (Timer #8)

TIMER 7 (Timer #7)

TIMER 6 (Timer #6)

TIMER 5 (Timer #5)

TIMER 4 (Timer #4)

TIMER 3 (Timer #3)

TIMER 2 (Timer #2)

TIMER 1 (Timer #1)

CR1 - CR8 Light flashes while timer is running, light is steady on when time has comlpleted, but not yet reset.

Figure 10–2. FSVT Board Edge



10.4 TEST POINTS

Table 10–1 lists the FSVT board test points and Figure 10–3 shows the test point

locations.

TP1

TP2

TP3

PC1

Table 10–1. FSVT Board Test Points

Test Points

COM, common

+5V, power used for factory test used for factory test



Figure 10–3. FSVT Board Test Point and Timer Locations




The FSVT Board has three card edge connectors.

• P3, the top connector, is a 36-pin connector used only for mechanical board retention; this connector is not user configurable


Vital I/O data

– P 2-44 through P2-47 are wired in a specific pattern to common P2-48 per the application .lvc CAAPE report for board addressing; the remaining P2 pins are not user configurable

• P1, the lower connector, is a 60-pin connector used only for mechanical board retention; this connector is not user configurable

10.6 SPECIFICATIONS

Table 10–2. FSVT Board Specifications/Assembly Differences:

Specification



Logic Voltage Range

Logic Current Load (Maximum)

Number of Discrete Timers Per Board

Used for Vital Timers Number

Minimum Run Time (minutes/seconds)

Maximum Run Time (minutes/seconds)

Assign to I/O Bus With Signature Header

Drawing No. (ID letter)

Jumper TB4 Timer Settings (min/max)




Time Setting Method

59473-894

-01 -02

2 (1 of each type)

1

4.75 to 5.25 Volts

500 mA

8

1 through 8 9 through 16

0:00

59:59

59473-871-01 (A)

00/09 seconds

0/50 seconds

00/09 minutes

0/50 minutes

Jumper Selection


Signature Headers and PROMs

APPENDIX A – SIGNATURE HEADERS AND PROMS

A.1 INTRODUCTION

This appendix provides VPI circuit boards Signature Header and PROM information.

A.2 GENERAL

This section provides VPI circuit boards Signature Header and PROM information.

Address Signature Headers (for Vital inputs and I/O Bus boards) have assigned

signature letters, summarized in Table A–1.

Table A–1. Address Signature Headers (For Vital Inputs and I/O Bus Boards)

Address Signature Header Drawing Number

59473-871-01

59473-871-02

59473-871-03

59473-871-04

59473-871-05

59473-871-06

59473-871-07

59473-871-08

59473-871-09

59473-871-10

59473-871-11

59473-871-12

59473-871-13

59473-871-14

59473-871-15

59473-871-16

Address Signature Letter

I

J

K

L

M

N

O

P

E

F

G

H

A

B

C

D

P2511B, Volume 3, Rev. C, Nov/13 A–1 Alstom Signaling Inc.


Address Signature PROMs for all Vital output boards except LDO2 are provided in

Table A–2.

Signature

Number

(Vital

Output

Board

Number)

17

18

19

20

11

12

13

14

15

16

8

9

10

5

6

7

1

2

3

4

Signature

PROM

Drawing

Number

39780-003-01

39780-003-02

39780-003-03

39780-003-04

39780-003-05

39780-003-06

39780-003-07

39780-003-08

39780-003-09

39780-003-10

39780-003-11

39780-003-12

39780-003-13

39780-003-14

39780-003-15

39780-003-16

39780-003-17

39780-003-18

39780-003-19

39780-003-20

Table A–2. Address Signature PROMs

Selectable

Signature

PROM

Switch

Settings

1

1

1

1

1

1

2

1

1

1

0

0

1 tens ones

0 1

0

0

0

0

0

0

2

3

4

5

6

7

7

8

9

4

5

6

0

1

2

3

8

9

0

Signature

Number

(Vital

Output

Board

Number)

37

38

39

40

31

32

33

34

35

36

25

26

27

28

29

30

21

22

23

24

Signature

PROM

Drawing

Number

39780-003-21

39780-003-22

39780-003-23

39780-003-24

39780-003-25

39780-003-26

39780-003-27

39780-003-28

39780-003-29

39780-003-30

39780-003-31

39780-003-32

39780-003-33

39780-003-34

39780-003-35

39780-003-36

39780-003-37

39780-003-38

39780-003-39

39780-003-40

Selectable

Signature

PROM

Switch Settings

3

3

3

3

3

3

4

3

3

3

2

2

3 tens

2

2

2

2

2

2

2

7

8

9

4

5

6

0

1

2

3

8

9

0 ones

1

5

6

7

2

3

4



Figure A–1 shows the Selectable Signature PROM assembly. The locations of key

reference points are indicated to assist in installing and configuring the device. The figure shows the selection of “01” to be installed on the first Vital output board of a system.

Pin 1

Tens

Switch

Ones

Switch

Figure A–1. Selectable Signature PROM Assembly

Note: This assembly is designed to replace a 16-pin integrated circuit that is installed in a Vital output board of a VPI system. The

Alstom drawing numbers of these integrated circuits are listed in the table above under the heading “Signature PROM Drawing

No.”

Note: The location and orientation of the 16-pin socket where this assembly is to be installed varies for the different board types.

Be careful to observe the location of Pin 1 when installing this assembly.

Note: This assembly should be handled carefully as damage to the 16 machined pins may result. While the pins on this assembly are quite strong, they are made of a material that cannot be bent often without breaking.





Vital Board Layout Drawings

APPENDIX B – VITAL BOARD LAYOUT DRAWINGS

B.1 INTRODUCTION

This appendix provides the layout drawings for each Vital board type.

B.2 GENERAL

This appendix contains layout drawings of the boards discussed in this manual.

P2511B, Volume 3, Rev. C, Nov/13 B–1 Alstom Signaling Inc.


Figure B–1. CPU II Board, P/N 31166-374-00



59

R1

N1

60

R2

8 1

2 8 C 4 1

T

E

T

N

H

R

T

E

R3

N2

R4

8 1

2 8 C 4 1

J1

RS232

DIAGNOSTIC

PORT

7 1

2 8 C 4 1

1

2

ALIVE

6 J5 1

2 8 C 4 1

S1

D15-D12

S2

D11-D8

S3

D7-D4

1 S4

D3-D0

Figure B–2. CPU2 Interface Board, P/N 31166-499-00



Figure B–3. VRD Board, P/N 59473-740-00



Figure B–4. VSC Board, P/N 59473-939-00



Figure B–5. VSC Board with Daughterboard, P/N 59473-939-00



Figure B–6. CRG Board, P/N 31166-261-00



Figure B–7. IOB Board, P/N 59473-827-00



Figure B–8. DI Board, P/N 59473-867-00



Figure B–9. SBO Board, P/N 59473-739-00



Figure B–10. DBO Board, P/N 59473-747-00



Figure B–11. DBO-50V Board, P/N 59473-977-00



Figure B–12. LDO Board, P/N 59473-749-00



Figure B–13. LDO2 Board, P/N 31166-340-00



Figure B–14. ACO Board, P/N 59473-937-00



Figure B–15. FSVT Board, P/N 59473-894-00


FOR QUESTIONS AND INQUIRIES, CONTACT CUSTOMER SERVICE AT

1-800-717-4477

OR

WWW.ALSTOMSIGNALINGSOLUTIONS.COM

ALSTOM SIGNALING INC.

1025 JOHN STREET

WEST HENRIETTA, NY 14586

Alstom VPI II Vital Subsystem, CPU II, VRD, VSC, CRG, IOB, DI, SBO, DBO, DBO-50V, LDO, LDO2, ACO, FSVT Vital Vital Subsystem Manual

Assistant Bot

VPI

II

Vital Processor

Interlocking Control

System

Vital Subsystem

VPI

 II

Vital Processor

Interlocking Control

System

Vital Subsystem

SECTION 1 – VITAL PRINTED CIRCUIT BOARDS

Vital Subsystem

Non-Vital Subsystem

SECTION 2 – CPU II BOARD, P/N 31166-374-XX

System ID

SECTION 3 – VRD BOARD, P/N 59473-740-02

SECTION 4 – VSC BOARD, P/N 59473-939-XX

SECTION 5 – CRG BOARD, P/N 31166-261-XX

SECTION 6 – IOB BOARD, P/N 59473-827-XX

SECTION 7 – DI BOARD, P/N 59473-867-XX

SECTION 8 – VITAL DC OUTPUT BOARDS, P/N 59473-739-XX,

-747-XX, -977-XX, -749-XX, 31166-340-XX

SECTION 9 – ACO BOARD, P/N 59473-937-XX

SECTION 10 – FSVT BOARD, P/N 59473-894-XX

APPENDIX A – SIGNATURE HEADERS AND PROMS

Pin 1

Tens

Switch

Ones

Switch

APPENDIX B – VITAL BOARD LAYOUT DRAWINGS

Key Features

Frequently Answers and Questions

What does VPI II Vital Subsystem provide?

What information is included in the manual?

What are some of the key features of the VPI II Vital Subsystem?

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