RAM Flash MCP VCC Best Practices AN

RAM Flash MCP VCC Best Practices AN
Power-On Sequence Best Practice for
Flash, PSRAM, and Mobile DRAM based
Spansion® MCP products
Application Note
By: Matteo Zammattio
1. Introduction
Spansion has several combinations of MCP products, based on stacking a NOR MirrorBit® flash with a RAM
product. This solution is extremely important to save board layout space in electronic systems where there is
a critical constraint, such as mobile phones and other portable devices.
The roles of the MirrorBit flash memory are to properly boot the system, run application code, store
configurations and user-data.
Depending on the memory configuration required by every specific microcontroller (MCU), the NOR flash can
be combined with a lower density Pseudo-Static RAM (PSRAM), used as scratch memory for the system
stack. It can be also combined with a lower or equal density low-power DRAM, used to run high performance
code on single- or double-data rate bus.
A common denominator for reliable platform designs is to properly power-up the NOR flash and its RAM
companion chip with a power-supply ramp suitable for both components. Some other constraints such as
reset pulse duration and proper set-up command sequence should be performed after the power-up phase.
2. Power Supply Regulator and Reset Circuit
Almost all embedded systems are equipped with a dedicated power supply regulator and a supervisor. The
power source can be either a battery or a transformer of the AC line. The DC level is filtered and passed to a
voltage regulator.
The role of the regulator is to provide an accurate and reliable regulation of the voltage level within certain
limits of maximum supply current drained by the active and passive components.
The microcontrollers are very demanding in terms of power supply values and power-on and -off transients.
In most cases there is a required precision of 5%. Failure of the power supply regulator to keep the VCC in
that range requires holding the microcontroller in reset, as it is not able to provide a reliable operation. A/D
converters, internal oscillators and other very sensitive internal blocks require such level of accuracy.
The role of the supervisor is to sense the power supply level and generate the reset if VCC falls out of the valid
range. Sometimes the supervisor is integrated directly into the regulator circuit. Figure 2.1 shows a typical
power supply network of a generic embedded system. It is important to note that not only the VCC flash core
power supply is monitored, but also other power supplies that are used by the microcontroller.
The output of the supervisor signal can be used as RESET# signal for the flash memory. In general, it is used
as a global system reset signal for the MCU and other components.
Publication Number RAM_Flash_MCP_VCC_Best_Practices_AN
Revision 01
Issue Date January 11, 2011
Programm er
GuideApplication
Note
Figure 2.1 Typical Power Supply Network for 1.8V Memories and MCU
The capacitive load of the filtering network drastically affects the VCC power-ramp slope. Reducing its value
leads to faster rise time of the power supply from 0V to its nominal value.
The filtering network is very specific to the type of regulator and active loads. DC-DC buck regulators require
a specific compensation network for their loop stability. Linear regulators have a slightly different filtering
approach. It is important to notice that the filtering network plays a role in the definition of the voltage slope
(VCC slew-rate) during the power-on and -off transients.
Sometimes power supply networks using very similar regulators, filtering network, microcontrollers and
memories might have different power voltage ramps. That depends on the amount of current required to
supply specific peripherals (displays, sensors, actuators, network controllers, and other active loads).
Microcontrollers are also very sensitive devices in terms of supply voltage slope during power-on -off
transients. If they have multiple power-supplies, specific tracking must be carried out by the regulator in order
to not violate their power-on sequence.
3. POR, VCC Slope, and Reset Timings
Memories are equipped with an internal Power-On-Reset circuit (POR). It is mainly used to detect power
supply variations and “reset” the device during a power-on supply transient. “Reset” the device means to load
a required content from internal configuration registers either made of fuses or flash cells.
Recent memory architectures require starting the execution of an internal state machine at power-on.
The POR circuit relevant trip points are summarized in Figure 3.1.
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Figure 3.1 POR Circuit Hysteresis
The POR circuit needs to keep the internal circuits in a reliable and defined state during the power-on
transient until the VCC has reached the VCC_OK trip-point. In other words, when VCC_OK internal signal is
asserted the internal configurations are loaded and the state machine can boot from its internal ROM.
It is important to notice that the internal configuration is loaded when the VCC has not yet reached the
minimum specified level for proper operation. Due to that, internal circuits active during the configuration
phase should be able to work properly at lower VCC level.
Extremely sharp ramp slopes can also lead the memory device to not detect properly the VCC trip-point and to
not properly generate the internal configuration signals.
In terms of power consumption, the power-on reset circuit is a low-power circuit. This is to prevent having the
absorbed current erode the available budget of overall current of the device. If this low power consumption
mode does not detect and restore the internal configuration in certain conditions, this might lead to failure
modes.
In certain implementations, the POR circuit is switched off after detecting the VCC_OK trip point. When this
happens VCC needs to drop below a certain trip point to allow the POR to start new power-up detection again.
The POR circuit ignores extremely fast undershoots and overshoots of a few nanoseconds impacting the VCC
line. Some internal capacitors might be required in order to filter such undesired events.
NOR flash memories are designed with a RESET# pin (active low). In the actual implementation of the
Spansion products, the reset pin does not influence the POR circuit operation. In other words, a failure of the
POR circuit cannot be recovered driving the RESET# signal low. The role of the RESET# signal is to reset the
internal state machine/MCU. The RESET# signal cannot force the reloading of the internal configuration
registers. The RESET# signal must be pulled low right after a VCC rising edge, in order to match the timing of
the internal configuration (VCC set-up time). Then RESET# must be released when the device is ready to
enter active state after an initialization has completed (time from RESET# high to CE# low).
For legacy PSRAM and Mobile DRAM products, the reset signal is not provided. The device initialization
phase is controlled detecting the VCC ramp only with a POR circuit.
The ramp up time for VCC to linearly ramp up from 10% to 90% of its nominal value should lie between 100 µs
and 10 ms to prevent device initialization issues and subsequent read/write errors.
After the VCC has reached a sufficient level, the self initialization of the PSRAM and Mobile-DRAM device
takes place. The internal mode-registers are loaded with default values. This operation will take up to 150s
depending on the device architecture.
Advanced PSRAM and Mobile DRAM products support deep-power-down mode as well. Similarly to powerup initialization, exiting DPD mode requires reinitializing the device.
Figure 3.2 shows the relevant sequence to power-up and initialize an MCP with NOR flash and PSRAM.
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Programm er
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Figure 3.2 Power-Up Sequence of an MCP with NOR Flash and PSRAM
Some 3V PSRAMs require two CE signals. Figure 3.3 shows an example of how CE1# (active low) and CE2
(active high, low to enter deep-power-down mode) must interact in order to properly power-up a device.
Mobile DRAMs require specific commands to be executed to complete the initialization after power-up and
initialization time, such all-banks precharge and one or more auto-refresh. After that the mode registers need
to be set before to start reading and writing the device.
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Figure 3.3 Power-On Timing for a 3V PSRAM (Two-Chip Enable Signals)
4. PSRAM and Mobile DRAM Mode Register and Extended Mode Register
Settings
Basic asynchronous PSRAM devices do not require additional settings after the proper power-on sequence
has completed.
Advanced PSRAMs require additional register settings after power-on to mainly set-up the read/write
operation modes (asynchronous/burst) and the refresh operation modes (e.g. a specific bus configuration
register is provided in Cellular RAM products). The output driver strength is another parameter that can be set
on the configuration register. It indicates the slew rate of data output buffers active when the PSRAM provides
its content on the bus. Normally full driver strength can be used for all PSRAM devices with an equivalent
capacitive load of 30 pF on the data pins.
Mobile DRAM requires additional register settings after power-on timings are satisfied.
Mode Register (burst length and timings) and Extented Mode Register (output driver strength, partial array
refresh configuration) must be properly configured with dedicated command cycles.
The output driver strength Extended Mode Register-field indicates the slew rate of data output buffers active
when the Mobile DRAM provides its content on the bus.
Spansion suggests selecting default full driver strength in system designs, in order to easily exchange Mobile
DRAM parts in similar densities MCPs, in case the data-line load capacitance is in the range of 20 pF.
For lower capacitive loads, please consult the Mobile-DRAM related data sheet.
After setting those two registers properly, it is possible to read/write the Mobile DRAM address space.
5. Conclusion
System designers should carefully look at the VCC ramp slope and signal timing during boot sequence, in
order to satisfy both flash and RAM components embedded in the MCP. Proper register settings are also
required in order to access the related memories.
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6. Revision History
Section
Description
Revision 01 (January 11, 2011)
Initial release
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Colophon
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
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