datasheet for VL53B5263F

datasheet for VL53B5263F
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
General Information
4GB 512Mx72 DDR3 SDRAM ULP ECC REGISTERED Mini-RDIMM 244-PIN
Description
The VL53B5263F is a 512Mx72 DDR3 SDRAM high density Mini-RDIMM. This memory module is dual rank, consists
of eighteen CMOS 256Mx8 bits with 8 banks DDR3 Synchronous DRAMs in BGA packages, a 28-bit registered
buffer/PLL clock in BGA package, and a 2K EEPROM in an 8-pin MLF package. This module is a 244-pin mini dual inline memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are mounted
on the printed circuit board for each DDR3 SDRAM.
Features
Pin Description
244-pin, registered mini dual in-line memory module (Mini-RDIMM)
Supports ECC error detection and correction
Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, PC3-6400
VDD = VDDQ = 1.5V +/-0.075V
JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 )
VDDSPD = 3.0V to 3.6V
Eight internal component banks for concurrent operation
8-bit pre-fetch architecture
Bi-directional differential data-strobe
Nominal and dynamic on-die termination (ODT)
ZQ calibration support
Programmable CAS# latency: 11 (DDR3-1600), 9 (DDR3-1333),
7 (DDR3-1066), 6 (DDR3-800)
Programmable burst; length (8)
Average refresh period 7.8 us
Asynchronous reset
Fly-by topology
On board terminated command, address, and control bus
Serial presence detect (SPD) with EEPROM
JEDEC pinout
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 17.78mm (0.700”), double sided components
Order Information:
VL53B5263F - K0 S X
DRAM DIE (Option)
DRAM MANUFACTURER
S - SAMSUNG
MODULE SPEED
K0: PC3-12800 @ CL11
K9: PC3-10600 @ CL9
F8: PC3-8500 @ CL7
E7: PC3-6400 @ CL
Pin Name
Function
A0~A14
Address Inputs
A10/AP
Address Input/ Autoprecharge
A12/BC#
Address Input/ Burst Chop
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS8
Data Strobes
DQS0#~DQS8#
Data Strobes Complement
DM0~DM8
Data Masks
CB0~CB7
Data Check Bits I/O
PAR_IN
Parity Input
ERR_OUT#
Parity Error Output
CK0, CK0#
Clock Input
ODT0, ODT1
On-die Termination Control
CKE0, CKE1
Clock Enables
CS0#, CS1#
Chip Selects
RAS#
Row Address Strobes
CAS#
Column Address Strobes
WE#
Write Enable
VDD
Voltage Supply 1.5V +/- 0.075V
VSS
Ground
SA0~SA2
SPD Address
SDA
SPD Data Input/Output
SCL
SPD Clock Input
VREFCA
Reference Voltage for CA
VREFDQ
Reference Voltage for DQ
VDDSPD
SPD Voltage Supply 3.0V to 3.6V
VTT
Termination Voltage
RESET#
Register and SDRAM Control
NC
No Connect
VL: Lead-free/RoHS
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
1
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
Pin Configuration
244-PIN DDR3 Mini-RDIMM FRONT SIDE
244-PIN DDR3 Mini-RDIMM BACK SIDE
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VTT
31
DQ24
62
A2
92
DQ40
123
VTT
153
DQ29
184
A1
214
DQ45
2
VREFDQ
32
DQ25
63
VDD
93
DQ41
124
VSS
154
VSS
185
VDD
215
VSS
3
VSS
33
VSS
64
CK1 *
94
VSS
125
DQ4
155
DM3
186
CK0
216
DM5
4
DQ0
34
DQS3#
65
CK1# *
95
DQS5#
126
DQ5
156
NC
187
CK0#
217
NC
5
DQ1
35
DQS3
96
DQS5
127
VSS
157
VSS
218
VSS
6
VSS
36
VSS
66
VDD
97
VSS
128
DM0
158
DQ30
188
VDD
219
DQ46
7
DQS0#
37
DQ26
67
VREFCA
98
DQ42
129
NC
159
DQ31
189
VDD
220
DQ47
8
DQS0
38
DQ27
68
VDD
99
DQ43
130
VSS
160
VSS
190
EVENT# *
221
VSS
9
VSS
39
VSS
69
PAR_IN
100
VSS
131
DQ6
161
CB4
191
A0
222
DQ52
10
DQ2
40
CB0
70
VDD
101
DQ48
132
DQ7
162
CB5
192
VDD
223
DQ53
11
DQ3
41
CB1
71
A10/ AP
102
DQ49
133
VSS
163
VSS
193
BA1
224
VSS
12
VSS
42
VSS
72
BA0
103
VSS
134
DQ12
164
DM8
194
VDD
225
DM6
13
DQ8
43
DQS8#
73
VDD
104
DQS6#
135
DQ13
165
NC
195
RAS#
226
NC
14
DQ9
44
DQS8
74
WE#
105
DQS6
136
VSS
166
VSS
196
CS0#
227
VSS
15
VSS
45
VSS
75
CAS#
106
VSS
137
DM1
167
CB6
197
VDD
228
DQ54
16
DQS1#
46
CB2
76
VDD
107
DQ50
138
NC
168
CB7
198
ODT0
229
DQ55
17
DQS1
47
CB3
77
CS1#
108
DQ51
139
VSS
169
VSS
199
A13
230
VSS
18
VSS
48
VSS
78
ODT1
109
VSS
140
DQ14
170
NC
200
VDD
231
DQ60
19
DQ10
49
NC
79
VDD
110
DQ56
141
DQ15
171
TEST *
201
CS3# *
232
DQ61
20
DQ11
50
RESET#
80
CS2# *
111
DQ57
142
VSS
172
CKE1
202
NC
233
VSS
21
VSS
51
CKE0
81
NC
112
VSS
143
DQ20
173
VDD
203
VSS
234
DM7
22
DQ16
52
VDD
82
VSS
113
DQS7#
144
DQ21
174
A15 *
204
DQ36
235
NC
23
DQ17
53
BA2
83
DQ32
114
DQS7
145
VSS
175
A14
205
DQ37
236
VSS
24
VSS
54
Err_Out#
84
DQ33
115
VSS
146
DM2
176
VDD
206
VSS
237
DQ62
25
DQS2#
55
VDD
85
VSS
116
DQ58
147
NC
177
A12/BC#
207
DM4
238
DQ63
26
DQS2
56
A11
86
DQS4#
117
DQ59
148
VSS
178
A9
208
NC
239
VSS
27
VSS
57
A7
87
DQS4
118
VSS
149
DQ22
179
VDD
209
VSS
240
VDDSPD
28
DQ18
58
VDD
88
VSS
119
SA0
150
DQ23
180
A8
210
DQ38
241
SA1
29
DQ19
59
A5
89
DQ34
120
SCL
151
VSS
181
A6
211
DQ39
242
SDA
30
VSS
60
A4
90
DQ35
121
SA2
152
DQ28
182
VDD
212
VSS
243
VSS
61
VDD
91
VSS
122
VTT
183
A3
213
DQ44
244
VTT
KEY
KEY
*: These pins are not used in this module.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
2
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
Function Block Diagram
RCS1#
RCS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
D0
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
Vss
u
DQS1
DQS1#
DM1
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
D1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vss
D10
u
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vss
D11
u
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
D3
D13
u
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
D5
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
D14
u
DQS6
DQS6#
DM6
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
DQS3
DQS3#
DM3
D4
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
DQS5
DQS5#
DM5
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
DQS2
DQS2#
DM2
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
D6
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
D15
u
DQS7
DQS7#
DM7
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vss
D12
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
D7
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
D16
u
DQS8
DQS8#
DM8
u
Command, address, control, and clock line terminations
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
cpV
yp
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Vss
D8
cl brB cpr cprB
cpO
cpP
cpQ
cpR
cpS
cpT
cpU
yp
cpV
D17
RA0-RA14, RBA0-RBA2
RRAS#, RCAS#, RWE#,
RCS0#, RCKE0, RODT0
RCS1#, RCKE1, RODT1
DDR3
SDRAM
PCK0
PCK0#
DDR3
SDRAM
39 ohm +/-5%
VTT
36 ohm +/-5%
VDD
0.1uF
u
22 ohm +/-5%
CS1#
CS0#
A0-A14
BA0-BA2
RAS#
CAS#
WE#
CKE0
ODT0
CKE1
ODT1
CK0
CK0#
120 ohm
+/-1%
1:2
R
E
G
I
S
T
E
R
/
P
L
L
RCS1# -> CS1#: SDRAMs D9-D17
RCS0# -> CS0#: SDRAMs D0-D8
RA0-RA14 -> A0-A14: SDRAMs D0-D17
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D17
RRAS# -> RAS#: SDRAMs D0-D17
RCAS# -> CAS#: SDRAMs D0-D17
RWE# -> WE#: SDRAMs D0-D17
RCKE0 -> CKE0: SDRAMs D0-D8
RODT0 -> ODT0: SDRAMs D0-D8
RCKE1 -> CKE1: SDRAMs D9-D17
RODT1 -> ODT1: SDRAMs D9-D17
VDDSPD
Serial PD
SCL
SDA
WP
Vss
A0
A1
A2
SA0 SA1 SA2
VDD
Serial PD
D0-D17
VTT
D0-D17
VREFCA
D0-D17
VREFDQ
D0-D17
VSS
D0-D17
PCK0
Notes:
PCK0#
1. Unless otherw ise noted, resistor values are 15 ohms +/-5%
PAR_IN
RESET#
22 ohm +/-5%
QERR#
2. ZQ resistors are 240 ohms +/-1%
Err_Out#
RST #
RESET#: SDRAMs D0-D17
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
3
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN, VOUT
TSTG
IL
IOZ
IVREF
Parameter
MIN
MAX
Unit
Voltage on VDD pin relative to VSS
-0.4
1.975
V
Voltage on VDDQ pin relative to VSS
-0.4
1.975
V
Voltage on any pin relative to VSS
-0.4
1.975
Storage temperature
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
V
0
-55
100
Address, BA,
RAS#, CAS#,WE#,
CS#, CKE, ODT
-5
5
uA
CK, CK#
-5
150
uA
DM
-4
4
uA
-10
10
uA
-18
18
uA
DQ, DQS, DQS#
VREF supply leakage current; VREF = Valid VREF level
C
DC Operating Conditions
Symbol
VDD
VDDQ
Parameter
Min
Typical
Max
Unit
Notes
Supply Voltage
1.425
1.5
1.575
V
1,2
I/O Supply Voltage
1.425
1.5
1.575
V
1,2
VREFDQ (DC)
I/O reference voltage DQ bus
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
VREFCA (DC)
Input reference voltage CMD/ADD bus
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
-0.483 x VDDQ
0.5 x VDDQ
+0.517 x VDDQ
V
5
VTT
Termination Reference Voltage
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD
4. For reference: approximate VDD/2 +/-15mV.
5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce
timing margins.
Operating Temperature Condition
Symbol
TOPER
Parameter
Operating temperature
Rating
Units
0 - 95
0
C
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At 0 - 85 C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
o
o
85 C < TOPER <= 95 C.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
4
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
Command and Address
VIHCA(DC)
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
VREF + 0.100
VDD
V
VILCA(DC)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
VSS
VREF - 0.100
V
VIHDQ(DC)
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
VREF + 0.100
VDD
V
VILDQ(DC)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
VSS
VREF - 0.100
V
Min
Max
Unit
DQ and DM
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Command and Address
VIHCA(AC)
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
VREF + 0.175
-
V
VILCA(AC)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
-
VREF - 0.175
V
DQ and DM
VIHDQ(AC)
Input High (Logic 1) Voltage (DDR3-800/1066)
VREF + 0.175
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage (DDR3-800/1066)
-
VREF - 0.175
V
VIHDQ(AC)
Input High (Logic 1) Voltage (DDR3-1600/1333)
VREF + 0.150
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage (DDR3-1600/1333)
-
VREF - 0.150
V
Symbol
Min
Max
Unit
Input capacitance (A0~A14, BA0~BA2, RAS#, CAS#, WE#)
CIN1
5.5
6.5
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#)
CIN2
5.5
6.5
pF
Input capacitance (CK0, CK0#)
CIN3
5.5
6.5
pF
7
8.6
pF
7
9.0
pF
F8 (DDR3-1066)
7
9.4
pF
E7 (DDR3-800)
7
10.0
pF
Input/Output Capacitance
0
TA=25 C, f=100MHz
Parameter
K0 (DDR3-1600)
Input/Output capacitance
(DQ, DQS, DQS#, DM, CB)
K9 (DDR3-1333)
CIO
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
5
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
IDD Specification
Condition
Operating one bank active-precharge current;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE
is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRC= tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD);
CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W.
Precharge power-down current;
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs
are FLOATING.
Precharge standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is
HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
Precharge quiet standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is
HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
Active power-down current;
All device banks open; tCK= tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs
are FLOATING.
Active standby current;
All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS=
tRAS MAX(IDD)); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
Operating burst read current;
All device banks open; Continuous burst reads; IOUT = 0mA;
BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS
MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W.
Operating burst write current;
All device banks open; Continuous burst writes; BL = 8; CL =
CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD);
tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING.
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH; CS# is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING.
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL =
CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC=
tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is
HIGH; CS# is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs; Data pattern is same
as IDD4R.
K0
K9
F8
E7
IDD0*
613
568
523
523
mA
IDD1*
703
658
613
613
mA
IDD2P-F**
370
370
370
370
mA
IDD2P-S**
316
316
316
316
mA
IDD2N**
460
460
406
406
mA
IDD2Q**
460
460
406
406
mA
IDD3P**
460
406
406
406
mA
IDD3N**
730
730
640
640
mA
IDD4R*
1018
883
793
793
mA
IDD4W*
1063
928
838
838
mA
IDD5**
2260
2170
2080
2080
mA
IDD6**
216
216
216
216
mA
IDD7*
1468
1423
1153
1153
mA
Symbol (DDR3-1600) (DDR3-1333) (DDR3-1066) (DDR3-800)
Unit
Note: IDD specification is based on Samsung D-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
6
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
E7
(DDR3-800)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
8
-
8
-
8
-
8
-
ns
1.25
<1.50
1.5
<1.875
1.875
<2.5
2.5
3.3
ns
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
tCK(DLL_OFF)
tCK(avg)
tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max
+
+
+
+
+
+
+
+
tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
Clock Period
tCK(abs)
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Clock Period Jitter
tJIT(per)
-70
70
-80
80
-90
90
-100
100
ps
tJIT(per, lck)
-60
60
-70
70
-80
80
-90
90
ps
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
ns
tJIT(cc)
140
160
180
200
ps
Cycle to Cycle Period Jitter during DLL
locking period
tJIT(cc, lck)
120
140
160
180
ps
Cumulative error across 2 cycles
tERR(2per)
-103
103
-118
118
-132
132
-147
147
ps
Cumulative error across 3 cycles
tERR(3per)
-122
122
-140
140
-157
157
-175
175
ps
Cumulative error across 4 cycles
tERR(4per)
-136
136
-155
155
-175
175
-194
194
ps
Cumulative error across 5 cycles
tERR(5per)
-147
147
-168
168
-188
188
-209
209
ps
Cumulative error across 6 cycles
tERR(6per)
-155
155
-177
177
-200
200
-222
222
ps
Cumulative error across 7 cycles
tERR(7per)
-163
163
-186
186
-209
209
-232
232
ps
Cumulative error across 8 cycles
tERR(8per)
-169
169
-193
193
-217
217
-241
241
ps
Cumulative error across 9 cycles
tERR(9per)
-175
175
-200
200
-224
224
-249
249
ps
Cumulative error across 10 cycles
tERR(10per)
-180
180
-205
205
-231
231
-257
257
ps
Cumulative error across 11 cycles
tERR(11per)
-184
184
-210
210
-237
237
-263
263
ps
Cumulative error across 12 cycles
tERR(12per)
-188
188
-215
215
-242
242
-269
269
ps
Cumulative error across n = 13, 14 ... 49, 50
cycles
tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min
tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max
tERR(nper)
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
0.43
-
tCK(avg)
Absolute clock Low pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
0.43
-
tCK(avg)
DQS,DQS# to DQ skew, per group, per
access
tDQSQ
-
100
-
125
-
150
-
200
ps
DQ output hold time from DQS, DQS#
tQH
0.38
-
0.38
-
0.38
-
0.38
-
tCK(avg)
DQ low-impedance time from CK, CK#
tLZ(DQ)
-450
225
-500
250
-600
300
-800
400
ps
DQ high-impedance time from CK, CK#
tHZ(DQ)
-
225
-
250
-
300
-
400
ps
tDS(base)
10
-
30
-
25
-
75
-
ps
tDH(base)
45
-
65
-
100
-
150
-
ps
tDIPW
360
-
400
-
490
-
600
-
ps
Data Timing
Data setup time to DQS, DQS# referenced
to Vih(ac)Vil(ac) levels
Data hold time to DQS, DQS# referenced to
Vih(ac)Vil(ac) levels
DQ and DM Input pulse width for each input
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
7
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
E7
(DDR3-800)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Unit
Data Strobe Timing
DQS, DQS# READ Preamble
tRPRE
0.9
-
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# differential READ Postamble
tRPST
0.3
-
0.3
-
0.3
-
0.3
-
tCK
DQS, DQS# output high time
tQSH
0.4
-
0.4
-
0.38
-
0.38
-
tCK(avg)
DQS, DQS# output low time
tQSL
0.4
-
0.4
-
0.38
-
0.38
-
tCK(avg)
DQS, DQS# WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
0.3
-
tCK
tDQSCK
-225
225
-255
255
-300
300
-400
400
ps
tLZ(DQS)
-450
225
-500
250
-600
300
-800
400
ps
tHZ(DQS)
-
225
-
250
-
300
-
400
ps
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tDQSS
-0.27
0.27
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK(avg)
tDSS
0.18
-
0.2
-
0.2
-
0.2
-
tCK(avg)
tDSH
0.18
-
0.2
-
0.2
-
0.2
-
tCK(avg)
DLL locking time
tDLLK
512
-
512
-
512
-
512
-
nCK
Internal READ Command to PRECHARGE
Command delay
tRTP
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
Delay from start of internal write transaction
to internal read command
tWTR
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
tWR
15
-
15
-
15
-
15
-
ns
nCK
DQS, DQS# rising edge output access time
from rising CK, CK#
DQS, DQS# low-impedance time
(Referenced from
RL-1)
DQS, DQS# high-impedance time
(Referenced from RL+BL/ 2)
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse
width
DQS, DQS# rising edge to CK, CK# rising
edge
DQS,DQS# failing edge setup time to CK,
CK# rising edge
DQS,DQS# failing edge hold time to CK,
CK# rising edge
Command and Address Timing
WRITE recovery time
Mode Register Set command cycle time
tMRD
4
-
4
-
4
-
4
-
Mode Register Set command update delay
tMOD
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
CAS# to CAS# command delay
tCCD
4
-
4
-
4
-
4
-
Auto precharge write recovery + precharge
time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for
1KB page size
tDAL(min)
tMPRR
nCK
WR + roundup (tRP / tCK(AVG))
1
-
tRAS
35
nCK
1
-
1
-
1
-
nCK
9*tREFI
36
9*tREFI
37.5
9*tREFI
37.5
9*tREFI
ns
-
tRRD
max
(4tCK,6ns)
-
max
(4tCK,6ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,10ns)
ACTIVE to ACTIVE command period for
2KB page size
tRRD
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,10ns)
-
max
(4tCK,10ns)
-
Four activate window for 1KB page size
tFAW
30
-
30
-
37.5
-
40
-
ns
Four activate window for 2KB page size
tFAW
40
-
45
-
50
-
50
-
ns
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
45
-
65
-
125
-
200
-
ps
Command and Address hold time from CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIH(base)
120
-
140
-
200
-
275
-
ps
tIPW
560
-
620
-
780
-
900
-
ps
Control & Address Input pulse width for each
input
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
8
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
E7
(DDR3-800)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Unit
Refresh Timing
2Gb REFRESH to REFRESH OR
REFRESH to ACTIVE command interval
tRFC
160
-
160
-
160
-
160
-
ns
Average periodic refresh interval
(0°C<= TCASE <= 85 °C)
tREFI
7.8
-
7.8
-
7.8
-
7.8
-
us
Average periodic refresh interval
(85°C<= TCASE <= 95 °C)
tREFI
3.9
-
3.9
-
3.9
-
3.9
-
us
Power-up and RESET calibration time
tZQinitI
512
-
512
-
512
-
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
256
-
256
-
256
-
tCK
tZQCS
64
-
64
-
64
-
64
-
tCK
tXPR
max
(5tCK, tRFC
+ 10ns)
-
max
(5tCK, tRFC
+ 10ns)
-
max
(5tCK, tRFC
+ 10ns)
-
max
(5tCK, tRFC
+ 10ns)
-
tXS
max(5tC,
tRFC+10ns)
-
max(5tC,
tRFC+10ns)
-
max(5tC,
tRFC +10ns)
-
max(5tC,
tRFC +10ns)
-
Calibration Timing
Normal operation Short calibration time
Reset Timing
Exit Reset from CKE HIGH to a valid
command
Self Refresh Timing
Exit Self Refresh to commands not requiring
a locked DLL
Exit Self Refresh to commands requiring a
locked DLL
tXSDLL
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
Minimum CKE low width for Self refresh
entry to exit timing
tCKESR
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
nCK
-
Valid Clock Requirement after Self Refresh
Entry (SRE)
tCKSRE
max(5tC,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
Valid Clock Requirement before Self
Refresh Exit (SRX)
tCKSRX
max(5tC,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
tXP
max
(3tCK,6ns)
-
max
(3tCK,6ns)
-
max
(3tCK,7.5ns)
-
max
(3tCK,7.5ns)
-
tXPDLL
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
tCKE
max (3tCK,
5.625ns)
-
max (3tCK,
5.625ns)
-
max (3tCK,
5.625ns)
-
max (3tCK,
7.5ns)
-
tCPDED
1
-
1
-
1
-
1
-
nCK
tPD
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCK
Timing of ACT command to Power Down
entry
tACTPDEN
1
-
1
-
1
-
1
-
nCK
Timing of PRE command to Power Down
entry
tPRPDEN
1
-
1
-
1
-
1
-
nCK
Timing of RD/RDA command to Power
Down entry
tRDPDEN
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
tWRPDEN
WL + 4
+(tWR/ tCK)
-
WL + 4
+(tWR/ tCK)
-
WL + 4
+(tWR/ tCK)
-
WL + 4
+(tWR/ tCK)
-
nCK
tWRAPDEN
WL+4+WR+
1
-
WL+4+WR+1
-
WL+4+WR+1
-
WL+4+WR+1
-
nCK
tWRPDEN
WL + 2
+(tWR/ tCK)
-
WL + 2
+(tWR/ tCK)
-
WL + 2
+(tWR/ tCK)
-
WL + 2
+(tWR/ tCK)
-
nCK
Timing of WRA command to Power Down
entry (BL4MRS)
tWRAPDEN
WL+2+WR+
1
-
WL+2+WR+1
-
WL+2+WR+1
-
WL+2+WR+1
-
nCK
Timing of REF command to Power Down
entry
tREFPDEN
1
-
1
-
1
-
1
-
Timing of MRS command to Power Down
entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
Power Down Timing
Exit Power Down with DLL to any valid
command; Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
Exit Precharge Power Down with DLL frozen
to commands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of WR command to Power Down
entry BL8 (OTF, MRS), BL4OTF
Timing of WRA command to Power Down
entry BL8 (OTF, MRS), BL4OTF
Timing of WR command to Power Down
entry (BL4MRS)
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
9
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
E7
(DDR3-800)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Unit
ODT Timing
ODT high time without write command or
with write command and BC4
ODTH4
4
-
4
-
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
6
-
6
-
nCK
Asynchronous RTT turn-on delay (PowerDown with DLL frozen)
tAONPD
2
8.5
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (PowerDown with DLL frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
2
8.5
ns
ODT turn-on
tAON
-225
225
-250
250
-300
300
-400
400
ps
RTT_NOM and RTT_WR turn-off time from
ODTL off reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
tWLMRD
40
-
40
-
40
-
40
-
tCK
tWLDQSEN
25
-
25
-
25
-
25
-
tCK
Setup time for tDQSS latch
tWLS
165
-
195
-
245
-
325
-
ps
Hold time for tDQSS latch
tWLH
165
-
195
-
245
-
325
-
ps
Write leveling output delay
tWLO
0
7.5
0
9
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
0
2
ns
Write Leveling Timing
First DQS pulse rising edge after tDQSS
margining mode is programmed
DQS/DQS delay after tDQS margining mode
is programmed
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
10
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
Package Dimensions
FRONT VIEW
3.40
MAX
82.00 TYP
COMPONENT AREA
17.78
10.00
0.5 R
PIN 1
3.20
PIN 122
3.60
38.40 TYP
33.60 TYP
1.0 +/- 0.10
3.20
43.90 TYP
BACK VIEW
2.0 +/- 0.10 (2X)
COMPONENT AREA
3.80 +/- 0.10
2.55 TYP
0.60
TYP
PIN 244
1.0 +/- 0.10
0.45
TYP PIN 123
0.25 MAX
1.00 (2X)
Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
2. The dimensional diagram is for reference only.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
11
Product Specifications
PART NO.:
VL53B5263F-K0/K9/F8/E7S
REV: 1.0
Revision History:
Date
02/22/2011
Rev.
Page
1.0
All
Changes
Spec release
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
12
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement