IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009 2639 An Online Stability Margin Monitor for Digitally Controlled Switched-Mode Power Supplies Jeffrey Morroni, Student Member, IEEE, Regan Zane, Senior Member, IEEE, and Dragan Maksimović, Senior Member, IEEE Abstract—This paper presents a practical injection-based method for continuous monitoring of the crossover frequency and phase margin in digitally controlled switched-mode power supplies (SMPS). The proposed approach is derived from Middlebrook’s loop-gain measurement technique, adapted to a digital controller implementation. A digital square-wave signal is injected into the feedback loop and the injection signal frequency is adjusted while monitoring loop signals to obtain the system crossover frequency and phase margin online, i.e., during normal closed loop SMPS operation. The approach does not require open loop or steady-state SMPS operation and is capable of convergence in the presence of load transients or other disturbances. A method for designing the stability margin monitor, based on small-signal models derived using an envelope modeling approach, is also presented. Experimental results are given for multiple power stage configurations demonstrating close matches between monitored and expected crossover frequencies and phase margins. Index Terms—DC–DC power conversion, digital control. I. INTRODUCTION WITCHING power converters are nonlinear systems with dynamic responses that depend on the operating point. Typically, switched-mode power supply (SMPS) feedback loops are designed based on linearized small-signal models to achieve desired performance at the nominal operating point. At design time, it is a common practice to measure the system loop gain using a network analyzer to verify the loop stability margins under various conditions. Middlebrook’s injection technique  has been a widely adopted approach to measuring loop gain as it does not require breaking the feedback loop. Using this technique, designs can be verified offline to ensure desired performance before system deployment. However, offline performance verification does not provide information regarding the effect of operating changes on system performance after deployment. With advances in digital control for high-frequency dc–dc converters , it becomes possible to consider alternative design and verification techniques leading to improved closed-loop dynamic responses, faster design time, and improved SMPS robustness. In particular, various methods have been proposed to measure converter frequency responses online – or to tune compensator parameters based on an online assessment S Manuscript received March 6, 2009; revised May 18, 2009. Current version published December 18, 2009. This paper was presented in part at the Power Electronics Specialists Conference, Rhodes, Greece, June 2008. Recommended for publication by Associate Editor C. K. K. Tse. The authors are with the Department of Electrical and Computer Engineering, Colorado Power Electronics Center, University of Colorado, Boulder, CO 80309 USA (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TPEL.2009.2029335 of the frequency response –. Using these types of approaches, it becomes possible to assess and monitor control loop performance online. In  and , a pseudo-random binary sequence is injected into the control loop for the purpose of identifying the converter open loop control-to-output (Gvd ) frequency response. During the perturbation process, to obtain accurate information the system should operate in steady state. As a result, these approaches are best suited for one-time frequency response measurement. In –, frequency response information is obtained based on purposely induced limit-cycle oscillations, again assuming steady-state operation. Therefore, similar to –, these approaches are difficult to apply to continuous system monitoring. Recently, approaches to monitoring and/or tuning of control loops have been proposed which rely on injection of a digital sine-wave into the control loop , , . For example, a digital sine-wave can be injected into a digital control loop for the purpose of tuning compensator gain to achieve desired crossover frequency as part of an auto-tuning process . Similarly, in , a digital sine-wave is injected into the system and used, in a series of steps, to tune the parameters of a digital compensator for desired crossover frequency and phase margin. In this paper, inspired by Middlebrook’s analog injection technique , a method is proposed to measure the crossover frequency and phase margin in a digitally controlled SMPS online, i.e., during normal closed loop operation. The proposed approach does not require opening the feedback loop and is capable of continuously updating the measured crossover frequency and phase margin in the presence of load transients or other system disturbances. Applications of the technique include fast design time verifications, online dynamic performance monitoring of power supplies in power distribution systems (such as servers or spacecrafts –), and adaptive online tuning of controller parameters . Section II details the proposed approach for monitoring stability margins. Section III presents derivations of small-signal transfer functions for the stability margin monitor from which the system can be designed. Section IV presents experimental results. Conclusions are given in Section V. II. STABILITY MARGIN MONITOR Middlebrook’s analog loop gain measurement technique is a well known and widely accepted approach to measuring frequency responses without breaking the feedback loop , . Fig. 1 illustrates this approach for the case of voltage injection in series with the loop. The measured gain Tv (s) can be written 0885-8993/$26.00 © 2009 IEEE Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. 2640 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009 Further, when (6) is satisfied, the phase margin can be directly measured as ϕ = ϕm = Vy − Vx . Fig. 1. Small-signal SMPS model illustrating analog loop gain measurement technique using voltage injection without breaking the feedback loop , . as −V̂y (s) Z1 (s) Tv (s) = = T (s) 1 + Z2 (s) V̂x (s) Z1 (s) + Z2 (s) −Vy . Vx Based on (2)–(7), the crossover frequency and phase margin can be monitored online in digitally controlled systems without requiring any additional power stage information. The monitoring can be performed continuously during normal closed loop operation at the cost of a small output voltage perturbation imparted by the injection source Vz . However, the perturbation amplitude seen at the converter output can be automatically controlled by adjusting the signal injection amplitude δ, as shown in Fig. 2. Details regarding the design and implementation of each processing block shown in Fig. 2 are presented in Sections II-A–D. A. Injection Generator and Injection Amplitude Controller (1) where T(s) is the actual loop gain. From (1), T(s) ≈ Tv (s) when the following conditions are met: Z1 (s) Z2 (s) and T(s) Z1 (s)/Z2 (s). In an SMPS with analog voltage-mode PWM control, points in the loop where the impedance conditions for loop gain measurement using voltage injection are well satisfied typically include the converter output or the compensator output. Fig. 2 shows the proposed injection-based loop gain measurement technique applied to a digitally controlled SMPS. The digital controller has the standard architecture including a voltage A/D converter (ADC), discrete-time compensator Gc (z) and digital pulsewidth modulator (DPWM). Similar to the analog voltage injection approach, a small digital injection source Vz can be added to a digital feedback loop at a suitable point. For example, injection can occur at the compensator input or at the compensator output, as shown in Fig. 2. Under the assumption that the injection source Vz is purely sinusoidal and the fact that Z1 /Z2 = 0 in the digital part of the loop, the system loop gain can be found by loop analysis as T = (7) (2) From (2), the crossover frequency fc can be found as the injection frequency finj such that T (ej ω inj T s ) = 1 (3) where Ts is the switching period. Similarly, the loop gain phase margin is obtained from (4) ϕm = 180◦ + T ej ω inj T s . From (2) and (3), the crossover frequency is equal to the injection source frequency, fc = finj (5) Vy = Vx . (6) if The injection generator creates a 50% duty cycle, squarewave perturbation with frequency adjustable by the frequency command finj . Practically, this square-wave signal can be generated with a digital counter, running off of a high frequency system clock fclk and a digital comparator. Since the duty-cycle perturbation is not purely sinusoidal, (2)–(7) no longer hold directly, thus, requiring additional filters as described in Section II-B. It is of interest to derive the frequency resolution qf inj of the injection generator as a function of the injection frequency finj and the system clock frequency fclk . Begin by defining the ratio n= fclk . finj (8) Next, solving (8) for finj and then linearizing the equation fclk ∂finj =− . (9) ∂n n2 Finally, substituting (8) into (9) yields 2 ∂finj finj = . qf inj = ∂n fclk (10) When the stability margin monitor is operating in steady state, (5) is satisfied and the injection frequency is equal to the crossover frequency. In a typical system, the crossover frequency fc is a fraction of the switching frequency fs , which, in turn is a fraction of the system clock frequency. Hence, high resolution is typically attainable without requiring an unreasonably high-frequency system clock. To minimize the impact of the signal injection on the output voltage ripple, it is desirable to control the injection signal amplitude δ to obtain a minimum detectable output voltage perturbation of ±1 least significant bit (LSB) in the ADC. To ensure minimum output voltage perturbation independent of converter parameters or finj , the proposed stability margin monitor includes an automatic injection amplitude controller consisting of a feedback loop that adjusts δ to achieve the desired perturbation, as shown in Fig. 3. The injection amplitude controller takes as input the quantized output voltage error Verr , which is then passed through a peak detector. The peak output voltage error Vp is then Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. MORRONI et al.: AN ONLINE STABILITY MARGIN MONITOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 2641 Fig. 2. Crossover frequency and phase margin monitor block diagram. The outputs of stability margin monitor are crossover frequency and average phase margin of the output voltage loop gain T. The injection amplitude controller automatically adjusts the square-wave perturbation amplitude δ to result in minimum (±1 LSB) perturbation at the output voltage. Fig. 3. Block diagram of the injection amplitude controller. The injection amplitude δ is adjusted via feedback until the desired output voltage perturbation magnitude is achieved. compared to the desired LSB perturbation magnitude, Vp ref . A simple digital integral compensator adjusts δ so that the desired output voltage perturbation is achieved independent of finj . A secondary benefit to purposely introducing a periodic oscillation into a digital control loop involves improved dc voltage regulation, similar to the approach described in . In particular, the ±1 LSB periodic and symmetric oscillation imposed by Vz at the output voltage combined with the action of the integrator in the PID compensator work to position the dc value of the output voltage in the center of the zero-error bin of the voltage ADC. The accuracy with which the output voltage can be centered in the zero-error bin then becomes a function of the DPWM resolution rather than the ADC resolution. B. Bandpass Filters and Peak Detectors As described previously, in the proposed implementation of Fig. 2, Vz is a 50% duty cycle square-wave injection with ad- justable frequency determined by the frequency command finj . However, (2)–(7) are based on the assumption that Vz is a purely sinusoidal injection. To account for the infinite odd harmonics introduced by the square-wave, bandpass filters are used to remove all unwanted frequency components of Vx and Vy . The outputs of the bandpass filters, Vy ﬁlt and Vx ﬁlt , then contain only one frequency component equal to the injection frequency. The bandpass filters, Gbp (zbp ), are designed to be high Qfactor filters with the pass-band centered at finj . However, since finj changes in order to continuously satisfy (6), the filter passbands must also change. To realize self-adjustable bandpass digital filters, first consider a general form second-order digital filter Gbp (zbp ) = A 2 zbp (zbp − 1) . + Bzbp + C (11) Based on the discrete-time to continuous-time mapping s zbp = e f sample (12) the pass-band center frequency fpb and the Q-factor of (11) can be calculated as functions of B, C, and fsample (the filter sample frequency) √ B 2 − 4C fsample −1 (13) fpb = tan 2π B √ tan−1 B 2 −4C B 1 . √ Q= 2 ln C Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. (14) 2642 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009 Fig. 5. Block diagram of the proposed phase margin monitor. A pulse, Enable, related to phase shift is generated via digital relays and an XOR gate. A low-pass filter removes high frequency noise in ϕ to output the average phase margin, ϕ. Fig. 4. Experimental stability margin monitor waveforms. (a) Duty cycle injection source V z , (b) signals V y and V x , and (c) signals V y ﬁlt and V x ﬁlt . Given fsample , desired fpb and Q, (13) and (14) can be used to solve for the required filter coefficients B and C offline. Coefficient A can then be calculated to achieve the desired filter pass-band gain. After calculating A, B, and C offline, these coefficients can then be held constant while varying fsample online in proportion to finj . In doing so, the filter pass-band center frequency fpb automatically shifts in proportion to finj while Q stays constant (independent of finj ). Fig. 4 shows sample experimental waveforms, gathered using Chipscope (an embedded FPGA logic analyzer) of the important signals in the stability margin monitor. As shown, the injection source Vz causes a system perturbation seen in both signals Vx and Vy . However, since Vz is a square wave causing ±1 LSB output voltage perturbation, Vx and Vy have undesired harmonics as seen in Fig. 4(b). The previously described bandpass filters remove the unwanted frequency components of Vy and Vx such that Vy ﬁlt and Vx ﬁlt contain only the injection source frequency, as shown in Fig. 4(c). In the result shown in Fig. 4, the injection source frequency is approximately equal to crossover frequency because the magnitudes of the filtered signals are approximately equal. Further, the phase margin can be found directly as the phase shift between the two filtered signals. The digital peak detectors of Fig. 2 take as inputs the filtered waveforms, Vy ﬁlt and Vx ﬁlt , and output Vx env and Vy env , the envelope of the filtered signals. The peak detectors give an assessment of the magnitudes of each signal such that (6) can be continuously satisfied by controlling the injection frequency via a feedback loop. a very high bandwidth stability margin monitor is not necessary making an integral compensator a sufficient choice. The output of the integral compensator is finj , the injection frequency command, which is adjusted until there is no error between Vx env and Vy env , at which point (6) is satisfied and fc = finj . More detailed design criteria for the integral compensator are presented in Section III. D. Phase Detector The phase detector block diagram, used to monitor ϕ, is shown in Fig. 5 and is similar to some approaches used to detect phase in digital phase-locked loops . The phase detector takes as input the filtered signals, Vy ﬁlt and Vx ﬁlt . These signals are passed through a digital relay whose output is high when the input is above zero and low when the input is below zero. The two relay outputs are then XOR’d together to form an Enable pulse, labeled in Fig. 5, which is high whenever the two inputs are not equal. A counter running at the system clock frequency, fclk , measures the length of time Enable is high which is directly related to the phase shift between Vy ﬁlt and Vx ﬁlt . The main factor in the resolution/accuracy of ϕ is the sample rate, fsample , of the bandpass filters with respect to finj fsample = γfinj (15) where γ is an integer proportionality constant. Since Vy ﬁlt and Vx ﬁlt are sampled at a rate proportional to finj so that the filter pass-band tracks changes in injection frequency, the respective zero crossings of the two filtered signals could be shifted by as much as one sample period, 1/fsample , from the actual zerocrossings. This sampling effect leads to high frequency noise at the counter output ϕ as reported in . To remove the high frequency noise in the measured phase margin, a digital low-pass filter processes ϕ, as seen in Fig. 5. The output of the phase detector is then the average value of phase margin, labeled ϕ in Fig. 5. C. Integral Compensator An integral compensator with gain Gi is used to process the error between Vx env and Vy env , as shown in Fig. 2. Depending on the application and system specifications, a more sophisticated compensator could be used in place of the integral compensator. For the applications considered in this paper however, III. STABILITY MARGIN MONITOR MODELING This section aims to derive a model for the digital stability margin monitor from which the integrator Gi can be designed. Before discussing the details of the modeling approach, the experimental test-beds from which the models will be derived are Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. MORRONI et al.: AN ONLINE STABILITY MARGIN MONITOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 2643 TABLE I SUMMARY OF EXPERIMENTAL TEST-BED COMPENSATORS AND POWER STAGE PARAMETERS transfer function Gbp (zbp ) = 0.00195 zbp − 1 2 − 1.96z zbp bp + 0.998 (16) where fsample = 32 finj , i.e., γ = 32 in (15). Choice of γ is generally based on a compromise between the required system clock frequency and the required time resolution of the digital filter. With γ = 32, and assuming a maximum possible crossover frequency of 1/5th fs , the highest required filter clock frequency is 640 kHz for the experimental prototypes presented here. Based on (13) and (14), the filter pass-band center frequency and Q-factor can then be calculated as Fig. 6. Experimental prototypes used for modeling and testing of stability monitor. (a) Synchronous buck converter. (b) CCM or DCM boost converter. fpb ≈ fsample 32 Q ≈ 100 = 40 dB. first introduced. There are two experimental test-beds, shown in Fig. 6, used to verify functionality of the proposed stability margin monitor: a synchronous buck converter and a boost converter which can be operated in either continuous conduction mode (CCM) or discontinuous conduction mode (DCM). The nominal power stage parameters of the buck converter are given in Fig. 6(a). The buck converter output voltage ADC is a TI-THS1030 sampled once per switching period with an effective output voltage LSB resolution of 20 mV or 0.4% of the DC output voltage. The nominal switching frequency is 100 kHz. Nominally, the boost converter power stage parameters are as shown in Fig. 6(b) with Vg and L depending on the mode of operation (CCM or DCM). In CCM, Vg CCM = 15 V and LCCM = 100 µH. In DCM, Vg DCM = 10 V and LDCM = 10 µH. The boost converter ADC is an AD7822 with an effective output voltage resolution of 512 mV or 1.6% of the dc output voltage. As with the buck converter, the switching frequency is 100 kHz. A summary of the nominal power stage parameters and the digital compensators used for each test-bed is given in Table I. The matched bandpass filters used to remove the harmonics of Vy and Vx were implemented using the following discrete-time (17) (18) In order to design the stability margin monitor integral compensator, it is necessary to derive the transfer function from small-signal changes in injection frequency (control) to envelope error (output) Gf inj −V e (s) = V̂env error (s) . fˆinj (s) (19) Equation (19) can be determined by first splitting the overall transfer function into two separate transfer functions G1 (s) = V̂y env fˆinj (20) G2 (s) = V̂x env fˆinj (21) and from which (19) can be found by Gf inj −Ve (s) = G2 (s) − G1 (s). (22) To compute (20) and (21) and thus determine (22) an envelope modeling approach is used, adapted from resonant inverter modeling techniques –. First, the input perturbation Vz Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. 2644 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009 Fig. 7. (a) Gf inj Ve (s) for System 1 (synchronous buck converter). (b) Simulated (solid) and model (dashed) step responses for System 1. The results show a close match between the model and simulation. is assumed to be purely sinusoidal, which is a valid approximation due to the bandpass filters removing all frequency components of Vy and Vx except the fundamental component. Next, small-signal variations in finj are introduced and represented as a series of signals containing the carrier frequency finj and modulated sidebands finj ± nfm where n is an integer. Assuming the steady-state injection frequency is much larger than the ac injection frequency variations, all sidebands other than the fundamental can be neglected (i.e., n = 1). This approximation allows the small-signal input perturbation to be represented by three distinct frequency components, a carrier signal, finj , and two dominant sidebands, finj ± fm . This is consistent with the usual narrowband approximations made in resonant converter modeling . With the input decomposed into finj and finj ± fm , the response of the system can be determined by the sum of network response to the three distinct input frequencies. More specifically, the system response is determined by the response of the linear transfer functions seen by the input perturbation H1 (s) = V̂y ﬁlt T (s) N1 (s) Gbp (s) = =− ˆ 1 + T (s) D 1 (s) finj (23) H2 (s) = V̂x ﬁlt 1 N2 (s) Gbp (s) = . = ˆ 1 + T (s) D 2 (s) finj (24) and Using (23) and (24) and following the approach in , it can be shown that the envelope transfer function can be derived as (25), shown at the bottom of this page, where n = 1, 2. Using (25), the two envelope transfer functions, G1 (s) and G2 (s), can be computed and used to determine the complete envelope transfer function of (22). Finally, computing the stability Gn (s) = monitor loop gain as V̂env error fˆinj = Gf inj Tmonitor = V̂env error fˆinj Ve Gi (26) the control loop can be designed by applying standard frequency domain techniques. The bode plot of Gf inj Ve (s) for the buck SMPS (System 1 of Table I) is shown in Fig. 7(a). As shown in the Fig. 7(a), the envelope transfer function for System 1 consists of a lowfrequency real pole, contributed from the poles of the bandpass filters, and a high-frequency real pole present from the closedloop poles of the output voltage loop. To verify the accuracy and validity of the envelope model, open loop step responses from the model are compared to an equivalent MATLAB Simulink system simulation. The Simulink simulation consists of the switching power stage along with proposed stability margin monitor running in open loop at a fixed injection frequency. In the simulation, a small step in injection frequency is introduced after which the effect on the envelope error is observed. In Fig. 7(b), the simulated (solid) step response is compared to the step response predicted by the derived model (dashed). As indicated by Fig. 7(b), the predicted step response does not deviate from the simulation result by more than 5%, indicating an accurate modeling approach. To derive models for the other three experimental systems presented, only T(s) in (23) and (24) require modification. In particular, each system has a different plant transfer function, Gvd and/or Gc transfer function and, therefore, T(s) in (23) and (24) will change for each test-bed. The remaining three experimental systems were modeled with the resulting Bode responses given in Fig. 8. Note that for the analysis presented, the DCM boost converter Gvd transfer function assumes the Hn (−jωinj )Nn (s + jωinj )Dn (s − jωinj ) − Hn (jωinj )Nn (s − jωinj )Dn (s + jωinj ) jVs1 . 2s Hn (jωinj ) Dn (s + jωinj )Dn (s − jωinj ) Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. (25) MORRONI et al.: AN ONLINE STABILITY MARGIN MONITOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES Fig. 8. (a) Gf inj Ve for System 2 (synchronous buck converter). (b) Gf inj converter) based on proposed envelope modeling technique. Ve simple, single pole model given in . In all the four models derived in this paper, all high frequency dynamics (above 12 finj ) are discarded as this system is sampled. It should be noted that the models derived above are in the continuous-time, whereas the stability margin monitor is a digital system operating on discrete-time samples. Therefore, any suitable continuous-time to discrete-time mapping can be used to transform Gfinj Ve (s) into the discrete domain before designing the digital integrator, Gi . for System 3 (CCM boost converter). (c) Gf inj 2645 Ve for System 4 (DCM boost TABLE II SUMMARY OF INTEGRAL COMPENSATOR GAINS USED TO CONTROL THE STABILITY MARGIN MONITOR LOOP IV. EXPERIMENTAL RESULTS The prototypes used to experimentally verify the stability margin monitor operation are the same as summarized in Fig. 6 and Table I. The digital feedback loop was realized using a Virtex-IV FPGA platform with a system clock frequency of 50 MHz. The input injection magnitude δ is continuously updated based on the injection amplitude controller until the output voltage error Verr is the minimum possible, ±1 LSB. The speed of the input amplitude controller has been designed to be faster than the monitoring control loop while the sample frequency of the stability margin monitor control loop is equal to the injection frequency. Using the models derived in Section III, four separate control loops were designed for each of the four experimental systems tested. In particular, the control loops were designed, based on the loop gain given by (26), by selecting a Gi that results in the desired bandwidth with acceptable phase margin. A summary of the gains of the integral gains used to control finj is provided in Table II. In addition, Table II also indicates the bandwidth of stability margin control loop relative to its sample rate. Given the described experimental systems, Table III summarizes the experimental performance of the stability margin Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. 2646 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009 TABLE III SUMMARY OF EXPERIMENTAL STABILITY MONITORING RESULTS COMPARING STABILITY MARGINS BASED ON MODEL, MEASURED VIA PROPOSED MONITORING LOOP AND MEASURED VIA TRADITIONAL ANALOG LOOP GAIN MEASUREMENT TECHNIQUE monitor with the four different power stage configurations. In Table III, measured output voltage loop stability margins, finj and ϕ, based on the proposed monitoring approach closely match the values given by the discrete-time model of . Table III also shows measured results based on the standard analog injection technique, obtained by introducing an analog voltage injection at the converter output (Point A in Fig. 5), with the digital stability monitor disabled. The results from the standard analog injection technique indicate close matches with the measurements from the proposed digital technique and the discrete-time model. Fig. 9 shows the experimentally observed dynamics of finj , ϕ, and δ, captured in Chipscope under an abrupt power stage line transient. In particular, Fig. 9 shows an input voltage change in the synchronous buck converter power stage from 12 to 8 V with the PID compensator of System 1. Under this change, the monitor recognizes the bus voltage change and updates the stability margin monitor outputs accordingly. Note that the high frequency noise seen in the monitored phase margin is an artifact of the bandpass filter sample rate selection discussed previously. Fig. 10 shows load transient responses for both System 1 (buck converter) and System 4 (DCM boost converter) with the stability margin monitor activated. First, Fig. 10(a) is the load transient response, from 2.5 to 0 A, of System 1 with the phase margin monitor running. Note that the frequency of oscillation imposed by Vz is equal to the crossover frequency while the amplitude of the perturbation is only ±1 LSB due to the action of the feedback loop controlling δ. Similarly, Fig. 10(b) shows the load transient response for System 4, the DCM boost converter. Since the boost converter is operating in DCM, the load transient (from 0.3 to 50 mA) significantly affects the output voltage loop crossover frequency, as indicated by the oscillation frequency before and after the transient in Fig. 10(b). Note that a comparison of load transient responses with and without the stability margin monitor is given in  showing that the proposed system has little effect on the overall dynamic performance of the output voltage control loop. Fig. 9. Dynamic response of stability monitor under a change from V g = 12 to V g = 8 V with the compensator of System 1. (a) Crossover frequency fc , (b) average phase margin ϕ, and (c) injection amplitude δ. In the response of Fig. 10, notice the output voltage perturbation combined with the action of the integrator in the PID compensator centers the dc value of the output voltage in the zero-error bin with accuracy related to the DPWM resolution rather than the ADC resolution, as discussed previously. Since in general the DPWM resolution is finer than the ADC resolution, this equates to more precise dc regulation accuracy with the imposed output voltage oscillation. As a final note, the hardware required to implement the stability margin monitor is summarized in Table IV. As indicated, to implement the entire stability margin monitor requires a relatively modest gate count and no additional memory. Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. MORRONI et al.: AN ONLINE STABILITY MARGIN MONITOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 2647 Fig. 10. AC coupled output voltage (channel 1) and inductor current (channel 2) waveforms. (a) System 1 (synchronous buck) with crossover frequency and phase margin monitoring during a 2.5 A → 0 A load transient. (b) System 4 (DCM boost) with the crossover frequency and phase margin monitor during a 0.3 A → 0.05 A load transient. TABLE IV REQUIRED DIGITAL LOGIC RESOURCES TO IMPLEMENT DIGITAL STABILITY MONITOR V. CONCLUSION This paper has presented a practical method for continuously monitoring the crossover frequency and phase margin in digitally controlled SMPS. The proposed approach does not require open loop operation and is capable of converging to correct results in the presence of load transients or other disturbances. Further, the stability margin monitoring requires and ensures that only ±1 LSB output voltage perturbation is caused by the monitor. Small-signal models are derived by applying an envelope modeling approach and used to design the stability margin monitor control loop. Experimental results are presented using four different system configurations indicating close matches between monitored and expected crossover frequencies and phase margins. Experimental results are also presented showing the observed output voltage and inductor current during a load transient, indicating that the control loop is unaffected by disturbances. REFERENCES  R. D. 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Zane, “Small-signal discrete-time modeling of digitally controlled DC-DC converters,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2552–2556, Nov. 2007. Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply. 2648 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009 Jeffrey Morroni (S’06) received the B.S. and M.S. degrees in electrical engineering from the University of Colorado, Boulder, in 2006 and 2008, respectively. Currently, he is working toward the Ph.D. degree in power electronics from the Department of Electrical and Computer Engineering, Colorado Power Electronics Center, University of Colorado, Boulder. His current research interests in power electronics include advanced digital control techniques with a general focus on adaptive tuning. Dragan Maksimović (M’89–SM’04) received the B.S. and M.S. degrees in electrical engineering from the University of Belgrade, Belgrade, Yugoslavia, in 1984 and 1986, respectively, and the Ph.D. degree from the California Institute of Technology, Pasadena, in 1989. From 1989 to 1992, he was with the University of Belgrade. He has been with the Department of Electrical and Computer Engineering, University of Colorado, Boulder, since 1992, and he is currently a Professor and Director of the Colorado Power Electronics Center there. His current research interests include digital control techniques and mixed-signal integrated circuit design for power electronics. Dr. Maksimovic received the National Science Foundation CAREER Award in 1997, the Power Electronics Society Transactions Prize Paper Award in 1997, the Bruce Holland Excellence in Teaching Award in 2004, and the University of Colorado Inventor of the Year Award in 2006. Regan Zane (S’98–M’00–SM’07) received the B.S, M.S., and Ph.D. degrees in electrical engineering from the University of Colorado, Boulder, in 1996, 1998, and 1999, respectively. From 1999 to 2001, he was with GE Global Research Center, Niskayuna, NY, where he developed custom integrated circuit controllers for power electronic circuits and systems. He has been with the Department of Electrical and Computer Engineering, Colorado Power Electronics Center, University of Colorado, Boulder, as an Assistant Professor from 2001 to 2007, and as an Associate Professor of electrical and computer engineering, since 2008. He has ongoing research programs in energy-efficient lighting systems, adaptive algorithms and digital control techniques in power electronics systems, and low power energy harvesting for wireless devices. Dr. Zane received the 2004 National Science Foundation CAREER Award, the 2005 IEEE Microwave Best Paper Prize, the 2008 IEEE PELS Transactions Prize Letter Award, and the 2008 IEEE PELS Richard M. Bass Outstanding Young Power Electronics Engineer Award. He received from the University of Colorado the 2006 Inventor of the Year award, the 2006 Provost Faculty Achievement Award, and the 2008 John and Mercedes Peebles Innovation in Teaching Award. He is the Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS, LETTERS, and as a Member-at-Large of the IEEE POWER ELECTRONICS SOCIETY (PELS) AdCom. Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:48 from IEEE Xplore. Restrictions apply.
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