American Megatrends | MB967 | User`s manual | American Megatrends MB967 User`s manual

MB967
Intel® Ivy Bridge / C216 PCH
USER’S MANUAL
Version 1.3
Acknowledgments
AMI is a registered trademark of American Megatrends, Inc.
PS/2 is a trademark of International Business Machines
Corporation.
Intel is a registered trademark of Intel Corporation.
Microsoft Windows is a registered trademark of Microsoft
Corporation.
Winbond is a registered trademark of Winbond Electronics
Corporation.
All other product names or trademarks are properties of their
respective owners.
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MB967 User’s Manual
Table of Contents
Introduction .............................................................. 6
Product Description............................................................. 6
Specifications ...................................................................... 7
Checklist .............................................................................. 8
Board Dimensions ............................................................... 9
Installations ............................................................ 10
Installing the CPU ............................................................. 11
Installing the Memory ....................................................... 12
Setting the Jumpers ........................................................... 13
Jumper Locations on MB967 ............................................. 14
Jumper Settings on MB967................................................ 15
JP6, JP5, JP4: Bypass LANs & Reboot Setting ................. 15
JP2: Clear CMOS Contents ............................................... 15
JP3: Clear ME RTC Contents ............................................ 16
JP7: Flash Descriptor Security Override ............................ 16
JP9: ATX & AT Mode Select ............................................ 16
J17: PCIE1 & PCIE2 Golden Finger PCI-e Configuration
Connectors on MB967 ........................................ 17
Connector Locations on MB967 ........................................ 18
CN1: USB 3.0 Box Header ................................................ 19
CN2: COM1 RJ45 Connector ............................................ 19
CN3: CFast Connector ....................................................... 19
CN4: USB Connector ........................................................ 19
CN5, CN9: LAN Connectors ............................................. 19
CN7, CN8: SATA HDD Connector................................... 19
J1, J3, J7, J19: Power Output Connector ........................... 19
J2: Front Panel Function Connector .................................. 20
J4: COM2 Serial Port ........................................................ 20
J5: ATX 12V Power Connector ......................................... 20
J6: 24-pin ATX Power Connector ..................................... 21
J8, J9: Channel B DDR3 Socket ....................................... 21
J10: LPC Debug Port (Reserved for factory use only)....... 21
J11, J12: Channel A DDR3 Socket .................................... 21
J13: VGA Box Header ....................................................... 21
J14: Slim Type II Compact Flash Connector ..................... 21
J16: Mini PCI-e Card & m-SATA Connector.................... 21
J18: SPI Debug Port (Reserved for factory use only) ........ 21
J20, J21: USB 2.0 Pin Header ........................................... 22
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FAN1, 2, 3: System Fan Power Connector ........................ 22
CPU_FAN1: CPU Fan Power Connector .......................... 22
SW1: Software reset button ............................................... 22
PCIE1: PCI-e x8 Golden Finger 1 ..................................... 22
PCIE2: PCI-e x8 Golden Finger 2 ..................................... 22
LED1: Power, Bypass & Status LED ................................. 23
Digital I/O Sample Configuration .......................... 25
Watchdog Timer Configuration ............................ 29
BIOS Setup ............................................................. 33
BIOS Introduction.............................................................. 34
BIOS Setup ........................................................................ 34
Advanced Settings.............................................................. 36
Chipset Settings.................................................................. 49
Boot Settings ...................................................................... 54
CSM parameters................................................................. 55
Security Settings ................................................................ 56
Drivers Installation ................................................. 59
Intel Chipset Software Installation Utility ........................ 60
VGA Drivers Installation .................................................. 63
LAN Drivers Installation................................................... 66
Intel® Management Engine Interface ............................... 70
Intel® USB 3.0 Drivers ..................................................... 73
Appendix ................................................................. 76
A. I/O Port Address Map .................................................. 76
B. Interrupt Request Lines (IRQ) ...................................... 76
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MB967 User’s Manual
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INSTALLATIONS
Introduction
Product Description
®
The MB967 networking motherboard is based on the latest Intel C216
®
chipset. The platform supports 3rd generation Intel Core processor
family with LGA1155 packing and features an integrated dual-channel
ECC or Non-ECC DDR3 memory controller as well as a graphics core.
®
The latest Intel processors provide advanced performance in both
computing and graphics quality. This meets the requirement of customers
in the network security (Firewall, VPN, UTM…) and server market
segment.
The C216 platform is made with 22-nanometer technology that supports
Intel’s first processor architecture to unite the CPU and the graphics core
on the transistor level. MB967 utilizes the dramatic increase in
performance provided this Intel’s latest cutting-edge technology.
®
Measuring 355mm x 185mm, MB967 features Intel Active
Management Technology 8.0, offers eight GbE LAN ports, two fast
6Gbps SATA ports and two USB3.0 ports.
MB967 Features






6
Supports 8 Intel® 10/100/1000 LAN ports with 2 segments Bypass
LAN bypass enable/disable pre-setting by BIOS when power on/off
Supports Intel® 3rd Generation Core i7/i5/i3 / Xeon® processors
DDR3 x4, up to 32 GB
Mini PCI-e (m-SATA compatible) socket x1, CF socket x1,
CFast socket x1
iAMT 8.0 support
MB967 User’s Manual
INSTALLATIONS
Specifications
Product Name
MB967
Processor
Support for Intel® Sandy-Bridge and Ivy-Bridge processors
which fall within mainstream TDP envelope, up to 95W TDP.
Support for the following Intel® technologies:
 Intel SSE/MMX, AES and AVX new instructions
 VT-x and VT-d Virtualization Technologies
 ACPI 3.0
 Intel® 64 (64-bit extensions)
 PCI-e 3.0 (1x16 or 2x8)
 DMI 2.0
Chipset
BIOS
Memory
Video
Intel® Panther Point C216 PCH
 SATA 3.0
 iAMT 8.0
AMI BIOS
 Four DDR3 UDIMM total for 32GB max memory
 Dual channel DDR3 up to 1600 MHz
 Unbuffered
 ECC or non-ECC


Intel® CPU integrated graphics
IBASE VGA4 pin header on board


Eth1: Intel® 82579LM GbE PHY w/ iAMT 8.0 supporting.
No Bypass
Eth2~4: Intel® 82583V GbE. No Bypass.
Eth5~6: Intel® 82583V GbE. Supports Bypass.
Eth7~8: Intel® 82583V GbE. Supports Bypass.
Two segment hardware Bypass (Eth5 & 6; Eth7 & 8)
Control by GPIO / Watchdog / Electrical Disconnect
Bypass mode selection (H/W switch or BIOS)
SATA
Connector

SATA III (6.0Gb/s): 2 ports
USB Port



Two USB 3.0 ports at front panel
USB 3.0 box header on board
Four USB 2.0 pin header on board
Compact
Flash
ACARD ARC772 SATA to PATA for CompactFlash type II
Network
Controller
Network
Bypass
LPC I/O
Fan
Connector




Fintek F81866A:
 RS-232 [2x5] Pin Header on board x1
 RJ-45 Console x1
 KB/Mouse [1x6] Pin header
 Hardware monitors
 Fan connector x4
4-pin fan connectors:
 One for CPU fan (Smart Fan)
 Three for System fans (Smart Fan)
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INSTALLATIONS
Smart Fan
Control
The active temperature may be adjusted based on system
thermal test result
RTC
Intel C216 built-in RTC with on-board lithium battery & holder
Expansion
Slot
Expansion
Interface


Golden finger PCI-e x8, Front
Golden finger PCI-e x8, Rear



Mini PCI-e socket x1 (m-SATA compatible)
CF card socket x1
CFast card socket x1
#3 LED: Status (GPIO control, Yellow / Red)
#2 LED: Bypass: Green = LAN 5-6 or 7-8 Bypass,
Off = LAN Normal
#1 LED: Power
(Green = Power On, Off= No Power)
Front Panel
LED
LCM
Front Button
& Connector
Watchdog
Timer
TPM
Operating
Temperature
Storage
Temperature
2x16 characters LCM (COM2)
 Two RJ-45 1x4 connectors for Eth1~4 & 5~6
 USB 3.0 x2
 RJ-45 (for console, COM1)
 Three LEDs for Power, Bypass & Status
 Factory Mode Restore Reset Switch
Yes (256 segments, 0, 1, 2…255 sec/min)
Present in BMC and configurable by O/S agent to
automatically reset system if O/S hangs
nuvoTon WPCT210 TPM1.2
0C ~ 60C
-20C ~ 80C
Operational
Humidity
10% ~ 90% Relative Humidity (non-condensing)
RoHS
Compliant
Yes
Board Size
355 x 185mm, 1.6mm thickness
Checklist
Your MB967 package should include the items listed below.
 MB967 motherboard
 Driver DVD
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MB967 User’s Manual
INSTALLATIONS
Board Dimensions
MB967 User’s Manual
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INSTALLATIONS
Installations
This section provides information on how to use the jumpers and
connectors on the MB967 in order to set up a workable system. The
topics covered are:
Installing the CPU ................................................................................ 11
Installing the Memory .......................................................................... 12
Setting the Jumpers .............................................................................. 13
Connectors on MB967 ......................................................................... 14
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MB967 User’s Manual
INSTALLATIONS
Installing the CPU
The MB967 board supports an LGA1155 Socket (shown below) for Intel
Clarkdale processors.
To install the CPU, unlock first the socket by pressing the lever sideways,
then lift it up to a 90-degree. Then, position the CPU above the socket
such that the CPU corner aligns with the gold triangle matching the
socket corner with a small triangle. Carefully insert the CPU into the
socket and push down the lever to secure the CPU. Then, install the heat
sink and fan.
NOTE: Ensure that the CPU heat sink and the CPU top surface are in
total contact to avoid CPU overheating problem that would
cause your system to hang or be unstable.
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INSTALLATIONS
Installing the Memory
The MB967 board supports four DDR3 memory socket for a maximum
total memory of 32GB in DDR3 DIMM memory type.
Installing and Removing Memory Modules
To install the DDR3 modules, locate the memory slot on the board and
perform the following steps:
1. Hold the DDR3 module so that the key of the DDR3 module aligned
with that on the memory slot.
2. Gently push the DDR3 module in an upright position until the clips of
the slot close to hold the DDR3 module in place when the DDR3
module touches the bottom of the slot.
3. To remove the DDR3 module, press the clips with both hands.
DDR3 Module
12
Lock
Lock
Lock
Lock
MB967 User’s Manual
INSTALLATIONS
Setting the Jumpers
Jumpers are used on MB967 to select various settings and features
according to your needs and applications. Contact your supplier if you
have doubts about the best configuration for your needs. The following
lists the connectors on MB967 and their respective functions.
Jumper Locations on MB967 ............................................................... 14
Jumper Settings on MB967.................................................................. 15
JP6,JP5, JP4: Bypass LANs & Reboot Setting .................................... 15
JP2: Clear CMOS Contents ................................................................. 15
JP3: Clear ME RTC Contents .............................................................. 16
JP7: Flash Descriptor Security Override………………………………16
JP9: ATX & AT Mode Select .............................................................. 16
J17: PCIE1 & PCIE2 Golden Finger PCI-e Configuration .................. 16
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INSTALLATIONS
Jumper Locations on MB967
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Jumper Settings on MB967
JP6, JP5, JP4: Bypass LANs & Reboot Setting
JP6,JP5
JP4
Setting
Function
Power OFF
Power ON,
Power ON OS run
software
Normal Bypass Normal Bypass Normal Bypass
JP4 Pin 1-2
& 3-4 Open
JP5,JP6 Pin
1-2 Closed
JP4 Pin 1-2
& 3-4 Open
JP5,JP6 Pin
2-3 Closed
Default
Setting
JP4 Pin 1-2
& 3-4
Closed
JP5,JP6 Pin
1-2 Closed
JP4 Pin 3-4
Closed &
1-2 Open
JP5,JP6 Pin
1-2 Closed
System will
bypass
LANs upon
the time out
of watchdog
timer.
System
LANs
bypass
function
controlled
by SIO
GPIO43&44
or BIOS
Select.
System will
reboot upon
the time out
of watchdog
timer.
System will
bypass
LANs &
reboot upon
the time out
of watchdog
timer.



By BIOS Setting




LAN
Bypass &
System
reboot
LAN
Normal &
System
reboot
JP2: Clear CMOS Contents
Use JP2 to clear the CMOS contents. Note that the ATX-power connector
should be disconnected from the board before clearing CMOS.
JP3
Setting
Function
Pin 1-2
Short/Closed
Normal
Pin 2-3
Short/Closed
Clear CMOS
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INSTALLATIONS
JP3: Clear ME RTC Contents
JP3
Setting
Function
Pin 1-2
Short/Closed
Normal
Pin 2-3
Short/Closed
Clear ME RTC
JP7: Flash Descriptor Security Override
(ME BIOS Update Jumper)
JP7
Setting
Function
Open
Disable
(Default)
Short/Closed
Enable to update BIOS
JP9: ATX & AT Mode Select
JP9
Setting
Function
Short/Closed
AT Mode
(Default)
Open
ATX Mode
J17: PCIE1 & PCIE2 Golden Finger PCI-e Configuration
J17
16
Setting
Function
Remarks
Open
Combine to
1x16
For CPU with
1x16 support
Short /
Closed
Separate to2x8
Default for CPU
with 2x8 support
MB967 User’s Manual
INSTALLATIONS
Connectors on MB967
Connector Locations on MB967 .......................................................... 18
CN1: USB 3.0 Box Header.................................................................. 19
CN2: COM1 RJ45 Connector .............................................................. 19
CN3:CFast Connector .......................................................................... 19
CN4: USB Connector .......................................................................... 19
CN5, CN9 : LAN Connectors .............................................................. 19
CN7, CN8: SATA HDD Connector..................................................... 19
J1, J3, J7, J19: Power Output Connector ............................................. 19
J2: Front Panel Function Connector .................................................... 20
J4: COM2 Serial Port .......................................................................... 20
J5: ATX 12V Power Connector ........................................................... 20
J6: 24-pin ATX Power Connector ....................................................... 21
J8, J9: Channel B DDR3 Socket ......................................................... 21
J10: LPC Debug Port (Reserved for factory use only)......................... 21
J11, J12: Channel A DDR3 Socket ...................................................... 21
J13: VGA Box Header ......................................................................... 21
J14: Slim Type II Compact Flash Connector ....................................... 21
J16: Mini PCI-e Card & m-SATA Connector...................................... 21
J18: SPI Debug Port (Reserved for factory use only) .......................... 21
J20, J21: USB 2.0 Pin Header ............................................................. 22
FAN1, 2, 3: System Fan Power Connector .......................................... 22
CPU_FAN1: CPU Fan Power Connector ............................................ 22
SW1: Software reset button ................................................................. 22
PCIE1: PCI-e x8 Golden Finger 1 ....................................................... 22
PCIE2: PCI-e x8 Golden Finger 2 ....................................................... 22
LED1: Power, Bypass & Status LED .................................................. 23
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INSTALLATIONS
Connector Locations on MB967
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INSTALLATIONS
CN1: USB 3.0 Box Header
CN2: COM1 RJ45 Connector
Pin #
Signal Name (RS-232)
1
RTS, Request to send
2
DTR, Data terminal ready
3
TXD, Transmit data
4
Ground
5
Ground
6
RXD, Receive data
7
DSR, Data set ready
8
CTS, Clear to send
CN3: CFast Connector
CN4: USB Connector
CN5, CN9: LAN Connectors
CN7, CN8: SATA HDD Connector
Pin # Signal Name
1
Ground
2
TX+
3
TX4
Ground
5
RX6
RX+
7
Ground
J1, J3, J7, J19: Power Output Connector
Pin # Signal Name
4
1
1
+5V
2
GND
3
GND
4
+12V
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INSTALLATIONS
J2: Front Panel Function Connector
Signal Name
Pin #
PWR LED +
1
NC
3
PWR LED- (GND)
5
NC
7
GND
9
GND
11
PWR_SW
13
SLED+
15
GND
17
HDD LED +
19
Pin #
2
4
6
8
10
12
14
16
18
20
Signal Name
SPK +
NC
SPK – (GND)
+5V
NC
NC
PWR_SW
SLEDRST
HDD LED -
J4: COM2 Serial Port
Pin #
Signal Name (RS-232)
1
DCD, Data carrier detect
2
RXD, Receive data
3
TXD, Transmit data
4
DTR, Data terminal ready
5
Ground
6
DSR, Data set ready
7
RTS, Request to send
8
CTS, Clear to send
9
RI, Ring indicator
10
No Connect.
J5: ATX 12V Power Connector
Signal Name Pin #
+12V
5
+12V
6
+12V
7
+12V
8
20
Pin #
1
2
3
4
Signal Name
Ground
Ground
Ground
Ground
MB967 User’s Manual
INSTALLATIONS
J6: 24-pin ATX Power Connector
Signal Name Pin # Pin #
3.3V
13
1
-12V
14
2
Ground
15
3
PS-ON
16
4
Ground
17
5
Ground
18
6
Ground
19
7
-5V
20
8
+5V
21
9
+5V
22
10
+5V
23
11
Ground
24
12
Signal Name
3.3V
3.3V
Ground
+5V
Ground
+5V
Ground
Power good
5VSB
+12V
+12V
+3.3V
J8, J9: Channel B DDR3 Socket
J8, J9 are the second-channel DDR3 sockets.
J10: LPC Debug Port (Reserved for factory use only)
J11, J12: Channel A DDR3 Socket
J11, J12 are the first-channel DDR3 sockets.
J13: VGA Box Header
Signal Name Pin #
R
1
G
2
B
3
NC
4
GND
5
GND
6
GND
7
GND
8
Pin #
9
10
11
12
13
14
15
Signal Name
+5V
GND
NC
SPD1
Hsync
Vsync
SPCLK
J14: Slim Type II Compact Flash Connector
J16: Mini PCI-e Card & m-SATA Connector
J18: SPI Debug Port (Reserved for factory use only)
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INSTALLATIONS
J20, J21: USB 2.0 Pin Header
FAN1, 2, 3: System Fan Power Connector
FAN1/2/3 are 4-pin headers for System fan power.
Pin #
Signal Name
1
Ground
2
+12V
3
Rotation detection
4
Control
CPU_FAN1: CPU Fan Power Connector
Pin #
Signal Name
1
Ground
2
+12V
3
Rotation detection
4
Control
SW1: Software reset button
Signal Name Pin #
GND
1
Pin #
2
Signal Name
PCH
GPIO7
IO Base:
Read IO 0x500 and set bit 7 to “1” (Enabled GPIO function)
Read IO 0x504 and set bit 7 to “1” (GPIO act as GPI )
Read IO 0x50C and check the bit 7 (Control Pin)
Note: SW3 is controlled by GPIO only.
PCIE1: PCI-e x8 Golden Finger 1
PCIE2: PCI-e x8 Golden Finger 2
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MB967 User’s Manual
INSTALLATIONS
LED1: Power, Bypass & Status LED
C1
A1 Status (Yellow / Red)
C2
A2 Bypass (Green)
C3
A3 Power
Signal Name
SIO GPIO32
Bypass LEDPOWER LEDSTATUS LED
YELLOW
RED
(Green)
Pin #
C1
C2
C3
GPIO33
H
L
Pin #
A1
A2
A3
Signal Name
SIO GPIO33
Bypass LED+
POWER LED+
GPIO32
L
H
Index port: 4E
Data port: 4F
Device: 06
30h  bit1 = 1
C0h  set bit2, bit3 = 1 for GPO
C3h  set bit2, bit3 = 1 for Push Pull
C1h  bit2, bit3 (Control pin) for GPO32, 33
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Digital I/O Sample Configuration
Filename:Main.cpp
//--------------------------------------------------------------------------//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
//--------------------------------------------------------------------------#include <dos.h>
#include <conio.h>
#include <stdio.h>
#include <stdlib.h>
#include "F81865.H"
#define BIT0 0x01
#define BIT1 0x02
#define BIT2 0x04
#define BIT3 0x08
#define BIT4 0x10
#define BIT5 0x20
#define BIT6 0x40
#define BIT7 0x80
//--------------------------------------------------------------------------int main (void);
void Dio5Initial(void);
void Dio5SetOutput(unsigned char);
unsigned char Dio5GetInput(void);
void Dio5SetDirection(unsigned char);
unsigned char Dio5GetDirection(void);
//--------------------------------------------------------------------------int main (void)
{
char SIO;
unsigned char DIO;
printf("Fintek 81865/81866 digital I/O test program\n");
SIO = Init_F81865();
if (SIO == 0)
{
printf("Can not detect Fintek 81865/81866, program abort.\n");
return(1);
}//if (SIO == 0)
Dio5Initial();
/*
//for GPIO50..57
Dio5SetDirection(0xF0);
//GP50..53 = input, GP54..57=output
printf("Current DIO direction = 0x%X\n", Dio5GetDirection());
printf("Current DIO status = 0x%X\n", Dio5GetInput());
printf("Set DIO output to high\n");
Dio5SetOutput(0x0F);
printf("Set DIO output to low\n");
Dio5SetOutput(0x00);
*/
//for GPIO50..57
Dio5SetDirection(0xF0);
//
//GP50..53 = input, GP54..57=output
Dio5SetOutput(0x00);
DIO = Dio5GetInput() & 0x0F;
//clear
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INSTALLATIONS
Dio5SetOutput(0x00);
//clear
DIO = Dio5GetInput() & 0x0F;
if (DIO != 0x0A)
{
printf("The Fintek 81865 digital IO abnormal, abort.\n");
return(1);
}//if (DIO != 0x0A)
Dio5SetOutput(0xA0);
Dio5SetOutput(0xF0);
Dio5SetOutput(0xA0);
//clr# is high
//clk and clr# is high
//clr# is high
DIO = Dio5GetInput() & 0x0F;
if (DIO != 0x05)
{
printf("The Fintek 81865 digital IO abnormal, abort.\n");
return(1);
}
printf("!!! Pass !!!\n");
return 0;
}
//--------------------------------------------------------------------------void Dio5Initial(void)
{
unsigned char ucBuf;
//switch GPIO multi-function pin for gpio 50~57
//gpio53~57 UR5_FULL_EN(bit1), clear UR6_FULL_EN(bit3)
//set UR5_FULL_EN,should set UR_GP_PROG_EN = 1 (reg26,bit0) first
ucBuf = Get_F81865_Reg(0x26);
ucBuf |= BIT0;
Set_F81865_Reg(0x26, ucBuf);
//set UR5_FULL_EN(bit1), clear UR6_FULL_EN(bit3)
ucBuf = Get_F81865_Reg(0x2A);
ucBuf &= ~BIT3;//clear bit 3,
ucBuf |= BIT1;//set bit 1,
Set_F81865_Reg(0x2a, ucBuf);
//GPIO51 ~ GPIO52
//clear UR6_ALT_EN(bit5), IR_ALT_EN(bit4),set FDC_GP_EN(bit3)
//GPIO50
//set FDC_GP_EN(bit3), clear RTS6_ALT_EN(RTS6_2_ALT_EN)(bit6)
ucBuf = Get_F81865_Reg(0x2A);
ucBuf &= ~(BIT4+BIT5+BIT6);
//clear UR6_ALT_EN(bit5), IR_ALT_EN(bit4),
RTS6_ALT_EN(RTS6_2_ALT_EN)(bit6)
Set_F81865_Reg(0x2a, ucBuf);
//set FDC_GP_EN(bit3), should clear UR_GP_PROG_EN (reg26,bit0) first
ucBuf = Get_F81865_Reg(0x26);
ucBuf &= ~BIT0;
Set_F81865_Reg(0x26, ucBuf);//clear UR_GP_PROG_EN = 0 (reg26,bit0)
ucBuf = Get_F81865_Reg(0x2A);
ucBuf |= BIT3;
//set FDC_GP_EN(bit3),
Set_F81865_Reg(0x2a, ucBuf);
Set_F81865_LD(0x06);
//switch to logic device 6
//enable the GP5 group
ucBuf = Get_F81865_Reg(0x30);
ucBuf |= 0x01;
Set_F81865_Reg(0x30, ucBuf);
Set_F81865_Reg(0xA0, 0x00);
Set_F81865_Reg(0xA3, 0xFF);
}
//---------------------------------------------------------------------------
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MB967 User’s Manual
//define as input mode
//push pull mode
INSTALLATIONS
void Dio5SetOutput(unsigned char NewData)
{
Set_F81865_LD(0x06);
Set_F81865_Reg(0xA1, NewData);
}
//--------------------------------------------------------------------------unsigned char Dio5GetInput(void)
{
unsigned char result;
Set_F81865_LD(0x06);
result = Get_F81865_Reg(0xA2);
return (result);
}
//--------------------------------------------------------------------------void Dio5SetDirection(unsigned char NewData)
{
//NewData : 1 for input, 0 for output
Set_F81865_LD(0x06);
Set_F81865_Reg(0xA0, NewData);
}
//--------------------------------------------------------------------------unsigned char Dio5GetDirection(void)
{
unsigned char result;
Set_F81865_LD(0x06);
result = Get_F81865_Reg(0xA0);
return (result);
//switch to logic device 6
//switch to logic device 6
//switch to logic device 6
//switch to logic device 6
}
//---------------------------------------------------------------------------
Filename:81865.cpp
//--------------------------------------------------------------------------//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
//--------------------------------------------------------------------------#include "F81865.H"
#include <dos.h>
//--------------------------------------------------------------------------unsigned int F81865_BASE;
void Unlock_F81865 (void);
void Lock_F81865 (void);
//--------------------------------------------------------------------------unsigned int Init_F81865(void)
{
unsigned int result;
unsigned char ucDid;
F81865_BASE = 0x4E;
result = F81865_BASE;
ucDid = Get_F81865_Reg(0x20);
if (ucDid == 0x07||ucDid == 0x10)
{
goto Init_Finish;
}
//Fintek 81865/66
F81865_BASE = 0x2E;
result = F81865_BASE;
ucDid = Get_F81865_Reg(0x20);
if (ucDid == 0x07||ucDid == 0x10)
{
goto Init_Finish;
}
//Fintek 81865/66
F81865_BASE = 0x00;
result = F81865_BASE;
MB967 User’s Manual
27
INSTALLATIONS
Init_Finish:
return (result);
}
//--------------------------------------------------------------------------void Unlock_F81865 (void)
{
outportb(F81865_INDEX_PORT, F81865_UNLOCK);
outportb(F81865_INDEX_PORT, F81865_UNLOCK);
}
//--------------------------------------------------------------------------void Lock_F81865 (void)
{
outportb(F81865_INDEX_PORT, F81865_LOCK);
}
//--------------------------------------------------------------------------void Set_F81865_LD( unsigned char LD)
{
Unlock_F81865();
outportb(F81865_INDEX_PORT, F81865_REG_LD);
outportb(F81865_DATA_PORT, LD);
Lock_F81865();
}
//--------------------------------------------------------------------------void Set_F81865_Reg( unsigned char REG, unsigned char DATA)
{
Unlock_F81865();
outportb(F81865_INDEX_PORT, REG);
outportb(F81865_DATA_PORT, DATA);
Lock_F81865();
}
//--------------------------------------------------------------------------unsigned char Get_F81865_Reg(unsigned char REG)
{
unsigned char Result;
Unlock_F81865();
outportb(F81865_INDEX_PORT, REG);
Result = inportb(F81865_DATA_PORT);
Lock_F81865();
return Result;
}
//---------------------------------------------------------------------------
Filename:81865.h
//--------------------------------------------------------------------------//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
//--------------------------------------------------------------------------#ifndef __F81865_H
#define __F81865_H
1
//--------------------------------------------------------------------------#define F81865_INDEX_PORT
(F81865_BASE)
#define F81865_DATA_PORT
(F81865_BASE+1)
//--------------------------------------------------------------------------#define F81865_REG_LD
0x07
//--------------------------------------------------------------------------#define F81865_UNLOCK
0x87
#define F81865_LOCK
0xAA
//--------------------------------------------------------------------------unsigned int Init_F81865(void);
void Set_F81865_LD( unsigned char);
void Set_F81865_Reg( unsigned char, unsigned char);
unsigned char Get_F81865_Reg( unsigned char);
//--------------------------------------------------------------------------#endif //__F81865_H
28
MB967 User’s Manual
INSTALLATIONS
Watchdog Timer Configuration
The WDT is used to generate a variety of output signals after a user
programmable count. The WDT is suitable for use in the prevention of
system lock-up, such as when software becomes trapped in a deadlock.
Under these sorts of circumstances, the timer will count to zero and the
selected outputs will be driven. Under normal circumstance, the user will
restart the WDT at regular intervals before the timer counts to zero.
SAMPLE CODE:
This code and information is provided "as is" without warranty of any
kind, either expressed or implied, including but not limited to the implied
warranties of merchantability and/or fitness for a particular purpose.
//--------------------------------------------------------------------------//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
//--------------------------------------------------------------------------#include <dos.h>
#include <conio.h>
#include <stdio.h>
#include <stdlib.h>
#include "F81866.H"
//--------------------------------------------------------------------------int main (int argc, char *argv[]);
void EnableWDT(int);
void DisableWDT(void);
//--------------------------------------------------------------------------int main (int argc, char *argv[])
{
unsigned char bBuf;
unsigned char bTime;
char **endptr;
char SIO;
printf("Fintek 81866 watch dog program\n");
SIO = Init_F81866();
if (SIO == 0)
{
printf("Can not detect Fintek 81866, program abort.\n");
return(1);
}//if (SIO == 0)
if (argc != 2)
{
printf(" Parameter incorrect!!\n");
return (1);
}
bTime = strtol (argv[1], endptr, 10);
printf("System will reset after %d seconds\n", bTime);
if (bTime)
{
EnableWDT(bTime); }
else
{
DisableWDT();
}
MB967 User’s Manual
29
INSTALLATIONS
return 0;
}
//--------------------------------------------------------------------------void EnableWDT(int interval)
{
unsigned char bBuf;
bBuf = Get_F81866_Reg(0x2B);
bBuf &= (~0x20);
Set_F81866_Reg(0x2B, bBuf);
//Enable WDTO
Set_F81866_LD(0x07);
Set_F81866_Reg(0x30, 0x01);
//switch to logic device 7
//enable timer
bBuf = Get_F81866_Reg(0xF5);
bBuf &= (~0x0F);
bBuf |= 0x52;
Set_F81866_Reg(0xF5, bBuf);
//count mode is second
Set_F81866_Reg(0xF6, interval);
//set timer
bBuf = Get_F81866_Reg(0xFA);
bBuf |= 0x01;
Set_F81866_Reg(0xFA, bBuf);
//enable WDTO output
bBuf = Get_F81866_Reg(0xF5);
bBuf |= 0x20;
Set_F81866_Reg(0xF5, bBuf);
//start counting
}
//--------------------------------------------------------------------------void DisableWDT(void)
{
unsigned char bBuf;
Set_F81866_LD(0x07);
//switch to logic device 7
bBuf = Get_F81866_Reg(0xFA);
bBuf &= ~0x01;
Set_F81866_Reg(0xFA, bBuf);
//disable WDTO output
bBuf = Get_F81866_Reg(0xF5);
bBuf &= ~0x20;
bBuf |= 0x40;
Set_F81866_Reg(0xF5, bBuf);
//disable WDT
}
//--------------------------------------------------------------------------//--------------------------------------------------------------------------//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
//--------------------------------------------------------------------------#include "F81866.H"
#include <dos.h>
//--------------------------------------------------------------------------unsigned int F81866_BASE;
void Unlock_F81866 (void);
void Lock_F81866 (void);
//--------------------------------------------------------------------------unsigned int Init_F81866(void)
{
unsigned int result;
unsigned char ucDid;
F81866_BASE = 0x4E;
result = F81866_BASE;
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MB967 User’s Manual
INSTALLATIONS
ucDid = Get_F81866_Reg(0x20);
if (ucDid == 0x07)
{
goto Init_Finish;
}
F81866_BASE = 0x2E;
result = F81866_BASE;
ucDid = Get_F81866_Reg(0x20);
if (ucDid == 0x07)
{
goto Init_Finish;
}
//Fintek 81866
//Fintek 81866
F81866_BASE = 0x00;
result = F81866_BASE;
Init_Finish:
return (result);
}
//--------------------------------------------------------------------------void Unlock_F81866 (void)
{
outportb(F81866_INDEX_PORT, F81866_UNLOCK);
outportb(F81866_INDEX_PORT, F81866_UNLOCK);
}
//--------------------------------------------------------------------------void Lock_F81866 (void)
{
outportb(F81866_INDEX_PORT, F81866_LOCK);
}
//--------------------------------------------------------------------------void Set_F81866_LD( unsigned char LD)
{
Unlock_F81866();
outportb(F81866_INDEX_PORT, F81866_REG_LD);
outportb(F81866_DATA_PORT, LD);
Lock_F81866();
}
//--------------------------------------------------------------------------void Set_F81866_Reg( unsigned char REG, unsigned char DATA)
{
Unlock_F81866();
outportb(F81866_INDEX_PORT, REG);
outportb(F81866_DATA_PORT, DATA);
Lock_F81866();
}
//--------------------------------------------------------------------------unsigned char Get_F81866_Reg(unsigned char REG)
{
unsigned char Result;
Unlock_F81866();
outportb(F81866_INDEX_PORT, REG);
Result = inportb(F81866_DATA_PORT);
Lock_F81866();
return Result;
}
//--------------------------------------------------------------------------//--------------------------------------------------------------------------//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
//--------------------------------------------------------------------------#ifndef __F81866_H
#define __F81866_H
1
//--------------------------------------------------------------------------#define F81866_INDEX_PORT
(F81866_BASE)
#define F81866_DATA_PORT
(F81866_BASE+1)
//--------------------------------------------------------------------------#define F81866_REG_LD
0x07
//---------------------------------------------------------------------------
MB967 User’s Manual
31
INSTALLATIONS
#define F81866_UNLOCK
0x87
#define F81866_LOCK
0xAA
//--------------------------------------------------------------------------unsigned int Init_F81866(void);
void Set_F81866_LD( unsigned char);
void Set_F81866_Reg( unsigned char, unsigned char);
unsigned char Get_F81866_Reg( unsigned char);
//--------------------------------------------------------------------------#endif //__F81866_H
32
MB967 User’s Manual
BIOS SETUP
BIOS Setup
This chapter describes the different settings available in the AMI BIOS
that comes with the board. The topics covered in this chapter are as
follows:
BIOS Introduction ............................................................................... 34
BIOS Setup .......................................................................................... 34
Advanced Settings ............................................................................... 36
Chipset Settings ................................................................................... 49
Boot Settings........................................................................................ 54
CSM parameters .................................................................................. 55
Security Settings .................................................................................. 56
MB967 User’s Manual
33
BIOS SETUP
BIOS Introduction
The BIOS (Basic Input/Output System) installed in your computer
system’s ROM supports Intel processors. The BIOS provides critical
low-level support for a standard device such as disk drives, serial ports
and parallel ports. It also password protection as well as special support
for detailed fine-tuning of the chipset controlling the entire system.
BIOS Setup
The BIOS provides a Setup utility program for specifying the system
configurations and settings. The BIOS ROM of the system stores the
Setup utility. When you turn on the computer, the BIOS is immediately
activated. Pressing the <Del> key immediately allows you to enter the
Setup utility. If you are a little bit late pressing the <Del> key, POST
(Power On Self Test) will continue with its test routines, thus preventing
you from invoking the Setup. If you still wish to enter Setup, restart the
system by pressing the ”Reset” button or simultaneously pressing the
<Ctrl>, <Alt> and <Delete> keys. You can also restart by turning the
system Off and back On again. The following message will appear on the
screen:
Press <DEL> / <F2> to Enter Setup
In general, you press the arrow keys to highlight items, <Enter> to select,
the <PgUp> and <PgDn> keys to change entries, <F1> for help and
<Esc> to quit.
When you enter the Setup utility, the Main Menu screen will appear on
the screen. The Main Menu allows you to select from various setup
functions and exit choices.
Warning: It is strongly recommended that you avoid making any
changes to the chipset defaults. These defaults have been
carefully chosen by both AMI and your system manufacturer
to provide the absolute maximum performance and
reliability. Changing the defaults could cause the system to
become unstable and crash in some cases.
34
MB967 User’s Manual
BIOS SETUP
Main Settings
Aptio Setup Utility – Copyright © 2011 American Megatrends, Inc.
Main
Advanced
Chipset
Boot
BIOS Information
System Language
System Date
Access Level
Security
Save & Exit
Choose the system default
language
[English]
[Tue 06/19/2012]
Administrator
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
System Language
Choose the system default language.
System Date
Set the Date. Use Tab to switch between Data elements.
System Time
Set the Time. Use Tab to switch between Data elements.
MB967 User’s Manual
35
BIOS SETUP
Advanced Settings
This section allows you to configure and improve your system and allows
you to set up some system features according to your preference.
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
► PCI Subsystem Settings
► ACPI Settings
► Wake up event setting
► Trusted Computing
► CPU Configuration
► SATA Configuration
► Shutdown Temperature Configuration
► AMT Configuration
► Acoustic Management Configuration
► USB Configuration
► F81866 Super IO Configuration
► F81866 H/W Monitor
► Serial Port Console Redirection
► CPU PPM Configuration
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
PCI Subsystem Settings
Aptio Setup Utility
Main
Advanced
Chipset
PCI Bus Driver Version
Boot
Security
Save & Exit
V 2.05.02
→ ← Select
PCI 64bit Resources Handling
Above 4G Decoding
[Disabled]
PCI Common Settings
PCI Latency Timer
VGA Palette Snoop
[32 PCI Bus Clocks]
[Disabled]
PERR# Generation
SERR# Generation
[Disabled]
[Disabled]
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
► PCI Express Settings
Above 4G Decoding
Enables or Disables 64bit capable devices to be decoded in above 4G
address space (only if system supports 64 bit PCI decoding).
36
MB967 User’s Manual
BIOS SETUP
PCI Latency Timer
Value to be programmed into PCI Latency Timer Register.
VGA Palette Snoop
Enables or disables VGA Palette Registers Snooping.
PERR# Generation
Enables or disables PCI device to generate PERR#.
SERR# Generation
Enables or disables PCI device to generate SERR#.
PCI Express Settings
Change PCI Express devices settings.
PCI Express Settings
Aptio Setup Utility
Main
Advanced
Chipset
Boot
PCI Express Device Register Settings
Relaxed Ordering
Extended Tag
[Disabled]
[Disabled]
No Snoop
Maximum Payload
Maximum Read Request
[Enabled]
[Auto]
[Auto]
PCI Express Link Register Settings
ASPM Support
[Disabled]
WARNING: Enabling ASPM may cause some
PCI-E devices to fail
Extended Synch
[Disabled]
Link Training Retry
Link Training Timeout
Unpopulated Links
Security
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
[5]
100
[Keep Link ON]
Relaxed Ordering
Enables or disables PCI Express Device Relaxed Ordering.
Extended Tag
If ENABLED allows device to use 8-bit Tag field as a requester.
No Snoop
Enables or disables PCI Express Device No Snoop option.
MB967 User’s Manual
37
BIOS SETUP
Maximum Payload
Set Maximum Payload of PCI Express Device or allow System BIOS to
select the value.
Maximum Read Request
Set Maximum Read Request Size of PCI Express Device or allow System
BIOS to select the value.
ASPM Support
Set the ASPM Level: Force L0s – Force all links to L0s State:
AUTO – BIOS auto configure : DISABLE – Disables ASPM.
Extended Synch
If ENABLED allows generation of Extended Synchronization patterns.
Link Training Retry
Defines number of Retry Attempts software will take to retrain the link if
previous training attempt was unsuccessful.
Link Training Timeout
Defines number of Microseconds software will wait before polling ‘Link
Training’ bit in Link Status register. Value range from 10 to 1000 uS.
Unpopulated Links
In order to save power, software will disable unpopulated PCI Express
links, if this option set to ‘Disable Link’.
38
MB967 User’s Manual
BIOS SETUP
ACPI Settings
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
ACPI Settings
→ ← Select
Enable Hibernation
ACPI Sleep State
Lock Legacy Resources
S3 Video Repost
[Enabled]
[S1 only (CPU Stop C…]
[Disabled]
[Disabled]
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Enable Hibernation
Enables or Disables System ability to Hibernate (OS/S4 Sleep State).
This option may be not effective with some OS.
ACPI Sleep State
Select ACPI sleep state the system will enter, when the SUSPEND button
is pressed.
Lock Legacy Resources
Enabled or Disabled Lock of Legacy Resources.
S3 Video Repost
Enable or disable S3 Video Repost.
MB967 User’s Manual
39
BIOS SETUP
Wake up event settings
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Wake system with Fixed Time
[Disabled]
Wake on Ring
Wake on PCIE Wake Event
[Disabled]
[Disabled]
Security
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Wake system with Fixed Time
Enables or Disables System wake on alarm event. When enabled, System
will wake on the hr::min:: sec specified.
Wake on PCIE PME Wake Event
The options are Disabled and Enabled.
Trusted Computing
Aptio Setup Utility
Main
Advanced
Chipset
Configuration
Security Device Sup
Boot
Security
[Disabled]
Current TPM Status Information
SUPPORT TUREND OFF
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Security Device Support
Enables or disables BIOS support for security device. O.S. will not show
Security Device. TCG EFI protocol and INT1A interface will not be
available.
40
MB967 User’s Manual
BIOS SETUP
CPU Configuration
This section shows the CPU configuration parameters.
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
CPU Configuration
Intel(R) Xeon(R) CPU E3-1225 V2
CPU Signature
Microcode Patch
CPU Speed
Processor Cores
@
3.20GHz
306a8
c
3200 MHz
4
Intel HT Technology
Intel VT-x Technology
Intel SMX Technology
64-bit
Not Supported
Supported
Supported
Supported
Active Processor Cores
Limit CPUID Maximum
Execute Disable Bit
Intel Virtualization
Hardware Prefetcher
Adjacent Cache Line Prefetch
[All]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
[Enabled]
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Active Processor Cores
Number of cores to enable in each processor package.
Limit CPUID Maximum
Disabled for Windows XP.
Execute Disable Bit
XD can prevent certain classes of malicious buffer overflow attacks when
combined with a supporting OS (Windows Server 2003 SP1, Windows
XP SP2, SuSE Linux 9.2, Re33dHat Enterprise 3 Update 3.)
Intel Virtualization Technology
When enabled, a VMM can utilize the additional hardware capabilities
provided by Vanderpool Technology.
Hardware Prefetcher
To turn on/off the Mid level Cache (L2) streamer Prefetcher.
Adjacent Cache Line Prefetch
To turn on/off prefetching of adjacent cache lines.
MB967 User’s Manual
41
BIOS SETUP
SATA Configuration
SATA Devices Configuration.
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
SATA Controller(s)
SATA Mode Selection
[Enabled]
[IDE]
SATA Port0
Software Preserve
SATA Port1
Software Preserve
SATA Port2
Empty
Unknown
Empty
Unknown
Empty
Software Preserve
SATA Port3
Software Preserve
SATA Port4
Software Preserve
SATA Port5
Software Preserve
Unknown
Empty
Unknown
WDC WD5000BPKT (5
SUPPORTED
Empty
Unknown
SATA Controller(s)
Enable / Disable Serial ATA Controller.
SATA Mode Selection
(1) IDE Mode.
(2) AHCI Mode.
(3) RAID Mode.
42
MB967 User’s Manual
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
BIOS SETUP
Shutdown Temperature Configuration
Aptio Setup Utility
Main
Advanced
Chipset
APCI Shutdown Temperature
Boot
Security
Save & Exit
[Disabled]
ACPI Shutdown Temperature
Set function Disabled or 70/75/80/85/90/95 ℃
AMT Configuration
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
Intel AMT
BIOS Hotkey Pressed
MEBx Selection Screen
Hide Un-Configure ME Confirmation
Un-Configure ME
Amt Wait Timer
[Enabled]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
0
→ ← Select
Activate Remote Assistance Process
USB Configure
PET Progress
AMT CIRA Timeout
Watchdog
OS Timer
BIOS Timer
[Disabled]
[Enabled]
[Enabled]
0
[Disabled]
0
0
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Screen
AMT Configuration
Options are Enabled and Disabled.
Note: iAMT H/W is always enabled. This option just controls the BIOS
extension execution. If enabled, this requires additional firmware in the
SPI device.
Unconfigure ME
Perform AMT/ME unconfigure without password operation.
Amt Wait Timer
Set timer to wait before sending ASF_GET_BOOT_OPTIONS.
MB967 User’s Manual
43
BIOS SETUP
Activate Remote Assistance Process
Trigger CIRA boot.
PET Progress
User can Enable/Disable PET Events progress to receive PET events or
not.
Watchdog Timer
Enable/Disable Watchdog Timer.
Acoustic Management Configuration
Aptio Setup Utility
Main
Advanced
Chipset
Acoustic Management Configuration
Automatic Acoustic Management
Boot
Security
[Disabled]
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
44
MB967 User’s Manual
BIOS SETUP
USB Configuration
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
USB Configuration
USB Devices:
1 Keyboard, 2 Hubs
Legacy USB Support
USB3.0 Support
XHCI Hand-off
EHCI Hand-off
Port 60/64 Emulation
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
USB hardware delays and time-outs:
USB Transfer time-out
Device reset tine-out
Device power-up delay
[20 sec]
[20 sec]
[Auto]
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Legacy USB Support
Enables Legacy USB support.
AUTO option disables legacy support if no USB devices are connected.
DISABLE option will keep USB devices available only for EFI
applications.
USB3.0 Support
Enable/Disable USB3.0 (XHCI) Controller support.
XHCI Hand-off
This is a workaround for OSes without XHCI hand-off support. The
XHCI ownership change should be claimed by XHCI driver.
EHCI Hand-off
Enabled/Disabled. This is a workaround for OSes without EHCI hand-off
support. The EHCI ownership change should be claimed by EHCI driver.
Port 64/60 Emulation
Enables I/O port 60h/64h emulation support. This should be enabled for
the complete USB keyboard legacy support for non-USB aware OSes.
USB Transfer time-out
The time-out value for Control, Bulk, and Interrupt transfers.
MB967 User’s Manual
45
BIOS SETUP
Device reset tine-out
USB mass Storage device start Unit command time-out.
Device power-up delay
Maximum time the device will take before it properly reports itself to the
Host Controller. ‘Auto’ uses default value: for a Root port it is 100ms, for
a Hub port the delay is taken from Hub descriptor.
F81866 Super IO Configuration
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
Super IO Configuration
→ ← Select
F81866 Super IO Chip
► Serial Port 0 Configuration
► Serial Port 1 Configuration
Power Failure
KB/MS Power On
LAN5,6 Bypass Function
LAN7,8 Bypass Function
F81866
[Always off]
[None]
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
[Bypass]
[Bypass]
Serial Port Configuration
Set Parameters of Serial Ports. User can Enable/Disable the serial port
and Select an optimal settings for the Super IO Device.
LAN5, 6 Bypass Function
LAN5, 6 Bypass Function Setting [Bypass] or [Normal]
LAN7, 8 Bypass Function
LAN7, 8 Bypass Function Setting [Bypass] or [Normal]
46
MB967 User’s Manual
BIOS SETUP
F81866 H/W Monitor
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
PC Health Status
CPU smart fan control
Fan1 smart fan control
Fan2 smart fan control
CPU temperature
SYS temperature
CPU Fan Speed
FAN1 Speed
FAN2 Speed
[60 C]
[60 C]
[60 C]
+41 C
+35 C
7315 RPM
7308 RPM
7313 RPM
Vcore
+5V
+12V
1.5V
+3.3V
+0.928 V
+5.213 V
+12.144 V
+1.544 V
+3.360 V
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Temperatures/Voltages
These fields are the parameters of the hardware monitoring function
feature of the motherboard. The values are read-only values as monitored
by the system and show the PC health status.
CPU/Fan1/Fan2 Smart Fan Control
This field enables or disables the smart fan feature. At a certain
temperature, the fan starts turning. Once the temperature drops to a
certain level, it stops turning again.
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BIOS SETUP
Serial Port Console Redirection
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
COM0
Console Redirection
► Console Redirection Settings
COM1 (Pci Bus0, Dev0, Func0)
Console Redirection Port Is Disabled
[Enabled]
→ ← Select
[Enabled]
(Disabled)
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Console Redirection Settings
Aptio Setup Utility
Main
Advanced
Chipset
Boot
COM0
Console Redirection Settings
Terminal Type
Bits per second
[VT100+]
[115200]
Data Bits
Parity
Stop Bits
Flow Control
VT-UTF8 Combo Key Sup
Recorder Mode
Resolution 100x31
Legacy OS Redirection
Putty KeyPad
[8]
[None]
[1]
[None]
[Enabled]
[Disabled]
[Disabled]
[80x24]
[VT100]
48
Security
Save & Exit
Emulation: ANSI:
Extended ASCII char
Set. VT100: ASCII char
Set. VT100+: Extends
VT100 to support color,
Function keys, etc.
VT-UTF8: Uses UTF8
Encoding to map Unicode
Chars onto 1 or more
-------------------------------------------
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
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BIOS SETUP
Chipset Settings
This section allows you to configure and improve your system and allows
you to set up some system features according to your preference.
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
PCH Parameters
► PCH-IO Configuration
► System Agent (SA) Configuration
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
PCH-IO Configuration
This section allows you to configure the North Bridge Chipset.
Aptio Setup Utility
Main
Advanced
Chipset
Intel PCH RC Version
Intel PCH SKU Name
Intel PCH Rev ID
Boot
1.1.0.0
C216
O4/C1
Security
Save & Exit
PCI Express
Configuration settings
► PCI Express Configuration
► USB Configuration
PCH LAN Controller
Wake on LAN
[Enabled]
[Disabled]
High Precision Event Timer Configuration
High Precision Timer
[Enabled]
SLP_S4 Assertion Width
[4-5 Seconds]
→ ←
Select Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
PCH LAN Controller
Enable or disable onboard NIC.
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BIOS SETUP
Wake on LAN
Enable or disable integrated LAN to wake the system. (The Wake On
LAN cannot be disabled if ME is on at Sx state.)
SLP_S4 Assertion Width
Select a minimum assertion width of the SLP_S4# signal.
PCI Express Configuration
Main
Advanced
Chipset
Boot
Security
Save & Exit
PCI Express Configuration
PCI Express Clock Gating
DMI Link ASPM Control
DMI Link Extended Synch Control
PCIe-USB Glitch W/A
Subtractive Decode
[Enabled]
[Enabled]
[Disabled]
[Disabled]
[Disabled]
PCIE Port 1 is assign
► PCI Express Root Port 2
► PCI Express Root Port 3
► PCI Express Root Port 4
► PCI Express Root Port 5
► PCI Express Root Port 6
→ ←
Select Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
► PCI Express Root Port 7
► PCI Express Root Port 8
PCI Express Clock Gating
Enable or disable PCI Express Clock Gating for each root port.
DMI Link ASPM Control
The control of Active State Power Management on both NB side and SB
side of the DMI link.
PCIe-USB Glitch W/A
PCIe-USB Glitch W/A for bad USB device(s) connected behind
PCIE/PEG port.
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BIOS SETUP
USB Configuration
Main
Advanced
Chipset
Boot
Security
Save & Exit
USB Configuration
XHCI Pre-Boot Driver
xHCI Mode
HS Port #1 Switchable
HS Port #2 Switchable
HS Port #3 Switchable
HS Port #4 Switchable
xHCI Streams
[Disabled]
[Auto]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
EHCI1
[Enabled]
EHCI2
[Enabled]
USB Ports Per-Port Disable Control
[Disabled]
→ ←
Select Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
HS Port #1/2/3/4 Switchable
Allows for HS port switching between xHCI and EHCI. If disabled, port
is routed to EHCI. If HS port is routed to xHCI, the corresponding SS
port is enabled.
xHCI Streams
Enable or disable xHCI Maximum Primary Stream Array Size.
EHCI1/2
Control the USAB EHCI (USB 2.0) functions. One EHCI controller must
always be enabled.
USB Ports Per-Port Disable Control
Control each of the USB ports (0~13) disabling.
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BIOS SETUP
System Agent (SA) Configuration
Aptio Setup Utility
Main
Advanced
Chipset
Boot
System Agent Bridge Name
System Agent RC Version
VT-d Capability
IvyBridge
1.1.0.0
Supported
VT-d
CHAP Device (B0:D7:F0)
Thermal Device (B0:D4:F0)
Enable NB CRID
BDAT ACPI Table Support
C-State Pre-Wake
[Enabled]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
[Enabled]
Security
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
► Graphics Configuration
► Memory Configuration
VT-d
Check to enable VT-d function on MCH.
Graphics Configuration
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Graphics Configuration
IGFX VBIOS Version
IGfx Frequency
2132
350 MHz
Primary Display
Primary PEG
Internal Graphics
GTT Size
Aperture Size
DVMT Pre-Allocated
DVMT Total Gfx Mode
Gfx Low Power Mode
[Auto]
[Auto]
[Auto]
[2MB]
[256MB]
[64M]
[256M]
[Disabled]
Security
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Primary Display
Select which of IGFX/PEG/PCI graphics device should be primary
display or select SG for switchable Gfx.
Internal Graphics
Keep IGD enabled based on the setup options.
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DVMT Pre-Allocated
Select DVMT 5.0 Pre-Allocated (Fixed) graphics memory size used by
the internal graphics device.
DVMT Total Gfx Mem
Select DVMT 5.0 total graphics memory size used by the internal
graphics device.
Gfx Low Power Mode
This option is applicable for SFF only.
Memory Configuration
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
Memory Information
Memory Frequency
Total Memory
DIMM#0
DIMM#1
DIMM#2
1333 MHz
32768 MB (DDR3)
8192 MB (DDR3)
8192 MB (DDR3)
8192 MB (DDR3)
DIMM#3
CAS Latency (tCL)
Minimum delay time
CAS to RAS (tRCDmin)
Row Precharge (tRPmin)
Active to Precharge (tRASmin)
8192 MB (DDR3)
9
9
9
24
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
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BIOS SETUP
Boot Settings
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Boot Configuration
Setup Prompt Timeout
Bootup NumLock State
1
[On]
Quiet Boot
Fast Boot
[Disabled]
[Disabled]
CSM16 Module Version
07.68
GateA20 Active
Option ROM Messages
INT19 Trap Response
[Upon Request]
[Force BIOS]
[Immediate]
Boot Option Priorities
Boot Option #1
[SATA PM: WDC W
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Hard Drive BBS Priorities
► CSM parameters
Setup Prompt Timeout
Number of seconds to wait for setup activation key.
65535(0xFFFF) means indefinite waiting.
Bootup NumLock State
Select the keyboard NumLock state.
Quiet Boot
Enables/Disables Quiet Boot option.
Fast Boot
Enables/Disables boot with initialization of a minimal set of devices
required to launch active boot option. Has no effect for BBS boot
options.
GateA20 Active
UPON REQUEST – GA20 can be disabled using BIOS services.
ALWAYS – do not allow disabling GA20; this option is useful when any
RT code is executed above 1MB.
Option ROM Messages
Set display mode for Option ROM. Options are Force BIOS and Keep
Current.
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INT19 Trap Response
Enable: Allows Option ROMs to trap Int 19.
Boot Option Priorities
Sets the system boot order.
CSM parameters
This section allows you to configure the boot settings.
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Launch CSM
Boot option filter
Launch PXE OpROM policy
Launch Storage OpROM policy
Launch Video OpROM policy
[Always]
[UEFI and Legacy]
[Do not launch]
[Legacy only]
[Legacy only]
Other PCI device ROM priority
[UEFI OpROM]
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Boot option filter
This option controls what devices system can boot to.
Launch PXE OpROM policy
Controls the execution of UEFI and Legacy PXE OpROM.
Launch Storatge OpROM policy
Controls the execution of UEFI and Legacy Storage OpROM.
Launch Video OpROM policy
Controls the execution of UEFI and Legacy Video OpROM.
Other PCI device ROM priority
For PCI devices other than Network, Mass storage or Video defines
which OpROM to launch.
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BIOS SETUP
Security Settings
This section allows you to configure and improve your system and allows
you to set up some system features according to your preference.
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save & Exit
Password Description
If ONLY the Administrator’s password is set, then
this only limit access to Setup and is only asked
for when entering Setup.
If ONLY the User’s password is set, then this is a
power on password and must be entered to boot
or enter Setup. In Setup the User will have
Administrator rights
The password length must be
in the following range:
Minimum length
3
Maximum length
20
Administrator Password
User Password
Administrator Password
Set Setup Administrator Password.
User Password
Set User Password.
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MB967 User’s Manual
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
BIOS SETUP
Save & Exit Settings
Aptio Setup Utility
Main
Advanced
Chipset
Boot
Security
Save Changes and Exit
Discard Changes and Exit
Save Changes and Reset
Discard Changes and Reset
Save & Exit
→ ← Select
Screen
↑↓ Select Item
Enter: Select
+- Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save ESC: Exit
Save Options
Save Changes
Discard Changes
Restore Defaults
Save as User Defaults
Restore User Defaults
SATA PM: WDC WD5000BPKT-0
Save Changes and Exit
Exit system setup after saving the changes.
Discard Changes and Exit
Exit system setup without saving any changes.
Save Changes and Reset
Reset the system after saving the changes.
Discard Changes and Reset
Reset system setup without saving any changes.
Save Changes
Save Changes done so far to any of the setup options.
Discard Changes
Discard Changes done so far to any of the setup options.
Restore Defaults
Restore/Load Defaults values for all the setup options.
Save as User Defaults
Save the changes done so far as User Defaults.
Restore User Defaults
Restore the User Defaults to all the setup options.
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BIOS SETUP
This page is intentionally left blank.
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DRIVERS INSTALLATION
Drivers Installation
This section describes the installation procedures for software and
drivers. The software and drivers are included with the motherboard. If
you find the items missing, please contact the vendor where you made the
purchase. The contents of this section include the following:
Intel Chipset Software Installation Utility ........................................... 60
VGA Drivers Installation ..................................................................... 63
LAN Drivers Installation ..................................................................... 66
Intel® Management Engine Interface .................................................. 70
Intel® USB 3.0 Drivers ....................................................................... 73
IMPORTANT NOTE:
After installing your Windows operating system, you must install first the
Intel Chipset Software Installation Utility before proceeding with the
drivers installation.
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DRIVERS INSTALLATION
Intel Chipset Software Installation Utility
The Intel Chipset Drivers should be installed first before the software
drivers to enable Plug & Play INF support for Intel chipset components.
Follow the instructions below to complete the installation.
1. Insert the CD that comes with the board. Click Intel and then Intel(R)
7 Series Chipset Drivers.
2. Click Intel(R) Chipset Software Installation Utility.
[
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3. When the Welcome screen to the Intel® Chipset Device Software
appears, click Next to continue.
4. Click Yes to accept the software license agreement and proceed with
the installation process.
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DRIVERS INSTALLATION
5. On the Readme File Information screen, click Next to continue the
installation.
6. The Setup process is now complete. Click Finish to restart the
computer and for changes to take effect.
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VGA Drivers Installation
NOTE: Before installing the Intel(R) C216 Chipset Family Graphics
Driver, the Microsoft .NET Framework 3.5 SPI should be first
installed.
To install the VGA drivers, follow the steps below.
1. Insert the CD that comes with the board. Click Intel and then Intel(R)
Q7 Series Chipset Drivers.
2. Click Intel(R) C216 Chipset Family Graphics Driver.
[
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DRIVERS INSTALLATION
3. When the Welcome screen appears, click Next to continue.
4. Click Yes to to agree with the license agreement and continue the
installation.
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5. On the Readme File Information screen, click Next to continue the
installation of the Intel® Graphics Media Accelerator Driver.
6. On Setup Progress screen, click Next to continue.
7. Setup complete. Click Finish to restart the computer and for changes
to take effect.
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DRIVERS INSTALLATION
LAN Drivers Installation
1. Insert the CD that comes with the board. Click Intel and then Intel(R)
Q7 Series Chipset Drivers.
2. Click Intel(R) PRO LAN Network Driver.
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3. Click Install Drivers and Software.
4. When the Welcome screen appears, click Next.
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DRIVERS INSTALLATION
5. Click Next to to agree with the license agreement.
6. Click the checkbox for Drivers in the Setup Options screen to select it
and click Next to continue.
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7. The wizard is ready to begin installation. Click Install to begin the
installation.
8. When InstallShield Wizard is complete, click Finish.
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DRIVERS INSTALLATION
Intel® Management Engine Interface
Follow the steps below to install the Intel Management Engine.
1. Insert the CD that comes with the board. Click Intel and then Intel(R)
AMT 8.0 Drivers.
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2. When the Welcome screen to the InstallShield Wizard for Intel®
Management Engine Components, click the checkbox for Install Intel®
Control Center & click Next.
3. Click Yes to to agree with the license agreement.
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DRIVERS INSTALLATION
4. When the Setup Progress screen appears, click Next. Then, click
Finish when the setup progress has been successfully installed.
[
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Intel® USB 3.0 Drivers
1. Insert the CD that comes with the board. Click Intel and then Intel(R)
C216 Series Chipset Drivers.
2. Click Intel(R) USB 3.0 Drivers.
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DRIVERS INSTALLATION
3. When the Welcome screen to the InstallShield Wizard for Intel® USB
3.0 eXtensible Host Controller Driver, click Next.
4. Click Yes to to agree with the license agreement and continue the
installation.
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5. On the Readme File Information screen, click Next to continue the
installation of the Intel® USB 3.0 eXtensible Host Controller Driver.
6. Setup complete. Click Finish to restart the computer and for changes
to take effect.
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APPENDIX
Appendix
A. I/O Port Address Map
Each peripheral device in the system is assigned a set of I/O port
addresses which also becomes the identity of the device. The following
table lists the I/O port addresses used.
Address
000h - 01Fh
020h - 03Fh
040h - 05Fh
060h - 06Fh
070h - 07Fh
080h - 09Fh
0A0h - 0BFh
0C0h - 0DFh
0F0h
0F1h
1F0h - 1F7h
2F8h - 2FFh
2B0h- 2DFh
360h - 36Fh
3F8h - 3FFh
Device Description
DMA Controller #1
Interrupt Controller #1
Timer
Keyboard Controller
Real Time Clock, NMI
DMA Page Register
Interrupt Controller #2
DMA Controller #2
Clear Math Coprocessor Busy Signal
Reset Math Coprocessor
IDE Interface
Serial Port #2(COM2)
Graphics adapter Controller
Network Ports
Serial Port #1(COM1)
B. Interrupt Request Lines (IRQ)
Peripheral devices use interrupt request lines to notify CPU for the
service required. The following table shows the IRQ used by the devices
on board.
Level
IRQ0
IRQ1
IRQ3
IRQ4
IRQ8
IRQ14
IRQ15
76
Function
System Timer Output
Keyboard
Serial Port #2
Serial Port #1
Real Time Clock
Primary IDE
Secondary IDE
MB967 User’s Manual
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