UPD78064B(A) Data Sheet
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78064B(A)
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78064B(A) is an 8-bit single-chip microcontroller belonging to the µPD78064B subseries of the 78K/0
series. A stricter quality assurance program is applied to this device, which is classified as special grade, compared
to the µPD78064B, which is classified as standard grade.
The EMI (Electro Magnetic Interference) noise generated inside the µPD78064B(A) is reduced compared to the
µPD78064 subseries.
A one-time PROM version that can operate in the same power supply voltage as the mask ROM version, and various
development tools are available for this device.
For detailed descriptions of functions, refer to the following user’s manuals. Be sure to read them before
starting design.
µPD78064B Subseries User’s Manual
: U10785E
78K/0 Series User’s Manual Instruction : U12326E
FEATURES
• I/O ports : 57 (including segment signal output alter-
• Internal high-capacity ROM and RAM
• Internal ROM
nate-function pin)
: 32 Kbytes
• LCD controller/driver
• Internal high-speed RAM : 1024 bytes
• LCD display RAM
: 40 × 4 bits
Power supply voltage : VDD = 2.0 to 6.0 V
(static display mode)
• Three packages
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
: VDD = 2.5 to 6.0 V (1/3 bias)
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
: VDD = 2.7 to 6.0 V (1/2 bias)
• 8-bit resolution A/D converter : 8 channels
• Minimum instruction execution time can be changed
from high-speed (0.4 µs) to ultra-low-speed (122 µs)
• Serial interface : 2 channels
• Timer : 5 channels
• Power supply voltage : VDD = 2.0 to 6.0 V
APPLICATIONS
Control devices of automotive electrical equipment, gas detector circuit-breakers, safety devices, sphygmomanometer, etc.
The information in this document is subject to change without notice.
Document No. U11597EJ2V0DS00 (2nd edition)
Date Published July 1997 N
Printed in Japan
The mark
shows major revised points.
©
1996
µPD78064B(A)
ORDERING INFORMATION
Part Number
Package
µPD78064BGC(A)-×××-7EA
µPD78064BGC(A)-×××-8EU
Note
µPD78064BGF(A)-×××-3BA
Quality Grade
100-pin plastic QFP (fine pitch) (14 × 14 mm)
Special
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Special
100-pin plastic QFP (14 × 20 mm)
Special
Note Under development
Caution The µPD78064BGC(A) comes in two types of packages (refer to 11. PACKAGE DRAWINGS). For
packages which can be supplied, please consult an NEC sales representative.
Remark ××× indicates ROM code suffix.
Please refer to the Quality Grades on NEC Semiconductor Devices (C11531E) published by NEC Corporation
to know the specification of quality grade on the devices and its recommended applications.
Difference between µPD78064B(A) and µPD78064B
Part number
Item
Quality grade
2
µPD78064B(A)
Special
µPD78064B
Standard
µPD78064B(A)
78K/0 Series Development
The following shows the 78K/0 series products development. Subseries names are shown inside frames.
Mass-produced products
Products under development
The subseries whose names end with Y supports
the I2C bus specifications.
Controller
EMI noise reduced version of µPD78078
100-pin
µPD78075B
µPD78075BY
100-pin
µPD78078
µPD78078Y
Added timers to µPD78054 and enhanced external interface
100-pin
µPD78070A
µPD78070AY
ROM-less version of µPD78078
Enhanced serial I/O of µPD78078 and functions are defined.
µPD780058
µPD780018AY
µPD780058YNote
80-pin
µPD78058F
µPD78058FY
80-pin
µPD78054
µPD78054Y
Added UART and D/A to µPD78014 and enhanced I/Os
64-pin
µPD780034
µPD780034Y
Enhanced A/D of µPD780024
64-pin
µPD780024
µPD780024Y
Enhanced serial I/O of µPD78018F, EMI noise reduced version
64-pin
µPD78014H
64-pin
µPD78018F
µPD78018FY
64-pin
µPD78014
µPD78014Y
64-pin
µPD780001
64-pin
µPD78002
42-/44-pin
µPD78083
100-pin
80-pin
Enhanced serial I/O of µPD78054, EMI noise reduced version
EMI noise reduced version of µPD78054
EMI noise reduced version of µPD78018F
Low-voltage (1.8 V) version of µPD78014 and enhanced ROM/RAM size options
Added A/D and 16-bit timer to µPD78002
Added A/D to µPD78002
µPD78002Y
Basic subseries for control applications
Equipped with UART and operates at low-voltage (1.8 V)
Inverter controller
64-pin
µPD780964
Enhanced A/D of µPD780924
64-pin
µPD780924
Equipped with inverter control circuit and UART, EMI noise reduced version
78K/0
Series
FIPTM driver
100-pin
µPD780208
Enhanced I/O and FIP C/D of µPD78044F, 53 display outputs
100-pin
µPD780228
Enhanced I/O and FIP C/D of µPD78044H, 48 display outputs
80-pin
µPD78044H
Added N-ch open-drain I/O to µPD78044F, 34 display outputs
80-pin
µPD78044F
Basic subseries for driving FIPs, 34 display outputs
LCD driver
100-pin
µPD780308
100-pin
µPD78064B
100-pin
µPD78064
µPD780308Y
Enhanced SIO of µPD78064, expanded ROM and RAM
EMI noise reduced version of µPD78064
µPD78064Y
Basic subseries for driving LCDs, equipped with UART
IEBusTM supported
80-pin
µPD78098B
80-pin
µPD78098
EMI noise reduced version of µPD78098
Added IEBus controller to µPD78054
Meter controller
µPD780973
80-pin
Equipped with controller/driver for driving automobile meters
LV
64-pin
µPD78P0914
Equipped with PWM output, LV digital code decoder, and Hsync counter
Note Under planning
3
µPD78064B(A)
The following table shows the differences among subseries functions.
Function
Subseries name
Controller
ROM
capacity
Timer
8-bit 10-bit 8-bit
Serial interface
8-bit 16-bit Watch WDT A/D A/D D/A
µPD78075B
32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch
µPD78078
48K to 60K
µPD78070A
—
24K to 60K 2 ch
µPD78058F
48K to 60K
µPD78054
16K to 60K
µPD780034
8K to 32K
1.8 V
61
2.7 V
2 ch 3 ch (Time division 68
UART: 1 ch)
1.8 V
3 ch (UART: 1 ch) 69
2.7 V
—
8 ch
8 ch
—
—
µPD78014H
8K to 60K
µPD78014
8K to 32K
µPD780001
8K
µPD78002
8K to 16K
µPD780964
FIP driver
—
1 ch
53
1 ch
39
—
53
Available
3 ch Note
8 ch
—
8 ch
µPD780924
8 ch
—
µPD780208
32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch
—
µPD780228
48K to 60K 3 ch
—
—
1 ch
1 ch (UART: 1 ch) 33
1.8 V
—
—
2 ch (UART: 2 ch) 47
2.7 V
Available
—
2 ch
74
2.7 V
—
1 ch
72
4.5 V
68
2.7 V
3 ch (Time division 57
UART: 1 ch)
2.0 V
—
2.7 V
Available
—
µPD78044H 32K to 48K 2 ch 1 ch 1 ch
µPD78044F
16K to 40K
µPD780308
48K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch
µPD78064B
32K
µPD78064
16K to 32K
IEBus
supported
µPD78098B
40K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch
µPD78098
32K to 60K
Meter
controller
µPD780973
24K to 32K 3 ch 1 ch 1 ch 1 ch 5 ch
LV
µPD78P0914 32K
LCD
driver
Note 10 bits timer: 1 channel
4
1.8 V
2 ch
—
—
8K to 32K
3 ch (UART: 1 ch, Time 51
division 3-wire: 1 ch)
2.7 V
—
µPD78083
Inverter
controller
Available
2.0 V
µPD780024
µPD78018F
VDD MIN. External
value expansion
2 ch 3 ch (UART: 1 ch) 88
—
µPD780058
I/O
2 ch
—
—
2 ch (UART: 1 ch)
6 ch
—
—
1 ch 8 ch
—
2 ch 3 ch (UART: 1 ch) 69
—
—
2 ch (UART: 1 ch) 56
4.5 V
—
—
—
2 ch
4.5 V
Available
54
µPD78064B(A)
FUNCTION OVERVIEW
Item
Internal
memory
Function
ROM
32 Kbytes
High-speed RAM
1024 bytes
LCD display RAM
40 × 4 bits
General registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation)
When main system clock
instruction selected
execution When subsystem clock
time
selected
Instruction set
122 µs (@ 32.768-kHz operation)
•
•
•
•
I/O ports
(including segment signal output pins)
16-bit operation
Multiply/divide (8 bits × 8 bits,16 bits/8 bits)
Bit manipulate (set, reset, test, boolean operation)
BCD adjust, etc.
Total
• CMOS input
• CMOS I/O
: 57
: 02
: 55
A/D converter
• 8-bit resolution × 8 channels
LCD controller/driver
• Segment signal output
• Common signal output
• Bias
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel
• 3-wire serial I/O/UART mode selectable
: 1 channel
Timer
•
•
•
•
Timer output
3 (14-bit PWM output capability : 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
5.0 MHz (@ 5.0-MHz operation with main system clock)
32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0-MHz operation with main system clock)
Vectored
interrupt
source
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
Maskable
Internal : 12, external : 6
Non-maskable
Internal : 1
Software
: Maximum 40
: Maximum 4
: 1/2 or 1/3 switchable
:
:
:
:
1
2
1
1
channel
channels
channel
channel
1
Test input
Internal : 1, external: 1
Supply voltage
VDD = 2.0 to 6.0 V
Package
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)Note
• 100-pin plastic QFP (14 × 20 mm)
Note Under development
5
µPD78064B(A)
CONTENTS
1.
PIN CONFIGURATION (Top View) ................................................................................................... 7
2.
BLOCK DIAGRAM ........................................................................................................................... 10
3.
PIN FUNCTIONS .............................................................................................................................. 11
3.1
Port Pins ...................................................................................................................................................11
3.2
Non-port Pins ..........................................................................................................................................13
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ................................................... 14
4.
MEMORY SPACE ............................................................................................................................. 18
5.
PERIPHERAL HARDWARE FUNCTION FEATURE ..................................................................... 19
6.
5.1
Port ............................................................................................................................................................19
5.2
Clock Generator ......................................................................................................................................20
5.3
Timer/Event Counter ...............................................................................................................................20
5.4
Clock Output Control Circuit.................................................................................................................23
5.5
Buzzer Output Control Circuit .............................................................................................................. 23
5.6
A/D Converter ..........................................................................................................................................24
5.7
Serial Interface ........................................................................................................................................25
5.8
LCD Controller/Driver .............................................................................................................................27
INTERRUPT FUNCTIONS AND TEST FUNCTIONS ..................................................................... 28
6.1
Interrupt Functions .................................................................................................................................28
6.2
Test Functions ......................................................................................................................................... 32
7.
STANDBY FUNCTION ..................................................................................................................... 33
8.
RESET FUNCTION ........................................................................................................................... 33
9.
INSTRUCTION SET .......................................................................................................................... 34
10. ELECTRICAL SPECIFICATIONS ................................................................................................... 36
11. PACKAGE DRAWINGS ................................................................................................................... 56
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 59
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 60
APPENDIX B. RELATED DOCUMENTS ............................................................................................... 62
6
µPD78064B(A)
1. PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
µPD78064BGC(A)-×××-7EA
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
AVREF
P100
9
10
P101
VSS
P102
11
12
13
P103
P30/TO0
14
15
P31/TO1
P32/TO2
16
17
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
18
19
20
21
P72/SCK2/ASCK
X1
X2
IC
XT1/P07
VDD
XT2
P71/SO2/TXD
71
P70/SI2/RXD
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P80/S39
70
69
68
P81/S38
P82/S37
P83/S36
67
66
65
P84/S35
P85/S34
64
63
62
61
60
59
58
57
56
55
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
S20
S19
S18
S13
S14
S15
S16
S17
54
22
53
23
52
24
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
COM3
BIAS
VLC0
COM0
COM1
COM2
P113
P112
P111
P110
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1/TI01
P00/INTP0/TI00
RESET
7
8
S6
S7
S8
S9
S10
S11
S12
P17/ANI7
AVDD
5
6
S3
S4
S5
P14/ANI4
P15/ANI5
P16/ANI6
S0
S1
S2
P12/ANI2
P13/ANI3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
2
73
3
72
4
VLC1
VLC2
VSS
P11/ANI1
AVSS
P117
P116
P115
P114
P10/ANI0
µPD78064BGC(A)-×××-8EUNote
Note Under development
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS.
2. The AVDD pin functions as both an A/D converter power supply and a port power supply. When
the µPD78064B(A) is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVDD pin to another power supply which has the same
potential as VDD.
3. The AVSS pin functions as both an A/D converter ground and a port ground. When the
µPD78064B(A) is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVSS pin to another ground line than VSS.
7
µPD78064B(A)
• 100-pin plastic QFP (14 × 20 mm)
S22
S21
S23
7
8
VDD
XT1/P07
9
10
XT2
RESET
P00/INTP0/TI00
11
12
13
P01/INTP1/TI01
P02/INTP2
14
15
P03/INTP3
P04/INTP4
16
17
P05/INTP5
P110
P111
P112
P113
18
19
20
21
22
P114
P115
P116
P117
AVSS
P10/ANI0
23
24
25
26
27
28
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
VSS
VLC2
VLC1
VLC0
BIAS
COM3
COM2
COM1
COM0
P37
53
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P13/ANI3
P14/ANI4
P15/ANI5
P11/ANI1
P12/ANI2
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
75
74
73
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
X2
X1
76
5
6
VSS
P102
P103
P71/SO2/TXD
P72/SCK2/ASCK
IC
AVREF
P100
P101
P27/SCK0
P70/SI2/RXD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
2
78
3
77
4
P16/ANI6
P17/ANI7
AVDD
P26/SO0/SB1
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P25/SI0/SB0
µPD78064BGF(A)-×××-3BA
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS.
2. The AVDD pin functions as both an A/D converter power supply and a port power supply. When
the µPD78064B(A) is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVDD pin to another power supply which has the same
potential as VDD.
3. The AVSS pin functions as both an A/D converter ground and a port ground. When the
µPD78064B(A) is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVSS pin to another ground line than VSS.
8
µPD78064B(A)
ANI0 to ANI7
: Analog Input
P110 to P117
: Port11
ASCK
: Asynchronous Serial Clock
PCL
: Programmable Clock
AVDD
: Analog Power Supply
RESET
: Reset
AVREF
: Analog Reference Voltage
R XD
: Receive Data
AVSS
: Analog Ground
S0 to S39
: Segment Output
BIAS
: LCD Power Supply Bias Control
SB0, SB1
: Serial Bus
BUZ
: Buzzer Clock
SI0, SI2
: Serial Input
COM0 to COM3 : Common Output
SO0, SO2
: Serial Output
IC
SCK0, SCK2
: Serial Clock
INTP0 to INTP5 : Interrupt from Peripherals
TI00, TI01
: Timer Input
P00 to P05, P07 : Port0
TI1, TI2
: Timer Input
P10 to P17
: Port1
TO0 to TO2
: Timer Output
P25 to P27
: Port2
T XD
: Transmit Data
P30 to P37
: Port3
VDD
: Power Supply
P70 to P72
: Port7
VLC0 to VLC2
: LCD Power Supply
P80 to P87
: Port8
VSS
: Ground
P90 to P97
: Port9
X1, X2
: Crystal (Main System Clock)
P100 to P103
: Port10
XT1, XT2
: Crystal (Subsystem Clock)
: Internally Connected
9
µPD78064B(A)
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
P00
16-bit TIMER/
EVENT COUNTER
PORT0
P01-P05
P07
8-bit TIMER/
EVENT COUNTER 1
PORT1
P10-P17
PORT2
P25-P27
PORT3
P30-P37
PORT7
P70-P72
PORT8
P80-P87
PORT9
P90-P97
PORT10
P100-P103
PORT11
P110-P117
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SERIAL
INTERFACE 0
78K/0
CPU CORE
ROM
SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72
SERIAL
INTERFACE 2
S0-S23
ANI0/P10ANI7/P17
A/D CONVERTER
LCD
CONTROLLER/
DRIVER
AV REF
INTP0/P00INTP5/P05
BUZ/P36
S24/P97S31/P90
RAM
INTERRUPT
CONTROL
S32/P87S39/P80
COM0-COM3
VLC0-VLC2
BIAS
fLCD
BUZZER OUTPUT
RESET
X1
PCL/P35
CLOCK OUTPUT
CONTROL
SYSTEM
CONTROL
VDD
VSS AV DD AV SS IC
X2
XT1/P07
XT2
10
µPD78064B(A)
3. PIN FUNCTIONS
3.1
Port Pins (1/2)
Pin Name
I/O
P00
Input
P01
Input/
output
P02
P03
Port 0
7-bit I/O port.
Function
After Reset
Alternate
function
Input only.
Input
INTP0/TI00
Input/output can be specified bit-wise.
When used as an input port, an on-chip
pull-up resistor can be used by
software.
Input
INTP1/TI01
INTP2
INTP3
P04
INTP4
P05
INTP5
P07Note 1
Input
Input only.
Input
XT1
P10 to P17
Input/
output
Port 1
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.Note 2
Input
ANI0 to ANI7
P25
Input/
output
Port 2
3-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.
Input
SI0/SB0
Port 3
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.
Input
P26
P27
P30
P31
Input/
output
P32
P33
SO0/SB1
SCK0
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P70
P71
P72
Input/
output
Port 7
3-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.
Input
SI2/RXD
SO2/TXD
SCK2/ASCK
Notes 1. When using the P07/XT1 pins as an input port, set (1) bit 6 (FRC) of the processor clock control register
(PCC). (the on-chip feedback resistor of the subsystem clock oscillator should not be used.)
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, port 1 is set to the input
mode. However, the on-chip pull-up resistor is automatically disabled.
11
µPD78064B(A)
3.1
Port Pins (2/2)
Pin Name
P80 to P87
I/O
Function
After Reset
Alternate
function
Input
S39 to S32
Input/
Port 8
output
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.
Input/output port/segment signal output function can be specified
in 2-bit unit by the LCD display control register (LCDC).
P90 to P97
Input/
output
Port 9
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.
Input/output port/segment signal output function can be specified
in 2-bit unit by the LCD display control register (LCDC).
Input
S31 to S24
P100 to P103
Input/
output
Port 10
4-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.
LEDs can be driven directly.
Input
—
P110 to P117
Input/
output
Port 11
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be
used by software.
Falling edge detection capability.
Input
—
Caution For pins which also function as port pins, do not perform the following operations during A/D
conversion. If these operations are performed, the total error ratings cannot be kept (except for LCD
segment output alternate-function pin).
(1) Rewriting the output latch while the pin is used as a port pin.
(2) Changing the output level of the pin used as an output pin, even if it is not used as a port pin.
12
µPD78064B(A)
3.2
Non-port Pins (1/2)
Pin Name
INTP0
Function
After Reset
Alternate
function
External interrupt request input by which the effective edge (rising
edge, falling edge, or both rising edge and falling edge) can be
specified.
Input
P00/TI00
I/O
Input
INTP1
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
P05
SI0
Input
Serial interface serial data input.
Input
SI2
SO0
P25/SB0
P70/RXD
Output
Serial interface serial data output.
Input
SO2
P26/SB1
P71/TXD
Input/
output
Serial interface serial data input/output.
Input/
output
Serial interface serial clock input/output.
RxD
Input
Asynchronous serial interface serial data input.
Input
P70/SI2
TxD
Output
Asynchronous serial interface serial data output.
Input
P71/SO2
ASCK
Input
Asynchronous serial interface serial clock input.
Input
P72/SCK2
TI00
Input
External count clock input to 16-bit timer (TM0).
Input
P00/INTP0
SB0
SB1
SCK0
SCK2
Input
P25/SI0
P26/SO0
Input
P27
P72/ASCK
TI01
Capture trigger signal input to capture register (CR00).
TI1
External count clock input to 8-bit timer (TM1).
P33
TI2
External count clock input to 8-bit timer (TM2).
P34
TO0
Output
16-bit timer (TM0) output (shared with 14-bit PWM output).
P01/INTP1
Input
P30
TO1
8-bit timer (TM1) output.
P31
TO2
8-bit timer (TM2) output.
P32
PCL
Output
Clock output (for main system clock, subsystem clock trimming).
Input
P35
BUZ
Output
Buzzer output.
Input
P36
S0 to S23
Output
LCD controller/driver segment signal output.
Output
—
Input
P97 to P90
S24 to S31
S32 to S39
COM0 to COM3
P87 to P80
Output
LCD controller/driver common signal output.
Output
—
VLC0 to VLC2
—
LCD drive voltage. Split resistors can be incorporated by mask option.
—
—
BIAS
—
LCD drive power supply.
—
—
13
µPD78064B(A)
3.2
Non-port Pins (2/2)
Pin Name
I/O
Function
After Reset
Alternate
function
Input
P10 to P17
ANI0 to ANI7
Input
A/D converter analog input.
AVREF
Input
A/D converter reference voltage input.
—
—
AVDD
—
A/D converter analog power supply (shared with the port power supply).
—
—
AVSS
—
A/D converter ground potential (shared with the port ground potential).
—
—
RESET
Input
System reset input.
—
—
X1
Input
Main system clock oscillation crystal connection.
—
—
X2
—
—
—
Input
P07
—
—
XT1
Input
Subsystem clock oscillation crystal connection.
XT2
—
VDD
—
Positive power supply (except for port).
—
—
VSS
—
Ground potential (except for port).
—
—
IC
—
Internal connection. Connect directly to VSS pin.
—
—
Cautions 1. The AVDD pin functions as both an A/D converter power supply and a port power supply. When
the µPD78064B(A) is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVDD pin to another power supply which has the same potential
as VDD.
2. The AVSS pin functions as both an A/D converter ground and a port ground. When the
µPD78064B(A) is used in applications where the noise generated inside the microcontroller
needs to be reduced, connect the AVSS pin to another ground line than VSS.
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Input/output
Circuit Type
I/O
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-D
Input/output
16
Input
Pin Name
Recommended Connection when not Used
Connected to VSS.
Independently connected to VSS through a resistor.
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1
14
Connected to VDD.
µPD78064B(A)
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Input/output
Circuit Type
I/O
Recommended Connection when not Used
P10/ANI0 to P17/ANI7
11-C
Input/output
Independently connected to VDD or VSS through a resistor.
P25/SI0/SB0
10-C
Input/output
Independently connected to VDD or VSS through a resistor.
Pin Name
P26/SO0/SB1
P27/SCK0
P30/TO0
5-J
P31/TO1
P32/TO2
P33/TI1
8-D
P34/TI2
P35/PCL
5-J
P36/BUZ
P37
P70/SI2/RxD
8-D
P71/SO2/TxD
5-J
P72/SCK2/ASCK
8-D
P80/S39 to P87/S32
17-E
P90/S31 to P97/S24
P100 to P103
5-J
P110 to P117
8-D
S0 to S23
17-D
COM0 to COM3
18-B
VLC0 to VLC2
Independently connected to VDD through a resistor.
Output
—
—
RESET
2
Input
XT2
16
—
AVREF
—
Leave open
BIAS
—
Leave open.
Connected to VSS.
AVDD
Connected to another power supply which has the same potential as VDD.
AVSS
Connected to another ground line which has the same potential as VSS.
IC
Connected directly to VSS.
15
µPD78064B(A)
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2
Type 10-C
AV DD
pullup
enable
P-ch
AV DD
IN
data
P-ch
IN/OUT
Schmitt-Triggered Input with Hysteresis Characteristic
open drain
output disable
N-ch
AV SS
Type 5-J
Type 11-C
AV DD
AV DD
pullup
enable
pullup
enable
P-ch
AV DD
P-ch
data
P-ch
VDD
data
IN/OUT
output
disable
P-ch
IN/OUT
N-ch
P-ch
Comparator
AV SS
+
output
disable
N-ch
–
N-ch
VREF AV SS
(Threshold Voltage)
AV SS
input
enable
input
enable
Type 16
Type 8-D
AV DD
feedback cut-off
pullup
enable
P-ch
P-ch
AV DD
data
P-ch
IN/OUT
output
disable
N-ch
AV SS
XT1
16
XT2
µPD78064B(A)
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 17-D
Type 18-B
VLC0
VLC0
P-ch
P-ch
VLC1
VLC1
N-ch
N-ch
P-ch
P-ch
SEG
data
N-ch
OUT
N-ch
P-ch
COM
data
N-ch
VLC2
N-ch
P-ch
OUT
P-ch
VLC2
N-ch
VSS
VSS
Type 17-E
AV DD
pullup
enable
P-ch
AV DD
data
P-ch
IN/OUT
N-ch
output
disable
AV SS
input
enable
VLC0
P-ch
VLC1
N-ch
P-ch
SEG
data
N-ch
P-ch
VLC2
N-ch
AV SS
17
µPD78064B(A)
4. MEMORY SPACE
The memory map of the µPD78064B(A) is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH
Special Function Register (SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
General Registers
32 × 8 bits
Internal High-Speed RAM
1024 × 8 bits
Program Area
FB00H
FAFFH
Data Memory
Space
Reserved
FA80H
FA7FH
FA58H
FA57H
LCD Display RAM
40 × 4 bits
0800H
07FFH
Program Area
0080H
007FH
CALLT Table Area
8000H
7FFFH
Internal ROM
0040H
003FH
32768 × 8 bits
0000H
18
1000H
0FFFH
CALLF Entry Area
Reserved
Program
Memory
Space
7FFFH
Vector Table Area
0000H
µPD78064B(A)
5. PERIPHERAL HARDWARE FUNCTION FEATURE
5.1
Port
There are two kinds of I/O ports.
• CMOS input (P00, P07)
: 2
• CMOS input/output (P01 to P05, Port 1 to 3, 7 to 11)
: 55
Total
: 57
Table 5-1. Functions of Ports
Name
Port 0
Pin Name
P00, P07
Function
Dedicated input port
P01 to P05
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 1
P10 to P17
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 2
P25 to P27
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 3
P30 to P37
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 7
P70 to P72
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 8
P80 to P87
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display
control register (LCDC).
Port 9
P90 to P97
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display
control register (LCDC).
Port 10
P100 to P103
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Direct LED drive capability.
Port 11
P110 to P117
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
4
19
µPD78064B(A)
5.2
Clock Generator
There are two kinds of clocks, a main system clock and a subsystem clock.
The minimum instruction execution time can also be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation with main system clock)
• 122 µs (@ 32.768-kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
XT2
Subsystem
Clock
Oscillator
fXT
Watch Timer
Clock Output Function
Prescaler
X1
X2
Main
System
Clock
Oscillator
fX
Selector
Prescaler
fXX
Clock to
Peripheral
Hardware
1/2
Divider
fX
2
fXX
2
fXX fXX fXX
22 23 24
fXT
2
STOP
Selector
Standby
Control
Circuit
CPU
Clock
(fCPU)
To INTP0
Sampling Clock
5.3
Timer/Event Counter
Five timer/event counter channels are incorporated.
• 16-bit timer/event counter
: 1 channel
• 8-bit timer/event counter
: 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Table 5-2. Timer/Event Counter Types and Functions
Type
Function
Interval timer
External event counter
Timer output
PWM output
Pulse width measurement
Square wave output
One-shot pulse output
Interrupt request
Test input
20
16-bit Timer/
Event Counter
1 channel
1 channel
1 output
1 output
2 inputs
1 output
1 output
2
8-bit Timer/
Event Counter
2 channels
2 channels
2 outputs
–
–
2 outputs
–
2
—
—
Watch Timer
Watchdog Timer
1 channel
–
–
–
–
–
–
1
1 channel
–
–
–
–
–
–
1
1 input
–
µPD78064B(A)
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal Bus
INTP1
TI01/P01/INTP1
16-Bit
Capture/Compare
Register (CR00)
Selector
INTTM00
PWM
Pulse
Output
Control
Circuit
Match
Watch Timer Output
2fXX
fXX
16-Bit
Timer Register
(TM0)
Selector
fXX/2
fXX/22
TI00/P00/INTP0
Output
Control Circuit
Clear
Edge
Detector
TO0/P30
4
Selector
Match
INTTM01
INTP0
16-Bit
Capture/Compare
Register (CR01)
Internal Bus
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus
INTTM1
8-Bit
Compare
Register (CR10)
8-Bit
Compare Register
(CR20)
Match
Match
fXX/2-fXX/29
fXX/211
Selector
Output
Control
Circuit
TO2/P32
INTTM2
8-Bit
Timer Register 1
(TM1)
TI1/P33
Clear
Selector
8-Bit
Timer Register 2
(TM2)
Clear
fXX/2-fXX/29
fXX/211
Selector
Selector
Selector
TI2/P34
Output
Control
Circuit
TO1/P31
Internal Bus
21
µPD78064B(A)
Figure 5-4. Watch Timer Block Diagram
fXX/27
Selector
Selec- fW
tor
fXT
fW
214
5-Bit Counter
Prescaler
fW
24
fW
25
fW
26
fW
27
Selector
fW
28
INTWT
fW
213
fW
29
Selector
INTTM3
To 16-Bit
Timer/Event Counter
To LCD
Controller/Driver
Figure 5-5. Watchdog Timer Block Diagram
fXX
23
Prescaler
fXX
24
fXX
25
fXX
26
fXX
27
fXX
28
fXX
29
fXX
211
INTWDT
Maskable
Interrupt
Request
Selector
8-Bit Counter
Control
Circuit
RESET
INTWDT
Non-Maskable
Interrupt
Request
22
µPD78064B(A)
5.4
Clock Output Control Circuit
Clocks of the following frequency can be output as clock outputs:
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (@ 5.0-MHz operation
with main system clock)
• 32.768 kHz (@32.768-kHz operation with subsystem clock)
Figure 5-6. Clock Output Control Circuit Block Diagram
fXX
fXX/2
fXX/22
fXX/23
fXX/24
Selector
Synchronization
Circuit
Output Control Circuit
PCL/P35
4
fXX/25
fXX/26
fXX/27
fXT
5.5
Buzzer Output Control Circuit
Clocks of the following frequency can be output as buzzer outputs:
• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (@ 5.0-MHz operation with main system clock)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
fXX/29
fXX/210
Selector
Output Control Circuit
BUZ/P36
11
fXX/2
23
µPD78064B(A)
5.6
A/D converter
Eight 8-bit resolution A/D converter channels are incorporated.
The following two types of start-up method are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series Resistor String
AV DD
AV REF
ANI0/P10
ANI1/P11
Sample & Hold Circuit
ANI2/P12
ANI3/P13
ANI4/P14
Voltage Comparator
Selector
Tap
Selector
ANI5/P15
ANI6/P16
AV SS
ANI7/P17
INTP3/P03
Successive Approximation
Register (SAR)
Edge
Detector
Control
Circuit
INTAD
INTP3
A/D Conversion Result
Register (ADCR)
Internal Bus
Caution For pins which also function as port pins (refer to 3.1 Port Pins), do not perform the following
operations during A/D conversion. If these operations are performed, the total error ratings cannot
be kept (except for LCD segment output alternate-function pin).
(1) Rewriting the output latch while the pin is used as a port pin.
(2) Changing the output level of the pin used as an output pin, even if it is not used as a port pin.
24
µPD78064B(A)
5.7
Serial Interface
Two clocked serial interface channels are incorporated:
• Serial interface channel 0
• Serial interface channel 2
Table 5-3. Serial Interface Types and Functions
Function
3-wire serial I/O mode
SBI (serial bus interface) mode
2-wire serial I/O mode
Asynchronous serial interface
(UART) mode
Serial Interface Channel 0
Yes (MSB/LSB-first switchable)
Yes (MSB-first)
Yes (MSB-first)
No
Serial Interface Channel 2
Yes (MSB/LSB-first switchable)
No
No
Yes (Dedicated baud rate generator
incorporated)
4
25
µPD78064B(A)
Figure 5-9. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
Selector
Serial I/O
Shift Register 0 (SIO0)
Output
Latch
SO0/SB1/P26
Selector
SCK0/P27
Busy/Acknowledge
Output Circuit
Bus Release/Command/
Acknowledge Detector
Interrupt Request
Signal Generator
Serial Clock Counter
INTCSI0
fXX/2-fXX/28
Serial Clock Control Circuit
Selector
TO2
Figure 5-10. Serial Interface Channel 2 Block Diagram
Internal bus
RXD/SI2/P70
Receive Buffer
Register (RXB/SIO2)
Direction
Control Circuit
Direction
Control Circuit
Transmit Shift
Register (TXS/SIO2)
Receive Shift
Register (RXS)
Transmit
Control Circuit
TXD/SO2/P71
Receive
Control Circuit
INTSER
INTSR/INTCSI2
SCK Output
Control Circuit
ASCK/SCK2/P72
Baud Rate
Generator
26
fXX-fXX/210
INTST
µPD78064B(A)
5.8
LCD Controller/Driver
An LCD controller/driver with the following functions is incorporated.
• Selection of 5 types of display mode
• 16 of the segment signal of outputs can be switched to input/output ports in units of 2.
(P80/S39 to P87/S32, P90/S31 to P97/S24)
Table 5-4. Display Mode Types and Maximum Number of Display Pixels
Bias Method
Time Multiplexing
—
1/2
Static
2
3
3
4
1/3
Common Signal Used
COM0 (COM1 to COM3)
COM0, COM1
COM0 to COM2
COM0 to COM2
COM0 to COM3
Maximum Number of Display Pixels
40 (40 segments × 1 common)
80 (40 segments × 2 commons)
120 (40 segments × 3 commons)
160 (40 segments × 4 commons)
4
Figure 5-11. LCD Controller/Driver Block Diagram
Internal Bus
fW
26
Prescaler
Display
Data Memory
fW
29
Timing Controller
Segment
Data Selector
fW
28
fW
27
LCDCL
Selector
Port
Output Data
LCD Drive Voltage
Generator
Common Driver
Segment Driver
S0
S23 S24/P97
S39/P80
COM0 COM1 COM2 COM3
VLC2
VLC1
VLC0
BIAS
27
µPD78064B(A)
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1
Interrupt Functions
There are twenty interrupt sources of three different kinds, as shown below.
• Non-maskable : 1
28
• Maskable
: 18
• Software
: 1
µPD78064B(A)
Table 6-1. Interrupt Source List
Interrupt
Type
Default
Priority Note1
Interrupt Source
Name
Trigger
Nonmaskable
—
INTWDT
Watchdog timer overflow (with watchdog
timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow (with interval
timer mode selected)
1
INTP0
Pin input edge detection
2
Software
Internal/
External
Internal
Vector
Table
Address
Basic
Configuration
Type Note2
0004H
(A)
(B)
External
0006H
(C)
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTCSI0
Serial interface channel 0 transfer termination
8
INTSER
Serial interface channel 2 UART
reception error generation
0018H
9
INTSR
Serial interface channel 2 UART
reception termination
001AH
INTCSI2
Serial interface channel 2 3-wire transfer
termination
10
INTST
Serial interface channel 2 UART
transmission termination
001CH
11
INTTM3
Reference time interval signal from watch timer
001EH
12
INTTM00
16-bit timer register and capture/compare
register (CR00) match signal generation
0020H
13
INTTM01
16-bit timer register and capture/compare
register (CR01) match signal generation
0022H
14
INTTM1
8-bit timer/event counter 1 match signal
generation
0024H
15
INTTM2
8-bit timer/event counter 2 match signal
generation
0026H
16
INTAD
A/D converter conversion termination
0028H
—
BRK
BRK instruction execution
Internal
—
0014H
003EH
(B)
(E)
Notes 1. Default priority is a priority order when more than one maskable interrupt source is generated simultaneously. 0 is the highest priority and 16 the lowest priority.
2. Basic configuration types (A) to (E) correspond to those shown in Figure 6-1.
29
µPD78064B(A)
Figure 6-1. Basic Configuration of Interrupt Functions (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Priority
Control
Circuit
Interrupt
Request
Vector Table
Address
Generator
Standby Release
Signal
(B) Internal maskable interrupt
Internal Bus
MK
Interrupt
Request
IE
PR
ISP
Priority
Control
Circuit
IF
Vector Table
Address
Generator
Standby Release
Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Interrupt
Request
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
Sampling
Clock
Edge
Detector
MK
IF
IE
PR
Priority
Control
Circuit
ISP
Vector Table
Address
Generator
Standby
Release
Signal
30
µPD78064B(A)
Figure 6-1. Basic Configuration of Interrupt Functions (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
Interrupt
Request
Edge
Detector
MK
IE
PR
ISP
Priority Control
Circuit
IF
Vector Table
Address
Generator
Standby
Release
Signal
(E) Software interrupt
Internal Bus
Interrupt
Request
IF
: Interrupt request flag
IE
: Interrupt enable flag
Priority
Control
Circuit
Vector Table
Address
Generator
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
31
µPD78064B(A)
6.2
Test Functions
There are two test functions as shown in Table 6-2.
Table 6-2. Test Input Source List
Test Input Source
Name
Trigger
Internal/External
INTWT
Watch timer overflow
Internal
INTPT11
Port 11 falling edge detection
External
Figure 6-2. Basic Configuration of Test Function
Internal Bus
MK
Test Input
Signal
IF
: Test input flag
MK : Test mask flag
32
IF
Standby Release
Signal
µPD78064B(A)
7. STANDBY FUNCTION
The standby function is a function to reduce current consumption. The following two kinds of standby functions are
provided.
• HALT mode : Halts CPU operating clock and can reduce average current consumption by the intermittent
operation along with the normal operation.
• STOP mode : Halts main system clock oscillation. Halts all operations with the main system clock and sets
ultra-low current consumption state with subsystem clock only.
Figure 7-1. Standby Function
CSS=1
Subsystem Clock OperationNote
Main System Clock Operation
CSS=0
STOP
Instruction
Interrupt
Request
(
STOP Mode
Main System Clock
Oscillation Halted
HALT Instruction
HALT Instruction
Interrupt
Request
Interrupt
Request
)
HALT Mode
Clock Supply to CPU Halted,
Oscillation Maintained
(
)
HALT ModeNote
Clock Supply to CPU Halted,
Oscillation Maintained
(
)
Note Halting the main system clock enables the current consumption to be reduced.
When the CPU is operated by the subsystem clock, the main system clock should be halted by setting the bit
7 (MCC) of the processor clock control register (PCC). The STOP instruction is not available.
Caution When the main system clock is stopped and the system is operated by the subsystem clock, the
main system clock should be returned to after securing the oscillation stabilization time by a
program.
8. RESET FUNCTION
There are the following two kinds of resetting methods.
• External reset by RESET pin.
• Internal reset by watchdog timer runaway time detection.
33
µPD78064B(A)
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd operand
#byte
A
r Note
sfr
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
saddr !addr16 PSW
[DE]
[HL]
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
1st operand
A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r
MOV
B, C
sfr
saddr
!addr16
PSW
MOV
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
1
None
ROR
ROL
RORC
ROLC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
INC
DEC
DBNZ
MOV
MOV
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
MOV
[DE]
[HL]
MOV
MOV
[HL+byte]
[HL+B]
[HL+C]
X
C
MOV
Note Except r = A
34
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
[HL+byte]
[HL+B]
$addr16
[HL+C]
DBNZ
INC
DEC
PUSH
POP
ROR4
ROL4
MULU
DIVUW
µPD78064B(A)
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd operand
#word
AX
rp Note
sfrp
saddrp
!addr16
SP
None
1st operand
AX
ADDW
SUBW
CMPW
MOVW
rp
sfrp
saddrp
!addr16
SP
MOVW
MOVW
MOVW
MOVW
XCHW
MOVW
MOVW
MOVW
MOVW
MOVW Note
INCW,DECW
PUSH, POP
MOVW
MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
1st operand
A.bit
MOV1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
(4) Call instruction/branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd operand
AX
!addr16
!addr11
[addr5]
$addr16
1st operand
Basic instruction
BR
Compound
instruction
CALL
BR
CALLF
CALLT
BR, BC, BNC,
BZ, BNZ
BT, BF,
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
35
µPD78064B(A)
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Rating
Unit
VDD
–0.3 to +7.0
V
AVDD
–0.3 to VDD + 0.3
V
AVREF
–0.3 to VDD + 0.3
V
AVSS
–0.3 to +0.3
V
Input voltage
VI
–0.3 to VDD + 0.3
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Analog input voltage
VAN
P10 to P17
AVSS – 0.3 to AVREF + 0.3
V
Output current high
IOH
Per pin
–10
mA
Total for P01 to P05, P10 to P17, P25 to P27,
P30 to P37, P70 to P72, P80 to P87, P90 to P97,
P100 to P103, P110 to P117
–15
mA
Per pin
Peak value
30
mA
r.m.s. value
15
mA
Total for P01 to P05, P10 to P17,
Peak value
P25 to P27, P30 to P37, P70 to P72,
P80 to P87, P90 to P97,
r.m.s. value
P100 to P103, P110 to P117
100
mA
70
mA
Supply voltage
Output current low
Symbol
IOL Note
Test Conditions
Analog input pin
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] x √ Duty
Caution The product quality may be damaged even if a value of only one of the above parameters exceeds
the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That
is, the absolute maximum rating is a rating value which may cause a product to be damaged
physically. The absolute maximum rating values must therefore be observed when using the
product.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
CAPACITANCE (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz
15
pF
Output capacitance
COUT
Unmeasured pins
15
pF
I/O capacitance
CIO
returned to 0 V.
15
pF
36
µPD78064B(A)
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Ceramic
resonator
Recommended circuit
X1
IC X2
R1
C1
C2
Crystal
resonator
IC
X1
X2
R1
C2
C1
Parameter
Test conditions
Oscillation
frequency (fX) Note 1
VDD = Oscillation
voltage range
Oscillation
stabilization time Note 2
After VDD reaches oscillation voltage range MIN.
Oscillation
frequency (fX) Note 1
Oscillation
stabilization time Note 2
MIN.
TYP.
1
1
VDD = 4.5 to 6.0 V
MAX.
Unit
5
MHz
4
ms
5
MHz
10
ms
30
External clock
X2
µ PD74HCU04
X1
X1 input
frequency (fX) Note 1
1
5
MHz
X1 input
high-/low-level width
(tXH , tXL)
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the dotted line
should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
2. If the main system clock oscillator is operated by the subsystem clock when the main system
clock is stopped, reswitching to the main system clock should be performed after the oscillation
stabilization time has been obtained by the program.
37
µPD78064B(A)
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Crystal
resonator
Recommended circuit
IC XT1
XT2
R2
C3
C4
Parameter
Test conditions
Oscillation frequency
(fXT) Note 1
Oscillation
stabilization time
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
VDD = 4.5 to 6.0 V
Note 2
10
External clock
XT1
XT2
XT1 input frequency
(fXT) Note 1
32
100
kHz
XT1 input
high-/low-level
width (tXTH/tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line
should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
2. The subsystem clock oscillator is designed as a low amplification circuit to provide low
consumption current, causing misoperation by noise more frequently than the main system
clock oscillation circuit. Special care should therefore be taken about the wiring method when
the subsystem clock is used.
38
µPD78064B(A)
RECOMMENDED OSCILLATOR CONSTANT
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = –40 to +85°C)
Manufacturer
Murata Mfg.
Co., Ltd.
Matsushita
Electronics
Components
Co., Ltd.
Kyocera
Corporation
Part Number
Frequency (MHz)
Recommended
Circuit Constant
Oscillation
Voltage Range
Remarks
C1 (pF)
C2 (pF)
MIN. (V)
MAX. (V)
CSA5.00MG
5.00
30
30
2.2
6.0
CST5.00MGW
5.00
On-chip
On-chip
2.7
6.0
EF0GC5004A4
5.00
On-chip
On-chip
2.7
6.0
Lead type
EF0EC5004A4
5.00
On-chip
On-chip
2.0
6.0
Round lead type
EF0EN5004A4
5.00
33
33
2.7
6.0
Lead type
EF0S5004B5
5.00
On-chip
On-chip
2.7
6.0
Chip type
KBR-5.0MSA
5.00
33
33
2.7
6.0
Lead type
PBRC5.00A
5.00
33
33
2.7
6.0
Chip type
KBR-5.0MKS
5.00
On-chip
On-chip
2.7
6.0
Lead type
KBR-5.0MWS
5.00
On-chip
On-chip
2.7
6.0
Chip type
SUBSYSTEM CLOCK: CRYSTAL RESONATOR (TA = –40 to +60°C)
Manufacturer
Kyocera
Corporation
Part Number
KF-38G-12P0200Note
(Load capacitance 12 pF)
Recommended
Circuit Constant
Frequency (kHz)
32.768
Oscillation
Voltage Range
C3 (pF)
C4 (pF)
R2 (kΩ)
MIN. (V)
MAX. (V)
15
22
220
2.0
6.0
Note Maintenance-only product
Caution The recommended circuit constant and the oscillation voltage range are the conditions required for
stable oscillation, but do not guarantee oscillation frequency accuracy. In the case of applications
requiring oscillation frequency accuracy, the oscillation frequency must be adjusted in a mounted
circuit. For details, consult the resonator manufacturer directly.
39
µPD78064B(A)
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Input voltage,
high
Symbol
VIH1
Test Conditions
P10 to P17, P30 to P32,
P35 to P37, P80 to P87,
P90 to P97, P100 to P103
VDD = 2.7 to 6.0 V
P00 to P05, P25 to P27,
P33, P34, P70 to P72,
P110 to P117, RESET
VDD = 2.7 to 6.0 V
VIH3
X1, X2
VDD = 2.7 to 6.0 V
VIH4
XT1/P07, XT2
4.5 V ≤ VDD ≤ 6.0 V
VIH2
MIN.
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
Input voltage,
VIL1
P10 to P17, P30 to P32,
P35 to P37, P80 to P87,
P90 to P97, P100 to P103
VDD = 2.7 to 6.0 V
P00 to P05, P25 to P27,
P33, P34, P70 to P72,
P110 to P117, RESET
VDD = 2.7 to 6.0 V
VIL3
X1, X2
VDD = 2.7 to 6.0 V
VIL4
XT1/P07, XT2
4.5 V ≤ VDD ≤ 6.0 V
low
VIL2
Note
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
Output voltage,
high
VOH
Output voltage,
VOL1
Note
TYP.
MAX.
Unit
0.7 VDD
VDD
V
0.8 VDD
VDD
V
0.8 VDD
VDD
V
0.85 VDD
VDD
V
VDD – 0.5
VDD
V
VDD – 0.2
VDD
V
0.8 VDD
VDD
V
0.9 VDD
VDD
V
0.9 VDD
VDD
V
0
0.3 VDD
V
0
0.2 VDD
V
0
0.2 VDD
V
0
0.15 VDD
V
0
0.4
V
0
0.2
V
0
0.2 VDD
V
0
0.1 VDD
V
0
0.1 VDD
V
VDD = 4.5 to 6.0 V, IOH = –1 mA
VDD – 1.0
VDD
V
IOH = –100 µA
VDD – 0.5
VDD
V
2.0
V
P100 to P103
VDD = 4.5 to 6.0 V,
IOL = 15 mA
P01
P25
P70
P90
VDD = 4.5 to 6.0 V,
IOL = 1.6 mA
0.4
V
VDD = 4.5 to 6.0 V,
open-drain,
pull-up (R = 1 kΩ)
0.2 VDD
V
0.5
V
low
to
to
to
to
P05,
P27,
P72,
P97,
P10 to P17,
P30 to P37,
P80 to P87,
P110 to P117
VOL2
SB0, SB1, SCK0
VOL3
IOL = 400 µA
0.4
Note When P07/XT1 is used as P07, the inverse phase of P07 should be input to XT2.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
40
µPD78064B(A)
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Test Conditions
VIN = VDD
ILIH2
Input leakage
current, low
ILIL1
VIN = 0 V
ILIL2
MIN.
TYP.
MAX.
Unit
P00 to P05, P10 to P17,
P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117
3
µA
X1, X2, XT1/P07, XT2
20
µA
P00 to P05, P10 to P17,
P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117
–3
µA
X1, X2, XT1/P07, XT2
–20
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Software
pull-up resistor
R
90
kΩ
500
kΩ
4
12
mA
0.6
1.8
mA
Supply
current Note 1
IDD1
IDD2
VIN = 0 V, P01 to P05,
4.5 V ≤ VDD ≤ 6.0 V
P10 to P17, P25 to P27,
P30 to P37, P70 to P72,
2.7 V ≤ VDD < 4.5 V
P80 to P87, P90 to P97,
P100 to P103, P110 to P117
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 % Note 4
(fXX = 2.5 MHz) Note 2
VDD = 3.0 V ± 10 % Note 5
operating mode
VDD = 2.2 V ± 10 % Note 5
15
40
20
0.35
1.05
mA
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 % Note 4
(fXX = 5.0 MHz) Note 3
VDD = 3.0 V ± 10 % Note 5
operating mode
6.5
19.5
mA
0.8
2.4
mA
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 %
(fXX = 2.5 MHz) Note 2
VDD = 3.0 V ± 10 %
HALT mode
VDD = 2.2 V ± 10 %
1.4
4.2
mA
500
1500
µA
280
840
µA
1.6
4.8
mA
650
1950
µA
5.00-MHz crystal oscillation VDD = 5.0 V ± 10 %
(fXX = 5.0 MHz) Note 3
VDD = 3.0 V ± 10 %
HALT mode
Notes 1. The current flowing in VDD and AVDD, excluding the current flowing in an A/D converter, on-chip pullup resistors and LCD split resistors
2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
3. Main system clock fXX = fX operation (when OSMS is set to 01H)
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
5. Low-speed mode operation (when PCC is set to 04H)
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
41
µPD78064B(A)
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Supply
current Note 1
Symbol
IDD3
IDD4
IDD5
IDD6
Test Conditions
32.768-kHz crystal oscillation
operating mode Note 2
32.768-kHz crystal oscillation
HALT mode Note 2
MIN.
TYP.
MAX.
Unit
VDD = 5.0 V ± 10 %
60
120
µA
VDD = 3.0 V ± 10 %
32
64
µA
VDD = 2.2 V ± 10 %
24
48
µA
VDD = 5.0 V ± 10 %
25
55
µA
VDD = 3.0 V ± 10 %
5
15
µA
VDD = 2.2 V ± 10 %
2.5
12.5
µA
XT1 = VDD
VDD = 5.0 V ± 10 %
STOP mode
VDD = 3.0 V ± 10 %
When feedback resistor is connected
VDD = 2.2 V ± 10 %
1
30
µA
0.5
10
µA
0.3
10
µA
XT1 = VDD
STOP mode
VDD = 5.0 V ± 10 %
0.1
30
µA
VDD = 3.0 V ± 10 %
0.05
10
µA
When feedback resistor is disconnected
VDD = 2.2 V ± 10 %
0.05
10
µA
Notes 1. The current flowing in VDD and AVDD, excluding the current flowing in an A/D converter, on-chip pullup resistors and LCD split resistors
2. When the main system clock is stopped.
42
µPD78064B(A)
DC CHARACTERISTICS (TA = –10 to +85°C)
(1) Static Display Mode (VDD = 2.0 to 6.0 V)
Parameter
LCD drive voltage
Symbol
Test Conditions
MIN.
TYP.
2.0
VLCD
LCD split resistor
RLCD
LCD output voltage
deviation Note (common)
VODC
IO = ±5 µA
LCD output voltage
deviation Note (segment)
VODS
IO = ±1 µA
60
2.0 V ≤ VLCD ≤ VDD
VLCD0 = VLCD
100
MAX.
Unit
VDD
V
150
kΩ
0
±0.2
V
0
±0.2
V
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
(2) 1/3 Bias Method (VDD = 2.5 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
VDD
V
150
kΩ
0
±0.2
V
0
±0.2
V
LCD drive voltage
VLCD
2.5
LCD split resistor
RLCD
60
LCD output voltage
deviation Note (common)
VODC
IO = ±5 µA
LCD output voltage
deviation Note (segment)
VODS
IO = ±1 µA
2.5 V ≤ VLCD ≤ VDD
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
TYP.
100
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
(3) 1/2 Bias Method (VDD = 2.7 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
VDD
V
150
kΩ
0
±0.2
V
0
±0.2
V
LCD drive voltage
VLCD
2.7
LCD split resistor
RLCD
60
LCD output voltage
deviation Note (common)
VODC
IO = ±5 µA
LCD output voltage
VODS
IO = ±1 µA
deviation Note (segment)
2.7 V ≤ VLCD ≤ VDD
VLCD0 = VLCD
VLCD1 = VLCD × 1/2
TYP.
100
VLCD2 = VLCD1
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
43
µPD78064B(A)
AC CHARACTERISTICS
(1) Basic Operation (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Cycle time
(Minimum
instruction
execution time)
Symbol
TCY
Test Conditions
Operating on
MAX.
Unit
0.8
64
µs
2.2
64
µs
4.5 ≤ VDD ≤ 6.0 V
0.4
32
µs
2.7 ≤ VDD < 4.5 V
0.8
32
µs
125
µs
VDD = 2.7 to 6.0 V
main system clock
(fXX = 2.5 MHz)Note 1
Operating on
main system clock
(fXX = 5.0 MHz)Note 2
Operating on subsystem clock
TI00 input
high-/low-level
MIN.
tTIH00,
tTIL00
width
µs
2.7 V ≤ VDD < 4.5 V
2/fsam + 0.2
Note 4
µs
2/fsam + 0.5
Note 4
µs
2.0 V ≤ VDD < 2.7 V
VDD = 2.7 to 6.0 V
TI1, TI2 input
frequency
fTI1
VDD = 4.5 to 6.0 V
TI1, TI2 input
high-/low-level width
tTIH1,
tTIL1
RESET low-level
width
tRSL
122
2/fsam + 0.1Note 4
tTIH01,
tTIL01
tINTH,
tINTL
40 Note 3
4.5 V ≤ VDD ≤ 6.0 V
TI01 input
high-/low-level width
Interrupt input
high-/low-level
width
TYP.
VDD = 4.5 to 6.0 V
INTP0
INTP1 to INTP5,
P110 to P117
10
µs
20
µs
0
4
MHz
0
275
kHz
100
ns
1.8
µs
8/fsam
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
Note 4
µs
10
µs
20
µs
10
µs
20
µs
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
2. Main system clock fXX = fX operation (when OSMS is set to 01H)
3. This is the value when the external clock is used. The value is 114 µs (min.) when the crystal
resonator is used.
4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of
fsam is possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4).
44
µPD78064B(A)
TCY vs VDD (At main system clock fXX = fX/2 operation)
TCY vs VDD (At main system clock fXX = fX operation)
60
60
Cycle Time TCY [µs]
Cycle Time TCY [µs]
32
10
Guaranteed Operation
Range
2.0
10
Guaranteed Operation
Range
2.0
1.0
0.8
1.0
0.8
0.4
0.4
0
1
2
3
4
5
Supply Voltage VDD [V]
6
0
1
2
3
4
5
6
Supply Voltage VDD [V]
45
µPD78064B(A)
(2) Serial Interface (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
(a) Serial interface channel 0
(i)
3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY1
SCK0 high-/low-level
width
tKH1,
tKL1
SI0 setup time
(to SCK0↑)
tSIK1
SI0 hold time (from SCK0↑)
tKSI1
SO0 output delay time
from SCK0↓
tKSO1
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
300
ns
VDD = 4.5 to 6.0 V
400
ns
C = 100 pF Note
300
ns
MAX.
Unit
Note C is the load capacitance of SCK0, SO0 output line.
(ii) 3-wire serial I/O mode (SCK0...External clock input)
Parameter
SCK0 cycle time
Symbol
tKCY2
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
SCK0 high-/low-level
tKH2,
4.5 V ≤ VDD ≤ 6.0 V
400
ns
width
tKL2
2.7 V ≤ VDD < 4.5 V
800
ns
1600
ns
SI0 setup time (to SCK0↑)
tSIK2
100
ns
SI0 hold time (from SCK0↑)
tKSI2
400
ns
SO0 output delay time
from SCK0↓
tKSO2
SCK0 rise, fall time
tR2,
tF2
C = 100 pF
Note
Note C is the load capacitance of SO0 output line.
46
300
ns
1000
ns
µPD78064B(A)
(iii) SBI mode (SCK0...Internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY3
VDD = 4.5 to 6.0 V
800
ns
3200
ns
SCK0 high-/low-level
width
tKH3,
tKL3
VDD = 4.5 to 6.0 V
tKCY3/2 – 50
ns
tKCY3/2 – 150
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK3
VDD = 4.5 to 6.0 V
100
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI3
SB0, SB1 output delay
time from SCK0↓
tKSO3
SB0, SB1↓ from SCK0↑
tKSB
tKCY3
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY3
ns
SB0, SB1 high-level width
tSBH
tKCY3
ns
SB0, SB1 low-level width
tSBL
tKCY3
ns
R = 1 kΩ,
C = 100 pF Note
VDD = 4.5 to 6.0 V
300
ns
tKCY3/2
ns
0
250
ns
0
1000
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output lines, respectively.
(iv) SBI mode (SCK0...External clock input)
Parameter
SCK0 cycle time
Symbol
tKCY4
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
tKCY4/2
ns
SCK0 high-/low-level
width
tKH4,
tKL4
VDD = 4.5 to 6.0 V
SB0, SB1 setup time
(to SCK0↑)
tSIK4
VDD = 4.5 to 6.0 V
SB0, SB1 hold time
(from SCK0↑)
tKSI4
SB0, SB1 output delay
time from SCK0↓
tKSO4
SB0, SB1↓ from SCK0↑
tKSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0, SB1 high-level width
tSBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 rise, fall time
tR4,
tF4
R = 1 kΩ,
C = 100 pF Note
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
47
µPD78064B(A)
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
Test Conditions
R = 1 kΩ,
C = 100 pF
SCK0 high-level width
TYP.
MAX.
Unit
VDD = 2.7 to 6.0 V
1600
ns
3200
ns
VDD = 2.7 to 6.0 V
tKCY5/2 – 160
ns
tKCY5/2 – 190
ns
tKCY5/2 – 50
ns
Note
tKH5
MIN.
SCK0 low-level width
tKL5
VDD = 4.5 to 6.0 V
tKCY5/2 – 100
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK5
4.5 V ≤ VDD ≤ 6.0 V
300
ns
2.7 V ≤ VDD < 4.5 V
350
ns
400
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI5
600
ns
SB0, SB1 output delay
time from SCK0↓
tKSO5
0
300
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output lines, respectively.
(vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
SCK0 cycle time
tKCY6
VDD = 2.7 to 6.0 V
SCK0 high-level width
tKH6
VDD = 2.7 to 6.0 V
SCK0 low-level width
tKL6
VDD = 2.7 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
ns
3200
ns
650
ns
1300
ns
800
ns
1600
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK6
100
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI6
tKCY6/2
ns
SB0, SB1 output delay
time from SCK0↓
tKSO6
SCK0 rise, fall time
tR6,
tF6
R = 1 kΩ,
C = 100 pF Note
VDD = 4.5 to 6.0 V
0
300
ns
0
500
ns
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
48
µPD78064B(A)
(b) Serial interface channel 2
(i)
3-wire serial I/O mode (SCK2... Internal clock output)
Parameter
SCK2 cycle time
Symbol
tKCY7
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
SCK2 high-/low-level
width
tKH7,
tKL7
SI2 setup time
(to SCK2↑)
tSIK7
SI2 hold time
MIN.
TYP.
MAX.
Unit
800
ns
1600
ns
3200
ns
tKCY7/2 – 50
ns
tKCY7/2 – 100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
300
ns
400
ns
4.5 V ≤ VDD ≤ 6.0 V
tKSI7
(from SCK2↑)
SO0 output delay time
from SCK2↓
tKSO7
C = 100 pF Note
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK2 and SO2 output lines.
(ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter
SCK2 cycle time
Symbol
tKCY8
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
400
ns
SCK2 high-/low-level
tKH8,
4.5 V ≤ VDD ≤ 6.0 V
width
tKL8
2.7 V ≤ VDD < 4.5 V
800
ns
1600
ns
SI2 setup time
(to SCK2↑)
tSIK8
100
ns
SI2 hold time
(from SCK2↑)
tKSI8
400
ns
SO2 output delay time
from SCK2↓
tKSO8
SCK2 rise, fall time
tR8,
tF8
C = 100 pF Note
300
ns
1000
ns
Note C is the load capacitance of the SO2 output line.
49
µPD78064B(A)
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Transfer rate
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
78125
bps
2.7 V ≤ VDD < 4.5 V
39063
bps
19531
bps
MAX.
Unit
(iv) UART mode (External clock input)
Parameter
ASCK cycle time
Symbol
tKCY9
Test Conditions
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
400
ns
ASCK high-/low-level
tKH9,
4.5 V ≤ VDD ≤ 6.0 V
tKL9
2.7 V ≤ VDD < 4.5 V
ASCK rise, fall time
tR9,
tF9
50
TYP.
4.5 V ≤ VDD ≤ 6.0 V
width
Transfer rate
MIN.
800
ns
1600
ns
4.5 V ≤ VDD ≤ 6.0 V
39063
2.7 V ≤ VDD < 4.5 V
19531
bps
9766
bps
1000
ns
bps
µPD78064B(A)
AC Timing Test Point (Excluding X1, XT1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test Points
Clock Timing
1/fX
tXL
tXH
VIH3 (MIN.)
VIL3 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH4 (MIN.)
VIL4 (MAX.)
XT1 Input
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI1, TI2
51
µPD78064B(A)
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tRn
tFn
SCK0, SCK2
tSIKm
SI0, SI2
tKSIm
Input Data
tKSOm
SO0, SO2
Output Data
m = 1, 2, 7, 8
n = 2, 8
SBI mode (bus release signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tR4
tF4
SCK0
tKSB
tSBL
tSBK
tSBH
tSIK3, 4
tKSI3, 4
SB0, SB1
tKSO3, 4
SBI mode (command signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tR4
tF4
SCK0
tKSB
tSBK
tSIK3, 4
SB0, SB1
tKSO3, 4
52
tKSI3, 4
µPD78064B(A)
2-wire serial I/O mode:
tKCY5, 6
tKL5, 6
tKH5, 6
tR6
tF6
SCK0
tSIK5, 6
tKSI5, 6
tKSO5, 6
SB0, SB1
UART mode:
tKCY9
tKL9
tKH9
tR9
tF9
ASCK
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85°C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Symbol
Test Conditions
Resolution
Total error
MIN.
TYP.
MAX.
Unit
8
8
8
bit
±0.6
%
2.7 V ≤ AVREF ≤ 6.0 V
Note
Conversion time
tCONV
19.1
Sampling time
tSAMP
12/fXX
Analog input voltage
VIAN
AVSS
Reference voltage
AVREF
2.0
AVREF-AVSS resistance
RAIREF
4
±1.4
%
200
µs
µs
AVREF
AVDD
14
V
V
kΩ
Note Quantization error (±1/2 LSB) is not included. This is expressed in proportion to the full-scale value.
53
µPD78064B(A)
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85°C)
Parameter
Symbol
Data retention
supply voltage
VDDDR
Data retention
supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
tWAIT
wait time
Test Conditions
MIN.
TYP.
1.8
VDDDR = 1.8 V
Subsystem clock stopped and
feedback resistor disconnected
0.1
MAX.
Unit
6.0
V
10
µA
µs
0
Release by RESET
217/fX
ms
Release by interrupt
Note
ms
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSMS),
selection of 212/fXX and 214/fXX to 217/fXX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
54
µPD78064B(A)
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP5
RESET Input Timing
tRSL
RESET
55
µPD78064B(A)
11. PACKAGE DRAWINGS
100 PIN PLASTIC QFP (FINE PITCH) (
14)
A
B
75
76
51
50
F
Q
R
S
D
C
detail of lead end
26
25
100
1
G
H
I
M
J
M
P
K
N
L
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
16.0±0.2
B
14.0±0.2
0.630±0.008
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
16.0±0.2
0.630±0.008
F
G
1.0
1.0
0.039
0.039
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0±0.2
0.039 +0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.17 +0.03
–0.07
0.007 +0.001
–0.003
N
0.10
0.004
P
1.45
0.057
Q
0.125±0.075
0.005±0.003
R
S
5°±5°
1.7 MAX.
5°±5°
0.067 MAX.
P100GC-50-7EA-2
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
56
µPD78064B(A)
100 PIN PLASTIC LQFP (FINE PITCH) (14×14)
A
B
75
76
51
50
detail of lead end
S
C D
Q
R
26
25
100
1
F
G
H
I
M
J
K
P
M
N
NOTE
Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
L
ITEM
MILLIMETERS
INCHES
A
16.00±0.20
0.630±0.008
B
14.00±0.20
0.551 +0.009
–0.008
C
14.00±0.20
0.551 +0.009
–0.008
D
16.00±0.20
0.630±0.008
F
1.00
0.039
G
1.00
0.039
H
0.22 +0.05
–0.04
0.009±0.002
I
0.08
0.003
J
0.50 (T.P.)
0.020 (T.P.)
K
1.00±0.20
0.039 +0.009
–0.008
L
0.50±0.20
0.020 +0.008
–0.009
M
0.17 +0.03
–0.07
0.007 +0.001
–0.003
N
0.08
0.003
P
1.40±0.05
0.055±0.002
Q
0.10±0.05
0.004±0.002
R
3° +7°
–3°
3° +7°
–3°
S
1.60 MAX.
0.063 MAX.
S100GC-50-8EU
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
57
µPD78064B(A)
100 PIN PLASTIC QFP (14 x 20)
A
B
Q
F
G
H
I M
5°±5°
31
30
S
100
1
detail of lead end
D
51
50
C
80
81
J
M
P
K
N
L
P100GF-65-3BA1-2
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795 +0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
0.8
0.031
G
0.6
0.024
H
0.30 ± 0.10
0.012+0.004
–0.005
I
0.15
0.006
J
0.65 (T.P.)
0.026 (T.P.)
K
1.8 ± 0.2
0.071+0.008
–0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1 ± 0.1
0.004 ± 0.004
S
3.0 MAX.
0.119 MAX.
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
58
µPD78064B(A)
12. RECOMMENDED SOLDERING CONDITIONS
The µPD78064B(A) should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
(1) µPD78064BGC(A)-×××-7EA : 100-pin plastic QFP (Fine pitch) (14 × 14 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210°C or above),
Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125°C)
IR35-107-2
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above),
Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125°C)
VP15-107-2
Partial heating
Pin temperature: 300°C max. Duration: 3 sec. max. (per pin row)
—
(2) µPD78064BGF(A)-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
Number of times: 3 times max.
IR35-00-3
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above),
Number of times: 3 times max.
VP15-00-3
Wave soldering
Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once,
Preliminary heat temperature: 120°C max. (Package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max. Duration: 3 sec. max. (per pin row)
—
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH.
Cautions 1.
Use of more than one soldering method should be avoided (except in the case of partial
heating).
2.
Because the µPD78064BGC(A)-xxx-8EU is under development, its soldering condition is not
defined.
59
µPD78064B(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78064B(A).
Language Processing Software
RA78K/0
Notes 1, 2, 3, 4
78K/0 Series common assembler package
CC78K/0
Notes 1, 2, 3, 4
78K/0 Series common C compiler package
DF78064
Notes 1, 2, 3, 4
µPD78064 Subseries common device file
CC78K/0-L
Notes 1, 2, 3, 4
78K/0 Series common C compiler library source file
PROM Writing Tools
PG-1500
PROM programmer
PA-78P0308GC
(or PA-78P064GC)
PA-78P0308GF
(or PA-78P064GF)
Programmer adapters connected to PG-1500
PG-1500 controller
Notes 1, 2
PG-1500 control program
Debugging Tools
IE-78000-R
78K/0 Series common in-circuit emulator
IE-78000-R-A
78K/0 Series common in-circuit emulator (for integrated debugger)
IE-78000-R-BK
78K/0 Series common break board
IE-780308-R-EM
µPD780308 Subseries common emulation board
IE-78000-R-SV3
Interface adapter and cable (for IE-78000-R-A) when using EWS as a host machine
IE-70000-98-IF-B
Interface adapter (for IE-78000-R-A) when using PC-9800 Series (except notebook) as a host machine
IE-70000-98N-IF
Interface adapter and cable (for IE-78000-R-A) when using PC-9800 Series notebook as a host
machine
IE-70000-PC-IF-B
Interface adapter (for IE-78000-R-A) when using IBM PC/ATTM as a host machine
EP-78064GC-R
EP-78064GF-R
µPD78064 Subseries common emulation probes
TGC-100SDW
Adapter to be mounted on a target system board made for 100-pin plastic QFP (GC-7EA, GC-8EU)
Manufactured by TOKYO ELETECH Corporation. Contact on NEC sales representative to purchase.
EV-9200GF-100
SM78K0
ID78K0
60
Notes 5, 6, 7
Notes 4, 5, 6, 7
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA)
78K/0 Series common system simulator
IE-78000-R-A integrated debugger
SD78K/0
Notes 1, 2
IE-78000-R screen debugger
DF78064
Notes 1, 2, 4, 5, 6, 7
µPD78064 Subseries common device file
µPD78064B(A)
Real-Time OS
RX78K/0
MX78K0
Notes 1, 2, 3, 4
78K/0 series real-time OS
Notes 1, 2, 3, 4
78K/0 series OS
Fuzzy Inference Development Support System
FE9000
Note 1
FT9080
Note 1
FI78K0
, FE9200
Note 6
Fuzzy knowledge data creation tool
, FT9085
Note 2
Translator
Notes 1, 2
FD78K0
Notes 1, 2
Fuzzy inference module
Fuzzy inference debugger
Notes 1. PC-9800 Series (MS-DOSTM) based
2. IBM PC/AT and compatibles (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP 9000 Series 300TM (HP-UXTM) based
4. HP 9000 Series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS4800 Series (EWS-UX/V)
based
5. PC-9800 Series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
Remarks 1.
2.
For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78064.
61
µPD78064B(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document No
English
Japanese
U10785E
U10785J
This document
U11597J
µPD78P064B Data Sheet
U11598E
U11598J
78K/0 Series User’s Manual Instructions
µPD78064B Subseries User’s Manual
µPD78064B(A) Data Sheet
U12326E
U12326J
78K/0 Series Instruction Table
–
U10903J
78K/0 Series Instruction Set
–
U10904J
µPD78064B Subseries Special Function Register Table
–
Planned
Development Tool Related Documents (User’s Manual) (1/2)
Document Name
Document No
English
RA78K Series Assembler Package
Operation
EEU-1399
EEU-809
Language
EEU-1404
EEU-815
EEU-1402
EEU-817
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
Japanese
Operation
U11802E
U11802J
Assembly Language
U11801E
U11801J
Structured Assembly Language
U11789E
U11789J
Operation
EEU-1280
EEU-656
Language
EEU-1284
EEU-655
Operation
U11517E
U11517J
Language
U11518E
U11518J
Programming know-how
EEA-1208
EEA-618
–
U12322J
PG-1500 PROM Programmer
EEU-1335
EEU-651
PG-1500 Controller PC-9800 Series (MS-DOS) based
EEU-1291
EEU-704
PG-1500 Controller IBM PC Series (PC DOS) based
U10540E
EEU-5008
IE-78000-R
U11376E
U11376J
IE-78000-R-A
U10057E
U10057J
IE-78000-R-BK
EEU-1427
EEU-867
IE-780308-R-EM
U11362E
U11362J
EP-78064
EEU-1469
EEU-934
CC78K Series C Compiler
CC78K0 C Compiler
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
Caution The above related documents are subject to change without notice. Be sure to use the latest
documents when starting design.
62
µPD78064B(A)
Development Tool Related Documents (User’s Manual) (2/2)
Document Name
Document No
English
Japanese
SM78K0 System Simulator Windows based
Reference
U10181E
U10181J
SM78K Series System Simulator
External parts user open
interface specification
U10092E
U10092J
ID78K0 Integrated Debugger EWS based
Reference
–
U11151J
ID78K0 Integrated Debugger PC based
Reference
U11539E
U11539J
ID78K0 Integrated Debugger Windows based
Guide
U11649E
U11649J
SD78K/0 Screen Debugger
Introduction
U10539E
EEU-852
PC-9800 Series (MS-DOS) based
Reference
–
U10952J
SD78K/0 Screen Debugger
Introduction
EEU-1414
EEU-5024
IBM PC/AT (PC DOS) based
Reference
U11279E
U11279J
Embedded Software Related Documents (User’s Manual)
Document Name
Document No
English
Japanese
Basics
–
U11537J
Installation
–
U11536J
Basics
–
U12257J
Fuzzy Knowledge Data Creation Tool
EEU-1438
EEU-829
78K/0, 78K/II, 87AD Series
Fuzzy Inference Development Support System Translator
EEU-1444
EEU-862
78K/0 Series Fuzzy Inference Development Support System
Fuzzy Inference Module
EEU-1441
EEU-858
78K/0 Series Fuzzy Inference Development Support System
Fuzzy Inference Debugger
EEU-1458
EEU-921
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Other Related Documents
Document Name
Document No
English
Japanese
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C10531E
C10531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Electrostatic Discharge (ESD) Test
IEI-1201
MEM-539
Guide to Quality Assurance for Semiconductor Devices
MEI-1202
C11893J
–
U11416J
Microcomputer Product Series Guide
Caution The above related documents are subject to change without notice. Be sure to use the latest
documents when starting design.
63
µPD78064B(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
64
µPD78064B(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Mountain View, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby Sweden
Tel: 8-63 80 820
Fax: 8-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 3
65
µPD78064B(A)
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without
governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country
other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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